diff options
Diffstat (limited to 'libcpu/mips')
101 files changed, 4019 insertions, 14621 deletions
diff --git a/libcpu/mips/SConscript b/libcpu/mips/SConscript new file mode 100644 index 0000000000..5fca2b473b --- /dev/null +++ b/libcpu/mips/SConscript @@ -0,0 +1,19 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +group = [] +list = os.listdir(cwd) + +# add common code files +group = group + SConscript(os.path.join('common', 'SConscript')) + +# cpu porting code files +if rtconfig.CPU != 'common': + group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) + +Return('group') diff --git a/libcpu/mips/common/Kconfig b/libcpu/mips/common/Kconfig new file mode 100644 index 0000000000..a4dd748214 --- /dev/null +++ b/libcpu/mips/common/Kconfig @@ -0,0 +1,9 @@ +menu "RT-Thread MIPS CPU" + + config RT_USING_FPU + bool "Using Float Point Unit" + default n + help + Using Float Point Unit in code. + +endmenu diff --git a/libcpu/mips/common/SConscript b/libcpu/mips/common/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/mips/common/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/mips/common/asm.h b/libcpu/mips/common/asm.h index 190e8b110e..1b39eea05a 100644 --- a/libcpu/mips/common/asm.h +++ b/libcpu/mips/common/asm.h @@ -1,114 +1,112 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. + * Assembly Macros For MIPS * - * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle - * Copyright (C) 1999 by Silicon Graphics, Inc. - * Copyright (C) 2001 MIPS Technologies, Inc. - * Copyright (C) 2002 Maciej W. Rozycki + * Copyright (c) 2006-2019, RT-Thread Development Team * - * Some useful macros for MIPS assembler code + * SPDX-License-Identifier: Apache-2.0 * - * Some of the routines below contain useless nops that will be optimized - * away by gas in -O mode. These nops are however required to fill delay - * slots in noreorder mode. + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version */ + + #ifndef __ASM_H__ #define __ASM_H__ +#include <rtconfig.h> /* * LEAF - declare leaf routine */ #define LEAF(symbol) \ - .globl symbol; \ - .align 2; \ - .type symbol,@function; \ - .ent symbol,0; \ + .globl symbol; \ + .align 2; \ + .type symbol,@function; \ + .ent symbol,0; \ symbol: .frame sp,0,ra /* * NESTED - declare nested routine entry point */ #define NESTED(symbol, framesize, rpc) \ - .globl symbol; \ - .align 2; \ - .type symbol,@function; \ - .ent symbol,0; \ + .globl symbol; \ + .align 2; \ + .type symbol,@function; \ + .ent symbol,0; \ symbol: .frame sp, framesize, rpc /* * END - mark end of function */ #define END(function) \ - .end function; \ - .size function,.-function + .end function; \ + .size function,.-function /* * EXPORT - export definition of symbol */ #define EXPORT(symbol) \ - .globl symbol; \ + .globl symbol; \ symbol: /* * FEXPORT - export definition of a function symbol */ #define FEXPORT(symbol) \ - .globl symbol; \ - .type symbol,@function; \ + .globl symbol; \ + .type symbol,@function; \ symbol: /* * Global data declaration with size. */ #define EXPORTS(name,sz) \ - .globl name; \ - .type name,@object; \ - .size name,sz; \ + .globl name; \ + .type name,@object; \ + .size name,sz; \ name: /* * Weak data declaration with size. */ #define WEXPORT(name,sz) \ - .weakext name; \ - .type name,@object; \ - .size name,sz; \ + .weakext name; \ + .type name,@object; \ + .size name,sz; \ name: /* * Global data reference with size. */ #define IMPORT(name, size) \ - .extern name,size + .extern name,size /* * Global zeroed data. */ #define BSS(name,size) \ - .type name,@object; \ - .comm name,size + .type name,@object; \ + .comm name,size /* * Local zeroed data. */ #define LBSS(name,size) \ - .lcomm name,size + .lcomm name,size /* * ABS - export absolute symbol */ #define ABS(symbol,value) \ - .globl symbol; \ + .globl symbol; \ symbol = value #define TEXT(msg) \ - .pushsection .data; \ + .pushsection .data; \ 8: .asciiz msg; \ - .popsection; + .popsection; #define ENTRY(name) \ @@ -120,7 +118,94 @@ symbol = value /* * Macros to handle different pointer/register sizes for 32/64-bit code */ +#if defined ARCH_MIPS64 +/* + * Size of a register + */ +#define SZREG 8 + +/* + * Use the following macros in assemblercode to load/store registers, + * pointers etc. + */ +#define REG_S sd +#define REG_L ld +#define REG_SUBU dsubu +#define REG_ADDU daddu + +/* + * How to add/sub/load/store/shift C int variables. + */ +#define INT_ADD dadd +#define INT_ADDU daddu +#define INT_ADDI daddi +#define INT_ADDIU daddiu +#define INT_SUB dsub +#define INT_SUBU dsubu +#define INT_L ld +#define INT_S sd +#define INT_SLL dsll +#define INT_SLLV dsllv +#define INT_SRL dsrl +#define INT_SRLV dsrlv +#define INT_SRA dsra +#define INT_SRAV dsrav + +/* + * Use the following macros in assemblercode to load/store registers, + * pointers etc. + */ +#define LONG_ADD dadd +#define LONG_ADDU daddu +#define LONG_ADDI daddi +#define LONG_ADDIU daddiu +#define LONG_SUB dsub +#define LONG_SUBU dsubu +#define LONG_L ld +#define LONG_S sd +#define LONG_SP sdp +#define LONG_SLL dsll +#define LONG_SLLV dsllv +#define LONG_SRL dsrl +#define LONG_SRLV dsrlv +#define LONG_SRA dsra +#define LONG_SRAV dsrav + +#define LONG .dword +#define LONGSIZE 8 +#define LONGMASK 7 +#define LONGLOG 3 + +/* + * How to add/sub/load/store/shift pointers. + */ +#define PTR_ADD dadd +#define PTR_ADDU daddu +#define PTR_ADDI daddi +#define PTR_ADDIU daddiu +#define PTR_SUB dsub +#define PTR_SUBU dsubu +#define PTR_L ld +#define PTR_S sd +#define PTR_LA dla +#define PTR_LI dli +#define PTR_SLL dsll +#define PTR_SLLV dsllv +#define PTR_SRL dsrl +#define PTR_SRLV dsrlv +#define PTR_SRA dsra +#define PTR_SRAV dsrav + +#define PTR_SCALESHIFT 3 + +#define PTR .dword +#define PTRSIZE 8 +#define PTRLOG 3 + +#define MFC0 dmfc0 +#define MTC0 dmtc0 +#else /* * Size of a register */ @@ -214,6 +299,7 @@ symbol = value #define MFC0 mfc0 #define MTC0 mtc0 +#endif #define SSNOP sll zero, zero, 1 diff --git a/libcpu/mips/common/cache.h b/libcpu/mips/common/cache.h deleted file mode 100644 index 1c7cf41324..0000000000 --- a/libcpu/mips/common/cache.h +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Cache operations for the cache instruction. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle - * (C) Copyright 1999 Silicon Graphics, Inc. - */ -#ifndef __CACHE_H__ -#define __CACHE_H__ - - -#define KUSEG 0x00000000 -#define KSEG0 0x80000000 -#define KSEG1 0xa0000000 -#define KSEG2 0xc0000000 -#define KSEG3 0xe0000000 - -/* - * Cache Operations available on all MIPS processors with R4000-style caches - */ -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 - -#define Hit_Invalidate_I 0x10 -#define Hit_Invalidate_D 0x11 -#define Hit_Writeback_Inv_D 0x15 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 - -/* - *The lock state is cleared by executing an Index -Invalidate, Index Writeback Invalidate, Hit -Invalidate, or Hit Writeback Invalidate -operation to the locked line, or via an Index -Store Tag operation with the lock bit reset in -the TagLo register. - */ -#define Fetch_And_Lock_I 0x1c -#define Fetch_And_Lock_D 0x1d -/* - * R4000-specific cacheops - */ -#define Create_Dirty_Excl_D 0x0d -#define Fill 0x14 - -/* - * R4000SC and R4400SC-specific cacheops - */ -#define Index_Invalidate_SI 0x02 -#define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_SD 0x1b -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f - -/* - * R5000-specific cacheops - */ -#define R5K_Page_Invalidate_S 0x17 - -/* - * RM7000-specific cacheops - */ -#define Page_Invalidate_T 0x16 - -/* - * R1000-specific cacheops - * - * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. - * Most of the _S cacheops are identical to the R4000SC _SD cacheops. - */ -#define Index_Writeback_Inv_S 0x03 -#define Index_Load_Tag_S 0x07 -#define Index_Store_Tag_S 0x0B -#define Hit_Invalidate_S 0x13 -#define Cache_Barrier 0x14 -#define Hit_Writeback_Inv_S 0x17 -#define Index_Load_Data_I 0x18 -#define Index_Load_Data_D 0x19 -#define Index_Load_Data_S 0x1b -#define Index_Store_Data_I 0x1c -#define Index_Store_Data_D 0x1d -#define Index_Store_Data_S 0x1f - - -#ifndef __ASSEMBLER__ - -#ifndef dcache_size -#define dcache_size (g_mips_core.dcache_ways * g_mips_core.dcache_lines_per_way * g_mips_core.dcache_line_size) -#endif - -#ifndef icache_size -#define icache_size (g_mips_core.dcache_ways * g_mips_core.dcache_lines_per_way * g_mips_core.dcache_line_size) -#endif - -#ifndef cpu_dcache_line_size -#define cpu_dcache_line_size() g_mips_core.icache_line_size -#endif - -#ifndef cpu_icache_line_size -#define cpu_icache_line_size() g_mips_core.icache_line_size -#endif - -#define cache_op(op, addr) \ - __asm__ __volatile__( \ - " .set noreorder \n" \ - " .set mips3\n\t \n" \ - " cache %0, %1 \n" \ - " .set mips0 \n" \ - " .set reorder" \ - : \ - : "i" (op), "m" (*(unsigned char *)(addr))) - -#define cache16_unroll32(base, op) \ - __asm__ __volatile__( \ - " .set noreorder \n" \ - " .set mips3 \n" \ - " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \ - " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \ - " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \ - " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \ - " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \ - " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \ - " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \ - " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \ - " cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \ - " cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \ - " cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \ - " cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \ - " cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \ - " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \ - " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \ - " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \ - " .set mips0 \n" \ - " .set reorder \n" \ - : \ - : "r" (base), \ - "i" (op)); - - -static inline void flush_icache_line_indexed(rt_ubase_t addr) -{ - cache_op(Index_Invalidate_I, addr); -} - -static inline void flush_dcache_line_indexed(rt_ubase_t addr) -{ - cache_op(Index_Writeback_Inv_D, addr); -} - -static inline void flush_icache_line(rt_ubase_t addr) -{ - cache_op(Hit_Invalidate_I, addr); -} - -static inline void lock_icache_line(rt_ubase_t addr) -{ - cache_op(Fetch_And_Lock_I, addr); -} - -static inline void lock_dcache_line(rt_ubase_t addr) -{ - cache_op(Fetch_And_Lock_D, addr); -} - -static inline void flush_dcache_line(rt_ubase_t addr) -{ - cache_op(Hit_Writeback_Inv_D, addr); -} - -static inline void invalidate_dcache_line(rt_ubase_t addr) -{ - cache_op(Hit_Invalidate_D, addr); -} - -static inline void blast_dcache16(void) -{ - rt_ubase_t start = KSEG0; - rt_ubase_t end = start + dcache_size; - rt_ubase_t addr; - - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr, Index_Writeback_Inv_D); -} - -static inline void inv_dcache16(void) -{ - rt_ubase_t start = KSEG0; - rt_ubase_t end = start + dcache_size; - rt_ubase_t addr; - - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr, Hit_Invalidate_D); -} - -static inline void blast_icache16(void) -{ - rt_ubase_t start = KSEG0; - rt_ubase_t end = start + icache_size; - rt_ubase_t addr; - - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr, Index_Invalidate_I); -} - - - -void r4k_cache_init(void); -void r4k_cache_flush_all(void); -void r4k_icache_flush_all(void); -void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size); -void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size); -void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size); -void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size); - -#endif /*end of __ASSEMBLER__ */ - -#endif /* end of __CACHE_H__ */ diff --git a/libcpu/mips/common/context_gcc.S b/libcpu/mips/common/context_gcc.S new file mode 100644 index 0000000000..3fdbe374c9 --- /dev/null +++ b/libcpu/mips/common/context_gcc.S @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + * 2020-07-26 lizhirui Fixed some problems + */ + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ +#endif + +#include "mips_regs.h" +#include "stackframe.h" + + .section ".text", "ax" + .set noreorder + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) + * a0 --> from + * a1 --> to + */ + .globl rt_hw_context_switch +rt_hw_context_switch: + MTC0 ra, CP0_EPC + SAVE_ALL + + REG_S sp, 0(a0) /* store sp in preempted tasks TCB */ + REG_L sp, 0(a1) /* get new task stack pointer */ + + RESTORE_ALL_AND_RET + +/* + * void rt_hw_context_switch_to(rt_uint32 to)/* + * a0 --> to + */ + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + REG_L sp, 0(a0) /* get new task stack pointer */ + RESTORE_ALL_AND_RET + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* + */ + .globl rt_thread_switch_interrupt_flag + .globl rt_interrupt_from_thread + .globl rt_interrupt_to_thread + .globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + PTR_LA t0, rt_thread_switch_interrupt_flag + REG_L t1, 0(t0) + nop + bnez t1, _reswitch + nop + li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ + LONG_S t1, 0(t0) + PTR_LA t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ + LONG_S a0, 0(t0) +_reswitch: + PTR_LA t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ + LONG_S a1, 0(t0) + jr ra + nop + +/* + * void rt_hw_context_switch_interrupt_do(rt_base_t flag) + */ + .globl rt_interrupt_enter + .globl rt_interrupt_leave + .globl rt_general_exc_dispatch + .globl mips_irq_handle +mips_irq_handle: + SAVE_ALL + + /* let k0 keep the current context sp */ + move k0, sp + /* switch to kernel stack */ + PTR_LA sp, _system_stack + + jal rt_interrupt_enter + nop + /* Get Old SP from k0 as paremeter in a0 */ + move a0, k0 + jal rt_general_exc_dispatch + nop + jal rt_interrupt_leave + nop + + /* switch sp back to thread context */ + move sp, k0 + + /* + * if rt_thread_switch_interrupt_flag set, jump to + * rt_hw_context_switch_interrupt_do and do not return + */ + PTR_LA k0, rt_thread_switch_interrupt_flag + LONG_L k1, 0(k0) + beqz k1, spurious_interrupt + nop + LONG_S zero, 0(k0) /* clear flag */ + nop + + /* + * switch to the new thread + */ + PTR_LA k0, rt_interrupt_from_thread + LONG_L k1, 0(k0) + nop + LONG_S sp, 0(k1) /* store sp in preempted task TCB */ + + PTR_LA k0, rt_interrupt_to_thread + LONG_L k1, 0(k0) + nop + LONG_L sp, 0(k1) /* get new task stack pointer */ + j spurious_interrupt + nop + +spurious_interrupt: + RESTORE_ALL_AND_RET + .set reorder diff --git a/libcpu/mips/common/entry_gcc.S b/libcpu/mips/common/entry_gcc.S new file mode 100644 index 0000000000..d1a0704809 --- /dev/null +++ b/libcpu/mips/common/entry_gcc.S @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + */ + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ +#endif + +#include <mips.h> +#include <rtconfig.h> + +#include "asm.h" +#include <rtconfig.h> + + .section ".start", "ax" + .set noreorder + + /* the program entry */ + .globl _rtthread_entry +_rtthread_entry: +#ifndef RT_USING_SELF_BOOT + .globl _start +_start: +#endif + PTR_LA ra, _rtthread_entry + + /* disable interrupt */ + MTC0 zero, CP0_CAUSE + MTC0 zero, CP0_STATUS # Set CPU to disable interrupt. + ehb + +#ifdef ARCH_MIPS64 + dli t0, ST0_KX + MTC0 t0, CP0_STATUS +#endif + + /* setup stack pointer */ + PTR_LA sp, _system_stack + PTR_LA gp, _gp + + bal rt_cpu_early_init + nop + + /* clear bss */ + PTR_LA t0, __bss_start + PTR_LA t1, __bss_end + +_clr_bss_loop: + sw zero, 0(t0) + bne t1, t0, _clr_bss_loop + addu t0, 4 + /* jump to RT-Thread RTOS */ + jal rtthread_startup + nop + + /* restart, never die */ + j _start + nop diff --git a/libcpu/mips/common/exception.c b/libcpu/mips/common/exception.c new file mode 100644 index 0000000000..3da8ecead6 --- /dev/null +++ b/libcpu/mips/common/exception.c @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + */ + +#include <rtthread.h> +#include <rthw.h> +#include "exception.h" +#include "mips_regs.h" + +/** + * @addtogroup MIPS + */ + +/*@{*/ + +extern rt_ubase_t __ebase_entry; +rt_ubase_t rt_interrupt_from_thread; +rt_ubase_t rt_interrupt_to_thread; +rt_ubase_t rt_thread_switch_interrupt_flag; + +const char *exception_name[] = { + "Interrupt", + "(X)TLB Modify Exception", + "(X)TLB Read/Fetch Exception", + "(X)TLB Write Exception", + "Address Read/Fetch Exception", + "Address Write Exception", + "", + "", + "Syscall", + "Breakpoint", + "Reversed Instruction Exception", + "Coprocessor Unit Invalid", + "Overflow", + "Trap", + "FPU Exception in Vector Instruction", + "FPU Exception", + "Loongson Custom Exception", + "", + "", + "(X)TLB Read Denied Exception", + "(X)TLB Execute Denied Exception", + "Vector Module Disabled Exception", + "", + "", + "", + "", + "", + "", + "", + "", + "Cache Error Exception", + "" + }; + +rt_base_t rt_hw_interrupt_disable(void) +{ + rt_base_t status = read_c0_status(); + clear_c0_status(ST0_IE); + return status; +} + +void rt_hw_interrupt_enable(rt_base_t level) +{ + write_c0_status(level); +} + +/** + * exception handle table + */ +#define RT_EXCEPTION_MAX 32 +exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX]; + +/** + * setup the exception handle + */ +exception_func_t rt_set_except_vector(int n, exception_func_t func) +{ + exception_func_t old_handler = sys_exception_handlers[n]; + + if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func)) + { + return 0; + } + + sys_exception_handlers[n] = func; + + return old_handler; +} + +void mips_dump_regs(struct pt_regs *regs) +{ + int i, j; + for (i = 0; i < 32 / 4; i++) + { + for (j = 0; j < 4; j++) + { + int reg = 4 * i + j; + rt_kprintf("%d: 0x%08x, ", reg, regs->regs[reg]); + } + rt_kprintf("\n"); + } +} + +void tlb_refill_handler(void) +{ + rt_kprintf("TLB-Miss Happens, EPC: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); +} + +void cache_error_handler(void) +{ + rt_kprintf("Cache Exception Happens, EPC: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); +} + +static void unhandled_exception_handle(struct pt_regs *regs) +{ + rt_kprintf("Unknown Exception, EPC: 0x%p, CAUSE: 0x%08x\n", read_c0_epc(), read_c0_cause()); + rt_kprintf("Exception Name:%s\n",exception_name[(read_c0_cause() >> 2) & 0x1f]); +#ifdef SOC_LS2K1000 + rt_kprintf("ExeCode = 0x%08x,BadAddr = 0x%p\n",(read_c0_cause() >> 2) & 0x1f,mmu_tlb_get_bad_vaddr()); +#else + rt_kprintf("ExeCode = 0x%08x\n",(read_c0_cause() >> 2) & 0x1f); +#endif + rt_kprintf("ST0: 0x%08x ",regs->cp0_status); + rt_kprintf("ErrorPC: 0x%p\n",read_c0_errorepc()); + mips_dump_regs(regs); + rt_hw_cpu_shutdown(); +} + +static void install_default_exception_handler(void) +{ + rt_int32_t i; + + for (i = 0; i < RT_EXCEPTION_MAX; i++) + sys_exception_handlers[i] = + (exception_func_t)unhandled_exception_handle; +} + +int rt_hw_exception_init(void) +{ + rt_ubase_t ebase = (rt_ubase_t)&__ebase_entry; +#ifdef ARCH_MIPS64 + ebase |= 0xffffffff00000000; +#endif + write_c0_ebase(ebase); + clear_c0_status(ST0_BEV | ST0_ERL | ST0_EXL); + clear_c0_status(ST0_IM | ST0_IE); + set_c0_status(ST0_CU0); + /* install the default exception handler */ + install_default_exception_handler(); + + return RT_EOK; +} + +void rt_general_exc_dispatch(struct pt_regs *regs) +{ + rt_ubase_t cause, exccode; + cause = read_c0_cause(); + exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; + + if (exccode == 0) + { + rt_ubase_t status, pending; + + status = read_c0_status(); + pending = (cause & CAUSEF_IP) & (status & ST0_IM); + if (pending & CAUSEF_IP0) + rt_do_mips_cpu_irq(0); + if (pending & CAUSEF_IP1) + rt_do_mips_cpu_irq(1); + if (pending & CAUSEF_IP2) + rt_do_mips_cpu_irq(2); + if (pending & CAUSEF_IP3) + rt_do_mips_cpu_irq(3); + if (pending & CAUSEF_IP4) + rt_do_mips_cpu_irq(4); + if (pending & CAUSEF_IP5) + rt_do_mips_cpu_irq(5); + if (pending & CAUSEF_IP6) + rt_do_mips_cpu_irq(6); + if (pending & CAUSEF_IP7) + rt_do_mips_cpu_irq(7); + } + else + { + if (sys_exception_handlers[exccode]) + sys_exception_handlers[exccode](regs); + } +} + +/* Mask means disable the interrupt */ +void mips_mask_cpu_irq(rt_uint32_t irq) +{ + clear_c0_status(1 << (STATUSB_IP0 + irq)); +} + +/* Unmask means enable the interrupt */ +void mips_unmask_cpu_irq(rt_uint32_t irq) +{ + set_c0_status(1 << (STATUSB_IP0 + irq)); +} + +/*@}*/ diff --git a/libcpu/mips/common/exception.h b/libcpu/mips/common/exception.h index 2cb03d20e7..68107f6235 100644 --- a/libcpu/mips/common/exception.h +++ b/libcpu/mips/common/exception.h @@ -1,166 +1,28 @@ /* - * File : cpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team + * Copyright (c) 2006-2019, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2010-05-17 swkyer first version + * 2019-12-04 Jiaxun Yang Initial version */ + #ifndef __EXCEPTION_H__ #define __EXCEPTION_H__ +#include "ptrace.h" -/* - * important register numbers - */ -#define REG_EPC 37 -#define REG_FP 72 -#define REG_SP 29 - -/* - * Stack layout for the GDB exception handler - * Derived from the stack layout described in asm-mips/stackframe.h - * - * The first PTRSIZE*6 bytes are argument save space for C subroutines. - */ -#define NUMREGS 90 - -#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */ -#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */ -#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */ -#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */ -#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */ -#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */ -#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */ -#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */ -#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */ -#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */ -#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */ -#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */ -#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */ -#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */ -#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */ -#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */ -#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */ -#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */ -#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */ -#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */ -#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */ -#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */ -#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */ -#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */ -#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */ -#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */ -#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */ -#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */ -#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */ -#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */ -#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */ -#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */ - -/* - * Saved special registers - */ -#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */ -#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */ -#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */ -#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */ -#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */ -#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */ - -///* -// * Saved floating point registers -// */ -//#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */ -//#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */ -//#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */ -//#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */ -//#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */ -//#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */ -//#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */ -//#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */ -//#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */ -//#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */ -//#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */ -//#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */ -//#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */ -//#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */ -//#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */ -//#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */ -//#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */ -//#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */ -//#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */ -//#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */ -//#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */ -//#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */ -//#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */ -//#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */ -//#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */ -//#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */ -//#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */ -//#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */ -//#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */ -//#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */ -//#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */ -//#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */ -// -//#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */ -//#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */ -//#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */ -// -//#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */ -// -///* -// * Again, CP0 registers -// */ -//#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */ -#define GDB_FR_FRP ((GDB_FR_EPC) + LONGSIZE) /* 72 */ -#define GDB_FR_CP0_INDEX ((GDB_FR_FRP) + LONGSIZE) /* 74 */ - -#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */ -#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */ -#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */ -#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */ -#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */ -#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */ -#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */ -#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */ -#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */ -#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */ -#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */ -#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */ -#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */ -#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */ -#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */ - -#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1)) - -/* - * This is the same as above, but for the high-level - * part of the INT stub. - */ -typedef struct pt_regs_s -{ - /* Saved main processor registers. */ - rt_base_t regs[32]; - /* Saved special registers. */ - rt_base_t cp0_status; - rt_base_t hi; - rt_base_t lo; - rt_base_t cp0_badvaddr; - rt_base_t cp0_cause; - rt_base_t cp0_epc; -} pt_regs_t; +#ifndef __ASSEMBLY__ -typedef void (* exception_func_t)(pt_regs_t *regs); +typedef void (* exception_func_t)(struct pt_regs *regs); +extern int rt_hw_exception_init(void); extern exception_func_t sys_exception_handlers[]; +extern void rt_do_mips_cpu_irq(rt_uint32_t ip); exception_func_t rt_set_except_vector(int n, exception_func_t func); -void install_default_execpt_handle(void); +extern void mips_mask_cpu_irq(rt_uint32_t irq); +extern void mips_unmask_cpu_irq(rt_uint32_t irq); +#endif #endif /* end of __EXCEPTION_H__ */ diff --git a/libcpu/mips/common/exception_gcc.S b/libcpu/mips/common/exception_gcc.S new file mode 100644 index 0000000000..c685928a84 --- /dev/null +++ b/libcpu/mips/common/exception_gcc.S @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + * 2020-07-26 lizhirui Add xtlb exception entry + */ +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ +#endif + +#include <mips.h> + + .section ".exc_vectors", "ax" + .extern tlb_refill_handler + .extern cache_error_handler + .extern mips_irq_handle + + /* 0x0 - TLB refill handler */ + .global tlb_refill_exception + .type tlb_refill_exception,@function +ebase_start: +tlb_refill_exception: + b _general_exception_handler + nop + + /* 0x080 - XTLB refill handler */ + .org ebase_start + 0x080 + b _general_exception_handler + nop + + /* 0x100 - Cache error handler */ + .org ebase_start + 0x100 + j cache_error_handler + nop + + /* 0x180 - Exception/Interrupt handler */ + .global general_exception + .type general_exception,@function + .org ebase_start + 0x180 +general_exception: + b _general_exception_handler + nop + + /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */ + .global irq_exception + .type irq_exception,@function + .org ebase_start + 0x200 +irq_exception: + b _general_exception_handler + nop + + /* general exception handler */ +_general_exception_handler: + .set noreorder + PTR_LA k0, mips_irq_handle + jr k0 + nop + .set reorder + + /* interrupt handler */ +_irq_handler: + .set noreorder + PTR_LA k0, mips_irq_handle + jr k0 + nop + .set reorder diff --git a/libcpu/mips/common/mips.h b/libcpu/mips/common/mips.h index 6a9811ae7e..94f664308c 100644 --- a/libcpu/mips/common/mips.h +++ b/libcpu/mips/common/mips.h @@ -1,39 +1,23 @@ /* - * File : mips.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2019, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2016��9��7�� Urey the first version + * 2016-09-07 Urey first version */ #ifndef _COMMON_MIPS_H_ #define _COMMON_MIPS_H_ #include "mips_cfg.h" - +#include "ptrace.h" #include "mips_types.h" -#include "mips_asm.h" -#include "mips_def.h" +#include "asm.h" #include "mips_regs.h" #include "mips_addrspace.h" #include "mips_cache.h" -#include "mips_context.h" -#include "mips_excpt.h" +#include "exception.h" #endif /* _COMMON_MIPS_H_ */ diff --git a/libcpu/mips/common/mips_addrspace.h b/libcpu/mips/common/mips_addrspace.h index 3b82a4e371..f3bb60662e 100644 --- a/libcpu/mips/common/mips_addrspace.h +++ b/libcpu/mips/common/mips_addrspace.h @@ -1,25 +1,11 @@ /* - * File : mips_addrspace.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2019, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2016��9��12�� Urey the first version + * 2019-12-04 Jiaxun Yang Initial version */ #ifndef _MIPS_ADDRSPACE_H_ @@ -38,7 +24,7 @@ #define _ATYPE_ __PTRDIFF_TYPE__ #define _ATYPE32_ int #define _ATYPE64_ __s64 -#ifdef CONFIG_64BIT +#ifdef ARCH_MIPS64 #define _CONST64_(x) x ## L #else #define _CONST64_(x) x ## LL @@ -68,7 +54,7 @@ #define XPHYSADDR(a) ((_ACAST64_(a)) & \ _CONST64_(0x000000ffffffffff)) -#ifdef CONFIG_64BIT +#ifdef ARCH_MIPS64 /* * Memory segments (64bit kernel mode addresses) @@ -89,6 +75,12 @@ #define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) #define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) +#define KUSEGBASE 0xffffffff00000000 +#define KSEG0BASE 0xffffffff80000000 +#define KSEG1BASE 0xffffffffa0000000 +#define KSEG2BASE 0xffffffffc0000000 +#define KSEG3BASE 0xffffffffe0000000 + #else #define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE) @@ -104,24 +96,25 @@ #define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE) #define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE) -/* - * Memory segments (32bit kernel mode addresses) - * These are the traditional names used in the 32-bit universe. - */ -//#define KUSEGBASE 0x00000000 -//#define KSEG0BASE 0x80000000 -//#define KSEG1BASE 0xa0000000 -//#define KSEG2BASE 0xc0000000 -//#define KSEG3BASE 0xe0000000 - #define CKUSEG 0x00000000 #define CKSEG0 0x80000000 #define CKSEG1 0xa0000000 #define CKSEG2 0xc0000000 #define CKSEG3 0xe0000000 +/* + * Memory segments (32bit kernel mode addresses) + * These are the traditional names used in the 32-bit universe. + */ +#define KUSEGBASE 0x00000000 +#define KSEG0BASE 0x80000000 +#define KSEG1BASE 0xa0000000 +#define KSEG2BASE 0xc0000000 +#define KSEG3BASE 0xe0000000 + #endif + /* * Cache modes for XKPHYS address conversion macros */ @@ -147,14 +140,6 @@ * Returns the uncached address of a sdram address */ #ifndef __ASSEMBLY__ -#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229) -/* We use a 36 bit physical address map here and - cannot access physical memory directly from core */ -#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000) -#else /* !CONFIG_SOC_AU1X00 */ -#define UNCACHED_SDRAM(a) CKSEG1ADDR(a) -#endif /* CONFIG_SOC_AU1X00 */ -#endif /* __ASSEMBLY__ */ /* * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting @@ -162,46 +147,19 @@ * R8000 implements most with its 48-bit physical address space. */ #define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ - -#ifndef CONFIG_CPU_R8000 - -/* - * The R8000 doesn't have the 32-bit compat spaces so we don't define them - * in order to catch bugs in the source code. - */ - #define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000) #define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ -#endif - #define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK) #define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE) +#endif #ifndef __ASSEMBLY__ -/* - * Change virtual addresses to physical addresses and vv. - * These are trivial on the 1:1 Linux/MIPS mapping - */ -static inline phys_addr_t virt_to_phys(volatile void * address) -{ -#ifndef CONFIG_64BIT - return CPHYSADDR(address); -#else - return XPHYSADDR(address); +#define REG8( addr ) (*(volatile u8 *) (addr)) +#define REG16( addr ) (*(volatile u16 *)(addr)) +#define REG32( addr ) (*(volatile u32 *)(addr)) +#define REG64( addr ) (*(volatile u64 *)(addr)) #endif -} - -static inline void * phys_to_virt(unsigned long address) -{ -#ifndef CONFIG_64BIT - return (void *)KSEG0ADDR(address); -#else - return (void *)CKSEG0ADDR(address); -#endif -} -#endif - #endif /* _MIPS_ADDRSPACE_H_ */ diff --git a/libcpu/mips/common/mips_asm.h b/libcpu/mips/common/mips_asm.h deleted file mode 100644 index 8f97e370ab..0000000000 --- a/libcpu/mips/common/mips_asm.h +++ /dev/null @@ -1,447 +0,0 @@ -/* - * File : mips_asm.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��7�� Urey the first version - */ - -#ifndef _MIPS_ASM_H_ -#define _MIPS_ASM_H_ - - -/* ********************************************************************* */ -/* Interface macro & data definition */ - -#ifdef __ASSEMBLY__ - -/******** ASSEMBLER SPECIFIC DEFINITIONS ********/ - -#ifdef __ghs__ -#define ALIGN(x) .##align (1 << (x)) -#else -#define ALIGN(x) .##align (x) -#endif - -#ifdef __ghs__ -#define SET_MIPS3() -#define SET_MIPS0() -#define SET_PUSH() -#define SET_POP() -#else -#define SET_MIPS3() .##set mips3 -#define SET_MIPS0() .##set mips0 -#define SET_PUSH() .##set push -#define SET_POP() .##set pop -#endif - -/* Different assemblers have different requirements for how to - * indicate that the next section is bss : - * - * Some use : .bss - * Others use : .section bss - * - * We select which to use based on _BSS_OLD_, which may be defined - * in makefile. - */ -#ifdef _BSS_OLD_ -#define BSS .##section bss -#else -#define BSS .##bss -#endif - -#define LEAF(name)\ - .##text;\ - .##globl name;\ - .##ent name;\ -name: - - -#define SLEAF(name)\ - .##text;\ - .##ent name;\ -name: - - -#ifdef __ghs__ -#define END(name)\ - .##end name -#else -#define END(name)\ - .##size name,.-name;\ - .##end name -#endif - - -#define EXTERN(name) - -#else - -#define U64 unsigned long long -#define U32 unsigned int -#define U16 unsigned short -#define U8 unsigned char -#define S64 signed long long -#define S32 int -#define S16 short int -#define S8 signed char -//#define bool U8 - -#ifndef _SIZE_T_ -#define _SIZE_T_ -#ifdef __ghs__ - typedef unsigned int size_t; -#else - typedef unsigned long size_t; -#endif -#endif - -/* Sets the result on bPort */ -#define BIT_SET(bPort,bBitMask) (bPort |= bBitMask) -#define BIT_CLR(bPort,bBitMask) (bPort &= ~bBitMask) - -/* Returns the result */ -#define GET_BIT_SET(bPort,bBitMask) (bPort | bBitMask) -#define GET_BIT_CLR(bPort,bBitMask) (bPort & ~bBitMask) - -/* Returns 0 if the condition is False & a non-zero value if it is True */ -#define TEST_BIT_SET(bPort,bBitMask) (bPort & bBitMask) -#define TEST_BIT_CLR(bPort,bBitMask) ((~bPort) & bBitMask) - -/* Split union definitions */ -typedef union tunSU16 -{ - U16 hwHW; - struct tst2U8 - { - U8 bB0; - U8 bB1; - }st2U8; -}tunSU16; - -typedef union tunSU32 -{ - U32 wW; - struct tst2U16 - { - U16 hwHW0; - U16 hwHW1; - }st2U16; - struct tst4U8 - { - U8 bB0; - U8 bB1; - U8 bB2; - U8 bB3; - }st4U8; -}tunSU32; - -#endif /* #ifdef __ASSEMBLY__ */ - - -/******** DEFINITIONS FOR BOTH ASSEMBLER AND C ********/ - - -#define NO_ERR 0x00000000 /* operation completed successfully */ -#define ERR 0xffffffff /* operation completed not successfully */ - -#define False 0 -#define True !False - -#ifndef NULL -#define NULL ((void *)0) -#endif//NULL - -#ifndef MIN -#define MIN(x,y) ((x) < (y) ? (x) : (y)) -#endif//MIN - -#ifndef MAX -#define MAX(x,y) ((x) > (y) ? (x) : (y)) -#endif//MAX - -#define MAXUINT(w) (\ - ((w) == sizeof(U8)) ? 0xFFU :\ - ((w) == sizeof(U16)) ? 0xFFFFU :\ - ((w) == sizeof(U32)) ? 0xFFFFFFFFU : 0\ - ) - -#define MAXINT(w) (\ - ((w) == sizeof(S8)) ? 0x7F :\ - ((w) == sizeof(S16)) ? 0x7FFF :\ - ((w) == sizeof(S32)) ? 0x7FFFFFFF : 0\ - ) - -#define MSK(n) ((1 << (n)) - 1) - -#define KUSEG_MSK 0x80000000 -#define KSEG_MSK 0xE0000000 - -#define KUSEGBASE 0x00000000 -#define KSEG0BASE 0x80000000 -#define KSEG1BASE 0xA0000000 -#define KSSEGBASE 0xC0000000 -#define KSEG3BASE 0xE0000000 - -/* Below macros perform the following functions : - * - * KSEG0 : Converts KSEG0/1 or physical addr (below 0.5GB) to KSEG0. - * KSEG1 : Converts KSEG0/1 or physical addr (below 0.5GB) to KSEG1. - * PHYS : Converts KSEG0/1 or physical addr (below 0.5GB) to physical address. - * KSSEG : Not relevant for converting, but used for determining range. - * KSEG3 : Not relevant for converting, but used for determining range. - * KUSEG : Not relevant for converting, but used for determining range. - * KSEG0A : Same as KSEG0 but operates on register rather than constant. - * KSEG1A : Same as KSEG1 but operates on register rather than constant. - * PHYSA : Same as PHYS but operates on register rather than constant. - * CACHED : Alias for KSEG0 macro . - * (Note that KSEG0 cache attribute is determined by K0 - * field of Config register, but this is typically cached). - * UNCACHED : Alias for KSEG1 macro . - */ -#ifdef __ASSEMBLY__ -#define KSEG0(addr) (((addr) & ~KSEG_MSK) | KSEG0BASE) -#define KSEG1(addr) (((addr) & ~KSEG_MSK) | KSEG1BASE) -#define KSSEG(addr) (((addr) & ~KSEG_MSK) | KSSEGBASE) -#define KSEG3(addr) (((addr) & ~KSEG_MSK) | KSEG3BASE) -#define KUSEG(addr) (((addr) & ~KUSEG_MSK) | KUSEGBASE) -#define PHYS(addr) ( (addr) & ~KSEG_MSK) -#define KSEG0A(reg) and reg, ~KSEG_MSK; or reg, KSEG0BASE -#define KSEG1A(reg) and reg, ~KSEG_MSK; or reg, KSEG1BASE -#define PHYSA(reg) and reg, ~KSEG_MSK -#else -#define KSEG0(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG0BASE) -#define KSEG1(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG1BASE) -#define KSSEG(addr) (((U32)(addr) & ~KSEG_MSK) | KSSEGBASE) -#define KSEG3(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG3BASE) -#define KUSEG(addr) (((U32)(addr) & ~KUSEG_MSK) | KUSEGBASE) -#define PHYS(addr) ((U32)(addr) & ~KSEG_MSK) -#endif - -#define CACHED(addr) KSEG0(addr) -#define UNCACHED(addr) KSEG1(addr) - - -#ifdef __ASSEMBLY__ -/* Macroes to access variables at constant addresses - * Compensates for signed 16 bit displacement - * Typical use: li a0, HIKSEG1(ATLAS_ASCIIWORD) - * sw v1, LO_OFFS(ATLAS_ASCIIWORD)(a0) - */ -#define HIKSEG0(addr) ((KSEG0(addr) + 0x8000) & 0xffff0000) -#define HIKSEG1(addr) ((KSEG1(addr) + 0x8000) & 0xffff0000) -#define HI_PART(addr) (((addr) + 0x8000) & 0xffff0000) -#define LO_OFFS(addr) ((addr) & 0xffff) -#endif - - -/* Most/Least significant 32 bit from 64 bit double word */ -#define HI32(data64) ((U32)(data64 >> 32)) -#define LO32(data64) ((U32)(data64 & 0xFFFFFFFF)) - -#if ((!defined(__ASSEMBLY__)) && (!defined(__LANGUAGE_ASSEMBLY))) -#define REG8( addr ) (*(volatile U8 *) (addr)) -#define REG16( addr ) (*(volatile U16 *)(addr)) -#define REG32( addr ) (*(volatile U32 *)(addr)) -#define REG64( addr ) (*(volatile U64 *)(addr)) -#endif - -/* Register field mapping */ -#define REGFIELD(reg, rfld) (((reg) & rfld##_MSK) >> rfld##_SHF) - -/* absolute register address, access */ -#define REGA(addr) REG32(addr) - -/* physical register address, access: base address + offsett */ -#define REGP(base,phys) REG32( (U32)(base) + (phys) ) - -/* relative register address, access: base address + offsett */ -#define REG(base,offs) REG32( (U32)(base) + offs##_##OFS ) - -/* relative register address, access: base address + offsett */ -#define REG_8(base,offs) REG8( (U32)(base) + offs##_##OFS ) - -/* relative register address, access: base address + offsett */ -#define REG_16(base,offs) REG16( (U32)(base) + offs##_##OFS ) - -/* relative register address, access: base address + offsett */ -#define REG_64(base,offs) REG64( (U32)(base) + offs##_##OFS ) - -/************************************** - * Macroes not used by YAMON any more - * (kept for backwards compatibility) - */ -/* register read field */ -#define REGARD(addr,fld) ((REGA(addr) & addr##_##fld##_##MSK) \ - >> addr##_##fld##_##SHF) - -/* register write numeric field value */ -#define REGAWRI(addr,fld,intval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\ - | ((intval) << addr##_##fld##_##SHF)) - -/* register write enumerated field value */ -#define REGAWRE(addr,fld,enumval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\ - | ((addr##_##fld##_##enumval) << addr##_##fld##_##SHF)) - - -/* Examples: - * - * exccode = REGARD(CPU_CAUSE,EXC); - * - * REGA(SDR_CONTROL) = REGAWRI(OSG_CONTROL,TMO,17) - * | REGAWRE(OSG_CONTROL,DTYPE,PC1); - */ - - -/* register read field */ -#define REGRD(base,offs,fld) ((REG(base,offs) & offs##_##fld##_##MSK) \ - >> offs##_##fld##_##SHF) - -/* register write numeric field value */ -#define REGWRI(base,offs,fld,intval)((REG(base,offs)& ~(offs##_##fld##_##MSK))\ - | (((intval) << offs##_##fld##_##SHF) & offs##_##fld##_##MSK)) - -/* register write enumerated field value */ -#define REGWRE(base,offs,fld,enumval)((REG(base,offs) & ~(offs##_##fld##_##MSK))\ - | ((offs##_##fld##_##enumval) << offs##_##fld##_##SHF)) - - -/* physical register read field */ -#define REGPRD(base,phys,fld) ((REGP(base,phys) & phys##_##fld##_##MSK) \ - >> phys##_##fld##_##SHF) - -/* physical register write numeric field value */ -#define REGPWRI(base,phys,fld,intval)((REGP(base,phys)& ~(phys##_##fld##_##MSK))\ - | ((intval) << phys##_##fld##_##SHF)) - -/* physical register write enumerated field value */ -#define REGPWRE(base,phys,fld,enumval)((REGP(base,phys) & ~(phys##_##fld##_##MSK))\ - | ((phys##_##fld##_##enumval) << phys##_##fld##_##SHF)) -/* - * End of macroes not used by YAMON any more - *********************************************/ - -/* Endian related macros */ - -#define SWAP_BYTEADDR32( addr ) ( (addr) ^ 0x3 ) -#define SWAP_U16ADDR32( addr ) ( (addr) ^ 0x2 ) - -/* Set byte address to little endian format */ -#ifdef EL -#define SWAP_BYTEADDR_EL(addr) addr -#else -#define SWAP_BYTEADDR_EL(addr) SWAP_BYTEADDR32( addr ) -#endif - -/* Set byte address to big endian format */ -#ifdef EB -#define SWAP_BYTEADDR_EB(addr) addr -#else -#define SWAP_BYTEADDR_EB(addr) SWAP_BYTEADDR32( addr ) -#endif - -/* Set U16 address to little endian format */ -#ifdef EL -#define SWAP_U16ADDR_EL(addr) addr -#else -#define SWAP_U16ADDR_EL(addr) SWAP_U16ADDR32( addr ) -#endif - -/* Set U16 address to big endian format */ -#ifdef EB -#define SWAP_U16ADDR_EB(addr) addr -#else -#define SWAP_U16ADDR_EB(addr) SWAP_U16ADDR32( addr ) -#endif - -#ifdef EL -#define REGW32LE(addr, data) REG32(addr) = (data) -#define REGR32LE(addr, data) (data) = REG32(addr) -#else -#define REGW32LE(addr, data) REG32(addr) = SWAPEND32(data) -#define REGR32LE(addr, data) (data) = REG32(addr), (data) = SWAPEND32(data) -#endif - -/* Set of 'LE'-macros, convert by BE: */ -#ifdef EL -#define CPU_TO_LE32( value ) (value) -#define LE32_TO_CPU( value ) (value) - -#define CPU_TO_LE16( value ) (value) -#define LE16_TO_CPU( value ) (value) -#else -#define CPU_TO_LE32( value ) ( ( ((U32)value) << 24) | \ - ((0x0000FF00UL & ((U32)value)) << 8) | \ - ((0x00FF0000UL & ((U32)value)) >> 8) | \ - ( ((U32)value) >> 24) ) -#define LE32_TO_CPU( value ) CPU_TO_LE32( value ) - -#define CPU_TO_LE16( value ) ( ((U16)(((U16)value) << 8)) | \ - ((U16)(((U16)value) >> 8)) ) -#define LE16_TO_CPU( value ) CPU_TO_LE16( value ) -#endif - -/* Set of 'BE'-macros, convert by LE: */ -#ifdef EB -#define CPU_TO_BE32( value ) (value) -#define BE32_TO_CPU( value ) (value) - -#define CPU_TO_BE16( value ) (value) -#define BE16_TO_CPU( value ) (value) -#else -#define CPU_TO_BE32( value ) ( ( ((U32)value) << 24) | \ - ((0x0000FF00UL & ((U32)value)) << 8) | \ - ((0x00FF0000UL & ((U32)value)) >> 8) | \ - ( ((U32)value) >> 24) ) -#define BE32_TO_CPU( value ) CPU_TO_BE32( value ) - -#define CPU_TO_BE16( value ) ( ((U16)(((U16)value) << 8)) | \ - ((U16)(((U16)value) >> 8)) ) -#define BE16_TO_CPU( value ) CPU_TO_BE16( value ) -#endif - - -/* Control characters */ -#define CTRL_A ('A'-0x40) -#define CTRL_B ('B'-0x40) -#define CTRL_C ('C'-0x40) -#define CTRL_D ('D'-0x40) -#define CTRL_E ('E'-0x40) -#define CTRL_F ('F'-0x40) -#define CTRL_H ('H'-0x40) -#define CTRL_K ('K'-0x40) -#define CTRL_N ('N'-0x40) -#define CTRL_P ('P'-0x40) -#define CTRL_U ('U'-0x40) -#define BACKSPACE 0x08 -#define DEL 0x7F -#define TAB 0x09 -#define CR 0x0D /* Enter Key */ -#define LF 0x0A -#define ESC 0x1B -#define SP 0x20 -#define CSI 0x9B - - -/* DEF2STR(x) converts #define symbol to string */ -#define DEF2STR1(x) #x -#define DEF2STR(x) DEF2STR1(x) - - -#endif /* _MIPS_ASM_H_ */ diff --git a/libcpu/mips/common/mips_cache.c b/libcpu/mips/common/mips_cache.c index 1c979b7106..8c86bb131a 100644 --- a/libcpu/mips/common/mips_cache.c +++ b/libcpu/mips/common/mips_cache.c @@ -19,7 +19,7 @@ * * Change Logs: * Date Author Notes - * 2016��9��7�� Urey the first version + * 2016-09-07 Urey the first version */ #include <rtthread.h> diff --git a/libcpu/mips/common/mips_cache.h b/libcpu/mips/common/mips_cache.h index a947041073..438dd76cde 100644 --- a/libcpu/mips/common/mips_cache.h +++ b/libcpu/mips/common/mips_cache.h @@ -19,7 +19,7 @@ * * Change Logs: * Date Author Notes - * 2016��9��10�� Urey the first version + * 2016-09-07 Urey the first version */ #ifndef _MIPS_CACHE_H_ @@ -38,11 +38,7 @@ #define INDEX_LOAD_TAG_D 0x05 #define INDEX_STORE_TAG_I 0x08 #define INDEX_STORE_TAG_D 0x09 -#if defined(CONFIG_CPU_LOONGSON2) -#define HIT_INVALIDATE_I 0x00 -#else #define HIT_INVALIDATE_I 0x10 -#endif #define HIT_INVALIDATE_D 0x11 #define HIT_WRITEBACK_INV_D 0x15 diff --git a/libcpu/mips/common/mips_cfg.h b/libcpu/mips/common/mips_cfg.h index 3f0575d65a..f7e38b4af4 100644 --- a/libcpu/mips/common/mips_cfg.h +++ b/libcpu/mips/common/mips_cfg.h @@ -19,7 +19,7 @@ * * Change Logs: * Date Author Notes - * 2016��9��10�� Urey the first version + * 2016-09-07 Urey the first version */ #ifndef _MIPS_CFG_H_ @@ -30,12 +30,12 @@ typedef struct mips32_core_cfg { uint16_t icache_line_size; -// uint16_t icache_lines_per_way; -// uint16_t icache_ways; + uint16_t icache_lines_per_way; + uint16_t icache_ways; uint16_t icache_size; uint16_t dcache_line_size; -// uint16_t dcache_lines_per_way; -// uint16_t dcache_ways; + uint16_t dcache_lines_per_way; + uint16_t dcache_ways; uint16_t dcache_size; uint16_t max_tlb_entries; /* number of tlb entry */ diff --git a/libcpu/mips/common/mips_context.h b/libcpu/mips/common/mips_context.h deleted file mode 100644 index 60d573784d..0000000000 --- a/libcpu/mips/common/mips_context.h +++ /dev/null @@ -1,280 +0,0 @@ -/* - * File : mips_context_asm.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��7�� Urey the first version - */ - -#ifndef _MIPS_CONTEXT_ASM_H_ -#define _MIPS_CONTEXT_ASM_H_ - -#define CONTEXT_SIZE ( STK_CTX_SIZE + FPU_ADJ ) -#ifdef __mips_hard_float -#define FPU_ADJ (32 * 4 + 8) /* FP0-FP31 + CP1_STATUS */ -#define FPU_CTX ( CONTEXT_SIZE - FPU_ADJ ) -#else -#define FPU_ADJ 0 -#endif - - - -#ifdef __ASSEMBLY__ - -#ifdef __mips_hard_float -.global _fpctx_save -.global _fpctx_load -#endif - -.macro SAVE_CONTEXT - .set push - .set noat - .set noreorder - .set volatile - - //save SP - move k1, sp - move k0, sp - subu sp, k1, CONTEXT_SIZE - sw k0, (29 * 4)(sp) - - //save REG - sw $0, ( 0 * 4)(sp) - sw $1, ( 1 * 4)(sp) - sw $2, ( 2 * 4)(sp) - sw $3, ( 3 * 4)(sp) - sw $4, ( 4 * 4)(sp) - sw $5, ( 5 * 4)(sp) - sw $6, ( 6 * 4)(sp) - sw $7, ( 7 * 4)(sp) - sw $8, ( 8 * 4)(sp) - sw $9, ( 9 * 4)(sp) - sw $10, (10 * 4)(sp) - sw $11, (11 * 4)(sp) - sw $12, (12 * 4)(sp) - sw $13, (13 * 4)(sp) - sw $14, (14 * 4)(sp) - sw $15, (15 * 4)(sp) - sw $16, (16 * 4)(sp) - sw $17, (17 * 4)(sp) - sw $18, (18 * 4)(sp) - sw $19, (19 * 4)(sp) - sw $20, (20 * 4)(sp) - sw $21, (21 * 4)(sp) - sw $22, (22 * 4)(sp) - sw $23, (23 * 4)(sp) - sw $24, (24 * 4)(sp) - sw $25, (25 * 4)(sp) - /* K0 K1 */ - sw $28, (28 * 4)(sp) - /* SP */ - sw $30, (30 * 4)(sp) - sw $31, (31 * 4)(sp) - - /* STATUS CAUSE EPC.... */ - mfc0 $2, CP0_STATUS - sw $2, STK_OFFSET_SR(sp) - - mfc0 $2, CP0_CAUSE - sw $2, STK_OFFSET_CAUSE(sp) - - mfc0 $2, CP0_BADVADDR - sw $2, STK_OFFSET_BADVADDR(sp) - - MFC0 $2, CP0_EPC - sw $2, STK_OFFSET_EPC(sp) - - mfhi $2 - sw $2, STK_OFFSET_HI(sp) - - mflo $2 - sw $2, STK_OFFSET_LO(sp) -#ifdef __mips_hard_float - add a0, sp,STK_CTX_SIZE - - mfc0 t0, CP0_STATUS - .set push - .set at - or t0, M_StatusCU1 - .set push - mtc0 t0, CP0_STATUS - - cfc1 t0, CP1_STATUS - sw t0 , 0x00(a0) - swc1 $f0,(0x04 * 1)(a0) - swc1 $f1,(0x04 * 2)(a0) - swc1 $f2,(0x04 * 3)(a0) - swc1 $f3,(0x04 * 4)(a0) - swc1 $f4,(0x04 * 5)(a0) - swc1 $f5,(0x04 * 6)(a0) - swc1 $f6,(0x04 * 7)(a0) - swc1 $f7,(0x04 * 8)(a0) - swc1 $f8,(0x04 * 9)(a0) - swc1 $f9,(0x04 * 10)(a0) - swc1 $f10,(0x04 * 11)(a0) - swc1 $f11,(0x04 * 12)(a0) - swc1 $f12,(0x04 * 13)(a0) - swc1 $f13,(0x04 * 14)(a0) - swc1 $f14,(0x04 * 15)(a0) - swc1 $f15,(0x04 * 16)(a0) - swc1 $f16,(0x04 * 17)(a0) - swc1 $f17,(0x04 * 18)(a0) - swc1 $f18,(0x04 * 19)(a0) - swc1 $f19,(0x04 * 20)(a0) - swc1 $f20,(0x04 * 21)(a0) - swc1 $f21,(0x04 * 22)(a0) - swc1 $f22,(0x04 * 23)(a0) - swc1 $f23,(0x04 * 24)(a0) - swc1 $f24,(0x04 * 25)(a0) - swc1 $f25,(0x04 * 26)(a0) - swc1 $f26,(0x04 * 27)(a0) - swc1 $f27,(0x04 * 28)(a0) - swc1 $f28,(0x04 * 29)(a0) - swc1 $f29,(0x04 * 30)(a0) - swc1 $f30,(0x04 * 31)(a0) - swc1 $f31,(0x04 * 32)(a0) - - nop -#endif - - //restore a0 - lw a0, (REG_A0 * 4)(sp) - - .set pop -.endm - - -.macro RESTORE_CONTEXT - .set push - .set noat - .set noreorder - .set volatile - -#ifdef __mips_hard_float - add a0, sp,STK_CTX_SIZE - - mfc0 t0, CP0_STATUS - .set push - .set at - or t0, M_StatusCU1 - .set noat - mtc0 t0, CP0_STATUS - - lw t0 , 0x00(a0) - lwc1 $f0,(0x04 * 1)(a0) - lwc1 $f1,(0x04 * 2)(a0) - lwc1 $f2,(0x04 * 3)(a0) - lwc1 $f3,(0x04 * 4)(a0) - lwc1 $f4,(0x04 * 5)(a0) - lwc1 $f5,(0x04 * 6)(a0) - lwc1 $f6,(0x04 * 7)(a0) - lwc1 $f7,(0x04 * 8)(a0) - lwc1 $f8,(0x04 * 9)(a0) - lwc1 $f9,(0x04 * 10)(a0) - lwc1 $f10,(0x04 * 11)(a0) - lwc1 $f11,(0x04 * 12)(a0) - lwc1 $f12,(0x04 * 13)(a0) - lwc1 $f13,(0x04 * 14)(a0) - lwc1 $f14,(0x04 * 15)(a0) - lwc1 $f15,(0x04 * 16)(a0) - lwc1 $f16,(0x04 * 17)(a0) - lwc1 $f17,(0x04 * 18)(a0) - lwc1 $f18,(0x04 * 19)(a0) - lwc1 $f19,(0x04 * 20)(a0) - lwc1 $f20,(0x04 * 21)(a0) - lwc1 $f21,(0x04 * 22)(a0) - lwc1 $f22,(0x04 * 23)(a0) - lwc1 $f23,(0x04 * 24)(a0) - lwc1 $f24,(0x04 * 25)(a0) - lwc1 $f25,(0x04 * 26)(a0) - lwc1 $f26,(0x04 * 27)(a0) - lwc1 $f27,(0x04 * 28)(a0) - lwc1 $f28,(0x04 * 29)(a0) - lwc1 $f29,(0x04 * 30)(a0) - lwc1 $f30,(0x04 * 31)(a0) - lwc1 $f31,(0x04 * 32)(a0) - ctc1 t0, CP1_STATUS ;/* restore fpp status reg */ - - nop -#endif - - /* ͨ�üĴ��� */ - /* ZERO */ - lw $1, ( 1 * 4)(sp) - /* V0 */ - lw $3, ( 3 * 4)(sp) - lw $4, ( 4 * 4)(sp) - lw $5, ( 5 * 4)(sp) - lw $6, ( 6 * 4)(sp) - lw $7, ( 7 * 4)(sp) - lw $8, ( 8 * 4)(sp) - lw $9, ( 9 * 4)(sp) - lw $10, (10 * 4)(sp) - lw $11, (11 * 4)(sp) - lw $12, (12 * 4)(sp) - lw $13, (13 * 4)(sp) - lw $14, (14 * 4)(sp) - lw $15, (15 * 4)(sp) - lw $16, (16 * 4)(sp) - lw $17, (17 * 4)(sp) - lw $18, (18 * 4)(sp) - lw $19, (19 * 4)(sp) - lw $20, (20 * 4)(sp) - lw $21, (21 * 4)(sp) - lw $22, (22 * 4)(sp) - lw $23, (23 * 4)(sp) - lw $24, (24 * 4)(sp) - lw $25, (25 * 4)(sp) - lw $26, (26 * 4)(sp) - lw $27, (27 * 4)(sp) - lw $28, (28 * 4)(sp) - /* SP */ - lw $30, (30 * 4)(sp) - lw $31, (31 * 4)(sp) - - - /* STATUS CAUSE EPC.... */ - lw $2, STK_OFFSET_HI(sp) - mthi $2 - lw $2, STK_OFFSET_LO(sp) - mtlo $2 - - lw $2, STK_OFFSET_SR(sp) - mtc0 $2, CP0_STATUS - - lw $2, STK_OFFSET_BADVADDR(sp) - mtc0 $2, CP0_BADVADDR - - lw $2, STK_OFFSET_CAUSE(sp) - mtc0 $2, CP0_CAUSE - - lw $2, STK_OFFSET_EPC(sp) - MTC0 $2, CP0_EPC - - //restore $2 - lw $2, ( 2 * 4)(sp) - //restore sp - lw $29, (29 * 4)(sp) - - eret - nop - .set pop -.endm -#endif -#endif /* _MIPS_CONTEXT_ASM_H_ */ diff --git a/libcpu/mips/common/mips_def.h b/libcpu/mips/common/mips_def.h deleted file mode 100644 index 70da2deccf..0000000000 --- a/libcpu/mips/common/mips_def.h +++ /dev/null @@ -1,2310 +0,0 @@ -/* - * File : mips_def.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��7�� Urey the first version - */ - -#ifndef _COMMON_MIPS_DEF_H_ -#define _COMMON_MIPS_DEF_H_ - - -/* - ************************************************************************ - * I N S T R U C T I O N F O R M A T S * - ************************************************************************ - * - * The following definitions describe each field in an instruction. There - * is one diagram for each type of instruction, with field definitions - * following the diagram for that instruction. Note that if a field of - * the same name and position is defined in an earlier diagram, it is - * not defined again in the subsequent diagram. Only new fields are - * defined for each diagram. - * - * R-Type (operate) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | | rs | rt | rd | sa | | - * | Opcode | | | Tcode | func | - * | | Bcode | | sel | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define S_InstnOpcode 26 -#define M_InstnOpcode (0x3f << S_InstnOpcode) -#define S_InstnRS 21 -#define M_InstnRS (0x1f << S_InstnRS) -#define S_InstnRT 16 -#define M_InstnRT (0x1f << S_InstnRT) -#define S_InstnRD 11 -#define M_InstnRD (0x1f << S_InstnRD) -#define S_InstnSA 6 -#define M_InstnSA (0x1f << S_InstnSA) -#define S_InstnTcode 6 -#define M_InstnTcode (0x3ff << S_InstnTcode) -#define S_InstnBcode 6 -#define M_InstnBcode (0xfffff << S_InstnBcode) -#define S_InstnFunc 0 -#define M_InstnFunc (0x3f << S_InstnFunc) -#define S_InstnSel 0 -#define M_InstnSel (0x7 << S_InstnSel) - -/* - * I-Type (load, store, branch, immediate) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | rs | rt | Offset | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define S_InstnOffset 0 -#define M_InstnOffset (0xffff << S_InstnOffset) - -/* - * I-Type (pref) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | rs | hint | Offset | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define S_InstnHint S_InstnRT -#define M_InstnHint M_InstnRT - -/* - * J-Type (jump) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | JIndex | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define S_InstnJIndex 0 -#define M_InstnJIndex (0x03ffffff << S_InstnJIndex) - -/* - * FP R-Type (operate) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | fmt | ft | fs | fd | func | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define S_InstnFmt S_InstnRS -#define M_InstnFmt M_InstnRS -#define S_InstnFT S_InstnRT -#define M_InstnFT M_InstnRT -#define S_InstnFS S_InstnRD -#define M_InstnFS M_InstnRD -#define S_InstnFD S_InstnSA -#define M_InstnFD M_InstnSA - -/* - * FP R-Type (cpu <-> cpu data movement)) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | sub | rt | fs | 0 | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define S_InstnSub S_InstnRS -#define M_InstnSub M_InstnRS - -/* - * FP R-Type (compare) - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | | | | | | |C| | - * | Opcode | fmt | ft | fs | cc |0|A| func | - * | | | | | | |B| | - * | | | | | | |S| | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define S_InstnCCcmp 8 -#define M_InstnCCcmp (0x7 << S_InstnCCcmp) -#define S_InstnCABS 6 -#define M_InstnCABS (0x1 << S_InstnCABS) - -/* - * FP R-Type (FPR conditional move on FP cc) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | fmt | cc |n|t| fs | fd | func | - * | | | |d|f| | | | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define S_InstnCC 18 -#define M_InstnCC (0x7 << S_InstnCC) -#define S_InstnND 17 -#define M_InstnND (0x1 << S_InstnND) -#define S_InstnTF 16 -#define M_InstnTF (0x1 << S_InstnTF) - -/* - * FP R-Type (3-operand operate) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | fr | ft | fs | fd | op4 | fmt3| - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define S_InstnFR S_InstnRS -#define M_InstnFR M_InstnRS -#define S_InstnOp4 3 -#define M_InstnOp4 (0x7 << S_InstnOp4) -#define S_InstnFmt3 0 -#define M_InstnFmt3 (0x7 << S_InstnFmt3) - -/* - * FP R-Type (Indexed load, store) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | rs | rt | 0 | fd | func | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ -/* - * FP R-Type (prefx) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | rs | rt | hint | 0 | func | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define S_InstnHintX S_InstnRD -#define M_InstnHintX M_InstnRD - -/* - * FP R-Type (GPR conditional move on FP cc) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | rs | cc |n|t| rd | 0 | func | - * | | | |d|f| | | | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -/* - * FP I-Type (load, store) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | rs | ft | Offset | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -/* - * FP I-Type (branch) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | fmt | cc |n|t| Offset | - * | | | |d|f| | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - - -/* - ************************************************************************* - * V I R T U A L A D D R E S S D E F I N I T I O N S * - ************************************************************************* - */ - -#ifdef MIPSADDR64 -#define A_K0BASE UNS64Const(0xffffffff80000000) -#define A_K1BASE UNS64Const(0xffffffffa0000000) -#define A_K2BASE UNS64Const(0xffffffffc0000000) -#define A_K3BASE UNS64Const(0xffffffffe0000000) -#define A_REGION UNS64Const(0xc000000000000000) -#define A_XKPHYS_ATTR UNS64Const(0x3800000000000000) -#else -#define A_K0BASE 0x80000000 -#define A_K1BASE 0xa0000000 -#define A_K2BASE 0xc0000000 -#define A_K3BASE 0xe0000000 -#endif -#define M_KMAPPED 0x40000000 /* KnSEG address is mapped if bit is one */ - - -#ifdef MIPS_Model64 - -#define S_VMAP64 62 -#define M_VMAP64 UNS64Const(0xc000000000000000) - -#define K_VMode11 3 -#define K_VMode10 2 -#define K_VMode01 1 -#define K_VMode00 0 - -#define S_KSEG3 29 -#define M_KSEG3 (0x7 << S_KSEG3) -#define K_KSEG3 7 - -#define S_SSEG 29 -#define M_SSEG (0x7 << S_KSEG3) -#define K_SSEG 6 - -#define S_KSSEG 29 -#define M_KSSEG (0x7 << S_KSEG3) -#define K_KSSEG 6 - -#define S_KSEG1 29 -#define M_KSEG1 (0x7 << S_KSEG3) -#define K_KSEG1 5 - -#define S_KSEG0 29 -#define M_KSEG0 (0x7 << S_KSEG3) -#define K_KSEG0 4 - -#define S_XKSEG 29 -#define M_XKSEG (0x7 << S_KSEG3) -#define K_XKSEG 3 - -#define S_USEG 31 -#define M_USEG (0x1 << S_USEG) -#define K_USEG 0 - -#define S_EjtagProbeMem 20 -#define M_EjtagProbeMem (0x1 << S_EjtagProbeMem) -#define K_EjtagProbeMem 0 - - - -#else - -#define S_KSEG3 29 -#define M_KSEG3 (0x7 << S_KSEG3) -#define K_KSEG3 7 - -#define S_KSSEG 29 -#define M_KSSEG (0x7 << S_KSSEG) -#define K_KSSEG 6 - -#define S_SSEG 29 -#define M_SSEG (0x7 << S_SSEG) -#define K_SSEG 6 - -#define S_KSEG1 29 -#define M_KSEG1 (0x7 << S_KSEG1) -#define K_KSEG1 5 - -#define S_KSEG0 29 -#define M_KSEG0 (0x7 << S_KSEG0) -#define K_KSEG0 4 - -#define S_KUSEG 31 -#define M_KUSEG (0x1 << S_KUSEG) -#define K_KUSEG 0 - -#define S_SUSEG 31 -#define M_SUSEG (0x1 << S_SUSEG) -#define K_SUSEG 0 - -#define S_USEG 31 -#define M_USEG (0x1 << S_USEG) -#define K_USEG 0 - -#define K_EjtagLower 0xff200000 -#define K_EjtagUpper 0xff3fffff - -#define S_EjtagProbeMem 20 -#define M_EjtagProbeMem (0x1 << S_EjtagProbeMem) -#define K_EjtagProbeMem 0 - -#endif - - - -/* - ************************************************************************* - * C A C H E I N S T R U C T I O N O P E R A T I O N C O D E S * - ************************************************************************* - */ - -/* - * Cache encodings - */ -#define K_CachePriI 0 /* Primary Icache */ -#define K_CachePriD 1 /* Primary Dcache */ -#define K_CachePriU 1 /* Unified primary */ -#define K_CacheTerU 2 /* Unified Tertiary */ -#define K_CacheSecU 3 /* Unified secondary */ - - -/* - * Function encodings - */ -#define S_CacheFunc 2 /* Amount to shift function encoding within 5-bit field */ -#define K_CacheIndexInv 0 /* Index invalidate */ -#define K_CacheIndexWBInv 0 /* Index writeback invalidate */ -#define K_CacheIndexLdTag 1 /* Index load tag */ -#define K_CacheIndexStTag 2 /* Index store tag */ -#define K_CacheHitInv 4 /* Hit Invalidate */ -#define K_CacheFill 5 /* Fill (Icache only) */ -#define K_CacheHitWBInv 5 /* Hit writeback invalidate */ -#define K_CacheHitWB 6 /* Hit writeback */ -#define K_CacheFetchLock 7 /* Fetch and lock */ - -#define ICIndexInv ((K_CacheIndexInv << S_CacheFunc) | K_CachePriI) -#define DCIndexWBInv ((K_CacheIndexWBInv << S_CacheFunc) | K_CachePriD) -#define DCIndexInv DCIndexWBInv -#define ICIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriI) -#define DCIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriD) -#define ICIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriI) -#define DCIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriD) -#define ICHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriI) -#define DCHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriD) -#define ICFill ((K_CacheFill << S_CacheFunc) | K_CachePriI) -#define DCHitWBInv ((K_CacheHitWBInv << S_CacheFunc) | K_CachePriD) -#define DCHitWB ((K_CacheHitWB << S_CacheFunc) | K_CachePriD) -#define ICFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriI) -#define DCFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriD) - - -/* - ************************************************************************* - * P R E F E T C H I N S T R U C T I O N H I N T S * - ************************************************************************* - */ - -#define PrefLoad 0 -#define PrefStore 1 -#define PrefLoadStreamed 4 -#define PrefStoreStreamed 5 -#define PrefLoadRetained 6 -#define PrefStoreRetained 7 -#define PrefWBInval 25 -#define PrefNudge 25 - - -/* - ************************************************************************* - * C P U R E G I S T E R D E F I N I T I O N S * - ************************************************************************* - */ - - -/* - ************************************************************************* - * S O F T W A R E G P R N A M E S * - ************************************************************************* - */ -#ifdef __ASSEMBLY__ -#define zero $0 -#define AT $1 -#define v0 $2 -#define v1 $3 -#define a0 $4 -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 -#define s0 $16 -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 -#define t9 $25 -#define k0 $26 -#define k1 $27 -#define gp $28 -#define sp $29 -#define fp $30 -#define ra $31 - -/* - * The following registers are used by the AVP environment and - * are not part of the normal software definitions. - */ - -#ifdef MIPSAVPENV -#define repc $25 /* Expected exception PC */ -#define tid $30 /* Current test case address */ -#endif - - -/* - ************************************************************************* - * H A R D W A R E G P R N A M E S * - ************************************************************************* - * - * In the AVP environment, several of the `r' names are removed from the - * name space because they are used by the kernel for special purposes. - * Removing them causes assembly rather than runtime errors for tests that - * use the `r' names. - * - * - r25 (repc) is used as the expected PC on an exception - * - r26-r27 (k0, k1) are used in the exception handler - * - r30 (tid) is used as the current test address - */ - -#define r0 $0 -#define r1 $1 -#define r2 $2 -#define r3 $3 -#define r4 $4 -#define r5 $5 -#define r6 $6 -#define r7 $7 -#define r8 $8 -#define r9 $9 -#define r10 $10 -#define r11 $11 -#define r12 $12 -#define r13 $13 -#define r14 $14 -#define r15 $15 -#define r16 $16 -#define r17 $17 -#define r18 $18 -#define r19 $19 -#define r20 $20 -#define r21 $21 -#define r22 $22 -#define r23 $23 -#define r24 $24 -#ifdef MIPSAVPENV -#define r25 r25_unknown -#define r26 r26_unknown -#define r27 r27_unknown -#else -#define r25 $25 -#define r26 $26 -#define r27 $27 -#endif -#define r28 $28 -#define r29 $29 -#ifdef MIPSAVPENV -#define r30 r30_unknown -#else -#define r30 $30 -#endif -#define r31 $31 - -#endif - -/* - ************************************************************************* - * H A R D W A R E G P R I N D I C E S * - ************************************************************************* - * - * These definitions provide the index (number) of the GPR, as opposed - * to the assembler register name ($n). - */ - -#define R_r0 0 -#define R_r1 1 -#define R_r2 2 -#define R_r3 3 -#define R_r4 4 -#define R_r5 5 -#define R_r6 6 -#define R_r7 7 -#define R_r8 8 -#define R_r9 9 -#define R_r10 10 -#define R_r11 11 -#define R_r12 12 -#define R_r13 13 -#define R_r14 14 -#define R_r15 15 -#define R_r16 16 -#define R_r17 17 -#define R_r18 18 -#define R_r19 19 -#define R_r20 20 -#define R_r21 21 -#define R_r22 22 -#define R_r23 23 -#define R_r24 24 -#define R_r25 25 -#define R_r26 26 -#define R_r27 27 -#define R_r28 28 -#define R_r29 29 -#define R_r30 30 -#define R_r31 31 -#define R_hi 32 /* Hi register */ -#define R_lo 33 /* Lo register */ - - -/* - ************************************************************************* - * S O F T W A R E G P R M A S K S * - ************************************************************************* - * - * These definitions provide the bit mask corresponding to the GPR number - */ - -#define M_AT (1<<1) -#define M_v0 (1<<2) -#define M_v1 (1<<3) -#define M_a0 (1<<4) -#define M_a1 (1<<5) -#define M_a2 (1<<6) -#define M_a3 (1<<7) -#define M_t0 (1<<8) -#define M_t1 (1<<9) -#define M_t2 (1<<10) -#define M_t3 (1<<11) -#define M_t4 (1<<12) -#define M_t5 (1<<13) -#define M_t6 (1<<14) -#define M_t7 (1<<15) -#define M_s0 (1<<16) -#define M_s1 (1<<17) -#define M_s2 (1<<18) -#define M_s3 (1<<19) -#define M_s4 (1<<20) -#define M_s5 (1<<21) -#define M_s6 (1<<22) -#define M_s7 (1<<23) -#define M_t8 (1<<24) -#define M_t9 (1<<25) -#define M_k0 (1<<26) -#define M_k1 (1<<27) -#define M_gp (1<<28) -#define M_sp (1<<29) -#define M_fp (1<<30) -#define M_ra (1<<31) - - -/* - ************************************************************************* - * C P 0 R E G I S T E R D E F I N I T I O N S * - ************************************************************************* - * Each register has the following definitions: - * - * C0_rrr The register number (as a $n value) - * R_C0_rrr The register index (as an integer corresponding - * to the register number) - * - * Each field in a register has the following definitions: - * - * S_rrrfff The shift count required to right-justify - * the field. This corresponds to the bit - * number of the right-most bit in the field. - * M_rrrfff The Mask required to isolate the field. - * - * Register diagrams included below as comments correspond to the - * MIPS32 and MIPS64 architecture specifications. Refer to other - * sources for register diagrams for older architectures. - */ - - -/* - ************************************************************************ - * I N D E X R E G I S T E R ( 0 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |P| 0 | Index | Index - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Index $0 -#define R_C0_Index 0 -#define C0_INX C0_Index /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_IndexP 31 /* Probe failure (R)*/ -#define M_IndexP (0x1 << S_IndexP) - -#define S_IndexIndex 0 /* TLB index (R/W)*/ -#define M_IndexIndex (0x3f << S_IndexIndex) - -#define M_Index0Fields 0x7fffffc0 -#define M_IndexRFields 0x80000000 - - -/* - ************************************************************************ - * R A N D O M R E G I S T E R ( 1 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | 0 | Index | Random - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Random $1 -#define R_C0_Random 1 -#define C0_RAND $1 /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_RandomIndex 0 /* TLB random index (R)*/ -#define M_RandomIndex (0x3f << S_RandomIndex) - -#define M_Random0Fields 0xffffffc0 -#define M_RandomRFields 0x0000003f - - -/* - ************************************************************************ - * E N T R Y L O 0 R E G I S T E R ( 2 ) * - ************************************************************************ - * - * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Fill (0) //| 0 | PFN | C |D|V|G| EntryLo0 - * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_EntryLo0 $2 -#define R_C0_EntryLo0 2 -#define C0_TLBLO_0 C0_EntryLo0 /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_EntryLoPFN 6 /* PFN (R/W) */ -#define M_EntryLoPFN (0xffffff << S_EntryLoPFN) -#define S_EntryLoC 3 /* Coherency attribute (R/W) */ -#define M_EntryLoC (0x7 << S_EntryLoC) -#define S_EntryLoD 2 /* Dirty (R/W) */ -#define M_EntryLoD (0x1 << S_EntryLoD) -#define S_EntryLoV 1 /* Valid (R/W) */ -#define M_EntryLoV (0x1 << S_EntryLoV) -#define S_EntryLoG 0 /* Global (R/W) */ -#define M_EntryLoG (0x1 << S_EntryLoG) -#define M_EntryLoOddPFN (0x1 << S_EntryLoPFN) /* Odd PFN bit */ -#define S_EntryLo_RS K_PageAlign /* Right-justify PFN */ -#define S_EntryLo_LS S_EntryLoPFN /* Position PFN to appropriate position */ - -#define M_EntryLo0Fields 0x00000000 -#define M_EntryLoRFields 0xc0000000 -#define M_EntryLo0Fields64 UNS64Const(0x0000000000000000) -#define M_EntryLoRFields64 UNS64Const(0xffffffffc0000000) - -/* - * Cache attribute values in the C field of EntryLo and the - * K0 field of Config - */ -#define K_CacheAttrCWTnWA 0 /* Cacheable, write-thru, no write allocate */ -#define K_CacheAttrCWTWA 1 /* Cacheable, write-thru, write allocate */ -#define K_CacheAttrU 2 /* Uncached */ -#define K_CacheAttrC 3 /* Cacheable */ -#define K_CacheAttrCN 3 /* Cacheable, non-coherent */ -#define K_CacheAttrCCE 4 /* Cacheable, coherent, exclusive */ -#define K_CacheAttrCCS 5 /* Cacheable, coherent, shared */ -#define K_CacheAttrCCU 6 /* Cacheable, coherent, update */ -#define K_CacheAttrUA 7 /* Uncached accelerated */ - - -/* - ************************************************************************ - * E N T R Y L O 1 R E G I S T E R ( 3 ) * - ************************************************************************ - * - * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Fill (0) //| 0 | PFN | C |D|V|G| EntryLo1 - * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_EntryLo1 $3 -#define R_C0_EntryLo1 3 -#define C0_TLBLO_1 C0_EntryLo1 /* OBSOLETE - DO NOT USE IN NEW CODE */ - -/* - * Field definitions are as given for EntryLo0 above - */ - - -/* - ************************************************************************ - * C O N T E X T R E G I S T E R ( 4 ) * - ************************************************************************ - * - * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | // PTEBase | BadVPN<31:13> | 0 | Context - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Context $4 -#define R_C0_Context 4 -#define C0_CTXT C0_Context /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_ContextPTEBase 23 /* PTE base (R/W) */ -#define M_ContextPTEBase (0x1ff << S_ContextPTEBase) -#define S_ContextBadVPN 4 /* BadVPN2 (R) */ -#define M_ContextBadVPN (0x7ffff << S_ContextBadVPN) -#define S_ContextBadVPN_LS 9 /* Position BadVPN to bit 31 */ -#define S_ContextBadVPN_RS 13 /* Right-justify shifted BadVPN field */ - -#define M_Context0Fields 0x0000000f -#define M_ContextRFields 0x007ffff0 -#define M_Context0Fields64 UNS64Const(0x000000000000000f) -#define M_ContextRFields64 UNS64Const(0x00000000007ffff0) - - -/* - ************************************************************************ - * P A G E M A S K R E G I S T E R ( 5 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | 0 | Mask | 0 | PageMask - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_PageMask $5 -#define R_C0_PageMask 5 /* Mask (R/W) */ -#define C0_PGMASK C0_PageMask /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_PageMaskMask 13 -#define M_PageMaskMask (0xfff << S_PageMaskMask) - -#define M_PageMask0Fields 0xfe001fff -#define M_PageMaskRFields 0x00000000 - -/* - * Values in the Mask field - */ -#define K_PageMask4K 0x000 /* K_PageMasknn values are values for use */ -#define K_PageMask16K 0x003 /* with KReqPageAttributes or KReqPageMask macros */ -#define K_PageMask64K 0x00f -#define K_PageMask256K 0x03f -#define K_PageMask1M 0x0ff -#define K_PageMask4M 0x3ff -#define K_PageMask16M 0xfff - -#define M_PageMask4K (K_PageMask4K << S_PageMaskMask) /* M_PageMasknn values are masks */ -#define M_PageMask16K (K_PageMask16K << S_PageMaskMask) /* in position in the PageMask register */ -#define M_PageMask64K (K_PageMask64K << S_PageMaskMask) -#define M_PageMask256K (K_PageMask256K << S_PageMaskMask) -#define M_PageMask1M (K_PageMask1M << S_PageMaskMask) -#define M_PageMask4M (K_PageMask4M << S_PageMaskMask) -#define M_PageMask16M (K_PageMask16M << S_PageMaskMask) - - -/* - ************************************************************************ - * W I R E D R E G I S T E R ( 6 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | 0 | Index | Wired - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Wired $6 -#define R_C0_Wired 6 -#define C0_TLBWIRED C0_Wired /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_WiredIndex 0 /* TLB wired boundary (R/W) */ -#define M_WiredIndex (0x3f << S_WiredIndex) - -#define M_Wired0Fields 0xffffffc0 -#define M_WiredRFields 0x00000000 - - -/* - ************************************************************************ - * B A D V A D D R R E G I S T E R ( 8 ) * - ************************************************************************ - * - * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | // Bad Virtual Address | BadVAddr - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_BadVAddr $8 -#define R_C0_BadVAddr 8 -#define C0_BADVADDR C0_BadVAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define M_BadVAddrOddPage K_PageSize /* Even/Odd VA bit for pair of PAs */ - -#define M_BadVAddr0Fields 0x00000000 -#define M_BadVAddrRFields 0xffffffff -#define M_BadVAddr0Fields64 UNS64Const(0x0000000000000000) -#define M_BadVAddrRFields64 UNS64Const(0xffffffffffffffff) - -/* - ************************************************************************ - * C O U N T R E G I S T E R ( 9 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Count Value | Count - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Count $9 -#define R_C0_Count 9 -#define C0_COUNT C0_Count /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define M_Count0Fields 0x00000000 -#define M_CountRFields 0x00000000 - - -/* - ************************************************************************ - * E N T R Y H I R E G I S T E R ( 1 0 ) * - ************************************************************************ - * - * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | R | Fill // VPN2 | 0 | ASID | EntryHi - * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_EntryHi $10 -#define R_C0_EntryHi 10 -#define C0_TLBHI C0_EntryHi /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_EntryHiR64 62 /* Region (R/W) */ -#define M_EntryHiR64 UNS64Const(0xc000000000000000) -#define S_EntryHiVPN2 13 /* VPN/2 (R/W) */ -#define M_EntryHiVPN2 (0x7ffff << S_EntryHiVPN2) -#define M_EntryHiVPN264 UNS64Const(0x000000ffffffe000) -#define S_EntryHiASID 0 /* ASID (R/W) */ -#define M_EntryHiASID (0xff << S_EntryHiASID) -#define S_EntryHiVPN_Shf S_EntryHiVPN2 - -#define M_EntryHi0Fields 0x00001f00 -#define M_EntryHiRFields 0x00000000 -#define M_EntryHi0Fields64 UNS64Const(0x0000000000001f00) -#define M_EntryHiRFields64 UNS64Const(0x3fffff0000000000) - - -/* - ************************************************************************ - * C O M P A R E R E G I S T E R ( 1 1 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Compare Value | Compare - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Compare $11 -#define R_C0_Compare 11 -#define C0_COMPARE C0_Compare /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define M_Compare0Fields 0x00000000 -#define M_CompareRFields 0x00000000 - - -/* - ************************************************************************ - * S T A T U S R E G I S T E R ( 1 2 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |C|C|C|C|R|F|R|M|P|B|T|S|M| | R |I|I|I|I|I|I|I|I|K|S|U|U|R|E|E|I| - * |U|U|U|U|P|R|E|X|X|E|S|R|M| | s |M|M|M|M|M|M|M|M|X|X|X|M|s|R|X|E| Status - * |3|2|1|0| | | | | |V| | |I| | v |7|6|5|4|3|2|1|0| | | | |v|L|L| | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Status $12 -#define R_C0_Status 12 -#define C0_SR C0_Status /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_StatusCU 28 /* Coprocessor enable (R/W) */ -#define M_StatusCU (0xf << S_StatusCU) -#define S_StatusCU3 31 -#define M_StatusCU3 (0x1 << S_StatusCU3) -#define S_StatusCU2 30 -#define M_StatusCU2 (0x1 << S_StatusCU2) -#define S_StatusCU1 29 -#define M_StatusCU1 (0x1 << S_StatusCU1) -#define S_StatusCU0 28 -#define M_StatusCU0 (0x1 << S_StatusCU0) -#define S_StatusRP 27 /* Enable reduced power mode (R/W) */ -#define M_StatusRP (0x1 << S_StatusRP) -#define S_StatusFR 26 /* Enable 64-bit FPRs (MIPS64 only) (R/W) */ -#define M_StatusFR (0x1 << S_StatusFR) -#define S_StatusRE 25 /* Enable reverse endian (R/W) */ -#define M_StatusRE (0x1 << S_StatusRE) -#define S_StatusMX 24 /* Enable access to MDMX resources (MIPS64 only) (R/W) */ -#define M_StatusMX (0x1 << S_StatusMX) -#define S_StatusPX 23 /* Enable access to 64-bit instructions/data (MIPS64 only) (R/W) */ -#define M_StatusPX (0x1 << S_StatusPX) -#define S_StatusBEV 22 /* Enable Boot Exception Vectors (R/W) */ -#define M_StatusBEV (0x1 << S_StatusBEV) -#define S_StatusTS 21 /* Denote TLB shutdown (R/W) */ -#define M_StatusTS (0x1 << S_StatusTS) -#define S_StatusSR 20 /* Denote soft reset (R/W) */ -#define M_StatusSR (0x1 << S_StatusSR) -#define S_StatusNMI 19 -#define M_StatusNMI (0x1 << S_StatusNMI) /* Denote NMI (R/W) */ -#define S_StatusIM 8 /* Interrupt mask (R/W) */ -#define M_StatusIM (0xff << S_StatusIM) -#define S_StatusIM7 15 -#define M_StatusIM7 (0x1 << S_StatusIM7) -#define S_StatusIM6 14 -#define M_StatusIM6 (0x1 << S_StatusIM6) -#define S_StatusIM5 13 -#define M_StatusIM5 (0x1 << S_StatusIM5) -#define S_StatusIM4 12 -#define M_StatusIM4 (0x1 << S_StatusIM4) -#define S_StatusIM3 11 -#define M_StatusIM3 (0x1 << S_StatusIM3) -#define S_StatusIM2 10 -#define M_StatusIM2 (0x1 << S_StatusIM2) -#define S_StatusIM1 9 -#define M_StatusIM1 (0x1 << S_StatusIM1) -#define S_StatusIM0 8 -#define M_StatusIM0 (0x1 << S_StatusIM0) -#define S_StatusKX 7 /* Enable access to extended kernel addresses (MIPS64 only) (R/W) */ -#define M_StatusKX (0x1 << S_StatusKX) -#define S_StatusSX 6 /* Enable access to extended supervisor addresses (MIPS64 only) (R/W) */ -#define M_StatusSX (0x1 << S_StatusSX) -#define S_StatusUX 5 /* Enable access to extended user addresses (MIPS64 only) (R/W) */ -#define M_StatusUX (0x1 << S_StatusUX) -#define S_StatusKSU 3 /* Two-bit current mode (R/W) */ -#define M_StatusKSU (0x3 << S_StatusKSU) -#define S_StatusUM 4 /* User mode if supervisor mode not implemented (R/W) */ -#define M_StatusUM (0x1 << S_StatusUM) -#define S_StatusSM 3 /* Supervisor mode (R/W) */ -#define M_StatusSM (0x1 << S_StatusSM) -#define S_StatusERL 2 /* Denotes error level (R/W) */ -#define M_StatusERL (0x1 << S_StatusERL) -#define S_StatusEXL 1 /* Denotes exception level (R/W) */ -#define M_StatusEXL (0x1 << S_StatusEXL) -#define S_StatusIE 0 /* Enables interrupts (R/W) */ -#define M_StatusIE (0x1 << S_StatusIE) - -#define M_Status0Fields 0x00040000 -#define M_StatusRFields 0x058000e0 /* FR, MX, PX, KX, SX, UX unused in MIPS32 */ -#define M_Status0Fields64 0x00040000 -#define M_StatusRFields64 0x00000000 - -/* - * Values in the KSU field - */ -#define K_StatusKSU_U 2 /* User mode in KSU field */ -#define K_StatusKSU_S 1 /* Supervisor mode in KSU field */ -#define K_StatusKSU_K 0 /* Kernel mode in KSU field */ - - -/* - ************************************************************************ - * C A U S E R E G I S T E R ( 1 3 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |B| | C | |I|W| |I|I|I|I|I|I|I|I| | | R | - * |D| | E | Rsvd |V|P| Rsvd |P|P|P|P|P|P|P|P| | ExcCode | s | Cause - * | | | | | | | |7|6|5|4|3|2|1|0| | | v | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Cause $13 -#define R_C0_Cause 13 -#define C0_CAUSE C0_Cause /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_CauseBD 31 -#define M_CauseBD (0x1 << S_CauseBD) -#define S_CauseCE 28 -#define M_CauseCE (0x3<< S_CauseCE) -#define S_CauseIV 23 -#define M_CauseIV (0x1 << S_CauseIV) -#define S_CauseWP 22 -#define M_CauseWP (0x1 << S_CauseWP) -#define S_CauseIP 8 -#define M_CauseIP (0xff << S_CauseIP) -#define S_CauseIPEXT 10 -#define M_CauseIPEXT (0x3f << S_CauseIPEXT) -#define S_CauseIP7 15 -#define M_CauseIP7 (0x1 << S_CauseIP7) -#define S_CauseIP6 14 -#define M_CauseIP6 (0x1 << S_CauseIP6) -#define S_CauseIP5 13 -#define M_CauseIP5 (0x1 << S_CauseIP5) -#define S_CauseIP4 12 -#define M_CauseIP4 (0x1 << S_CauseIP4) -#define S_CauseIP3 11 -#define M_CauseIP3 (0x1 << S_CauseIP3) -#define S_CauseIP2 10 -#define M_CauseIP2 (0x1 << S_CauseIP2) -#define S_CauseIP1 9 -#define M_CauseIP1 (0x1 << S_CauseIP1) -#define S_CauseIP0 8 -#define M_CauseIP0 (0x1 << S_CauseIP0) -#define S_CauseExcCode 2 -#define M_CauseExcCode (0x1f << S_CauseExcCode) - -#define M_Cause0Fields 0x4f3f0083 -#define M_CauseRFields 0xb000fc7c - -/* - * Values in the CE field - */ -#define K_CauseCE0 0 /* Coprocessor 0 in the CE field */ -#define K_CauseCE1 1 /* Coprocessor 1 in the CE field */ -#define K_CauseCE2 2 /* Coprocessor 2 in the CE field */ -#define K_CauseCE3 3 /* Coprocessor 3 in the CE field */ - -/* - * Values in the ExcCode field - */ -#define EX_INT 0 /* Interrupt */ -#define EXC_INT (EX_INT << S_CauseExcCode) -#define EX_MOD 1 /* TLB modified */ -#define EXC_MOD (EX_MOD << S_CauseExcCode) -#define EX_TLBL 2 /* TLB exception (load or ifetch) */ -#define EXC_TLBL (EX_TLBL << S_CauseExcCode) -#define EX_TLBS 3 /* TLB exception (store) */ -#define EXC_TLBS (EX_TLBS << S_CauseExcCode) -#define EX_ADEL 4 /* Address error (load or ifetch) */ -#define EXC_ADEL (EX_ADEL << S_CauseExcCode) -#define EX_ADES 5 /* Address error (store) */ -#define EXC_ADES (EX_ADES << S_CauseExcCode) -#define EX_IBE 6 /* Instruction Bus Error */ -#define EXC_IBE (EX_IBE << S_CauseExcCode) -#define EX_DBE 7 /* Data Bus Error */ -#define EXC_DBE (EX_DBE << S_CauseExcCode) -#define EX_SYS 8 /* Syscall */ -#define EXC_SYS (EX_SYS << S_CauseExcCode) -#define EX_SYSCALL EX_SYS -#define EXC_SYSCALL EXC_SYS -#define EX_BP 9 /* Breakpoint */ -#define EXC_BP (EX_BP << S_CauseExcCode) -#define EX_BREAK EX_BP -#define EXC_BREAK EXC_BP -#define EX_RI 10 /* Reserved instruction */ -#define EXC_RI (EX_RI << S_CauseExcCode) -#define EX_CPU 11 /* CoProcessor Unusable */ -#define EXC_CPU (EX_CPU << S_CauseExcCode) -#define EX_OV 12 /* OVerflow */ -#define EXC_OV (EX_OV << S_CauseExcCode) -#define EX_TR 13 /* Trap instruction */ -#define EXC_TR (EX_TR << S_CauseExcCode) -#define EX_TRAP EX_TR -#define EXC_TRAP EXC_TR -#define EX_FPE 15 /* floating point exception */ -#define EXC_FPE (EX_FPE << S_CauseExcCode) -#define EX_C2E 18 /* COP2 exception */ -#define EXC_C2E (EX_C2E << S_CauseExcCode) -#define EX_MDMX 22 /* MDMX exception */ -#define EXC_MDMX (EX_MDMX << S_CauseExcCode) -#define EX_WATCH 23 /* Watch exception */ -#define EXC_WATCH (EX_WATCH << S_CauseExcCode) -#define EX_MCHECK 24 /* Machine check exception */ -#define EXC_MCHECK (EX_MCHECK << S_CauseExcCode) -#define EX_CacheErr 30 /* Cache error caused re-entry to Debug Mode */ -#define EXC_CacheErr (EX_CacheErr << S_CauseExcCode) - - -/* - ************************************************************************ - * E P C R E G I S T E R ( 1 4 ) * - ************************************************************************ - * - * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | // Exception PC | EPC - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_EPC $14 -#define R_C0_EPC 14 - -#define M_EPC0Fields 0x00000000 -#define M_EPCRFields 0x00000000 -#define M_EPC0Fields64 UNS64Const(0x0000000000000000) -#define M_EPCRFields64 UNS64Const(0x0000000000000000) - -/* - ************************************************************************ - * P R I D R E G I S T E R ( 1 5 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Company Opts | Company ID | Procesor ID | Revision | PRId - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_PRId $15 -#define R_C0_PRId 15 -#define C0_PRID C0_PRID /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_PRIdCoOpt 24 /* Company options (R) */ -#define M_PRIdCoOpt (0xff << S_PRIdCoOpt) -#define S_PRIdCoID 16 /* Company ID (R) */ -#define M_PRIdCoID (0xff << S_PRIdCoID) -#define S_PRIdImp 8 /* Implementation ID (R) */ -#define M_PRIdImp (0xff << S_PRIdImp) -#define S_PRIdRev 0 /* Revision (R) */ -#define M_PRIdRev (0xff << S_PRIdRev) - -#define M_PRId0Fields 0x00000000 -#define M_PRIdRFields 0xffffffff -/* - * Values in the Company ID field - */ -#define K_PRIdCoID_MIPS 1 -#define K_PRIdCoID_Broadcom 2 -#define K_PRIdCoID_Alchemy 3 -#define K_PRIdCoID_SiByte 4 -#define K_PRIdCoID_SandCraft 5 -#define K_PRIdCoID_Philips 6 -#define K_PRIdCoID_NextAvailable 7 /* Next available encoding */ - - -/* - * Values in the implementation number field - */ -#define K_PRIdImp_Jade 0x80 -#define K_PRIdImp_Opal 0x81 -#define K_PRIdImp_Ruby 0x82 -#define K_PRIdImp_JadeLite 0x83 -#define K_PRIdImp_4KEc 0x84 /* Emerald with TLB MMU */ -#define K_PRIdImp_4KEmp 0x85 /* Emerald with FM MMU */ -#define K_PRIdImp_4KSc 0x86 /* Coral */ - -#define K_PRIdImp_R3000 0x01 -#define K_PRIdImp_R4000 0x04 -#define K_PRIdImp_R10000 0x09 -#define K_PRIdImp_R4300 0x0b -#define K_PRIdImp_R5000 0x23 -#define K_PRIdImp_R5200 0x28 -#define K_PRIdImp_R5400 0x54 - -/* - ************************************************************************ - * C O N F I G R E G I S T E R ( 1 6 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |M| |B| A | A | | K | Config - * | | Reserved for Implementations|E| T | R | Reserved | 0 | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Config $16 -#define R_C0_Config 16 -#define C0_CONFIG C0_Config /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_ConfigMore 31 /* Additional config registers present (R) */ -#define M_ConfigMore (0x1 << S_ConfigMore) -#define S_ConfigImpl 16 /* Implementation-specific fields */ -#define M_ConfigImpl (0x7fff << S_ConfigImpl) -#define S_ConfigBE 15 /* Denotes big-endian operation (R) */ -#define M_ConfigBE (0x1 << S_ConfigBE) -#define S_ConfigAT 13 /* Architecture type (R) */ -#define M_ConfigAT (0x3 << S_ConfigAT) -#define S_ConfigAR 10 /* Architecture revision (R) */ -#define M_ConfigAR (0x7 << S_ConfigAR) -#define S_ConfigMT 7 /* MMU Type (R) */ -#define M_ConfigMT (0x7 << S_ConfigMT) -#define S_ConfigK0 0 /* Kseg0 coherency algorithm (R/W) */ -#define M_ConfigK0 (0x7 << S_ConfigK0) - -/* - * The following definitions are technically part of the "reserved for - * implementations" field, but are the semi-standard definition used in - * fixed-mapping MMUs to control the cacheability of kuseg and kseg2/3 - * references. For that reason, they are included here, but may be - * overridden by true implementation-specific definitions - */ -#define S_ConfigK23 28 /* Kseg2/3 coherency algorithm (FM MMU only) (R/W) */ -#define M_ConfigK23 (0x7 << S_ConfigK23) -#define S_ConfigKU 25 /* Kuseg coherency algorithm (FM MMU only) (R/W) */ -#define M_ConfigKU (0x7 << S_ConfigKU) - -#define M_Config0Fields 0x00000078 -#define M_ConfigRFields 0x8000ff80 - -/* - * Values in the AT field - */ -#define K_ConfigAT_MIPS32 0 /* MIPS32 */ -#define K_ConfigAT_MIPS64S 1 /* MIPS64 with 32-bit addresses */ -#define K_ConfigAT_MIPS64 2 /* MIPS64 with 32/64-bit addresses */ - -/* - * Values in the MT field - */ -#define K_ConfigMT_NoMMU 0 /* No MMU */ -#define K_ConfigMT_TLBMMU 1 /* Standard TLB MMU */ -#define K_ConfigMT_BATMMU 2 /* Standard BAT MMU */ -#define K_ConfigMT_FMMMU 3 /* Standard Fixed Mapping MMU */ - - -/* - ************************************************************************ - * C O N F I G 1 R E G I S T E R ( 1 6, SELECT 1 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |M| MMU Size | IS | IL | IA | DS | DL | DA |C|M|P|W|C|E|F| Config1 - * | | | | | | | | |2|D|C|R|A|P|P| - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Config1 $16,1 -#define R_C0_Config1 16 - -#define S_Config1More 31 /* Additional Config registers present (R) */ -#define M_Config1More (0x1 << S_Config1More) -#define S_Config1MMUSize 25 /* Number of MMU entries - 1 (R) */ -#define M_Config1MMUSize (0x3f << S_Config1MMUSize) -#define S_Config1IS 22 /* Icache sets per way (R) */ -#define M_Config1IS (0x7 << S_Config1IS) -#define S_Config1IL 19 /* Icache line size (R) */ -#define M_Config1IL (0x7 << S_Config1IL) -#define S_Config1IA 16 /* Icache associativity - 1 (R) */ -#define M_Config1IA (0x7 << S_Config1IA) -#define S_Config1DS 13 /* Dcache sets per way (R) */ -#define M_Config1DS (0x7 << S_Config1DS) -#define S_Config1DL 10 /* Dcache line size (R) */ -#define M_Config1DL (0x7 << S_Config1DL) -#define S_Config1DA 7 /* Dcache associativity (R) */ -#define M_Config1DA (0x7 << S_Config1DA) -#define S_Config1C2 6 /* Coprocessor 2 present (R) */ -#define M_Config1C2 (0x1 << S_Config1C2) -#define S_Config1MD 5 /* Denotes MDMX present (R) */ -#define M_Config1MD (0x1 << S_Config1MD) -#define S_Config1PC 4 /* Denotes performance counters present (R) */ -#define M_Config1PC (0x1 << S_Config1PC) -#define S_Config1WR 3 /* Denotes watch registers present (R) */ -#define M_Config1WR (0x1 << S_Config1WR) -#define S_Config1CA 2 /* Denotes MIPS-16 present (R) */ -#define M_Config1CA (0x1 << S_Config1CA) -#define S_Config1EP 1 /* Denotes EJTAG present (R) */ -#define M_Config1EP (0x1 << S_Config1EP) -#define S_Config1FP 0 /* Denotes floating point present (R) */ -#define M_Config1FP (0x1 << S_Config1FP) - -#define M_Config10Fields 0x00000060 -#define M_Config1RFields 0x7fffff9f - -/* - * The following macro generates a table that is indexed - * by the Icache or Dcache sets field in Config1 and - * contains the decoded value of sets per way - */ -#define Config1CacheSets() \ - HALF(64); \ - HALF(128); \ - HALF(256); \ - HALF(512); \ - HALF(1024); \ - HALF(2048); \ - HALF(4096); \ - HALF(8192); - -/* - * The following macro generates a table that is indexed - * by the Icache or Dcache line size field in Config1 and - * contains the decoded value of the cache line size, in bytes - */ -#define Config1CacheLineSize() \ - HALF(0); \ - HALF(4); \ - HALF(8); \ - HALF(16); \ - HALF(32); \ - HALF(64); \ - HALF(128); \ - HALF(256); - - -/* - ************************************************************************ - * C O N F I G 2 R E G I S T E R ( 1 6, SELECT 2 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |M| | | | | | | | | | | | |S|T| Config1 - * | | | | | | | | | | | | | |M|L| - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Config2 $16,2 -#define R_C0_Config2 16 - -#define S_Config2More 31 /* Additional Config registers present (R) */ -#define M_Config2More (0x1 << S_Config2More) -#define S_Config2SM 1 /* Denotes SmartMIPS ASE present (R) */ -#define M_Config2SM (0x1 << S_Config2SM) -#define S_Config2TL 0 /* Denotes Tracing Logic present (R) */ -#define M_Config2TL (0x1 << S_Config2TL) - -#define M_Config20Fields 0xfffffffc -#define M_Config2RFields 0x00000003 - -/* - ************************************************************************ - * L L A D D R R E G I S T E R ( 1 7 ) * - ************************************************************************ - * - * 6 6 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | // LL Physical Address | LLAddr - * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_LLAddr $17 -#define R_C0_LLAddr 17 -#define C0_LLADDR C0_LLAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define M_LLAddr0Fields 0x00000000 -#define M_LLAddrRFields 0x00000000 -#define M_LLAddr0Fields64 UNS64Const(0x0000000000000000) -#define M_LLAddrRFields64 UNS64Const(0x0000000000000000) - - -/* - ************************************************************************ - * W A T C H L O R E G I S T E R ( 1 8 ) * - ************************************************************************ - * - * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | // Watch Virtual Address |I|R|W| WatchLo - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_WatchLo $18 -#define R_C0_WatchLo 18 -#define C0_WATCHLO C0_WatchLo /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_WatchLoVAddr 3 /* Watch virtual address (R/W) */ -#define M_WatchLoVAddr (0x1fffffff << S_WatchLoVAddr) -#define S_WatchLoI 2 /* Enable Istream watch (R/W) */ -#define M_WatchLoI (0x1 << S_WatchLoI) -#define S_WatchLoR 1 /* Enable data read watch (R/W) */ -#define M_WatchLoR (0x1 << S_WatchLoR) -#define S_WatchLoW 0 /* Enable data write watch (R/W) */ -#define M_WatchLoW (0x1 << S_WatchLoW) - -#define M_WatchLo0Fields 0x00000000 -#define M_WatchLoRFields 0x00000000 -#define M_WatchLo0Fields64 UNS64Const(0x0000000000000000) -#define M_WatchLoRFields64 UNS64Const(0x0000000000000000) - -#define M_WatchLoEnables (M_WatchLoI | M_WatchLoR | M_WatchLoW) - - -/* - ************************************************************************ - * W A T C H H I R E G I S T E R ( 1 9 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |M|G| Rsvd | ASID | Rsvd | Mask | 0 | WatchHi - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_WatchHi $19 -#define R_C0_WatchHi 19 -#define C0_WATCHHI C0_WatchHi /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_WatchHiM 31 /* Denotes additional Watch registers present (R) */ -#define M_WatchHiM (0x1 << S_WatchHiM) -#define S_WatchHiG 30 /* Enable ASID-independent Watch match (R/W) */ -#define M_WatchHiG (0x1 << S_WatchHiG) -#define S_WatchHiASID 16 /* ASID value to match (R/W) */ -#define M_WatchHiASID (0xff << S_WatchHiASID) -#define S_WatchHiMask 3 /* Address inhibit mask (R/W) */ -#define M_WatchHiMask (0x1ff << S_WatchHiMask) - -#define M_WatchHi0Fields 0x3f00f007 -#define M_WatchHiRFields 0x80000000 - - -/* - ************************************************************************ - * X C O N T E X T R E G I S T E R ( 2 0 ) * - ************************************************************************ - * - * 6 // 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 // 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | // PTEBase | R | BadVPN2<39:13> | 0 | XContext - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_XContext $20 -#define R_C0_XContext 20 -#define C0_EXTCTXT C0_XContext /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_XContextBadVPN2 4 /* BadVPN2 (R) */ -#define S_XContextBadVPN S_XContextBadVPN2 - -#define M_XContext0Fields 0x0000000f - - -/* - ************************************************************************ - * D E B U G R E G I S T E R ( 2 3 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |D|D|N|L|D|H|C|I|M|C|D|I|D|D| | |N|S| |D|D|D|D|D|D| - * |B|M|o|S|o|a|o|B|C|a|B|E|D|D|EJTAG|DExcCode |o|S| |I|I|D|D|B|S| - * |D| |D|N|z|l|u|u|h|c|u|X|B|B| ver | |S|t| |N|B|B|B|p|S| - * | | |C|M|e|t|n|s|e|h|s|I|S|L| | |S| | 0 |T| |S|L| | | Debug - * | | |R| | | |t|E|c|e|E| |I|I| | |t| | | | | | | | | - * | | | | | | |D|P|k|E|P| |m|m| | | | | | | | | | | | - * | | | | | | |M| |P|P| | |p|p| | | | | | | | | | | | - * | | | | | | | | | | | | |r|r| | | | | | | | | | | | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Debug $23 /* EJTAG */ -#define R_C0_Debug 23 - -#define S_DebugDBD 31 /* Debug branch delay (R) */ -#define M_DebugDBD (0x1 << S_DebugDBD) -#define S_DebugDM 30 /* Debug mode (R) */ -#define M_DebugDM (0x1 << S_DebugDM) -#define S_DebugNoDCR 29 /* No debug control register present (R) */ -#define M_DebugNoDCR (0x1 << S_DebugNoDCR) -#define S_DebugLSNM 28 /* Load/Store Normal Memory (R/W) */ -#define M_DebugLSNM (0x1 << S_DebugLSNM) -#define S_DebugDoze 27 /* Doze (R) */ -#define M_DebugDoze (0x1 << S_DebugDoze) -#define S_DebugHalt 26 /* Halt (R) */ -#define M_DebugHalt (0x1 << S_DebugHalt) -#define S_DebugCountDM 25 /* Count register behavior in debug mode (R/W) */ -#define M_DebugCountDM (0x1 << S_DebugCountDM) -#define S_DebugIBusEP 24 /* Imprecise Instn Bus Error Pending (R/W) */ -#define M_DebugIBusEP (0x1 << S_DebugIBusEP) -#define S_DebugMCheckP 23 /* Imprecise Machine Check Pending (R/W) */ -#define M_DebugMCheckP (0x1 << S_DebugMCheckP) -#define S_DebugCacheEP 22 /* Imprecise Cache Error Pending (R/W) */ -#define M_DebugCacheEP (0x1 << S_DebugCacheEP) -#define S_DebugDBusEP 21 /* Imprecise Data Bus Error Pending (R/W) */ -#define M_DebugDBusEP (0x1 << S_DebugDBusEP) -#define S_DebugIEXI 20 /* Imprecise Exception Inhibit (R/W) */ -#define M_DebugIEXI (0x1 << S_DebugIEXI) -#define S_DebugDDBSImpr 19 /* Debug data break store imprecise (R) */ -#define M_DebugDDBSImpr (0x1 << S_DebugDDBSImpr) -#define S_DebugDDBLImpr 18 /* Debug data break load imprecise (R) */ -#define M_DebugDDBLImpr (0x1 << S_DebugDDBLImpr) -#define S_DebugEJTAGver 15 /* EJTAG version number (R) */ -#define M_DebugEJTAGver (0x7 << S_DebugEJTAGver) -#define S_DebugDExcCode 10 /* Debug exception code (R) */ -#define M_DebugDExcCode (0x1f << S_DebugDExcCode) -#define S_DebugNoSSt 9 /* No single step implemented (R) */ -#define M_DebugNoSSt (0x1 << S_DebugNoSSt) -#define S_DebugSSt 8 /* Single step enable (R/W) */ -#define M_DebugSSt (0x1 << S_DebugSSt) -#define S_DebugDINT 5 /* Debug interrupt (R) */ -#define M_DebugDINT (0x1 << S_DebugDINT) -#define S_DebugDIB 4 /* Debug instruction break (R) */ -#define M_DebugDIB (0x1 << S_DebugDIB) -#define S_DebugDDBS 3 /* Debug data break store (R) */ -#define M_DebugDDBS (0x1 << S_DebugDDBS) -#define S_DebugDDBL 2 /* Debug data break load (R) */ -#define M_DebugDDBL (0x1 << S_DebugDDBL) -#define S_DebugDBp 1 /* Debug breakpoint (R) */ -#define M_DebugDBp (0x1 << S_DebugDBp) -#define S_DebugDSS 0 /* Debug single step (R) */ -#define M_DebugDSS (0x1 << S_DebugDSS) - -#define M_Debug0Fields 0x01f000c0 -#define M_DebugRFields 0xec0ffe3f - - -/* - ************************************************************************ - * D E P C R E G I S T E R ( 2 4 ) * - ************************************************************************ - * - * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | // EJTAG Debug Exception PC | DEPC - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - - -#define C0_DEPC $24 -#define R_C0_DEPC 24 - -#define M_DEEPC0Fields 0x00000000 -#define M_DEEPCRFields 0x00000000 -#define M_DEEPC0Fields64 UNS64Const(0x0000000000000000) -#define M_DEEPCRFields64 UNS64Const(0x0000000000000000) - - -/* - ************************************************************************ - * P E R F C N T R E G I S T E R ( 2 5 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | | | |I| | | |E| - * |M| 0 | Event |E|U|S|K|X| PerfCnt - * | | | | | | | |L| - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Event Count | PerfCnt - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_PerfCnt $25 -#define R_C0_PerfCnt 25 -#define C0_PRFCNT0 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define C0_PRFCNT1 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_PerfCntM 31 /* More performance counters exist (R) */ -#define M_PerfCntM (1 << S_PerfCntM) -#define S_PerfCntEvent 5 /* Enabled event (R/W) */ -#define M_PerfCntEvent (0x3f << S_PerfCntEvent) -#define S_PerfCntIE 4 /* Interrupt Enable (R/W) */ -#define M_PerfCntIE (1 << S_PerfCntIE) -#define S_PerfCntU 3 /* Enable counting in User Mode (R/W) */ -#define M_PerfCntU (1 << S_PerfCntU) -#define S_PerfCntS 2 /* Enable counting in Supervisor Mode (R/W) */ -#define M_PerfCntS (1 << S_PerfCntS) -#define S_PerfCntK 1 /* Enable counting in Kernel Mode (R/W) */ -#define M_PerfCntK (1 << S_PerfCntK) -#define S_PerfCntEXL 0 /* Enable counting while EXL==1 (R/W) */ -#define M_PerfCntEXL (1 << S_PerfCntEXL) - -#define M_PerfCnt0Fields 0x7ffff800 -#define M_PerfCntRFields 0x80000000 - - -/* - ************************************************************************ - * E R R C T L R E G I S T E R ( 2 6 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Error Control | ErrCtl - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_ErrCtl $26 -#define R_C0_ErrCtl 26 -#define C0_ECC $26 /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define R_C0_ECC 26 /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define M_ErrCtl0Fields 0x00000000 -#define M_ErrCtlRFields 0x00000000 - - -/* - ************************************************************************ - * C A C H E E R R R E G I S T E R ( 2 7 ) * CacheErr - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Cache Error Control | CacheErr - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_CacheErr $27 -#define R_C0_CacheErr 27 -#define C0_CACHE_ERR C0_CacheErr /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define M_CacheErr0Fields 0x00000000 -#define M_CachErrRFields 0x00000000 - - -/* - ************************************************************************ - * T A G L O R E G I S T E R ( 2 8 ) * TagLo - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | TagLo | TagLo - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_TagLo $28 -#define R_C0_TagLo 28 -#define C0_TAGLO C0_TagLo /* OBSOLETE - DO NOT USE IN NEW CODE */ - -/* - * Some implementations use separate TagLo registers for the - * instruction and data caches. In those cases, the following - * definitions can be used in relevant code - */ - -#define C0_ITagLo $28,0 -#define C0_DTagLo $28,2 - -#define M_TagLo0Fields 0x00000000 -#define M_TagLoRFields 0x00000000 - - -/* - ************************************************************************ - * D A T A L O R E G I S T E R ( 2 8, SELECT 1 ) * DataLo - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | DataLo | DataLo - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_DataLo $28,1 -#define R_C0_DataLo 28 - -/* - * Some implementations use separate DataLo registers for the - * instruction and data caches. In those cases, the following - * definitions can be used in relevant code - */ - -#define C0_IDataLo $28,1 -#define C0_DDataLo $28,3 - -#define M_DataLo0Fields 0x00000000 -#define M_DataLoRFields 0xffffffff - - -/* - ************************************************************************ - * T A G H I R E G I S T E R ( 2 9 ) * TagHi - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | TagHi | TagHi - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_TagHi $29 -#define R_C0_TagHi 29 -#define C0_TAGHI C0_TagHi /* OBSOLETE - DO NOT USE IN NEW CODE */ - -/* - * Some implementations use separate TagHi registers for the - * instruction and data caches. In those cases, the following - * definitions can be used in relevant code - */ - -#define C0_ITagHi $29,0 -#define C0_DTagHi $29,2 - -#define M_TagHi0Fields 0x00000000 -#define M_TagHiRFields 0x00000000 - - -/* - ************************************************************************ - * D A T A H I R E G I S T E R ( 2 9, SELECT 1 ) * DataHi - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | DataHi | DataHi - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_DataHi $29,1 -#define R_C0_DataHi 29 - -/* - * Some implementations use separate DataHi registers for the - * instruction and data caches. In those cases, the following - * definitions can be used in relevant code - */ - -#define C0_IDataHi $29,1 -#define C0_DDataHi $29,3 - -#define M_DataHi0Fields 0x00000000 -#define M_DataHiRFields 0xffffffff - - -/* - ************************************************************************ - * E R R O R E P C R E G I S T E R ( 3 0 ) * - ************************************************************************ - * - * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | // Error PC | ErrorEPC - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_ErrorEPC $30 -#define R_C0_ErrorEPC 30 -#define C0_ERROR_EPC C0_ErrorEPC /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define M_ErrorEPC0Fields 0x00000000 -#define M_ErrorEPCRFields 0x00000000 -#define M_ErrorEPC0Fields64 UNS64Const(0x0000000000000000) -#define M_ErrorEPCRFields64 UNS64Const(0x0000000000000000) - - -/* - ************************************************************************ - * D E S A V E R E G I S T E R ( 3 1 ) * - ************************************************************************ - * - * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | // EJTAG Register Save Value | DESAVE - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_DESAVE $31 -#define R_C0_DESAVE 31 - -#define M_DESAVE0Fields 0x00000000 -#define M_DESAVERFields 0x00000000 -#define M_DESAVE0Fields64 UNS64Const(0x0000000000000000) -#define M_DESAVERFields64 UNS64Const(0x0000000000000000) - - -/* - ************************************************************************* - * C P 1 R E G I S T E R D E F I N I T I O N S * - ************************************************************************* - */ - - -/* - ************************************************************************* - * H A R D W A R E F P R N A M E S * - ************************************************************************* - */ - -#define fp0 $f0 -#define fp1 $f1 -#define fp2 $f2 -#define fp3 $f3 -#define fp4 $f4 -#define fp5 $f5 -#define fp6 $f6 -#define fp7 $f7 -#define fp8 $f8 -#define fp9 $f9 -#define fp10 $f10 -#define fp11 $f11 -#define fp12 $f12 -#define fp13 $f13 -#define fp14 $f14 -#define fp15 $f15 -#define fp16 $f16 -#define fp17 $f17 -#define fp18 $f18 -#define fp19 $f19 -#define fp20 $f20 -#define fp21 $f21 -#define fp22 $f22 -#define fp23 $f23 -#define fp24 $f24 -#define fp25 $f25 -#define fp26 $f26 -#define fp27 $f27 -#define fp28 $f28 -#define fp29 $f29 -#define fp30 $f30 -#define fp31 $f31 - -/* - * The following definitions are used to convert an FPR name - * into the corresponding even or odd name, respectively. - * This is used in macro substitution in the AVPs. - */ - -#define fp1_even $f0 -#define fp3_even $f2 -#define fp5_even $f4 -#define fp7_even $f6 -#define fp9_even $f8 -#define fp11_even $f10 -#define fp13_even $f12 -#define fp15_even $f14 -#define fp17_even $f16 -#define fp19_even $f18 -#define fp21_even $f20 -#define fp23_even $f22 -#define fp25_even $f24 -#define fp27_even $f26 -#define fp29_even $f28 -#define fp31_even $f30 - -#define fp0_odd $f1 -#define fp2_odd $f3 -#define fp4_odd $f5 -#define fp6_odd $f7 -#define fp8_odd $f9 -#define fp10_odd $f11 -#define fp12_odd $f13 -#define fp14_odd $f15 -#define fp16_odd $f17 -#define fp18_odd $f19 -#define fp20_odd $f21 -#define fp22_odd $f23 -#define fp24_odd $f25 -#define fp26_odd $f27 -#define fp28_odd $f29 -#define fp30_odd $f31 - - -/* - ************************************************************************* - * H A R D W A R E F P R I N D I C E S * - ************************************************************************* - * - * These definitions provide the index (number) of the FPR, as opposed - * to the assembler register name ($n). - */ - -#define R_fp0 0 -#define R_fp1 1 -#define R_fp2 2 -#define R_fp3 3 -#define R_fp4 4 -#define R_fp5 5 -#define R_fp6 6 -#define R_fp7 7 -#define R_fp8 8 -#define R_fp9 9 -#define R_fp10 10 -#define R_fp11 11 -#define R_fp12 12 -#define R_fp13 13 -#define R_fp14 14 -#define R_fp15 15 -#define R_fp16 16 -#define R_fp17 17 -#define R_fp18 18 -#define R_fp19 19 -#define R_fp20 20 -#define R_fp21 21 -#define R_fp22 22 -#define R_fp23 23 -#define R_fp24 24 -#define R_fp25 25 -#define R_fp26 26 -#define R_fp27 27 -#define R_fp28 28 -#define R_fp29 29 -#define R_fp30 30 -#define R_fp31 31 - - -/* - ************************************************************************* - * H A R D W A R E F C R N A M E S * - ************************************************************************* - */ - -#define fc0 $0 -#define fc25 $25 -#define fc26 $26 -#define fc28 $28 -#define fc31 $31 - - -/* - ************************************************************************* - * H A R D W A R E F C R I N D I C E S * - ************************************************************************* - * - * These definitions provide the index (number) of the FCR, as opposed - * to the assembler register name ($n). - */ - -#define R_fc0 0 -#define R_fc25 25 -#define R_fc26 26 -#define R_fc28 28 -#define R_fc31 31 - - -/* - ************************************************************************* - * H A R D W A R E F C C N A M E S * - ************************************************************************* - */ - -#define cc0 $fcc0 -#define cc1 $fcc1 -#define cc2 $fcc2 -#define cc3 $fcc3 -#define cc4 $fcc4 -#define cc5 $fcc5 -#define cc6 $fcc6 -#define cc7 $fcc7 - - -/* - ************************************************************************* - * H A R D W A R E F C C I N D I C E S * - ************************************************************************* - * - * These definitions provide the index (number) of the CC, as opposed - * to the assembler register name ($n). - */ - -#define R_cc0 0 -#define R_cc1 1 -#define R_cc2 2 -#define R_cc3 3 -#define R_cc4 4 -#define R_cc5 5 -#define R_cc6 6 -#define R_cc7 7 - - -/* - ************************************************************************ - * I M P L E M E N T A T I O N R E G I S T E R * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |Reserved for Additional|3|P|D|S| Implementation| Revision | FIR - * | Configuration Bits |D|S| | | | | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C1_FIR $0 -#define R_C1_FIR 0 - -#define S_FIRConfigS 16 -#define M_FIRConfigS (0x1 << S_FIRConfigS) -#define S_FIRConfigD 17 -#define M_FIRConfigD (0x1 << S_FIRConfigD) -#define S_FIRConfigPS 18 -#define M_FIRConfigPS (0x1 << S_FIRConfigPS) -#define S_FIRConfig3D 19 -#define M_FIRConfig3D (0x1 << S_FIRConfig3D) -#define M_FIRConfigAll (M_FIRConfigS|M_FIRConfigD|M_FIRConfigPS|M_FIRConfig3D) - -#define S_FIRImp 8 -#define M_FIRImp (0xff << S_FIRImp) - -#define S_FIRRev 0 -#define M_FIRRev (0xff << S_FIRRev) - -#define M_FIR0Fields 0xfff00000 -#define M_FIRRFields 0x000fffff - -/* - ************************************************************************ - * C O N D I T I O N C O D E S R E G I S T E R * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | 0 | CC | FCCR - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C1_FCCR $25 -#define R_C1_FCCR 25 - -#define S_FCCRCC 0 -#define M_FCCRCC (0xff << S_FCCRCC) -#define S_FCCRCC7 7 -#define M_FCCRCC7 (0x1 << S_FCCRCC7) -#define S_FCCRCC6 6 -#define M_FCCRCC6 (0x1 << S_FCCRCC6) -#define S_FCCRCC5 5 -#define M_FCCRCC5 (0x1 << S_FCCRCC5) -#define S_FCCRCC4 4 -#define M_FCCRCC4 (0x1 << S_FCCRCC4) -#define S_FCCRCC3 3 -#define M_FCCRCC3 (0x1 << S_FCCRCC3) -#define S_FCCRCC2 2 -#define M_FCCRCC2 (0x1 << S_FCCRCC2) -#define S_FCCRCC1 1 -#define M_FCCRCC1 (0x1 << S_FCCRCC1) -#define S_FCCRCC0 0 -#define M_FCCRCC0 (0x1 << S_FCCRCC0) - -#define M_FCCR0Fields 0xffffff00 -#define M_FCCRRFields 0x000000ff - - -/* - ************************************************************************ - * E X C E P T I O N S R E G I S T E R * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | 0 | Cause | 0 | Flags | 0 | FEXR - * | |E|V|Z|O|U|I| |V|Z|O|U|I| | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C1_FEXR $26 -#define R_C1_FEXR 26 - -#define S_FEXRExc 12 -#define M_FEXRExc (0x3f << S_FEXRExc) -#define S_FEXRExcE 17 -#define M_FEXRExcE (0x1 << S_FEXRExcE) -#define S_FEXRExcV 16 -#define M_FEXRExcV (0x1 << S_FEXRExcV) -#define S_FEXRExcZ 15 -#define M_FEXRExcZ (0x1 << S_FEXRExcZ) -#define S_FEXRExcO 14 -#define M_FEXRExcO (0x1 << S_FEXRExcO) -#define S_FEXRExcU 13 -#define M_FEXRExcU (0x1 << S_FEXRExcU) -#define S_FEXRExcI 12 -#define M_FEXRExcI (0x1 << S_FEXRExcI) - -#define S_FEXRFlg 2 -#define M_FEXRFlg (0x1f << S_FEXRFlg) -#define S_FEXRFlgV 6 -#define M_FEXRFlgV (0x1 << S_FEXRFlgV) -#define S_FEXRFlgZ 5 -#define M_FEXRFlgZ (0x1 << S_FEXRFlgZ) -#define S_FEXRFlgO 4 -#define M_FEXRFlgO (0x1 << S_FEXRFlgO) -#define S_FEXRFlgU 3 -#define M_FEXRFlgU (0x1 << S_FEXRFlgU) -#define S_FEXRFlgI 2 -#define M_FEXRFlgI (0x1 << S_FEXRFlgI) - -#define M_FEXR0Fields 0xfffc0f83 -#define M_FEXRRFields 0x00000000 - - -/* - ************************************************************************ - * E N A B L E S R E G I S T E R * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | 0 | Enables | 0 |F|RM | FENR - * | |V|Z|O|U|I| |S| | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C1_FENR $28 -#define R_C1_FENR 28 - -#define S_FENREna 7 -#define M_FENREna (0x1f << S_FENREna) -#define S_FENREnaV 11 -#define M_FENREnaV (0x1 << S_FENREnaV) -#define S_FENREnaZ 10 -#define M_FENREnaZ (0x1 << S_FENREnaZ) -#define S_FENREnaO 9 -#define M_FENREnaO (0x1 << S_FENREnaO) -#define S_FENREnaU 8 -#define M_FENREnaU (0x1 << S_FENREnaU) -#define S_FENREnaI 7 -#define M_FENREnaI (0x1 << S_FENREnaI) - -#define S_FENRFS 2 -#define M_FENRFS (0x1 << S_FENRFS) - -#define S_FENRRM 0 -#define M_FENRRM (0x3 << S_FENRRM) - -#define M_FENR0Fields 0xfffff078 -#define M_FENRRFields 0x00000000 - - -/* - ************************************************************************ - * C O N T R O L / S T A T U S R E G I S T E R * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | FCC |F|C|Imp| 0 | Cause | Enables | Flags | RM| FCSR - * |7|6|5|4|3|2|1|S|C| | |E|V|Z|O|U|I|V|Z|O|U|I|V|Z|O|U|I| | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C1_FCSR $31 -#define R_C1_FCSR 31 - -#define S_FCSRFCC7_1 25 /* Floating point condition codes 7..1 (R/W) */ -#define M_FCSRFCC7_1 (0x7f << S_FCSRFCC7_1) -#define S_FCSRCC7 31 -#define M_FCSRCC7 (0x1 << S_FCSRCC7) -#define S_FCSRCC6 30 -#define M_FCSRCC6 (0x1 << S_FCSRCC6) -#define S_FCSRCC5 29 -#define M_FCSRCC5 (0x1 << S_FCSRCC5) -#define S_FCSRCC4 28 -#define M_FCSRCC4 (0x1 << S_FCSRCC4) -#define S_FCSRCC3 27 -#define M_FCSRCC3 (0x1 << S_FCSRCC3) -#define S_FCSRCC2 26 -#define M_FCSRCC2 (0x1 << S_FCSRCC2) -#define S_FCSRCC1 25 -#define M_FCSRCC1 (0x1 << S_FCSRCC1) - -#define S_FCSRFS 24 /* Flush denorms to zero (R/W) */ -#define M_FCSRFS (0x1 << S_FCSRFS) - -#define S_FCSRCC0 23 /* Floating point condition code 0 (R/W) */ -#define M_FCSRCC0 (0x1 << S_FCSRCC0) -#define S_FCSRCC S_FCSRCC0 -#define M_FCSRCC M_FCSRCC0 - -#define S_FCSRImpl 21 /* Implementation-specific control bits (R/W) */ -#define M_FCSRImpl (0x3 << S_FCSRImpl) - -#define S_FCSRExc 12 /* Exception cause (R/W) */ -#define M_FCSRExc (0x3f << S_FCSRExc) -#define S_FCSRExcE 17 -#define M_FCSRExcE (0x1 << S_FCSRExcE) -#define S_FCSRExcV 16 -#define M_FCSRExcV (0x1 << S_FCSRExcV) -#define S_FCSRExcZ 15 -#define M_FCSRExcZ (0x1 << S_FCSRExcZ) -#define S_FCSRExcO 14 -#define M_FCSRExcO (0x1 << S_FCSRExcO) -#define S_FCSRExcU 13 -#define M_FCSRExcU (0x1 << S_FCSRExcU) -#define S_FCSRExcI 12 -#define M_FCSRExcI (0x1 << S_FCSRExcI) - -#define S_FCSREna 7 /* Exception enable (R/W) */ -#define M_FCSREna (0x1f << S_FCSREna) -#define S_FCSREnaV 11 -#define M_FCSREnaV (0x1 << S_FCSREnaV) -#define S_FCSREnaZ 10 -#define M_FCSREnaZ (0x1 << S_FCSREnaZ) -#define S_FCSREnaO 9 -#define M_FCSREnaO (0x1 << S_FCSREnaO) -#define S_FCSREnaU 8 -#define M_FCSREnaU (0x1 << S_FCSREnaU) -#define S_FCSREnaI 7 -#define M_FCSREnaI (0x1 << S_FCSREnaI) - -#define S_FCSRFlg 2 /* Exception flags (R/W) */ -#define M_FCSRFlg (0x1f << S_FCSRFlg) -#define S_FCSRFlgV 6 -#define M_FCSRFlgV (0x1 << S_FCSRFlgV) -#define S_FCSRFlgZ 5 -#define M_FCSRFlgZ (0x1 << S_FCSRFlgZ) -#define S_FCSRFlgO 4 -#define M_FCSRFlgO (0x1 << S_FCSRFlgO) -#define S_FCSRFlgU 3 -#define M_FCSRFlgU (0x1 << S_FCSRFlgU) -#define S_FCSRFlgI 2 -#define M_FCSRFlgI (0x1 << S_FCSRFlgI) - -#define S_FCSRRM 0 /* Rounding mode (R/W) */ -#define M_FCSRRM (0x3 << S_FCSRRM) - -#define M_FCSR0Fields 0x001c0000 -#define M_FCSRRFields 0x00000000 - -/* - * Values in the rounding mode field (of both FCSR and FCCR) - */ -#define K_FCSRRM_RN 0 -#define K_FCSRRM_RZ 1 -#define K_FCSRRM_RP 2 -#define K_FCSRRM_RM 3 - -#endif /* _COMMON_MIPS_DEF_H_ */ diff --git a/libcpu/mips/common/mips_excpt.h b/libcpu/mips/common/mips_excpt.h deleted file mode 100644 index 868b046d3c..0000000000 --- a/libcpu/mips/common/mips_excpt.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * File : mips_excpt.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��7�� Urey the first version - */ - -#ifndef _MIPS_EXCPT_H_ -#define _MIPS_EXCPT_H_ - -#include "mips_regs.h" - -#ifndef __ASSEMBLY__ -typedef void (* exception_func_t)(mips_reg_ctx *regs); - -//extern exception_func_t mips_exception_handlers[]; - -int rt_hw_exception_init(void); -exception_func_t rt_set_except_vector(int n, exception_func_t func); -void install_default_execpt_handle(void); -#endif /* __ASSEMBLY__ */ -#endif /* _MIPS_EXCPT_H_ */ diff --git a/libcpu/mips/common/mips_fpu.h b/libcpu/mips/common/mips_fpu.h new file mode 100644 index 0000000000..50df3746a5 --- /dev/null +++ b/libcpu/mips/common/mips_fpu.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + */ + +#ifndef _MIPS_FPU_H_ +#define _MIPS_FPU_H_ + +#ifndef __ASSEMBLY__ + +#include <mips_regs.h> +/** + * init hardware FPU + */ +#ifdef RT_USING_FPU +rt_inline void rt_hw_fpu_init(void) +{ + rt_uint32_t c0_status = 0; + rt_uint32_t c1_status = 0; + + /* Enable CU1 */ + c0_status = read_c0_status(); + c0_status |= (ST0_CU1 | ST0_FR); + write_c0_status(c0_status); + + /* FCSR Configs */ + c1_status = read_c1_status(); + c1_status |= (FPU_CSR_FS | FPU_CSR_FO | FPU_CSR_FN); /* Set FS, FO, FN */ + c1_status &= ~(FPU_CSR_ALL_E); /* Disable exception */ + c1_status = (c1_status & (~FPU_CSR_RM)) | FPU_CSR_RN; /* Set RN */ + write_c1_status(c1_status); + + return ; +} +#else + rt_inline void rt_hw_fpu_init(void){} /* Do nothing */ +#endif + +#endif + +#endif diff --git a/libcpu/mips/common/mips_regs.h b/libcpu/mips/common/mips_regs.h index 7ea07d3869..a13e24b539 100644 --- a/libcpu/mips/common/mips_regs.h +++ b/libcpu/mips/common/mips_regs.h @@ -1,202 +1,140 @@ /* - * File : mips_regs.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2019, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2016��9��7�� Urey the first version + * 2019-12-04 Jiaxun Yang Initial version */ #ifndef _MIPS_REGS_H_ #define _MIPS_REGS_H_ +#include <rtconfig.h> +#define REG_A0 4 +#define REG_SP 29 +#define REG_GP 28 +#define REG_FP 30 +#define REG_RA 31 +#ifndef ARCH_MIPS64 +#define zero $0 /* wired zero */ +#define AT $1 /* assembler temp - uppercase because of ".set at" */ +#define v0 $2 /* return value */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 /* caller saved */ +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define ta0 $12 +#define t5 $13 +#define ta1 $13 +#define t6 $14 +#define ta2 $14 +#define t7 $15 +#define ta3 $15 +#define s0 $16 /* callee saved */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* caller saved */ +#define t9 $25 +#define jp $25 /* PIC jump register */ +#define k0 $26 /* kernel scratch */ +#define k1 $27 +#define gp $28 /* global pointer */ +#define sp $29 /* stack pointer */ +#define fp $30 /* frame pointer */ +#define s8 $30 /* same like fp! */ +#define ra $31 /* return address */ -#if !defined(__ASSEMBLY__) && !defined(ASSEMBLY) -#include <rtdef.h> - -#define MIPS_REG_NR 32 -typedef struct { - rt_uint32_t regs[MIPS_REG_NR]; /* 32 ��ͨ��Ŀ�ļĴ��� */ - rt_uint32_t CP0Status; /* CP0 Э������״̬�Ĵ��� */ - rt_uint32_t CP0DataHI; /* ������λ�Ĵ��� */ - rt_uint32_t CP0DataLO; /* ������λ�Ĵ��� */ - rt_uint32_t CP0BadVAddr; /* ������ַ�Ĵ��� */ - rt_uint32_t CP0Cause; /* �����жϻ����쳣�鿴�ļĴ���*/ - rt_uint32_t CP0EPC; /* ����������Ĵ��� */ -} mips_reg_ctx; - -#define MIPS_ARG_REG_NR 4 -typedef struct -{ - rt_uint32_t args[MIPS_ARG_REG_NR]; /* 4 �������Ĵ��� */ -} mips_arg_ctx; - -struct linkctx -{ - rt_uint32_t id; - struct linkctx *next; -}; - -struct fpctx -{ - struct linkctx link; - rt_uint32_t fcsr; - rt_uint32_t reserved; -}; - - -struct fp32ctx -{ - struct fpctx fp; - union - { - double d[16]; /* even doubles */ - float s[32]; /* even singles, padded */ - }; -}; - -struct fp64ctx -{ - struct fpctx fp; - union - { - double d[32]; /* even doubles, followed by odd doubles */ - float s[64]; /* even singles, followed by odd singles, padded */ - }; -}; - -#endif /* !defined(__ASSEMBLY__) && !defined(ASSEMBLY) */ - -#define MIPS_STK_CTX_WORD_SIZE 38 -#define SZREG 4 -/********************************************************************************************************* - MIPS �ļĴ������� -*********************************************************************************************************/ -#define REG_ZERO 0 /* wired zero */ -#define REG_AT 1 /* assembler temp */ -#define REG_V0 2 /* return reg 0 */ -#define REG_V1 3 /* return reg 1 */ -#define REG_A0 4 /* arg reg 0 */ -#define REG_A1 5 /* arg reg 1 */ -#define REG_A2 6 /* arg reg 2 */ -#define REG_A3 7 /* arg reg 3 */ -#define REG_T0 8 /* caller saved 0 */ -#define REG_T1 9 /* caller saved 1 */ -#define REG_T2 10 /* caller saved 2 */ -#define REG_T3 11 /* caller saved 3 */ -#define REG_T4 12 /* caller saved 4 */ -#define REG_T5 13 /* caller saved 5 */ -#define REG_T6 14 /* caller saved 6 */ -#define REG_T7 15 /* caller saved 7 */ -#define REG_S0 16 /* callee saved 0 */ -#define REG_S1 17 /* callee saved 1 */ -#define REG_S2 18 /* callee saved 2 */ -#define REG_S3 19 /* callee saved 3 */ -#define REG_S4 20 /* callee saved 4 */ -#define REG_S5 21 /* callee saved 5 */ -#define REG_S6 22 /* callee saved 6 */ -#define REG_S7 23 /* callee saved 7 */ -#define REG_T8 24 /* caller saved 8 */ -#define REG_T9 25 /* caller saved 9 */ -#define REG_K0 26 /* kernel temp 0 */ -#define REG_K1 27 /* kernel temp 1 */ -#define REG_GP 28 /* global pointer */ -#define REG_SP 29 /* stack pointer */ -#define REG_S8 30 /* callee saved 8 */ -#define REG_FP REG_S8 /* callee saved 8 */ -#define REG_RA 31 /* return address */ - -#define STK_CTX_SIZE (MIPS_STK_CTX_WORD_SIZE * SZREG) -#define STK_OFFSET_SR ((32 + 0) * SZREG) -#define STK_OFFSET_HI ((32 + 1) * SZREG) -#define STK_OFFSET_LO ((32 + 2) * SZREG) -#define STK_OFFSET_BADVADDR ((32 + 3) * SZREG) -#define STK_OFFSET_CAUSE ((32 + 4) * SZREG) -#define STK_OFFSET_EPC ((32 + 5) * SZREG) - -#define STK_OFFSET_LAST ((MIPS_STK_CTX_WORD_SIZE - 1) * SZREG) +#else -#define FP32CTX_CSR ((SZREG)*2) -#define FP64CTX_CSR ((SZREG)*2) +#define zero $0 /* wired zero */ +#define AT $at /* assembler temp - uppercase because of ".set at" */ +#define v0 $2 /* return value - caller saved */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */ +#define ta0 $8 +#define a5 $9 +#define ta1 $9 +#define a6 $10 +#define ta2 $10 +#define a7 $11 +#define ta3 $11 +#define t0 $12 /* caller saved */ +#define t1 $13 +#define t2 $14 +#define t3 $15 +#define s0 $16 /* callee saved */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* caller saved */ +#define t9 $25 /* callee address for PIC/temp */ +#define jp $25 /* PIC jump register */ +#define k0 $26 /* kernel temporary */ +#define k1 $27 +#define gp $28 /* global pointer - caller saved for PIC */ +#define sp $29 /* stack pointer */ +#define fp $30 /* frame pointer */ +#define s8 $30 /* callee saved */ +#define ra $31 /* return address */ -#define LINKCTX_ID ((SZREG)*0) -#define LINKCTX_NEXT ((SZREG)*1) -#define LINKCTX_TYPE_MSA 0x004D5341 -#define LINKCTX_TYPE_FP32 0x46503332 -#define LINKCTX_TYPE_FP64 0x46503634 -#define LINKCTX_TYPE_FMSA 0x463D5341 -#define LINKCTX_TYPE_DSP 0x00445350 -#define LINKCTX_TYPE_STKSWP 0x53574150 -#define LINKCTX_TYPE_XPA 0x00585041 +#endif -#define FP32CTX_0 ((SZREG)*4) -#define FP32CTX_2 (FP32CTX_0 + (1 * 8)) -#define FP32CTX_4 (FP32CTX_0 + (2 * 8)) -#define FP32CTX_6 (FP32CTX_0 + (3 * 8)) -#define FP32CTX_8 (FP32CTX_0 + (4 * 8)) -#define FP32CTX_10 (FP32CTX_0 + (5 * 8)) -#define FP32CTX_12 (FP32CTX_0 + (6 * 8)) -#define FP32CTX_14 (FP32CTX_0 + (7 * 8)) -#define FP32CTX_16 (FP32CTX_0 + (8 * 8)) -#define FP32CTX_18 (FP32CTX_0 + (9 * 8)) -#define FP32CTX_20 (FP32CTX_0 + (10 * 8)) -#define FP32CTX_22 (FP32CTX_0 + (11 * 8)) -#define FP32CTX_24 (FP32CTX_0 + (12 * 8)) -#define FP32CTX_26 (FP32CTX_0 + (13 * 8)) -#define FP32CTX_28 (FP32CTX_0 + (14 * 8)) -#define FP32CTX_30 (FP32CTX_0 + (15 * 8)) -#define FP32CTX_SIZE (FP32CTX_30 + (17 * 8)) +#define fv0 $f0 /* return value */ +#define fv0f $f1 +#define fv1 $f2 +#define fv1f $f3 +#define fa0 $f12 /* argument registers */ +#define fa0f $f13 +#define fa1 $f14 +#define fa1f $f15 +#define ft0 $f4 /* caller saved */ +#define ft0f $f5 +#define ft1 $f6 +#define ft1f $f7 +#define ft2 $f8 +#define ft2f $f9 +#define ft3 $f10 +#define ft3f $f11 +#define ft4 $f16 +#define ft4f $f17 +#define ft5 $f18 +#define ft5f $f19 +#define fs0 $f20 /* callee saved */ +#define fs0f $f21 +#define fs1 $f22 +#define fs1f $f23 +#define fs2 $f24 +#define fs2f $f25 +#define fs3 $f26 +#define fs3f $f27 +#define fs4 $f28 +#define fs4f $f29 +#define fs5 $f30 +#define fs5f $f31 -#define FP64CTX_0 ((SZREG)*4) -#define FP64CTX_2 (FP64CTX_0 + (1 * 8)) -#define FP64CTX_4 (FP64CTX_0 + (2 * 8)) -#define FP64CTX_6 (FP64CTX_0 + (3 * 8)) -#define FP64CTX_8 (FP64CTX_0 + (4 * 8)) -#define FP64CTX_10 (FP64CTX_0 + (5 * 8)) -#define FP64CTX_12 (FP64CTX_0 + (6 * 8)) -#define FP64CTX_14 (FP64CTX_0 + (7 * 8)) -#define FP64CTX_16 (FP64CTX_0 + (8 * 8)) -#define FP64CTX_18 (FP64CTX_0 + (9 * 8)) -#define FP64CTX_20 (FP64CTX_0 + (10 * 8)) -#define FP64CTX_22 (FP64CTX_0 + (11 * 8)) -#define FP64CTX_24 (FP64CTX_0 + (12 * 8)) -#define FP64CTX_26 (FP64CTX_0 + (13 * 8)) -#define FP64CTX_28 (FP64CTX_0 + (14 * 8)) -#define FP64CTX_30 (FP64CTX_0 + (15 * 8)) -#define FP64CTX_1 (FP64CTX_30 + (1 * 8)) -#define FP64CTX_3 (FP64CTX_30 + (2 * 8)) -#define FP64CTX_5 (FP64CTX_30 + (3 * 8)) -#define FP64CTX_7 (FP64CTX_30 + (4 * 8)) -#define FP64CTX_9 (FP64CTX_30 + (5 * 8)) -#define FP64CTX_11 (FP64CTX_30 + (6 * 8)) -#define FP64CTX_13 (FP64CTX_30 + (7 * 8)) -#define FP64CTX_15 (FP64CTX_30 + (8 * 8)) -#define FP64CTX_17 (FP64CTX_30 + (9 * 8)) -#define FP64CTX_19 (FP64CTX_30 + (10 * 8)) -#define FP64CTX_21 (FP64CTX_30 + (11 * 8)) -#define FP64CTX_23 (FP64CTX_30 + (12 * 8)) -#define FP64CTX_25 (FP64CTX_30 + (13 * 8)) -#define FP64CTX_27 (FP64CTX_30 + (14 * 8)) -#define FP64CTX_29 (FP64CTX_30 + (15 * 8)) -#define FP64CTX_31 (FP64CTX_30 + (16 * 8)) -#define FP64CTX_SIZE (FP64CTX_31 + (17 * 8)) +#define fcr31 $31 /* FPU status register */ -#define FPCTX_SIZE() (mips_getsr() & ST0_FR ? FP64CTX_SIZE : FP32CTX_SIZE) /* * The following macros are especially useful for __asm__ @@ -284,75 +222,128 @@ struct fp64ctx /* * Coprocessor 1 (FPU) register names */ -#define CP1_REVISION $0 -#define CP1_STATUS $31 +#define CP1_REVISION $0 +#define CP1_UFR $1 +#define CP1_UNFR $4 +#define CP1_FCCR $25 +#define CP1_FEXR $26 +#define CP1_FENR $28 +#define CP1_STATUS $31 + /* - * FPU Status Register Values + * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. */ +#define MIPS_FPIR_S (_ULCAST_(1) << 16) +#define MIPS_FPIR_D (_ULCAST_(1) << 17) +#define MIPS_FPIR_PS (_ULCAST_(1) << 18) +#define MIPS_FPIR_3D (_ULCAST_(1) << 19) +#define MIPS_FPIR_W (_ULCAST_(1) << 20) +#define MIPS_FPIR_L (_ULCAST_(1) << 21) +#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) +#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23) +#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28) +#define MIPS_FPIR_FREP (_ULCAST_(1) << 29) + /* - * Status Register Values + * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register. */ - -#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ -#define FPU_CSR_COND 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ -#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ -#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ -#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ -#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ -#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ -#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ +#define MIPS_FCCR_CONDX_S 0 +#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S) +#define MIPS_FCCR_COND0_S 0 +#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S) +#define MIPS_FCCR_COND1_S 1 +#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S) +#define MIPS_FCCR_COND2_S 2 +#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S) +#define MIPS_FCCR_COND3_S 3 +#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S) +#define MIPS_FCCR_COND4_S 4 +#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S) +#define MIPS_FCCR_COND5_S 5 +#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S) +#define MIPS_FCCR_COND6_S 6 +#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S) +#define MIPS_FCCR_COND7_S 7 +#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S) /* - * X the exception cause indicator - * E the exception enable - * S the sticky/flag bit -*/ -#define FPU_CSR_ALL_X 0x0003f000 -#define FPU_CSR_UNI_X 0x00020000 -#define FPU_CSR_INV_X 0x00010000 -#define FPU_CSR_DIV_X 0x00008000 -#define FPU_CSR_OVF_X 0x00004000 -#define FPU_CSR_UDF_X 0x00002000 -#define FPU_CSR_INE_X 0x00001000 + * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register. + */ +#define MIPS_FENR_FS_S 2 +#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S) -#define FPU_CSR_ALL_E 0x00000f80 -#define FPU_CSR_INV_E 0x00000800 -#define FPU_CSR_DIV_E 0x00000400 -#define FPU_CSR_OVF_E 0x00000200 -#define FPU_CSR_UDF_E 0x00000100 -#define FPU_CSR_INE_E 0x00000080 +/* + * FPU Status Register Values + */ +#define FPU_CSR_COND_S 23 /* $fcc0 */ +#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S) -#define FPU_CSR_ALL_S 0x0000007c -#define FPU_CSR_INV_S 0x00000040 -#define FPU_CSR_DIV_S 0x00000020 -#define FPU_CSR_OVF_S 0x00000010 -#define FPU_CSR_UDF_S 0x00000008 -#define FPU_CSR_INE_S 0x00000004 +#define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */ +#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S) -/* rounding mode */ -#define FPU_CSR_RN 0x0 /* nearest */ -#define FPU_CSR_RZ 0x1 /* towards zero */ -#define FPU_CSR_RU 0x2 /* towards +Infinity */ -#define FPU_CSR_RD 0x3 /* towards -Infinity */ +#define FPU_CSR_FO 0x00400000 +#define FPU_CSR_FN 0x00200000 +#define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */ +#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S) +#define FPU_CSR_COND1_S 25 /* $fcc1 */ +#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S) +#define FPU_CSR_COND2_S 26 /* $fcc2 */ +#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S) +#define FPU_CSR_COND3_S 27 /* $fcc3 */ +#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S) +#define FPU_CSR_COND4_S 28 /* $fcc4 */ +#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S) +#define FPU_CSR_COND5_S 29 /* $fcc5 */ +#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S) +#define FPU_CSR_COND6_S 30 /* $fcc6 */ +#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S) +#define FPU_CSR_COND7_S 31 /* $fcc7 */ +#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S) /* - * Values for PageMask register + * Bits 22:20 of the FPU Status Register will be read as 0, + * and should be written as zero. */ -#ifdef CONFIG_CPU_VR41XX +#define FPU_CSR_RSVD (_ULCAST_(7) << 20) -/* Why doesn't stupidity hurt ... */ +#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19) +#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18) -#define PM_1K 0x00000000 -#define PM_4K 0x00001800 -#define PM_16K 0x00007800 -#define PM_64K 0x0001f800 -#define PM_256K 0x0007f800 +/* + * X the exception cause indicator + * E the exception enable + * S the sticky/flag bit +*/ +#define FPU_CSR_ALL_X 0x0003f000 +#define FPU_CSR_UNI_X 0x00020000 +#define FPU_CSR_INV_X 0x00010000 +#define FPU_CSR_DIV_X 0x00008000 +#define FPU_CSR_OVF_X 0x00004000 +#define FPU_CSR_UDF_X 0x00002000 +#define FPU_CSR_INE_X 0x00001000 -#else +#define FPU_CSR_ALL_E 0x00000f80 +#define FPU_CSR_INV_E 0x00000800 +#define FPU_CSR_DIV_E 0x00000400 +#define FPU_CSR_OVF_E 0x00000200 +#define FPU_CSR_UDF_E 0x00000100 +#define FPU_CSR_INE_E 0x00000080 + +#define FPU_CSR_ALL_S 0x0000007c +#define FPU_CSR_INV_S 0x00000040 +#define FPU_CSR_DIV_S 0x00000020 +#define FPU_CSR_OVF_S 0x00000010 +#define FPU_CSR_UDF_S 0x00000008 +#define FPU_CSR_INE_S 0x00000004 + +/* Bits 0 and 1 of FPU Status Register specify the rounding mode */ +#define FPU_CSR_RM 0x00000003 +#define FPU_CSR_RN 0x0 /* nearest */ +#define FPU_CSR_RZ 0x1 /* towards zero */ +#define FPU_CSR_RU 0x2 /* towards +Infinity */ +#define FPU_CSR_RD 0x3 /* towards -Infinity */ #define PM_4K 0x00000000 #define PM_16K 0x00006000 @@ -364,7 +355,6 @@ struct fp64ctx #define PM_64M 0x07ffe000 #define PM_256M 0x1fffe000 -#endif /* * Values used for computation of new tlb entries @@ -440,38 +430,6 @@ struct fp64ctx #define ST0_IL (_ULCAST_(1) << 23) #define ST0_DL (_ULCAST_(1) << 24) -/* - * Bitfields in the TX39 family CP0 Configuration Register 3 - */ -#define TX39_CONF_ICS_SHIFT 19 -#define TX39_CONF_ICS_MASK 0x00380000 -#define TX39_CONF_ICS_1KB 0x00000000 -#define TX39_CONF_ICS_2KB 0x00080000 -#define TX39_CONF_ICS_4KB 0x00100000 -#define TX39_CONF_ICS_8KB 0x00180000 -#define TX39_CONF_ICS_16KB 0x00200000 - -#define TX39_CONF_DCS_SHIFT 16 -#define TX39_CONF_DCS_MASK 0x00070000 -#define TX39_CONF_DCS_1KB 0x00000000 -#define TX39_CONF_DCS_2KB 0x00010000 -#define TX39_CONF_DCS_4KB 0x00020000 -#define TX39_CONF_DCS_8KB 0x00030000 -#define TX39_CONF_DCS_16KB 0x00040000 - -#define TX39_CONF_CWFON 0x00004000 -#define TX39_CONF_WBON 0x00002000 -#define TX39_CONF_RF_SHIFT 10 -#define TX39_CONF_RF_MASK 0x00000c00 -#define TX39_CONF_DOZE 0x00000200 -#define TX39_CONF_HALT 0x00000100 -#define TX39_CONF_LOCK 0x00000080 -#define TX39_CONF_ICE 0x00000020 -#define TX39_CONF_DCE 0x00000010 -#define TX39_CONF_IRSIZE_SHIFT 2 -#define TX39_CONF_IRSIZE_MASK 0x0000000c -#define TX39_CONF_DRSIZE_SHIFT 0 -#define TX39_CONF_DRSIZE_MASK 0x00000003 /* * Status register bits available in all MIPS CPUs. @@ -729,77 +687,77 @@ struct fp64ctx #define __read_32bit_c0_register(source, sel) \ ({ int __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mfc0\t%0, " #source "\n\t" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__res)); \ - __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mfc0\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0\n\t" \ + : "=r" (__res)); \ + __res; \ }) #define __read_64bit_c0_register(source, sel) \ ({ unsigned long __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmfc0\t%0, " #source "\n\t" \ - ".set\tmips0" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0" \ - : "=r" (__res)); \ - __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmfc0\t%0, " #source "\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + __res; \ }) #define __write_32bit_c0_register(register, sel, value) \ do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mtc0\t%z0, " #register "\n\t" \ - : : "Jr" (value)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mtc0\t%z0, " #register "\n\t" \ + : : "Jr" (value)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ } while (0) #define __write_64bit_c0_register(register, sel, value) \ do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmtc0\t%z0, " #register "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmtc0\t%z0, " #register "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ } while (0) #define __read_ulong_c0_register(reg, sel) \ - ((sizeof(unsigned long) == 4) ? \ - __read_32bit_c0_register(reg, sel) : \ - __read_64bit_c0_register(reg, sel)) + ((sizeof(unsigned long) == 4) ? \ + __read_32bit_c0_register(reg, sel) : \ + __read_64bit_c0_register(reg, sel)) #define __write_ulong_c0_register(reg, sel, val) \ do { \ - if (sizeof(unsigned long) == 4) \ - __write_32bit_c0_register(reg, sel, val); \ - else \ - __write_64bit_c0_register(reg, sel, val); \ + if (sizeof(unsigned long) == 4) \ + __write_32bit_c0_register(reg, sel, val); \ + else \ + __write_64bit_c0_register(reg, sel, val); \ } while (0) /* @@ -808,59 +766,59 @@ do { \ */ #define __read_64bit_c0_split(source, sel) \ ({ \ - unsigned long long val; \ - unsigned long flags; \ - \ - local_irq_save(flags); \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - ".set\tmips0" \ - : "=r" (val)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source ", " #sel "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - ".set\tmips0" \ - : "=r" (val)); \ - local_irq_restore(flags); \ - \ - val; \ + unsigned long long val; \ + unsigned long flags; \ + \ + local_irq_save(flags); \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%M0, " #source "\n\t" \ + "dsll\t%L0, %M0, 32\n\t" \ + "dsrl\t%M0, %M0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + ".set\tmips0" \ + : "=r" (val)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%M0, " #source ", " #sel "\n\t" \ + "dsll\t%L0, %M0, 32\n\t" \ + "dsrl\t%M0, %M0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + ".set\tmips0" \ + : "=r" (val)); \ + local_irq_restore(flags); \ + \ + val; \ }) #define __write_64bit_c0_split(source, sel, val) \ do { \ - unsigned long flags; \ - \ - local_irq_save(flags); \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dsll\t%L0, %L0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - "dsll\t%M0, %M0, 32\n\t" \ - "or\t%L0, %L0, %M0\n\t" \ - "dmtc0\t%L0, " #source "\n\t" \ - ".set\tmips0" \ - : : "r" (val)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dsll\t%L0, %L0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - "dsll\t%M0, %M0, 32\n\t" \ - "or\t%L0, %L0, %M0\n\t" \ - "dmtc0\t%L0, " #source ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "r" (val)); \ - local_irq_restore(flags); \ + unsigned long flags; \ + \ + local_irq_save(flags); \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, " #source "\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, " #source ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + local_irq_restore(flags); \ } while (0) #define read_c0_index() __read_32bit_c0_register($0, 0) @@ -906,6 +864,9 @@ do { \ #define read_c0_prid() __read_32bit_c0_register($15, 0) +#define read_c0_ebase() __read_32bit_c0_register($15, 1) +#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) + #define read_c0_config() __read_32bit_c0_register($16, 0) #define read_c0_config1() __read_32bit_c0_register($16, 1) #define read_c0_config2() __read_32bit_c0_register($16, 2) @@ -1001,20 +962,20 @@ do { \ #define read_32bit_cp0_register(source) \ ({ int __res; \ __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ "mfc0\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ + ".set\tpop" \ : "=r" (__res)); \ __res;}) #define read_32bit_cp0_set1_register(source) \ ({ int __res; \ __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ "cfc0\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ + ".set\tpop" \ : "=r" (__res)); \ __res;}) @@ -1033,13 +994,13 @@ do { \ #define write_32bit_cp0_register(register,value) \ __asm__ __volatile__( \ "mtc0\t%0,"STR(register)"\n\t" \ - "nop" \ + "nop" \ : : "r" (value)); #define write_32bit_cp0_set1_register(register,value) \ __asm__ __volatile__( \ - "ctc0\t%0,"STR(register)"\n\t" \ - "nop" \ + "ctc0\t%0,$"STR(register)"\n\t" \ + "nop" \ : : "r" (value)); #define write_64bit_cp0_register(register,value) \ @@ -1055,16 +1016,16 @@ do { \ #define read_mips32_cp0_config1() \ ({ int __res; \ __asm__ __volatile__( \ - ".set\tnoreorder\n\t" \ - ".set\tnoat\n\t" \ - "#.set\tmips64\n\t" \ - "#mfc0\t$1, $16, 1\n\t" \ - "#.set\tmips0\n\t" \ - ".word\t0x40018001\n\t" \ - "move\t%0,$1\n\t" \ - ".set\tat\n\t" \ - ".set\treorder" \ - :"=r" (__res)); \ + ".set\tnoreorder\n\t" \ + ".set\tnoat\n\t" \ + "#.set\tmips64\n\t" \ + "#mfc0\t$1, $16, 1\n\t" \ + "#.set\tmips0\n\t" \ + ".word\t0x40018001\n\t" \ + "move\t%0,$1\n\t" \ + ".set\tat\n\t" \ + ".set\treorder" \ + :"=r" (__res)); \ __res;}) #endif @@ -1073,45 +1034,51 @@ do { \ */ #define read_32bit_cp1_register(source) \ ({ int __res; \ - __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ - "cfc1\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + "cfc1\t%0,$"STR(source)"\n\t" \ + ".set\tpop" \ : "=r" (__res)); \ __res;}) +#define write_32bit_cp1_register(register,value) \ + __asm__ __volatile__( \ + "ctc1\t%0,$"STR(register)"\n\t" \ + "nop" \ + : : "r" (value)); + /* TLB operations. */ static inline void tlb_probe(void) { - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbp\n\t" - ".set reorder"); + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbp\n\t" + ".set reorder"); } static inline void tlb_read(void) { - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbr\n\t" - ".set reorder"); + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbr\n\t" + ".set reorder"); } static inline void tlb_write_indexed(void) { - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbwi\n\t" - ".set reorder"); + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbwi\n\t" + ".set reorder"); } static inline void tlb_write_random(void) { - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbwr\n\t" - ".set reorder"); + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbwr\n\t" + ".set reorder"); } /* @@ -1121,38 +1088,38 @@ static inline void tlb_write_random(void) static inline unsigned int \ set_c0_##name(unsigned int set) \ { \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res |= set; \ - write_c0_##name(res); \ - \ - return res; \ + unsigned int res; \ + \ + res = read_c0_##name(); \ + res |= set; \ + write_c0_##name(res); \ + \ + return res; \ } \ - \ + \ static inline unsigned int \ clear_c0_##name(unsigned int clear) \ { \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res &= ~clear; \ - write_c0_##name(res); \ - \ - return res; \ + unsigned int res; \ + \ + res = read_c0_##name(); \ + res &= ~clear; \ + write_c0_##name(res); \ + \ + return res; \ } \ - \ + \ static inline unsigned int \ change_c0_##name(unsigned int change, unsigned int new) \ { \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res &= ~change; \ - res |= (new & change); \ - write_c0_##name(res); \ - \ - return res; \ + unsigned int res; \ + \ + res = read_c0_##name(); \ + res &= ~change; \ + res |= (new & change); \ + write_c0_##name(res); \ + \ + return res; \ } __BUILD_SET_C0(status,CP0_STATUS) @@ -1163,6 +1130,17 @@ __BUILD_SET_C0(config,CP0_CONFIG) #define set_cp0_cause(x) set_c0_cause(x) #define set_cp0_config(x) set_c0_config(x) +#define read_c1_status() read_32bit_cp1_register(31) +#define write_c1_status(x) write_32bit_cp1_register(31, x) + +#define readb(reg) (*((volatile unsigned char *) (reg))) +#define readw(reg) (*((volatile unsigned short *) (reg))) +#define readl(reg) (*((volatile unsigned int *) (reg))) + +#define writeb(data, reg) ((*((volatile unsigned char *)(reg))) = (unsigned char)(data)) +#define writew(data, reg) ((*((volatile unsigned short *)(reg))) = (unsigned short)(data)) +#define writel(data, reg) ((*((volatile unsigned int *)(reg))) = (unsigned int)(data)) + #endif /* !__ASSEMBLY__ */ #endif /* _MIPS_REGS_H_ */ diff --git a/libcpu/mips/common/mips_types.h b/libcpu/mips/common/mips_types.h index 7f0b8a6855..cc12d44391 100644 --- a/libcpu/mips/common/mips_types.h +++ b/libcpu/mips/common/mips_types.h @@ -19,7 +19,7 @@ * * Change Logs: * Date Author Notes - * 2016��9��7�� Urey the first version + * 2016-09-07 Urey the first version */ #ifndef _MIPS_TYPES_H_ @@ -87,30 +87,17 @@ typedef unsigned long long u64; #endif -#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \ - || defined(CONFIG_64BIT) -typedef u64 dma_addr_t; - -typedef u64 phys_addr_t; -typedef u64 phys_size_t; - -#else typedef u32 dma_addr_t; typedef u32 phys_addr_t; typedef u32 phys_size_t; -#endif -typedef u64 dma64_addr_t; /* * Don't use phys_t. You've been warned. */ -#ifdef CONFIG_64BIT_PHYS_ADDR -typedef unsigned long long phys_t; -#else + typedef unsigned long phys_t; -#endif #endif /* __ASSEMBLY__ */ diff --git a/libcpu/mips/common/mipscfg.h b/libcpu/mips/common/mipscfg.h deleted file mode 100644 index b4f30615f8..0000000000 --- a/libcpu/mips/common/mipscfg.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * File : mipscfg.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-27 swkyer first version - */ -#ifndef __MIPSCFG_H__ -#define __MIPSCFG_H__ - - -typedef struct mips32_core_cfg -{ - rt_uint16_t icache_line_size; - rt_uint16_t icache_lines_per_way; - rt_uint16_t icache_ways; - rt_uint16_t dcache_line_size; - rt_uint16_t dcache_lines_per_way; - rt_uint16_t dcache_ways; - - rt_uint16_t max_tlb_entries; /* number of tlb entry */ -} mips32_core_cfg_t; - -extern mips32_core_cfg_t g_mips_core; - -#endif /* end of __MIPSCFG_H__ */ diff --git a/libcpu/mips/common/mipsregs.h b/libcpu/mips/common/mipsregs.h deleted file mode 100644 index 22e5754b8b..0000000000 --- a/libcpu/mips/common/mipsregs.h +++ /dev/null @@ -1,706 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle - * Copyright (C) 2000 Silicon Graphics, Inc. - * Modified for further R[236]000 support by Paul M. Antoine, 1996. - * Kevin D. Kissell, [email protected] and Carsten Langgaard, [email protected] - * Copyright (C) 2000, 07 MIPS Technologies, Inc. - * Copyright (C) 2003, 2004 Maciej W. Rozycki - * - * Change Logs: - * Date Author Notes - * - */ -#ifndef __MIPSREGS_H__ -#define __MIPSREGS_H__ - -/* - * The following macros are especially useful for __asm__ - * inline assembler. - */ -#ifndef __STR -#define __STR(x) #x -#endif -#ifndef STR -#define STR(x) __STR(x) -#endif - -/* - * Configure language - */ -#ifdef __ASSEMBLY__ -#define _ULCAST_ -#else -#define _ULCAST_ (unsigned long) -#endif - -/* - * Coprocessor 0 register names - */ -#define CP0_INDEX $0 -#define CP0_RANDOM $1 -#define CP0_ENTRYLO0 $2 -#define CP0_ENTRYLO1 $3 -#define CP0_CONF $3 -#define CP0_CONTEXT $4 -#define CP0_PAGEMASK $5 -#define CP0_WIRED $6 -#define CP0_INFO $7 -#define CP0_BADVADDR $8 -#define CP0_COUNT $9 -#define CP0_ENTRYHI $10 -#define CP0_COMPARE $11 -#define CP0_STATUS $12 -#define CP0_CAUSE $13 -#define CP0_EPC $14 -#define CP0_PRID $15 -#define CP0_CONFIG $16 -#define CP0_LLADDR $17 -#define CP0_WATCHLO $18 -#define CP0_WATCHHI $19 -#define CP0_XCONTEXT $20 -#define CP0_FRAMEMASK $21 -#define CP0_DIAGNOSTIC $22 -#define CP0_DEBUG $23 -#define CP0_DEPC $24 -#define CP0_PERFORMANCE $25 -#define CP0_ECC $26 -#define CP0_CACHEERR $27 -#define CP0_TAGLO $28 -#define CP0_TAGHI $29 -#define CP0_ERROREPC $30 -#define CP0_DESAVE $31 - -/* - * R4640/R4650 cp0 register names. These registers are listed - * here only for completeness; without MMU these CPUs are not useable - * by Linux. A future ELKS port might take make Linux run on them - * though ... - */ -#define CP0_IBASE $0 -#define CP0_IBOUND $1 -#define CP0_DBASE $2 -#define CP0_DBOUND $3 -#define CP0_CALG $17 -#define CP0_IWATCH $18 -#define CP0_DWATCH $19 - -/* - * Coprocessor 0 Set 1 register names - */ -#define CP0_S1_DERRADDR0 $26 -#define CP0_S1_DERRADDR1 $27 -#define CP0_S1_INTCONTROL $20 - -/* - * Coprocessor 0 Set 2 register names - */ -#define CP0_S2_SRSCTL $12 /* MIPSR2 */ - -/* - * Coprocessor 0 Set 3 register names - */ -#define CP0_S3_SRSMAP $12 /* MIPSR2 */ - -/* - * TX39 Series - */ -#define CP0_TX39_CACHE $7 - -/* - * Coprocessor 1 (FPU) register names - */ -#define CP1_REVISION $0 -#define CP1_STATUS $31 - -/* - * FPU Status Register Values - */ -/* - * Status Register Values - */ - -#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ -#define FPU_CSR_COND 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ -#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ -#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ -#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ -#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ -#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ -#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ - - -/* FS/FO/FN */ -#define FPU_CSR_FS 0x01000000 -#define FPU_CSR_FO 0x00400000 -#define FPU_CSR_FN 0x00200000 - -/* - * Bits 18 - 20 of the FPU Status Register will be read as 0, - * and should be written as zero. - */ -#define FPU_CSR_RSVD 0x001c0000 - -/* - * X the exception cause indicator - * E the exception enable - * S the sticky/flag bit -*/ -#define FPU_CSR_ALL_X 0x0003f000 -#define FPU_CSR_UNI_X 0x00020000 -#define FPU_CSR_INV_X 0x00010000 -#define FPU_CSR_DIV_X 0x00008000 -#define FPU_CSR_OVF_X 0x00004000 -#define FPU_CSR_UDF_X 0x00002000 -#define FPU_CSR_INE_X 0x00001000 - -#define FPU_CSR_ALL_E 0x00000f80 -#define FPU_CSR_INV_E 0x00000800 -#define FPU_CSR_DIV_E 0x00000400 -#define FPU_CSR_OVF_E 0x00000200 -#define FPU_CSR_UDF_E 0x00000100 -#define FPU_CSR_INE_E 0x00000080 - -#define FPU_CSR_ALL_S 0x0000007c -#define FPU_CSR_INV_S 0x00000040 -#define FPU_CSR_DIV_S 0x00000020 -#define FPU_CSR_OVF_S 0x00000010 -#define FPU_CSR_UDF_S 0x00000008 -#define FPU_CSR_INE_S 0x00000004 - -/* Bits 0 and 1 of FPU Status Register specify the rounding mode */ -#define FPU_CSR_RM 0x00000003 -#define FPU_CSR_RN 0x0 /* nearest */ -#define FPU_CSR_RZ 0x1 /* towards zero */ -#define FPU_CSR_RU 0x2 /* towards +Infinity */ -#define FPU_CSR_RD 0x3 /* towards -Infinity */ - - -/* - * R4x00 interrupt enable / cause bits - */ -#define IE_SW0 (_ULCAST_(1) << 8) -#define IE_SW1 (_ULCAST_(1) << 9) -#define IE_IRQ0 (_ULCAST_(1) << 10) -#define IE_IRQ1 (_ULCAST_(1) << 11) -#define IE_IRQ2 (_ULCAST_(1) << 12) -#define IE_IRQ3 (_ULCAST_(1) << 13) -#define IE_IRQ4 (_ULCAST_(1) << 14) -#define IE_IRQ5 (_ULCAST_(1) << 15) - -/* - * R4x00 interrupt cause bits - */ -#define C_SW0 (_ULCAST_(1) << 8) -#define C_SW1 (_ULCAST_(1) << 9) -#define C_IRQ0 (_ULCAST_(1) << 10) -#define C_IRQ1 (_ULCAST_(1) << 11) -#define C_IRQ2 (_ULCAST_(1) << 12) -#define C_IRQ3 (_ULCAST_(1) << 13) -#define C_IRQ4 (_ULCAST_(1) << 14) -#define C_IRQ5 (_ULCAST_(1) << 15) - -/* - * Bitfields in the R4xx0 cp0 status register - */ -#define ST0_IE 0x00000001 -#define ST0_EXL 0x00000002 -#define ST0_ERL 0x00000004 -#define ST0_KSU 0x00000018 -# define KSU_USER 0x00000010 -# define KSU_SUPERVISOR 0x00000008 -# define KSU_KERNEL 0x00000000 -#define ST0_UX 0x00000020 -#define ST0_SX 0x00000040 -#define ST0_KX 0x00000080 -#define ST0_DE 0x00010000 -#define ST0_CE 0x00020000 - -/* - * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate - * cacheops in userspace. This bit exists only on RM7000 and RM9000 - * processors. - */ -#define ST0_CO 0x08000000 - -/* - * Bitfields in the R[23]000 cp0 status register. - */ -#define ST0_IEC 0x00000001 -#define ST0_KUC 0x00000002 -#define ST0_IEP 0x00000004 -#define ST0_KUP 0x00000008 -#define ST0_IEO 0x00000010 -#define ST0_KUO 0x00000020 -/* bits 6 & 7 are reserved on R[23]000 */ -#define ST0_ISC 0x00010000 -#define ST0_SWC 0x00020000 -#define ST0_CM 0x00080000 - -/* - * Bits specific to the R4640/R4650 - */ -#define ST0_UM (_ULCAST_(1) << 4) -#define ST0_IL (_ULCAST_(1) << 23) -#define ST0_DL (_ULCAST_(1) << 24) - -/* - * Enable the MIPS DSP ASE - */ -#define ST0_MX 0x01000000 - -/* - * Bitfields in the TX39 family CP0 Configuration Register 3 - */ -#define TX39_CONF_ICS_SHIFT 19 -#define TX39_CONF_ICS_MASK 0x00380000 -#define TX39_CONF_ICS_1KB 0x00000000 -#define TX39_CONF_ICS_2KB 0x00080000 -#define TX39_CONF_ICS_4KB 0x00100000 -#define TX39_CONF_ICS_8KB 0x00180000 -#define TX39_CONF_ICS_16KB 0x00200000 - -#define TX39_CONF_DCS_SHIFT 16 -#define TX39_CONF_DCS_MASK 0x00070000 -#define TX39_CONF_DCS_1KB 0x00000000 -#define TX39_CONF_DCS_2KB 0x00010000 -#define TX39_CONF_DCS_4KB 0x00020000 -#define TX39_CONF_DCS_8KB 0x00030000 -#define TX39_CONF_DCS_16KB 0x00040000 - -#define TX39_CONF_CWFON 0x00004000 -#define TX39_CONF_WBON 0x00002000 -#define TX39_CONF_RF_SHIFT 10 -#define TX39_CONF_RF_MASK 0x00000c00 -#define TX39_CONF_DOZE 0x00000200 -#define TX39_CONF_HALT 0x00000100 -#define TX39_CONF_LOCK 0x00000080 -#define TX39_CONF_ICE 0x00000020 -#define TX39_CONF_DCE 0x00000010 -#define TX39_CONF_IRSIZE_SHIFT 2 -#define TX39_CONF_IRSIZE_MASK 0x0000000c -#define TX39_CONF_DRSIZE_SHIFT 0 -#define TX39_CONF_DRSIZE_MASK 0x00000003 - -/* - * Status register bits available in all MIPS CPUs. - */ -#define ST0_IM 0x0000ff00 -#define STATUSB_IP0 8 -#define STATUSF_IP0 (_ULCAST_(1) << 8) -#define STATUSB_IP1 9 -#define STATUSF_IP1 (_ULCAST_(1) << 9) -#define STATUSB_IP2 10 -#define STATUSF_IP2 (_ULCAST_(1) << 10) -#define STATUSB_IP3 11 -#define STATUSF_IP3 (_ULCAST_(1) << 11) -#define STATUSB_IP4 12 -#define STATUSF_IP4 (_ULCAST_(1) << 12) -#define STATUSB_IP5 13 -#define STATUSF_IP5 (_ULCAST_(1) << 13) -#define STATUSB_IP6 14 -#define STATUSF_IP6 (_ULCAST_(1) << 14) -#define STATUSB_IP7 15 -#define STATUSF_IP7 (_ULCAST_(1) << 15) -#define STATUSB_IP8 0 -#define STATUSF_IP8 (_ULCAST_(1) << 0) -#define STATUSB_IP9 1 -#define STATUSF_IP9 (_ULCAST_(1) << 1) -#define STATUSB_IP10 2 -#define STATUSF_IP10 (_ULCAST_(1) << 2) -#define STATUSB_IP11 3 -#define STATUSF_IP11 (_ULCAST_(1) << 3) -#define STATUSB_IP12 4 -#define STATUSF_IP12 (_ULCAST_(1) << 4) -#define STATUSB_IP13 5 -#define STATUSF_IP13 (_ULCAST_(1) << 5) -#define STATUSB_IP14 6 -#define STATUSF_IP14 (_ULCAST_(1) << 6) -#define STATUSB_IP15 7 -#define STATUSF_IP15 (_ULCAST_(1) << 7) -#define ST0_CH 0x00040000 -#define ST0_SR 0x00100000 -#define ST0_TS 0x00200000 -#define ST0_BEV 0x00400000 -#define ST0_RE 0x02000000 -#define ST0_FR 0x04000000 -#define ST0_CU 0xf0000000 -#define ST0_CU0 0x10000000 -#define ST0_CU1 0x20000000 -#define ST0_CU2 0x40000000 -#define ST0_CU3 0x80000000 -#define ST0_XX 0x80000000 /* MIPS IV naming */ - -/* - * Bitfields and bit numbers in the coprocessor 0 cause register. - * - * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. - */ -#define CAUSEB_EXCCODE 2 -#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) -#define CAUSEB_IP 8 -#define CAUSEF_IP (_ULCAST_(255) << 8) -#define CAUSEB_IP0 8 -#define CAUSEF_IP0 (_ULCAST_(1) << 8) -#define CAUSEB_IP1 9 -#define CAUSEF_IP1 (_ULCAST_(1) << 9) -#define CAUSEB_IP2 10 -#define CAUSEF_IP2 (_ULCAST_(1) << 10) -#define CAUSEB_IP3 11 -#define CAUSEF_IP3 (_ULCAST_(1) << 11) -#define CAUSEB_IP4 12 -#define CAUSEF_IP4 (_ULCAST_(1) << 12) -#define CAUSEB_IP5 13 -#define CAUSEF_IP5 (_ULCAST_(1) << 13) -#define CAUSEB_IP6 14 -#define CAUSEF_IP6 (_ULCAST_(1) << 14) -#define CAUSEB_IP7 15 -#define CAUSEF_IP7 (_ULCAST_(1) << 15) -#define CAUSEB_IV 23 -#define CAUSEF_IV (_ULCAST_(1) << 23) -#define CAUSEB_CE 28 -#define CAUSEF_CE (_ULCAST_(3) << 28) -#define CAUSEB_BD 31 -#define CAUSEF_BD (_ULCAST_(1) << 31) - -/* - * Bits in the coprocessor 0 config register. - */ -/* Generic bits. */ -#define CONF_CM_CACHABLE_NO_WA 0 -#define CONF_CM_CACHABLE_WA 1 -#define CONF_CM_UNCACHED 2 -#define CONF_CM_CACHABLE_NONCOHERENT 3 -#define CONF_CM_CACHABLE_CE 4 -#define CONF_CM_CACHABLE_COW 5 -#define CONF_CM_CACHABLE_CUW 6 -#define CONF_CM_CACHABLE_ACCELERATED 7 -#define CONF_CM_CMASK 7 -#define CONF_BE (_ULCAST_(1) << 15) - -/* Bits common to various processors. */ -#define CONF_CU (_ULCAST_(1) << 3) -#define CONF_DB (_ULCAST_(1) << 4) -#define CONF_IB (_ULCAST_(1) << 5) -#define CONF_DC (_ULCAST_(7) << 6) -#define CONF_IC (_ULCAST_(7) << 9) -#define CONF_EB (_ULCAST_(1) << 13) -#define CONF_EM (_ULCAST_(1) << 14) -#define CONF_SM (_ULCAST_(1) << 16) -#define CONF_SC (_ULCAST_(1) << 17) -#define CONF_EW (_ULCAST_(3) << 18) -#define CONF_EP (_ULCAST_(15)<< 24) -#define CONF_EC (_ULCAST_(7) << 28) -#define CONF_CM (_ULCAST_(1) << 31) - -/* Bits specific to the R4xx0. */ -#define R4K_CONF_SW (_ULCAST_(1) << 20) -#define R4K_CONF_SS (_ULCAST_(1) << 21) -#define R4K_CONF_SB (_ULCAST_(3) << 22) - -/* Bits specific to the R5000. */ -#define R5K_CONF_SE (_ULCAST_(1) << 12) -#define R5K_CONF_SS (_ULCAST_(3) << 20) - -/* Bits specific to the RM7000. */ -#define RM7K_CONF_SE (_ULCAST_(1) << 3) -#define RM7K_CONF_TE (_ULCAST_(1) << 12) -#define RM7K_CONF_CLK (_ULCAST_(1) << 16) -#define RM7K_CONF_TC (_ULCAST_(1) << 17) -#define RM7K_CONF_SI (_ULCAST_(3) << 20) -#define RM7K_CONF_SC (_ULCAST_(1) << 31) - -/* Bits specific to the R10000. */ -#define R10K_CONF_DN (_ULCAST_(3) << 3) -#define R10K_CONF_CT (_ULCAST_(1) << 5) -#define R10K_CONF_PE (_ULCAST_(1) << 6) -#define R10K_CONF_PM (_ULCAST_(3) << 7) -#define R10K_CONF_EC (_ULCAST_(15)<< 9) -#define R10K_CONF_SB (_ULCAST_(1) << 13) -#define R10K_CONF_SK (_ULCAST_(1) << 14) -#define R10K_CONF_SS (_ULCAST_(7) << 16) -#define R10K_CONF_SC (_ULCAST_(7) << 19) -#define R10K_CONF_DC (_ULCAST_(7) << 26) -#define R10K_CONF_IC (_ULCAST_(7) << 29) - -/* Bits specific to the VR41xx. */ -#define VR41_CONF_CS (_ULCAST_(1) << 12) -#define VR41_CONF_M16 (_ULCAST_(1) << 20) -#define VR41_CONF_AD (_ULCAST_(1) << 23) - -/* Bits specific to the R30xx. */ -#define R30XX_CONF_FDM (_ULCAST_(1) << 19) -#define R30XX_CONF_REV (_ULCAST_(1) << 22) -#define R30XX_CONF_AC (_ULCAST_(1) << 23) -#define R30XX_CONF_RF (_ULCAST_(1) << 24) -#define R30XX_CONF_HALT (_ULCAST_(1) << 25) -#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) -#define R30XX_CONF_DBR (_ULCAST_(1) << 29) -#define R30XX_CONF_SB (_ULCAST_(1) << 30) -#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) - -/* Bits specific to the TX49. */ -#define TX49_CONF_DC (_ULCAST_(1) << 16) -#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ -#define TX49_CONF_HALT (_ULCAST_(1) << 18) -#define TX49_CONF_CWFON (_ULCAST_(1) << 27) - -/* Bits specific to the MIPS32/64 PRA. */ -#define MIPS_CONF_MT (_ULCAST_(7) << 7) -#define MIPS_CONF_AR (_ULCAST_(7) << 10) -#define MIPS_CONF_AT (_ULCAST_(3) << 13) -#define MIPS_CONF_M (_ULCAST_(1) << 31) - -/* - * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. - */ -#define MIPS_CONF1_FP (_ULCAST_(1) << 0) -#define MIPS_CONF1_EP (_ULCAST_(1) << 1) -#define MIPS_CONF1_CA (_ULCAST_(1) << 2) -#define MIPS_CONF1_WR (_ULCAST_(1) << 3) -#define MIPS_CONF1_PC (_ULCAST_(1) << 4) -#define MIPS_CONF1_MD (_ULCAST_(1) << 5) -#define MIPS_CONF1_C2 (_ULCAST_(1) << 6) -#define MIPS_CONF1_DA (_ULCAST_(7) << 7) -#define MIPS_CONF1_DL (_ULCAST_(7) << 10) -#define MIPS_CONF1_DS (_ULCAST_(7) << 13) -#define MIPS_CONF1_IA (_ULCAST_(7) << 16) -#define MIPS_CONF1_IL (_ULCAST_(7) << 19) -#define MIPS_CONF1_IS (_ULCAST_(7) << 22) -#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) - -#define MIPS_CONF2_SA (_ULCAST_(15)<< 0) -#define MIPS_CONF2_SL (_ULCAST_(15)<< 4) -#define MIPS_CONF2_SS (_ULCAST_(15)<< 8) -#define MIPS_CONF2_SU (_ULCAST_(15)<< 12) -#define MIPS_CONF2_TA (_ULCAST_(15)<< 16) -#define MIPS_CONF2_TL (_ULCAST_(15)<< 20) -#define MIPS_CONF2_TS (_ULCAST_(15)<< 24) -#define MIPS_CONF2_TU (_ULCAST_(7) << 28) - -#define MIPS_CONF3_TL (_ULCAST_(1) << 0) -#define MIPS_CONF3_SM (_ULCAST_(1) << 1) -#define MIPS_CONF3_MT (_ULCAST_(1) << 2) -#define MIPS_CONF3_SP (_ULCAST_(1) << 4) -#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) -#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) -#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) -#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) - -/* - * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. - */ -#define MIPS_FPIR_S (_ULCAST_(1) << 16) -#define MIPS_FPIR_D (_ULCAST_(1) << 17) -#define MIPS_FPIR_PS (_ULCAST_(1) << 18) -#define MIPS_FPIR_3D (_ULCAST_(1) << 19) -#define MIPS_FPIR_W (_ULCAST_(1) << 20) -#define MIPS_FPIR_L (_ULCAST_(1) << 21) -#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) - -/* - * R10000 performance counter definitions. - * - * FIXME: The R10000 performance counter opens a nice way to implement CPU - * time accounting with a precission of one cycle. I don't have - * R10000 silicon but just a manual, so ... - */ - -/* - * Events counted by counter #0 - */ -#define CE0_CYCLES 0 -#define CE0_INSN_ISSUED 1 -#define CE0_LPSC_ISSUED 2 -#define CE0_S_ISSUED 3 -#define CE0_SC_ISSUED 4 -#define CE0_SC_FAILED 5 -#define CE0_BRANCH_DECODED 6 -#define CE0_QW_WB_SECONDARY 7 -#define CE0_CORRECTED_ECC_ERRORS 8 -#define CE0_ICACHE_MISSES 9 -#define CE0_SCACHE_I_MISSES 10 -#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 -#define CE0_EXT_INTERVENTIONS_REQ 12 -#define CE0_EXT_INVALIDATE_REQ 13 -#define CE0_VIRTUAL_COHERENCY_COND 14 -#define CE0_INSN_GRADUATED 15 - -/* - * Events counted by counter #1 - */ -#define CE1_CYCLES 0 -#define CE1_INSN_GRADUATED 1 -#define CE1_LPSC_GRADUATED 2 -#define CE1_S_GRADUATED 3 -#define CE1_SC_GRADUATED 4 -#define CE1_FP_INSN_GRADUATED 5 -#define CE1_QW_WB_PRIMARY 6 -#define CE1_TLB_REFILL 7 -#define CE1_BRANCH_MISSPREDICTED 8 -#define CE1_DCACHE_MISS 9 -#define CE1_SCACHE_D_MISSES 10 -#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 -#define CE1_EXT_INTERVENTION_HITS 12 -#define CE1_EXT_INVALIDATE_REQ 13 -#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 -#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 - -/* - * These flags define in which privilege mode the counters count events - */ -#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ -#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ -#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ -#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ - - -#ifndef __ASSEMBLY__ - -/* - * Macros to access the system control coprocessor - */ -#define __read_32bit_c0_register(source, sel) \ -({ int __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mfc0\t%0, " #source "\n\t" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__res)); \ - __res; \ -}) - -#define __write_32bit_c0_register(register, sel, value) \ -do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mtc0\t%z0, " #register "\n\t" \ - : : "Jr" ((unsigned int)(value))); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" ((unsigned int)(value))); \ -} while (0) - -#define read_c0_index() __read_32bit_c0_register($0, 0) -#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) - -#define read_c0_random() __read_32bit_c0_register($1, 0) -#define write_c0_random(val) __write_32bit_c0_register($1, 0, val) - -#define read_c0_entrylo0() __read_32bit_c0_register($2, 0) -#define write_c0_entrylo0(val) __write_32bit_c0_register($2, 0, val) - -#define read_c0_entrylo1() __read_32bit_c0_register($3, 0) -#define write_c0_entrylo1(val) __write_32bit_c0_register($3, 0, val) - -#define read_c0_conf() __read_32bit_c0_register($3, 0) -#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) - -#define read_c0_context() __read_32bit_c0_register($4, 0) -#define write_c0_context(val) __write_32bit_c0_register($4, 0, val) - -#define read_c0_userlocal() __read_32bit_c0_register($4, 2) -#define write_c0_userlocal(val) __write_32bit_c0_register($4, 2, val) - -#define read_c0_pagemask() __read_32bit_c0_register($5, 0) -#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) - -#define read_c0_wired() __read_32bit_c0_register($6, 0) -#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) - -#define read_c0_info() __read_32bit_c0_register($7, 0) - -#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ -#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) - -#define read_c0_badvaddr() __read_32bit_c0_register($8, 0) -#define write_c0_badvaddr(val) __write_32bit_c0_register($8, 0, val) - -#define read_c0_count() __read_32bit_c0_register($9, 0) -#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) - -#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ -#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) - -#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ -#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) - -#define read_c0_entryhi() __read_32bit_c0_register($10, 0) -#define write_c0_entryhi(val) __write_32bit_c0_register($10, 0, val) - -#define read_c0_compare() __read_32bit_c0_register($11, 0) -#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) - -#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ -#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) - -#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ -#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) - -#define read_c0_status() __read_32bit_c0_register($12, 0) -#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) - -#define read_c0_cause() __read_32bit_c0_register($13, 0) -#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) - -#define read_c0_epc() __read_32bit_c0_register($14, 0) -#define write_c0_epc(val) __write_32bit_c0_register($14, 0, val) - -#define read_c0_prid() __read_32bit_c0_register($15, 0) - -#define read_c0_ebase() __read_32bit_c0_register($15, 1) -#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) - -#define read_c0_config() __read_32bit_c0_register($16, 0) -#define read_c0_config1() __read_32bit_c0_register($16, 1) -#define read_c0_config2() __read_32bit_c0_register($16, 2) -#define read_c0_config3() __read_32bit_c0_register($16, 3) -#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) -#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) -#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) -#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) - - -/* - * Macros to access the floating point coprocessor control registers - */ -#define read_32bit_cp1_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ - /* gas fails to assemble cfc1 for some archs (octeon).*/ \ - ".set\tmips1\n\t" \ - "cfc1\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ - : "=r" (__res)); \ - __res;}) -#define write_32bit_cp1_register(register, value) \ -do { \ - __asm__ __volatile__( \ - "ctc1\t%z0, "STR(register)"\n\t" \ - : : "Jr" ((unsigned int)(value))); \ -} while (0) - -#define read_c1_status() read_32bit_cp1_register(CP1_STATUS) -#define read_c1_revision() read_32bit_cp1_register(CP1_REVISION); -#define write_c1_status(val) write_32bit_cp1_register(CP1_STATUS, val) - - -#endif /* end of __ASSEMBLY__ */ - -#endif /* end of __MIPSREGS_H__ */ - diff --git a/libcpu/mips/common/ptrace.h b/libcpu/mips/common/ptrace.h new file mode 100644 index 0000000000..00ce58a085 --- /dev/null +++ b/libcpu/mips/common/ptrace.h @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + */ + +#ifndef _MIPS_PTRACE_H +#define _MIPS_PTRACE_H + +#include "asm.h" +#include "mips_regs.h" + +#define HI_LO_SIZE 4 + +#define FP_REG_SIZE 8 +#define NUM_FPU_REGS 16 + +#ifndef __ASSEMBLY__ +#include <rtthread.h> + +struct mips_fpu_struct { + rt_uint64_t fpr[NUM_FPU_REGS]; + rt_uint32_t fcr31; + rt_uint32_t pad; +}; + +struct pt_regs { +#ifndef ARCH_MIPS64 + /* Only O32 Need This! */ + /* Pad bytes for argument save space on the stack. */ + rt_uint32_t pad0[8]; + + /* Saved main processor registers. */ + rt_uint32_t regs[32]; + + /* Saved special registers. */ + rt_uint32_t cp0_status; + rt_uint32_t hi; + rt_uint32_t lo; + rt_uint32_t cp0_badvaddr; + rt_uint32_t cp0_cause; + rt_uint32_t cp0_epc; +#else + /* Saved main processor registers. */ + unsigned long regs[32]; + + /* Saved special registers. */ + rt_uint32_t cp0_status; + rt_uint32_t hi; + rt_uint32_t lo; + unsigned long cp0_badvaddr; + rt_uint32_t cp0_cause; + unsigned long cp0_epc; +#endif + +#ifdef RT_USING_FPU + /* FPU Registers */ + /* Unlike Linux Kernel, we save these registers unconditionally, + * so it should be a part of pt_regs */ + struct mips_fpu_struct fpu; +#endif +} __aligned(8); +#endif + +/* Note: For call stack o32 ABI has 0x8 shadowsoace Here */ +#ifdef ARCH_MIPS64 +#define PT_R0 (0x0 * LONGSIZE) /* 0 */ +#else +#define PT_R0 (0x8 * LONGSIZE) /* 0 */ +#endif +#define PT_R1 ((PT_R0) + LONGSIZE) /* 1 */ +#define PT_R2 ((PT_R1) + LONGSIZE) /* 2 */ +#define PT_R3 ((PT_R2) + LONGSIZE) /* 3 */ +#define PT_R4 ((PT_R3) + LONGSIZE) /* 4 */ +#define PT_R5 ((PT_R4) + LONGSIZE) /* 5 */ +#define PT_R6 ((PT_R5) + LONGSIZE) /* 6 */ +#define PT_R7 ((PT_R6) + LONGSIZE) /* 7 */ +#define PT_R8 ((PT_R7) + LONGSIZE) /* 8 */ +#define PT_R9 ((PT_R8) + LONGSIZE) /* 9 */ +#define PT_R10 ((PT_R9) + LONGSIZE) /* 10 */ +#define PT_R11 ((PT_R10) + LONGSIZE) /* 11 */ +#define PT_R12 ((PT_R11) + LONGSIZE) /* 12 */ +#define PT_R13 ((PT_R12) + LONGSIZE) /* 13 */ +#define PT_R14 ((PT_R13) + LONGSIZE) /* 14 */ +#define PT_R15 ((PT_R14) + LONGSIZE) /* 15 */ +#define PT_R16 ((PT_R15) + LONGSIZE) /* 16 */ +#define PT_R17 ((PT_R16) + LONGSIZE) /* 17 */ +#define PT_R18 ((PT_R17) + LONGSIZE) /* 18 */ +#define PT_R19 ((PT_R18) + LONGSIZE) /* 19 */ +#define PT_R20 ((PT_R19) + LONGSIZE) /* 20 */ +#define PT_R21 ((PT_R20) + LONGSIZE) /* 21 */ +#define PT_R22 ((PT_R21) + LONGSIZE) /* 22 */ +#define PT_R23 ((PT_R22) + LONGSIZE) /* 23 */ +#define PT_R24 ((PT_R23) + LONGSIZE) /* 24 */ +#define PT_R25 ((PT_R24) + LONGSIZE) /* 25 */ +#define PT_R26 ((PT_R25) + LONGSIZE) /* 26 */ +#define PT_R27 ((PT_R26) + LONGSIZE) /* 27 */ +#define PT_R28 ((PT_R27) + LONGSIZE) /* 28 */ +#define PT_R29 ((PT_R28) + LONGSIZE) /* 29 */ +#define PT_R30 ((PT_R29) + LONGSIZE) /* 30 */ +#define PT_R31 ((PT_R30) + LONGSIZE) /* 31 */ + +/* + * Saved special registers + */ +#define PT_STATUS ((PT_R31) + LONGSIZE) /* 32 */ +#define PT_HI ((PT_STATUS) + HI_LO_SIZE) /* 33 */ +#define PT_LO ((PT_HI) + HI_LO_SIZE) /* 34 */ +#define PT_BADVADDR ((PT_LO) + LONGSIZE) /* 35 */ +#define PT_CAUSE ((PT_BADVADDR) + LONGSIZE) /* 36 */ +#define PT_EPC ((PT_CAUSE) + LONGSIZE) /* 37 */ + +#define PT_REG_END ((PT_EPC) + LONGSIZE) /* Align already ensured manually */ + +#ifdef RT_USING_FPU +#define PT_FPU_R0 (PT_REG_END) +#define PT_FPU_R2 ((PT_FPU_R0) + FP_REG_SIZE) +#define PT_FPU_R4 ((PT_FPU_R2) + FP_REG_SIZE) +#define PT_FPU_R6 ((PT_FPU_R4) + FP_REG_SIZE) +#define PT_FPU_R8 ((PT_FPU_R6) + FP_REG_SIZE) +#define PT_FPU_R10 ((PT_FPU_R8) + FP_REG_SIZE) +#define PT_FPU_R12 ((PT_FPU_R10) + FP_REG_SIZE) +#define PT_FPU_R14 ((PT_FPU_R12) + FP_REG_SIZE) +#define PT_FPU_R16 ((PT_FPU_R14) + FP_REG_SIZE) +#define PT_FPU_R18 ((PT_FPU_R16) + FP_REG_SIZE) +#define PT_FPU_R20 ((PT_FPU_R18) + FP_REG_SIZE) +#define PT_FPU_R22 ((PT_FPU_R20) + FP_REG_SIZE) +#define PT_FPU_R24 ((PT_FPU_R22) + FP_REG_SIZE) +#define PT_FPU_R26 ((PT_FPU_R24) + FP_REG_SIZE) +#define PT_FPU_R28 ((PT_FPU_R26) + FP_REG_SIZE) +#define PT_FPU_R30 ((PT_FPU_R28) + FP_REG_SIZE) +#define PT_FPU_FCSR31 ((PT_FPU_R30) + FP_REG_SIZE) +#define PT_FPU_PAD0 ((PT_FPU_FCSR31) + 4) + +#define PT_FPU_END ((PT_FPU_PAD0) + 4) +#define PT_SIZE PT_FPU_END +#else +#define PT_SIZE PT_REG_END +#endif + +#endif
\ No newline at end of file diff --git a/libcpu/mips/common/stack.c b/libcpu/mips/common/stack.c new file mode 100644 index 0000000000..b933b184e7 --- /dev/null +++ b/libcpu/mips/common/stack.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + */ + +#include <rtthread.h> + +#include "mips.h" + +register rt_uint32_t $GP __asm__ ("$28"); + +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) +{ + static rt_ubase_t wSR=0; + static rt_ubase_t wGP; + rt_uint8_t *stk; + + struct pt_regs *pt; + + rt_uint32_t i; + + /* Get stack aligned */ + stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stack_addr, 8); + stk -= sizeof(struct pt_regs); + pt = (struct pt_regs*)stk; + +#ifndef ARCH_MIPS64 + for (i = 0; i < 8; ++i) + { + pt->pad0[i] = 0xdeadbeef; + } +#endif + /* Fill Stack register numbers */ + for (i = 0; i < 32; ++i) + { + pt->regs[i] = 0xdeadbeef; + } + + pt->regs[REG_SP] = (rt_ubase_t)stk; + pt->regs[REG_A0] = (rt_ubase_t)parameter; + pt->regs[REG_GP] = (rt_ubase_t)$GP; + pt->regs[REG_FP] = (rt_ubase_t)0x0; + pt->regs[REG_RA] = (rt_ubase_t)texit; + + pt->hi = 0x0; + pt->lo = 0x0; + pt->cp0_status = (ST0_IE | ST0_CU0 | ST0_IM); +#ifdef RT_USING_FPU + pt->cp0_status |= (ST0_CU1 | ST0_FR); +#endif + pt->cp0_cause = read_c0_cause(); + pt->cp0_epc = (rt_ubase_t)tentry; + pt->cp0_badvaddr = 0x0; + + return stk; +} diff --git a/libcpu/mips/common/stackframe.h b/libcpu/mips/common/stackframe.h index 96b69ab14f..bb92a18c9c 100644 --- a/libcpu/mips/common/stackframe.h +++ b/libcpu/mips/common/stackframe.h @@ -1,228 +1,256 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. + * Copyright (c) 2006-2019, RT-Thread Development Team * - * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle - * Copyright (C) 1994, 1995, 1996 Paul M. Antoine. - * Copyright (C) 1999 Silicon Graphics, Inc. - * Copyright (C) 2007 Maciej W. Rozycki + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version */ + #ifndef __STACKFRAME_H__ #define __STACKFRAME_H__ #include "asm.h" -#include "mipsregs.h" - -/* - * Stack layout for the INT exception handler - * Derived from the stack layout described in asm-mips/stackframe.h - * - * The first PTRSIZE*6 bytes are argument save space for C subroutines. - */ - -//#define PT_R0 (PTRSIZE*6) /* 0 */ -#define PT_R0 (0) /* 0 */ -#define PT_R1 ((PT_R0) + LONGSIZE) /* 1 */ -#define PT_R2 ((PT_R1) + LONGSIZE) /* 2 */ -#define PT_R3 ((PT_R2) + LONGSIZE) /* 3 */ -#define PT_R4 ((PT_R3) + LONGSIZE) /* 4 */ -#define PT_R5 ((PT_R4) + LONGSIZE) /* 5 */ -#define PT_R6 ((PT_R5) + LONGSIZE) /* 6 */ -#define PT_R7 ((PT_R6) + LONGSIZE) /* 7 */ -#define PT_R8 ((PT_R7) + LONGSIZE) /* 8 */ -#define PT_R9 ((PT_R8) + LONGSIZE) /* 9 */ -#define PT_R10 ((PT_R9) + LONGSIZE) /* 10 */ -#define PT_R11 ((PT_R10) + LONGSIZE) /* 11 */ -#define PT_R12 ((PT_R11) + LONGSIZE) /* 12 */ -#define PT_R13 ((PT_R12) + LONGSIZE) /* 13 */ -#define PT_R14 ((PT_R13) + LONGSIZE) /* 14 */ -#define PT_R15 ((PT_R14) + LONGSIZE) /* 15 */ -#define PT_R16 ((PT_R15) + LONGSIZE) /* 16 */ -#define PT_R17 ((PT_R16) + LONGSIZE) /* 17 */ -#define PT_R18 ((PT_R17) + LONGSIZE) /* 18 */ -#define PT_R19 ((PT_R18) + LONGSIZE) /* 19 */ -#define PT_R20 ((PT_R19) + LONGSIZE) /* 20 */ -#define PT_R21 ((PT_R20) + LONGSIZE) /* 21 */ -#define PT_R22 ((PT_R21) + LONGSIZE) /* 22 */ -#define PT_R23 ((PT_R22) + LONGSIZE) /* 23 */ -#define PT_R24 ((PT_R23) + LONGSIZE) /* 24 */ -#define PT_R25 ((PT_R24) + LONGSIZE) /* 25 */ -#define PT_R26 ((PT_R25) + LONGSIZE) /* 26 */ -#define PT_R27 ((PT_R26) + LONGSIZE) /* 27 */ -#define PT_R28 ((PT_R27) + LONGSIZE) /* 28 */ -#define PT_R29 ((PT_R28) + LONGSIZE) /* 29 */ -#define PT_R30 ((PT_R29) + LONGSIZE) /* 30 */ -#define PT_R31 ((PT_R30) + LONGSIZE) /* 31 */ - -/* - * Saved special registers - */ -#define PT_STATUS ((PT_R31) + LONGSIZE) /* 32 */ -#define PT_HI ((PT_STATUS) + LONGSIZE) /* 33 */ -#define PT_LO ((PT_HI) + LONGSIZE) /* 34 */ -#define PT_BADVADDR ((PT_LO) + LONGSIZE) /* 35 */ -#define PT_CAUSE ((PT_BADVADDR) + LONGSIZE) /* 36 */ -#define PT_EPC ((PT_CAUSE) + LONGSIZE) /* 37 */ +#include "mips_regs.h" +#include "ptrace.h" -#define PT_SIZE ((((PT_EPC) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1)) +/* You MUST ensure FP is enabled before SAVE_FPU! */ + .macro SAVE_FPU + .set push + .set noreorder +#ifdef RT_USING_FPU + /* Ensure CU1 (FPU) is enabled */ + MFC0 v1, CP0_STATUS + lui t1, %hi(ST0_CU1) + addiu t1, t1, %lo(ST0_CU1) + or v1, v1, t1 + MTC0 v1, CP0_STATUS + SSNOP + cfc1 v1, fcr31 + /* Store as delay slot */ + s.d $f0, PT_FPU_R0(sp) + s.d $f2, PT_FPU_R2(sp) + s.d $f4, PT_FPU_R4(sp) + s.d $f6, PT_FPU_R6(sp) + s.d $f8, PT_FPU_R8(sp) + s.d $f10, PT_FPU_R10(sp) + s.d $f12, PT_FPU_R12(sp) + s.d $f14, PT_FPU_R14(sp) + s.d $f16, PT_FPU_R16(sp) + s.d $f18, PT_FPU_R18(sp) + s.d $f20, PT_FPU_R20(sp) + s.d $f22, PT_FPU_R22(sp) + s.d $f24, PT_FPU_R24(sp) + s.d $f26, PT_FPU_R26(sp) + s.d $f28, PT_FPU_R28(sp) + s.d $f30, PT_FPU_R30(sp) + LONG_S v1, PT_FPU_FCSR31(sp) +#endif + .set reorder + .set pop + .endm + .macro SAVE_AT + .set push + .set noat + LONG_S $1, PT_R1(sp) + .set pop + .endm - .macro SAVE_AT - .set push - .set noat - LONG_S $1, PT_R1(sp) - .set pop - .endm + .macro SAVE_TEMP + mfhi v1 + LONG_S $8, PT_R8(sp) + LONG_S $9, PT_R9(sp) + sw v1, PT_HI(sp) + mflo v1 + LONG_S $10, PT_R10(sp) + LONG_S $11, PT_R11(sp) + sw v1, PT_LO(sp) + LONG_S $12, PT_R12(sp) + LONG_S $13, PT_R13(sp) + LONG_S $14, PT_R14(sp) + LONG_S $15, PT_R15(sp) + LONG_S $24, PT_R24(sp) + .endm - .macro SAVE_TEMP - mfhi v1 - LONG_S $8, PT_R8(sp) - LONG_S $9, PT_R9(sp) - LONG_S v1, PT_HI(sp) - mflo v1 - LONG_S $10, PT_R10(sp) - LONG_S $11, PT_R11(sp) - LONG_S v1, PT_LO(sp) - LONG_S $12, PT_R12(sp) - LONG_S $13, PT_R13(sp) - LONG_S $14, PT_R14(sp) - LONG_S $15, PT_R15(sp) - LONG_S $24, PT_R24(sp) - .endm + .macro SAVE_STATIC + LONG_S $16, PT_R16(sp) + LONG_S $17, PT_R17(sp) + LONG_S $18, PT_R18(sp) + LONG_S $19, PT_R19(sp) + LONG_S $20, PT_R20(sp) + LONG_S $21, PT_R21(sp) + LONG_S $22, PT_R22(sp) + LONG_S $23, PT_R23(sp) + LONG_S $30, PT_R30(sp) + .endm - .macro SAVE_STATIC - LONG_S $16, PT_R16(sp) - LONG_S $17, PT_R17(sp) - LONG_S $18, PT_R18(sp) - LONG_S $19, PT_R19(sp) - LONG_S $20, PT_R20(sp) - LONG_S $21, PT_R21(sp) - LONG_S $22, PT_R22(sp) - LONG_S $23, PT_R23(sp) - LONG_S $30, PT_R30(sp) - .endm + .macro SAVE_SOME + .set push + .set noat + .set reorder + move k1, sp + move k0, sp + PTR_SUBU sp, k1, PT_SIZE + LONG_S k0, PT_R29(sp) + LONG_S $3, PT_R3(sp) + LONG_S $0, PT_R0(sp) + MFC0 v1, CP0_STATUS + LONG_S $2, PT_R2(sp) + LONG_S v1, PT_STATUS(sp) + LONG_S $4, PT_R4(sp) + MFC0 v1, CP0_CAUSE + LONG_S $5, PT_R5(sp) + LONG_S v1, PT_CAUSE(sp) + LONG_S $6, PT_R6(sp) + MFC0 v1, CP0_EPC + LONG_S $7, PT_R7(sp) + LONG_S v1, PT_EPC(sp) + LONG_S $25, PT_R25(sp) + LONG_S $28, PT_R28(sp) + LONG_S $31, PT_R31(sp) + .set pop + .endm - .macro get_saved_sp - nop - .endm + .macro SAVE_ALL + SAVE_SOME + SAVE_AT + SAVE_TEMP + SAVE_FPU + SAVE_STATIC + .endm - .macro SAVE_SOME - .set push - .set noat - .set reorder - move k1, sp -8: move k0, sp - PTR_SUBU sp, k1, PT_SIZE - LONG_S k0, PT_R29(sp) - LONG_S $3, PT_R3(sp) - LONG_S $0, PT_R0(sp) - mfc0 v1, CP0_STATUS - LONG_S $2, PT_R2(sp) - LONG_S v1, PT_STATUS(sp) - LONG_S $4, PT_R4(sp) - mfc0 v1, CP0_CAUSE - LONG_S $5, PT_R5(sp) - LONG_S v1, PT_CAUSE(sp) - LONG_S $6, PT_R6(sp) - MFC0 v1, CP0_EPC - LONG_S $7, PT_R7(sp) - LONG_S v1, PT_EPC(sp) - LONG_S $25, PT_R25(sp) - LONG_S $28, PT_R28(sp) - LONG_S $31, PT_R31(sp) - .set pop - .endm + .macro RESTORE_FPU + .set push + .set noreorder +#ifdef RT_USING_FPU + /* Ensure CU1 (FPU) is enabled */ + MFC0 v1, CP0_STATUS + lui t1, %hi(ST0_CU1) + addiu t1, t1, %lo(ST0_CU1) + or v1, v1, t1 + MTC0 v1, CP0_STATUS + SSNOP + LONG_L v1, PT_FPU_FCSR31(sp) + ctc1 v1, fcr31 + l.d $f0, PT_FPU_R0(sp) + l.d $f2, PT_FPU_R2(sp) + l.d $f4, PT_FPU_R4(sp) + l.d $f6, PT_FPU_R6(sp) + l.d $f8, PT_FPU_R8(sp) + l.d $f10, PT_FPU_R10(sp) + l.d $f12, PT_FPU_R12(sp) + l.d $f14, PT_FPU_R14(sp) + l.d $f16, PT_FPU_R16(sp) + l.d $f18, PT_FPU_R18(sp) + l.d $f20, PT_FPU_R20(sp) + l.d $f22, PT_FPU_R22(sp) + l.d $f24, PT_FPU_R24(sp) + l.d $f26, PT_FPU_R26(sp) + l.d $f28, PT_FPU_R28(sp) + l.d $f30, PT_FPU_R30(sp) +#endif + .set reorder + .set pop + .endm - .macro SAVE_ALL - SAVE_SOME - SAVE_AT - SAVE_TEMP - SAVE_STATIC - .endm + .macro RESTORE_AT + .set push + .set noat + LONG_L $1, PT_R1(sp) + .set pop + .endm - .macro RESTORE_AT - .set push - .set noat - LONG_L $1, PT_R1(sp) - .set pop - .endm + .macro RESTORE_TEMP + lw $24, PT_LO(sp) + LONG_L $8, PT_R8(sp) + LONG_L $9, PT_R9(sp) + mtlo $24 + lw $24, PT_HI(sp) + LONG_L $10, PT_R10(sp) + LONG_L $11, PT_R11(sp) + mthi $24 + LONG_L $12, PT_R12(sp) + LONG_L $13, PT_R13(sp) + LONG_L $14, PT_R14(sp) + LONG_L $15, PT_R15(sp) + LONG_L $24, PT_R24(sp) + .endm - .macro RESTORE_TEMP - LONG_L $24, PT_LO(sp) - LONG_L $8, PT_R8(sp) - LONG_L $9, PT_R9(sp) - mtlo $24 - LONG_L $24, PT_HI(sp) - LONG_L $10, PT_R10(sp) - LONG_L $11, PT_R11(sp) - mthi $24 - LONG_L $12, PT_R12(sp) - LONG_L $13, PT_R13(sp) - LONG_L $14, PT_R14(sp) - LONG_L $15, PT_R15(sp) - LONG_L $24, PT_R24(sp) - .endm + .macro RESTORE_STATIC + LONG_L $16, PT_R16(sp) + LONG_L $17, PT_R17(sp) + LONG_L $18, PT_R18(sp) + LONG_L $19, PT_R19(sp) + LONG_L $20, PT_R20(sp) + LONG_L $21, PT_R21(sp) + LONG_L $22, PT_R22(sp) + LONG_L $23, PT_R23(sp) + LONG_L $30, PT_R30(sp) + .endm - .macro RESTORE_STATIC - LONG_L $16, PT_R16(sp) - LONG_L $17, PT_R17(sp) - LONG_L $18, PT_R18(sp) - LONG_L $19, PT_R19(sp) - LONG_L $20, PT_R20(sp) - LONG_L $21, PT_R21(sp) - LONG_L $22, PT_R22(sp) - LONG_L $23, PT_R23(sp) - LONG_L $30, PT_R30(sp) - .endm +#define STATMASK 0x1f - .macro RESTORE_SOME - .set push - .set reorder - .set noat - LONG_L v0, PT_STATUS(sp) - mtc0 v0, CP0_STATUS - LONG_L v1, PT_EPC(sp) - MTC0 v1, CP0_EPC - LONG_L $31, PT_R31(sp) - LONG_L $28, PT_R28(sp) - LONG_L $25, PT_R25(sp) - LONG_L $7, PT_R7(sp) - LONG_L $6, PT_R6(sp) - LONG_L $5, PT_R5(sp) - LONG_L $4, PT_R4(sp) - LONG_L $3, PT_R3(sp) - LONG_L $2, PT_R2(sp) - .set pop - .endm + .macro RESTORE_SOME + .set push + .set reorder + .set noat + mfc0 a0, CP0_STATUS + ori a0, STATMASK + xori a0, STATMASK + mtc0 a0, CP0_STATUS + li v1, (ST0_CU1 | ST0_FR | ST0_IM) + and a0, v1, a0 + LONG_L v0, PT_STATUS(sp) + li v1, ~(ST0_CU1 | ST0_FR | ST0_IM) + and v0, v1 + or v0, a0 + li v1, (ST0_KX | ST0_SX | ST0_UX) + or v0, v1 + mtc0 v0, CP0_STATUS + LONG_L v1, PT_EPC(sp) + MTC0 v1, CP0_EPC + LONG_L $31, PT_R31(sp) + LONG_L $28, PT_R28(sp) + LONG_L $25, PT_R25(sp) + LONG_L $7, PT_R7(sp) + LONG_L $6, PT_R6(sp) + LONG_L $5, PT_R5(sp) + LONG_L $4, PT_R4(sp) + LONG_L $3, PT_R3(sp) + LONG_L $2, PT_R2(sp) + .set pop + .endm - .macro RESTORE_SP_AND_RET - LONG_L sp, PT_R29(sp) - .set mips3 - eret - .set mips0 - .endm + .macro RESTORE_SP_AND_RET + LONG_L sp, PT_R29(sp) + eret + nop + .endm - .macro RESTORE_SP - LONG_L sp, PT_R29(sp) - .endm + .macro RESTORE_SP + LONG_L sp, PT_R29(sp) + .endm - .macro RESTORE_ALL - RESTORE_TEMP - RESTORE_STATIC - RESTORE_AT - RESTORE_SOME - RESTORE_SP - .endm + .macro RESTORE_ALL + RESTORE_TEMP + RESTORE_FPU + RESTORE_STATIC + RESTORE_AT + RESTORE_SOME + RESTORE_SP + .endm - .macro RESTORE_ALL_AND_RET - RESTORE_TEMP - RESTORE_STATIC - RESTORE_AT - RESTORE_SOME - RESTORE_SP_AND_RET - .endm + .macro RESTORE_ALL_AND_RET + RESTORE_TEMP + RESTORE_FPU + RESTORE_STATIC + RESTORE_AT + RESTORE_SOME + RESTORE_SP_AND_RET + .endm #endif /* end of __STACKFRAME_H__ */ diff --git a/libcpu/mips/gs232/SConscript b/libcpu/mips/gs232/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/mips/gs232/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/mips/gs232/cache.c b/libcpu/mips/gs232/cache.c new file mode 100644 index 0000000000..484d3816f4 --- /dev/null +++ b/libcpu/mips/gs232/cache.c @@ -0,0 +1,231 @@ +/* + * Cache Ops For Loongson GS232 + * + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2010-07-09 Bernard first version + * 2011-08-08 lgnq modified for LS1B + * 2015-07-08 chinesebear modified for loongson 1c + */ + +#include <rtthread.h> +#include <mips.h> + +#define K0BASE 0x80000000 +#define PRID_LS1C 0x4220 + +extern void Clear_TagLo (void); +extern void Invalidate_Icache_Ls1c(unsigned int); +extern void Invalidate_Dcache_ClearTag_Ls1c(unsigned int); +extern void Invalidate_Dcache_Fill_Ls1c(unsigned int); +extern void Writeback_Invalidate_Dcache(unsigned int); +extern void enable_cpu_cache(void); + +typedef struct cacheinfo_t +{ + unsigned int icache_size; + unsigned int dcache_size; + unsigned int icacheline_size; + unsigned int dcacheline_size; +} cacheinfo_t ; + +typedef struct cacheop_t +{ + void (*Clear_TagLo) (void); + void (*Invalidate_Icache) (unsigned int); + void (*Invalidate_Dcache_Fill) (unsigned int); + void (*Invalidate_Dcache_ClearTag) (unsigned int); + void (*Init_Cache)(void); +} cacheop_t ; + +static cacheop_t cacheop, *pcacheop; +static cacheinfo_t cacheinfo, *pcacheinfo; + +int identify_cpu(void) +{ + unsigned int cpu_id; + + pcacheop = &cacheop; + pcacheinfo = &cacheinfo; + + rt_kprintf("CPU configure: 0x%08x\n", read_c0_config()); + cpu_id = read_c0_prid(); + switch (cpu_id) + { + case PRID_LS1C: + rt_kprintf("CPU:Loongson 1C\n"); + pcacheop->Clear_TagLo = Clear_TagLo; + pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1c; + pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1c; + pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1c; + break; + default: + rt_kprintf("Unknown CPU type, system halted!\n"); + while (1) + { + ; + } + break; + } + + return 0; +} + +void probe_cache(void) +{ + unsigned int config1 = read_c0_config1(); + unsigned int icache_size, icache_line_size, icache_sets, icache_ways; + unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways; + + if ((icache_line_size = ((config1 >> 19) & 7))) + icache_line_size = 2 << icache_line_size; + else + icache_line_size = icache_line_size; + icache_sets = 64 << ((config1 >> 22) & 7); + icache_ways = 1 + ((config1 >> 16) & 7); + icache_size = icache_sets * icache_ways * icache_line_size; + + if ((dcache_line_size = ((config1 >> 10) & 7))) + dcache_line_size = 2 << dcache_line_size; + else + dcache_line_size = dcache_line_size; + dcache_sets = 64 << ((config1 >> 13) & 7); + dcache_ways = 1 + ((config1 >> 7) & 7); + dcache_size = dcache_sets * dcache_ways * dcache_line_size; + + rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size); + rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size); + + pcacheinfo->icache_size = icache_size; + pcacheinfo->dcache_size = dcache_size; + pcacheinfo->icacheline_size = icache_line_size; + pcacheinfo->dcacheline_size = dcache_line_size; + + return ; +} + +void invalidate_writeback_dcache_all(void) +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + + while (start < end) + { + Writeback_Invalidate_Dcache(start); //hit writeback invalidate + start += pcacheinfo->dcacheline_size; + } +} + +void invalidate_writeback_dcache(unsigned long addr, int size) +{ + unsigned long start, end; + + start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size); + end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size); + + while (start <end) + { + Writeback_Invalidate_Dcache(start); + start += pcacheinfo->dcacheline_size; + } +} + +void invalidate_icache_all(void) +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->icache_size); + + while (start < end) + { + pcacheop->Invalidate_Icache(start); + start += pcacheinfo->icacheline_size; + } +} + +void invalidate_dcache_all(void) +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + while (start <end) + { + Invalidate_Dcache_Fill_Ls1c(start); + start += pcacheinfo->icacheline_size; + } +} + +//with cache disabled +void init_dcache(void) +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + + while (start < end) + { + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; + } + +} + +void rt_hw_cache_init(void) +{ + unsigned int start, end; + + /* 1. identify cpu and probe cache */ + identify_cpu(); + probe_cache(); + + start = K0BASE; + end = (start + pcacheinfo->icache_size); + + /* + * 2. clear CP0 taglo/taghi register; + */ + pcacheop->Clear_TagLo(); + + /* + * 3. invalidate instruction cache; + */ + while (start < end) + { + pcacheop->Invalidate_Icache(start); //index invalidate icache + start += pcacheinfo->icacheline_size; + } + + /* + * 4. invalidate data cache; + */ + start = K0BASE; + end = (start + pcacheinfo->dcache_size); + while(start < end) + { + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; + } + + start = K0BASE; + while(start < end) + { + pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache + start += pcacheinfo->dcacheline_size; + } + + start = K0BASE; + while(start < end) + { + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; + } + + /* enable cache */ + enable_cpu_cache(); + rt_kprintf("enable cpu cache done\n"); + + return ; +} + + diff --git a/libcpu/mips/loongson_1c/cache.h b/libcpu/mips/gs232/cache.h index b5c2d4501e..381298e4df 100644 --- a/libcpu/mips/loongson_1c/cache.h +++ b/libcpu/mips/gs232/cache.h @@ -1,20 +1,19 @@ /* - * File : cache.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * Cache Ops For Loongson GS232 + * + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2010-07-09 Bernard first version - * 2011-08-08 lgnq modified for LS1B + * 2010-07-09 Bernard first version + * 2011-08-08 lgnq modified for LS1B + * 2015-07-08 chinesebear modified for loongson 1c */ + #ifndef __CACHE_H__ #define __CACHE_H__ - /* * Cache Operations */ diff --git a/libcpu/mips/loongson_1c/cache_gcc.S b/libcpu/mips/gs232/cache_gcc.S index af25c31ded..10a41652a3 100644 --- a/libcpu/mips/loongson_1c/cache_gcc.S +++ b/libcpu/mips/gs232/cache_gcc.S @@ -1,11 +1,7 @@ /* - * File : cache_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * Copyright (c) 2006-2019, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -13,13 +9,17 @@ * 2010-09-11 bernard port to Loongson SoC3210 * 2011-08-08 lgnq port to Loongson LS1B * 2015-07-08 chinesebear port to Loongson LS1C + * 2019-07-19 Zhou Yanjie clean up code */ -#include "../common/mipsregs.h" -#include "../common/mips.inc" -#include "../common/asm.h" + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ +#endif + +#include <mips.h> #include "cache.h" - .ent cache_init + .ent cache_init .global cache_init .set noreorder cache_init: @@ -69,84 +69,84 @@ cache_i4way: sllv t5, t4, t5 #if 0 la t0, memvar - sw t7, 0x0(t0) #ways - sw t5, 0x4(t0) #icache size - sw t6, 0x8(t0) #dcache size + sw t7, 0x0(t0) #ways + sw t5, 0x4(t0) #icache size + sw t6, 0x8(t0) #dcache size #endif ####part 3#### - .set mips3 - lui a0, 0x8000 - addu a1, $0, t5 - addu a2, $0, t6 + .set mips3 + lui a0, 0x8000 + addu a1, $0, t5 + addu a2, $0, t6 cache_init_d2way: #a0=0x80000000, a1=icache_size, a2=dcache_size #a3, v0 and v1 used as local registers - mtc0 $0, CP0_TAGHI - addu v0, $0, a0 - addu v1, a0, a2 + mtc0 $0, CP0_TAGHI + addu v0, $0, a0 + addu v1, a0, a2 1: slt a3, v0, v1 - beq a3, $0, 1f - nop - mtc0 $0, CP0_TAGLO - beq t7, 1, 4f - cache Index_Store_Tag_D, 0x0(v0) # 1 way - beq t7, 2 ,4f - cache Index_Store_Tag_D, 0x1(v0) # 2 way - cache Index_Store_Tag_D, 0x2(v0) # 4 way - cache Index_Store_Tag_D, 0x3(v0) + beq a3, $0, 1f + nop + mtc0 $0, CP0_TAGLO + beq t7, 1, 4f + cache Index_Store_Tag_D, 0x0(v0) # 1 way + beq t7, 2 ,4f + cache Index_Store_Tag_D, 0x1(v0) # 2 way + cache Index_Store_Tag_D, 0x2(v0) # 4 way + cache Index_Store_Tag_D, 0x3(v0) 4: beq $0, $0, 1b - addiu v0, v0, 0x20 + addiu v0, v0, 0x20 1: cache_flush_i2way: - addu v0, $0, a0 - addu v1, a0, a1 + addu v0, $0, a0 + addu v1, a0, a1 1: slt a3, v0, v1 - beq a3, $0, 1f - nop - beq t3, 1, 4f - cache Index_Invalidate_I, 0x0(v0) # 1 way - beq t3, 2, 4f - cache Index_Invalidate_I, 0x1(v0) # 2 way - cache Index_Invalidate_I, 0x2(v0) - cache Index_Invalidate_I, 0x3(v0) # 4 way + beq a3, $0, 1f + nop + beq t3, 1, 4f + cache Index_Invalidate_I, 0x0(v0) # 1 way + beq t3, 2, 4f + cache Index_Invalidate_I, 0x1(v0) # 2 way + cache Index_Invalidate_I, 0x2(v0) + cache Index_Invalidate_I, 0x3(v0) # 4 way 4: beq $0, $0, 1b - addiu v0, v0, 0x20 + addiu v0, v0, 0x20 1: cache_flush_d2way: - addu v0, $0, a0 - addu v1, a0, a2 + addu v0, $0, a0 + addu v1, a0, a2 1: slt a3, v0, v1 - beq a3, $0, 1f - nop - beq t7, 1, 4f - cache Index_Writeback_Inv_D, 0x0(v0) #1 way - beq t7, 2, 4f - cache Index_Writeback_Inv_D, 0x1(v0) # 2 way - cache Index_Writeback_Inv_D, 0x2(v0) - cache Index_Writeback_Inv_D, 0x3(v0) # 4 way + beq a3, $0, 1f + nop + beq t7, 1, 4f + cache Index_Writeback_Inv_D, 0x0(v0) #1 way + beq t7, 2, 4f + cache Index_Writeback_Inv_D, 0x1(v0) # 2 way + cache Index_Writeback_Inv_D, 0x2(v0) + cache Index_Writeback_Inv_D, 0x3(v0) # 4 way 4: beq $0, $0, 1b - addiu v0, v0, 0x20 + addiu v0, v0, 0x20 1: cache_init_finish: - jr t1 + jr t1 nop .set reorder - .end cache_init + .end cache_init ########################### # Enable CPU cache # ########################### LEAF(enable_cpu_cache) - .set noreorder - mfc0 t0, CP0_CONFIG - nop - and t0, ~0x03 - or t0, 0x03 - mtc0 t0, CP0_CONFIG - nop - .set reorder - j ra + .set noreorder + mfc0 t0, CP0_CONFIG + nop + and t0, ~0x03 + or t0, 0x03 + mtc0 t0, CP0_CONFIG + nop + .set reorder + j ra END (enable_cpu_cache) ########################### @@ -154,26 +154,26 @@ END (enable_cpu_cache) ########################### LEAF(disable_cpu_cache) - .set noreorder - mfc0 t0, CP0_CONFIG - nop - and t0, ~0x03 - or t0, 0x2 - mtc0 t0, CP0_CONFIG - nop - .set reorder - j ra + .set noreorder + mfc0 t0, CP0_CONFIG + nop + and t0, ~0x03 + or t0, 0x2 + mtc0 t0, CP0_CONFIG + nop + .set reorder + j ra END (disable_cpu_cache) /**********************************/ /* Invalidate Instruction Cache */ /**********************************/ LEAF(Clear_TagLo) - .set noreorder - mtc0 zero, CP0_TAGLO - nop - .set reorder - j ra + .set noreorder + mtc0 zero, CP0_TAGLO + nop + .set reorder + j ra END(Clear_TagLo) .set mips3 @@ -181,38 +181,38 @@ END(Clear_TagLo) /* Invalidate Instruction Cache */ /**********************************/ LEAF(Invalidate_Icache_Ls1c) - .set noreorder - cache Index_Invalidate_I,0(a0) - cache Index_Invalidate_I,1(a0) - cache Index_Invalidate_I,2(a0) - cache Index_Invalidate_I,3(a0) - .set reorder - j ra + .set noreorder + cache Index_Invalidate_I,0(a0) + cache Index_Invalidate_I,1(a0) + cache Index_Invalidate_I,2(a0) + cache Index_Invalidate_I,3(a0) + .set reorder + j ra END(Invalidate_Icache_Ls1c) /**********************************/ /* Invalidate Data Cache */ /**********************************/ LEAF(Invalidate_Dcache_ClearTag_Ls1c) - .set noreorder - cache Index_Store_Tag_D, 0(a0) # BDSLOT: clear tag - cache Index_Store_Tag_D, 1(a0) # BDSLOT: clear tag - .set reorder - j ra + .set noreorder + cache Index_Store_Tag_D, 0(a0) # BDSLOT: clear tag + cache Index_Store_Tag_D, 1(a0) # BDSLOT: clear tag + .set reorder + j ra END(Invalidate_Dcache_ClearTag_Ls1c) LEAF(Invalidate_Dcache_Fill_Ls1c) - .set noreorder - cache Index_Writeback_Inv_D, 0(a0) # BDSLOT: clear tag - cache Index_Writeback_Inv_D, 1(a0) # BDSLOT: clear tag - .set reorder - j ra + .set noreorder + cache Index_Writeback_Inv_D, 0(a0) # BDSLOT: clear tag + cache Index_Writeback_Inv_D, 1(a0) # BDSLOT: clear tag + .set reorder + j ra END(Invalidate_Dcache_Fill_Ls1c) LEAF(Writeback_Invalidate_Dcache) - .set noreorder - cache Hit_Writeback_Inv_D, (a0) - .set reorder - j ra + .set noreorder + cache Hit_Writeback_Inv_D, (a0) + .set reorder + j ra END(Writeback_Invalidate_Dcache) .set mips0 diff --git a/libcpu/mips/gs232/cpuinit_gcc.S b/libcpu/mips/gs232/cpuinit_gcc.S new file mode 100644 index 0000000000..3379d7dae4 --- /dev/null +++ b/libcpu/mips/gs232/cpuinit_gcc.S @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + */ + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ +#endif + +#include <mips.h> + + .section ".start", "ax" + .set noreorder + + .globl rt_cpu_early_init +rt_cpu_early_init: + jr ra + nop
\ No newline at end of file diff --git a/libcpu/mips/gs232/cpuport.c b/libcpu/mips/gs232/cpuport.c new file mode 100644 index 0000000000..1b13719449 --- /dev/null +++ b/libcpu/mips/gs232/cpuport.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2010-07-09 Bernard first version + * 2010-09-11 Bernard add CPU reset implementation + * 2015-07-06 chinesebear modified for loongson 1c + */ + +#include <rtthread.h> +#include "gs232.h" + +/** + * @addtogroup Loongson GS232 + */ + +/*@{*/ + +/** + * this function will reset CPU + * + */ +void rt_hw_cpu_reset(void) +{ + /* open the watch-dog */ + WDT_EN = 0x01; /* watch dog enable */ + WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ + WDT_SET = 0x01; /* watch dog start */ + + rt_kprintf("reboot system...\n"); + while (1); +} + +/** + * this function will shutdown CPU + * + */ +void rt_hw_cpu_shutdown(void) +{ + rt_kprintf("shutdown...\n"); + + while (1); +} + + +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define Hit_Writeback_Inv_D 0x15 + + +void flush_cache(unsigned long start_addr, unsigned long size) +{ + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); + + while (1) { + cache_op(Hit_Writeback_Inv_D, addr); + cache_op(Hit_Invalidate_I, addr); + if (addr == aend) + break; + addr += lsize; + } +} + + +/*@}*/ + diff --git a/libcpu/mips/gs232/gs232.h b/libcpu/mips/gs232/gs232.h new file mode 100644 index 0000000000..6e90f7ba66 --- /dev/null +++ b/libcpu/mips/gs232/gs232.h @@ -0,0 +1,67 @@ +/* + * Misc define for GS232 + * + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + */ + +#ifndef __GS232_H__ +#define __GS232_H__ + +#include <mips.h> + +#define INTC_BASE 0xBFD01040 + +#define GS232_INTC_CELLS 5 +#define GS232_NR_IRQS (32 * GS232_INTC_CELLS) + +#define GMAC0_BASE 0xBFE10000 +#define GMAC0_DMA_BASE 0xBFE11000 +#define GMAC1_BASE 0xBFE20000 +#define GMAC1_DMA_BASE 0xBFE21000 +#define I2C0_BASE 0xBFE58000 +#define PWM0_BASE 0xBFE5C000 +#define PWM1_BASE 0xBFE5C010 +#define PWM2_BASE 0xBFE5C020 +#define PWM3_BASE 0xBFE5C030 +#define WDT_BASE 0xBFE5C060 +#define RTC_BASE 0xBFE64000 +#define I2C1_BASE 0xBFE68000 +#define I2C2_BASE 0xBFE70000 +#define AC97_BASE 0xBFE74000 +#define NAND_BASE 0xBFE78000 +#define SPI_BASE 0xBFE80000 +#define CAN1_BASE 0xBF004300 +#define CAN0_BASE 0xBF004400 + +#ifndef __ASSEMBLY__ +#include <rthw.h> + +/* Watch Dog registers */ +#define WDT_EN HWREG32(WDT_BASE + 0x00) +#define WDT_SET HWREG32(WDT_BASE + 0x04) +#define WDT_TIMER HWREG32(WDT_BASE + 0x08) + +#define PLL_FREQ HWREG32(0xbfe78030) +#define PLL_DIV_PARAM HWREG32(0xbfe78034) + +struct gs232_intc_regs +{ + volatile unsigned int int_isr; + volatile unsigned int int_en; + volatile unsigned int int_set; + volatile unsigned int int_clr; /* offset 0x10*/ + volatile unsigned int int_pol; + volatile unsigned int int_edge; /* offset 0 */ +}; + +extern void rt_hw_timer_init(void); + +#endif + +#endif
\ No newline at end of file diff --git a/libcpu/mips/gs232/interrupt.c b/libcpu/mips/gs232/interrupt.c new file mode 100644 index 0000000000..f3e0f80763 --- /dev/null +++ b/libcpu/mips/gs232/interrupt.c @@ -0,0 +1,162 @@ +/* + * Interrupt handle for GS232 + * + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2010-10-15 Bernard first version + * 2010-10-15 lgnq modified for LS1B + * 2013-03-29 aozima Modify the interrupt interface implementations. + * 2015-07-06 chinesebear modified for loongson 1c + * 2019-12-04 Jiaxun Yang Generialize + */ + +#include <rtthread.h> +#include <rthw.h> +#include "gs232.h" + + +#define MAX_INTR (GS232_NR_IRQS) + +static struct rt_irq_desc irq_handle_table[MAX_INTR]; +void rt_interrupt_dispatch(void *ptreg); +void rt_hw_timer_handler(); + +static struct gs232_intc_regs volatile *gs232_hw0_icregs += (struct gs232_intc_regs volatile *)(INTC_BASE); + +/** + * @addtogroup Loongson GS232 + */ + +/*@{*/ + +static void rt_hw_interrupt_handler(int vector, void *param) +{ + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + rt_int32_t idx; + rt_int32_t i; + rt_uint32_t c0_status = 0; + + for (i=0; i < GS232_INTC_CELLS; i++) + { + /* Disable */ + (gs232_hw0_icregs+i)->int_en = 0x0; + /* Trigger active low */ + (gs232_hw0_icregs+i)->int_pol = -1; /* Must be done here */ + /* Make all interrupts level triggered */ + (gs232_hw0_icregs+i)->int_edge = 0x00000000; + /* Mask all interrupts */ + (gs232_hw0_icregs+i)->int_clr = 0xffffffff; + mips_unmask_cpu_irq(i + 2); + } + + rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table)); + for (idx = 0; idx < MAX_INTR; idx ++) + { + irq_handle_table[idx].handler = rt_hw_interrupt_handler; + } +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + /* mask interrupt */ + (gs232_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f)); +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + (gs232_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f)); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if (vector >= 0 && vector < MAX_INTR) + { + old_handler = irq_handle_table[vector].handler; + +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX); +#endif /* RT_USING_INTERRUPT_INFO */ + irq_handle_table[vector].handler = handler; + irq_handle_table[vector].param = param; + } + + return old_handler; +} + + +/** + * ִ Call ISR + * @IRQn ID of IRQ + */ +void gs232_do_IRQ(int IRQn) +{ + rt_isr_handler_t irq_func; + void *param; + + irq_func = irq_handle_table[IRQn].handler; + param = irq_handle_table[IRQn].param; + + irq_func(IRQn, param); + +#ifdef RT_USING_INTERRUPT_INFO + irq_handle_table[IRQn].counter++; +#endif + + return ; +} + + +void rt_do_mips_cpu_irq(rt_uint32_t ip) +{ + rt_uint32_t intstatus, irq, n; + + if (ip == 7) { + rt_hw_timer_handler(); + } else { + n = ip - 2; + /* Receive interrupt signal, compute the irq */ + intstatus = (gs232_hw0_icregs+n)->int_isr & (gs232_hw0_icregs+n)->int_en; + if (0 == intstatus) + return ; + + irq = __rt_ffs(intstatus) - 1; + gs232_do_IRQ((n<<5) + irq); + + /* ack interrupt */ + (gs232_hw0_icregs+n)->int_clr |= (1 << irq); + } +} + + +/*@}*/ + + diff --git a/libcpu/mips/gs232/ls1b.h b/libcpu/mips/gs232/ls1b.h new file mode 100644 index 0000000000..071a4aeb82 --- /dev/null +++ b/libcpu/mips/gs232/ls1b.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-08-08 lgnq first version + */ + +#ifndef __LS1B_H__ +#define __LS1B_H__ + +#include <gs232.h> + +#define LS1B_ACPI_IRQ 0 +#define LS1B_HPET_IRQ 1 +#define LS1B_UART0_IRQ 2 +#define LS1B_UART1_IRQ 3 +#define LS1B_UART2_IRQ 4 +#define LS1B_UART3_IRQ 5 +#define LS1B_CAN0_IRQ 6 +#define LS1B_CAN1_IRQ 7 +#define LS1B_SPI0_IRQ 8 +#define LS1B_SPI1_IRQ 9 +#define LS1B_AC97_IRQ 10 +#define LS1B_MS_IRQ 11 +#define LS1B_KB_IRQ 12 +#define LS1B_DMA0_IRQ 13 +#define LS1B_DMA1_IRQ 14 +#define LS1B_NAND_IRQ 15 +#define LS1B_I2C0_IRQ 16 +#define LS1B_I2C1_IRQ 17 +#define LS1B_PWM0_IRQ 18 +#define LS1B_PWM1_IRQ 19 +#define LS1B_PWM2_IRQ 20 +#define LS1B_PWM3_IRQ 21 +#define LS1B_LPC_IRQ 22 +#define LS1B_EHCI_IRQ 32 +#define LS1B_OHCI_IRQ 33 +#define LS1B_GMAC1_IRQ 34 +#define LS1B_GMAC2_IRQ 35 +#define LS1B_SATA_IRQ 36 +#define LS1B_GPU_IRQ 37 +#define LS1B_PCI_INTA_IRQ 38 +#define LS1B_PCI_INTB_IRQ 39 +#define LS1B_PCI_INTC_IRQ 40 +#define LS1B_PCI_INTD_IRQ 41 + +#define LS1B_GPIO_IRQ 64 +#define LS1B_GPIO_FIRST_IRQ 64 +#define LS1B_GPIO_IRQ_COUNT 96 +#define LS1B_GPIO_LAST_IRQ (LS1B_GPIO_FIRST_IRQ + LS1B_GPIO_IRQ_COUNT-1) + +#define INT_PCI_INTA (1<<6) +#define INT_PCI_INTB (1<<7) +#define INT_PCI_INTC (1<<8) +#define INT_PCI_INTD (1<<9) + +#define LS1B_LAST_IRQ 159 +#define MIPS_CPU_TIMER_IRQ 167 +#define LS1B_INTREG_BASE 0xbfd01040 + +#define LS1B_DMA_IRQ_BASE 168 +#define LS1B_DMA_IRQ_COUNT 16 + +#endif diff --git a/libcpu/mips/gs232/ls1c.h b/libcpu/mips/gs232/ls1c.h new file mode 100644 index 0000000000..54c7e36e99 --- /dev/null +++ b/libcpu/mips/gs232/ls1c.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-08-08 lgnq first version + * 2015-07-06 chinesebear modified for loongson 1c + */ + +#ifndef __LS1C_H__ +#define __LS1C_H__ + +#include <gs232.h> + +#define LS1C_ACPI_IRQ 0 +#define LS1C_HPET_IRQ 1 +//#define LS1C_UART0_IRQ 3 // linux����3��v1.4�汾��1c�ֲ�����2�������Σ���ȷ�� +#define LS1C_UART1_IRQ 4 +#define LS1C_UART2_IRQ 5 +#define LS1C_CAN0_IRQ 6 +#define LS1C_CAN1_IRQ 7 +#define LS1C_SPI0_IRQ 8 +#define LS1C_SPI1_IRQ 9 +#define LS1C_AC97_IRQ 10 +#define LS1C_MS_IRQ 11 +#define LS1C_KB_IRQ 12 +#define LS1C_DMA0_IRQ 13 +#define LS1C_DMA1_IRQ 14 +#define LS1C_DMA2_IRQ 15 +#define LS1C_NAND_IRQ 16 +#define LS1C_PWM0_IRQ 17 +#define LS1C_PWM1_IRQ 18 +#define LS1C_PWM2_IRQ 19 +#define LS1C_PWM3_IRQ 20 +#define LS1C_RTC_INT0_IRQ 21 +#define LS1C_RTC_INT1_IRQ 22 +#define LS1C_RTC_INT2_IRQ 23 +#define LS1C_UART3_IRQ 29 +#define LS1C_ADC_IRQ 30 +#define LS1C_SDIO_IRQ 31 + + +#define LS1C_EHCI_IRQ (32+0) +#define LS1C_OHCI_IRQ (32+1) +#define LS1C_OTG_IRQ (32+2) +#define LS1C_MAC_IRQ (32+3) +#define LS1C_CAM_IRQ (32+4) +#define LS1C_UART4_IRQ (32+5) +#define LS1C_UART5_IRQ (32+6) +#define LS1C_UART6_IRQ (32+7) +#define LS1C_UART7_IRQ (32+8) +#define LS1C_UART8_IRQ (32+9) +#define LS1C_UART9_IRQ (32+13) +#define LS1C_UART10_IRQ (32+14) +#define LS1C_UART11_IRQ (32+15) +#define LS1C_I2C2_IRQ (32+17) +#define LS1C_I2C1_IRQ (32+18) +#define LS1C_I2C0_IRQ (32+19) + + +#define LS1C_GPIO_IRQ 64 +#define LS1C_GPIO_FIRST_IRQ 64 +#define LS1C_GPIO_IRQ_COUNT 96 +#define LS1C_GPIO_LAST_IRQ (LS1C_GPIO_FIRST_IRQ + LS1C_GPIO_IRQ_COUNT-1) + + +#define LS1C_LAST_IRQ 159 +#define LS1C_INTREG_BASE 0xbfd01040 + +// ��о1c���жϷ�Ϊ���飬ÿ��32�� +#define LS1C_NR_IRQS (32*5) + + +// GPIO��ź��жϺ�֮��Ļ���ת�� +#define LS1C_GPIO_TO_IRQ(GPIOn) (LS1C_GPIO_FIRST_IRQ + (GPIOn)) +#define LS1C_IRQ_TO_GPIO(IRQn) ((IRQn) - LS1C_GPIO_FIRST_IRQ) + +#endif + diff --git a/libcpu/mips/gs232/mipscfg.c b/libcpu/mips/gs232/mipscfg.c new file mode 100644 index 0000000000..85e0e633ea --- /dev/null +++ b/libcpu/mips/gs232/mipscfg.c @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2010-05-27 swkyer first version + */ +#include <rtthread.h> +#include <mips.h> + +mips32_core_cfg_t g_mips_core = +{ + 16, /* icache_line_size */ + 256, /* icache_lines_per_way */ + 4, /* icache_ways */ + 16, /* dcache_line_size */ + 256, /* dcache_lines_per_way */ + 4, /* dcache_ways */ + 16, /* max_tlb_entries */ +}; + +static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) +{ + rt_uint16_t rets = 1; + + while (n--) + rets *= b; + + return rets; +} + +static rt_uint16_t m_log2(rt_uint16_t b) +{ + rt_uint16_t rets = 0; + + while (b != 1) + { + b /= 2; + rets++; + } + + return rets; +} + +/** + * read core attribute + */ +void mips32_cfg_init(void) +{ + rt_uint16_t val; + rt_uint32_t cp0_config1; + + cp0_config1 = read_c0_config(); + if (cp0_config1 & 0x80000000) + { + cp0_config1 = read_c0_config1(); + + val = (cp0_config1 & (7<<22))>>22; + g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<19))>>19; + g_mips_core.icache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<16))>>16; + g_mips_core.icache_ways = val + 1; + + val = (cp0_config1 & (7<<13))>>13; + g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<10))>>10; + g_mips_core.dcache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<7))>>7; + g_mips_core.dcache_ways = val + 1; + + val = (cp0_config1 & (0x3F<<25))>>25; + g_mips_core.max_tlb_entries = val + 1; + } +} diff --git a/libcpu/mips/gs232/timer.c b/libcpu/mips/gs232/timer.c new file mode 100644 index 0000000000..8879b82ccf --- /dev/null +++ b/libcpu/mips/gs232/timer.c @@ -0,0 +1,41 @@ +/* + * Assembly Macros For MIPS + * + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + */ + +#include <rtthread.h> +#include <rthw.h> +#include <mips.h> +#include <board.h> + +/** + * This is the timer interrupt service routine. + */ +void rt_hw_timer_handler(void) +{ + unsigned int count; + + count = read_c0_compare(); + write_c0_compare(count); + write_c0_count(0); + + /* increase a OS tick */ + rt_tick_increase(); +} + +/** + * This function will initial OS timer + */ +void rt_hw_timer_init(void) +{ + write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND); + write_c0_count(0); + mips_unmask_cpu_irq(7); +}
\ No newline at end of file diff --git a/libcpu/mips/gs264/SConscript b/libcpu/mips/gs264/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/mips/gs264/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/mips/gs264/cache.c b/libcpu/mips/gs264/cache.c new file mode 100644 index 0000000000..54d38d0d3f --- /dev/null +++ b/libcpu/mips/gs264/cache.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-29 quanzhao the first version + * 2020-07-26 lizhirui porting to ls2k + */ + +#include <rthw.h> +#include <rtdef.h> + +rt_inline rt_uint64_t rt_cpu_icache_line_size(void) +{ + rt_uint64_t ctr; + return 4 << (ctr & 0xF); +} + +rt_inline rt_uint64_t rt_cpu_dcache_line_size(void) +{ + rt_uint64_t ctr; + return 4 << ((ctr >> 16) & 0xF); +} + +void rt_hw_cpu_icache_invalidate(void *addr, int size) +{ + rt_uint64_t line_size = rt_cpu_icache_line_size(); + rt_uint64_t start_addr = (rt_uint64_t)addr; + rt_uint64_t end_addr = (rt_uint64_t) addr + size + line_size - 1; +} + +void rt_hw_cpu_dcache_invalidate(void *addr, int size) +{ + rt_uint64_t line_size = rt_cpu_dcache_line_size(); + rt_uint64_t start_addr = (rt_uint64_t)addr; + rt_uint64_t end_addr = (rt_uint64_t) addr + size + line_size - 1; +} + +void rt_hw_cpu_dcache_clean(void *addr, int size) +{ + rt_uint64_t line_size = rt_cpu_dcache_line_size(); + rt_uint64_t start_addr = (rt_uint64_t)addr; + rt_uint64_t end_addr = (rt_uint64_t) addr + size + line_size - 1; +} + +void rt_hw_cpu_icache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_INVALIDATE) + rt_hw_cpu_icache_invalidate(addr, size); +} + +void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_FLUSH) + rt_hw_cpu_dcache_clean(addr, size); + else if (ops == RT_HW_CACHE_INVALIDATE) + rt_hw_cpu_dcache_invalidate(addr, size); +} + +rt_base_t rt_hw_cpu_icache_status(void) +{ + return 0; +} + +rt_base_t rt_hw_cpu_dcache_status(void) +{ + return 0; +} diff --git a/libcpu/mips/gs264/cache.h b/libcpu/mips/gs264/cache.h new file mode 100644 index 0000000000..10a4afd899 --- /dev/null +++ b/libcpu/mips/gs264/cache.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-03-25 quanzhao the first version + */ +#ifndef __CACHE_H__ +#define __CACHE_H__ + +unsigned long rt_cpu_get_smp_id(void); + +void rt_cpu_mmu_disable(void); +void rt_cpu_mmu_enable(void); +void rt_cpu_tlb_set(volatile unsigned long*); + +void rt_cpu_dcache_clean_flush(void); +void rt_cpu_icache_flush(void); + +void rt_cpu_vector_set_base(unsigned int addr); + +#endif diff --git a/libcpu/mips/gs264/cpuinit_gcc.S b/libcpu/mips/gs264/cpuinit_gcc.S new file mode 100644 index 0000000000..592fedd88a --- /dev/null +++ b/libcpu/mips/gs264/cpuinit_gcc.S @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-05 bigmagic Initial version + */ + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ +#endif + +#include <mips.h> + + .section ".text", "ax" + .set noreorder + + .globl rt_cpu_early_init +rt_cpu_early_init: + mfc0 t0, CP0_CONFIG + ori t0, 3 + mtc0 t0, CP0_CONFIG + ehb + jr ra diff --git a/libcpu/mips/gs264/mips_mmu.c b/libcpu/mips/gs264/mips_mmu.c new file mode 100644 index 0000000000..7bed69596a --- /dev/null +++ b/libcpu/mips/gs264/mips_mmu.c @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-26 lizhirui the first version + */ + +#include <string.h> +#include <stdlib.h> + +#include "mips.h" +#include "mips_mmu.h" + +void mmu_init() +{ + uint32_t status = read_c0_status(); + status |= 0x07 << 5;//ux = 1,sx = 1,kx = 1 + write_c0_status(status); + + mmu_clear_tlb(); + mmu_clear_itlb(); +} + +void mmu_set_cpu_mode(cpu_mode_t cpu_mode) +{ + uint32_t status = read_c0_status(); + status &= ~(0x03 << 3); + status |= ((uint32_t)cpu_mode & 0x03) << 3; + write_c0_status(status); +} + +cpu_mode_t mmu_get_cpu_mode() +{ + uint32_t status = read_c0_status(); + return (cpu_mode_t)((status >> 3) & 0x03); +} + +void mmu_clear_tlb() +{ + uint32_t max_tlb_index = mmu_get_max_tlb_index(); + uint64_t va = KSEG0BASE; + uint32_t entry; + tlb_item_t tlb_item; + + for(entry = 0;entry <= max_tlb_index;entry++) + { + mmu_tlb_item_init(&tlb_item); + mmu_tlb_write_indexed(entry,&tlb_item); + } +} + +void mmu_clear_itlb() +{ + uint32_t diag = read_c0_diag(); + write_c0_diag(diag | (0x01 << 2));//write ITLB bit + read_c0_entrylo0(); +} + +uint32_t mmu_get_max_tlb_index() +{ + uint32_t config1 = read_c0_config1(); + return ((config1 >> 25) & 0x3F); +} + +void mmu_tlb_write_indexed(uint32_t index,tlb_item_t *tlb_item) +{ + tlb_item -> entry_lo[0].g |= tlb_item -> entry_lo[1].g; + tlb_item -> entry_lo[1].g |= tlb_item -> entry_lo[0].g; + mmu_tlb_set_index(index); + write_c0_entrylo0(reg_type_convert(tlb_item -> entry_lo[0],uint64_t)); + write_c0_entrylo1(reg_type_convert(tlb_item -> entry_lo[1],uint64_t)); + write_c0_entryhi(reg_type_convert(tlb_item -> entry_hi,uint64_t)); + write_c0_pagemask(reg_type_convert(tlb_item -> page_mask,uint64_t)); + tlb_write_indexed(); + read_c0_entrylo0(); +} + +void mmu_tlb_write_random(tlb_item_t *tlb_item) +{ + tlb_item -> entry_lo[0].g |= tlb_item -> entry_lo[1].g; + tlb_item -> entry_lo[1].g |= tlb_item -> entry_lo[0].g; + write_c0_entrylo0(reg_type_convert(tlb_item -> entry_lo[0],uint64_t)); + write_c0_entrylo1(reg_type_convert(tlb_item -> entry_lo[1],uint64_t)); + write_c0_entryhi(reg_type_convert(tlb_item -> entry_hi,uint64_t)); + write_c0_pagemask(reg_type_convert(tlb_item -> page_mask,uint64_t)); + tlb_write_random(); + read_c0_entrylo0(); +} + +void mmu_tlb_read(uint32_t index,tlb_item_t *tlb_item) +{ + mmu_tlb_set_index(index); + tlb_read(); + uint64_t entrylo[2]; + uint64_t entryhi; + uint64_t page_mask; + entrylo[0] = read_c0_entrylo0(); + entrylo[1] = read_c0_entrylo1(); + entryhi = read_c0_entryhi(); + page_mask = read_c0_pagemask(); + tlb_item -> entry_lo[0] = reg_type_convert(entrylo[0],entry_lo_t); + tlb_item -> entry_lo[1] = reg_type_convert(entrylo[1],entry_lo_t); + tlb_item -> entry_hi = reg_type_convert(entryhi,entry_hi_t); + tlb_item -> page_mask = reg_type_convert(page_mask,page_mask_t); +} + +uint32_t mmu_tlb_find(uint64_t vpn,uint32_t asid,uint32_t *index) +{ + entry_hi_t entry_hi; + entry_hi.r = (vpn >> 62) & 0x03; + entry_hi.vpn2 = (vpn >> 13) & 0x7FFFFFFU; + entry_hi.asid = asid & 0xFFU; + tlb_item_t tlb_item; + //mmu_tlb_read(6,&tlb_item); + //tlb_dump(); + mmu_tlb_item_init(&tlb_item); + tlb_item.entry_lo[0].g = tlb_item.entry_lo[1].g = 1; + read_c0_entrylo0();//i don't know why,but if i don't read any register of mmu,tplb will be failed in qemu. + write_c0_entrylo0(reg_type_convert(tlb_item.entry_lo[0],uint64_t)); + write_c0_entrylo1(reg_type_convert(tlb_item.entry_lo[1],uint64_t)); + write_c0_entryhi(reg_type_convert(entry_hi,uint64_t)); + //__asm__ __volatile__("ehb"); + //read_c0_entryhi(); + //rt_kprintf("entry_hi = %p\n",read_c0_entryhi()); + tlb_probe(); + *index = mmu_tlb_get_index(); + return mmu_tlb_is_matched(); +} + +void mmu_tlb_item_init(tlb_item_t *tlb_item) +{ + memset(tlb_item,0,sizeof(tlb_item_t)); + tlb_item -> entry_lo[0].c = 0x03; + tlb_item -> entry_lo[1].c = 0x03; +} + +void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t asid,uint32_t global) +{ + uint64_t page_mask_v = (uint64_t)page_mask; + + /*if(page_mask_v & (1 << 13)) + { + page_mask_v |= (1 << 12); + }*/ + + uint64_t lb = lowbit((~(page_mask_v)) << 12); + uint64_t pn_remained = ((~(page_mask_v)) << 12) | lb; + vpn &= pn_remained; + ppn &= pn_remained; + uint64_t odd_vpn = vpn | lb; + uint64_t even_vpn = vpn & (~lb); + uint32_t index; + tlb_item_t tlb_item,tlb2_item; + + mmu_tlb_item_init(&tlb_item); + mmu_tlb_item_init(&tlb2_item); + tlb_item.page_mask.mask = page_mask; + + if(mmu_tlb_find(vpn & (~lb),asid,&index)) + { + mmu_tlb_read(index,&tlb_item); + mmu_tlb_write_indexed(index,&tlb2_item); + } + + entry_lo_t *entry_lo = &tlb_item.entry_lo[vpn == even_vpn ? 0 : 1]; + tlb_item.entry_lo[0].g = tlb_item.entry_lo[1].g = global; + entry_lo -> d = 1; + entry_lo -> ri = 0; + entry_lo -> xi = 0; + entry_lo -> v = 1; + entry_lo -> pfn = ppn >> 12; + tlb_item.entry_hi.r = (vpn >> 62) & 0x03; + tlb_item.entry_hi.vpn2 = (vpn >> 13) & 0x7FFFFFFU; + tlb_item.entry_hi.asid = asid & 0xFFU; + mmu_tlb_write_random(&tlb_item); +} + +uint32_t mmu_tlb_get_random() +{ + return read_c0_random(); +} + +uint32_t mmu_tlb_get_index() +{ + return read_c0_index() & 0x3F; +} + +void mmu_tlb_set_index(uint32_t index) +{ + write_c0_index(index & 0x3F); +} + +uint32_t mmu_tlb_is_matched() +{ + return (read_c0_index() & 0x80000000) == 0; +} + +uint64_t mmu_tlb_get_bad_vaddr() +{ + return read_c0_badvaddr(); +} + +void tlb_dump() +{ + uint32_t max_index = mmu_get_max_tlb_index(); + //uint32_t max_index = 10; + uint32_t entry; + tlb_item_t tlb_item; + + for(entry = 0;entry <= max_index;entry++) + { + mmu_tlb_read(entry,&tlb_item); + //mmu_tlb_write_indexed(entry,&tlb_item); + //mmu_tlb_read(entry,&tlb_item); + rt_kprintf("vpn = 0x%p,ppn0 = 0x%p,ppn1 = 0x%p\n",(uint64_t)tlb_item.entry_hi.vpn2 << 13 | (uint64_t)tlb_item.entry_hi.asid << 62,(uint64_t)tlb_item.entry_lo[0].pfn << 12,(uint64_t)tlb_item.entry_lo[1].pfn << 12); + rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[0].v,tlb_item.entry_lo[0].d,tlb_item.entry_lo[0].g,tlb_item.entry_lo[0].ri,tlb_item.entry_lo[0].xi,tlb_item.entry_lo[0].c); + rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[1].v,tlb_item.entry_lo[1].d,tlb_item.entry_lo[1].g,tlb_item.entry_lo[1].ri,tlb_item.entry_lo[1].xi,tlb_item.entry_lo[1].c); + } +} diff --git a/libcpu/mips/gs264/mips_mmu.h b/libcpu/mips/gs264/mips_mmu.h new file mode 100644 index 0000000000..fcbcef3621 --- /dev/null +++ b/libcpu/mips/gs264/mips_mmu.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-26 lizhirui the first version + */ +#ifndef __MIPS_MMU_H__ +#define __MIPS_MMU_H__ + +typedef enum cpu_mode_t +{ + CPU_MODE_KERNEL = 0x00, + CPU_MODE_SUPERVISOR = 0x01, + CPU_MODE_USER = 0x02 +}cpu_mode_t; + +typedef enum page_mask_enum_t +{ + PAGE_MASK_4KB = 0x00, + PAGE_MASK_16KB = 0x03, + PAGE_MASK_64KB = 0x0F, + PAGE_MASK_256KB = 0x3F, + PAGE_MASK_1MB = 0xFF, + PAGE_MASK_4MB = 0x3FF, + PAGE_MASK_16MB = 0xFFF, + PAGE_MASK_64MB = 0x3FFF, + PAGE_MASK_256MB = 0xFFFF, + PAGE_MASK_1GB = 0x3FFFF +}page_mask_enum_t; + +typedef struct page_mask_t +{ + uint64_t : 11; + uint64_t : 2; + uint64_t mask : 18; + uint64_t : 33; +}page_mask_t; + +typedef struct entry_lo_t +{ + uint64_t g : 1; + uint64_t v : 1; + uint64_t d : 1; + uint64_t c : 3; + uint64_t pfn : 24; + uint64_t pfnx : 3; + uint64_t : 29; + uint64_t xi : 1; + uint64_t ri : 1; +}entry_lo_t; + +typedef struct entry_hi_t +{ + uint64_t asid : 8; + uint64_t : 5; + uint64_t vpn2 : 27; + uint64_t : 22; + uint64_t r : 2; +}entry_hi_t; + +typedef struct tlb_item_t +{ + entry_lo_t entry_lo[2]; + entry_hi_t entry_hi; + page_mask_t page_mask; +}tlb_item_t; + +#define read_c0_diag() __read_32bit_c0_register($22, 0) +#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) +#define read_c0_badvaddr() __read_64bit_c0_register($8, 0) +#define read_c0_random() __read_32bit_c0_register($1, 0) + +#define reg_type_convert(variable,new_type) *((new_type *)(&variable)) +#define lowbit(x) ((x) & (-(x))) + +void mmu_init(); +void mmu_set_cpu_mode(cpu_mode_t cpu_mode); +cpu_mode_t mmu_get_cpu_mode(); +void mmu_clear_tlb(); +void mmu_clear_itlb(); +uint32_t mmu_get_max_tlb_index(); +void mmu_tlb_write_indexed(uint32_t index,tlb_item_t *tlb_item); +void mmu_tlb_write_random(tlb_item_t *tlb_item); +void mmu_tlb_read(uint32_t index,tlb_item_t *tlb_item); +uint32_t mmu_tlb_find(uint64_t vpn,uint32_t asid,uint32_t *index); +void mmu_tlb_item_init(tlb_item_t *tlb_item); +void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t asid,uint32_t global); +uint32_t mmu_tlb_get_random(); +uint32_t mmu_tlb_get_index(); +void mmu_tlb_set_index(uint32_t index); +uint32_t mmu_tlb_is_matched(); +uint64_t mmu_tlb_get_bad_vaddr(); + +void tlb_dump(); + +#endif
\ No newline at end of file diff --git a/libcpu/mips/gs264/mipscfg.c b/libcpu/mips/gs264/mipscfg.c new file mode 100644 index 0000000000..b2aed120ae --- /dev/null +++ b/libcpu/mips/gs264/mipscfg.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-28 lizhirui first version + */ +#include <rtthread.h> +#include <mips.h> + +mips32_core_cfg_t g_mips_core = +{ + 64, /* icache_line_size */ + 128, /* icache_lines_per_way */ + 4, /* icache_ways */ + 32768, + 64, /* dcache_line_size */ + 128, /* dcache_lines_per_way */ + 4, /* dcache_ways */ + 32768, + 64, /* max_tlb_entries */ +}; + +static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) +{ + rt_uint16_t rets = 1; + + while (n--) + rets *= b; + + return rets; +} + +static rt_uint16_t m_log2(rt_uint16_t b) +{ + rt_uint16_t rets = 0; + + while (b != 1) + { + b /= 2; + rets++; + } + + return rets; +} + +/** + * read core attribute + */ +void mips32_cfg_init(void) +{ + rt_uint16_t val; + rt_uint32_t cp0_config1; + + cp0_config1 = read_c0_config(); + if (cp0_config1 & 0x80000000) + { + cp0_config1 = read_c0_config1(); + + val = (cp0_config1 & (7<<22))>>22; + g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<19))>>19; + g_mips_core.icache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<16))>>16; + g_mips_core.icache_ways = val + 1; + + val = (cp0_config1 & (7<<13))>>13; + g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<10))>>10; + g_mips_core.dcache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<7))>>7; + g_mips_core.dcache_ways = val + 1; + + val = (cp0_config1 & (0x3F<<25))>>25; + g_mips_core.max_tlb_entries = val + 1; + } +} diff --git a/libcpu/mips/gs264/mmu.c b/libcpu/mips/gs264/mmu.c new file mode 100644 index 0000000000..b5bedace50 --- /dev/null +++ b/libcpu/mips/gs264/mmu.c @@ -0,0 +1,819 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2012-01-10 bernard porting to AM1808 + * 2020-07-26 lizhirui porting to ls2k + */ + +#include <rtthread.h> +#include <rthw.h> +#include <board.h> + +#include "cache.h" +#include "mips_mmu.h" +#include "mmu.h" + +void *current_mmu_table = RT_NULL; + +void *mmu_table_get() +{ + return current_mmu_table; +} + +void switch_mmu(void *mmu_table) +{ + current_mmu_table = mmu_table; + + mmu_clear_tlb(); + mmu_clear_itlb(); +} + +/* dump 2nd level page table */ +void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb) +{ + int i; + int fcnt = 0; + + for (i = 0; i < 256; i++) + { + rt_uint32_t pte2 = ptb[i]; + if ((pte2 & 0x3) == 0) + { + if (fcnt == 0) + rt_kprintf(" "); + rt_kprintf("%04x: ", i); + fcnt++; + if (fcnt == 16) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + continue; + } + if (fcnt != 0) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + + rt_kprintf(" %04x: %x: ", i, pte2); + if ((pte2 & 0x3) == 0x1) + { + rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n", + ((pte2 >> 7) | (pte2 >> 4))& 0xf, + (pte2 >> 15) & 0x1, + ((pte2 >> 10) | (pte2 >> 2)) & 0x1f); + } + else + { + rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n", + ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1, + ((pte2 >> 4) | (pte2 >> 2)) & 0x1f); + } + } +} + +void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb) +{ + int i; + int fcnt = 0; + + rt_kprintf("page table@%p\n", ptb); + for (i = 0; i < 1024*4; i++) + { + rt_uint32_t pte1 = ptb[i]; + if ((pte1 & 0x3) == 0) + { + rt_kprintf("%03x: ", i); + fcnt++; + if (fcnt == 16) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + continue; + } + if (fcnt != 0) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + + rt_kprintf("%03x: %08x: ", i, pte1); + if ((pte1 & 0x3) == 0x3) + { + rt_kprintf("LPAE\n"); + } + else if ((pte1 & 0x3) == 0x1) + { + rt_kprintf("pte,ns:%d,domain:%d\n", + (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf); + /* + *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000) + * - 0x80000000 + 0xC0000000)); + */ + } + else if (pte1 & (1 << 18)) + { + rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10))& 0xf, + (pte1 >> 4) & 0x1, + ((pte1 >> 10) | (pte1 >> 2)) & 0x1f); + } + else + { + rt_kprintf("section,ns:%d,ap:%x," + "xn:%d,texcb:%02x,domain:%d\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10))& 0xf, + (pte1 >> 4) & 0x1, + (((pte1 & (0x7 << 12)) >> 10) | + ((pte1 & 0x0c) >> 2)) & 0x1f, + (pte1 >> 5) & 0xf); + } + } +} + +/* level1 page table, each entry for 1MB memory. */ +volatile unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024))); +void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart, + rt_uint32_t vaddrEnd, + rt_uint32_t paddrStart, + rt_uint32_t attr) +{ + volatile rt_uint32_t *pTT; + volatile int i, nSec; + pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20); + nSec = (vaddrEnd >> 20) - (vaddrStart >> 20); + for(i = 0; i <= nSec; i++) + { + *pTT = attr | (((paddrStart >> 20) + i) << 20); + pTT++; + } +} + +unsigned long rt_hw_set_domain_register(unsigned long domain_val) +{ + unsigned long old_domain; + + //asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain)); + //asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory"); + + return old_domain; +} + +void rt_hw_cpu_dcache_clean(void *addr, int size); +void rt_hw_init_mmu_table(struct mem_desc *mdesc, rt_uint32_t size) +{ + /* set page table */ + for(; size > 0; size--) + { + rt_hw_mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end, + mdesc->paddr_start, mdesc->attr); + mdesc++; + } + rt_hw_cpu_dcache_clean((void*)MMUTable, sizeof MMUTable); +} + +void rt_hw_mmu_init(void) +{ + rt_cpu_dcache_clean_flush(); + rt_cpu_icache_flush(); + rt_hw_cpu_dcache_disable(); + rt_hw_cpu_icache_disable(); + rt_cpu_mmu_disable(); + + /*rt_hw_cpu_dump_page_table(MMUTable);*/ + rt_hw_set_domain_register(0x55555555); + + rt_cpu_tlb_set(MMUTable); + + rt_cpu_mmu_enable(); + + rt_hw_cpu_icache_enable(); + rt_hw_cpu_dcache_enable(); +} + +/* + mem map +*/ + +void rt_hw_cpu_dcache_clean(void *addr, int size); + +int rt_hw_mmu_map_init(rt_mmu_info *mmu_info, void* v_address, size_t size, size_t *vtable, size_t pv_off) +{ + size_t l1_off, va_s, va_e; + rt_base_t level; + + if (!mmu_info || !vtable) + { + return -1; + } + + va_s = (size_t)v_address; + va_e = (size_t)v_address + size - 1; + + if ( va_e < va_s) + { + return -1; + } + + va_s >>= ARCH_SECTION_SHIFT; + va_e >>= ARCH_SECTION_SHIFT; + + if (va_s == 0) + { + return -1; + } + + level = rt_hw_interrupt_disable(); + + for (l1_off = va_s; l1_off <= va_e; l1_off++) + { + size_t v = vtable[l1_off]; + + if (v & ARCH_MMU_USED_MASK) + { + rt_kprintf("Error:vtable[%d] = 0x%p(is not zero),va_s = 0x%p,va_e = 0x%p!\n",l1_off,v,va_s,va_e); + rt_hw_interrupt_enable(level); + return -1; + } + } + + mmu_info->vtable = vtable; + mmu_info->vstart = va_s; + mmu_info->vend = va_e; + mmu_info->pv_off = pv_off; + + rt_hw_interrupt_enable(level); + + return 0; +} + +static size_t find_vaddr(rt_mmu_info *mmu_info, int pages) +{ + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; + size_t find_off = 0; + size_t find_va = 0; + int n = 0; + + if (!pages) + { + return 0; + } + + if (!mmu_info) + { + return 0; + } + + for (l1_off = mmu_info->vstart; l1_off <= mmu_info->vend; l1_off++) + { + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + if (*mmu_l1 & ARCH_MMU_USED_MASK) + { + mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); + for (l2_off = 0; l2_off < (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE); l2_off++) + { + if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK) + { + /* in use */ + n = 0; + } + else + { + if (!n) + { + find_va = l1_off; + find_off = l2_off; + } + n++; + if (n >= pages) + { + return (find_va << ARCH_SECTION_SHIFT) + (find_off << ARCH_PAGE_SHIFT); + } + } + } + } + else + { + if (!n) + { + find_va = l1_off; + find_off = 0; + } + n += (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE); + if (n >= pages) + { + return (find_va << ARCH_SECTION_SHIFT) + (find_off << ARCH_PAGE_SHIFT); + } + } + } + return 0; +} + +#ifdef RT_USING_USERSPACE +static int check_vaddr(rt_mmu_info *mmu_info, void *va, int pages) +{ + size_t loop_va = (size_t)va & ~ARCH_PAGE_MASK; + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; + + if (!pages) + { + return -1; + } + + if (!mmu_info) + { + return -1; + } + + while (pages--) + { + l1_off = (loop_va >> ARCH_SECTION_SHIFT); + l2_off = ((loop_va & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT); + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + + if (*mmu_l1 & ARCH_MMU_USED_MASK) + { + mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); + if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK) + { + return -1; + } + } + loop_va += ARCH_PAGE_SIZE; + } + return 0; +} +#endif + +static void __rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t npages) +{ + size_t loop_va = (size_t)v_addr & ~ARCH_PAGE_MASK; + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; + size_t *ref_cnt; + + if (!mmu_info) + { + return; + } + + while (npages--) + { + l1_off = (loop_va >> ARCH_SECTION_SHIFT); + if (l1_off < mmu_info->vstart || l1_off > mmu_info->vend) + { + return; + } + + l2_off = ((loop_va & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT); + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + + if (*mmu_l1 & ARCH_MMU_USED_MASK) + { + mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); + } + else + { + return; + } + + if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK) + { + *(mmu_l2 + l2_off) = 0; + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l2 + l2_off, 4); + + ref_cnt = mmu_l2 + (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE); + (*ref_cnt)--; + if (!*ref_cnt) + { +#ifdef RT_USING_USERSPACE + rt_pages_free(mmu_l2, 0); +#else + rt_free_align(mmu_l2); +#endif + *mmu_l1 = 0; + + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l1, 4); + } + } + loop_va += ARCH_PAGE_SIZE; + } +} + +static int __rt_hw_mmu_map(rt_mmu_info *mmu_info, void* v_addr, void* p_addr, size_t npages, size_t attr) +{ + size_t loop_va = (size_t)v_addr & ~ARCH_PAGE_MASK; + size_t loop_pa = (size_t)p_addr & ~ARCH_PAGE_MASK; + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; + size_t *ref_cnt; + + if (!mmu_info) + { + return -1; + } + + while (npages--) + { + l1_off = (loop_va >> ARCH_SECTION_SHIFT); + l2_off = ((loop_va & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT); + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + + if (*mmu_l1 & ARCH_MMU_USED_MASK) + { + mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); + } + else + { +#ifdef RT_USING_USERSPACE + mmu_l2 = (size_t*)rt_pages_alloc(0); +#else + mmu_l2 = (size_t*)rt_malloc_align(ARCH_PAGE_TBL_SIZE * 2, ARCH_PAGE_TBL_SIZE); +#endif + if (mmu_l2) + { + rt_memset(mmu_l2, 0, ARCH_PAGE_TBL_SIZE * 2); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l2, ARCH_PAGE_TBL_SIZE); + + *mmu_l1 = (((size_t)mmu_l2 + mmu_info->pv_off) | 0x1); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l1, 4); + } + else + { + /* error, unmap and quit */ + __rt_hw_mmu_unmap(mmu_info, v_addr, npages); + return -1; + } + } + + ref_cnt = mmu_l2 + (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE); + (*ref_cnt)++; + + *(mmu_l2 + l2_off) = (loop_pa | attr); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l2 + l2_off, 4); + + loop_va += ARCH_PAGE_SIZE; + loop_pa += ARCH_PAGE_SIZE; + } + return 0; +} + +static void rt_hw_cpu_tlb_invalidate(void) +{ + mmu_clear_tlb(); + mmu_clear_itlb(); +} + +#ifdef RT_USING_USERSPACE +void *_rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void* p_addr, size_t size, size_t attr) +{ + size_t pa_s, pa_e; + size_t vaddr; + int pages; + int ret; + + if (!size) + { + return 0; + } + pa_s = (size_t)p_addr; + pa_e = (size_t)p_addr + size - 1; + pa_s >>= ARCH_PAGE_SHIFT; + pa_e >>= ARCH_PAGE_SHIFT; + pages = pa_e - pa_s + 1; + if (v_addr) + { + vaddr = (size_t)v_addr; + pa_s = (size_t)p_addr; + if ((vaddr & ARCH_PAGE_MASK) != (pa_s & ARCH_PAGE_MASK)) + { + return 0; + } + vaddr &= ~ARCH_PAGE_MASK; + if (check_vaddr(mmu_info, (void*)vaddr, pages) != 0) + { + return 0; + } + } + else + { + vaddr = find_vaddr(mmu_info, pages); + } + if (vaddr) { + ret = __rt_hw_mmu_map(mmu_info, (void*)vaddr, p_addr, pages, attr); + if (ret == 0) + { + rt_hw_cpu_tlb_invalidate(); + return (void*)(vaddr + ((size_t)p_addr & ARCH_PAGE_MASK)); + } + } + return 0; +} +#else +void *_rt_hw_mmu_map(rt_mmu_info *mmu_info, void* p_addr, size_t size, size_t attr) +{ + size_t pa_s, pa_e; + size_t vaddr; + int pages; + int ret; + + pa_s = (size_t)p_addr; + pa_e = (size_t)p_addr + size - 1; + pa_s >>= ARCH_PAGE_SHIFT; + pa_e >>= ARCH_PAGE_SHIFT; + pages = pa_e - pa_s + 1; + vaddr = find_vaddr(mmu_info, pages); + if (vaddr) { + ret = __rt_hw_mmu_map(mmu_info, (void*)vaddr, p_addr, pages, attr); + if (ret == 0) + { + rt_hw_cpu_tlb_invalidate(); + return (void*)(vaddr + ((size_t)p_addr & ARCH_PAGE_MASK)); + } + } + return 0; +} +#endif + +#ifdef RT_USING_USERSPACE +static int __rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void* v_addr, size_t npages, size_t attr) +{ + size_t loop_va = (size_t)v_addr & ~ARCH_PAGE_MASK; + size_t loop_pa; + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; + size_t *ref_cnt; + + if (!mmu_info) + { + return -1; + } + + while (npages--) + { + loop_pa = (size_t)rt_pages_alloc(0) + mmu_info->pv_off; + if (!loop_pa) + goto err; + + //rt_kprintf("vaddr = %08x is mapped to paddr = %08x\n",v_addr,loop_pa); + l1_off = (loop_va >> ARCH_SECTION_SHIFT); + l2_off = ((loop_va & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT); + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + + if (*mmu_l1 & ARCH_MMU_USED_MASK) + { + mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); + } + else + { + //mmu_l2 = (size_t*)rt_malloc_align(ARCH_PAGE_TBL_SIZE * 2, ARCH_PAGE_TBL_SIZE); + mmu_l2 = (size_t*)rt_pages_alloc(0); + if (mmu_l2) + { + rt_memset(mmu_l2, 0, ARCH_PAGE_TBL_SIZE * 2); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l2, ARCH_PAGE_TBL_SIZE); + + *mmu_l1 = (((size_t)mmu_l2 + mmu_info->pv_off) | 0x1); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l1, 4); + } + else + goto err; + } + + ref_cnt = mmu_l2 + (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE); + (*ref_cnt)++; + + //loop_pa += mmu_info->pv_off; + *(mmu_l2 + l2_off) = (loop_pa | attr); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l2 + l2_off, 4); + + loop_va += ARCH_PAGE_SIZE; + } + return 0; +err: + { + /* error, unmap and quit */ + int i; + void *va, *pa; + + va = (void*)((size_t)v_addr & ~ARCH_PAGE_MASK); + for (i = 0; i < npages; i++) + { + pa = rt_hw_mmu_v2p(mmu_info, va); + pa -= mmu_info->pv_off; + rt_pages_free(pa, 0); + va += ARCH_PAGE_SIZE; + } + + __rt_hw_mmu_unmap(mmu_info, v_addr, npages); + return -1; + } +} + +void *_rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void *v_addr, size_t size, size_t attr) +{ + size_t vaddr; + size_t offset; + int pages; + int ret; + + if (!size) + { + return 0; + } + offset = (size_t)v_addr & ARCH_PAGE_MASK; + size += (offset + ARCH_PAGE_SIZE - 1); + pages = (size >> ARCH_PAGE_SHIFT); + if (v_addr) + { + vaddr = (size_t)v_addr; + vaddr &= ~ARCH_PAGE_MASK; + if (check_vaddr(mmu_info, (void*)vaddr, pages) != 0) + { + return 0; + } + } + else + { + vaddr = find_vaddr(mmu_info, pages); + } + if (vaddr) { + ret = __rt_hw_mmu_map_auto(mmu_info, (void*)vaddr, pages, attr); + if (ret == 0) + { + rt_hw_cpu_tlb_invalidate(); + return (void*)vaddr + offset; + } + } + return 0; +} +#endif + +void _rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t size) +{ + size_t va_s, va_e; + int pages; + + va_s = (size_t)v_addr; + va_e = (size_t)v_addr + size - 1; + va_s >>= ARCH_PAGE_SHIFT; + va_e >>= ARCH_PAGE_SHIFT; + pages = va_e - va_s + 1; + __rt_hw_mmu_unmap(mmu_info, v_addr, pages); + rt_hw_cpu_tlb_invalidate(); +} + +//va --> pa +void *rt_hw_kernel_virt_to_phys(void *v_addr, size_t size) +{ + void *p_addr = 0; + + return p_addr; +} + +//pa --> va +void *rt_hw_kernel_phys_to_virt(void *p_addr, size_t size) +{ + void *v_addr = 0; + + #ifdef RT_USING_USERSPACE + extern rt_mmu_info mmu_info; + v_addr = rt_hw_mmu_map(&mmu_info, 0, p_addr, size, MMU_MAP_K_RW); + #else + v_addr = p_addr; + #endif + + return v_addr; +} + +#ifdef RT_USING_USERSPACE +void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void* p_addr, size_t size, size_t attr) +{ + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_map(mmu_info, v_addr, p_addr, size, attr); + rt_hw_interrupt_enable(level); + return ret; +} + +void *rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void *v_addr, size_t size, size_t attr) +{ + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_map_auto(mmu_info, v_addr, size, attr); + rt_hw_interrupt_enable(level); + return ret; +} +#endif + +void rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t size) +{ + rt_base_t level; + + level = rt_hw_interrupt_disable(); + _rt_hw_mmu_unmap(mmu_info, v_addr, size); + rt_hw_interrupt_enable(level); +} + +void *_rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void* v_addr) +{ + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; + size_t tmp; + size_t pa; + + l1_off = (size_t)v_addr >> ARCH_SECTION_SHIFT; + + if (!mmu_info) + { + return (void*)0; + } + + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + + tmp = *mmu_l1; + + switch (tmp & ARCH_MMU_USED_MASK) + { + case 0: /* not used */ + break; + case 1: /* page table */ + mmu_l2 = (size_t *)((tmp & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); + l2_off = (((size_t)v_addr & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT); + pa = *(mmu_l2 + l2_off); + if (pa & ARCH_MMU_USED_MASK) + { + if ((pa & ARCH_MMU_USED_MASK) == 1) + { + /* lage page, not support */ + break; + } + pa &= ~(ARCH_PAGE_MASK); + pa += ((size_t)v_addr & ARCH_PAGE_MASK); + return (void*)pa; + } + break; + case 2: + case 3: + /* section */ + if (tmp & ARCH_TYPE_SUPERSECTION) + { + /* super section, not support */ + break; + } + pa = (tmp & ~ARCH_SECTION_MASK); + pa += ((size_t)v_addr & ARCH_SECTION_MASK); + return (void*)pa; + } + return (void*)0; +} + +void *rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void* v_addr) +{ + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_v2p(mmu_info, v_addr); + rt_hw_interrupt_enable(level); + return ret; +} + +#ifdef RT_USING_USERSPACE +void init_mm_setup(unsigned int *mtbl, unsigned int size, unsigned int pv_off) { + unsigned int va; + + for (va = 0; va < 0x1000; va++) { + unsigned int vaddr = (va << 20); + if (vaddr >= KERNEL_VADDR_START && vaddr - KERNEL_VADDR_START < size) { + mtbl[va] = ((va << 20) + pv_off) | NORMAL_MEM; + } else if (vaddr >= (KERNEL_VADDR_START + pv_off) && vaddr - (KERNEL_VADDR_START + pv_off) < size) { + mtbl[va] = (va << 20) | NORMAL_MEM; + } else { + mtbl[va] = 0; + } + } +} +#endif diff --git a/libcpu/mips/gs264/mmu.h b/libcpu/mips/gs264/mmu.h new file mode 100644 index 0000000000..2472bf975f --- /dev/null +++ b/libcpu/mips/gs264/mmu.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-25 quanzhao the first version + * 2020-07-26 lizhirui porting to ls2k + */ +#ifndef __MMU_H_ +#define __MMU_H_ + +#include <rtthread.h> + +#define DESC_SEC (0x2) +#define MEMWBWA ((1<<12)|(3<<2)) /* write back, write allocate */ +#define MEMWB (3<<2) /* write back, no write allocate */ +#define MEMWT (2<<2) /* write through, no write allocate */ +#define SHAREDEVICE (1<<2) /* shared device */ +#define STRONGORDER (0<<2) /* strong ordered */ +#define XN (1<<4) /* execute Never */ +#ifdef RT_USING_USERSPACE +#define AP_RW (1<<10) /* supervisor=RW, user=No */ +#define AP_RO ((1<<10) |(1 << 15)) /* supervisor=RW, user=No */ +#else +#define AP_RW (3<<10) /* supervisor=RW, user=RW */ +#define AP_RO ((2<<10) /* supervisor=RW, user=RO */ +#endif + +#define SHARED (1<<16) /* shareable */ + +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) + +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) + +/* device mapping type */ +#define DEVICE_MEM (SHARED|AP_RW|DOMAIN0|SHAREDEVICE|DESC_SEC|XN) +/* normal memory mapping type */ +#define NORMAL_MEM (SHARED|AP_RW|DOMAIN0|MEMWBWA|DESC_SEC) + +#define STRONG_ORDER_MEM (SHARED|AP_RO|XN|DESC_SEC) + +struct mem_desc +{ + rt_uint32_t vaddr_start; + rt_uint32_t vaddr_end; + rt_uint32_t paddr_start; + rt_uint32_t attr; +}; + +#define MMU_MAP_MTBL_XN (1<<0) +#define MMU_MAP_MTBL_A (1<<1) +#define MMU_MAP_MTBL_B (1<<2) +#define MMU_MAP_MTBL_C (1<<3) +#define MMU_MAP_MTBL_AP01(x) (x<<4) +#define MMU_MAP_MTBL_TEX(x) (x<<6) +#define MMU_MAP_MTBL_AP2(x) (x<<9) +#define MMU_MAP_MTBL_SHARE (1<<10) + +#define MMU_MAP_K_RO (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(1)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_K_RWCB (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_K_RW (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_K_DEVICE (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_U_RO (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(1)|MMU_MAP_MTBL_AP01(2)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_U_RWCB (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_U_RW (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_U_DEVICE (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_SHARE) + +#define ARCH_SECTION_SHIFT 20 +#define ARCH_SECTION_SIZE (1 << ARCH_SECTION_SHIFT) +#define ARCH_SECTION_MASK (ARCH_SECTION_SIZE - 1) +#define ARCH_PAGE_SHIFT 14 +#define ARCH_PAGE_SIZE (1 << ARCH_PAGE_SHIFT) +#define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1) +#define ARCH_PAGE_TBL_SHIFT 10 +#define ARCH_PAGE_TBL_SIZE (1 << ARCH_PAGE_TBL_SHIFT) +#define ARCH_PAGE_TBL_MASK (ARCH_PAGE_TBL_SIZE - 1) + +#define ARCH_MMU_USED_MASK 3 + +#define ARCH_TYPE_SUPERSECTION (1 << 18) + +typedef struct +{ + size_t *vtable; + size_t vstart; + size_t vend; + size_t pv_off; +} rt_mmu_info; + +void *mmu_table_get(); +void switch_mmu(void *mmu_table); + +int rt_hw_mmu_map_init(rt_mmu_info *mmu_info, void* v_address, size_t size, size_t *vtable, size_t pv_off); +#ifdef RT_USING_USERSPACE +void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void* p_addr, size_t size, size_t attr); +void *rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void *v_addr, size_t size, size_t attr); +#else +void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void* p_addr, size_t size, size_t attr); +#endif +void rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t size); +void *rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void* v_addr); + +void *rt_hw_kernel_phys_to_virt(void *p_addr, size_t size); +void *rt_hw_kernel_virt_to_phys(void *v_addr, size_t size); + +#endif diff --git a/libcpu/mips/loongson_1b/cache.c b/libcpu/mips/loongson_1b/cache.c deleted file mode 100644 index 842f392cb7..0000000000 --- a/libcpu/mips/loongson_1b/cache.c +++ /dev/null @@ -1,230 +0,0 @@ -/* - * File : cache.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-07-09 Bernard first version - * 2011-08-08 lgnq modified for LS1B - */ - -#include <rtthread.h> -#include "../common/mipsregs.h" - -#define K0BASE 0x80000000 -#define PRID_LS1B 0x4220 - -extern void Clear_TagLo (void); -extern void Invalidate_Icache_Ls1b(unsigned int); -extern void Invalidate_Dcache_ClearTag_Ls1b(unsigned int); -extern void Invalidate_Dcache_Fill_Ls1b(unsigned int); -extern void Writeback_Invalidate_Dcache(unsigned int); -extern void enable_cpu_cache(void); - -typedef struct cacheinfo_t -{ - unsigned int icache_size; - unsigned int dcache_size; - unsigned int icacheline_size; - unsigned int dcacheline_size; -} cacheinfo_t ; - -typedef struct cacheop_t -{ - void (*Clear_TagLo) (void); - void (*Invalidate_Icache) (unsigned int); - void (*Invalidate_Dcache_Fill) (unsigned int); - void (*Invalidate_Dcache_ClearTag) (unsigned int); - void (*Init_Cache)(void); -} cacheop_t ; - -static cacheop_t cacheop, *pcacheop; -static cacheinfo_t cacheinfo, *pcacheinfo; - -int identify_cpu(void) -{ - unsigned int cpu_id; - - pcacheop = &cacheop; - pcacheinfo = &cacheinfo; - - rt_kprintf("CPU configure: 0x%08x\n", read_c0_config()); - cpu_id = read_c0_prid(); - switch (cpu_id) - { - case PRID_LS1B: - rt_kprintf("CPU:LS1B\n"); - pcacheop->Clear_TagLo = Clear_TagLo; - pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1b; - pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1b; - pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1b; - break; - default: - rt_kprintf("Unknown CPU type, system halted!\n"); - while (1) - { - ; - } - break; - } - - return 0; -} - -void probe_cache(void) -{ - unsigned int config1 = read_c0_config1(); - unsigned int icache_size, icache_line_size, icache_sets, icache_ways; - unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways; - - if ((icache_line_size = ((config1 >> 19) & 7))) - icache_line_size = 2 << icache_line_size; - else - icache_line_size = icache_line_size; - icache_sets = 64 << ((config1 >> 22) & 7); - icache_ways = 1 + ((config1 >> 16) & 7); - icache_size = icache_sets * icache_ways * icache_line_size; - - if ((dcache_line_size = ((config1 >> 10) & 7))) - dcache_line_size = 2 << dcache_line_size; - else - dcache_line_size = dcache_line_size; - dcache_sets = 64 << ((config1 >> 13) & 7); - dcache_ways = 1 + ((config1 >> 7) & 7); - dcache_size = dcache_sets * dcache_ways * dcache_line_size; - - rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size); - rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size); - - pcacheinfo->icache_size = icache_size; - pcacheinfo->dcache_size = dcache_size; - pcacheinfo->icacheline_size = icache_line_size; - pcacheinfo->dcacheline_size = dcache_line_size; - - return ; -} - -void invalidate_writeback_dcache_all(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - - while (start < end) - { - Writeback_Invalidate_Dcache(start); //hit writeback invalidate - start += pcacheinfo->dcacheline_size; - } -} - -void invalidate_writeback_dcache(unsigned long addr, int size) -{ - unsigned long start, end; - - start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size); - end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size); - - while (start <end) - { - Writeback_Invalidate_Dcache(start); - start += pcacheinfo->dcacheline_size; - } -} - -void invalidate_icache_all(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->icache_size); - - while (start < end) - { - pcacheop->Invalidate_Icache(start); - start += pcacheinfo->icacheline_size; - } -} - -void invalidate_dcache_all(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - while (start <end) - { - Invalidate_Dcache_Fill_Ls1b(start); - start += pcacheinfo->icacheline_size; - } -} - -//with cache disabled -void init_dcache(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - - while (start < end) - { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; - } - -} - -void rt_hw_cache_init(void) -{ - unsigned int start, end; - - /* 1. identify cpu and probe cache */ - identify_cpu(); - probe_cache(); - - start = K0BASE; - end = (start + pcacheinfo->icache_size); - - /* - * 2. clear CP0 taglo/taghi register; - */ - pcacheop->Clear_TagLo(); - - /* - * 3. invalidate instruction cache; - */ - while (start < end) - { - pcacheop->Invalidate_Icache(start); //index invalidate icache - start += pcacheinfo->icacheline_size; - } - - /* - * 4. invalidate data cache; - */ - start = K0BASE; - end = (start + pcacheinfo->dcache_size); - while(start < end) - { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; - } - - start = K0BASE; - while(start < end) - { - pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache - start += pcacheinfo->dcacheline_size; - } - - start = K0BASE; - while(start < end) - { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; - } - - /* enable cache */ - enable_cpu_cache(); - rt_kprintf("enable cpu cache done\n"); - - return ; -} diff --git a/libcpu/mips/loongson_1b/cache.h b/libcpu/mips/loongson_1b/cache.h deleted file mode 100644 index b5c2d4501e..0000000000 --- a/libcpu/mips/loongson_1b/cache.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * File : cache.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-07-09 Bernard first version - * 2011-08-08 lgnq modified for LS1B - */ -#ifndef __CACHE_H__ -#define __CACHE_H__ - -/* - * Cache Operations - */ -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 -#define Index_Invalidate_SI 0x02 -#define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_D 0x0d -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_I 0x10 -#define Hit_Invalidate_D 0x11 -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Fill 0x14 -#define Hit_Writeback_Inv_D 0x15 -/* 0x16 is unused */ -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 -/* 0x1a is unused */ -#define Hit_Writeback_SD 0x1b -/* 0x1c is unused */ -/* 0x1e is unused */ -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f - -#endif diff --git a/libcpu/mips/loongson_1b/cache_gcc.S b/libcpu/mips/loongson_1b/cache_gcc.S deleted file mode 100644 index bb6f46de4c..0000000000 --- a/libcpu/mips/loongson_1b/cache_gcc.S +++ /dev/null @@ -1,217 +0,0 @@ -/* - * File : cache_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-09-11 bernard port to Loongson SoC3210 - * 2011-08-08 lgnq port to Loongson LS1B - */ -#include "../common/mipsregs.h" -#include "../common/mips.inc" -#include "../common/asm.h" -#include "cache.h" - - .ent cache_init - .global cache_init - .set noreorder -cache_init: - move t1,ra -####part 2#### -cache_detect_4way: - mfc0 t4, CP0_CONFIG - andi t5, t4, 0x0e00 - srl t5, t5, 9 #ic - andi t6, t4, 0x01c0 - srl t6, t6, 6 #dc - addiu t8, $0, 1 - addiu t9, $0, 2 - #set dcache way - beq t6, $0, cache_d1way - addiu t7, $0, 1 #1 way - beq t6, t8, cache_d2way - addiu t7, $0, 2 #2 way - beq $0, $0, cache_d4way - addiu t7, $0, 4 #4 way -cache_d1way: - beq $0, $0, 1f - addiu t6, t6, 12 #1 way -cache_d2way: - beq $0, $0, 1f - addiu t6, t6, 11 #2 way -cache_d4way: - addiu t6, t6, 10 #4 way (10), 2 way(11), 1 way(12) -1: #set icache way - beq t5, $0, cache_i1way - addiu t3, $0, 1 #1 way - beq t5, t8, cache_i2way - addiu t3, $0, 2 #2 way - beq $0, $0, cache_i4way - addiu t3, $0, 4 #4 way -cache_i1way: - beq $0, $0, 1f - addiu t5, t5, 12 -cache_i2way: - beq $0, $0, 1f - addiu t5, t5, 11 -cache_i4way: - addiu t5, t5, 10 #4 way (10), 2 way(11), 1 way(12) - -1: addiu t4, $0, 1 - sllv t6, t4, t6 - sllv t5, t4, t5 -#if 0 - la t0, memvar - sw t7, 0x0(t0) #ways - sw t5, 0x4(t0) #icache size - sw t6, 0x8(t0) #dcache size -#endif -####part 3#### - .set mips3 - lui a0, 0x8000 - addu a1, $0, t5 - addu a2, $0, t6 -cache_init_d2way: -#a0=0x80000000, a1=icache_size, a2=dcache_size -#a3, v0 and v1 used as local registers - mtc0 $0, CP0_TAGHI - addu v0, $0, a0 - addu v1, a0, a2 -1: slt a3, v0, v1 - beq a3, $0, 1f - nop - mtc0 $0, CP0_TAGLO - beq t7, 1, 4f - cache Index_Store_Tag_D, 0x0(v0) # 1 way - beq t7, 2 ,4f - cache Index_Store_Tag_D, 0x1(v0) # 2 way - cache Index_Store_Tag_D, 0x2(v0) # 4 way - cache Index_Store_Tag_D, 0x3(v0) -4: beq $0, $0, 1b - addiu v0, v0, 0x20 -1: -cache_flush_i2way: - addu v0, $0, a0 - addu v1, a0, a1 -1: slt a3, v0, v1 - beq a3, $0, 1f - nop - beq t3, 1, 4f - cache Index_Invalidate_I, 0x0(v0) # 1 way - beq t3, 2, 4f - cache Index_Invalidate_I, 0x1(v0) # 2 way - cache Index_Invalidate_I, 0x2(v0) - cache Index_Invalidate_I, 0x3(v0) # 4 way -4: beq $0, $0, 1b - addiu v0, v0, 0x20 -1: -cache_flush_d2way: - addu v0, $0, a0 - addu v1, a0, a2 -1: slt a3, v0, v1 - beq a3, $0, 1f - nop - beq t7, 1, 4f - cache Index_Writeback_Inv_D, 0x0(v0) #1 way - beq t7, 2, 4f - cache Index_Writeback_Inv_D, 0x1(v0) # 2 way - cache Index_Writeback_Inv_D, 0x2(v0) - cache Index_Writeback_Inv_D, 0x3(v0) # 4 way -4: beq $0, $0, 1b - addiu v0, v0, 0x20 -1: -cache_init_finish: - jr t1 - nop - .set reorder - .end cache_init - -########################### -# Enable CPU cache # -########################### - -LEAF(enable_cpu_cache) - .set noreorder - mfc0 t0, CP0_CONFIG - nop - and t0, ~0x03 - or t0, 0x03 - mtc0 t0, CP0_CONFIG - nop - .set reorder - j ra -END (enable_cpu_cache) - -########################### -# disable CPU cache # -########################### - -LEAF(disable_cpu_cache) - .set noreorder - mfc0 t0, CP0_CONFIG - nop - and t0, ~0x03 - or t0, 0x2 - mtc0 t0, CP0_CONFIG - nop - .set reorder - j ra -END (disable_cpu_cache) - -/**********************************/ -/* Invalidate Instruction Cache */ -/**********************************/ -LEAF(Clear_TagLo) - .set noreorder - mtc0 zero, CP0_TAGLO - nop - .set reorder - j ra -END(Clear_TagLo) - - .set mips3 -/**********************************/ -/* Invalidate Instruction Cache */ -/**********************************/ -LEAF(Invalidate_Icache_Ls1b) - .set noreorder - cache Index_Invalidate_I,0(a0) - cache Index_Invalidate_I,1(a0) - cache Index_Invalidate_I,2(a0) - cache Index_Invalidate_I,3(a0) - .set reorder - j ra -END(Invalidate_Icache_Ls1b) - -/**********************************/ -/* Invalidate Data Cache */ -/**********************************/ -LEAF(Invalidate_Dcache_ClearTag_Ls1b) - .set noreorder - cache Index_Store_Tag_D, 0(a0) # BDSLOT: clear tag - cache Index_Store_Tag_D, 1(a0) # BDSLOT: clear tag - .set reorder - j ra -END(Invalidate_Dcache_ClearTag_Ls1b) - -LEAF(Invalidate_Dcache_Fill_Ls1b) - .set noreorder - cache Index_Writeback_Inv_D, 0(a0) # BDSLOT: clear tag - cache Index_Writeback_Inv_D, 1(a0) # BDSLOT: clear tag - .set reorder - j ra -END(Invalidate_Dcache_Fill_Ls1b) - -LEAF(Writeback_Invalidate_Dcache) - .set noreorder - cache Hit_Writeback_Inv_D, (a0) - .set reorder - j ra -END(Writeback_Invalidate_Dcache) - .set mips0 diff --git a/libcpu/mips/loongson_1b/context_gcc.S b/libcpu/mips/loongson_1b/context_gcc.S deleted file mode 100644 index ce004dc716..0000000000 --- a/libcpu/mips/loongson_1b/context_gcc.S +++ /dev/null @@ -1,149 +0,0 @@ -/* - * File : context_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-09-11 bernard port to Loongson SoC3210 - * 2011-08-08 lgnq port to Loongson LS1B - */ - -#include "../common/mips.inc" -#include "../common/stackframe.h" - - .section ".text", "ax" - .set noreorder - -/* - * rt_base_t rt_hw_interrupt_disable() - */ - .globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mfc0 v0, CP0_STATUS - and v1, v0, 0xfffffffe - mtc0 v1, CP0_STATUS - jr ra - nop - -/* - * void rt_hw_interrupt_enable(rt_base_t level) - */ - .globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - mtc0 a0, CP0_STATUS - jr ra - nop - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) - * a0 --> from - * a1 --> to - */ - .globl rt_hw_context_switch -rt_hw_context_switch: - mtc0 ra, CP0_EPC - SAVE_ALL - - sw sp, 0(a0) /* store sp in preempted tasks TCB */ - lw sp, 0(a1) /* get new task stack pointer */ - - RESTORE_ALL_AND_RET - -/* - * void rt_hw_context_switch_to(rt_uint32 to)/* - * a0 --> to - */ - .globl rt_hw_context_switch_to -rt_hw_context_switch_to: - lw sp, 0(a0) /* get new task stack pointer */ - - RESTORE_ALL_AND_RET - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* - */ - .globl rt_thread_switch_interrupt_flag - .globl rt_interrupt_from_thread - .globl rt_interrupt_to_thread - .globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - la t0, rt_thread_switch_interrupt_flag - lw t1, 0(t0) - nop - bnez t1, _reswitch - nop - li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ - sw t1, 0(t0) - la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ - sw a0, 0(t0) -_reswitch: - la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ - sw a1, 0(t0) - jr ra - nop - -/* - * void rt_hw_context_switch_interrupt_do(rt_base_t flag) - */ - .globl rt_interrupt_enter - .globl rt_interrupt_leave - .globl mips_irq_handle -mips_irq_handle: - SAVE_ALL - - mfc0 t0, CP0_CAUSE - and t1, t0, 0xff - bnez t1, spurious_interrupt /* check exception */ - nop - - /* let k0 keep the current context sp */ - move k0, sp - /* switch to kernel stack */ - li sp, SYSTEM_STACK - - jal rt_interrupt_enter - nop - jal rt_interrupt_dispatch - nop - jal rt_interrupt_leave - nop - - /* switch sp back to thread's context */ - move sp, k0 - - /* - * if rt_thread_switch_interrupt_flag set, jump to - * rt_hw_context_switch_interrupt_do and don't return - */ - la k0, rt_thread_switch_interrupt_flag - lw k1, 0(k0) - beqz k1, spurious_interrupt - nop - sw zero, 0(k0) /* clear flag */ - nop - - /* - * switch to the new thread - */ - la k0, rt_interrupt_from_thread - lw k1, 0(k0) - nop - sw sp, 0(k1) /* store sp in preempted tasks's TCB */ - - la k0, rt_interrupt_to_thread - lw k1, 0(k0) - nop - lw sp, 0(k1) /* get new task's stack pointer */ - j spurious_interrupt - nop - -spurious_interrupt: - RESTORE_ALL_AND_RET - - .set reorder diff --git a/libcpu/mips/loongson_1b/cpuport.c b/libcpu/mips/loongson_1b/cpuport.c deleted file mode 100644 index c095c04814..0000000000 --- a/libcpu/mips/loongson_1b/cpuport.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * File : cpuport.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-07-09 Bernard first version - * 2010-09-11 Bernard add CPU reset implementation - */ - -#include <rtthread.h> -#include "ls1b.h" - -/** - * @addtogroup Loongson LS1B - */ - -/*@{*/ - -/** - * this function will reset CPU - * - */ -void rt_hw_cpu_reset(void) -{ - /* open the watch-dog */ - WDT_EN = 0x01; /* watch dog enable */ - WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ - WDT_SET = 0x01; /* watch dog start */ - - rt_kprintf("reboot system...\n"); - while (1); -} - -/** - * this function will shutdown CPU - * - */ -void rt_hw_cpu_shutdown(void) -{ - rt_kprintf("shutdown...\n"); - - while (1); -} - -extern rt_uint32_t cp0_get_cause(void); -extern rt_uint32_t cp0_get_status(void); -extern rt_uint32_t cp0_get_hi(void); -extern rt_uint32_t cp0_get_lo(void); - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - static rt_uint32_t g_sr = 0; - - if (g_sr == 0) - { - g_sr = cp0_get_status(); - g_sr &= 0xfffffffe; - g_sr |= 0x8401; - } - - /** Start at stack top */ - stk = (rt_uint32_t *)stack_addr; - *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ - *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ - *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ - *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ - *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ - *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ - *(--stk) = (rt_uint32_t) texit; /* ra */ - *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ - *(--stk) = (rt_uint32_t) stack_addr; /* sp */ - *(--stk) = (rt_uint32_t) 0x0000001c; /* gp */ - *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ - *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ - *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ - *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ - *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ - *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ - *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ - *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ - *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ - *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ - *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ - *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ - *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ - *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ - *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ - *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ - *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ - *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ - *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ - *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ - *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ - *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ - *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ - *(--stk) = (rt_uint32_t) parameter; /* a0 */ - *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ - *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ - *(--stk) = (rt_uint32_t) 0x00000001; /* at */ - *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - -/*@}*/ - diff --git a/libcpu/mips/loongson_1b/exception.c b/libcpu/mips/loongson_1b/exception.c deleted file mode 100644 index 4a3745cbc5..0000000000 --- a/libcpu/mips/loongson_1b/exception.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * File : cpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - */ -#include <rtthread.h> -#include <rthw.h> -#include "../common/exception.h" -#include "../common/mipsregs.h" - -/** - * @addtogroup Loongson - */ - -/*@{*/ - -/** - * exception handle table - */ -#define RT_EXCEPTION_MAX 8 -exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX]; - -/** - * setup the exception handle - */ -exception_func_t rt_set_except_vector(int n, exception_func_t func) -{ - exception_func_t old_handler = sys_exception_handlers[n]; - - if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func)) - { - return 0; - } - - sys_exception_handlers[n] = func; - - return old_handler; -} - -void tlb_refill_handler(void) -{ - rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); -} - -void cache_error_handler(void) -{ - rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); -} - -static void unhandled_exception_handle(pt_regs_t *regs) -{ - rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause()); -} - -void install_default_execpt_handle(void) -{ - rt_int32_t i; - - for (i=0; i<RT_EXCEPTION_MAX; i++) - sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle; -} - -void exception_handler(pt_regs_t *regs) -{ - rt_uint32_t cause; - rt_uint32_t index; - - cause = (read_c0_cause() & read_c0_config()); - cause = (cause & 0xfc00) >> 8; - - for (index = RT_EXCEPTION_MAX; index > 0; index --) - { - if (cause & (1 << index)) - { - sys_exception_handlers[index](regs); - cause &= ~(1 << index); - } - } -} - -/*@}*/ diff --git a/libcpu/mips/loongson_1b/interrupt.c b/libcpu/mips/loongson_1b/interrupt.c deleted file mode 100644 index 998d1e4918..0000000000 --- a/libcpu/mips/loongson_1b/interrupt.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-10-15 Bernard first version - * 2010-10-15 lgnq modified for LS1B - * 2013-03-29 aozima Modify the interrupt interface implementations. - */ - -#include <rtthread.h> -#include <rthw.h> -#include "ls1b.h" - -#define MAX_INTR 32 - -extern rt_uint32_t rt_interrupt_nest; -rt_uint32_t rt_interrupt_from_thread; -rt_uint32_t rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -static struct rt_irq_desc irq_handle_table[MAX_INTR]; -void rt_interrupt_dispatch(void *ptreg); -void rt_hw_timer_handler(); - -static struct ls1b_intc_regs volatile *ls1b_hw0_icregs -= (struct ls1b_intc_regs volatile *)(LS1B_INTREG_BASE); - -/** - * @addtogroup Loongson LS1B - */ - -/*@{*/ - -static void rt_hw_interrupt_handler(int vector, void *param) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} - -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init(void) -{ - rt_int32_t idx; - - /* pci active low */ - ls1b_hw0_icregs->int_pol = -1; //must be done here 20110802 lgnq - /* make all interrupts level triggered */ - (ls1b_hw0_icregs+0)->int_edge = 0x0000e000; - /* mask all interrupts */ - (ls1b_hw0_icregs+0)->int_clr = 0xffffffff; - - rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table)); - for (idx = 0; idx < MAX_INTR; idx ++) - { - irq_handle_table[idx].handler = rt_hw_interrupt_handler; - } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -/** - * This function will mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_mask(int vector) -{ - /* mask interrupt */ - (ls1b_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f)); -} - -/** - * This function will un-mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_umask(int vector) -{ - (ls1b_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f)); -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param new_handler the interrupt service routine to be installed - * @param old_handler the old interrupt service routine - */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) -{ - rt_isr_handler_t old_handler = RT_NULL; - - if (vector >= 0 && vector < MAX_INTR) - { - old_handler = irq_handle_table[vector].handler; - -#ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX); -#endif /* RT_USING_INTERRUPT_INFO */ - irq_handle_table[vector].handler = handler; - irq_handle_table[vector].param = param; - } - - return old_handler; -} - -void rt_interrupt_dispatch(void *ptreg) -{ - int irq; - void *param; - rt_isr_handler_t irq_func; - static rt_uint32_t status = 0; - rt_uint32_t c0_status; - rt_uint32_t c0_cause; - volatile rt_uint32_t cause_im; - volatile rt_uint32_t status_im; - rt_uint32_t pending_im; - - /* check os timer */ - c0_status = read_c0_status(); - c0_cause = read_c0_cause(); - - cause_im = c0_cause & ST0_IM; - status_im = c0_status & ST0_IM; - pending_im = cause_im & status_im; - - if (pending_im & CAUSEF_IP7) - { - rt_hw_timer_handler(); - } - - if (pending_im & CAUSEF_IP2) - { - /* the hardware interrupt */ - status = ls1b_hw0_icregs->int_isr; - if (!status) - return; - - for (irq = MAX_INTR; irq > 0; --irq) - { - if ((status & (1 << irq))) - { - status &= ~(1 << irq); - - irq_func = irq_handle_table[irq].handler; - param = irq_handle_table[irq].param; - - /* do interrupt */ - irq_func(irq, param); - -#ifdef RT_USING_INTERRUPT_INFO - irq_handle_table[irq].counter++; -#endif /* RT_USING_INTERRUPT_INFO */ - - /* ack interrupt */ - ls1b_hw0_icregs->int_clr |= (1 << irq); - } - } - } - else if (pending_im & CAUSEF_IP3) - { - rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); - } - else if (pending_im & CAUSEF_IP4) - { - rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); - } - else if (pending_im & CAUSEF_IP5) - { - rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); - } - else if (pending_im & CAUSEF_IP6) - { - rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); - } -} - -/*@}*/ diff --git a/libcpu/mips/loongson_1b/ls1b.h b/libcpu/mips/loongson_1b/ls1b.h deleted file mode 100644 index 34393a3448..0000000000 --- a/libcpu/mips/loongson_1b/ls1b.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * File : ls1b.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2011, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-08-08 lgnq first version - */ - -#ifndef __LS1B_H__ -#define __LS1B_H__ - -#include "../common/mipsregs.h" - -#define LS1B_ACPI_IRQ 0 -#define LS1B_HPET_IRQ 1 -#define LS1B_UART0_IRQ 2 -#define LS1B_UART1_IRQ 3 -#define LS1B_UART2_IRQ 4 -#define LS1B_UART3_IRQ 5 -#define LS1B_CAN0_IRQ 6 -#define LS1B_CAN1_IRQ 7 -#define LS1B_SPI0_IRQ 8 -#define LS1B_SPI1_IRQ 9 -#define LS1B_AC97_IRQ 10 -#define LS1B_MS_IRQ 11 -#define LS1B_KB_IRQ 12 -#define LS1B_DMA0_IRQ 13 -#define LS1B_DMA1_IRQ 14 -#define LS1B_NAND_IRQ 15 -#define LS1B_I2C0_IRQ 16 -#define LS1B_I2C1_IRQ 17 -#define LS1B_PWM0_IRQ 18 -#define LS1B_PWM1_IRQ 19 -#define LS1B_PWM2_IRQ 20 -#define LS1B_PWM3_IRQ 21 -#define LS1B_LPC_IRQ 22 -#define LS1B_EHCI_IRQ 32 -#define LS1B_OHCI_IRQ 33 -#define LS1B_GMAC1_IRQ 34 -#define LS1B_GMAC2_IRQ 35 -#define LS1B_SATA_IRQ 36 -#define LS1B_GPU_IRQ 37 -#define LS1B_PCI_INTA_IRQ 38 -#define LS1B_PCI_INTB_IRQ 39 -#define LS1B_PCI_INTC_IRQ 40 -#define LS1B_PCI_INTD_IRQ 41 - -#define LS1B_GPIO_IRQ 64 -#define LS1B_GPIO_FIRST_IRQ 64 -#define LS1B_GPIO_IRQ_COUNT 96 -#define LS1B_GPIO_LAST_IRQ (LS1B_GPIO_FIRST_IRQ + LS1B_GPIO_IRQ_COUNT-1) - -#define INT_PCI_INTA (1<<6) -#define INT_PCI_INTB (1<<7) -#define INT_PCI_INTC (1<<8) -#define INT_PCI_INTD (1<<9) - -#define LS1B_LAST_IRQ 159 -#define MIPS_CPU_TIMER_IRQ 167 -#define LS1B_INTREG_BASE 0xbfd01040 - -#define LS1B_DMA_IRQ_BASE 168 -#define LS1B_DMA_IRQ_COUNT 16 - -struct ls1b_intc_regs -{ - volatile unsigned int int_isr; - volatile unsigned int int_en; - volatile unsigned int int_set; - volatile unsigned int int_clr; /* offset 0x10*/ - volatile unsigned int int_pol; - volatile unsigned int int_edge; /* offset 0 */ -}; - -struct ls1b_cop_global_regs -{ - volatile unsigned int control; - volatile unsigned int rd_inten; - volatile unsigned int wr_inten; - volatile unsigned int rd_intisr; /* offset 0x10*/ - volatile unsigned int wr_intisr; - unsigned int unused[11]; -} ; - -struct ls1b_cop_channel_regs -{ - volatile unsigned int rd_control; - volatile unsigned int rd_src; - volatile unsigned int rd_cnt; - volatile unsigned int rd_status; /* offset 0x10*/ - volatile unsigned int wr_control; - volatile unsigned int wr_src; - volatile unsigned int wr_cnt; - volatile unsigned int wr_status; /* offset 0x10*/ -} ; - -struct ls1b_cop_regs -{ - struct ls1b_cop_global_regs global; - struct ls1b_cop_channel_regs chan[8][2]; -} ; - -#define __REG8(addr) *((volatile unsigned char *)(addr)) -#define __REG16(addr) *((volatile unsigned short *)(addr)) -#define __REG32(addr) *((volatile unsigned int *)(addr)) - -#define GMAC0_BASE 0xBFE10000 -#define GMAC0_DMA_BASE 0xBFE11000 -#define GMAC1_BASE 0xBFE20000 -#define GMAC1_DMA_BASE 0xBFE21000 -#define I2C0_BASE 0xBFE58000 -#define PWM0_BASE 0xBFE5C000 -#define PWM1_BASE 0xBFE5C010 -#define PWM2_BASE 0xBFE5C020 -#define PWM3_BASE 0xBFE5C030 -#define WDT_BASE 0xBFE5C060 -#define RTC_BASE 0xBFE64000 -#define I2C1_BASE 0xBFE68000 -#define I2C2_BASE 0xBFE70000 -#define AC97_BASE 0xBFE74000 -#define NAND_BASE 0xBFE78000 -#define SPI_BASE 0xBFE80000 -#define CAN1_BASE 0xBF004300 -#define CAN0_BASE 0xBF004400 - -/* Watch Dog registers */ -#define WDT_EN __REG32(WDT_BASE + 0x00) -#define WDT_SET __REG32(WDT_BASE + 0x04) -#define WDT_TIMER __REG32(WDT_BASE + 0x08) - -#define PLL_FREQ __REG32(0xbfe78030) -#define PLL_DIV_PARAM __REG32(0xbfe78034) - -#endif diff --git a/libcpu/mips/loongson_1b/mipscfg.c b/libcpu/mips/loongson_1b/mipscfg.c deleted file mode 100644 index 10dd3fee9e..0000000000 --- a/libcpu/mips/loongson_1b/mipscfg.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * File : mipscfg.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-27 swkyer first version - */ -#include <rtthread.h> -#include "../common/mipsregs.h" -#include "../common/mipscfg.h" - -mips32_core_cfg_t g_mips_core = -{ - 16, /* icache_line_size */ - 256, /* icache_lines_per_way */ - 4, /* icache_ways */ - 16, /* dcache_line_size */ - 256, /* dcache_lines_per_way */ - 4, /* dcache_ways */ - 16, /* max_tlb_entries */ -}; - -static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) -{ - rt_uint16_t rets = 1; - - while (n--) - rets *= b; - - return rets; -} - -static rt_uint16_t m_log2(rt_uint16_t b) -{ - rt_uint16_t rets = 0; - - while (b != 1) - { - b /= 2; - rets++; - } - - return rets; -} - -/** - * read core attribute - */ -void mips32_cfg_init(void) -{ - rt_uint16_t val; - rt_uint32_t cp0_config1; - - cp0_config1 = read_c0_config(); - if (cp0_config1 & 0x80000000) - { - cp0_config1 = read_c0_config1(); - - val = (cp0_config1 & (7<<22))>>22; - g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<19))>>19; - g_mips_core.icache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<16))>>16; - g_mips_core.icache_ways = val + 1; - - val = (cp0_config1 & (7<<13))>>13; - g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<10))>>10; - g_mips_core.dcache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<7))>>7; - g_mips_core.dcache_ways = val + 1; - - val = (cp0_config1 & (0x3F<<25))>>25; - g_mips_core.max_tlb_entries = val + 1; - } -} diff --git a/libcpu/mips/loongson_1b/start_gcc.S b/libcpu/mips/loongson_1b/start_gcc.S deleted file mode 100644 index fd98335671..0000000000 --- a/libcpu/mips/loongson_1b/start_gcc.S +++ /dev/null @@ -1,137 +0,0 @@ -/* - * File : start_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-09-04 bernard porting to Jz47xx - */ - -#include "../common/mips.inc" -#include "../common/stackframe.h" - - .section ".start", "ax" - .set noreorder - - /* the program entry */ - .globl _start -_start: - .set noreorder - la ra, _start - - /* disable interrupt */ - mfc0 t0, CP0_STATUS - and t0, 0xfffffffe # By default it will be disabled. - mtc0 t0, CP0_STATUS # Set CPU to disable interrupt. - nop - - /* disable cache */ - mfc0 t0, CP0_CONFIG - and t0, 0xfffffff8 - or t0, 0x2 # disable,!default value is not it! - mtc0 t0, CP0_CONFIG # Set CPU to disable cache. - nop - - /* setup stack pointer */ - li sp, SYSTEM_STACK - la gp, _gp - - /* clear bss */ - la t0, __bss_start - la t1, __bss_end -_clr_bss_loop: - sw zero, 0(t0) - bne t0, t1, _clr_bss_loop - addiu t0, t0, 4 - - /* jump to RT-Thread RTOS */ - jal rtthread_startup - nop - - /* restart, never die */ - j _start - nop - .set reorder - - .globl cp0_get_cause -cp0_get_cause: - mfc0 v0, CP0_CAUSE - jr ra - nop - - .globl cp0_get_status -cp0_get_status: - mfc0 v0, CP0_STATUS - jr ra - nop - - .globl cp0_get_hi -cp0_get_hi: - mfhi v0 - jr ra - nop - - .globl cp0_get_lo -cp0_get_lo: - mflo v0 - jr ra - nop - - .extern tlb_refill_handler - .extern cache_error_handler - - /* Exception Handler */ - - /* 0x0 - TLB refill handler */ - .section .vectors.1, "ax", %progbits - .global tlb_refill_exception - .type tlb_refill_exception,@function -tlb_refill_exception: - j tlb_refill_handler - nop - - /* 0x100 - Cache error handler */ - .section .vectors.2, "ax", %progbits - j cache_error_handler - nop - - /* 0x180 - Exception/Interrupt handler */ - .section .vectors.3, "ax", %progbits - .global general_exception - .type general_exception,@function -general_exception: - j _general_exception_handler - nop - - /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */ - .section .vectors.4, "ax", %progbits - .global irq_exception - .type irq_exception,@function -irq_exception: - j _irq_handler - nop - - .section .vectors, "ax", %progbits - .extern mips_irq_handle - - /* general exception handler */ -_general_exception_handler: - .set noreorder - la k0, mips_irq_handle - jr k0 - nop - .set reorder - - /* interrupt handler */ -_irq_handler: - .set noreorder - la k0, mips_irq_handle - jr k0 - nop - .set reorder diff --git a/libcpu/mips/loongson_1c/cache.c b/libcpu/mips/loongson_1c/cache.c deleted file mode 100644 index bf97db9b4e..0000000000 --- a/libcpu/mips/loongson_1c/cache.c +++ /dev/null @@ -1,233 +0,0 @@ -/* - * File : cache.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-07-09 Bernard first version - * 2011-08-08 lgnq modified for LS1B - * 2015-07-08 chinesebear modified for loongson 1c - */ - -#include <rtthread.h> -#include "../common/mipsregs.h" - -#define K0BASE 0x80000000 -#define PRID_LS1C 0x4220 - -extern void Clear_TagLo (void); -extern void Invalidate_Icache_Ls1c(unsigned int); -extern void Invalidate_Dcache_ClearTag_Ls1c(unsigned int); -extern void Invalidate_Dcache_Fill_Ls1c(unsigned int); -extern void Writeback_Invalidate_Dcache(unsigned int); -extern void enable_cpu_cache(void); - -typedef struct cacheinfo_t -{ - unsigned int icache_size; - unsigned int dcache_size; - unsigned int icacheline_size; - unsigned int dcacheline_size; -} cacheinfo_t ; - -typedef struct cacheop_t -{ - void (*Clear_TagLo) (void); - void (*Invalidate_Icache) (unsigned int); - void (*Invalidate_Dcache_Fill) (unsigned int); - void (*Invalidate_Dcache_ClearTag) (unsigned int); - void (*Init_Cache)(void); -} cacheop_t ; - -static cacheop_t cacheop, *pcacheop; -static cacheinfo_t cacheinfo, *pcacheinfo; - -int identify_cpu(void) -{ - unsigned int cpu_id; - - pcacheop = &cacheop; - pcacheinfo = &cacheinfo; - - rt_kprintf("CPU configure: 0x%08x\n", read_c0_config()); - cpu_id = read_c0_prid(); - switch (cpu_id) - { - case PRID_LS1C: - rt_kprintf("CPU:Loongson 1C\n"); - pcacheop->Clear_TagLo = Clear_TagLo; - pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1c; - pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1c; - pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1c; - break; - default: - rt_kprintf("Unknown CPU type, system halted!\n"); - while (1) - { - ; - } - break; - } - - return 0; -} - -void probe_cache(void) -{ - unsigned int config1 = read_c0_config1(); - unsigned int icache_size, icache_line_size, icache_sets, icache_ways; - unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways; - - if ((icache_line_size = ((config1 >> 19) & 7))) - icache_line_size = 2 << icache_line_size; - else - icache_line_size = icache_line_size; - icache_sets = 64 << ((config1 >> 22) & 7); - icache_ways = 1 + ((config1 >> 16) & 7); - icache_size = icache_sets * icache_ways * icache_line_size; - - if ((dcache_line_size = ((config1 >> 10) & 7))) - dcache_line_size = 2 << dcache_line_size; - else - dcache_line_size = dcache_line_size; - dcache_sets = 64 << ((config1 >> 13) & 7); - dcache_ways = 1 + ((config1 >> 7) & 7); - dcache_size = dcache_sets * dcache_ways * dcache_line_size; - - rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size); - rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size); - - pcacheinfo->icache_size = icache_size; - pcacheinfo->dcache_size = dcache_size; - pcacheinfo->icacheline_size = icache_line_size; - pcacheinfo->dcacheline_size = dcache_line_size; - - return ; -} - -void invalidate_writeback_dcache_all(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - - while (start < end) - { - Writeback_Invalidate_Dcache(start); //hit writeback invalidate - start += pcacheinfo->dcacheline_size; - } -} - -void invalidate_writeback_dcache(unsigned long addr, int size) -{ - unsigned long start, end; - - start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size); - end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size); - - while (start <end) - { - Writeback_Invalidate_Dcache(start); - start += pcacheinfo->dcacheline_size; - } -} - -void invalidate_icache_all(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->icache_size); - - while (start < end) - { - pcacheop->Invalidate_Icache(start); - start += pcacheinfo->icacheline_size; - } -} - -void invalidate_dcache_all(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - while (start <end) - { - Invalidate_Dcache_Fill_Ls1c(start); - start += pcacheinfo->icacheline_size; - } -} - -//with cache disabled -void init_dcache(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - - while (start < end) - { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; - } - -} - -void rt_hw_cache_init(void) -{ - unsigned int start, end; - - /* 1. identify cpu and probe cache */ - identify_cpu(); - probe_cache(); - - start = K0BASE; - end = (start + pcacheinfo->icache_size); - - /* - * 2. clear CP0 taglo/taghi register; - */ - pcacheop->Clear_TagLo(); - - /* - * 3. invalidate instruction cache; - */ - while (start < end) - { - pcacheop->Invalidate_Icache(start); //index invalidate icache - start += pcacheinfo->icacheline_size; - } - - /* - * 4. invalidate data cache; - */ - start = K0BASE; - end = (start + pcacheinfo->dcache_size); - while(start < end) - { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; - } - - start = K0BASE; - while(start < end) - { - pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache - start += pcacheinfo->dcacheline_size; - } - - start = K0BASE; - while(start < end) - { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; - } - - /* enable cache */ - enable_cpu_cache(); - rt_kprintf("enable cpu cache done\n"); - - return ; -} - - diff --git a/libcpu/mips/loongson_1c/context_gcc.S b/libcpu/mips/loongson_1c/context_gcc.S deleted file mode 100644 index fbffd34866..0000000000 --- a/libcpu/mips/loongson_1c/context_gcc.S +++ /dev/null @@ -1,162 +0,0 @@ -/* - * File : context_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-09-11 bernard port to Loongson SoC3210 - * 2011-08-08 lgnq port to Loongson LS1B - */ - -#include "../common/mips.inc" -#include "../common/stackframe.h" -#include "stackframe_fpu.h" - - .section ".text", "ax" - .set noreorder - -/* - * rt_base_t rt_hw_interrupt_disable() - */ - .globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mfc0 v0, CP0_STATUS - and v1, v0, 0xfffffffe - mtc0 v1, CP0_STATUS - jr ra - nop - -/* - * void rt_hw_interrupt_enable(rt_base_t level) - */ - .globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - ori a0, 0x00000800 - mtc0 a0, CP0_STATUS - ehb - mfc0 v0, CP0_CAUSE - ehb - or v1, v0, 0x800000 //EBASE + 0x200 - mtc0 v1, CP0_CAUSE - ehb - jr ra - nop - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) - * a0 --> from - * a1 --> to - */ - .globl rt_hw_context_switch -rt_hw_context_switch: - mtc0 ra, CP0_EPC - SAVE_ALL - SAVE_FPU - - sw sp, 0(a0) /* store sp in preempted tasks TCB */ - lw sp, 0(a1) /* get new task stack pointer */ - - RESTORE_FPU - RESTORE_ALL_AND_RET - -/* - * void rt_hw_context_switch_to(rt_uint32 to)/* - * a0 --> to - */ - .globl rt_hw_context_switch_to -rt_hw_context_switch_to: - lw sp, 0(a0) /* get new task stack pointer */ - - RESTORE_FPU - RESTORE_ALL_AND_RET - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* - */ - .globl rt_thread_switch_interrupt_flag - .globl rt_interrupt_from_thread - .globl rt_interrupt_to_thread - .globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - la t0, rt_thread_switch_interrupt_flag - lw t1, 0(t0) - nop - bnez t1, _reswitch - nop - li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ - sw t1, 0(t0) - la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ - sw a0, 0(t0) -_reswitch: - la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ - sw a1, 0(t0) - jr ra - nop - -/* - * void rt_hw_context_switch_interrupt_do(rt_base_t flag) - */ - .globl rt_interrupt_enter - .globl rt_interrupt_leave - .globl mips_irq_handle -mips_irq_handle: - SAVE_ALL - SAVE_FPU - - mfc0 t0, CP0_CAUSE - and t1, t0, 0xff - bnez t1, spurious_interrupt /* check exception */ - nop - - /* let k0 keep the current context sp */ - move k0, sp - /* switch to kernel stack */ - li sp, SYSTEM_STACK - - jal rt_interrupt_enter - nop - jal rt_interrupt_dispatch - nop - jal rt_interrupt_leave - nop - - /* switch sp back to thread's context */ - move sp, k0 - - /* - * if rt_thread_switch_interrupt_flag set, jump to - * rt_hw_context_switch_interrupt_do and don't return - */ - la k0, rt_thread_switch_interrupt_flag - lw k1, 0(k0) - beqz k1, spurious_interrupt - nop - sw zero, 0(k0) /* clear flag */ - nop - - /* - * switch to the new thread - */ - la k0, rt_interrupt_from_thread - lw k1, 0(k0) - nop - sw sp, 0(k1) /* store sp in preempted tasks's TCB */ - - la k0, rt_interrupt_to_thread - lw k1, 0(k0) - nop - lw sp, 0(k1) /* get new task's stack pointer */ - j spurious_interrupt - nop - -spurious_interrupt: - RESTORE_FPU - RESTORE_ALL_AND_RET - - .set reorder diff --git a/libcpu/mips/loongson_1c/cpuport.c b/libcpu/mips/loongson_1c/cpuport.c deleted file mode 100644 index 03fdc2a514..0000000000 --- a/libcpu/mips/loongson_1c/cpuport.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * File : cpuport.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-07-09 Bernard first version - * 2010-09-11 Bernard add CPU reset implementation - * 2015-07-06 chinesebear modified for loongson 1c - */ - -#include <rtthread.h> -#include "ls1c.h" - -register rt_uint32_t $GP __asm__ ("$28"); - -/** - * @addtogroup Loongson LS1B - */ - -/*@{*/ - -/** - * this function will reset CPU - * - */ -void rt_hw_cpu_reset(void) -{ - /* open the watch-dog */ - WDT_EN = 0x01; /* watch dog enable */ - WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ - WDT_SET = 0x01; /* watch dog start */ - - rt_kprintf("reboot system...\n"); - while (1); -} - -/** - * this function will shutdown CPU - * - */ -void rt_hw_cpu_shutdown(void) -{ - rt_kprintf("shutdown...\n"); - - while (1); -} - -extern rt_uint32_t cp0_get_cause(void); -extern rt_uint32_t cp0_get_status(void); -extern rt_uint32_t cp0_get_hi(void); -extern rt_uint32_t cp0_get_lo(void); - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - static rt_uint32_t g_sr = 0; - static rt_uint32_t g_gp = 0; - - if (g_sr == 0) - { - g_sr = cp0_get_status(); - g_sr &= 0xfffffffe; - g_sr |= 0x8401; - - g_gp = $GP; - } - - /** Start at stack top */ - stk = (rt_uint32_t *)stack_addr; - *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ - *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ - *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ - *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ - *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ - *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ - *(--stk) = (rt_uint32_t) texit; /* ra */ - *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ - *(--stk) = (rt_uint32_t) stack_addr; /* sp */ - *(--stk) = (rt_uint32_t) g_gp; /* gp */ - *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ - *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ - *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ - *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ - *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ - *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ - *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ - *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ - *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ - *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ - *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ - *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ - *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ - *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ - *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ - *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ - *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ - *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ - *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ - *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ - *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ - *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ - *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ - *(--stk) = (rt_uint32_t) parameter; /* a0 */ - *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ - *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ - *(--stk) = (rt_uint32_t) 0x00000001; /* at */ - *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - -#define cache_op(op,addr) \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noreorder \n" \ - " .set mips3\n\t \n" \ - " cache %0, %1 \n" \ - " .set pop \n" \ - : \ - : "i" (op), "R" (*(unsigned char *)(addr))) - -#if defined(CONFIG_CPU_LOONGSON2) -#define Hit_Invalidate_I 0x00 -#else -#define Hit_Invalidate_I 0x10 -#endif -#define Hit_Invalidate_D 0x11 -#define CONFIG_SYS_CACHELINE_SIZE 32 -#define Hit_Writeback_Inv_D 0x15 - - -void flush_cache(unsigned long start_addr, unsigned long size) -{ - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; - unsigned long addr = start_addr & ~(lsize - 1); - unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); - - while (1) { - cache_op(Hit_Writeback_Inv_D, addr); - cache_op(Hit_Invalidate_I, addr); - if (addr == aend) - break; - addr += lsize; - } -} - - -/*@}*/ - diff --git a/libcpu/mips/loongson_1c/exception.c b/libcpu/mips/loongson_1c/exception.c deleted file mode 100644 index 4a3745cbc5..0000000000 --- a/libcpu/mips/loongson_1c/exception.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * File : cpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - */ -#include <rtthread.h> -#include <rthw.h> -#include "../common/exception.h" -#include "../common/mipsregs.h" - -/** - * @addtogroup Loongson - */ - -/*@{*/ - -/** - * exception handle table - */ -#define RT_EXCEPTION_MAX 8 -exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX]; - -/** - * setup the exception handle - */ -exception_func_t rt_set_except_vector(int n, exception_func_t func) -{ - exception_func_t old_handler = sys_exception_handlers[n]; - - if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func)) - { - return 0; - } - - sys_exception_handlers[n] = func; - - return old_handler; -} - -void tlb_refill_handler(void) -{ - rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); -} - -void cache_error_handler(void) -{ - rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); -} - -static void unhandled_exception_handle(pt_regs_t *regs) -{ - rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause()); -} - -void install_default_execpt_handle(void) -{ - rt_int32_t i; - - for (i=0; i<RT_EXCEPTION_MAX; i++) - sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle; -} - -void exception_handler(pt_regs_t *regs) -{ - rt_uint32_t cause; - rt_uint32_t index; - - cause = (read_c0_cause() & read_c0_config()); - cause = (cause & 0xfc00) >> 8; - - for (index = RT_EXCEPTION_MAX; index > 0; index --) - { - if (cause & (1 << index)) - { - sys_exception_handlers[index](regs); - cause &= ~(1 << index); - } - } -} - -/*@}*/ diff --git a/libcpu/mips/loongson_1c/interrupt.c b/libcpu/mips/loongson_1c/interrupt.c deleted file mode 100644 index 407580d89e..0000000000 --- a/libcpu/mips/loongson_1c/interrupt.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-10-15 Bernard first version - * 2010-10-15 lgnq modified for LS1B - * 2013-03-29 aozima Modify the interrupt interface implementations. - * 2015-07-06 chinesebear modified for loongson 1c - */ - -#include <rtthread.h> -#include <rthw.h> -#include "ls1c.h" -#include "ls1c_public.h" - - -#define MAX_INTR (LS1C_NR_IRQS) - -extern rt_uint32_t rt_interrupt_nest; -rt_uint32_t rt_interrupt_from_thread; -rt_uint32_t rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -static struct rt_irq_desc irq_handle_table[MAX_INTR]; -void rt_interrupt_dispatch(void *ptreg); -void rt_hw_timer_handler(); - -static struct ls1c_intc_regs volatile *ls1c_hw0_icregs -= (struct ls1c_intc_regs volatile *)(LS1C_INTREG_BASE); - -/** - * @addtogroup Loongson LS1B - */ - -/*@{*/ - -static void rt_hw_interrupt_handler(int vector, void *param) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} - -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init(void) -{ - rt_int32_t idx; - rt_int32_t i; - rt_uint32_t c0_status = 0; - - // ����Э������0��״̬�Ĵ���SR��IM7-2�������ж� - c0_status = read_c0_status(); - c0_status |= 0xFC00; - write_c0_status(c0_status); - - // ��о1c���жϷ�Ϊ���� - for (i=0; i<5; i++) - { - /* disable */ - (ls1c_hw0_icregs+i)->int_en = 0x0; - /* pci active low */ - (ls1c_hw0_icregs+i)->int_pol = -1; //must be done here 20110802 lgnq - /* make all interrupts level triggered */ - (ls1c_hw0_icregs+i)->int_edge = 0x00000000; - /* mask all interrupts */ - (ls1c_hw0_icregs+i)->int_clr = 0xffffffff; - } - - rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table)); - for (idx = 0; idx < MAX_INTR; idx ++) - { - irq_handle_table[idx].handler = rt_hw_interrupt_handler; - } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -/** - * This function will mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_mask(int vector) -{ - /* mask interrupt */ - (ls1c_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f)); -} - -/** - * This function will un-mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_umask(int vector) -{ - (ls1c_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f)); -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param new_handler the interrupt service routine to be installed - * @param old_handler the old interrupt service routine - */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) -{ - rt_isr_handler_t old_handler = RT_NULL; - - if (vector >= 0 && vector < MAX_INTR) - { - old_handler = irq_handle_table[vector].handler; - -#ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX); -#endif /* RT_USING_INTERRUPT_INFO */ - irq_handle_table[vector].handler = handler; - irq_handle_table[vector].param = param; - } - - return old_handler; -} - - -/** - * ִ���жϴ������� - * @IRQn �жϺ� - */ -void ls1c_do_IRQ(int IRQn) -{ - rt_isr_handler_t irq_func; - void *param; - - // �ҵ��жϴ������� - irq_func = irq_handle_table[IRQn].handler; - param = irq_handle_table[IRQn].param; - - // ִ���жϴ������� - irq_func(IRQn, param); - -#ifdef RT_USING_INTERRUPT_INFO - irq_handle_table[IRQn].counter++; -#endif - - return ; -} - - -void ls1c_irq_dispatch(int n) -{ - rt_uint32_t intstatus, irq; - - /* Receive interrupt signal, compute the irq */ - intstatus = (ls1c_hw0_icregs+n)->int_isr & (ls1c_hw0_icregs+n)->int_en; - if (0 == intstatus) - return ; - - // ִ���жϴ������� - irq = ls1c_ffs(intstatus) - 1; - ls1c_do_IRQ((n<<5) + irq); - - /* ack interrupt */ - (ls1c_hw0_icregs+n)->int_clr |= (1 << irq); - - return ; -} - - -void rt_interrupt_dispatch(void *ptreg) -{ - int irq; - void *param; - rt_isr_handler_t irq_func; - static rt_uint32_t status = 0; - rt_uint32_t c0_status; - rt_uint32_t c0_cause; - volatile rt_uint32_t cause_im; - volatile rt_uint32_t status_im; - rt_uint32_t pending_im; - - /* check os timer */ - c0_status = read_c0_status(); - c0_cause = read_c0_cause(); - - cause_im = c0_cause & ST0_IM; - status_im = c0_status & ST0_IM; - pending_im = cause_im & status_im; - - if (pending_im & CAUSEF_IP7) - { - rt_hw_timer_handler(); - } - else if (pending_im & CAUSEF_IP2) - { - ls1c_irq_dispatch(0); - } - else if (pending_im & CAUSEF_IP3) - { - ls1c_irq_dispatch(1); - } - else if (pending_im & CAUSEF_IP4) - { - ls1c_irq_dispatch(2); - } - else if (pending_im & CAUSEF_IP5) - { - ls1c_irq_dispatch(3); - } - else if (pending_im & CAUSEF_IP6) - { - ls1c_irq_dispatch(4); - } -} - -/*@}*/ - - diff --git a/libcpu/mips/loongson_1c/ls1c.h b/libcpu/mips/loongson_1c/ls1c.h deleted file mode 100644 index a203810c37..0000000000 --- a/libcpu/mips/loongson_1c/ls1c.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * File : ls1c.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2011, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-08-08 lgnq first version - * 2015-07-06 chinesebear modified for loongson 1c - */ - -#ifndef __LS1C_H__ -#define __LS1C_H__ - -#include "../common/mipsregs.h" - -#define LS1C_ACPI_IRQ 0 -#define LS1C_HPET_IRQ 1 -//#define LS1C_UART0_IRQ 3 // linux����3��v1.4�汾��1c�ֲ�����2�������Σ���ȷ�� -#define LS1C_UART1_IRQ 4 -#define LS1C_UART2_IRQ 5 -#define LS1C_CAN0_IRQ 6 -#define LS1C_CAN1_IRQ 7 -#define LS1C_SPI0_IRQ 8 -#define LS1C_SPI1_IRQ 9 -#define LS1C_AC97_IRQ 10 -#define LS1C_MS_IRQ 11 -#define LS1C_KB_IRQ 12 -#define LS1C_DMA0_IRQ 13 -#define LS1C_DMA1_IRQ 14 -#define LS1C_DMA2_IRQ 15 -#define LS1C_NAND_IRQ 16 -#define LS1C_PWM0_IRQ 17 -#define LS1C_PWM1_IRQ 18 -#define LS1C_PWM2_IRQ 19 -#define LS1C_PWM3_IRQ 20 -#define LS1C_RTC_INT0_IRQ 21 -#define LS1C_RTC_INT1_IRQ 22 -#define LS1C_RTC_INT2_IRQ 23 -#define LS1C_UART3_IRQ 29 -#define LS1C_ADC_IRQ 30 -#define LS1C_SDIO_IRQ 31 - - -#define LS1C_EHCI_IRQ (32+0) -#define LS1C_OHCI_IRQ (32+1) -#define LS1C_OTG_IRQ (32+2) -#define LS1C_MAC_IRQ (32+3) -#define LS1C_CAM_IRQ (32+4) -#define LS1C_UART4_IRQ (32+5) -#define LS1C_UART5_IRQ (32+6) -#define LS1C_UART6_IRQ (32+7) -#define LS1C_UART7_IRQ (32+8) -#define LS1C_UART8_IRQ (32+9) -#define LS1C_UART9_IRQ (32+13) -#define LS1C_UART10_IRQ (32+14) -#define LS1C_UART11_IRQ (32+15) -#define LS1C_I2C2_IRQ (32+17) -#define LS1C_I2C1_IRQ (32+18) -#define LS1C_I2C0_IRQ (32+19) - - -#define LS1C_GPIO_IRQ 64 -#define LS1C_GPIO_FIRST_IRQ 64 -#define LS1C_GPIO_IRQ_COUNT 96 -#define LS1C_GPIO_LAST_IRQ (LS1C_GPIO_FIRST_IRQ + LS1C_GPIO_IRQ_COUNT-1) - - -#define LS1C_LAST_IRQ 159 -#define LS1C_INTREG_BASE 0xbfd01040 - -// ��о1c���жϷ�Ϊ���飬ÿ��32�� -#define LS1C_NR_IRQS (32*5) - - -// GPIO��ź��жϺ�֮��Ļ���ת�� -#define LS1C_GPIO_TO_IRQ(GPIOn) (LS1C_GPIO_FIRST_IRQ + (GPIOn)) -#define LS1C_IRQ_TO_GPIO(IRQn) ((IRQn) - LS1C_GPIO_FIRST_IRQ) - - -struct ls1c_intc_regs -{ - volatile unsigned int int_isr; - volatile unsigned int int_en; - volatile unsigned int int_set; - volatile unsigned int int_clr; /* offset 0x10*/ - volatile unsigned int int_pol; - volatile unsigned int int_edge; /* offset 0 */ -}; - -struct ls1c_cop_global_regs -{ - volatile unsigned int control; - volatile unsigned int rd_inten; - volatile unsigned int wr_inten; - volatile unsigned int rd_intisr; /* offset 0x10*/ - volatile unsigned int wr_intisr; - unsigned int unused[11]; -} ; - -struct ls1c_cop_channel_regs -{ - volatile unsigned int rd_control; - volatile unsigned int rd_src; - volatile unsigned int rd_cnt; - volatile unsigned int rd_status; /* offset 0x10*/ - volatile unsigned int wr_control; - volatile unsigned int wr_src; - volatile unsigned int wr_cnt; - volatile unsigned int wr_status; /* offset 0x10*/ -} ; - -struct ls1c_cop_regs -{ - struct ls1c_cop_global_regs global; - struct ls1c_cop_channel_regs chan[8][2]; -} ; - -#define __REG8(addr) *((volatile unsigned char *)(addr)) -#define __REG16(addr) *((volatile unsigned short *)(addr)) -#define __REG32(addr) *((volatile unsigned int *)(addr)) - -#define GMAC0_BASE 0xBFE10000 -#define GMAC0_DMA_BASE 0xBFE11000 -#define GMAC1_BASE 0xBFE20000 -#define GMAC1_DMA_BASE 0xBFE21000 -#define I2C0_BASE 0xBFE58000 -#define PWM0_BASE 0xBFE5C000 -#define PWM1_BASE 0xBFE5C010 -#define PWM2_BASE 0xBFE5C020 -#define PWM3_BASE 0xBFE5C030 -#define WDT_BASE 0xBFE5C060 -#define RTC_BASE 0xBFE64000 -#define I2C1_BASE 0xBFE68000 -#define I2C2_BASE 0xBFE70000 -#define AC97_BASE 0xBFE74000 -#define NAND_BASE 0xBFE78000 -#define SPI_BASE 0xBFE80000 -#define CAN1_BASE 0xBF004300 -#define CAN0_BASE 0xBF004400 - -/* Watch Dog registers */ -#define WDT_EN __REG32(WDT_BASE + 0x00) -#define WDT_SET __REG32(WDT_BASE + 0x04) -#define WDT_TIMER __REG32(WDT_BASE + 0x08) - -#define PLL_FREQ __REG32(0xbfe78030) -#define PLL_DIV_PARAM __REG32(0xbfe78034) - -#endif - diff --git a/libcpu/mips/loongson_1c/mipscfg.c b/libcpu/mips/loongson_1c/mipscfg.c deleted file mode 100644 index 10dd3fee9e..0000000000 --- a/libcpu/mips/loongson_1c/mipscfg.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * File : mipscfg.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-27 swkyer first version - */ -#include <rtthread.h> -#include "../common/mipsregs.h" -#include "../common/mipscfg.h" - -mips32_core_cfg_t g_mips_core = -{ - 16, /* icache_line_size */ - 256, /* icache_lines_per_way */ - 4, /* icache_ways */ - 16, /* dcache_line_size */ - 256, /* dcache_lines_per_way */ - 4, /* dcache_ways */ - 16, /* max_tlb_entries */ -}; - -static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) -{ - rt_uint16_t rets = 1; - - while (n--) - rets *= b; - - return rets; -} - -static rt_uint16_t m_log2(rt_uint16_t b) -{ - rt_uint16_t rets = 0; - - while (b != 1) - { - b /= 2; - rets++; - } - - return rets; -} - -/** - * read core attribute - */ -void mips32_cfg_init(void) -{ - rt_uint16_t val; - rt_uint32_t cp0_config1; - - cp0_config1 = read_c0_config(); - if (cp0_config1 & 0x80000000) - { - cp0_config1 = read_c0_config1(); - - val = (cp0_config1 & (7<<22))>>22; - g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<19))>>19; - g_mips_core.icache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<16))>>16; - g_mips_core.icache_ways = val + 1; - - val = (cp0_config1 & (7<<13))>>13; - g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<10))>>10; - g_mips_core.dcache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<7))>>7; - g_mips_core.dcache_ways = val + 1; - - val = (cp0_config1 & (0x3F<<25))>>25; - g_mips_core.max_tlb_entries = val + 1; - } -} diff --git a/libcpu/mips/loongson_1c/sdram_cfg.h b/libcpu/mips/loongson_1c/sdram_cfg.h deleted file mode 100644 index 3f88f26623..0000000000 --- a/libcpu/mips/loongson_1c/sdram_cfg.h +++ /dev/null @@ -1,85 +0,0 @@ - -#ifndef __OPENLOONGSON_SDRAM_CFG_H -#define __OPENLOONGSON_SDRAM_CFG_H - - -//#define SD_FREQ (6 * PLL_M) / (2 * SDRAM_PARAM_DIV_NUM) -#define SD_FREQ (((APB_CLK / 4) * (PLL_MULT / CPU_DIV)) / SDRAM_PARAM_DIV_NUM) - - -/* 颗粒行数 */ -#define ROW_1K 0x7 -#define ROW_2K 0x0 -#define ROW_4K 0x1 -#define ROW_8K 0x2 -#define ROW_16K 0x3 -/* 颗粒列数 */ -#define COL_256 0x7 -#define COL_512 0x0 -#define COL_1K 0x1 -#define COL_2K 0x2 -#define COL_4K 0x3 -/* 颗粒位宽 */ -#define WIDTH_8 0x0 -#define WIDTH_16 0x1 -#define WIDTH_32 0x2 - -#define TRCD 3 -#define TCL 3 -#define TRP 3 -#define TRFC 8 -#define TRAS 6 -#define TREF 0x818 -#define TWR 2 - -#define DEF_SEL 0x1 -#define DEF_SEL_N 0x0 -#define HANG_UP 0x1 -#define HANG_UP_N 0x0 -#define CFG_VALID 0x1 - - -#if 0 -// 白菜板8MB -/* - 以型号为IS42S16400的SDRAM为例， - 物理参数为， - 容量：8MB - 位宽：16位 - 列宽：8位，即2的8次方，即256 - 行宽：12位，即2的12次方，即4K - - 所以， - 颗粒的位宽=WIDTH_16 - 颗粒的列数=COL_256 - 颗粒的行数=ROW_4K - - 再结合宏SD_PARA0和芯片手册中寄存器SD_CONFIG，相信一看就能明白 - 替换宏SD_PARA0中的行宽、列宽和位宽 -*/ -#define SDRAM_WIDTH (WIDTH_16) -#define SDRAM_COL (COL_256) -#define SDRAM_ROW (ROW_4K) - -#else - -// 智龙32MByte -#define SDRAM_WIDTH (WIDTH_16) -#define SDRAM_COL (COL_512) -#define SDRAM_ROW (ROW_8K) - -#endif - -#define SD_PARA0 (0x7f<<25 | \ - (TRAS << 21) | \ - (TRFC << 17) | (TRP << 14) | (TCL << 11) | \ - (TRCD << 8) | (SDRAM_WIDTH << 6) | (SDRAM_COL << 3) | \ - SDRAM_ROW) - -#define SD_PARA1 ((HANG_UP_N << 8) | (DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7)) - -#define SD_PARA1_EN ((CFG_VALID << 9) | (HANG_UP_N << 8) | \ - (DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7)) - - -#endif diff --git a/libcpu/mips/loongson_1c/stackframe_fpu.h b/libcpu/mips/loongson_1c/stackframe_fpu.h deleted file mode 100644 index 93b8ef10c3..0000000000 --- a/libcpu/mips/loongson_1c/stackframe_fpu.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * ls1c FPU's stackframe - * �ʼ���룬��������뵽stackframe.h�е�SAVE_ALL, RESTORE_ALL��RESTORE_ALL_AND_RET�У� - * �����ǵ�Դ�ļ�"stackframe.h"λ��Ŀ¼"libcpu\mips\common"�ڣ���Ӱ�쵽����mips cpu - * ���ԣ������½���Դ�ļ� - */ -#ifndef __OPENLOONGSON_STACKFRAME_FPU_H -#define __OPENLOONGSON_STACKFRAME_FPU_H - - -#include "../common/asm.h" -#include "../common/mipsregs.h" -#include "../common/stackframe.h" - - - -#define PT_FPU_R0 (0) -#define PT_FPU_R2 ((PT_FPU_R0) + 2*LONGSIZE) -#define PT_FPU_R4 ((PT_FPU_R2) + 2*LONGSIZE) -#define PT_FPU_R6 ((PT_FPU_R4) + 2*LONGSIZE) -#define PT_FPU_R8 ((PT_FPU_R6) + 2*LONGSIZE) -#define PT_FPU_R10 ((PT_FPU_R8) + 2*LONGSIZE) -#define PT_FPU_R12 ((PT_FPU_R10) + 2*LONGSIZE) -#define PT_FPU_R14 ((PT_FPU_R12) + 2*LONGSIZE) -#define PT_FPU_R16 ((PT_FPU_R14) + 2*LONGSIZE) -#define PT_FPU_R18 ((PT_FPU_R16) + 2*LONGSIZE) -#define PT_FPU_R20 ((PT_FPU_R18) + 2*LONGSIZE) -#define PT_FPU_R22 ((PT_FPU_R20) + 2*LONGSIZE) -#define PT_FPU_R24 ((PT_FPU_R22) + 2*LONGSIZE) -#define PT_FPU_R26 ((PT_FPU_R24) + 2*LONGSIZE) -#define PT_FPU_R28 ((PT_FPU_R26) + 2*LONGSIZE) -#define PT_FPU_R30 ((PT_FPU_R28) + 2*LONGSIZE) - -#define PT_FPU_SIZE ((((PT_FPU_R30) + 2*LONGSIZE) + (2*PTRSIZE-1)) & ~(2*PTRSIZE-1)) - - - .macro SAVE_FPU - .set push - .set noreorder -#ifdef RT_USING_FPU - move k1, sp /* �����ֳ� */ - and k0, k1, 0xFFFFFFF8 /* 8�ֽڶ��� */ - PTR_SUBU sp, k0, PT_FPU_SIZE /* ����ջ�� */ - s.d $f0, PT_FPU_R0(sp) - s.d $f2, PT_FPU_R2(sp) - s.d $f4, PT_FPU_R4(sp) - s.d $f6, PT_FPU_R6(sp) - s.d $f8, PT_FPU_R8(sp) - s.d $f10, PT_FPU_R10(sp) - s.d $f12, PT_FPU_R12(sp) - s.d $f14, PT_FPU_R14(sp) - s.d $f16, PT_FPU_R16(sp) - s.d $f18, PT_FPU_R18(sp) - s.d $f20, PT_FPU_R20(sp) - s.d $f22, PT_FPU_R22(sp) - s.d $f24, PT_FPU_R24(sp) - s.d $f26, PT_FPU_R26(sp) - s.d $f28, PT_FPU_R28(sp) - s.d $f30, PT_FPU_R30(sp) - move sp, k1 /* �ָ��ֳ� */ -#endif - .set reorder - .set pop - .endm - - - .macro RESTORE_FPU - .set push - .set noreorder -#ifdef RT_USING_FPU - move k1, sp /* �����ֳ� */ - and k0, k1, 0xFFFFFFF8 /* 8�ֽڶ��� */ - PTR_SUBU sp, k0, PT_FPU_SIZE /* ����ջ��*/ - l.d $f0, PT_FPU_R0(sp) - l.d $f2, PT_FPU_R2(sp) - l.d $f4, PT_FPU_R4(sp) - l.d $f6, PT_FPU_R6(sp) - l.d $f8, PT_FPU_R8(sp) - l.d $f10, PT_FPU_R10(sp) - l.d $f12, PT_FPU_R12(sp) - l.d $f14, PT_FPU_R14(sp) - l.d $f16, PT_FPU_R16(sp) - l.d $f18, PT_FPU_R18(sp) - l.d $f20, PT_FPU_R20(sp) - l.d $f22, PT_FPU_R22(sp) - l.d $f24, PT_FPU_R24(sp) - l.d $f26, PT_FPU_R26(sp) - l.d $f28, PT_FPU_R28(sp) - l.d $f30, PT_FPU_R30(sp) - move sp, k1 /* �ָ��ֳ� */ -#endif - .set reorder - .set pop - .endm - - -#endif - diff --git a/libcpu/mips/loongson_1c/start_gcc.S b/libcpu/mips/loongson_1c/start_gcc.S deleted file mode 100644 index 4e71bc0524..0000000000 --- a/libcpu/mips/loongson_1c/start_gcc.S +++ /dev/null @@ -1,529 +0,0 @@ -/* - * File : start_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-09-04 bernard porting to Jz47xx - */ - -#include "../common/mips.inc" -#include "../common/stackframe.h" -#include "sdram_cfg.h" -#include "cache.h" -#include "rtconfig.h" - -#define SR_BOOT_EXC_VEC 0x00400000 - - -/* config pll div for cpu and sdram */ -#define PLL_MULT (0x54) // 晶振为24Mhz时，PLL=504Mhz -#define SDRAM_DIV (0) // SDRAM为CPU的2分频 -#define CPU_DIV (2) // CPU为PLL的2分频 - - // 配置内存大小 -#define MEM_SIZE (0x02000000) // 32MByte - - /* Delay macro */ -#define DELAY(count) \ - li v0, count; \ - 99: \ - bnez v0, 99b;\ - addiu v0, -1 - - -#define msize s2 -#define output_en s3 - - - - - .section ".start", "ax" - .set noreorder - - /* the program entry */ - .globl _start -_start: - .set noreorder - la ra, _start - -#if !defined(RT_USING_SELF_BOOT) - - /* disable interrupt */ - mfc0 t0, CP0_STATUS - and t0, 0xfffffffe # By default it will be disabled. - mtc0 t0, CP0_STATUS # Set CPU to disable interrupt. - nop - - /* disable cache */ - mfc0 t0, CP0_CONFIG - and t0, 0xfffffff8 - or t0, 0x2 # disable,!default value is not it! - mtc0 t0, CP0_CONFIG # Set CPU to disable cache. - nop - - /* setup stack pointer */ - li sp, SYSTEM_STACK - la gp, _gp - - /* clear bss */ - la t0, __bss_start - la t1, __bss_end -_clr_bss_loop: - sw zero, 0(t0) - bne t0, t1, _clr_bss_loop - addiu t0, t0, 4 - - /* jump to RT-Thread RTOS */ - jal rtthread_startup - nop - - /* restart, never die */ - j _start - nop - -#else - - mtc0 zero, CP0_STATUS // 清零cp0 status寄存器 - mtc0 zero, CP0_CAUSE // 清零cp0 cause寄存器 - - /* - 设置启动异常向量入口地址为ROM地址(0xbfc00000) - 将寄存器cp0 status的BEV置1，使CPU采用ROM(kseg1)空间的异常入口点 - */ - li t0, SR_BOOT_EXC_VEC /* Exception to Boostrap Location */ - mtc0 t0, CP0_STATUS - - /* setup stack pointer */ - li sp, SYSTEM_STACK - la gp, _gp - - /* initialize spi */ - li t0, 0xbfe80000 //地址0xbfe80000为SPI0的寄存器基地址 - li t1, 0x17 // div 4, fast_read + burst_en + memory_en double I/O 模式 部分SPI flash可能不支持 - sb t1, 0x4(t0) // 设置寄存器sfc_param - li t1, 0x05 - sb t1, 0x6(t0) // 设置寄存器sfc_timing - - /* 设置sdram cs1复用关系，开发板使用ejtag_sel gpio_0引脚(第五复用)作为第二片sdram的片选 - 注意sw2拨码开关的设置，使用ejtag烧录pmon时需要调整拨码开关，烧录完再调整回来 */ - li a0, 0xbfd011c0 - lw a1, 0x40(a0) - ori a1, 0x01 - sw a1, 0x40(a0) - - - bal locate - nop - - /* restart, never die */ - j _start - nop -#endif - - .set reorder - - .globl cp0_get_cause -cp0_get_cause: - mfc0 v0, CP0_CAUSE - jr ra - nop - - .globl cp0_get_status -cp0_get_status: - mfc0 v0, CP0_STATUS - jr ra - nop - - .globl cp0_get_hi -cp0_get_hi: - mfhi v0 - jr ra - nop - - .globl cp0_get_lo -cp0_get_lo: - mflo v0 - jr ra - nop - -#if defined(RT_USING_SELF_BOOT) - -/****************************************LOCATE*********************************/ - -/* - * We get here from executing a bal to get the PC value of the current execute - * location into ra. Check to see if we run from ROM or if this is ramloaded. - * 寄存器ra内保持着函数的返回地址，根据ra的值来判断当前是从ROM冷启动，还是从RAM热复位的 - * ROM冷启动由通电引起，RAM热复位为各种异常引起，比如看门狗引起的复位等， - * 也就是RAM热复位之前CPU已经开始运行了 - * 如果是从ROM冷启动，则寄存器ra的值为指令"bal locate"所在位置加8字节，大概在0xBFC00000附近 - * 如果是从RAM热复位，则集成器ra的值为0x80xxxxxx - */ -locate: -// la s0, uncached -// subu s0, ra, s0 - /* - * start.s的这段汇编程序在ROM（入口点为0xBFC00000）中运行 - * 而编译链接时指定的起始地址是0x80100000，所以需要修正一下地址 - * s0中保存着ra与start的差值，在后续的代码中可以起到修正地址的作用 - * 在看看文件开始的时候，对寄存器s0用途的描述是“ link versus load offset, used to relocate absolute adresses” - * 除了修正地址外，还通过s0的值来判断是从ROM冷启动，还是从RAM热启动 - */ - - la s0, _start // s0 = _start， 其中start的地址为编译链接时，指定的0x80010000 - subu s0, ra, s0 // s0 = ra - s0，其中ra的值在ROM入口地址0xBFC00000附近 - and s0, 0xffff0000 // s0 = s0 & 0xffff0000 - - /* - * 初始化cp0的status寄存器和cause寄存器 - * 在异常引起的(从RAM)热复位后，需要重新初始化cp0的status和cause， - * 如果是从ROM冷启动的，那么前面已经初始化了，这里是再次重复初始化，没有影响的 - */ - li t0, SR_BOOT_EXC_VEC - mtc0 t0, CP0_CONFIG // 重新初始化cp0的status寄存器 - mtc0 zero, CP0_CAUSE // 重新清零cp0的cause寄存器 - .set noreorder - - li t0, 0xbfe78030 // 地址0xbfe78030为PLL/SDRAM频率配置寄存器的地址 - /* 设置PLL倍频 及SDRAM分频 */ - li t2, (0x80000008 | (PLL_MULT << 8) | (0x3 << 2) | SDRAM_DIV) - /* 设置CPU分频 */ - li t3, (0x00008003 | (CPU_DIV << 8)) - /* 注意：首先需要把分频使能位清零 */ - li t1, 0x2 - sw t1, 0x4(t0) // 清零CPU_DIV_VALID，即disable - sw t2, 0x0(t0) // 写寄存器START_FREQ - sw t3, 0x4(t0) // 写寄存器CLK_DIV_PARAM - DELAY(2000) - - /* 芯片上电默认使用gpio(输入模式）但大多时候是使用模块的功能，如lcd i2c spi ac97等 - 所以这里把gpio都关闭，方便使用模块功能。如果上电后需要gpio输出一个确定电平， - 如继电器、LDE等，可以修改这里的代码。*/ - /* disable all gpio */ - li a0,0xbfd00000 - sw zero,0x10c0(a0) /* disable gpio 0-31 */ - sw zero,0x10c4(a0) /* disable gpio 32-63 */ - sw zero,0x10c8(a0) /* disable gpio 64-95 */ - sw zero,0x10cc(a0) - - li t0, 0xffffffff - sw t0, 0x10d0(a0) - sw t0, 0x10d4(a0) - sw t0, 0x10d8(a0) - sw t0, 0x10dc(a0) - - sw t0, 0x10f0(a0) - sw t0, 0x10f4(a0) - sw t0, 0x10f8(a0) - sw t0, 0x10fc(a0) - - - /* lcd soft_reset and panel config & timing */ -#ifdef DC_FB0 -/* li a0, 0xbc301240 - li a1, 0x00100103 - sw a1, 0x0(a0) - li a1, 0x00000103 - sw a1, 0x0(a0) //soft_reset - li a1, 0x00100103 - sw a1, 0x0(a0) - - li a1, 0x80001111 - sw a1, 0x180(a0) //panel config - li a1, 0x33333333 - sw a1, 0x1a0(a0)*/ -#endif - - li output_en, 0x1 -#ifdef FAST_STARTUP - li a1, 0x03000000 - sw a1, 0x10c4(a0) - sw a1, 0x10d4(a0) - lw a2, 0x10e4(a0) - and a2, a1 - beq a2, a1, get_pin_val_finish - nop - li output_en, 0x1 - -get_pin_val_finish: - -#endif - - /* Initializing. Standby... */ - /* - * 根据s0的值判断是否为ROM冷启动 - * 如果s0不等于0，则是ROM冷启动；如果等于0，则是RAM热复位 - * 冷启动，则需要初始化内存，cache，加载代码到内存等 - */ - bnez s0, 1f // 如果寄存器s0不等于0，则说明是ROM冷启动，则跳转到下一个标号1处进行彻底初始化 - nop - li a0, 128 - - jal rtthread_startup // 热复位，则直接跳转到函数main - nop -1: - -/* use only 8wins */ -#define CPU_WIN_BASE 0xbfd00000 -#define CPU_WIN_MASK 0xbfd00040 -#define CPU_WIN_MMAP 0xbfd00080 - -#define set_cpu_window(id, base, mask, mmap) \ - li t0, CPU_WIN_BASE ; \ - sw $0, 0x80+id*8(t0) ; \ - li t1, base ; \ - sw t1, 0x00+id*8(t0) ; \ - sw $0, 0x04+id*8(t0) ; \ - li t1, mask ; \ - sw t1, 0x40+id*8(t0) ; \ - sw $0, 0x44+id*8(t0) ; \ - li t1, mmap ; \ - sw t1, 0x80+id*8(t0) ; \ - sw $0, 0x84+id*8(t0) - -/* fixup cpu window */ -cpu_win_fixup: - // - // hit = (paddr & mask) == (mmap & mask) - // mapped_addr = paddr &~mask | mmap & mask - // - // mmap[7] -> enable - // mmap[5] -> block trans enable - // mmap[4] -> cachable - // mmap[1:0] -> destination - // - // NOTE: the address windows has priority, win0 > win1 > ... > win7 - -/* set_cpu_window(0, 0x1c280000, 0xfff80000, 0x1c280083) // camera 512K - set_cpu_window(1, 0x1c300000, 0xfff00000, 0x1c300081) // dc 1M - set_cpu_window(2, 0x1fe10000, 0xffffe000, 0x1fe10082) // gmac0 8K - set_cpu_window(3, 0x1fe10000, 0xffff0000, 0x1fe100d0) // gmac0 64K - set_cpu_window(4, 0x1f000000, 0xff000000, 0x1f000082) // AXIMUX 16M - set_cpu_window(5, 0x00000000, 0x00000000, 0x000000f0) // ddr 0 - set_cpu_window(6, 0x00000000, 0x00000000, 0x000000f0) // ddr 0 - set_cpu_window(7, 0x00000000, 0x00000000, 0x000000f0) // ddr 0*/ - -/* set_cpu_window(0, 0x1c280000, 0xfff80000, 0x1c2800d3) // camera -// set_cpu_window(1, 0x1fc00000, 0xfff00000, 0x1fc000f2) // - set_cpu_window(2, 0x1c300000, 0xfff00000, 0x1c3000d1) // dc 1M -// set_cpu_window(3, 0x1f000000, 0xff000000, 0x1f0000d2) // - set_cpu_window(4, 0x00000000, 0x00000000, 0x000000f0) - set_cpu_window(5, 0x00000000, 0x00000000, 0x000000f0) - set_cpu_window(6, 0x00000000, 0x00000000, 0x000000f0) // ddr 0 - set_cpu_window(7, 0x00000000, 0x00000000, 0x000000f0) // ddr 0*/ - - // after this fixup, the kernel code should be compiled with - // uncached instruction fetch patch - - /* 配置内存 */ - li msize, MEM_SIZE -#if !defined(NAND_BOOT_EN) - - /* - 手册建议，先写寄存器SD_CONFIG[31:0]，然后再写寄存器的SD_CONFIG[63:32]， - 即先写低32位，再写高32位。 - 写三次寄存器，最后一次将最高位置一，即使能 - */ - - // 写第一次 - li t1, 0xbfd00410 // 寄存器SD_CONFIG[31:0]的地址为0xbfd00410 - li a1, SD_PARA0 // 宏SD_PARA0在sdram_cfg.S中定义的 - sw a1, 0x0(t1) // 将宏SD_PARA0的值写入寄存器SD_CONFIG[31:0] - li a1, SD_PARA1 - sw a1, 0x4(t1) // 同理，将宏SD_PARA1的值写入寄存器SD_CONFIG[63:32] - - // 写第二次 - li a1, SD_PARA0 - sw a1, 0x0(t1) - li a1, SD_PARA1 - sw a1, 0x4(t1) - - // 写第三次 - li a1, SD_PARA0 - sw a1, 0x0(t1) - li a1, SD_PARA1_EN // 使能 - sw a1, 0x4(t1) -// DELAY(100) -#endif - - /**************************************CACHE*****************************/ - -#define CF_7_SE (1 << 3) /* Secondary cache enable */ -#define CF_7_SC (1 << 31) /* Secondary cache not present */ -#define CF_7_TE (1 << 12) /* Tertiary cache enable */ -#define CF_7_TC (1 << 17) /* Tertiary cache not present */ -#define CF_7_TS (3 << 20) /* Tertiary cache size */ -#define CF_7_TS_AL 20 /* Shift to align */ -#define NOP8 nop;nop;nop;nop;nop;nop;nop;nop - -do_caches: - /* Init caches... */ - li s7, 0 /* no L2 cache */ - li s8, 0 /* no L3 cache */ - - bal cache_init // 调用汇编函数cache_init - nop - - mfc0 a0, CP0_CONFIG // 将协处理器0的config寄存器的值加载到寄存器a0 - and a0, a0, ~((1<<12) | 7) // a0 = a0 & ~((1<<12) | 7) - or a0, a0, 2 // a0 |= 2 - mtc0 a0, CP0_CONFIG // 将寄存器a0的值写入协处理器0的config寄存器 - -/***********************MEMORY DEBUGGING AND COPY SELF TO RAM***********************/ -//#include "newtest.32/mydebug.S" -bootnow: - /* copy program to sdram to make copy fast */ - /* 先将执行拷贝pmon到内存任务的代码，拷贝到内存0xa0000000 */ - - /* 先确定需要拷贝的代码段为标号121到标号122之间的代码 - * 由于链接时指定的起始地址是0x80010000， - * 而目前正在ROM（SPI NOR FLASH，起始地址为0xBFC00000）运行 - * 所以需要用寄存器s0来修正一下地址 - */ - la t0, 121f // 将下一个标号121所在地址，加载到寄存器t0 - addu t0, s0 // 使用寄存器s0修正t0中的(标号121的)地址 - la t1, 122f // 将下一个标号122所在地址，加载到寄存器t1 - addu t1, s0 // 使用寄存器s0修正t1中的(标号122的)地址 - - li t2, 0xa0000000 // 将立即数0xa0000000（起始地址）加载到寄存器t2 -1: - lw v0, (t0) // 将寄存器t0所指的内存地址开始4字节的数据加载到寄存器v0 - sw v0, (t2) // 将寄存器v0的内容保存到寄存器t2所指的内存中 - addu t0, 4 // 寄存器t0向后移4字节 - addu t2, 4 // 寄存器t2向后移4字节 - ble t0, t1, 1b // 如果t0 <= t1，则跳转到上一个标号1处，继续拷贝后面的4字节 - nop - - li t0, 0xa0000000 // 将立即数0xa0000000加载到寄存器t0 - jr t0 // 跳转到起始地址0xa0000000处开始执行（拷贝任务） - nop - -121: - /* Copy PMON to execute location... */ - /* 将固件拷贝到起始地址为0xa0010000的内存空间 - 由于kseg0(0x8000 0000 - 0x9FFF FFFF)和kseg1(0xA000 0000 - 0xBFFF FFFF)是映射到物理内存的相同区域 - 即拷贝到0xA000 0000开始的kseg1，就相当于拷贝到0x8000 0000开始的kseg0 - 这就是为什么链接时，指定的地址是0x8001 0000，而拷贝的目标起始地址是0xA001 0000 - */ - la a0, _start // 加载符号start所在地址0x80010000加载到寄存器a0中 - addu a1, a0, s0 // 使用寄存器s0修正寄存器a0中的地址，a1=0xBFC00000 - la a2, __bss_start // 加载_edata（链接脚本中的一个符号）到寄存器a2 - or a0, 0xa0000000 // a0 = a0 | 0xa0000000 = 0xa0010000 - or a2, 0xa0000000 // a2 = a2 | 0xa0000000，修正地址_edata - subu t1, a2, a0 // t1 = a2 - a0，即计算从start到_edata之间的长度（字节数） - srl t1, t1, 2 // t1 >>= 2，即t1除以4。(和前面类似，每次拷贝4字节，所以除以4) - // 似乎t1计算结果没有被使用，马上就被后面的覆盖了 - - move t0, a0 // t0 = a0 = 0xa0010000 (目标起始地址) - move t1, a1 // t1 = a1 = 0xBFC00000 (start在ROM中的地址，源起始地址) - move t2, a2 // t2 = a2 (_edata在ROM中的地址，源结束地址) - - /* copy text section */ -1: and t3, t0, 0x0000ffff // t3 = t0 & 0x0000ffff，取低16位 - bnez t3, 2f // 如果t3不等于0，则跳转到下一个标号2处继续执行，t3的计算结果似乎没被使用，就被后面的覆盖了 - nop -2: lw t3, 0(t1) // 从源地址t1处加载4字节到寄存器t3中 - nop - sw t3, 0(t0) // 将寄存器t3中的4字节数据保存到目标地址t0处 - addu t0, 4 // 目标地址t0后移4字节 - addu t1, 4 // 源地址t1 后移4字节 - bne t2, t0, 1b // 如果t2不等于t0，则跳到上一个标号1处继续拷贝，总的来说就是判断拷贝是否结束 - nop - /* copy text section done. */ - - /* clear bss */ - la t0, __bss_start - la t1, __bss_end -_clr_bss_loop: - sw zero, 0(t0) - bne t0, t1, _clr_bss_loop - addiu t0, t0, 4 - - /* disable interrupt */ - mfc0 t0, CP0_STATUS - and t0, 0xfffffffe # By default it will be disabled. - mtc0 t0, CP0_STATUS # Set CPU to disable interrupt. - nop - - /* disable cache */ - mfc0 t0, CP0_CONFIG - and t0, 0xfffffff8 - or t0, 0x2 # disable,!default value is not it! - mtc0 t0, CP0_CONFIG # Set CPU to disable cache. - nop - - /* jump to RT-Thread RTOS */ - jal rtthread_startup - nop - - /* restart, never die */ - j _start - nop - - -122: - -stuck: - b stuck - nop -#endif - - .extern tlb_refill_handler - .extern cache_error_handler - - /* Exception Handler */ - - /* 0x0 - TLB refill handler */ - .section .vectors.1, "ax", %progbits - .global tlb_refill_exception - .type tlb_refill_exception,@function -tlb_refill_exception: - j tlb_refill_handler - nop - - /* 0x100 - Cache error handler */ - .section .vectors.2, "ax", %progbits - j cache_error_handler - nop - - /* 0x180 - Exception/Interrupt handler */ - .section .vectors.3, "ax", %progbits - .global general_exception - .type general_exception,@function -general_exception: - j _general_exception_handler - nop - - /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */ - .section .vectors.4, "ax", %progbits - .global irq_exception - .type irq_exception,@function -irq_exception: - j _irq_handler - nop - - .section .vectors, "ax", %progbits - .extern mips_irq_handle - - /* general exception handler */ -_general_exception_handler: - .set noreorder - la k0, mips_irq_handle - jr k0 - nop - .set reorder - - /* interrupt handler */ -_irq_handler: - .set noreorder - la k0, mips_irq_handle - jr k0 - nop - .set reorder diff --git a/libcpu/mips/pic32/SConscript b/libcpu/mips/pic32/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/mips/pic32/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/mips/pic32/context_gcc.S b/libcpu/mips/pic32/context_gcc.S index 3e820fb9d8..bd46dffdc7 100644 --- a/libcpu/mips/pic32/context_gcc.S +++ b/libcpu/mips/pic32/context_gcc.S @@ -1,5 +1,20 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-05-24 aozima first version + * 2019-07-19 Zhou Yanjie clean up code + */ + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ +#endif + #include <p32xxxx.h> -#include "../common/mips.inc" +#include "../common/mips_def.h" #include "../common/stackframe.h" .section ".text", "ax" diff --git a/libcpu/mips/x1000/cache.c b/libcpu/mips/x1000/cache.c deleted file mode 100644 index 5fc9682810..0000000000 --- a/libcpu/mips/x1000/cache.c +++ /dev/null @@ -1,217 +0,0 @@ -/* - * File : cache.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016/11/02 Urey the first version - */ - -#include <rtthread.h> -#include <board.h> -#include <rthw.h> - -#include "../common/mips.h" - - -#define CONFIG_SYS_DCACHE_SIZE 16384 -#define CONFIG_SYS_ICACHE_SIZE 16384 -#define CONFIG_SYS_CACHELINE_SIZE 32 - -#define K0_TO_K1() \ -do { \ - unsigned long __k0_addr; \ - \ - __asm__ __volatile__( \ - "la %0, 1f\n\t" \ - "or %0, %0, %1\n\t" \ - "jr %0\n\t" \ - "nop\n\t" \ - "1: nop\n" \ - : "=&r"(__k0_addr) \ - : "r" (0x20000000) ); \ -} while(0) - -#define K1_TO_K0() \ -do { \ - unsigned long __k0_addr; \ - __asm__ __volatile__( \ - "nop;nop;nop;nop;nop;nop;nop\n\t" \ - "la %0, 1f\n\t" \ - "jr %0\n\t" \ - "nop\n\t" \ - "1: nop\n" \ - : "=&r" (__k0_addr)); \ -} while (0) - -#define INVALIDATE_BTB() \ -do { \ - unsigned long tmp; \ - __asm__ __volatile__( \ - ".set mips32\n\t" \ - "mfc0 %0, $16, 7\n\t" \ - "nop\n\t" \ - "ori %0, 2\n\t" \ - "mtc0 %0, $16, 7\n\t" \ - "nop\n\t" \ - ".set mips2\n\t" \ - : "=&r" (tmp)); \ -} while (0) - -#define __sync() \ - __asm__ __volatile__( \ - ".set push\n\t" \ - ".set noreorder\n\t" \ - ".set mips2\n\t" \ - "sync\n\t" \ - ".set pop" \ - : /* no output */ \ - : /* no input */ \ - : "memory") - -#if defined(JZ4775) || defined(X1000) -#define SYNC_WB() \ -do { \ - __asm__ __volatile__ ( \ - "sync\n\t" \ - "lw $0, %0\n\t" \ - : \ - :"m"(*(int *)0xa0000000) \ - :"memory"); \ -} while (0) -#else -#error "not define sync wb" -#define SYNC_WB() __asm__ __volatile__ ("sync") -#endif - - -#undef cache_op -#define cache_op(op, addr) \ - __asm__ __volatile__( \ - ".set push\n" \ - ".set noreorder\n" \ - ".set mips3\n" \ - "cache %0, %1\n" \ - ".set pop\n" \ - : \ - : "i" (op), "R" (*(unsigned char *)(addr))) - - -void rt_hw_dcache_flush_line(rt_uint32_t addr) -{ - cache_op(HIT_WRITEBACK_INV_D, addr); - SYNC_WB(); -} - -void rt_hw_dcache_flush_range(rt_uint32_t start_addr, rt_uint32_t size) -{ - rt_uint32_t lsize = CONFIG_SYS_CACHELINE_SIZE; - rt_uint32_t addr = start_addr & ~(lsize - 1); - rt_uint32_t aend = (start_addr + size - 1) & ~(lsize - 1); - rt_uint32_t writebuffer; - - for (; addr <= aend; addr += lsize) - { - cache_op(HIT_WRITEBACK_INV_D, addr); - } - SYNC_WB(); -} - -void rt_hw_dcache_flush_all(void) -{ - rt_uint32_t addr; - - for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE) - { - cache_op(INDEX_WRITEBACK_INV_D, addr); - } - - SYNC_WB(); -} - -void rt_hw_dcache_invalidate_range(rt_uint32_t start_addr,rt_uint32_t size) -{ - rt_uint32_t lsize = CONFIG_SYS_CACHELINE_SIZE; - rt_uint32_t addr = start_addr & ~(lsize - 1); - rt_uint32_t aend = (start_addr + size - 1) & ~(lsize - 1); - - for (; addr <= aend; addr += lsize) - cache_op(HIT_INVALIDATE_D, addr); -} - -void rt_hw_dcache_invalidate_all(void) -{ - rt_uint32_t addr; - - for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE) - { - cache_op(INDEX_STORE_TAG_D, addr); - } - - SYNC_WB(); -} - -void rt_hw_icache_flush_line(rt_uint32_t addr) -{ - cache_op(HIT_INVALIDATE_I, addr); -} - -void rt_hw_icache_flush_all(void) -{ - rt_uint32_t addr; - - asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ - asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ - - for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE) - { - cache_op(INDEX_STORE_TAG_I, addr); - } - - INVALIDATE_BTB(); -} - -void rt_hw_icache_invalidate_all(void) -{ - rt_uint32_t i; - - K0_TO_K1(); - - asm volatile (".set noreorder\n" - ".set mips32\n\t" - "mtc0\t$0,$28\n\t" - "mtc0\t$0,$29\n" - ".set mips0\n" - ".set reorder\n"); - for (i = CKSEG0; i < CKSEG0 + CONFIG_SYS_ICACHE_SIZE; i += CONFIG_SYS_CACHELINE_SIZE) - cache_op(INDEX_STORE_TAG_I, i); - - K1_TO_K0(); - - INVALIDATE_BTB(); -} - - -void rt_hw_flush_cache_all(void) -{ - rt_hw_dcache_flush_all(); - rt_hw_icache_flush_all(); -} - - - diff --git a/libcpu/mips/x1000/cache.h b/libcpu/mips/x1000/cache.h deleted file mode 100644 index 0454527d91..0000000000 --- a/libcpu/mips/x1000/cache.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * File : cache.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��19�� Urey the first version - */ - -#ifndef _X1000_CACHE_H_ -#define _X1000_CACHE_H_ - -#include "../common/mips.h" -#include "../common/mips_cache.h" - - -void rt_hw_icache_invalidate_all(void); -void rt_hw_icache_flush_all(void); - -void rt_hw_dcache_flush_all(void); -void rt_hw_dcache_flush_range(rt_uint32_t addr, rt_uint32_t size); -void rt_hw_dcache_invalidate_all(void); -void rt_hw_dcache_invalidate_range(rt_uint32_t addr,rt_uint32_t size); - -void rt_hw_flush_cache_all(void); -#endif /* _X1000_CACHE_H_ */ diff --git a/libcpu/mips/x1000/cpu.c b/libcpu/mips/x1000/cpu.c deleted file mode 100644 index e1a51b9fe7..0000000000 --- a/libcpu/mips/x1000/cpu.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - * File : cpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��8�� Urey the first version - */ - - -#include <rtthread.h> -#include <board.h> -#include <rthw.h> - -#include "../common/mips.h" - -mips32_core_cfg_t g_mips_core = -{ - .icache_line_size = 32, - .icache_size = 16384, - - .dcache_line_size = 32, - .dcache_size = 16384, - - .max_tlb_entries = 16, /* max_tlb_entries */ -}; - -void rt_hw_tlb_init(void) -{ -//---------------------------------------------------------------------------------- -//cchappy tlb 0x30000000 to 0xC0000000 -//---------------------------------------------------------------------------------- - unsigned int pagemask = 0x007fe000;//0x01ffe000; /* 4MB */ - /* cached D:allow-W V:valid G */ - unsigned int entrylo0 = (0x30000000 >> 6) | (3 << 3) + (1 << 2) + (1 << 1) + 1; - unsigned int entrylo1 = (0x30400000 >> 6) | (3 << 3) + (1 << 2) + (1 << 1) + 1; - unsigned int entryhi = 0xc0000000; /* kseg2 base */ - int i; - __write_32bit_c0_register($5, 4, 0xa9000000); - write_c0_pagemask(pagemask); - write_c0_wired(0); -/* indexed write 32 tlb entry */ - for(i = 0; i < 32; i++) - { - asm ( - ".macro _ssnop; sll $0, $0, 1; .endm\n\t" - ".macro _ehb; sll $0, $0, 3; .endm\n\t" - ".macro mtc0_tlbw_hazard; _ssnop; _ssnop; _ehb; .endm\n\t" - ".macro tlbw_use_hazard; _ssnop; _ssnop; _ssnop; _ehb; .endm\n\t" - "\n\t" - "mtc0 %0, $0\n\t" /* write Index */ - "tlbw_use_hazard\n\t" - "mtc0 %1, $5\n\t" /* write PageMask */ - "mtc0 %2, $10\n\t" /* write EntryHi */ - "mtc0 %3, $2\n\t" /* write EntryLo0 */ - "mtc0 %4, $3\n\t" /* write EntryLo1 */ - "mtc0_tlbw_hazard\n\t" - "tlbwi \n\t" /* TLB indexed write */ - "tlbw_use_hazard\n\t" - : : "Jr" (i), "r" (pagemask), "r" (entryhi), - "r" (entrylo0), "r" (entrylo1) - ); - entryhi += 0x0800000; /* 32MB */ - entrylo0 += (0x0800000 >> 6); - entrylo1 += (0x0800000 >> 6); - } -} - -void rt_hw_cache_init(void) -{ - r4k_cache_flush_all(); -} - -/** - * this function will reset CPU - * - */ -RT_WEAK void rt_hw_cpu_reset() -{ - /* open the watch-dog */ - REG_WDT_TCSR = WDT_TCSR_EXT_EN; - REG_WDT_TCSR |= WDT_TCSR_PRESCALE_1024; - REG_WDT_TDR = 0x03; - REG_WDT_TCNT = 0x00; - REG_WDT_TCER |= WDT_TCER_TCEN; - - rt_kprintf("reboot system...\n"); - rt_hw_interrupt_disable(); - while (1); -} - -/** - * this function will shutdown CPU - * - */ -RT_WEAK void rt_hw_cpu_shutdown() -{ - rt_kprintf("shutdown...\n"); - rt_hw_interrupt_disable(); - while (1); -} - -/** - * This function finds the first bit set (beginning with the least significant bit) - * in value and return the index of that bit. - * - * Bits are numbered starting at 1 (the least significant bit). A return value of - * zero from any of these functions means that the argument was zero. - * - * @return return the index of the first bit set. If value is 0, then this function - * shall return 0. - */ -RT_WEAK int __rt_ffs(int value) -{ - return __builtin_ffs(value); -} diff --git a/libcpu/mips/x1000/interrupt.c b/libcpu/mips/x1000/interrupt.c deleted file mode 100644 index 2a7a42e792..0000000000 --- a/libcpu/mips/x1000/interrupt.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - * File : cpu_intc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016/09/07 Urey the first version - */ - -#include <stdio.h> -#include <stdlib.h> - -#include <rtthread.h> -#include <rthw.h> -#include <board.h> - -#include "../common/mips.h" - -#define INTERRUPTS_MAX 64 - -extern rt_uint32_t rt_interrupt_nest; -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -static struct rt_irq_desc isr_table[INTERRUPTS_MAX]; - -static void rt_hw_interrupt_handler(int vector, void *param) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} - -void rt_hw_interrupt_init(void) -{ - rt_int32_t idx; - - clear_c0_status(0xff04); /* clear ERL */ - set_c0_status(0x0400); /* set IP2 */ - - - rt_memset(isr_table, 0x00, sizeof(isr_table)); - for (idx = 0; idx < INTERRUPTS_MAX; idx ++) - { - isr_table[idx].handler = rt_hw_interrupt_handler; - } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; - - /* enable cpu interrupt mask */ - set_c0_status(IE_IRQ0 | IE_IRQ1); -} - -void rt_hw_interrupt_mask(int vector) -{ - /* mask interrupt */ - __intc_mask_irq(vector); -} - -void rt_hw_interrupt_umask(int vector) -{ - __intc_unmask_irq(vector); -} - -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) -{ - rt_isr_handler_t old_handler = RT_NULL; - - if(vector < INTERRUPTS_MAX) - { - old_handler = isr_table[vector].handler; - -#ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); -#endif /* RT_USING_INTERRUPT_INFO */ - isr_table[vector].handler = handler; - isr_table[vector].param = param; - } - - return old_handler; -} - -rt_inline int fls(int x) -{ - __asm__("clz %0, %1" : "=r" (x) : "r" (x)); - - return 32 - x; -} - -void rt_interrupt_dispatch(void *ptreg) -{ - void *param; - rt_isr_handler_t irq_func; - - int irq = 0, group; - rt_uint32_t intc_ipr0 = 0, intc_ipr1 = 0, vpu_pending = 0; - - rt_uint32_t c0_status, c0_cause; - rt_uint32_t pending_im; - - /* check os timer */ - c0_status = read_c0_status(); - c0_cause = read_c0_cause(); - - pending_im = (c0_cause & ST0_IM) & (c0_status & ST0_IM); - - if (pending_im & CAUSEF_IP3) - { - extern void rt_hw_ost_handler(void); - rt_hw_ost_handler(); - return; - } - if (pending_im & CAUSEF_IP2) - { - intc_ipr0 = REG_INTC_IPR(0); - intc_ipr1 = REG_INTC_IPR(1); - - if (intc_ipr0) - { - irq = fls(intc_ipr0) - 1; - intc_ipr0 &= ~(1<<irq); - } - else if(intc_ipr1) - { - irq = fls(intc_ipr1) - 1; - intc_ipr1 &= ~(1<<irq); - irq += 32; - } - else - { - //VPU - } - - if (irq >= INTERRUPTS_MAX) - rt_kprintf("max interrupt, irq=%d\n", irq); - - /* do interrupt */ - irq_func = isr_table[irq].handler; - param = isr_table[irq].param; - (*irq_func)(irq, param); - -#ifdef RT_USING_INTERRUPT_INFO - isr_table[irq].counter++; -#endif /* RT_USING_INTERRUPT_INFO */ - - /* ack interrupt */ - __intc_ack_irq(irq); - } - - if (pending_im & CAUSEF_IP0) - rt_kprintf("CAUSEF_IP0\n"); - if (pending_im & CAUSEF_IP1) - rt_kprintf("CAUSEF_IP1\n"); - if (pending_im & CAUSEF_IP4) - rt_kprintf("CAUSEF_IP4\n"); - if (pending_im & CAUSEF_IP5) - rt_kprintf("CAUSEF_IP5\n"); - if (pending_im & CAUSEF_IP6) - rt_kprintf("CAUSEF_IP6\n"); - if (pending_im & CAUSEF_IP7) - rt_kprintf("CAUSEF_IP7\n"); -} - -#ifdef RT_USING_INTERRUPT_INFO -#include <finsh.h> -int list_irqs(void) -{ - int index; - - rt_kprintf("interrupt list:\n"); - rt_kprintf("----------------\n"); - rt_kprintf("name counter\n"); - for (index = 0; index < INTERRUPTS_MAX; index ++) - { - if (isr_table[index].handler != rt_hw_interrupt_handler) - { - rt_kprintf("%-*.*s %d\n", RT_NAME_MAX, RT_NAME_MAX, isr_table[index].name, isr_table[index].counter); - } - } - - return 0; -} -MSH_CMD_EXPORT(list_irqs, list interrupt counter); -#endif - -unsigned int spin_lock_irqsave(void) -{ - register unsigned int t; - t = read_c0_status(); - write_c0_status((t & (~1))); - return (t); -} - -void spin_unlock_irqrestore(unsigned int val) -{ - write_c0_status(val); -} diff --git a/libcpu/mips/x1000/mips_backtrace.c b/libcpu/mips/x1000/mips_backtrace.c deleted file mode 100644 index b8a861bad5..0000000000 --- a/libcpu/mips/x1000/mips_backtrace.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * File : mips_backtrace.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��11�� Urey the first version - */ - -#include <rtthread.h> -#include <stdlib.h> -#include <stdio.h> -#include <stdint.h> - -#include "mips.h" - -/********************************************************************************************************* - ָ��� -*********************************************************************************************************/ -#define ADDUI_SP_INST 0x27bd0000 -#define SW_RA_INST 0xafbf0000 -#define JR_RA_INST 0x03e00008 - -#define INST_OP_MASK 0xffff0000 -#define INST_OFFSET_MASK 0x0000ffff - -#define abs(s) ((s) < 0 ? -(s):(s)) - -int backtrace_ctx(mips_reg_ctx *ctx) -{ - unsigned long *addr; - unsigned long *pc, *ra, *sp; - size_t ra_offset; - size_t stack_size; - int depth; - int size = 8; - - pc = (unsigned long *)(unsigned long)ctx->CP0EPC; - ra = (unsigned long *)(unsigned long)ctx->regs[REG_RA]; - sp = (unsigned long *)(unsigned long)ctx->regs[REG_SP]; - - rt_kprintf("[0x%08x]\n", pc); - - if (size == 1) return 1; - - ra_offset = stack_size = 0; - - for (addr = ra; !ra_offset || !stack_size; --addr) - { - switch (*addr & INST_OP_MASK) { - case ADDUI_SP_INST: - stack_size = abs((short)(*addr&INST_OFFSET_MASK)); - break; - - case SW_RA_INST: - ra_offset = (short)(*addr&INST_OFFSET_MASK); - break; - - case 0x3c1c0000: - goto out_of_loop; - - default: - break; - } - } - -out_of_loop: - if (ra_offset) ra = *(unsigned long **)((unsigned long)sp + ra_offset); - if (stack_size) sp = (unsigned long *)((unsigned long)sp + stack_size); - - // repeat backwar scanning - for (depth = 1; depth < size && ra && ra != (unsigned long *)0xffffffff; ++depth) - { - rt_kprintf("RA[%2d] : [0x%08x]\n", depth ,ra); - - ra_offset = 0; - stack_size = 0; - - for ( addr = ra; !ra_offset || !stack_size; -- addr ) - { - switch( *addr & INST_OP_MASK) - { - case ADDUI_SP_INST: - stack_size = abs((short)(*addr&INST_OFFSET_MASK)); - break; - - case SW_RA_INST: - ra_offset = abs((short)(*addr&INST_OFFSET_MASK)); - break; - - case 0x3c1c0000: - return depth +1; - - default: - break; - } - } - - ra = *(unsigned long **)((unsigned long)sp + ra_offset); - sp = (unsigned long *)((unsigned long)sp + stack_size); - } - - return depth; -} - -int backtrace(void) -{ - unsigned long *addr; - unsigned long *ra; - unsigned long *sp; - int size = 8, depth; - - size_t ra_offset; - size_t stack_size; - - // get current $a and $sp - __asm__ __volatile__ ( - " move %0, $ra\n" - " move %1, $sp\n" - : "=r"(ra), "=r"(sp) - ); - - // scanning to find the size of hte current stack frame - stack_size = 0; - - for ( addr = (unsigned long *)backtrace; !stack_size; ++addr) - { - if ((*addr & INST_OP_MASK ) == ADDUI_SP_INST ) - stack_size = abs((short)(*addr&INST_OFFSET_MASK)); - else if ( *addr == JR_RA_INST ) - break; - } - - sp = (unsigned long *) (( unsigned long )sp + stack_size); - - // repeat backwar scanning - for ( depth = 0; depth < size && ((( unsigned long )ra > KSEG0BASE) && (( unsigned long )ra < KSEG1BASE)); ++ depth ) - { - rt_kprintf("RA[%2d] : [0x%08x]\n", depth, ra); - { - extern void rt_thread_exit(void); - if ((uint32_t)ra == (uint32_t)(rt_thread_exit)) - return depth; - } - - ra_offset = 0; - stack_size = 0; - - for ( addr = ra; !ra_offset || !stack_size; -- addr ) - { - switch( *addr & INST_OP_MASK) - { - case ADDUI_SP_INST: - stack_size = abs((short)(*addr&INST_OFFSET_MASK)); - break; - - case SW_RA_INST: - ra_offset = (short)(*addr&INST_OFFSET_MASK); - break; - - case 0x3c1c0000: - return depth +1; - - default: - break; - } - } - - ra = *(unsigned long **)((unsigned long)sp + ra_offset); - sp = (unsigned long*) ((unsigned long)sp+stack_size ); - } - - return depth; -} - -#include <rtthread.h> -extern long list_thread(void); -void assert_hook(const char* ex, const char* func, rt_size_t line) -{ - backtrace(); - - list_thread(); - rt_kprintf("(%s) assertion failed at function:%s, line number:%d \n", ex, func, line); -} - -int backtrace_init(void) -{ -#ifdef RT_DEBUG - rt_assert_set_hook(assert_hook); -#endif - return 0; -} -INIT_DEVICE_EXPORT(backtrace_init); diff --git a/libcpu/mips/x1000/mips_cache_gcc.S b/libcpu/mips/x1000/mips_cache_gcc.S deleted file mode 100644 index 671f193af0..0000000000 --- a/libcpu/mips/x1000/mips_cache_gcc.S +++ /dev/null @@ -1,62 +0,0 @@ -/* - * File : mips_cache_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��19�� Urey the first version - */ - -#ifndef __ASSEMBLY__ -# define __ASSEMBLY__ -#endif - -#include "../common/mips.h" - - .text - .set noreorder - - .globl cache_init - .ent cache_init -cache_init: - .set noreorder - mtc0 zero, CP0_TAGLO - move t0, a0 // cache total size - move t1, a1 // cache line size - li t2, 0x80000000 - addu t3, t0, t2 - -_cache_init_loop: - cache 8, 0(t2) // icache_index_store_tag - cache 9, 0(t2) // dcache_index_store_tag - addu t2, t1 - bne t2, t3, _cache_init_loop - nop - - mfc0 t0, CP0_CONFIG - li t1, 0x7 - not t1 - and t0, t0, t1 - or t0, 0x3 // cacheable, noncoherent, write-back, write allocate - mtc0 t0, CP0_CONFIG - - jr ra - nop - - .set reorder - .end cache_init diff --git a/libcpu/mips/x1000/mips_context_gcc.S b/libcpu/mips/x1000/mips_context_gcc.S deleted file mode 100644 index d4c314ab65..0000000000 --- a/libcpu/mips/x1000/mips_context_gcc.S +++ /dev/null @@ -1,95 +0,0 @@ -/* - * File : mips_context_asm.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��7�� Urey the first version - */ - -#ifndef __ASSEMBLY__ -# define __ASSEMBLY__ -#endif - -#include "../common/mips.h" - - .global rt_thread_switch_interrupt_flag - .global rt_interrupt_from_thread - .global rt_interrupt_to_thread - - .section .text,"ax",@progbits - .set noreorder - .set noat - - .globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mfc0 v0,CP0_STATUS - srl v1,v0,1 - sll v1,v1,1 -# and v1,v0,0xfffffffe - mtc0 v1,CP0_STATUS - jr ra - nop - -LEAF(rt_hw_interrupt_enable) - mtc0 a0,CP0_STATUS - jr ra - nop -END(rt_hw_interrupt_enable) - -/* - * void rt_hw_context_switch_to(rt_uint32 to)/* - * a0 --> to - */ -LEAF(rt_hw_context_switch_to) - lw sp , 0(a0) /* switch to the new stack */ - RESTORE_CONTEXT -END(rt_hw_context_switch_to) - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) - * a0 --> from - * a1 --> to - */ -LEAF(rt_hw_context_switch) - mtc0 ra, CP0_EPC - SAVE_CONTEXT - - sw sp, 0(a0) /* store sp in preempted tasks TCB */ - lw sp, 0(a1) /* get new task stack pointer */ - - RESTORE_CONTEXT -END(rt_hw_context_switch) - -LEAF(rt_hw_context_switch_interrupt) - la t0, rt_thread_switch_interrupt_flag - lw t1, 0(t0) - nop - bnez t1, _reswitch - nop - li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ - sw t1, 0(t0) - la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ - sw a0, 0(t0) -_reswitch: - la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ - sw a1, 0(t0) - jr ra - nop -END(rt_hw_context_switch_interrupt) - diff --git a/libcpu/mips/x1000/mips_excpt.c b/libcpu/mips/x1000/mips_excpt.c deleted file mode 100644 index 5d2a3dce6d..0000000000 --- a/libcpu/mips/x1000/mips_excpt.c +++ /dev/null @@ -1,382 +0,0 @@ -/* - * File : mips_excpt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��7�� Urey the first version - */ - -#include <rtthread.h> -#include <rthw.h> -#include <stdio.h> - -#include "mips.h" -#include "mips_excpt.h" - -extern int backtrace(void); -int backtrace_ctx(mips_reg_ctx *ctx); - -extern long list_thread(void); - -const static char *regstr[] = { - "$0 zero", "$1 at", "$2 v0", "$3 v1", "$4 a0", "$5 a1", "$6 a2", "$7 a3", - "$8 t0", "$9 t1", "$10 t2", "$11 t3", "$12 t4", "$13 t5", "$14 t6", "$15 t7", - "$16 s0", "$17 s1", "$18 s2", "$19 s3", "$20 s4", "$21 s5", "$22 s6", "$23 s7", - "$24 t8", "$25 t9", "$26 k0", "$27 k1", "$28 gp", "$29 sp", "$30 fp", "$31 ra" -}; - -static const char *cause_strings[32] = -{ - /* 0 */ "Int", - /* 1 */ "TLB Mods", - /* 2 */ "TLB Load", - /* 3 */ "TLB Store", - /* 4 */ "Address Load", - /* 5 */ "Address Store", - /* 6 */ "Instruction Bus Error", - /* 7 */ "Data Bus Error", - /* 8 */ "Syscall", - /* 9 */ "Breakpoint", - /* 10 */ "Reserved Instruction", - /* 11 */ "Coprocessor Unuseable", - /* 12 */ "Overflow", - /* 13 */ "Trap", - /* 14 */ "Instruction Virtual Coherency Error", - /* 15 */ "FP Exception", - /* 16 */ "Reserved 16", - /* 17 */ "Reserved 17", - /* 18 */ "Reserved 18", - /* 19 */ "Reserved 19", - /* 20 */ "Reserved 20", - /* 21 */ "Reserved 21", - /* 22 */ "Reserved 22", - /* 23 */ "Watch", - /* 24 */ "Reserved 24", - /* 25 */ "Reserved 25", - /* 26 */ "Reserved 26", - /* 27 */ "Reserved 27", - /* 28 */ "Reserved 28", - /* 29 */ "Reserved 29", - /* 30 */ "Reserved 30", - /* 31 */ "Data Virtual Coherency Error" -}; - - -/** - * exception handle table - */ -exception_func_t sys_exception_handlers[32]; - -static void mod_handler(mips_reg_ctx *regs) -{ - rt_kprintf("tlb modification exception\n"); - rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_kprintf(" cause: 0x%08x\n", read_c0_cause()); - - list_thread(); - - printf("-----------------------------------------------------\n"); - printf("BACKTRACE:\n"); - backtrace(); - printf("-----------------------------------------------------\n"); - - rt_hw_cpu_shutdown(); -} - -static void tlbl_handler(mips_reg_ctx *regs) -{ - rt_kprintf("tlb exception: load\n"); - rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_kprintf(" cause: 0x%08x\n", read_c0_cause()); - - list_thread(); - - printf("-----------------------------------------------------\n"); - printf("BACKTRACE:\n"); - backtrace(); - printf("-----------------------------------------------------\n"); - - rt_hw_cpu_shutdown(); -} - -static void tlbs_handler(mips_reg_ctx *regs) -{ - rt_kprintf("tlb exception: store\n"); - rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_kprintf(" cause: 0x%08x\n", read_c0_cause()); - - list_thread(); - - printf("-----------------------------------------------------\n"); - printf("BACKTRACE:\n"); - backtrace(); - printf("-----------------------------------------------------\n"); - - rt_hw_cpu_shutdown(); -} - -static void adel_handler(mips_reg_ctx *regs) -{ - rt_kprintf("address error exception: load\n"); - rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_kprintf(" cause: 0x%08x\n", read_c0_cause()); - - list_thread(); - rt_kprintf("current thread: %.*s\n", RT_NAME_MAX, rt_thread_self()->name); - - printf("-----------------------------------------------------\n"); - printf("BACKTRACE:\n"); - backtrace(); - printf("-----------------------------------------------------\n"); - - rt_hw_cpu_shutdown(); -} - -static void ades_handler(mips_reg_ctx *regs) -{ - rt_kprintf("address error exception: store\n"); - rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_kprintf(" cause: 0x%08x\n", read_c0_cause()); - - list_thread(); - - printf("-----------------------------------------------------\n"); - printf("BACKTRACE:\n"); - backtrace(); - printf("-----------------------------------------------------\n"); - - rt_hw_cpu_shutdown(); -} - -static void fpe_handler(mips_reg_ctx *regs) -{ - rt_kprintf("floating point exception\n"); - rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_kprintf(" cause: 0x%08x\n", read_c0_cause()); - - list_thread(); - - printf("-----------------------------------------------------\n"); - printf("BACKTRACE:\n"); - backtrace(); - printf("-----------------------------------------------------\n"); - - rt_hw_cpu_shutdown(); -} - - -static void unhandled_exception_handle(mips_reg_ctx *regs) -{ - int i; - unsigned int cause = read_c0_cause(); - unsigned int exc = (cause >> 2) & 0x1f; - - rt_kprintf("exception happens, epc: 0x%08x\n", regs->CP0EPC); - rt_kprintf(" cause: 0x%08x\n", regs->CP0Cause); - - for (i = 0; i < 32; i++) - { - if (i % 4 == 0) - printf("\n"); - printf("%8s %08x ", regstr[i], regs->regs[i]); - } - printf("\n"); - - list_thread(); - rt_hw_cpu_shutdown(); -} - -static void install_default_exception_handler(void) -{ - int i; - - for (i=0; i<sizeof(sys_exception_handlers)/sizeof(sys_exception_handlers[0]); i++) - sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle; - - sys_exception_handlers[EX_MOD] = mod_handler; - sys_exception_handlers[EX_TLBL] = tlbl_handler; - sys_exception_handlers[EX_TLBS] = tlbs_handler; - sys_exception_handlers[EX_ADEL] = adel_handler; - sys_exception_handlers[EX_ADES] = ades_handler; - sys_exception_handlers[EX_FPE] = fpe_handler; -} - -int rt_hw_exception_init(void) -{ - /* install the default exception handler */ - install_default_exception_handler(); - - return RT_EOK; -} - -/** - * setup the exception handle - */ -exception_func_t rt_set_except_vector(int n, exception_func_t func) -{ - exception_func_t old_handler = sys_exception_handlers[n]; - - if ((n == 0) || (n > 32) || (!func)) - { - return 0; - } - - sys_exception_handlers[n] = func; - - return old_handler; -} - -void mips_exception_handler(mips_reg_ctx *ctx) -{ - static int read_epc_count = 0; - static int epc_save = 0; - int i; - unsigned int epc; - - //��� read_epc_count>0 ˵�� c_except_handler �ڶ� epc ʱ�����ˣ����� epc ������һ���µ��쳣 - if (read_epc_count > 0) - { - printf("ERROR: read epc fail when except handle\n"); - epc = epc_save; - read_epc_count = 0; - } - else - { - read_epc_count++; - epc_save = 0; - epc = read_c0_epc(); - epc_save = epc; - - if (epc != 0) - { - printf("-----------------------------------------------------\n"); - for (i = 0; i < 4; i++) - { - printf("%08x:\t%08x\n", - (epc - 4 * 4 + i * 4), - *(unsigned int *) ((epc - 4 * 4 + i * 4) | 0xa0000000)); - } - for (i = 0; i < 4; i++) - { - printf("%08x:\t%08x\n", - (epc + i * 4), - *(unsigned int *) ((epc + i * 4) | 0xa0000000)); - } - printf("-----------------------------------------------------\n"); - } - - read_epc_count--; - } - - printf("-----------------------------------------------------\n"); - unsigned int cause = read_c0_cause(); - unsigned int exc = (cause >> 2) & 0x1f; - printf("CAUSE=%08x --> %s\n", cause, cause_strings[exc]); - printf("EPC=%08x\n", epc); - - for (i = 0; i < 32; i++) - { - if ((i != 0) && (i % 4 == 0)) - printf("\n"); - printf("%8s %08x ", regstr[i], ctx->regs[i]); - } - printf("\n-----------------------------------------------------\n"); - printf("%s: \t %8x\n","CP0Status ", ctx->CP0Status); - printf("%s: \t %8x\n","CP0DataHI ", ctx->CP0DataHI); - printf("%s: \t %8x\n","CP0DataLO ", ctx->CP0DataLO); - printf("%s: \t %8x\n","CP0BadVAddr", ctx->CP0BadVAddr); - printf("%s: \t %8x\n","CP0Cause ", ctx->CP0Cause); - printf("%s: \t %8x\n","CP0EPC ", ctx->CP0EPC); - printf("-----------------------------------------------------\n"); - -#if 0 - switch (exc) - { - case EX_MOD: - /* TLB modified */ - break; - - case EX_TLBL: /* TLB exc(load or ifetch) */ - case EX_TLBS: /* TLB exception (store) */ - - break; - - case EX_ADEL: /* Address err(load or ifetch) */ - case EX_ADES: /* Address error (store) */ - - break; - - case EX_IBE: /* Instruction Bus Error */ - case EX_DBE: /* Data Bus Error */ - - break; - - case EX_SYS: /* Syscall */ - - break; - - case EX_BP: /* Breakpoint */ - case EX_TR: /* Trap instruction */ - - break; - case EX_RI: /* Reserved instruction */ - - break; - case EX_FPE: /* floating point exception */ - break; - - case EX_CPU: /* CoProcessor Unusable */ - - break; - case EX_OV: /* OVerflow */ - case EX_C2E: /* COP2 exception */ - case EX_MDMX: /* MDMX exception */ - case EX_WATCH: /* Watch exception */ - case EX_MCHECK: /* Machine check exception */ - case EX_CacheErr: /* Cache error caused re-entry */ - /* to Debug Mode */ - - break; - default: - rt_kprintf("Unknow exception: %d\r\n", exc); - break; - } -#else - sys_exception_handlers[exc](ctx); -#endif - - rt_hw_cpu_shutdown(); -} - - -void mips_cache_error_handler (unsigned int Addr) -{ - rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); - list_thread(); - rt_hw_cpu_shutdown(); -} - -void mips_tlb_refill_handler(void) -{ - rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); - rt_kprintf(" cause: 0x%08x\n", read_c0_cause()); - list_thread(); - rt_kprintf("current thread: %s\n", rt_thread_self()->name); - rt_hw_cpu_shutdown(); -} diff --git a/libcpu/mips/x1000/mips_excpt_gcc.S b/libcpu/mips/x1000/mips_excpt_gcc.S deleted file mode 100644 index c403adf93b..0000000000 --- a/libcpu/mips/x1000/mips_excpt_gcc.S +++ /dev/null @@ -1,102 +0,0 @@ -/* - * File : mips_excpt_asm.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��7�� Urey the first version - */ - -#ifndef __ASSEMBLY__ -# define __ASSEMBLY__ -#endif - -#include "../common/mips.h" - -#define _EXC_STKSIZE 20*1024 - -;/********************************************************************************************************* -; PTE BASE ��ض��� -;*********************************************************************************************************/ - -#define PTE_BASE_OFFSET 23 -#define PTE_BASE_SIZE 9 -#define MIPS32_BADVPN2_SHIFT 2 - - - .section ".text", "ax" - .set noreorder - -LEAF(mips_tlb_refill_handlerx) - .set push - .set noat - .set noreorder - .set volatile - - ;/* - ; * K1 = CP0_CTXT - ; * K0 = K1 - ; */ - mfc0 k1 , CP0_CONTEXT ;/* K1 ���� Context �Ĵ��� */ - ehb - move k0 , k1 ;/* K0 ���� Context �Ĵ��� */ - - ;/* - ; * K1 <<= PTE_BASE_SIZE - ; * K1 >>= PTE_BASE_SIZE - ; * K1 >>= 4 - ; * K1 >>= MIPS32_BADVPN2_SHIFT - ; * K1 <<= 3 - ; */ - sll k1 , PTE_BASE_SIZE - srl k1 , (PTE_BASE_SIZE + 4 + MIPS32_BADVPN2_SHIFT) ;/* K1 Ϊ BAD VPN2 */ - sll k1 , (4 - 1) - - ;/* - ; * K0 >>= PTE_BASE_OFFSET - ; * K0 <<= PTE_BASE_OFFSET - ; */ - srl k0 , PTE_BASE_OFFSET - sll k0 , PTE_BASE_OFFSET ;/* K0 Ϊ PTE BASE */ - - ;/* - ; * K1 = K1 | K0 - ; */ - or k1 , k1 , k0 ;/* �ϳ� */ - - ;/* - ; * K0 = *K1 - ; * K1 = *(K1 + 4) - ; */ - lw k0 , 0(k1) - lw k1 , 4(k1) - - ;/* - ; * CP0_TLBLO0 = K0 - ; * CP0_TLBLO1 = K1 - ; */ - mtc0 k0 , CP0_ENTRYLO0 ;/* EntryLo0 */ - mtc0 k1 , CP0_ENTRYLO1 ;/* EntryLo1 */ - ehb - - tlbwr ;/* TLB ����滻 */ - - eret ;/* �쳣���� */ - - .set pop -END(mips_tlb_refill_handlerx) diff --git a/libcpu/mips/x1000/mips_fp_gcc.S b/libcpu/mips/x1000/mips_fp_gcc.S deleted file mode 100644 index b219084065..0000000000 --- a/libcpu/mips/x1000/mips_fp_gcc.S +++ /dev/null @@ -1,197 +0,0 @@ -/* - * File : mips_vfp32_asm.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��9�� Urey the first version - */ - -#ifndef __ASSEMBLY__ -# define __ASSEMBLY__ -#endif - -#ifdef __mips_hard_float - -.module hardfloat -.module doublefloat -.set nomips16 - -#include "../common/mips.h" -#undef fp - - .global mips_vfp32_init -LEAF(mips_vfp32_init) - mfc0 t0, CP0_STATUS - or t0 , M_StatusCU1 - mtc0 t0, CP0_STATUS - jr ra - nop -END(mips_vfp32_init) - -# -# FUNCTION: _fpctx_save -# -# DESCRIPTION: save floating point registers to memory starting at a0 -# -# RETURNS: int -# 0: No context saved -# CTX_*: Type of context stored -# - .global _fpctx_save -LEAF(_fpctx_save) - sw zero, LINKCTX_NEXT(a0) - mfc0 t0, CP0_STATUS - li t1, M_StatusCU1 - and t1, t0, t1 - bnez t1, 1f - # FP not enabled, bail out - move v0, zero - jr ra - -1: # Save FP32 base - li t1, ST0_FR - and t0, t0, t1 - cfc1 t2, $31 - sw t2, FP32CTX_CSR(a0) - sdc1 $f0, FP32CTX_0(a0) - sdc1 $f2, FP32CTX_2(a0) - sdc1 $f4, FP32CTX_4(a0) - sdc1 $f6, FP32CTX_6(a0) - sdc1 $f8, FP32CTX_8(a0) - sdc1 $f10, FP32CTX_10(a0) - sdc1 $f12, FP32CTX_12(a0) - sdc1 $f14, FP32CTX_14(a0) - sdc1 $f16, FP32CTX_16(a0) - sdc1 $f18, FP32CTX_18(a0) - sdc1 $f20, FP32CTX_20(a0) - sdc1 $f22, FP32CTX_22(a0) - sdc1 $f24, FP32CTX_24(a0) - sdc1 $f26, FP32CTX_26(a0) - sdc1 $f28, FP32CTX_28(a0) - sdc1 $f30, FP32CTX_30(a0) - bnez t0, 2f - li v0, LINKCTX_TYPE_FP32 - sw v0, LINKCTX_ID(a0) - jr ra - -2: # Save FP64 extra -.set push -.set fp=64 - sdc1 $f1, FP64CTX_1(a0) - sdc1 $f3, FP64CTX_3(a0) - sdc1 $f5, FP64CTX_5(a0) - sdc1 $f7, FP64CTX_7(a0) - sdc1 $f9, FP64CTX_9(a0) - sdc1 $f11, FP64CTX_11(a0) - sdc1 $f13, FP64CTX_13(a0) - sdc1 $f15, FP64CTX_15(a0) - sdc1 $f17, FP64CTX_17(a0) - sdc1 $f19, FP64CTX_19(a0) - sdc1 $f21, FP64CTX_21(a0) - sdc1 $f23, FP64CTX_23(a0) - sdc1 $f25, FP64CTX_25(a0) - sdc1 $f27, FP64CTX_27(a0) - sdc1 $f29, FP64CTX_29(a0) - sdc1 $f31, FP64CTX_31(a0) -.set pop - li v0, LINKCTX_TYPE_FP64 - sw v0, LINKCTX_ID(a0) - jr ra -END(_fpctx_save) - -# -# FUNCTION: _fpctx_load -# -# DESCRIPTION: load floating point registers from context chain starting at a0 -# -# RETURNS: int -# 0: Unrecognised context -# CTX_*: Type of context restored -# - .global _fpctx_load -LEAF(_fpctx_load) - lw v0, LINKCTX_ID(a0) - # Detect type - li t0, LINKCTX_TYPE_FP64 - li t1, LINKCTX_TYPE_FP32 - li t2, M_StatusCU1 - beq v0, t0, 0f - beq v0, t1, 1f - # Don't recognise this context, fail - move v0, zero - jr ra - -0: # FP64 context - # Enable CU1 - di t3 - ehb - or t3, t3, t2 - mtc0 t3, CP0_STATUS - ehb - # Load FP64 extra -.set push -.set fp=64 - ldc1 $f1, FP64CTX_1(a0) - ldc1 $f3, FP64CTX_3(a0) - ldc1 $f5, FP64CTX_5(a0) - ldc1 $f7, FP64CTX_7(a0) - ldc1 $f9, FP64CTX_9(a0) - ldc1 $f11, FP64CTX_11(a0) - ldc1 $f13, FP64CTX_13(a0) - ldc1 $f15, FP64CTX_15(a0) - ldc1 $f17, FP64CTX_17(a0) - ldc1 $f19, FP64CTX_19(a0) - ldc1 $f21, FP64CTX_21(a0) - ldc1 $f23, FP64CTX_23(a0) - ldc1 $f25, FP64CTX_25(a0) - ldc1 $f27, FP64CTX_27(a0) - ldc1 $f29, FP64CTX_29(a0) - ldc1 $f31, FP64CTX_31(a0) -.set pop -1: # FP32 context - # Enable CU1 - di t3 - ehb - or t3, t3, t2 - mtc0 t3, CP0_STATUS - ehb - # Load FP32 base - lw t1, FP32CTX_CSR(a0) - ctc1 t1, $31 - ldc1 $f0, FP32CTX_0(a0) - ldc1 $f2, FP32CTX_2(a0) - ldc1 $f4, FP32CTX_4(a0) - ldc1 $f6, FP32CTX_6(a0) - ldc1 $f8, FP32CTX_8(a0) - ldc1 $f10, FP32CTX_10(a0) - ldc1 $f12, FP32CTX_12(a0) - ldc1 $f14, FP32CTX_14(a0) - ldc1 $f16, FP32CTX_16(a0) - ldc1 $f18, FP32CTX_18(a0) - ldc1 $f20, FP32CTX_20(a0) - ldc1 $f22, FP32CTX_22(a0) - ldc1 $f24, FP32CTX_24(a0) - ldc1 $f26, FP32CTX_26(a0) - ldc1 $f28, FP32CTX_28(a0) - ldc1 $f30, FP32CTX_30(a0) - # Return CTX_FP32/64 - jr ra -END(_fpctx_load) - -#endif diff --git a/libcpu/mips/x1000/stack.c b/libcpu/mips/x1000/stack.c deleted file mode 100644 index 0043ea2a21..0000000000 --- a/libcpu/mips/x1000/stack.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * File : stack.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��8�� Urey the first version - */ - -#include <rtthread.h> - -#include "../common/mips.h" - -register U32 $GP __asm__ ("$28"); - -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) -{ - static rt_uint32_t wSR=0; - static rt_uint32_t wGP; - - mips_reg_ctx *regCtx; - mips_arg_ctx *argCtx; - rt_uint32_t i; - - if (wSR == 0) - { - wSR = read_c0_status(); - wSR &= 0xfffffffe; - wSR |= 0x0403; - - wGP = $GP; - } - - if ((rt_uint32_t) stack_addr & 0x7) - { - stack_addr = (rt_uint8_t *)((rt_uint32_t)stack_addr - 4); - } - - argCtx = (mips_arg_ctx *)((rt_uint32_t)stack_addr - sizeof(mips_arg_ctx)); - regCtx = (mips_reg_ctx *)((rt_uint32_t)stack_addr - sizeof(mips_arg_ctx) - sizeof(mips_reg_ctx)); - - for (i = 0; i < 4; ++i) - { - argCtx->args[i] = i; - } - - //����ͨ�üĴ��� - for (i = 0; i < 32; ++i) - { - regCtx->regs[i] = i; - } - - regCtx->regs[REG_SP] = (rt_uint32_t)stack_addr; - regCtx->regs[REG_A0] = (rt_uint32_t)parameter; - regCtx->regs[REG_GP] = (rt_uint32_t)wGP; - regCtx->regs[REG_FP] = (rt_uint32_t)0x0; - regCtx->regs[REG_RA] = (rt_uint32_t)texit; - - regCtx->CP0DataLO = 0x00; - regCtx->CP0DataHI = 0x00; - regCtx->CP0Cause = read_c0_cause(); - regCtx->CP0Status = wSR; - regCtx->CP0EPC = (rt_uint32_t)tentry; - regCtx->CP0BadVAddr= 0x00; - - return (rt_uint8_t *)(regCtx); -} diff --git a/libcpu/mips/x1000/startup_gcc.S b/libcpu/mips/x1000/startup_gcc.S deleted file mode 100644 index 1376cb7dd4..0000000000 --- a/libcpu/mips/x1000/startup_gcc.S +++ /dev/null @@ -1,328 +0,0 @@ -/* - * File : startup.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��7�� Urey the first version - */ - -#ifndef __ASSEMBLY__ -# define __ASSEMBLY__ -#endif - -#include "../common/mips.h" - -#define IRQ_STACK_SIZE 0x2000 -#define EXC_STACK_SIZE 0x2000 - - - .section ".bss" - ALIGN(4) -irq_stack_low: - .space IRQ_STACK_SIZE -irq_stack_top: - .space 8 - - ALIGN(4) -exc_stack_low: - .space EXC_STACK_SIZE -exc_stack_top: - .space 8 - -#define SYSTEM_STACK 0x80003fe8 - -;/********************************************************************************************************* -; ��� -;*********************************************************************************************************/ - .global rtthread_startup - .global mips_vfp32_init - - .global _start - .section ".start", "ax" - .set noreorder -_start: - .set noreorder - la ra, _start - - li t1, 0x00800000 - mtc0 t1, CP0_CAUSE - - /* init cp0 registers. */ - li t0, 0x1000FC00 /* BEV = 0 and mask all interrupt */ - mtc0 t0, CP0_STATUS - -#ifdef __mips_hard_float - jal mips_vfp32_init - nop -#endif - - /* setup stack pointer */ - li sp, SYSTEM_STACK - la gp, _gp - -_cache_init: - /* init caches, assumes a 4way * 128set * 32byte I/D cache */ - mtc0 zero, CP0_TAGLO /* TAGLO reg */ - mtc0 zero, CP0_TAGHI /* TAGHI reg */ - li t0, 3 /* enable cache for kseg0 accesses */ - mtc0 t0, CP0_CONFIG /* CONFIG reg */ - la t0, 0x80000000 /* an idx op should use an unmappable address */ - ori t1, t0, 0x4000 /* 16kB cache */ - -_cache_loop: - cache 0x8, 0(t0) /* index store icache tag */ - cache 0x9, 0(t0) /* index store dcache tag */ - bne t0, t1, _cache_loop - addiu t0, t0, 0x20 /* 32 bytes per cache line */ - nop - - /* invalidate BTB */ - mfc0 t0, CP0_CONFIG - nop - ori t0, 2 - mtc0 t0, CP0_CONFIG - nop - - - /* jump to RT-Thread RTOS */ - jal rtthread_startup - nop - - /* restart, never die */ - j _start - nop - .set reorder - - -;/********************************************************************************************************* -; �쳣������ -;*********************************************************************************************************/ - /* 0x0 - TLB refill handler */ - .section .vectors.1, "ax", %progbits - j mips_tlb_refill_entry - nop - - /* 0x100 - Cache error handler */ - .section .vectors.2, "ax", %progbits - j mips_cache_error_entry - nop - - /* 0x180 - Exception/Interrupt handler */ - .section .vectors.3, "ax", %progbits - j mips_exception_entry - nop - - /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */ - .section .vectors.4, "ax", %progbits - j mips_interrupt_entry - nop - .section .vectors, "ax", %progbits - - .global mips_exception_handler -// .global mips_syscall -LEAF(mips_exception_entry) - .set push - .set noat - .set noreorder - .set volatile - - mfc0 k0, C0_CAUSE - andi k0, k0, 0x7c - beq zero, k0, except_do_intr - nop - - andi k0,(0x08 << 2) - beq zero,k0,except_do - nop -except_do_intr: - la k0,mips_interrupt_entry - jr k0 - nop -except_do_syscall: -// la k0,mips_syscall -// jr k0 - nop -except_do: - //save sp - move k0,sp - //la sp, exc_stack_top - subu sp, sp, CONTEXT_SIZE - //save context - sw $0, (4*0)(sp); - sw $1, (4*1)(sp); - sw $2, (4*2)(sp); - sw $3, (4*3)(sp); - sw $4, (4*4)(sp); - sw $5, (4*5)(sp); - sw $6, (4*6)(sp); - sw $7, (4*7)(sp); - sw $8, (4*8)(sp); - sw $9, (4*9)(sp); - sw $10, (4*10)(sp); - sw $11, (4*11)(sp); - sw $12, (4*12)(sp); - sw $13, (4*13)(sp); - sw $14, (4*14)(sp); - sw $15, (4*15)(sp); - sw $16, (4*16)(sp); - sw $17, (4*17)(sp); - sw $18, (4*18)(sp); - sw $19, (4*19)(sp); - sw $20, (4*20)(sp); - sw $21, (4*21)(sp); - sw $22, (4*22)(sp); - sw $23, (4*23)(sp); - sw $24, (4*24)(sp); - sw $25, (4*25)(sp); - sw $26, (4*26)(sp); - sw $27, (4*27)(sp); - sw $28, (4*28)(sp); - sw k0, (4*29)(sp); //old sp - sw $30, (4*30)(sp); - sw $31, (4*31)(sp); - - /* STATUS CAUSE EPC.... */ - mfc0 $2, CP0_STATUS - sw $2, STK_OFFSET_SR(sp) - - mfc0 $2, CP0_CAUSE - sw $2, STK_OFFSET_CAUSE(sp) - - mfc0 $2, CP0_BADVADDR - sw $2, STK_OFFSET_BADVADDR(sp) - - MFC0 $2, CP0_EPC - sw $2, STK_OFFSET_EPC(sp) - - mfhi $2 - sw $2, STK_OFFSET_HI(sp) - - mflo $2 - sw $2, STK_OFFSET_LO(sp) - - move a0, sp - la k0, mips_exception_handler - j k0 - nop - - // - - .set pop -END(mips_exception_entry) - - .global mips_tlb_refill_handler -LEAF(mips_tlb_refill_entry) - .set push - .set noat - .set noreorder - .set volatile - - la k0,mips_tlb_refill_handler - jr k0 - - nop - eret - nop - - .set pop -END(mips_tlb_refill_entry) - - .global mips_cache_error_handler -LEAF(mips_cache_error_entry) - .set push - .set noat - .set noreorder - .set volatile - - la k0,mips_cache_error_handler - jr k0 - nop - eret - nop - - .set pop -END(mips_cache_error_entry) - - - -.global rt_interrupt_dispatch -.global rt_interrupt_enter -.global rt_interrupt_leave -LEAF(mips_interrupt_entry) - .set push - .set noat - .set noreorder - .set volatile - - //mfc0 k0,CP0_EPC - SAVE_CONTEXT - - mfc0 t0, CP0_CAUSE - mfc0 t1, CP0_STATUS - and t0, t1 - - andi t0, 0xff00 - beqz t0, spurious_interrupt - nop - - /* let k0 keep the current context sp */ - move k0, sp - - /* switch to kernel stack */ - la sp, irq_stack_top - jal rt_interrupt_enter - nop - jal rt_interrupt_dispatch - nop - jal rt_interrupt_leave - nop - - /* switch sp back to thread's context */ - move sp, k0 - - /* - * if rt_thread_switch_interrupt_flag set, jump to - * rt_hw_context_switch_interrupt_do and don't return - */ - la k0, rt_thread_switch_interrupt_flag - lw k1, 0(k0) - beqz k1, spurious_interrupt - nop - sw zero, 0(k0) /* clear flag */ - nop - - /* - * switch to the new thread - */ - la k0, rt_interrupt_from_thread - lw k1, 0(k0) - nop - sw sp, 0(k1) /* store sp in preempted tasks's TCB */ - - la k0, rt_interrupt_to_thread - lw k1, 0(k0) - nop - lw sp, 0(k1) /* get new task's stack pointer */ - j spurious_interrupt - nop -spurious_interrupt: - RESTORE_CONTEXT - - .set pop -END(mips_interrupt_entry) diff --git a/libcpu/mips/x1000/x1000.h b/libcpu/mips/x1000/x1000.h deleted file mode 100644 index aa18297395..0000000000 --- a/libcpu/mips/x1000/x1000.h +++ /dev/null @@ -1,284 +0,0 @@ -/* - * File : x1000.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2015-11-19 Urey the first version - */ - -#ifndef __X1000_H__ -#define __X1000_H__ - -#include "../common/mips.h" - -#ifndef __ASSEMBLY__ - -#define cache_unroll(base,op) \ - __asm__ __volatile__(" \ - .set noreorder; \ - .set mips3; \ - cache %1, (%0); \ - .set mips0; \ - .set reorder" \ - : \ - : "r" (base), \ - "i" (op)); - -/* cpu pipeline flush */ -static inline void jz_sync(void) -{ - __asm__ volatile ("sync"); -} - -static inline void writeb(u8 value, u32 address) -{ - *((volatile u8 *) address) = value; -} -static inline void writew( u16 value, u32 address) -{ - *((volatile u16 *) address) = value; -} -static inline void writel(u32 value, u32 address) -{ - *((volatile u32 *) address) = value; -} - -static inline u8 readb(u32 address) -{ - return *((volatile u8 *)address); -} - -static inline u16 readw(u32 address) -{ - return *((volatile u16 *)address); -} - -static inline u32 readl(u32 address) -{ - return *((volatile u32 *)address); -} - -static inline void jz_writeb(u32 address, u8 value) -{ - *((volatile u8 *)address) = value; -} - -static inline void jz_writew(u32 address, u16 value) -{ - *((volatile u16 *)address) = value; -} - -static inline void jz_writel(u32 address, u32 value) -{ - *((volatile u32 *)address) = value; -} - -static inline u8 jz_readb(u32 address) -{ - return *((volatile u8 *)address); -} - -static inline u16 jz_readw(u32 address) -{ - return *((volatile u16 *)address); -} - -static inline u32 jz_readl(u32 address) -{ - return *((volatile u32 *)address); -} - -#define BIT(n) (0x01u << (n)) -#define BIT0 (0x01u << 0) -#define BIT1 (0x01u << 1) -#define BIT2 (0x01u << 2) -#define BIT3 (0x01u << 3) -#define BIT4 (0x01u << 4) -#define BIT5 (0x01u << 5) -#define BIT6 (0x01u << 6) -#define BIT7 (0x01u << 7) -#define BIT8 (0x01u << 8) -#define BIT9 (0x01u << 9) -#define BIT10 (0x01u << 10) -#define BIT11 (0x01u << 11) -#define BIT12 (0x01u << 12) -#define BIT13 (0x01u << 13) -#define BIT14 (0x01u << 14) -#define BIT15 (0x01u << 15) -#define BIT16 (0x01u << 16) -#define BIT17 (0x01u << 17) -#define BIT18 (0x01u << 18) -#define BIT19 (0x01u << 19) -#define BIT20 (0x01u << 20) -#define BIT21 (0x01u << 21) -#define BIT22 (0x01u << 22) -#define BIT23 (0x01u << 23) -#define BIT24 (0x01u << 24) -#define BIT25 (0x01u << 25) -#define BIT26 (0x01u << 26) -#define BIT27 (0x01u << 27) -#define BIT28 (0x01u << 28) -#define BIT29 (0x01u << 29) -#define BIT30 (0x01u << 30) -#define BIT31 (0x01u << 31) - -/* Generate the bit field mask from msb to lsb */ -#define BITS_H2L(msb, lsb) ((0xFFFFFFFF >> (32-((msb)-(lsb)+1))) << (lsb)) - - -/* Get the bit field value from the data which is read from the register */ -#define get_bf_value(data, lsb, mask) (((data) & (mask)) >> (lsb)) - -#endif /* !ASSEMBLY */ - - -//---------------------------------------------------------------------- -// Register Definitions -// -/* AHB0 BUS Devices Base */ -#define HARB0_BASE 0xB3000000 -#define EMC_BASE 0xB3010000 -#define DDRC_BASE 0xB3020000 -#define MDMAC_BASE 0xB3030000 -#define LCD_BASE 0xB3050000 -#define TVE_BASE 0xB3050000 -#define SLCD_BASE 0xB3050000 -#define CIM_BASE 0xB3060000 -#define IPU_BASE 0xB3080000 -/* AHB1 BUS Devices Base */ -#define HARB1_BASE 0xB3200000 -#define DMAGP0_BASE 0xB3210000 -#define DMAGP1_BASE 0xB3220000 -#define DMAGP2_BASE 0xB3230000 -#define MC_BASE 0xB3250000 -#define ME_BASE 0xB3260000 -#define DEBLK_BASE 0xB3270000 -#define IDCT_BASE 0xB3280000 -#define CABAC_BASE 0xB3290000 -#define TCSM0_BASE 0xB32B0000 -#define TCSM1_BASE 0xB32C0000 -#define SRAM_BASE 0xB32D0000 -/* AHB2 BUS Devices Base */ -#define HARB2_BASE 0xB3400000 -#define NEMC_BASE 0xB3410000 -#define DMAC_BASE 0xB3420000 -#define UHC_BASE 0xB3430000 -//#define UDC_BASE 0xB3440000 -#define SFC_BASE 0xB3440000 -#define GPS_BASE 0xB3480000 -#define ETHC_BASE 0xB34B0000 -#define BCH_BASE 0xB34D0000 -#define MSC0_BASE 0xB3450000 -#define MSC1_BASE 0xB3460000 -#define MSC2_BASE 0xB3470000 -#define OTG_BASE 0xb3500000 - -/* APB BUS Devices Base */ -#define CPM_BASE 0xB0000000 -#define INTC_BASE 0xB0001000 -#define TCU_BASE 0xB0002000 -#define WDT_BASE 0xB0002000 -#define OST_BASE 0xB2000000 /* OS Timer */ -#define RTC_BASE 0xB0003000 -#define GPIO_BASE 0xB0010000 -#define AIC_BASE 0xB0020000 -#define DMIC_BASE 0xB0021000 -#define ICDC_BASE 0xB0020000 -#define UART0_BASE 0xB0030000 -#define UART1_BASE 0xB0031000 -#define UART2_BASE 0xB0032000 -#define SCC_BASE 0xB0040000 -#define SSI0_BASE 0xB0043000 -#define SSI1_BASE 0xB0044000 -#define SSI2_BASE 0xB0045000 -#define I2C0_BASE 0xB0050000 -#define I2C1_BASE 0xB0051000 -#define I2C2_BASE 0xB0052000 -#define PS2_BASE 0xB0060000 -#define SADC_BASE 0xB0070000 -#define OWI_BASE 0xB0072000 -#define TSSI_BASE 0xB0073000 - -/* NAND CHIP Base Address*/ -#define NEMC_CS1_IOBASE 0Xbb000000 -#define NEMC_CS2_IOBASE 0Xba000000 -#define NEMC_CS3_IOBASE 0Xb9000000 -#define NEMC_CS4_IOBASE 0Xb8000000 -#define NEMC_CS5_IOBASE 0Xb7000000 -#define NEMC_CS6_IOBASE 0Xb6000000 - -/********************************************************************************************************* -** WDT -*********************************************************************************************************/ -#define WDT_TDR (0x00) -#define WDT_TCER (0x04) -#define WDT_TCNT (0x08) -#define WDT_TCSR (0x0C) - -#define REG_WDT_TDR REG16(WDT_BASE + WDT_TDR) -#define REG_WDT_TCER REG8(WDT_BASE + WDT_TCER) -#define REG_WDT_TCNT REG16(WDT_BASE + WDT_TCNT) -#define REG_WDT_TCSR REG16(WDT_BASE + WDT_TCSR) - -#define WDT_TSCR_WDTSC (1 << 16) - -#define WDT_TCSR_PRESCALE_1 (0 << 3) -#define WDT_TCSR_PRESCALE_4 (1 << 3) -#define WDT_TCSR_PRESCALE_16 (2 << 3) -#define WDT_TCSR_PRESCALE_64 (3 << 3) -#define WDT_TCSR_PRESCALE_256 (4 << 3) -#define WDT_TCSR_PRESCALE_1024 (5 << 3) - -#define WDT_TCSR_EXT_EN (1 << 2) -#define WDT_TCSR_RTC_EN (1 << 1) -#define WDT_TCSR_PCK_EN (1 << 0) - -#define WDT_TCER_TCEN (1 << 0) - -/* RTC Reg */ -#define RTC_RTCCR (0x00) /* rw, 32, 0x00000081 */ -#define RTC_RTCSR (0x04) /* rw, 32, 0x???????? */ -#define RTC_RTCSAR (0x08) /* rw, 32, 0x???????? */ -#define RTC_RTCGR (0x0c) /* rw, 32, 0x0??????? */ -#define RTC_HCR (0x20) /* rw, 32, 0x00000000 */ -#define RTC_HWFCR (0x24) /* rw, 32, 0x0000???0 */ -#define RTC_HRCR (0x28) /* rw, 32, 0x00000??0 */ -#define RTC_HWCR (0x2c) /* rw, 32, 0x00000008 */ -#define RTC_HWRSR (0x30) /* rw, 32, 0x00000000 */ -#define RTC_HSPR (0x34) /* rw, 32, 0x???????? */ -#define RTC_WENR (0x3c) /* rw, 32, 0x00000000 */ -#define RTC_CKPCR (0x40) /* rw, 32, 0x00000010 */ -#define RTC_OWIPCR (0x44) /* rw, 32, 0x00000010 */ -#define RTC_PWRONCR (0x48) /* rw, 32, 0x???????? */ - -#define RTCCR_WRDY BIT(7) -#define WENR_WEN BIT(31) - -#define RECOVERY_SIGNATURE (0x001a1a) -#define REBOOT_SIGNATURE (0x003535) -#define UNMSAK_SIGNATURE (0x7c0000)//do not use these bits - - -#include "x1000_cpm.h" -#include "x1000_intc.h" -#include "x1000_otg_dwc.h" -#include "x1000_aic.h" -#include "x1000_slcdc.h" - -#endif /* _JZ_M150_H_ */ diff --git a/libcpu/mips/x1000/x1000_aic.h b/libcpu/mips/x1000/x1000_aic.h deleted file mode 100644 index ed2c8e6f73..0000000000 --- a/libcpu/mips/x1000/x1000_aic.h +++ /dev/null @@ -1,794 +0,0 @@ -/** - ****************************************************************************** - * @file x1000_aic.h - * @author Urey - * @version V1.0.0 - * @date 2017��2��20�� - * @brief TODO - ****************************************************************************** -**/ - - -#ifndef _X1000_AIC_H_ -#define _X1000_AIC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#define AIC_FR (AIC_BASE + 0x00) -#define AIC_CR (AIC_BASE + 0x04) -#define AIC_ACCR1 (AIC_BASE + 0x08) -#define AIC_ACCR2 (AIC_BASE + 0x0c) -#define AIC_I2SCR (AIC_BASE + 0x10) -#define AIC_SR (AIC_BASE + 0x14) -#define AIC_ACSR (AIC_BASE + 0x18) -#define AIC_I2SSR (AIC_BASE + 0x1c) -#define AIC_ACCAR (AIC_BASE + 0x20) -#define AIC_ACCDR (AIC_BASE + 0x24) -#define AIC_ACSAR (AIC_BASE + 0x28) -#define AIC_ACSDR (AIC_BASE + 0x2c) -#define AIC_I2SDIV (AIC_BASE + 0x30) -#define AIC_DR (AIC_BASE + 0x34) - -#define SPDIF_ENA (AIC_BASE + 0x80) -#define SPDIF_CTRL (AIC_BASE + 0x84) -#define SPDIF_STATE (AIC_BASE + 0x88) -#define SPDIF_CFG1 (AIC_BASE + 0x8c) -#define SPDIF_CFG2 (AIC_BASE + 0x90) -#define SPDIF_FIFO (AIC_BASE + 0x94) - -#define ICDC_CKCFG (AIC_BASE + 0xa0) -#define ICDC_RGADW (AIC_BASE + 0xa4) -#define ICDC_RGDATA (AIC_BASE + 0xa8) - - -/* AIC_FR definition */ -#define AIC_FR_RFTH_LSB 24 -#define AIC_FR_RFTH(x) ( ( (x)/2 - 1 ) << AIC_FR_RFTH_LSB) // 2, 4, ..., 32 -#define AIC_FR_RFTH_MASK BITS_H2L(27, AIC_FR_RFTH_LSB) - -#define AIC_FR_TFTH_LSB 16 -#define AIC_FR_TFTH(x) ( ( (x)/2 ) << AIC_FR_TFTH_LSB) // 2, 4, ..., 32 -#define AIC_FR_TFTH_MASK BITS_H2L(20, AIC_FR_TFTH_LSB) - -/* new@4770 */ -#define AIC_FR_IBCKD BIT10 - -/* new@4770 */ -#define AIC_FR_ISYNCD BIT9 - -/* new@4770 */ -#define IC_FR_DMODE BIT8 - -#define AIC_FR_LSMP BIT6 -#define AIC_FR_ICDC BIT5 -#define AIC_FR_AUSEL BIT4 -#define AIC_FR_RST BIT3 -#define AIC_FR_BCKD BIT2 -#define AIC_FR_SYNCD BIT1 -#define AIC_FR_ENB BIT0 - - -/* AIC_CR definition */ -#define AIC_CR_PACK16 BIT28 - -#define AIC_CR_CHANNEL_LSB 24 -#define AIC_CR_CHANNEL_MASK BITS_H2L(26, 24) -#define AIC_CR_CHANNEL_MONO (0x0 << AIC_CR_CHANNEL_LSB) -#define AIC_CR_CHANNEL_STEREO (0x1 << AIC_CR_CHANNEL_LSB) -#define AIC_CR_CHANNEL_4CHNL (0x3 << AIC_CR_CHANNEL_LSB) -#define AIC_CR_CHANNEL_6CHNL (0x5 << AIC_CR_CHANNEL_LSB) -#define AIC_CR_CHANNEL_8CHNL (0x7 << AIC_CR_CHANNEL_LSB) - -#define AIC_CR_OSS_LSB 19 -#define AIC_CR_OSS_MASK BITS_H2L(21, AIC_CR_OSS_LSB) -#define AIC_CR_OSS(n) (((n) > 18 ? (n)/6 : (n)/9) << AIC_CR_OSS_LSB) /* n = 8, 16, 18, 20, 24 */ - -#define AIC_CR_ISS_LSB 16 -#define AIC_CR_ISS_MASK BITS_H2L(18, AIC_CR_ISS_LSB) -#define AIC_CR_ISS(n) (((n) > 18 ? (n)/6 : (n)/9) << AIC_CR_ISS_LSB) /* n = 8, 16, 18, 20, 24 */ - -#define AIC_CR_RDMS BIT15 -#define AIC_CR_TDMS BIT14 -#define AIC_CR_M2S BIT11 -#define AIC_CR_ENDSW BIT10 -#define AIC_CR_AVSTSU BIT9 -#define AIC_CR_TFLUSH BIT8 -#define AIC_CR_RFLUSH BIT7 -#define AIC_CR_EROR BIT6 -#define AIC_CR_ETUR BIT5 -#define AIC_CR_ERFS BIT4 -#define AIC_CR_ETFS BIT3 -#define AIC_CR_ENLBF BIT2 -#define AIC_CR_ERPL BIT1 -#define AIC_CR_EREC BIT0 - -/* AIC controller AC-link control register 1(ACCR1) */ -#define AIC_ACCR1_RS_LSB 16 -#define AIC_ACCR1_RS_MASK BITS_H2L(25, AIC_ACCR1_RS_LSB) -#define AIC_ACCR1_RS_SLOT(n) ((1 << ((n) - 3)) << AIC_ACCR1_RS_LSB) /* n = 3 .. 12 */ - -#define AIC_ACCR1_XS_LSB 0 -#define AIC_ACCR1_XS_MASK BITS_H2L(9, AIC_ACCR1_XS_LSB) -#define AIC_ACCR1_XS_SLOT(n) ((1 << ((n) - 3)) << AIC_ACCR1_XS_LSB) /* n = 3 .. 12 */ - -/* AIC controller AC-link control register 2 (ACCR2) */ -#define AIC_ACCR2_ERSTO BIT18 -#define AIC_ACCR2_ESADR BIT17 -#define AIC_ACCR2_ECADT BIT16 -#define AIC_ACCR2_SO BIT3 -#define AIC_ACCR2_SR BIT2 -#define AIC_ACCR2_SS BIT1 -#define AIC_ACCR2_SA BIT0 - -/* AIC controller i2s/msb-justified control register (I2SCR) */ -#define AIC_I2SCR_RFIRST BIT17 -#define AIC_I2SCR_SWLH BIT16 -#define AIC_I2SCR_ISTPBK BIT13 -#define AIC_I2SCR_STPBK BIT12 -#define AIC_I2SCR_ESCLK BIT4 -#define AIC_I2SCR_AMSL BIT0 - -/* AIC controller FIFO status register (AICSR) */ -#define AIC_SR_RFL_LSB 24 -#define AIC_SR_RFL_MASK BITS_H2L(29, AIC_SR_RFL_LSB) - -#define AIC_SR_TFL_LSB 8 -#define AIC_SR_TFL_MASK BITS_H2L(13, AIC_SR_TFL_LSB) - -#define AIC_SR_ROR BIT6 -#define AIC_SR_TUR BIT5 -#define AIC_SR_RFS BIT4 -#define AIC_SR_TFS BIT3 - -/* AIC controller AC-link status register (ACSR) */ -#define AIC_ACSR_SLTERR BIT21 -#define AIC_ACSR_CRDY BIT20 -#define AIC_ACSR_CLPM BIT19 -#define AIC_ACSR_RSTO BIT18 -#define AIC_ACSR_SADR BIT17 -#define AIC_ACSR_CADT BIT16 - -/* AIC controller I2S/MSB-justified status register (I2SSR) */ -#define AIC_I2SSR_CHBSY BIT5 -#define AIC_I2SSR_TBSY BIT4 -#define AIC_I2SSR_RBSY BIT3 -#define AIC_I2SSR_BSY BIT2 - -/* AIC controller AC97 codec command address register (ACCAR) */ -#define AIC_ACCAR_CAR_LSB 0 -#define AIC_ACCAR_CAR_MASK BITS_H2L(19, AIC_ACCAR_CAR_LSB) - - -/* AIC controller AC97 codec command data register (ACCDR) */ -#define AIC_ACCDR_CDR_LSB 0 -#define AIC_ACCDR_CDR_MASK BITS_H2L(19, AIC_ACCDR_CDR_LSB) - -/* AC97 read and write macro based on ACCAR and ACCDR */ -#define AC97_READ_CMD BIT19 -#define AC97_WRITE_CMD (BIT19 & ~BIT19) - -#define AC97_INDEX_LSB 12 -#define AC97_INDEX_MASK BITS_H2L(18, AC97_INDEX_LSB) - -#define AC97_DATA_LSB 4 -#define AC97_DATA_MASK BITS_H2L(19, AC97_DATA_LSB) - -/* AIC controller AC97 codec status address register (ACSAR) */ -#define AIC_ACSAR_SAR_LSB 0 -#define AIC_ACSAR_SAR_MASK BITS_H2L(19, AIC_ACSAR_SAR_LSB) - -/* AIC controller AC97 codec status data register (ACSDR) */ -#define AIC_ACSDR_SDR_LSB 0 -#define AIC_ACSDR_SDR_MASK BITS_H2L(19, AIC_ACSDR_SDR_LSB) - -/* AIC controller I2S/MSB-justified clock divider register (I2SDIV) */ -#define AIC_I2SDIV_IDIV_LSB 16 -#define AIC_I2SDIV_IDIV_MASK BITS_H2L(24, AIC_I2SDIV_IDIV_LSB) -#define AIC_I2SDIV_DIV_LSB 0 -#define AIC_I2SDIV_DIV_MASK BITS_H2L(8, AIC_I2SDIV_DIV_LSB) - -/* SPDIF enable register (SPDIF_ENA) */ -#define SPDIF_ENA_SPEN BIT0 - -/* SPDIF control register (SPDIF_CTRL) */ -#define SPDIF_CTRL_DMAEN BIT15 -#define SPDIF_CTRL_DTYPE BIT14 -#define SPDIF_CTRL_SIGN BIT13 -#define SPDIF_CTRL_INVALID BIT12 -#define SPDIF_CTRL_RST BIT11 -#define SPDIF_CTRL_SPDIFI2S BIT10 -#define SPDIF_CTRL_MTRIG BIT1 -#define SPDIF_CTRL_MFFUR BIT0 - -/* SPDIF state register (SPDIF_STAT) */ -#define SPDIF_STAT_BUSY BIT7 -#define SPDIF_STAT_FTRIG BIT1 -#define SPDIF_STAT_FUR BIT0 - -#define SPDIF_STAT_FLVL_LSB 8 -#define SPDIF_STAT_FLVL_MASK BITS_H2L(14, SPDIF_STAT_FLVL_LSB) - -/* SPDIF configure 1 register (SPDIF_CFG1) */ -#define SPDIF_CFG1_INITLVL BIT17 -#define SPDIF_CFG1_ZROVLD BIT16 - -#define SPDIF_CFG1_TRIG_LSB 12 -#define SPDIF_CFG1_TRIG_MASK BITS_H2L(13, SPDIF_CFG1_TRIG_LSB) -#define SPDIF_CFG1_TRIG(n) (((n) > 16 ? 3 : (n)/8) << SPDIF_CFG1_TRIG_LSB) /* n = 4, 8, 16, 32 */ - -#define SPDIF_CFG1_SRCNUM_LSB 8 -#define SPDIF_CFG1_SRCNUM_MASK BITS_H2L(11, SPDIF_CFG1_SRCNUM_LSB) - -#define SPDIF_CFG1_CH1NUM_LSB 4 -#define SPDIF_CFG1_CH1NUM_MASK BITS_H2L(7, SPDIF_CFG1_CH1NUM_LSB) - -#define SPDIF_CFG1_CH2NUM_LSB 0 -#define SPDIF_CFG1_CH2NUM_MASK BITS_H2L(3, SPDIF_CFG1_CH2NUM_LSB) - -/* SPDIF configure 2 register (SPDIF_CFG2) */ -#define SPDIF_CFG2_MAXWL BIT18 -#define SPDIF_CFG2_PRE BIT3 -#define SPDIF_CFG2_COPYN BIT2 -#define SPDIF_CFG2_AUDION BIT1 -#define SPDIF_CFG2_CONPRO BIT0 - -#define SPDIF_CFG2_FS_LSB 26 -#define SPDIF_CFG2_FS_MASK BITS_H2L(29, SPDIF_CFG2_FS_LSB) - -#define SPDIF_CFG2_ORGFRQ_LSB 22 -#define SPDIF_CFG2_ORGFRQ_MASK BITS_H2L(25, SPDIF_CFG2_ORGFRQ_LSB) - -#define SPDIF_CFG2_SAMWL_LSB 19 -#define SPDIF_CFG2_SAMWL_MASK BITS_H2L(21, SPDIF_CFG2_SAMWL_LSB) - -#define SPDIF_CFG2_CLKACU_LSB 16 -#define SPDIF_CFG2_CLKACU_MASK BITS_H2L(17, SPDIF_CFG2_CLKACU_LSB) - -#define SPDIF_CFG2_CATCODE_LSB 8 -#define SPDIF_CFG2_CATCODE_MASK BITS_H2L(15, SPDIF_CFG2_CATCODE_LSB) - -#define SPDIF_CFG2_CHMD_LSB 6 -#define SPDIF_CFG2_CHMD_MASK BITS_H2L(7, SPDIF_CFG2_CHMD_LSB) - -/* ICDC internal register access control register(RGADW) */ -#define ICDC_RGADW_RGWR BIT16 - -#define ICDC_RGADW_RGADDR_LSB 8 -#define ICDC_RGADW_RGADDR_MASK BITS_H2L(14, ICDC_RGADW_RGADDR_LSB) - -#define ICDC_RGADW_RGDIN_LSB 0 -#define ICDC_RGADW_RGDIN_MASK BITS_H2L(7, ICDC_RGADW_RGDIN_LSB) - - -/* ICDC internal register data output register (RGDATA)*/ -#define ICDC_RGDATA_IRQ BIT8 - -#define ICDC_RGDATA_RGDOUT_LSB 0 -#define ICDC_RGDATA_RGDOUT_MASK BITS_H2L(7, ICDC_RGDATA_RGDOUT_LSB) - - -#ifndef __MIPS_ASSEMBLER - - -#define REG_AIC_FR REG32(AIC_FR) -#define REG_AIC0_FR REG32(AIC0_FR) -#define REG_AIC_CR REG32(AIC_CR) -#define REG_AIC_ACCR1 REG32(AIC_ACCR1) -#define REG_AIC_ACCR2 REG32(AIC_ACCR2) -#define REG_AIC_I2SCR REG32(AIC_I2SCR) -#define REG_AIC_SR REG32(AIC_SR) -#define REG_AIC_ACSR REG32(AIC_ACSR) -#define REG_AIC_I2SSR REG32(AIC_I2SSR) -#define REG_AIC_ACCAR REG32(AIC_ACCAR) -#define REG_AIC_ACCDR REG32(AIC_ACCDR) -#define REG_AIC_ACSAR REG32(AIC_ACSAR) -#define REG_AIC_ACSDR REG32(AIC_ACSDR) -#define REG_AIC_I2SDIV REG32(AIC_I2SDIV) -#define REG_AIC_DR REG32(AIC_DR) - -#define REG_SPDIF_ENA REG32(SPDIF_ENA) -#define REG_SPDIF_CTRL REG32(SPDIF_CTRL) -#define REG_SPDIF_STATE REG32(SPDIF_STATE) -#define REG_SPDIF_CFG1 REG32(SPDIF_CFG1) -#define REG_SPDIF_CFG2 REG32(SPDIF_CFG2) -#define REG_SPDIF_FIFO REG32(SPDIF_FIFO) - -#define REG_ICDC_RGADW REG32(ICDC_RGADW) -#define REG_ICDC_RGDATA REG32(ICDC_RGDATA) - -#if 0 -#define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB ) -#define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB ) - -#define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL ) -#define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL ) - -#define __aic_play_zero() ( REG_AIC_FR &= ~AIC_FR_LSMP ) -#define __aic_play_lastsample() ( REG_AIC_FR |= AIC_FR_LSMP ) - -#define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD ) -#define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) ) - -#define jz_aic_ibck_in (CLRREG32(AIC_FR, AIC_FR_IBCKD)) -#define jz_aic_ibck_out (SETREG32(AIC_FR, AIC_FR_IBCKD)) - -#define jz_aic_isync_in (CLRREG32(AIC_FR, AIC_FR_ISYNCD)) -#define jz_aic_isync_out (SETREG32(AIC_FR, AIC_FR_ISYNCD)) - -#define jz_aic_enable_dmode (SETREG32(AIC_FR, AIC_FR_DMODE)) -#define jz_aic_disable_dmode (CLRREG32(AIC_FR, AIC_FR_DMODE)) - -#define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST ) - -#define __aic_reset() \ -do { \ - REG_AIC_FR |= AIC_FR_RST; \ -} while(0) - - -#define __aic_set_transmit_trigger(n) \ -do { \ - REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \ - REG_AIC_FR |= ((n) << AIC_FR_TFTH_LSB); \ -} while(0) - -#define __aic_set_receive_trigger(n) \ -do { \ - REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \ - REG_AIC_FR |= ((n) << AIC_FR_RFTH_LSB); \ -} while(0) - -#define __aic_enable_oldstyle() -#define __aic_enable_newstyle() -#define __aic_enable_pack16() ( REG_AIC_CR |= AIC_CR_PACK16 ) -#define __aic_enable_unpack16() ( REG_AIC_CR &= ~AIC_CR_PACK16) - -#define jz_aic_set_channel(n) \ - do { \ - switch((n)) { \ - case 1: \ - case 2: \ - case 4: \ - case 6: \ - case 8: \ - CLRREG32(AIC_CR, AIC_CR_CHANNEL_MASK); \ - SETREG32(AIC_CR, ((((n) - 1) << 24) & AIC_CR_CHANNEL_MASK)); \ - break; \ - default: \ - printk("invalid aic channel, must be 1, 2, 4, 6, or 8\n"); \ - break; \ - } \ - } while(0) - -/* n = AIC_CR_CHANNEL_MONO,AIC_CR_CHANNEL_STEREO ... */ -#define __aic_out_channel_select(n) \ -do { \ - REG_AIC_CR &= ~AIC_CR_CHANNEL_MASK; \ - REG_AIC_CR |= ((n) << AIC_CR_CHANNEL_LSB ); \ -} while(0) - -#define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC ) -#define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC ) -#define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL ) -#define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL ) -#define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF ) -#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF ) - -#define __aic_flush_tfifo() ( REG_AIC_CR |= AIC_CR_TFLUSH ) -#define __aic_unflush_tfifo() ( REG_AIC_CR &= ~AIC_CR_TFLUSH ) -#define __aic_flush_rfifo() ( REG_AIC_CR |= AIC_CR_RFLUSH ) -#define __aic_unflush_rfifo() ( REG_AIC_CR &= ~AIC_CR_RFLUSH ) - -#define __aic_enable_transmit_intr() \ - ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) ) -#define __aic_disable_transmit_intr() \ - ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) ) -#define __aic_enable_receive_intr() \ - ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) ) -#define __aic_disable_receive_intr() \ - ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) ) - -#define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS ) -#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS ) -#define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS ) -#define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS ) - -#define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S ) -#define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S ) -#define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW ) -#define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW ) -#define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU ) -#define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU ) - -#define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT(3) -#define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT(4) -#define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT(6) -#define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT(7) -#define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT(8) -#define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT(9) - -#define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT(3) -#define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT(4) -#define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT(6) -#define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT(7) -#define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT(8) -#define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT(9) - -#define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK ) -#define __ac97_set_xs_mono() \ -do { \ - REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ - REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \ -} while(0) -#define __ac97_set_xs_stereo() \ -do { \ - REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ - REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \ -} while(0) - -/* In fact, only stereo is support now. */ -#define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK ) -#define __ac97_set_rs_mono() \ -do { \ - REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ - REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \ -} while(0) -#define __ac97_set_rs_stereo() \ -do { \ - REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ - REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \ -} while(0) - -#define __ac97_warm_reset_codec() \ - do { \ - REG_AIC_ACCR2 |= AIC_ACCR2_SA; \ - REG_AIC_ACCR2 |= AIC_ACCR2_SS; \ - udelay(2); \ - REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \ - REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \ - } while (0) - -#define __ac97_cold_reset_codec() \ - do { \ - REG_AIC_ACCR2 |= AIC_ACCR2_SR; \ - udelay(2); \ - REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \ - } while (0) - -/* n=8,16,18,20 */ -#define __ac97_set_iass(n) \ - ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT ) -#define __ac97_set_oass(n) \ - ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT ) - -/* This bit should only be set in 2 channels configuration */ -#define __i2s_send_rfirst() ( REG_AIC_I2SCR |= AIC_I2SCR_RFIRST ) /* RL */ -#define __i2s_send_lfirst() ( REG_AIC_I2SCR &= ~AIC_I2SCR_RFIRST ) /* LR */ - -/* This bit should only be set in 2 channels configuration and 16bit-packed mode */ -#define __i2s_switch_lr() ( REG_AIC_I2SCR |= AIC_I2SCR_SWLH ) -#define __i2s_unswitch_lr() ( REG_AIC_I2SCR &= ~AIC_I2SCR_SWLH ) - -#define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL ) -#define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL ) - -/* n=8,16,18,20,24 */ -/*#define __i2s_set_sample_size(n) \ - ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/ - -#define __i2s_out_channel_select(n) __aic_out_channel_select(n) - -#define __i2s_set_oss_sample_size(n) \ - ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS(n)) -#define __i2s_set_iss_sample_size(n) \ - ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS(n)) - -#define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK ) -#define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK ) - -#define __i2s_stop_ibitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_ISTPBK ) -#define __i2s_start_ibitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_ISTPBK ) - -#define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS ) -#define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS ) -#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR ) -#define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR ) - -#define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) ) - -#define __aic_get_transmit_resident() \ - ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_LSB ) -#define __aic_get_receive_count() \ - ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_LSB ) - -#define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT ) -#define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR ) -#define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO ) -#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM ) -#define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY ) -#define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR ) -#define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR ) - -#define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY ) - -#define __ac97_out_rcmd_addr(reg) \ -do { \ - REG_AIC_ACCAR = AC97_READ_CMD | ((reg) << AC97_INDEX_LSB); \ -} while (0) - -#define __ac97_out_wcmd_addr(reg) \ -do { \ - REG_AIC_ACCAR = AC97_WRITE_CMD | ((reg) << AC97_INDEX_LSB); \ -} while (0) - -#define __ac97_out_data(value) \ -do { \ - REG_AIC_ACCDR = ((value) << AC97_DATA_LSB); \ -} while (0) - -#define __ac97_in_data() \ - ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> AC97_DATA_LSB ) - -#define __ac97_in_status_addr() \ - ( (REG_AIC_ACSAR & AC97_INDEX_MASK) >> AC97_INDEX_LSB ) - -#define __i2s_set_sample_rate(i2sclk, sync) \ - ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) ) - -#define __aic_write_tfifo(v) ( REG_AIC_DR = (v) ) -#define __aic_read_rfifo() ( REG_AIC_DR ) - -#define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC ) -#define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC ) -#define __aic0_internal_codec() ( REG_AIC0_FR |= AIC_FR_ICDC ) -#define __aic0_external_codec() ( REG_AIC0_FR &= ~AIC_FR_ICDC ) - -// -// Define next ops for AC97 compatible -// - -#define AC97_ACSR AIC_ACSR - -#define __ac97_enable() __aic_enable(); __aic_select_ac97() -#define __ac97_disable() __aic_disable() -#define __ac97_reset() __aic_reset() - -#define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n) -#define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n) - -#define __ac97_enable_record() __aic_enable_record() -#define __ac97_disable_record() __aic_disable_record() -#define __ac97_enable_replay() __aic_enable_replay() -#define __ac97_disable_replay() __aic_disable_replay() -#define __ac97_enable_loopback() __aic_enable_loopback() -#define __ac97_disable_loopback() __aic_disable_loopback() - -#define __ac97_enable_transmit_dma() __aic_enable_transmit_dma() -#define __ac97_disable_transmit_dma() __aic_disable_transmit_dma() -#define __ac97_enable_receive_dma() __aic_enable_receive_dma() -#define __ac97_disable_receive_dma() __aic_disable_receive_dma() - -#define __ac97_transmit_request() __aic_transmit_request() -#define __ac97_receive_request() __aic_receive_request() -#define __ac97_transmit_underrun() __aic_transmit_underrun() -#define __ac97_receive_overrun() __aic_receive_overrun() - -#define __ac97_clear_errors() __aic_clear_errors() - -#define __ac97_get_transmit_resident() __aic_get_transmit_resident() -#define __ac97_get_receive_count() __aic_get_receive_count() - -#define __ac97_enable_transmit_intr() __aic_enable_transmit_intr() -#define __ac97_disable_transmit_intr() __aic_disable_transmit_intr() -#define __ac97_enable_receive_intr() __aic_enable_receive_intr() -#define __ac97_disable_receive_intr() __aic_disable_receive_intr() - -#define __ac97_write_tfifo(v) __aic_write_tfifo(v) -#define __ac97_read_rfifo() __aic_read_rfifo() - -// -// Define next ops for I2S compatible -// - -#define I2S_ACSR AIC_I2SSR - -#define __i2s_enable() __aic_enable(); __aic_select_i2s() -#define __i2s_disable() __aic_disable() -#define __i2s_reset() __aic_reset() - -#define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n) -#define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n) - -#define __i2s_enable_record() __aic_enable_record() -#define __i2s_disable_record() __aic_disable_record() -#define __i2s_enable_replay() __aic_enable_replay() -#define __i2s_disable_replay() __aic_disable_replay() -#define __i2s_enable_loopback() __aic_enable_loopback() -#define __i2s_disable_loopback() __aic_disable_loopback() - -#define __i2s_enable_transmit_dma() __aic_enable_transmit_dma() -#define __i2s_disable_transmit_dma() __aic_disable_transmit_dma() -#define __i2s_enable_receive_dma() __aic_enable_receive_dma() -#define __i2s_disable_receive_dma() __aic_disable_receive_dma() - -#define __i2s_transmit_request() __aic_transmit_request() -#define __i2s_receive_request() __aic_receive_request() -#define __i2s_transmit_underrun() __aic_transmit_underrun() -#define __i2s_receive_overrun() __aic_receive_overrun() - -#define __i2s_clear_errors() __aic_clear_errors() - -#define __i2s_get_transmit_resident() __aic_get_transmit_resident() -#define __i2s_get_receive_count() __aic_get_receive_count() - -#define __i2s_enable_transmit_intr() __aic_enable_transmit_intr() -#define __i2s_disable_transmit_intr() __aic_disable_transmit_intr() -#define __i2s_enable_receive_intr() __aic_enable_receive_intr() -#define __i2s_disable_receive_intr() __aic_disable_receive_intr() - -#define __i2s_write_tfifo(v) __aic_write_tfifo(v) -#define __i2s_read_rfifo() __aic_read_rfifo() - -#define __i2s_reset_codec() \ - do { \ - } while (0) - - -/************************************************************************* - * SPDIF INTERFACE in AIC Controller - *************************************************************************/ - -#define __spdif_enable() ( REG_SPDIF_ENA |= SPDIF_ENA_SPEN ) -#define __spdif_disable() ( REG_SPDIF_ENA &= ~SPDIF_ENA_SPEN ) - -#define __spdif_enable_transmit_dma() ( REG_SPDIF_CTRL |= SPDIF_CTRL_DMAEN ) -#define __spdif_disable_transmit_dma() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_DMAEN ) -#define __spdif_enable_dtype() ( REG_SPDIF_CTRL |= SPDIF_CTRL_DTYPE ) -#define __spdif_disable_dtype() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_DTYPE ) -#define __spdif_enable_sign() ( REG_SPDIF_CTRL |= SPDIF_CTRL_SIGN ) -#define __spdif_disable_sign() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_SIGN ) -#define __spdif_enable_invalid() ( REG_SPDIF_CTRL |= SPDIF_CTRL_INVALID ) -#define __spdif_disable_invalid() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_INVALID ) -#define __spdif_enable_reset() ( REG_SPDIF_CTRL |= SPDIF_CTRL_RST ) -#define __spdif_select_spdif() ( REG_SPDIF_CTRL |= SPDIF_CTRL_SPDIFI2S ) -#define __spdif_select_i2s() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_SPDIFI2S ) -#define __spdif_enable_MTRIGmask() ( REG_SPDIF_CTRL |= SPDIF_CTRL_MTRIG ) -#define __spdif_disable_MTRIGmask() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_MTRIG ) -#define __spdif_enable_MFFURmask() ( REG_SPDIF_CTRL |= SPDIF_CTRL_MFFUR ) -#define __spdif_disable_MFFURmask() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_MFFUR ) - -#define __spdif_enable_initlvl_high() ( REG_SPDIF_CFG1 |= SPDIF_CFG1_INITLVL ) -#define __spdif_enable_initlvl_low() ( REG_SPDIF_CFG1 &= ~SPDIF_CFG1_INITLVL ) -#define __spdif_enable_zrovld_invald() ( REG_SPDIF_CFG1 |= SPDIF_CFG1_ZROVLD ) -#define __spdif_enable_zrovld_vald() ( REG_SPDIF_CFG1 &= ~SPDIF_CFG1_ZROVLD ) - -/* 0, 1, 2, 3 */ -#define __spdif_set_transmit_trigger(n) \ -do { \ - REG_SPDIF_CFG1 &= ~SPDIF_CFG1_TRIG_MASK; \ - REG_SPDIF_CFG1 |= SPDIF_CFG1_TRIG(n); \ -} while(0) - -/* 1 ~ 15 */ -#define __spdif_set_srcnum(n) \ -do { \ - REG_SPDIF_CFG1 &= ~SPDIF_CFG1_SRCNUM_MASK; \ - REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_SRCNUM_LSB); \ -} while(0) - -/* 1 ~ 15 */ -#define __spdif_set_ch1num(n) \ -do { \ - REG_SPDIF_CFG1 &= ~SPDIF_CFG1_CH1NUM_MASK; \ - REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH1NUM_LSB); \ -} while(0) - -/* 1 ~ 15 */ -#define __spdif_set_ch2num(n) \ -do { \ - REG_SPDIF_CFG1 &= ~SPDIF_CFG1_CH2NUM_MASK; \ - REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH2NUM_LSB); \ -} while(0) - -/* 0x0, 0x2, 0x3, 0xa, 0xe */ -#define __spdif_set_fs(n) \ -do { \ - REG_SPDIF_CFG2 &= ~SPDIF_CFG2_FS_MASK; \ - REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_FS_LSB); \ -} while(0) - -/* 0xd, 0xc, 0x5, 0x1 */ -#define __spdif_set_orgfrq(n) \ -do { \ - REG_SPDIF_CFG2 &= ~SPDIF_CFG2_ORGFRQ_MASK; \ - REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_ORGFRQ_LSB); \ -} while(0) - -/* 0x1, 0x6, 0x2, 0x4, 0x5 */ -#define __spdif_set_samwl(n) \ -do { \ - REG_SPDIF_CFG2 &= ~SPDIF_CFG2_SAMWL_MASK; \ - REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_SAMWL_LSB); \ -} while(0) - -#define __spdif_enable_samwl_24() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_MAXWL ) -#define __spdif_enable_samwl_20() ( REG_SPDIF_CFG1 &= ~SPDIF_CFG2_MAXWL ) - -/* 0x1, 0x1, 0x2, 0x3 */ -#define __spdif_set_clkacu(n) \ -do { \ - REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CLKACU_MASK; \ - REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CLKACU_LSB); \ -} while(0) - -/* see IEC60958-3 */ -#define __spdif_set_catcode(n) \ -do { \ - REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CATCODE_MASK; \ - REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CATCODE_LSB); \ -} while(0) - -/* n = 0x0, */ -#define __spdif_set_chmode(n) \ -do { \ - REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CHMD_MASK; \ - REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CHMD_LSB); \ -} while(0) - -#define __spdif_enable_pre() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_PRE ) -#define __spdif_disable_pre() ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_PRE ) -#define __spdif_enable_copyn() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_COPYN ) -#define __spdif_disable_copyn() ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_COPYN ) -/* audio sample word represents linear PCM samples */ -#define __spdif_enable_audion() ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_AUDION ) -/* udio sample word used for other purpose */ -#define __spdif_disable_audion() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_AUDION ) -#define __spdif_enable_conpro() ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CONPRO ) -#define __spdif_disable_conpro() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_CONPRO ) - -/*************************************************************************** - * ICDC - ***************************************************************************/ -#define __i2s_internal_codec() __aic_internal_codec() -#define __i2s_external_codec() __aic_external_codec() - -#define __icdc_clk_ready() ( REG_ICDC_CKCFG & ICDC_CKCFG_CKRDY ) -#define __icdc_sel_adc() ( REG_ICDC_CKCFG |= ICDC_CKCFG_SELAD ) -#define __icdc_sel_dac() ( REG_ICDC_CKCFG &= ~ICDC_CKCFG_SELAD ) - -#define __icdc_set_rgwr() ( REG_ICDC_RGADW |= ICDC_RGADW_RGWR ) -#define __icdc_clear_rgwr() ( REG_ICDC_RGADW &= ~ICDC_RGADW_RGWR ) -#define __icdc_rgwr_ready() ( REG_ICDC_RGADW & ICDC_RGADW_RGWR ) - -#define AIC_RW_CODEC_START() while (INREG32(ICDC_RGADW) & ICDC_RGADW_RGWR) -#define AIC_RW_CODEC_STOP() while (INREG32(ICDC_RGADW) & ICDC_RGADW_RGWR) - - -#define __icdc_set_addr(n) \ -do { \ - REG_ICDC_RGADW &= ~ICDC_RGADW_RGADDR_MASK; \ - REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGADDR_LSB; \ -} while(0) - -#define __icdc_set_cmd(n) \ -do { \ - REG_ICDC_RGADW &= ~ICDC_RGADW_RGDIN_MASK; \ - REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGDIN_LSB; \ -} while(0) - -#define __icdc_irq_pending() ( REG_ICDC_RGDATA & ICDC_RGDATA_IRQ ) -#define __icdc_get_value() ( REG_ICDC_RGDATA & ICDC_RGDATA_RGDOUT_MASK ) - - - -#endif /* __MIPS_ASSEMBLER */ - -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* _X1000_AIC_H_ */ diff --git a/libcpu/mips/x1000/x1000_cpm.h b/libcpu/mips/x1000/x1000_cpm.h deleted file mode 100644 index da2cc964e5..0000000000 --- a/libcpu/mips/x1000/x1000_cpm.h +++ /dev/null @@ -1,511 +0,0 @@ -/* - * File : x1000_cpm.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2017-02-03 Urey the first version - */ - -#ifndef _X1000_CPM_H_ -#define _X1000_CPM_H_ - -#define CPM_CPCCR (0x00) -#define CPM_CPCSR (0xd4) - -#define CPM_DDRCDR (0x2c) -#define CPM_I2SCDR (0x60) -#define CPM_I2SCDR1 (0x70) -#define CPM_LPCDR (0x64) -#define CPM_MSC0CDR (0x68) -#define CPM_MSC1CDR (0xa4) -#define CPM_USBCDR (0x50) -#define CPM_MACCDR (0x54) -#define CPM_UHCCDR (0x6c) -#define CPM_SFCCDR (0x74) -#define CPM_CIMCDR (0x7c) -#define CPM_PCMCDR (0x84) -#define CPM_PCMCDR1 (0xe0) -#define CPM_MPHYC (0xe8) - -#define CPM_INTR (0xb0) -#define CPM_INTRE (0xb4) -#define CPM_DRCG (0xd0) -#define CPM_CPSPPR (0x38) -#define CPM_CPPSR (0x34) - -#define CPM_USBPCR (0x3c) -#define CPM_USBRDT (0x40) -#define CPM_USBVBFIL (0x44) -#define CPM_USBPCR1 (0x48) - -#define CPM_CPAPCR (0x10) -#define CPM_CPMPCR (0x14) - -#define CPM_LCR (0x04) -#define CPM_PSWC0ST (0x90) -#define CPM_PSWC1ST (0x94) -#define CPM_PSWC2ST (0x98) -#define CPM_PSWC3ST (0x9c) -#define CPM_CLKGR (0x20) -#define CPM_CLKGR0 (0x20) -#define CPM_MESTSEL (0xec) -#define CPM_SRBC (0xc4) -#define CPM_ERNG (0xd8) -#define CPM_RNG (0xdc) -#define CPM_SLBC (0xc8) -#define CPM_SLPC (0xcc) -#define CPM_OPCR (0x24) -#define CPM_RSR (0x08) - - - - -/* - * CPM registers common define - */ - -/* Clock control register(CPCCR) */ -#define CPCCR_SEL_SRC_LSB 30 -#define CPCCR_SEL_SRC_MASK BITS_H2L(31, CPCCR_SEL_SRC_LSB) - -#define CPCCR_SEL_CPLL_LSB 28 -#define CPCCR_SEL_CPLL_MASK BITS_H2L(29, CPCCR_SEL_CPLL_LSB) - -#define CPCCR_SEL_H0PLL_LSB 26 -#define CPCCR_SEL_H0PLL_MASK BITS_H2L(27, CPCCR_SEL_H0PLL_LSB) - -#define CPCCR_SEL_H2PLL_LSB 24 -#define CPCCR_SEL_H2PLL_MASK BITS_H2L(25, CPCCR_SEL_H2PLL_LSB) - -#define CPCCR_CE_CPU BIT22 -#define CPCCR_CE_AHB0 BIT21 -#define CPCCR_CE_AHB2 BIT20 -#define CPCCR_CE (CPCCR_CE_CPU | CPCCR_CE_AHB0 | CPCCR_CE_AHB2) - -#define CPCCR_PDIV_LSB 16 -#define CPCCR_PDIV_MASK BITS_H2L(19, CPCCR_PDIV_LSB) - -#define CPCCR_H2DIV_LSB 12 -#define CPCCR_H2DIV_MASK BITS_H2L(15, CPCCR_H2DIV_LSB) - -#define CPCCR_H0DIV_LSB 8 -#define CPCCR_H0DIV_MASK BITS_H2L(11, CPCCR_H0DIV_LSB) - -#define CPCCR_L2DIV_LSB 4 -#define CPCCR_L2DIV_MASK BITS_H2L(7, CPCCR_L2DIV_LSB) - -#define CPCCR_CDIV_LSB 0 -#define CPCCR_CDIV_MASK BITS_H2L(3, CPCCR_CDIV_LSB) - -#define CPM_SRC_SEL_APLL 1 -#define CPM_PLL_SEL_SRC 1 -#define CPM_PLL_SEL_MPLL 2 - -/* Clock Status register(CPCSR) */ -#define CPCSR_SRC_MUX BIT31 -#define CPCSR_CPU_MUX BIT30 -#define CPCSR_AHB0_MUX BIT29 -#define CPCSR_AHB2_MUX BIT28 -#define CPCSR_DDR_MUX BIT27 -#define CPCSR_H2DIV_BUSY BIT2 -#define CPCSR_H0DIV_BUSY BIT1 -#define CPCSR_CDIV_BUSY BIT0 -#define CPCSR_DIV_BUSY (CPCSR_H2DIV_BUSY | CPCSR_H0DIV_BUSY | CPCSR_CDIV_BUSY) - -/* DDR clock divider register(DDCDR) */ -#define DDCDR_DCS_LSB 30 -#define DDCDR_DCS_MASK BITS_H2L(31, DDCDR_DCS_LSB) -#define DDCDR_DCS_STOP (0 << DDCDR_DCS_LSB) -#define DDCDR_DCS_APLL (1 << DDCDR_DCS_LSB) -#define DDCDR_DCS_MPLL (2 << DDCDR_DCS_LSB) -#define DDCDR_CE_DDR BIT29 -#define DDCDR_DDR_BUSY BIT28 -#define DDCDR_DDR_STOP BIT27 -#define DDCDR_GATE_EN BIT26 -#define DDCDR_DDR_CHANGE_EN BIT25 -#define DDCDR_DDR BIT24 -#define DDCDR_DDRDIV_LSB 0 -#define DDCDR_DDRDIV_MASK BITS_H2L(3, DDCDR_DDRDIV_LSB) - -/*MACPHY clock divider Register (MACCDR)*/ -#define MACCDR_MACPCS BIT31 -#define MACCDR_CE_MAC BIT29 -#define MACCDR_MAC_BUSY BIT28 -#define MACCDR_MAC_STOP BIT27 -#define MACCDR_MACCDR_LSB BIT0 -#define MACCDR_MACCDR_MASK BITS_H2L(7,MACCDR_MACCDR_LSB) - -/* I2S device clock divider register(I2SCDR) */ -#define I2SCDR_I2PCS BIT31 -#define I2SCDR_I2CS BIT30 - -#define I2SCDR_I2SDIV_M_LSB 13 -#define I2SCDR_I2SDIV_M_MASK BITS_H2L(21,I2SCDR_I2SDIV_M_LSB) -#define I2SCDR_I2SDIV_N_LSB 0 /* I2SCDR bit */ -#define I2SCDR_I2SDIV_N_MASK BITS_H2L(7, I2SCDR_I2SDIV_N_LSB) - - -/* I2S device clock divider register(I2SCDR1) */ -#define I2SCDR1_NEN BIT31 -#define I2SCDR1_DEN BIT30 -#define I2SCDR1_I2SDIV_D_LSB 0 -#define I2SCDR1_I2SDIV_D_MASK BITS_H2L(12,I2SCDR1_I2SDIV_D_LSB) - -/* LCD pix clock divider register(LPCDR) */ -#define LPCDR_LPCS_LSB 31 -#define LPCDR_LPCS_APLL (0 << LPCDR_LPCS_LSB) -#define LPCDR_LPCS_MPLL (1 << LPCDR_LPCS_LSB) -#define LPCDR_CE_LCD BIT28 -#define LPCDR_LCD_BUSY BIT27 -#define LPCDR_LCD_STOP BIT26 - -#define LPCDR_PIXDIV_LSB 0 /* LPCDR bit */ -#define LPCDR_PIXDIV_MASK BITS_H2L(7, LPCDR_PIXDIV_LSB) - -/* MSC clock divider register(MSCCDR) */ -#define MSCCDR_MPCS_LSB 31 /* MPCS bit */ -#define MSCCDR_MPCS_APLL (0 << MSCCDR_MPCS_LSB) -#define MSCCDR_MPCS_MPLL (1 << MSCCDR_MPCS_LSB) - -#define MSCCDR_CE_MSC BIT29 -#define MSCCDR_MSC_BUSY BIT28 -#define MSCCDR_MSC_STOP BIT27 -#define MSCCDR_S_CLK0_SEL BIT15 - -#define MSCCDR_MSCDIV_LSB 0 /* MSCCDR bit */ -#define MSCCDR_MSCDIV_MASK BITS_H2L(7, MSCCDR_MSCDIV_LSB) - - -/* OTG PHY clock divider register(USBCDR) */ -#define USBCDR_UCS BIT31 -#define USBCDR_UPCS BIT30 -#define USBCDR_CE_USB BIT29 -#define USBCDR_USB_BUSY BIT28 -#define USBCDR_USB_STOP BIT27 - -#define USBCDR_OTGDIV_LSB 0 /* USBCDR bit */ -#define USBCDR_OTGDIV_MASK BITS_H2L(7, USBCDR_OTGDIV_LSB) - -/* SSI clock divider register(SSICDR) */ -#define SSICDR_SPCS BIT31 -#define SSICDR_SCS BIT30 -#define SSICDR_CE_SSI BIT29 -#define SSICDR_SSI_BUSY BIT28 -#define SSICDR_SSI_STOP BIT27 -#define SSICDR_SSIDIV_LSB 0 /* SSICDR bit */ -#define SSICDR_SSIDIV_MASK BITS_H2L(7, SSICDR_SSIDIV_LSB) - -/* CIM mclk clock divider register(CIMCDR) */ -#define CIMCDR_CIMPCS_APLL (0 << 31) -#define CIMCDR_CIMPCS_MPLL BIT31 -#define CIMCDR_CE_CIM BIT29 -#define CIMCDR_CIM_BUSY BIT28 -#define CIMCDR_CIM_STOP BIT27 - -#define CIMCDR_CIMDIV_LSB 0 /* CIMCDR bit */ -#define CIMCDR_CIMDIV_MASK BITS_H2L(7, CIMCDR_CIMDIV_LSB) - - -/* PCM device clock divider register(PCMCDR) */ -#define PCMCDR_PCMPCS_LSB 30 -#define PCMCDR_PCMPCS_MASK BITS_H2L(31,PCMCDR_PCMPCS_LSB) -#define PCMCDR_PCMPCS_SCLK_A 0 << PCMCDR_PCMPCS_LSB -#define PCMCDR_PCMPCS_EXTCLK 1 << PCMCDR_PCMPCS_LSB -#define PCMCDR_PCMPCS_MPLL 2 << PCMCDR_PCMPCS_LSB -#define PCMCDR_CE_PCM BIT29 -#define PCMCDR_PCMDIV_M_LSB 13 -#define PCMCDR_PCMDIV_M_MASK BITS_H2L(21,PCMCDR_PCMDIV_M_LSB) -#define PCMCDR_PCMDIV_N_LSB 0 -#define PCMCDR_PCMDIV_N_MASK BITS_H2L(12,PCMCDR_PCMDIV_N_LSB) - -/* PCM device clock divider register(PCMCDR1) */ - -#define PCMCDR1_PCM_NEN BIT31 -#define PCMCDR1_PCM_DEN BIT30 -#define PCMCDR1_PCMDIV_D_LSB 0 -#define PCMCDR1_PCMDIV_D_MASK BITS_H2L(12,PCMCDR1_PCMDIV_D_LSB) - -/* MAC PHY Control Register (MPHYC) */ -#define MPHYC_MODE_SEL BIT31 //useless now -#define MPHYC_MAC_SPEED_LSB 29 -#define MPHYC_MAC_SPEED_MASK BITS_H2L(30,MPHYC_MAC_SPEED_LSB) -#define MPHYC_SOFT_RST BIT3 -#define MPHYC_PHY_INTF_LSB 0 -#define MPHYC_PHY_INTF_MASK BITS_H2L(2,MPHYC_PHY_INTF_MASK) //useless now - -/* CPM Interrupt Register (CPM_INTR)*/ -#define CPM_INTR_VBUS_INTR BIT1 -#define CPM_INTR_ADEV_INTR BIT0 - -/* CPM Interrupt Enable Register (CPM_INTRE)*/ -#define CPM_INTRE_VBUS_INTRE BIT1 -#define CPM_INTRE_ADEV_INTRE BIT0 - -/* CPM scratch pad protected register(CPSPPR) */ -#define CPSPPR_CPSPR_WRITABLE (0x00005a5a) - -/* OTG parameter control register(USBPCR) */ -#define USBPCR_USB_MODE BIT31 -#define USBPCR_AVLD_REG BIT30 -#define USBPCR_INCRM BIT27 /* INCR_MASK bit */ -#define USBPCR_TXRISE_TUNE BIT26 -#define USBPCR_COMMONONN BIT25 -#define USBPCR_VBUSVLDEXT BIT24 -#define USBPCR_VBUSVLDEXTSEL BIT23 -#define USBPCR_POR BIT22 -#define USBPCR_SIDDQ BIT21 -#define USBPCR_OTG_DISABLE BIT20 -#define USBPCR_TXPREEMPHTUNE BIT6 - -#define USBPCR_IDPULLUP_LSB 28 /* IDPULLUP_MASK bit */ -#define USBPCR_IDPULLUP_MASK BITS_H2L(29, USBPCR_IDPULLUP_LSB) - -#define USBPCR_COMPDISTUNE_LSB 17 -#define USBPCR_COMPDISTUNE_MASK BITS_H2L(19, USBPCR_COMPDISTUNE_LSB) - -#define USBPCR_OTGTUNE_LSB 14 -#define USBPCR_OTGTUNE_MASK BITS_H2L(16, USBPCR_OTGTUNE_LSB) - -#define USBPCR_SQRXTUNE_LSB 11 -#define USBPCR_SQRXTUNE_MASK BITS_H2L(13, USBPCR_SQRXTUNE_LSB) - -#define USBPCR_TXFSLSTUNE_LSB 7 -#define USBPCR_TXFSLSTUNE_MASK BITS_H2L(10, USBPCR_TXFSLSTUNE_LSB) - -#define USBPCR_TXRISETUNE_LSB 4 -#define USBPCR_TXRISETUNE_MASK BITS_H2L(5, USBPCR_TXRISETUNE_LSB) - -#define USBPCR_TXVREFTUNE_LSB 0 -#define USBPCR_TXVREFTUNE_MASK BITS_H2L(3, USBPCR_TXVREFTUNE_LSB) - -/* OTG reset detect timer register(USBRDT) */ -#define USBRDT_HB_MASK BIT26 -#define USBRDT_VBFIL_LD_EN BIT25 -#define USBRDT_IDDIG_EN BIT24 -#define USBRDT_IDDIG_REG BIT23 - -#define USBRDT_USBRDT_LSB 0 -#define USBRDT_USBRDT_MASK BITS_H2L(22, USBRDT_USBRDT_LSB) - -/* OTG parameter control register(USBPCR1) */ -#define USBPCR1_REG BIT31 -#define USBPCR1_USB_SEL BIT28 -#define USBPCR1_REFCLKSEL_LSB 26 -#define USBPCR1_REFCLKSEL_MASK BITS_H2L(27, USBPCR1_REFCLKSEL_LSB) - -#define USBPCR1_REFCLKDIV_LSB 24 -#define USBPCR1_REFCLKDIV_MASK BITS_H2L(25, USBPCR1_REFCLKDIV_LSB) - -#define USBPCR1_PORT_RST BIT21 - -#define USBPCR1_WORD_IF0 BIT19 -#define USBPCR1_WORD_IF1 BIT18 - - -/* APLL control register (CPXPCR) */ -#define CPAPCR_BS BIT31 -#define CPAPCR_M_LSB 24 -#define CPAPCR_M_MASK BITS_H2L(30, CPAPCR_M_LSB) - -#define CPAPCR_N_LSB 18 -#define CPAPCR_N_MASK BITS_H2L(22, CPAPCR_N_LSB) - -#define CPAPCR_OD_LSB 16 -#define CPAPCR_OD_MASK BITS_H2L(17, CPAPCR_OD_LSB) - -#define CPAPCR_LOCK BIT15 /* LOCK bit */ -#define CPAPCR_ON BIT10 -#define CPAPCR_BP BIT9 -#define CPAPCR_EN BIT8 -#define CPAPCR_PLLST_LSB 0 -#define CPAPCR_PLLST_MASK BITS_H2L(7,CPAPCR_PLLST_LSB) - -#define CPM_CPAPCR_EN CPAPCR_EN -#define CPM_CPAPCR_ON CPAPCR_ON - -/* MPLL control register (CPXPCR) */ -#define CPMPCR_BS BIT31 -#define CPMPCR_M_LSB 24 -#define CPMPCR_M_MASK BITS_H2L(30, CPAPCR_M_LSB) - -#define CPMPCR_N_LSB 18 -#define CPMPCR_N_MASK BITS_H2L(22, CPAPCR_N_LSB) - -#define CPMPCR_OD_LSB 16 -#define CPMPCR_OD_MASK BITS_H2L(17, CPAPCR_OD_LSB) - -#define CPMPCR_EN BIT7 -#define CPMPCR_BP BIT6 -#define CPMPCR_LOCK BIT1 /* LOCK bit */ -#define CPMPCR_ON BIT0 - -#define CPM_CPMPCR_EN CPMPCR_EN -#define CPM_CPMPCR_ON CPMPCR_ON - - - -/* Low power control register(LCR) */ -#define LCR_PST_LSB 8 -#define LCD_PST_MASK BITS_H2L(19,LCR_PST_LSB) -#define LCR_LPM_LSB 0 -#define LCR_LPM_MASK BITS_H2L(1,LCR_LPM_LSB) - -/* Clock gate register 0(CGR0) */ -#define CLKGR0_DDR BIT31 -#define CLKGR0_CPU BIT30 -#define CLKGR0_AHB0 BIT29 -#define CLKGR0_APB0 BIT28 -#define CLKGR0_RTC BIT27 -#define CLKGR0_PCM BIT26 -#define CLKGR0_MAC BIT25 -#define CLKGR0_AES BIT24 -#define CLKGR0_LCD BIT23 -#define CLKGR0_CIM BIT22 -#define CLKGR0_PDMA BIT21 -#define CLKGR0_OST BIT20 -#define CLKGR0_SSI BIT19 -#define CLKGR0_TCU BIT18 -#define CLKGR0_DMIC BIT17 -#define CLKGR0_UART2 BIT16 -#define CLKGR0_UART1 BIT15 -#define CLKGR0_UART0 BIT14 -#define CLKGR0_SADC BIT13 -#define CLKGR0_JPEG BIT12 -#define CLKGR0_AIC BIT11 -#define CLKGR0_I2C3 BIT10 -#define CLKGR0_I2C2 BIT9 -#define CLKGR0_I2C1 BIT8 -#define CLKGR0_I2C0 BIT7 -#define CLKGR0_SCC BIT6 -#define CLKGR0_MSC1 BIT5 -#define CLKGR0_MSC0 BIT4 -#define CLKGR0_OTG BIT3 -#define CLKGR0_SFC BIT2 -#define CLKGR0_EFUSE BIT1 -#define CLKGR0_NEMC BIT0 - -/* CPM MEST SEL Register */ - -#define MEST_SEL_TST8 BIT8 -#define MEST_SEL_TST7 BIT7 -#define MEST_SEL_TST4 BIT4 -#define MEST_SEL_TST3 BIT3 -#define MEST_SEL_TST1 BIT1 -#define MEST_SEL_TST0 BIT0 - -/*Soft Reset and Bus Control Register (SRBC)*/ - -#define SRBC_JPEG_SR BIT31 -#define SRBC_JPEG_STP BIT30 -#define SRBC_JPEG_ACK BIT29 -#define SRBC_LCD_SR BIT25 -#define SRBC_LCD_STP BIT24 -#define SRBC_LCD_ACK BIT23 -#define SRBC_CIM_STP BIT21 -#define SRBC_CIM_ACK BIT20 -#define SRBC_CPU_STP BIT15 -#define SRBC_CPU_ACK BIT14 -#define SRBC_OTG_SR BIT12 -#define SRBC_AHB2_STP BIT8 -#define SRBC_AHB2_ACK BIT7 -#define SRBC_DDR_STP BIT6 -#define SRBC_DDR_ACK BIT5 - - -/* Oscillator and power control register(OPCR) */ -#define OPCR_IDLE_DIS BIT31 -#define OPCR_MASK_INT BIT30 -#define OPCR_MASK_VPU BIT29 //ONLY FOR DEBUG -#define OPCR_GATE_SCLK_ABUS BIT28 -#define OPCR_L2C_PD BIT25 -#define OPCR_REQ_MODE BIT24 -#define OPCR_GATE_USBPHY_CLK BIT23 -#define OPCR_DIS_STOP_MUX BIT22 -#define OPCR_O1ST_LSB 8 -#define OPCR_O1ST_MASK BITS_H2L(19, OPCR_O1ST_LSB) -#define OPCR_OTGPHY0_ENABLE BIT7 /* otg */ -#define OPCR_OTGPHY1_ENABLE BIT6 /* uhc */ -#define OPCR_USBPHY_ENABLE (OPCR_OTGPHY0_ENABLE | OPCR_OTGPHY1_ENABLE) -#define OPCR_O1SE BIT4 -#define OPCR_PD BIT3 -#define OPCR_ERCS BIT2 -#define OPCR_BUSMODE BIT1 - - - -/* Reset status register(RSR) */ -#define RSR_HR BIT3 -#define RSR_P0R BIT2 -#define RSR_WR BIT1 -#define RSR_PR BIT0 - - -#ifndef __ASSEMBLY__ - -#define REG_CPM_CPCCR REG32(CPM_BASE + CPM_CPCCR) -#define REG_CPM_CPCSR REG32(CPM_BASE + CPM_CPCSR) -#define REG_CPM_DDCDR REG32(CPM_BASE + CPM_DDCDR) -#define REG_CPM_MACCDR REG32(CPM_BASE + CPM_MACCDR) -#define REG_CPM_I2SCDR REG32(CPM_BASE + CPM_I2SCDR) -#define REG_CPM_I2SCDR1 REG32(CPM_BASE + CPM_I2SCDR1) -#define REG_CPM_LPCDR REG32(CPM_BASE + CPM_LPCDR) -#define REG_CPM_MSC0CDR REG32(CPM_BASE + CPM_MSC0CDR) -#define REG_CPM_MSC1CDR REG32(CPM_BASE + CPM_MSC1CDR) -#define REG_CPM_USBCDR REG32(CPM_BASE + CPM_USBCDR) -#define REG_CPM_SSICDR REG32(CPM_BASE + CPM_SSICDR) -#define REG_CPM_CIMCDR REG32(CPM_BASE + CPM_CIMCDR) -#define REG_CPM_PCMCDR REG32(CPM_BASE + CPM_PCMCDR) -#define REG_CPM_PCMCDR1 REG32(CPM_BASE + CPM_PCMCDR1) -#define REG_CPM_MPHYC REG32(CPM_BASE + CPM_MPHYC) -#define REG_CPM_INTRCDR REG32(CPM_BASE + CPM_INTRCDR) -#define REG_CPM_INTRECDR REG32(CPM_BASE + CPM_INTRECDR) -#define REG_CPM_CPSPR REG32(CPM_BASE + CPM_CPSPR) -#define REG_CPM_CPSPPR REG32(CPM_BASE + CPM_CPSPPR) -#define REG_CPM_USBPCR REG32(CPM_BASE + CPM_USBPCR) -#define REG_CPM_USBRDT REG32(CPM_BASE + CPM_USBRDT) -#define REG_CPM_USBVBFIL REG32(CPM_BASE + CPM_USBVBFIL) -#define REG_CPM_USBPCR1 REG32(CPM_BASE + CPM_USBPCR1) -#define REG_CPM_CPAPCR REG32(CPM_BASE + CPM_CPAPCR) -#define REG_CPM_CPMPCR REG32(CPM_BASE + CPM_CPMPCR) - -#define REG_CPM_LCR REG32(CPM_BASE + CPM_LCR) -#define REG_CPM_PSWC0ST REG32(CPM_BASE + CPM_PSWC0ST) -#define REG_CPM_PSWC1ST REG32(CPM_BASE + CPM_PSWC1ST) -#define REG_CPM_PSWC2ST REG32(CPM_BASE + CPM_PSWC2ST) -#define REG_CPM_PSWC3ST REG32(CPM_BASE + CPM_PSWC3ST) -#define REG_CPM_CLKGR0 REG32(CPM_BASE + CPM_CLKGR0) -#define REG_CPM_SRBC REG32(CPM_BASE + CPM_SRBC) -#define REG_CPM_SLBC REG32(CPM_BASE + CPM_SLBC) -#define REG_CPM_SLPC REG32(CPM_BASE + CPM_SLPC) -#define REG_CPM_OPCR REG32(CPM_BASE + CPM_OPCR) -#define REG_CPM_RSR REG32(CPM_BASE + CPM_RSR) - -#define _REG_CPM_MSCCDR(n) REG_CPM_MSC##n##CDR -#define REG_CPM_MSCCDR(n) _REG_CPM_MSCCDR(n) - -/* CPM read write */ -#define cpm_inl(off) readl(CPM_BASE + off) -#define cpm_outl(val,off) writel(val, CPM_BASE + off) -#define cpm_test_bit(bit,off) (cpm_inl(off) & 0x1<<(bit)) -#define cpm_set_bit(bit,off) (cpm_outl((cpm_inl(off) | 0x1<<(bit)),off)) -#define cpm_clear_bit(bit,off) (cpm_outl(cpm_inl(off) & ~(0x1 << bit), off)) - -#endif /* __ASSEMBLY__ */ - -#endif /* _X1000_CPM_H_ */ diff --git a/libcpu/mips/x1000/x1000_intc.h b/libcpu/mips/x1000/x1000_intc.h deleted file mode 100644 index 1644b90777..0000000000 --- a/libcpu/mips/x1000/x1000_intc.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * File : x1000_intc.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2017-02-03 Urey the first version - */ - -#ifndef _X1000_INTC_H_ -#define _X1000_INTC_H_ - - -/* - * INTC (Interrupt Controller) - */ -#define INTC_ISR(n) (INTC_BASE + 0x00 + (n) * 0x20) -#define INTC_IMR(n) (INTC_BASE + 0x04 + (n) * 0x20) -#define INTC_IMSR(n) (INTC_BASE + 0x08 + (n) * 0x20) -#define INTC_IMCR(n) (INTC_BASE + 0x0c + (n) * 0x20) -#define INTC_IPR(n) (INTC_BASE + 0x10 + (n) * 0x20) - -#define REG_INTC_ISR(n) REG32(INTC_ISR((n))) -#define REG_INTC_IMR(n) REG32(INTC_IMR((n))) -#define REG_INTC_IMSR(n) REG32(INTC_IMSR((n))) -#define REG_INTC_IMCR(n) REG32(INTC_IMCR((n))) -#define REG_INTC_IPR(n) REG32(INTC_IPR((n))) - -// interrupt controller interrupts -#define IRQ_DMIC 0 -#define IRQ_AIC0 1 -#define IRQ_RESERVED2 2 -#define IRQ_RESERVED3 3 -#define IRQ_RESERVED4 4 -#define IRQ_RESERVED5 5 -#define IRQ_RESERVED6 6 -#define IRQ_SFC 7 -#define IRQ_SSI0 8 -#define IRQ_RESERVED9 9 -#define IRQ_PDMA 10 -#define IRQ_PDMAD 11 -#define IRQ_RESERVED12 12 -#define IRQ_RESERVED13 13 -#define IRQ_GPIO3 14 -#define IRQ_GPIO2 15 -#define IRQ_GPIO1 16 -#define IRQ_GPIO0 17 -#define IRQ_RESERVED18 18 -#define IRQ_RESERVED19 19 -#define IRQ_RESERVED20 20 -#define IRQ_OTG 21 -#define IRQ_RESERVED22 22 -#define IRQ_AES 23 -#define IRQ_RESERVED24 24 -#define IRQ_TCU2 25 -#define IRQ_TCU1 26 -#define IRQ_TCU0 27 -#define IRQ_RESERVED28 28 -#define IRQ_RESERVED29 29 -#define IRQ_CIM 30 -#define IRQ_LCD 31 -#define IRQ_RTC 32 -#define IRQ_RESERVED33 33 -#define IRQ_RESERVED34 34 -#define IRQ_RESERVED35 35 -#define IRQ_MSC1 36 -#define IRQ_MSC0 37 -#define IRQ_SCC 38 -#define IRQ_RESERVED39 39 -#define IRQ_PCM0 40 -#define IRQ_RESERVED41 41 -#define IRQ_RESERVED42 42 -#define IRQ_RESERVED43 43 -#define IRQ_HARB2 44 -#define IRQ_RESERVED45 45 -#define IRQ_HARB0 46 -#define IRQ_CPM 47 -#define IRQ_RESERVED48 48 -#define IRQ_UART2 49 -#define IRQ_UART1 50 -#define IRQ_UART0 51 -#define IRQ_DDR 52 -#define IRQ_RESERVED53 53 -#define IRQ_EFUSE 54 -#define IRQ_MAC 55 -#define IRQ_RESERVED56 56 -#define IRQ_RESERVED57 57 -#define IRQ_I2C2 58 -#define IRQ_I2C1 59 -#define IRQ_I2C0 60 -#define IRQ_PDMAM 61 -#define IRQ_JPEG 62 -#define IRQ_RESERVED63 63 - -#define IRQ_INTC_MAX 63 - -#ifndef __ASSEMBLY__ - -#define __intc_unmask_irq(n) (REG_INTC_IMCR((n)/32) = (1 << ((n)%32))) -#define __intc_mask_irq(n) (REG_INTC_IMSR((n)/32) = (1 << ((n)%32))) -#define __intc_ack_irq(n) (REG_INTC_IPR((n)/32) = (1 << ((n)%32))) /* A dummy ack, as the Pending Register is Read Only. Should we remove __intc_ack_irq() */ - -#endif /* !__ASSEMBLY__ */ - -#endif /* _X1000_INTC_H_ */ diff --git a/libcpu/mips/x1000/x1000_otg_dwc.h b/libcpu/mips/x1000/x1000_otg_dwc.h deleted file mode 100644 index bb77981daa..0000000000 --- a/libcpu/mips/x1000/x1000_otg_dwc.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * File : x1000_otg_dwc.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2017-02-03 Urey the first version - */ - -#ifndef _X1000_OTG_DWC_H_ -#define _X1000_OTG_DWC_H_ - -/* Globle Regs define */ -#define GOTG_CTL (OTG_BASE + 0x00) -#define GOTG_INTR (OTG_BASE + 0x04) -#define GAHB_CFG (OTG_BASE + 0x08) -#define GUSB_CFG (OTG_BASE + 0x0c) -#define GRST_CTL (OTG_BASE + 0x10) -#define GINT_STS (OTG_BASE + 0x14) -#define GINT_MASK (OTG_BASE + 0x18) -#define GRXSTS_READ (OTG_BASE + 0x1c) -#define GRXSTS_POP (OTG_BASE + 0x20) -#define GRXFIFO_SIZE (OTG_BASE + 0x24) -#define GNPTXFIFO_SIZE (OTG_BASE + 0x28) -#define GDTXFIFO_SIZE (OTG_BASE + 0x104) -#define GHW_CFG1 (OTG_BASE + 0x44) -#define GHW_CFG2 (OTG_BASE + 0x48) -#define GHW_CFG3 (OTG_BASE + 0x4c) -#define GHW_CFG4 (OTG_BASE + 0x50) -#define GDFIFO_CFG (OTG_BASE + 0x5c) -#define PCGC_CTL (OTG_BASE + 0xe00) - -/* Fifo number 1 ~ 15 */ -#define GDEIP_TXF(n) (OTG_BASE + (0x104 + ((n-1) * 0x4))) - -#define REG_GOTG_CTL REG32(GOTG_CTL) -#define REG_GOTG_INTR REG32(GOTG_INTR) -#define REG_GAHB_CFG REG32(GAHB_CFG) -#define REG_GUSB_CFG REG32(GUSB_CFG) -#define REG_GRST_CTL REG32(GRST_CTL) -#define REG_GINT_STS REG32(GINT_STS) -#define REG_GINT_MASK REG32(GINT_MASK) -#define REG_GRXSTS_READ REG32(GRXSTS_READ) -#define REG_GRXSTS_POP REG32(GRXSTS_POP) -#define REG_GRXFIFO_SIZE REG32(GRXFIFO_SIZE) -#define REG_GNPTXFIFO_SIZE REG32(GNPTXFIFO_SIZE) -#define REG_GDTXFIFO_SIZE REG32(GDTXFIFO_SIZE) -#define REG_GHW_CFG1 REG32(GHW_CFG1) -#define REG_GHW_CFG2 REG32(GHW_CFG2) -#define REG_GHW_CFG3 REG32(GHW_CFG3) -#define REG_GHW_CFG4 REG32(GHW_CFG4) -#define REG_GDFIFO_CFG REG32(GDFIFO_CFG) -#define REG_GDIEP_TXF(n) REG32(GDEIP_TXF(n)) -#define REG_PCGC_CTL REG32(PCGC_CTL) -/* Device Regs define */ -#define EP_FIFO(n) (OTG_BASE + (n+1)*0x1000) // FiX ME -#define REG_EP_FIFO(n) REG32(EP_FIFO(n)) - - -#define OTG_DCFG (OTG_BASE + 0x800) -#define OTG_DCTL (OTG_BASE + 0x804) -#define OTG_DSTS (OTG_BASE + 0x808) -#define DIEP_MASK (OTG_BASE + 0x810) -#define DOEP_MASK (OTG_BASE + 0x814) -#define OTG_DAINT (OTG_BASE + 0x818) -#define DAINT_MASK (OTG_BASE + 0x81c) - -#define DIEP_EMPMSK (OTG_BASE + 0x834) - - -/* It's used in OTG_MULT_PROC_INTRPT = 1 -#define DEACH_INT (OTG_BASE + 0x838) -#define DEACH_INTMASK (OTG_BASE + 0x83c) -#define DIEP0_INTMASK (OTG_BASE + 0x840) -#define DIEP1_INTMASK (OTG_BASE + 0x844) -#define DOEP0_INTMASK (OTG_BASE + 0x880) -#define DOEP1_INTMASK (OTG_BASE + 0x884) -*/ - -#define DIEP_CTL(n) (OTG_BASE + (0x900 + (n)*0x20)) -#define DOEP_CTL(n) (OTG_BASE + (0xb00 + (n)*0x20)) - -#define DIEP_INT(n) (OTG_BASE + (0x908 + (n)*0x20)) -#define DOEP_INT(n) (OTG_BASE + (0xb08 + (n)*0x20)) - -#define DIEP_SIZE(n) (OTG_BASE + (0x910 + (n)*0x20)) -#define DOEP_SIZE(n) (OTG_BASE + (0xb10 + (n)*0x20)) - -#define DIEP_TXFSTS(n) (OTG_BASE + (0x918 + (n)*0x20)) - -#define DIEP_DMA(n) (OTG_BASE + (0x914 + (n)*0x20)) -#define DOEP_DMA(n) (OTG_BASE + (0xb14 + (n)*0x20)) - -#define REG_OTG_DCFG REG32(OTG_DCFG) -#define REG_OTG_DCTL REG32(OTG_DCTL) -#define REG_OTG_DSTS REG32(OTG_DSTS) -#define REG_DIEP_MASK REG32(DIEP_MASK) -#define REG_DOEP_MASK REG32(DOEP_MASK) -#define REG_OTG_DAINT REG32(OTG_DAINT) -#define REG_DAINT_MASK REG32(DAINT_MASK) -#define REG_DIEP_EMPMSK REG32(DIEP_EMPMSK) - -#define REG_DIEP_CTL(n) REG32(DIEP_CTL(n)) -#define REG_DOEP_CTL(n) REG32(DOEP_CTL(n)) - -#define REG_DIEP_INT(n) REG32(DIEP_INT(n)) -#define REG_DOEP_INT(n) REG32(DOEP_INT(n)) - -#define REG_DIEP_SIZE(n) REG32(DIEP_SIZE(n)) -#define REG_DOEP_SIZE(n) REG32(DOEP_SIZE(n)) - -#define REG_DIEP_TXFSTS(n) REG32(DIEP_TXFSTS(n)) - -#define REG_DIEP_DMA(n) REG32(DIEP_DMA(n)) -#define REG_DOEP_DMA(n) REG32(DOEP_DMA(n)) - -/* Regs macro define */ -/*************************************************/ -#define AHBCFG_TXFE_LVL BIT7 -#define AHBCFG_DMA_ENA BIT5 -#define AHBCFG_GLOBLE_INTRMASK BIT0 -#define USBCFG_FORCE_DEVICE BIT30 -#define USBCFG_TRDTIME_MASK (0xf << 10) -#define USBCFG_TRDTIME_9 (9 << 10) -#define USBCFG_TRDTIME_6 (6 << 10) - -/* GRSTCTL */ -#define RSTCTL_AHB_IDLE BIT31 -#define RSTCTL_TXFNUM_ALL (0x10 << 6) -#define RSTCTL_TXFIFO_FLUSH BIT5 -#define RSTCTL_RXFIFO_FLUSH BIT4 -#define RSTCTL_INTK_FLUSH BIT3 -#define RSTCTL_FRMCNT_RST BIT2 -#define RSTCTL_CORE_RST BIT0 - -/* GINTMSK */ -#define GINTMSK_RSUME_DETE BIT31 -#define GINTMSK_CONID_STSCHG BIT28 -#define GINTMSK_RESET_DETE BIT23 -#define GINTMSK_FETCH_SUSPEND BIT22 -#define GINTMSK_OEP_INTR BIT19 -#define GINTMSK_IEP_INTR BIT18 -#define GINTMSK_EP_MISMATCH BIT17 -#define GINTMSK_ENUM_DONE BIT13 -#define GINTMSK_USB_RESET BIT12 -#define GINTMSK_USB_SUSPEND BIT11 -#define GINTMSK_USB_EARLYSUSPEND BIT10 -#define GINTMSK_I2C_INT BIT9 -#define GINTMSK_ULPK_CKINT BIT8 -#define GINTMSK_GOUTNAK_EFF BIT7 -#define GINTMSK_GINNAK_EFF BIT6 -#define GINTMSK_NPTXFIFO_EMPTY BIT5 -#define GINTMSK_RXFIFO_NEMPTY BIT4 -#define GINTMSK_START_FRAM BIT3 -#define GINTMSK_OTG_INTR BIT2 -#define GINTMSK_MODE_MISMATCH BIT1 - -/* GINTSTS */ -#define GINTSTS_RSUME_DETE BIT31 -#define GINTSTS_CONID_STSCHG BIT28 -#define GINTSTS_RESET_DETE BIT23 -#define GINTSTS_FETCH_SUSPEND BIT22 -#define GINTSTS_OEP_INTR BIT19 -#define GINTSTS_IEP_INTR BIT18 -#define GINTSTS_EP_MISMATCH BIT17 -#define GINTSTS_ENUM_DONE BIT13 -#define GINTSTS_USB_RESET BIT12 -#define GINTSTS_USB_SUSPEND BIT11 -#define GINTSTS_USB_EARLYSUSPEND BIT10 -#define GINTSTS_I2C_INT BIT9 -#define GINTSTS_ULPK_CKINT BIT8 -#define GINTSTS_GOUTNAK_EFF BIT7 -#define GINTSTS_GINNAK_EFF BIT6 -#define GINTSTS_NPTXFIFO_EMPTY BIT5 -#define GINTSTS_RXFIFO_NEMPTY BIT4 -#define GINTSTS_START_FRAM BIT3 -#define GINTSTS_OTG_INTR BIT2 -#define GINTSTS_MODE_MISMATCH BIT1 - -/* DCTL */ -#define DCTL_CGOUTNAK BIT10 -#define DCTL_CLR_GNPINNAK BIT8 -#define DCTL_SGNPINNAK BIT7 -#define DCTL_SOFT_DISCONN BIT1 -#define DCTL_SGOUTNAK BIT9 -/* DCFG */ -#define DCFG_DEV_ADDR_MASK (0x7f << 4) -#define DCFG_DEV_ADDR_BIT 4 -#define DCFG_DEV_DESC_DMA (1 << 23) -/* DSTS */ -#define DSTS_ERRATIC_ERROR BIT3 -#define DSTS_ENUM_SPEED_MASK (0x3 << 1) -#define DSTS_ENUM_SPEED_BIT BIT1 -#define DSTS_ENUM_SPEED_HIGH (0x0 << 1) -#define DSTS_ENUM_SPEED_FULL_30OR60 (0x1 << 1) -#define DSTS_ENUM_SPEED_LOW (0x2 << 1) -#define DSTS_ENUM_SPEED_FULL_48 (0x3 << 1) - -/* GRXSTSR/GRXSTSP */ -#define GRXSTSP_PKSTS_MASK (0xf << 17) -#define GRXSTSP_PKSTS_GOUT_NAK (0x1 << 17) -#define GRXSTSP_PKSTS_GOUT_RECV (0x2 << 17) -#define GRXSTSP_PKSTS_TX_COMP (0x3 << 17) -#define GRXSTSP_PKSTS_SETUP_COMP (0x4 << 17) -#define GRXSTSP_PKSTS_SETUP_RECV (0x6 << 17) -#define GRXSTSP_BYTE_CNT_MASK (0x7ff << 4) -#define GRXSTSP_BYTE_CNT_BIT 4 -#define GRXSTSP_EPNUM_MASK (0xf) -#define GRXSTSP_EPNUM_BIT BIT0 - - -/* DIOEPCTL */ -// ep0 -#define DEP_EP0_MAXPKET_SIZE 64 -#define DEP_EP0_MPS_64 (0x0) -#define DEP_EP0_MPS_32 (0x1) -#define DEP_EP0_MPS_16 (0x2) -#define DEP_EP0_MPS_8 (0x3) - -#define DEP_ENA_BIT BIT31 -#define DEP_DISENA_BIT BIT30 -#define DEP_SET_NAK BIT27 -#define DEP_CLEAR_NAK BIT26 -#define DEP_SET_STALL BIT21 -#define DEP_TYPE_MASK (0x3 << 18) -#define DEP_TYPE_CNTL (0x0 << 18) -#define DEP_TYPE_ISO (0x1 << 18) -#define DEP_TYPE_BULK (0x2 << 18) -#define DEP_TYPE_INTR (0x3 << 18) -#define USB_ACTIVE_EP BIT15 -#define DEP_PKTSIZE_MASK 0x7ff -#define DEP_FS_PKTSIZE 64 -#define DEP_HS_PKTSIZE 512 - -/* DIOEPINT */ -#define DEP_NYET_INT BIT14 -#define DEP_NAK_INT BIT13 -#define DEP_BABBLE_ERR_INT BIT12 -#define DEP_PKT_DROP_STATUS BIT11 -#define DEP_BNA_INT BIT9 -#define DEP_TXFIFO_UNDRN BIT8 // Only for INEP -#define DEP_OUTPKT_ERR BIT8 // Only for OUTEP -#define DEP_TXFIFO_EMPTY BIT7 -#define DEP_INEP_NAKEFF BIT6 // Only for INEP -#define DEP_B2B_SETUP_RECV BIT6 // Only for OUTEP0 -#define DEP_INTOKEN_EPMISATCH BIT5 // Only for INEP -#define DEP_STATUS_PHASE_RECV BIT5 // Only for OUTEP0 -#define DEP_INTOKEN_RECV_TXFIFO_EMPTY BIT4 // Only for INEP -#define DEP_OUTTOKEN_RECV_EPDIS BIT4 // Only for OUTEP -#define DEP_TIME_OUT BIT3 // Only for INEP -#define DEP_SETUP_PHASE_DONE BIT3 // Only for OUTEP0 -#define DEP_AHB_ERR BIT2 -#define DEP_EPDIS_INT BIT1 -#define DEP_XFER_COMP BIT0 // Used by INEP and OUTEP - -/* DOEPSIZ0 */ -#define DOEPSIZE0_SUPCNT_1 (0x1 << 29) -#define DOEPSIZE0_SUPCNT_2 (0x2 << 29) -#define DOEPSIZE0_SUPCNT_3 (0x3 << 29) -#define DOEPSIZE0_PKTCNT_BIT BIT19 - - -#define DEP_RXFIFO_SIZE 1064 -#define DEP_NPTXFIFO_SIZE 1024 -#define DEP_DTXFIFO_SIZE 768 - - -#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0 -#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1 -#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3 -#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5 -#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7 - -#define DWC_GAHBCFG_EXT_DMA_BURST_1word 0x0 -#define DWC_GAHBCFG_EXT_DMA_BURST_4word 0x1 -#define DWC_GAHBCFG_EXT_DMA_BURST_8word 0x2 -#define DWC_GAHBCFG_EXT_DMA_BURST_16word 0x3 -#define DWC_GAHBCFG_EXT_DMA_BURST_32word 0x4 -#define DWC_GAHBCFG_EXT_DMA_BURST_64word 0x5 -#define DWC_GAHBCFG_EXT_DMA_BURST_128word 0x6 -#define DWC_GAHBCFG_EXT_DMA_BURST_256word 0x7 - -#define DEP_NUM 2 - -#if 0 -#define UTMI_PHY_WIDTH 8 -#else -#define UTMI_PHY_WIDTH 16 -#endif - -#endif /* _X1000_OTG_DWC_H_ */ diff --git a/libcpu/mips/x1000/x1000_slcdc.h b/libcpu/mips/x1000/x1000_slcdc.h deleted file mode 100644 index fab76ffad9..0000000000 --- a/libcpu/mips/x1000/x1000_slcdc.h +++ /dev/null @@ -1,463 +0,0 @@ -/* - * File : x1000_slcdc.h - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team - * - * Change Logs: - * Date Author Notes - * 2017��3��20�� Urey the first version - */ -#ifndef _X1000_SLCDC_H_ -#define _X1000_SLCDC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/************************************************************************* - * SLCD (Smart LCD Controller) - *************************************************************************/ -#define LCDC0_BASE LCD_BASE - -#define SLCDC_CFG (LCDC0_BASE + 0xA0) /* SLCDC Configure Register */ -#define SLCDC_CTRL (LCDC0_BASE + 0xA4) /* SLCDC Control Register */ -#define SLCDC_STATE (LCDC0_BASE + 0xA8) /* SLCDC Status Register */ -#define SLCDC_DATA (LCDC0_BASE + 0xAC) /* SLCDC Data Register */ - -#define SLCDC_CFG_NEW (LCDC0_BASE + 0xB8) -#define SLCDC_WTIME (LCDC0_BASE + 0xB0) -#define SLCDC_TAS (LCDC0_BASE + 0xB4) -#define SLCDC_SLOW_TIME (LCDC0_BASE + 0xBC) - -/* SLCDC Configure Register */ -#define SLCDC_CFG_DWIDTH_BIT 10 -#define SLCDC_CFG_DWIDTH_MASK (0x7 << SLCDC_CFG_DWIDTH_BIT) -#define SLCDC_CFG_DWIDTH_18BIT (0 << SLCDC_CFG_DWIDTH_BIT) -#define SLCDC_CFG_DWIDTH_16BIT (1 << SLCDC_CFG_DWIDTH_BIT) -#define SLCDC_CFG_DWIDTH_8BIT_x3 (2 << SLCDC_CFG_DWIDTH_BIT) -#define SLCDC_CFG_DWIDTH_8BIT_x2 (3 << SLCDC_CFG_DWIDTH_BIT) -#define SLCDC_CFG_DWIDTH_8BIT_x1 (4 << SLCDC_CFG_DWIDTH_BIT) -#define SLCDC_CFG_DWIDTH_24BIT (5 << SLCDC_CFG_DWIDTH_BIT) -#define SLCDC_CFG_DWIDTH_9BIT_x2 (7 << SLCDC_CFG_DWIDTH_BIT) -#define SLCDC_CFG_CWIDTH_BIT (8) -#define SLCDC_CFG_CWIDTH_MASK (0x3 << SLCDC_CFG_CWIDTH_BIT) -#define SLCDC_CFG_CWIDTH_16BIT (0 << SLCDC_CFG_CWIDTH_BIT) -#define SLCDC_CFG_CWIDTH_8BIT (1 << SLCDC_CFG_CWIDTH_BIT) -#define SLCDC_CFG_CWIDTH_18BIT (2 << SLCDC_CFG_CWIDTH_BIT) -#define SLCDC_CFG_CWIDTH_24BIT (3 << SLCDC_CFG_CWIDTH_BIT) -#define SLCDC_CFG_CS_ACTIVE_LOW (0 << 4) -#define SLCDC_CFG_CS_ACTIVE_HIGH (1 << 4) -#define SLCDC_CFG_RS_CMD_LOW (0 << 3) -#define SLCDC_CFG_RS_CMD_HIGH (1 << 3) -#define SLCDC_CFG_CLK_ACTIVE_FALLING (0 << 1) -#define SLCDC_CFG_CLK_ACTIVE_RISING (1 << 1) -#define SLCDC_CFG_TYPE_PARALLEL (0 << 0) -#define SLCDC_CFG_TYPE_SERIAL (1 << 0) - -/* SLCD New Configure Register */ -#define SLCDC_NEW_CFG_DWIDTH_BIT 13 -#define SLCDC_NEW_CFG_DWIDTH_MASK (0x7 << SLCDC_NEW_CFG_DWIDTH_BIT) -#define SLCDC_NEW_CFG_DWIDTH_8BIT (0 << SLCDC_NEW_CFG_DWIDTH_BIT) -#define SLCDC_NEW_CFG_DWIDTH_9BIT (1 << SLCDC_NEW_CFG_DWIDTH_BIT) -#define SLCDC_NEW_CFG_DWIDTH_16BIT (2 << SLCDC_NEW_CFG_DWIDTH_BIT) -#define SLCDC_NEW_CFG_DWIDTH_18BIT (3 << SLCDC_NEW_CFG_DWIDTH_BIT) -#define SLCDC_NEW_CFG_DWIDTH_24BIT (4 << SLCDC_NEW_CFG_DWIDTH_BIT) -#define SLCDC_NEW_CFG_6800_MD (1 << 11) -#define SLCDC_NEW_CFG_CMD_9BIT (1 << 10) /* only use in old slcd */ -#define SLCDC_NEW_CFG_CMD_16BIT (0 << 10) /* only use in old slcd */ -#define SLCDC_NEW_CFG_DTIME_BIT 8 -#define SLCDC_NEW_CFG_DTIME_MASK (0x3 << SLCDC_NEW_CFG_DTIME_BIT) -#define SLCDC_NEW_CFG_DTIME_ONCE (0 << SLCDC_NEW_CFG_DTIME_BIT) -#define SLCDC_NEW_CFG_DTIME_TWICE (1 << SLCDC_NEW_CFG_DTIME_BIT) -#define SLCDC_NEW_CFG_DTIME_THREE (2 << SLCDC_NEW_CFG_DTIME_BIT) -#define SLCDC_NEW_CFG_CS_HIGH_IDLE (0 << 5) -#define SLCDC_NEW_CFG_CS_LOW_IDLE (1 << 5) -#define SLCDC_NEW_CFG_RS_CMD_LOW (0 << 4) -#define SLCDC_NEW_CFG_RS_CMD_HIGH (1 << 4) -#define SLCDC_NEW_CFG_CLK_ACTIVE_FALLING (0 << 3) -#define SLCDC_NEW_CFG_CLK_ACTIVE_RISING (1 << 3) -#define SLCDC_NEW_CFG_DTYPE_PARALLEL (0 << 2) -#define SLCDC_NEW_CFG_DTYPE_SERIAL (1 << 2) -#define SLCDC_NEW_CFG_CTYPE_PARALLEL (0 << 1) -#define SLCDC_NEW_CFG_CTYPE_SERIAL (1 << 1) -#define SLCDC_NEW_CFG_FMT_CONV_EN (1 << 0) - -/* SLCD Control Register */ -#define SLCDC_CTRL_TE_INV (1 << 9) -#define SLCDC_CTRL_NOT_USE_TE (1 << 8) -#define SLCDC_CTRL_DCSI_SEL (1 << 7) -#define SLCDC_CTRL_MIPI_MODE (1 << 6) -#define SLCDC_CTRL_NEW_MODE (1 << 5) -#define SLCDC_CTRL_FAST_MODE (1 << 4) -#define SLCDC_CTRL_GATE_MASK (1 << 3) -#define SLCDC_CTRL_DMA_MODE (1 << 2) -#define SLCDC_CTRL_DMA_START (1 << 1) -#define SLCDC_CTRL_DMA_EN (1 << 0) - -/* SLCD Status Register */ -#define SLCDC_STATE_BUSY (1 << 0) - -/* SLCD Data Register */ -#define SLCDC_DATA_RS_DATA (0 << 30) -#define SLCDC_DATA_RS_COMMAND (1 << 30) - -/************************************************************************* - * LCDC (LCD Controller) - *************************************************************************/ - -#define LCDC_CFG (LCDC0_BASE + 0x00) -#define LCDC_CTRL (LCDC0_BASE + 0x30) -#define LCDC_STATE (LCDC0_BASE + 0x34) -#define LCDC_OSDC (LCDC0_BASE + 0x100) -#define LCDC_OSDCTRL (LCDC0_BASE + 0x104) -#define LCDC_OSDS (LCDC0_BASE + 0x108) -#define LCDC_BGC0 (LCDC0_BASE + 0x10C) -#define LCDC_BGC1 (LCDC0_BASE + 0x2C4) -#define LCDC_KEY0 (LCDC0_BASE + 0x110) -#define LCDC_KEY1 (LCDC0_BASE + 0x114) -#define LCDC_ALPHA (LCDC0_BASE + 0x118) -#define LCDC_RGBC (LCDC0_BASE + 0x90) -#define LCDC_VAT (LCDC0_BASE + 0x0c) -#define LCDC_DAH (LCDC0_BASE + 0x10) -#define LCDC_DAV (LCDC0_BASE + 0x14) -#define LCDC_XYP0 (LCDC0_BASE + 0x120) -#define LCDC_XYP1 (LCDC0_BASE + 0x124) -#define LCDC_SIZE0 (LCDC0_BASE + 0x128) -#define LCDC_SIZE1 (LCDC0_BASE + 0x12C) -#define LCDC_VSYNC (LCDC0_BASE + 0x04) -#define LCDC_HSYNC (LCDC0_BASE + 0x08) -#define LCDC_PS (LCDC0_BASE + 0x18) -#define LCDC_CLS (LCDC0_BASE + 0x1c) -#define LCDC_SPL (LCDC0_BASE + 0x20) -#define LCDC_REV (LCDC0_BASE + 0x24) -#define LCDC_IID (LCDC0_BASE + 0x38) -#define LCDC_DA0 (LCDC0_BASE + 0x40) -#define LCDC_SA0 (LCDC0_BASE + 0x44) -#define LCDC_FID0 (LCDC0_BASE + 0x48) -#define LCDC_CMD0 (LCDC0_BASE + 0x4c) -#define LCDC_DA1 (LCDC0_BASE + 0x50) -#define LCDC_SA1 (LCDC0_BASE + 0x54) -#define LCDC_FID1 (LCDC0_BASE + 0x58) -#define LCDC_CMD1 (LCDC0_BASE + 0x5c) -#define LCDC_OFFS0 (LCDC0_BASE + 0x60) -#define LCDC_PW0 (LCDC0_BASE + 0x64) -#define LCDC_CNUM0 (LCDC0_BASE + 0x68) -#define LCDC_DESSIZE0 (LCDC0_BASE + 0x6C) -#define LCDC_OFFS1 (LCDC0_BASE + 0x70) -#define LCDC_PW1 (LCDC0_BASE + 0x74) -#define LCDC_CNUM1 (LCDC0_BASE + 0x78) -#define LCDC_DESSIZE1 (LCDC0_BASE + 0x7C) -#define LCDC_PCFG (LCDC0_BASE + 0x2C0) -#define LCDC_CPOS1 (0x78) -#define LCDC_DUAL_CTRL (0x2c8) -#define LCDC_ENH_CFG (0x400) -#define LCDC_ENH_CSCCFG (0x404) -#define LCDC_ENH_LUMACFG (0x408) -#define LCDC_ENH_CHROCFG0 (0x40c) -#define LCDC_ENH_CHROCFG1 (0x410) -#define LCDC_ENH_DITHERCFG (0x414) -#define LCDC_ENH_STATUS (0x418) -#define LCDC_ENH_GAMMA (0x800) -#define LCDC_ENH_VEE (0x1000) - -/* LCD Configure Register */ -#define LCDC_CFG_LCDPIN_BIT 31 -#define LCDC_CFG_LCDPIN_MASK (0x1 << LCDC_CFG_LCDPIN_BIT) -#define LCDC_CFG_LCDPIN_LCD (0x0 << LCDC_CFG_LCDPIN_BIT) -#define LCDC_CFG_LCDPIN_SLCD (0x1 << LCDC_CFG_LCDPIN_BIT) -#define LCDC_CFG_TVEPEH (1 << 30) -#define LCDC_CFG_NEWDES (1 << 28) -#define LCDC_CFG_PALBP (1 << 27) -#define LCDC_CFG_TVEN (1 << 26) -#define LCDC_CFG_RECOVER (1 << 25) -#define LCDC_CFG_PSM (1 << 23) -#define LCDC_CFG_CLSM (1 << 22) -#define LCDC_CFG_SPLM (1 << 21) -#define LCDC_CFG_REVM (1 << 20) -#define LCDC_CFG_HSYNM (1 << 19) -#define LCDC_CFG_PCLKM (1 << 18) -#define LCDC_CFG_INVDAT (1 << 17) -#define LCDC_CFG_SYNDIR_IN (1 << 16) -#define LCDC_CFG_PSP (1 << 15) -#define LCDC_CFG_CLSP (1 << 14) -#define LCDC_CFG_SPLP (1 << 13) -#define LCDC_CFG_REVP (1 << 12) -#define LCDC_CFG_HSP (1 << 11) -#define LCDC_CFG_PCP (1 << 10) -#define LCDC_CFG_DEP (1 << 9) -#define LCDC_CFG_VSP (1 << 8) -#define LCDC_CFG_MODE_TFT_18BIT (1 << 7) -#define LCDC_CFG_MODE_TFT_16BIT (0 << 7) -#define LCDC_CFG_MODE_TFT_24BIT (1 << 6) -#define LCDC_CFG_MODE_BIT 0 -#define LCDC_CFG_MODE_MASK (0x0f << LCDC_CFG_MODE_BIT) -#define LCDC_CFG_MODE_GENERIC_TFT (0 << LCDC_CFG_MODE_BIT) -#define LCDC_CFG_MODE_SPECIAL_TFT_1 (1 << LCDC_CFG_MODE_BIT) -#define LCDC_CFG_MODE_SPECIAL_TFT_2 (2 << LCDC_CFG_MODE_BIT) -#define LCDC_CFG_MODE_SPECIAL_TFT_3 (3 << LCDC_CFG_MODE_BIT) -#define LCDC_CFG_MODE_NONINTER_CCIR656 (4 << LCDC_CFG_MODE_BIT) -#define LCDC_CFG_MODE_INTER_CCIR656 (6 << LCDC_CFG_MODE_BIT) -#define LCDC_CFG_MODE_SERIAL_TFT (12 << LCDC_CFG_MODE_BIT) -#define LCDC_CFG_MODE_LCM (13 << LCDC_CFG_MODE_BIT) -/* LCD Control Register */ -#define LCDC_CTRL_PINMD (1 << 31) -#define LCDC_CTRL_BST_BIT 28 -#define LCDC_CTRL_BST_MASK (0x7 << LCDC_CTRL_BST_BIT) -#define LCDC_CTRL_BST_4 (0 << LCDC_CTRL_BST_BIT) -#define LCDC_CTRL_BST_8 (1 << LCDC_CTRL_BST_BIT) -#define LCDC_CTRL_BST_16 (2 << LCDC_CTRL_BST_BIT) -#define LCDC_CTRL_BST_32 (3 << LCDC_CTRL_BST_BIT) -#define LCDC_CTRL_BST_64 (4 << LCDC_CTRL_BST_BIT) -#define LCDC_CTRL_RGB565 (0 << 27) -#define LCDC_CTRL_RGB555 (1 << 27) -#define LCDC_CTRL_OFUP (1 << 26) -#define LCDC_CTRL_PDD_BIT 16 -#define LCDC_CTRL_PDD_MASK (0xff << LCDC_CTRL_PDD_BIT) -#define LCDC_CTRL_DACTE (1 << 14) -#define LCDC_CTRL_EOFM (1 << 13) -#define LCDC_CTRL_SOFM (1 << 12) -#define LCDC_CTRL_OFUM (1 << 11) -#define LCDC_CTRL_IFUM0 (1 << 10) -#define LCDC_CTRL_IFUM1 (1 << 9) -#define LCDC_CTRL_LDDM (1 << 8) -#define LCDC_CTRL_QDM (1 << 7) -#define LCDC_CTRL_BEDN (1 << 6) -#define LCDC_CTRL_PEDN (1 << 5) -#define LCDC_CTRL_DIS (1 << 4) -#define LCDC_CTRL_ENA (1 << 3) -#define LCDC_CTRL_BPP_BIT 0 -#define LCDC_CTRL_BPP_MASK (0x07 << LCDC_CTRL_BPP_BIT) -#define LCDC_CTRL_BPP_1 (0 << LCDC_CTRL_BPP_BIT) -#define LCDC_CTRL_BPP_2 (1 << LCDC_CTRL_BPP_BIT) -#define LCDC_CTRL_BPP_4 (2 << LCDC_CTRL_BPP_BIT) -#define LCDC_CTRL_BPP_8 (3 << LCDC_CTRL_BPP_BIT) -#define LCDC_CTRL_BPP_16 (4 << LCDC_CTRL_BPP_BIT) -#define LCDC_CTRL_BPP_18_24 (5 << LCDC_CTRL_BPP_BIT) -#define LCDC_CTRL_BPP_CMPS_24 (6 << LCDC_CTRL_BPP_BIT) -#define LCDC_CTRL_BPP_30 (7 << LCDC_CTRL_BPP_BIT) -/* LCD Status Register */ -#define LCDC_STATE_QD (1 << 7) -#define LCDC_STATE_EOF (1 << 5) -#define LCDC_STATE_SOF (1 << 4) -#define LCDC_STATE_OFU (1 << 3) -#define LCDC_STATE_IFU0 (1 << 2) -#define LCDC_STATE_IFU1 (1 << 1) -#define LCDC_STATE_LDD (1 << 0) -/* OSD Configure Register */ -#define LCDC_OSDC_PREMULTI1 (1 << 23) -#define LCDC_OSDC_COEF_SLE1_BIT 21 -#define LCDC_OSDC_COEF_SLE1_MASK (0x03 << LCDC_OSDC_COEF_SLE1_BIT) -#define LCDC_OSDC_COEF_SLE1_0 (0 << LCDC_OSDC_COEF_SLE1_BIT) -#define LCDC_OSDC_COEF_SLE1_1 (1 << LCDC_OSDC_COEF_SLE1_BIT) -#define LCDC_OSDC_COEF_SLE1_2 (2 << LCDC_OSDC_COEF_SLE1_BIT) -#define LCDC_OSDC_COEF_SLE1_3 (3 << LCDC_OSDC_COEF_SLE1_BIT) -#define LCDC_OSDC_PREMULTI0 (1 << 20) -#define LCDC_OSDC_COEF_SLE0_BIT 18 -#define LCDC_OSDC_COEF_SLE0_MASK (0x03 << LCDC_OSDC_COEF_SLE0_BIT) -#define LCDC_OSDC_COEF_SLE0_0 (0 << LCDC_OSDC_COEF_SLE0_BIT) -#define LCDC_OSDC_COEF_SLE0_1 (1 << LCDC_OSDC_COEF_SLE0_BIT) -#define LCDC_OSDC_COEF_SLE0_2 (2 << LCDC_OSDC_COEF_SLE0_BIT) -#define LCDC_OSDC_COEF_SLE0_3 (3 << LCDC_OSDC_COEF_SLE0_BIT) -#define LCDC_OSDC_ALPHAMD1 (1 << 17) -#define LCDC_OSDC_SOFM1 (1 << 15) -#define LCDC_OSDC_EOFM1 (1 << 14) -#define LCDC_OSDC_SOFM0 (1 << 11) -#define LCDC_OSDC_EOFM0 (1 << 10) -#define LCDC_OSDC_DENDM (1 << 9) -#define LCDC_OSDC_F1EN (1 << 4) -#define LCDC_OSDC_F0EN (1 << 3) -#define LCDC_OSDC_ALPHAEN (1 << 2) -#define LCDC_OSDC_ALPHAMD0 (1 << 1) -#define LCDC_OSDC_OSDEN (1 << 0) -/* OSD Controll Register */ -#define LCDC_OSDCTRL_IPU_CLKEN (1 << 15) -#define LCDC_OSDCTRL_RGB0_RGB565 (0 << 5) -#define LCDC_OSDCTRL_RGB0_RGB555 (1 << 5) -#define LCDC_OSDCTRL_RGB1_RGB565 (0 << 4) -#define LCDC_OSDCTRL_RGB1_RGB555 (1 << 4) -#define LCDC_OSDCTRL_BPP_BIT 0 -#define LCDC_OSDCTRL_BPP_MASK (0x7<<LCDC_OSDCTRL_BPP_BIT) -#define LCDC_OSDCTRL_BPP_15_16 (4 << LCDC_OSDCTRL_BPP_BIT) -#define LCDC_OSDCTRL_BPP_18_24 (5 << LCDC_OSDCTRL_BPP_BIT) -#define LCDC_OSDCTRL_BPP_CMPS_24 (6 << LCDC_OSDCTRL_BPP_BIT) -#define LCDC_OSDCTRL_BPP_30 (7 << LCDC_OSDCTRL_BPP_BIT) -/* OSD State Register */ -#define LCDC_OSDS_SOF1 (1 << 15) -#define LCDC_OSDS_EOF1 (1 << 14) -#define LCDC_OSDS_SOF0 (1 << 11) -#define LCDC_OSDS_EOF0 (1 << 10) -#define LCDC_OSDS_DEND (1 << 8) -/* Background 0 or Background 1 Color Register */ -#define LCDC_BGC_RED_OFFSET 16 -#define LCDC_BGC_RED_MASK (0xFF << LCDC_BGC_RED_OFFSET) -#define LCDC_BGC_GREEN_OFFSET 8 -#define LCDC_BGC_GREEN_MASK (0xFF << LCDC_BGC_GREEN_OFFSET) -#define LCDC_BGC_BLUE_OFFSET 0 -#define LCDC_BGC_BLUE_MASK (0xFF << LCDC_BGC_BLUE_OFFSET) -/* Foreground 0 or Foreground 1 Color Key Register */ -#define LCDC_KEY_KEYEN (1 << 31) -#define LCDC_KEY_KEYMD (1 << 30) -#define LCDC_KEY_RED_OFFSET 16 -#define LCDC_KEY_RED_MASK (0xFF << LCDC_KEY_RED_OFFSET) -#define LCDC_KEY_GREEN_OFFSET 8 -#define LCDC_KEY_GREEN_MASK (0xFF << LCDC_KEY_GREEN_OFFSET) -#define LCDC_KEY_BLUE_OFFSET 0 -#define LCDC_KEY_BLUE_MASK (0xFF << LCDC_KEY_BLUE_OFFSET) -#define LCDC_KEY_MASK (LCDC_KEY_RED_MASK | LCDC_KEY_GREEN_MASK\ -/* ALPHA Register */ -#define LCDC_ALPHA1_OFFSET 8 -#define LCDC_ALPHA1_MASK (0xFF << LCDC_ALPHA1_OFFSET) -#define LCDC_ALPHA0_OFFSET 0 -#define LCDC_ALPHA0_MASK (0xFF << LCDC_ALPHA0_OFFSET) -/* IPU Restart Register */ -#define LCDC_IPUR_IPUREN (1 << 31) -#define LCDC_IPUR_IPURMASK (0xFFFFFF) -/* RGB Control Register */ -#define LCDC_RGBC_RGBDM (1 << 15) -#define LCDC_RGBC_DMM (1 << 14) -#define LCDC_RGBC_RGBFMT (1 << 7) -#define LCDC_RGBC_ODDRGB_BIT 4 -#define LCDC_RGBC_ODDRGB_MASK (0x7 << LCDC_RGBC_ODDRGB_BIT) -#define LCDC_RGBC_ODD_RGB (0 << LCDC_RGBC_ODDRGB_BIT) -#define LCDC_RGBC_ODD_RBG (1 << LCDC_RGBC_ODDRGB_BIT) -#define LCDC_RGBC_ODD_GRB (2 << LCDC_RGBC_ODDRGB_BIT) -#define LCDC_RGBC_ODD_GBR (3 << LCDC_RGBC_ODDRGB_BIT) -#define LCDC_RGBC_ODD_BRG (4 << LCDC_RGBC_ODDRGB_BIT) -#define LCDC_RGBC_ODD_BGR (5 << LCDC_RGBC_ODDRGB_BIT) -#define LCDC_RGBC_EVENRGB_BIT 0 -#define LCDC_RGBC_EVENRGB_MASK (0x7<<LCDC_RGBC_EVENRGB_BIT) -#define LCDC_RGBC_EVEN_RGB 0 -#define LCDC_RGBC_EVEN_RBG 1 -#define LCDC_RGBC_EVEN_GRB 2 -#define LCDC_RGBC_EVEN_GBR 3 -#define LCDC_RGBC_EVEN_BRG 4 -#define LCDC_RGBC_EVEN_BGR 5 -/* Vertical Synchronize Register */ -#define LCDC_VSYNC_VPS_BIT 16 -#define LCDC_VSYNC_VPS_MASK (0xfff << LCDC_VSYNC_VPS_BIT) -#define LCDC_VSYNC_VPE_BIT 0 -#define LCDC_VSYNC_VPE_MASK (0xfff << LCDC_VSYNC_VPE_BIT) -/* Horizontal Synchronize Register */ -#define LCDC_HSYNC_HPS_BIT 16 -#define LCDC_HSYNC_HPS_MASK (0xfff << LCDC_HSYNC_HPS_BIT) -#define LCDC_HSYNC_HPE_BIT 0 -#define LCDC_HSYNC_HPE_MASK (0xfff << LCDC_HSYNC_HPE_BIT) -/* Virtual Area Setting Register */ -#define LCDC_VAT_HT_BIT 16 -#define LCDC_VAT_HT_MASK (0xfff << LCDC_VAT_HT_BIT) -#define LCDC_VAT_VT_BIT 0 -#define LCDC_VAT_VT_MASK (0xfff << LCDC_VAT_VT_BIT) -/* Display Area Horizontal Start/End Point Register */ -#define LCDC_DAH_HDS_BIT 16 -#define LCDC_DAH_HDS_MASK (0xfff << LCDC_DAH_HDS_BIT) -#define LCDC_DAH_HDE_BIT 0 -#define LCDC_DAH_HDE_MASK (0xfff << LCDC_DAH_HDE_BIT) -/* Display Area Vertical Start/End Point Register */ -#define LCDC_DAV_VDS_BIT 16 -#define LCDC_DAV_VDS_MASK (0xfff << LCDC_DAV_VDS_BIT) -#define LCDC_DAV_VDE_BIT 0 -#define LCDC_DAV_VDE_MASK (0xfff << LCDC_DAV_VDE_BIT) -/* Foreground 0 or Foreground 1 XY Position Register */ -#define LCDC_XYP_YPOS_BIT 16 -#define LCDC_XYP_YPOS_MASK (0xfff << LCDC_XYP_YPOS_BIT) -#define LCDC_XYP_XPOS_BIT 0 -#define LCDC_XYP_XPOS_MASK (0xfff << LCDC_XYP_XPOS_BIT) -/* Foreground 0 or Foreground 1 Size Register */ -#define LCDC_SIZE_HEIGHT_BIT 16 -#define LCDC_SIZE_HEIGHT_MASK (0xfff << LCDC_SIZE_HEIGHT_BIT) -#define LCDC_SIZE_WIDTH_BIT 0 -#define LCDC_SIZE_WIDTH_MASK (0xfff << LCDC_SIZE_WIDTH_BIT) -/* PS Signal Setting */ -#define LCDC_PS_PSS_BIT 16 -#define LCDC_PS_PSS_MASK (0xfff << LCDC_PS_PSS_BIT) -#define LCDC_PS_PSE_BIT 0 -#define LCDC_PS_PSE_MASK (0xfff << LCDC_PS_PSE_BIT) -/* CLS Signal Setting */ -#define LCDC_CLS_CLSS_BIT 16 -#define LCDC_CLS_CLSS_MASK (0xfff << LCDC_CLS_CLSS_BIT) -#define LCDC_CLS_CLSE_BIT 0 -#define LCDC_CLS_CLSE_MASK (0xfff << LCDC_CLS_CLSE_BIT) -/* SPL Signal Setting */ -#define LCDC_SPL_SPLS_BIT 16 -#define LCDC_SPL_SPLS_MASK (0xfff << LCDC_SPL_SPLS_BIT) -#define LCDC_SPL_SPLE_BIT 0 -#define LCDC_SPL_SPLE_MASK (0xfff << LCDC_SPL_SPLE_BIT) -/* REV Signal Setting */ -#define LCDC_REV_REVS_BIT 16 -#define LCDC_REV_REVS_MASK (0xfff << LCDC_REV_REVS_BIT) -/* DMA Command 0 or 1 Register */ -#define LCDC_CMD_SOFINT (1 << 31) -#define LCDC_CMD_EOFINT (1 << 30) -#define LCDC_CMD_CMD (1 << 29) -#define LCDC_CMD_PAL (1 << 28) -#define LCDC_CMD_COMPEN (1 << 27) -#define LCDC_CMD_FRM_EN (1 << 26) -#define LCDC_CMD_FIELD_SEL (1 << 25) -#define LCDC_CMD_16X16BLOCK (1 << 24) -#define LCDC_CMD_LEN_BIT 0 -#define LCDC_CMD_LEN_MASK (0xffffff << LCDC_CMD_LEN_BIT) -/* DMA Offsize Register 0,1 */ -#define LCDC_OFFS_BIT 0 -#define LCDC_OFFS_OFFSIZE_MASK (0xffffff << LCDC_OFFS_BIT) -/* DMA Page Width Register 0,1 */ -#define LCDC_PW_BIT 0 -#define LCDC_PW_PAGEWIDTH_MASK (0xffffff << LCDC_PW_BIT) -/* DMA Command Counter Register 0,1 */ -#define LCDC_CNUM_BIT 0 -#define LCDC_CNUM_CNUM_MASK (0xff << LCDC_CNUM_BIT) -#define LCDC_CPOS_ALPHAMD1 (1 << 31) -#define LCDC_CPOS_RGB_RGB565 (0 << 30) -#define LCDC_CPOS_RGB_RGB555 (1 << 30) -#define LCDC_CPOS_BPP_BIT 27 -#define LCDC_CPOS_BPP_MASK (0x07 << LCDC_CPOS_BPP_BIT) -#define LCDC_CPOS_BPP_16 (4 << LCDC_CPOS_BPP_BIT) -#define LCDC_CPOS_BPP_18_24 (5 << LCDC_CPOS_BPP_BIT) -#define LCDC_CPOS_BPP_CMPS_24 (6 << LCDC_CPOS_BPP_BIT) -#define LCDC_CPOS_BPP_30 (7 << LCDC_CPOS_BPP_BIT) -#define LCDC_CPOS_PREMULTI (1 << 26) -#define LCDC_CPOS_COEF_SLE_BIT 24 -#define LCDC_CPOS_COEF_SLE_MASK (0x3 << LCDC_CPOS_COEF_SLE_BIT) -#define LCDC_CPOS_COEF_SLE_0 (0 << LCDC_CPOS_COEF_SLE_BIT) -#define LCDC_CPOS_COEF_SLE_1 (1 << LCDC_CPOS_COEF_SLE_BIT) -#define LCDC_CPOS_COEF_SLE_2 (2 << LCDC_CPOS_COEF_SLE_BIT) -#define LCDC_CPOS_COEF_SLE_3 (3 << LCDC_CPOS_COEF_SLE_BIT) -#define LCDC_CPOS_YPOS_BIT 12 -#define LCDC_CPOS_YPOS_MASK (0xfff << LCDC_CPOS_YPOS_BIT) -#define LCDC_CPOS_XPOS_BIT 0 -#define LCDC_CPOS_XPOS_MASK (0xfff << LCDC_CPOS_XPOS_BIT) -/* Foreground 0,1 Size Register */ -#define LCDC_DESSIZE_ALPHA_BIT 24 -#define LCDC_DESSIZE_ALPHA_MASK (0xff << LCDC_DESSIZE_ALPHA_BIT) -#define LCDC_DESSIZE_HEIGHT_BIT 12 -#define LCDC_DESSIZE_HEIGHT_MASK (0xfff << LCDC_DESSIZE_HEIGHT_BIT) -#define LCDC_DESSIZE_WIDTH_BIT 0 -#define LCDC_DESSIZE_WIDTH_MASK (0xfff << LCDC_DESSIZE_WIDTH_BIT) -/* Priority level threshold configure Register */ -#define LCDC_PCFG_LCDC_PRI_MD (1 << 31) -#define LCDC_PCFG_HP_BST_BIT 28 -#define LCDC_PCFG_HP_BST_MASK (0x7 << LCDC_PCFG_HP_BST_BIT) -#define LCDC_PCFG_HP_BST_4 (0 << LCDC_PCFG_HP_BST_BIT) -#define LCDC_PCFG_HP_BST_8 (1 << LCDC_PCFG_HP_BST_BIT) -#define LCDC_PCFG_HP_BST_16 (2 << LCDC_PCFG_HP_BST_BIT) -#define LCDC_PCFG_HP_BST_32 (3 << LCDC_PCFG_HP_BST_BIT) -#define LCDC_PCFG_HP_BST_C16 (5 << LCDC_PCFG_HP_BST_BIT) -#define LCDC_PCFG_HP_BST_64 (4 << LCDC_PCFG_HP_BST_BIT) -#define LCDC_PCFG_HP_BST_DIS (7 << LCDC_PCFG_HP_BST_BIT) -#define LCDC_PCFG_PCFG2_BIT 18 -#define LCDC_PCFG_PCFG2_MASK (0x1ff << LCDC_PCFG_PCFG2_BIT) -#define LCDC_PCFG_PCFG1_BIT 9 -#define LCDC_PCFG_PCFG1_MASK (0x1ff << LCDC_PCFG_PCFG1_BIT) -#define LCDC_PCFG_PCFG0_BIT 0 -#define LCDC_PCFG_PCFG0_MASK (0x1ff << LCDC_PCFG_PCFG0_BIT) -/* Dual LCDC Channel Control register */ -#define LCDC_DUAL_CTRL_IPU_WR_SEL (1 << 8) -#define LCDC_DUAL_CTRL_TFT_SEL (1 << 6) -#define LCDC_DUAL_CTRL_PRI_IPU_EN (1 << 5) -#define LCDC_DUAL_CTRL_PRI_IPU_BIT 3 -#define LCDC_DUAL_CTRL_PRI_IPU_MASK (0x3 << LCDC_DUAL_CTRL_PRI_IPU_BIT) - - -#ifdef __cplusplus -} -#endif - -#endif /* _X1000_SLCDC_H_ */ diff --git a/libcpu/mips/xburst/SConscript b/libcpu/mips/xburst/SConscript deleted file mode 100644 index 0f06c299bb..0000000000 --- a/libcpu/mips/xburst/SConscript +++ /dev/null @@ -1,11 +0,0 @@ -# RT-Thread building script for component - -from building import * - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.S') -CPPPATH = [cwd] - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/libcpu/mips/xburst/cache.c b/libcpu/mips/xburst/cache.c deleted file mode 100644 index cd37f69993..0000000000 --- a/libcpu/mips/xburst/cache.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * File : cache.c - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes -*/ - -#include "../xburst/cache.h" - -#include <board.h> - -#define CACHE_SIZE 16*1024 -#define CACHE_LINE_SIZE 32 -#define KSEG0 0x80000000 - -#define K0_TO_K1() \ -do { \ - unsigned long __k0_addr; \ - \ - __asm__ __volatile__( \ - "la %0, 1f\n\t" \ - "or %0, %0, %1\n\t" \ - "jr %0\n\t" \ - "nop\n\t" \ - "1: nop\n" \ - : "=&r"(__k0_addr) \ - : "r" (0x20000000) ); \ -} while(0) - -#define K1_TO_K0() \ -do { \ - unsigned long __k0_addr; \ - __asm__ __volatile__( \ - "nop;nop;nop;nop;nop;nop;nop\n\t" \ - "la %0, 1f\n\t" \ - "jr %0\n\t" \ - "nop\n\t" \ - "1: nop\n" \ - : "=&r" (__k0_addr)); \ -} while (0) - -#define INVALIDATE_BTB() \ -do { \ - unsigned long tmp; \ - __asm__ __volatile__( \ - ".set mips32\n\t" \ - "mfc0 %0, $16, 7\n\t" \ - "nop\n\t" \ - "ori %0, 2\n\t" \ - "mtc0 %0, $16, 7\n\t" \ - "nop\n\t" \ - ".set mips2\n\t" \ - : "=&r" (tmp)); \ -} while (0) - -#define SYNC_WB() __asm__ __volatile__ ("sync") - -#define cache_op(op,addr) \ - __asm__ __volatile__( \ - " .set noreorder \n" \ - " .set mips32\n\t \n" \ - " cache %0, %1 \n" \ - " .set mips0 \n" \ - " .set reorder" \ - : \ - : "i" (op), "m" (*(unsigned char *)(addr))) - -void __icache_invalidate_all(void) -{ - unsigned int i; - - K0_TO_K1(); - - asm volatile (".set noreorder\n" - ".set mips32\n\t" - "mtc0\t$0,$28\n\t" - "mtc0\t$0,$29\n" - ".set mips0\n" - ".set reorder\n"); - for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE) - cache_op(Index_Store_Tag_I, i); - - K1_TO_K0(); - - INVALIDATE_BTB(); -} - -void __dcache_writeback_all(void) -{ - unsigned int i; - - for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE) - cache_op(Index_Writeback_Inv_D, i); - - SYNC_WB(); -} - -void rt_hw_cache_init(void) -{ - __dcache_writeback_all(); - __icache_invalidate_all(); -} - diff --git a/libcpu/mips/xburst/cache.h b/libcpu/mips/xburst/cache.h deleted file mode 100644 index c0f8a1f424..0000000000 --- a/libcpu/mips/xburst/cache.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * File : cache.h - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes -*/ - -#ifndef __CACHE_H__ -#define __CACHE_H__ - -/* - * Cache Operations - */ -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 -#define Index_Invalidate_SI 0x02 -#define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_D 0x0d -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_I 0x10 -#define Hit_Invalidate_D 0x11 -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Fill 0x14 -#define Hit_Writeback_Inv_D 0x15 -/* 0x16 is unused */ -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 -/* 0x1a is unused */ -#define Hit_Writeback_SD 0x1b -/* 0x1c is unused */ -/* 0x1e is unused */ -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f - -void rt_hw_cache_init(void); - -#endif diff --git a/libcpu/mips/xburst/cache_gcc.S b/libcpu/mips/xburst/cache_gcc.S deleted file mode 100644 index 76552698d0..0000000000 --- a/libcpu/mips/xburst/cache_gcc.S +++ /dev/null @@ -1,42 +0,0 @@ -/* - * File : cache_init.S - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - */ -#include "../common/mips.inc" -#include "../common/mipsregs.h" -#include "../common/stackframe.h" - - .text - .set noreorder - - .globl cache_init - .ent cache_init -cache_init: - .set noreorder - mtc0 zero, CP0_TAGLO - move t0, a0 // cache total size - move t1, a1 // cache line size - li t2, 0x80000000 - addu t3, t0, t2 - -_cache_init_loop: - cache 8, 0(t2) // icache_index_store_tag - cache 9, 0(t2) // dcache_index_store_tag - addu t2, t1 - bne t2, t3, _cache_init_loop - nop - - mfc0 t0, CP0_CONFIG - li t1, 0x7 - not t1 - and t0, t0, t1 - or t0, 0x3 // cacheable, noncoherent, write-back, write allocate - mtc0 t0, CP0_CONFIG - - jr ra - nop - - .set reorder - .end cache_init diff --git a/libcpu/mips/xburst/context_gcc.S b/libcpu/mips/xburst/context_gcc.S deleted file mode 100644 index d018de3da8..0000000000 --- a/libcpu/mips/xburst/context_gcc.S +++ /dev/null @@ -1,146 +0,0 @@ -/* - * File : context_gcc.S - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-09-11 bernard port to Jz4755 - */ -#include "../common/mips.inc" -#include "../common/stackframe.h" -#include "stack.h" - - .section ".text", "ax" - .set noreorder - -/* - * rt_base_t rt_hw_interrupt_disable() - */ - .globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mfc0 v0, CP0_STATUS - and v1, v0, 0xfffffffe - mtc0 v1, CP0_STATUS - jr ra - nop - -/* - * void rt_hw_interrupt_enable(rt_base_t level) - */ - .globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - mtc0 a0, CP0_STATUS - jr ra - nop - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) - * a0 --> from - * a1 --> to - */ - .globl rt_hw_context_switch -rt_hw_context_switch: - mtc0 ra, CP0_EPC - SAVE_ALL - - sw sp, 0(a0) /* store sp in preempted tasks TCB */ - lw sp, 0(a1) /* get new task stack pointer */ - - RESTORE_ALL_AND_RET - -/* - * void rt_hw_context_switch_to(rt_uint32 to)/* - * a0 --> to - */ - .globl rt_hw_context_switch_to -rt_hw_context_switch_to: - lw sp, 0(a0) /* get new task stack pointer */ - - RESTORE_ALL_AND_RET - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* - */ - .globl rt_thread_switch_interrupt_flag - .globl rt_interrupt_from_thread - .globl rt_interrupt_to_thread - .globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - la t0, rt_thread_switch_interrupt_flag - lw t1, 0(t0) - nop - bnez t1, _reswitch - nop - li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ - sw t1, 0(t0) - la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ - sw a0, 0(t0) -_reswitch: - la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ - sw a1, 0(t0) - jr ra - nop - - .globl system_dump - -/* - * void rt_hw_context_switch_interrupt_do(rt_base_t flag) - */ - .globl rt_interrupt_enter - .globl rt_interrupt_leave - .globl mips_irq_handle -mips_irq_handle: - SAVE_ALL - - mfc0 t0, CP0_CAUSE - mfc0 t1, CP0_STATUS - and t0, t1 - - andi t0, 0xff00 - beqz t0, spurious_interrupt - nop - - /* let k0 keep the current context sp */ - move k0, sp - /* switch to kernel stack */ - li sp, SYSTEM_STACK - - jal rt_interrupt_enter - nop - jal rt_interrupt_dispatch - nop - jal rt_interrupt_leave - nop - - /* switch sp back to thread's context */ - move sp, k0 - - /* - * if rt_thread_switch_interrupt_flag set, jump to - * rt_hw_context_switch_interrupt_do and don't return - */ - la k0, rt_thread_switch_interrupt_flag - lw k1, 0(k0) - beqz k1, spurious_interrupt - nop - sw zero, 0(k0) /* clear flag */ - nop - - /* - * switch to the new thread - */ - la k0, rt_interrupt_from_thread - lw k1, 0(k0) - nop - sw sp, 0(k1) /* store sp in preempted tasks's TCB */ - - la k0, rt_interrupt_to_thread - lw k1, 0(k0) - nop - lw sp, 0(k1) /* get new task's stack pointer */ - j spurious_interrupt - nop - -spurious_interrupt: - RESTORE_ALL_AND_RET - - .set reorder diff --git a/libcpu/mips/xburst/cpu.c b/libcpu/mips/xburst/cpu.c deleted file mode 100644 index 88137535d9..0000000000 --- a/libcpu/mips/xburst/cpu.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * File : cpu.c - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2010-07-09 Bernard first version - * 2010-09-11 Bernard add CPU reset implementation - */ -#include <rtthread.h> -#include <board.h> - -/** - * @addtogroup Ingenic - */ -/*@{*/ - -/** - * this function will reset CPU - * - */ -void rt_hw_cpu_reset() -{ - /* open the watch-dog */ - REG_WDT_TCSR = WDT_TCSR_EXT_EN; - REG_WDT_TCSR |= WDT_TCSR_PRESCALE_1024; - REG_WDT_TDR = 0x03; - REG_WDT_TCNT = 0x00; - REG_WDT_TCER |= WDT_TCER_TCEN; - - rt_kprintf("reboot system...\n"); - while (1); -} - -/** - * this function will shutdown CPU - * - */ -void rt_hw_cpu_shutdown() -{ - rt_kprintf("shutdown...\n"); - - while (1); -} - -/** - * This function finds the first bit set (beginning with the least significant bit) - * in value and return the index of that bit. - * - * Bits are numbered starting at 1 (the least significant bit). A return value of - * zero from any of these functions means that the argument was zero. - * - * @return return the index of the first bit set. If value is 0, then this function - * shall return 0. - */ -int __rt_ffs(int value) -{ - return __builtin_ffs(value); -} - -/*@}*/ diff --git a/libcpu/mips/xburst/exception.c b/libcpu/mips/xburst/exception.c deleted file mode 100644 index aebdf704ea..0000000000 --- a/libcpu/mips/xburst/exception.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * File : exception.c - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - */ -#include <rtthread.h> -#include <rthw.h> -#include "../common/exception.h" -#include "../common/mipsregs.h" - -/** - * @addtogroup Ingenic - */ -/*@{*/ - -/** - * exception handle table - */ -exception_func_t sys_exception_handlers[33]; - -/** - * setup the exception handle - */ -exception_func_t rt_set_except_vector(int n, exception_func_t func) -{ - exception_func_t old_handler = sys_exception_handlers[n]; - - if ((n == 0) || (n > 32) || (!func)) - { - return 0; - } - - sys_exception_handlers[n] = func; - - return old_handler; -} - -void tlb_refill_handler(void) -{ - rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); -} - -void cache_error_handler(void) -{ - rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); -} - -static void unhandled_exception_handle(pt_regs_t *regs) -{ - rt_kprintf("exception happens, epc: 0x%08x\n", regs->cp0_epc); -} - -void install_default_execpt_handle(void) -{ - rt_int32_t i; - - for (i=0; i<33; i++) - sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle; -} - -/*@}*/ - diff --git a/libcpu/mips/xburst/interrupt.c b/libcpu/mips/xburst/interrupt.c deleted file mode 100644 index 337646c735..0000000000 --- a/libcpu/mips/xburst/interrupt.c +++ /dev/null @@ -1,249 +0,0 @@ -/* - * File : interrupt.c - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * 2010-07-09 Bernard first version - * 2013-03-29 aozima Modify the interrupt interface implementations. - */ - -#include <rtthread.h> -#include <rthw.h> -#include <board.h> - -#if defined(RT_USING_JZ4770) || defined(RT_USING_JZ4775) || defined(RT_USING_JZ_M150) || defined(RT_USING_JZ_X1000) -#define INTERRUPTS_MAX 64 -#else -#define INTERRUPTS_MAX 32 -#endif - -extern rt_uint32_t rt_interrupt_nest; -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -static struct rt_irq_desc isr_table[INTERRUPTS_MAX]; - -/** - * @addtogroup Ingenic - */ -/*@{*/ - -static void rt_hw_interrupt_handler(int vector, void *param) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} - -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init(void) -{ - rt_int32_t idx; - - rt_memset(isr_table, 0x00, sizeof(isr_table)); - for (idx = 0; idx < INTERRUPTS_MAX; idx ++) - { - isr_table[idx].handler = rt_hw_interrupt_handler; - } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -/** - * This function will mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_mask(int vector) -{ - /* mask interrupt */ - __intc_mask_irq(vector); -} - -/** - * This function will un-mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_umask(int vector) -{ - __intc_unmask_irq(vector); -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param handler the interrupt service routine to be installed - * @param param the interrupt service function parameter - * @param name the interrupt name - * @return old handler - */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) -{ - rt_isr_handler_t old_handler = RT_NULL; - - if(vector < INTERRUPTS_MAX) - { - old_handler = isr_table[vector].handler; - -#ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); -#endif /* RT_USING_INTERRUPT_INFO */ - isr_table[vector].handler = handler; - isr_table[vector].param = param; - } - - return old_handler; -} - -#if defined(RT_USING_JZ4770) || defined(RT_USING_JZ4775) || defined(RT_USING_JZ_M150) || defined(RT_USING_JZ_X1000) -/* - * fls - find last bit set. - * @word: The word to search - * - * This is defined the same way as ffs. - * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. - */ -rt_inline int fls(int x) -{ - __asm__("clz %0, %1" : "=r" (x) : "r" (x)); - - return 32 - x; -} -#endif - -#include <mipsregs.h> - -void rt_interrupt_dispatch(void *ptreg) -{ - int i; - void *param; - rt_isr_handler_t irq_func; - -#if defined(RT_USING_JZ4770) || defined(RT_USING_JZ4775) || defined(RT_USING_JZ_M150) || defined(RT_USING_JZ_X1000) - int irq = 0, group; - rt_uint32_t intc_ipr0 = 0, intc_ipr1 = 0, vpu_pending = 0; - - rt_uint32_t c0_status, c0_cause; - rt_uint32_t pending_im; - - /* check os timer */ - c0_status = read_c0_status(); - c0_cause = read_c0_cause(); - - pending_im = (c0_cause & ST0_IM) & (c0_status & ST0_IM); - - if (pending_im & CAUSEF_IP3) - { - extern void rt_hw_ost_handler(void); - rt_hw_ost_handler(); - return; - } - - if (pending_im & CAUSEF_IP2) - { - intc_ipr0 = REG_INTC_IPR(0); - intc_ipr1 = REG_INTC_IPR(1); - - if (intc_ipr0) - { - irq = fls(intc_ipr0) - 1; - intc_ipr0 &= ~(1<<irq); - } - else if(intc_ipr1) - { - irq = fls(intc_ipr1) - 1; - intc_ipr1 &= ~(1<<irq); - irq += 32; - } -#ifndef RT_USING_JZ_X1000 /* X1000 has no VPU */ - else - { - __asm__ __volatile__ ( - "mfc0 %0, $13, 0 \n\t" - "nop \n\t" - :"=r"(vpu_pending) - :); - - if(vpu_pending & 0x800) - irq = IRQ_VPU; - else - return; - } -#endif - - if (irq >= INTERRUPTS_MAX) - rt_kprintf("max interrupt, irq=%d\n", irq); - - /* do interrupt */ - irq_func = isr_table[irq].handler; - param = isr_table[irq].param; - (*irq_func)(irq, param); - -#ifdef RT_USING_INTERRUPT_INFO - isr_table[i].counter++; -#endif /* RT_USING_INTERRUPT_INFO */ - - /* ack interrupt */ - __intc_ack_irq(irq); - } - - if (pending_im & CAUSEF_IP0) - rt_kprintf("CAUSEF_IP0\n"); - if (pending_im & CAUSEF_IP1) - rt_kprintf("CAUSEF_IP1\n"); - if (pending_im & CAUSEF_IP4) - rt_kprintf("CAUSEF_IP4\n"); - if (pending_im & CAUSEF_IP5) - rt_kprintf("CAUSEF_IP5\n"); - if (pending_im & CAUSEF_IP6) - rt_kprintf("CAUSEF_IP6\n"); - if (pending_im & CAUSEF_IP7) - rt_kprintf("CAUSEF_IP7\n"); -#else - static rt_uint32_t pending = 0; - - /* the hardware interrupt */ - pending |= REG_INTC_IPR; - if (!pending) return; - - for (i = INTERRUPTS_MAX; i > 0; --i) - { - if ((pending & (1<<i))) - { - pending &= ~(1<<i); - - /* do interrupt */ - irq_func = isr_table[i].handler; - param = isr_table[i].param; - (*irq_func)(i, param); - -#ifdef RT_USING_INTERRUPT_INFO - isr_table[i].counter++; -#endif /* RT_USING_INTERRUPT_INFO */ - - /* ack interrupt */ - __intc_ack_irq(i); - } - } -#endif -} - -/*@}*/ diff --git a/libcpu/mips/xburst/mipscfg.c b/libcpu/mips/xburst/mipscfg.c deleted file mode 100644 index 1e9b0c032f..0000000000 --- a/libcpu/mips/xburst/mipscfg.c +++ /dev/null @@ -1,358 +0,0 @@ -/* - * File : mipscfg.c - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2010-05-27 swkyer first version - */ -#include <rtthread.h> -#include "../common/mipsregs.h" -#include "../common/mipscfg.h" - -mips32_core_cfg_t g_mips_core = -{ - 16, /* icache_line_size */ - 256, /* icache_lines_per_way */ - 4, /* icache_ways */ - 16, /* dcache_line_size */ - 256, /* dcache_lines_per_way */ - 4, /* dcache_ways */ - 16, /* max_tlb_entries */ -}; - -static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) -{ - rt_uint16_t rets = 1; - - while (n--) - rets *= b; - - return rets; -} - -/** - * read core attribute - */ -void mips32_cfg_init(void) -{ - rt_uint16_t val; - rt_uint32_t cp0_config1; - - cp0_config1 = read_c0_config(); - if (cp0_config1 & 0x80000000) - { - cp0_config1 = read_c0_config1(); - - val = (cp0_config1 & (7<<22))>>22; - g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<19))>>19; - g_mips_core.icache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<16))>>16; - g_mips_core.icache_ways = val + 1; - - val = (cp0_config1 & (7<<13))>>13; - g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<10))>>10; - g_mips_core.dcache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<7))>>7; - g_mips_core.dcache_ways = val + 1; - - val = (cp0_config1 & (0x3F<<25))>>25; - g_mips_core.max_tlb_entries = val + 1; - } -} - -#ifdef RT_USING_FINSH -#include <finsh.h> -static void CP0_status_analyze(unsigned long value) -{ - if(value & (1<<26)) - rt_kprintf(" FR"); - if(value & (1<<23)) - rt_kprintf(" PX"); - if(value & (1<<22)) - rt_kprintf(" BEV"); - if(value & (1<<20)) - rt_kprintf(" SR"); - if(value & (1<<19)) - rt_kprintf(" NMI"); - if(value & (1<<20)) - rt_kprintf(" SR"); - if(value & (0xFF<<8)) - rt_kprintf(" IM:0x%02X", (value >> 8) & 0xFF); - if(value & (1<<7)) - rt_kprintf(" KX"); - if(value & (1<<6)) - rt_kprintf(" SX"); - if(value & (1<<5)) - rt_kprintf(" UX"); - if(value & (0x03<<3)) - rt_kprintf(" KSU:0x%02X", (value >> 3) & 0x03); - if(value & (1<<2)) - rt_kprintf(" ERL"); - if(value & (1<<1)) - rt_kprintf(" EXL"); - if(value & (1<<0)) - rt_kprintf(" IE"); -} - -static void CP0_config0_analyze(unsigned long value) -{ - /* [31] M */ - if(value & (1UL<<31)) - rt_kprintf(" M"); - - /* [15] BE */ - if(value & (1<<15)) - rt_kprintf(" big-endian"); - else - rt_kprintf(" little-endian"); - - /* [14:13] AT */ - { - int AT = (value >> 13) & 0x03; - - if(AT == 0) - { - rt_kprintf(" MIPS32"); - } - else if(AT == 1) - { - rt_kprintf(" MIPS64/A32"); - } - else if(AT == 2) - { - rt_kprintf(" MIPS64/A64"); - } - else - { - rt_kprintf(" unkown"); - } - } - - /* [12:10] AR */ - { - int AR = (value >> 10) & 0x07; - - if(AR == 0) - { - rt_kprintf(" R1"); - } - else if(AR == 1) - { - rt_kprintf(" R2"); - } - else - { - rt_kprintf(" reserve"); - } - } - - /* [3] VI */ - if(value & (1UL<<31)) - rt_kprintf(" VI"); - - /* [2:0] K0 */ - { - int K0 = value & 0x07; - - if(K0 == 2) - { - rt_kprintf(" uncached"); - } - else if(K0 == 3) - { - rt_kprintf(" cacheable"); - } - else - { - rt_kprintf(" K0:reserve"); - } - } -} - -static void CP0_config1_analyze(unsigned long value) -{ - /* [31] M */ - if(value & (1UL<<31)) - rt_kprintf(" M"); - - /* [30:25] MMU size */ - { - int MMU_size = (value >> 25) & 0x3F; - rt_kprintf(" TLB:%d", MMU_size + 1); - } - - /* [24:22] IS, [21:19] IL, [18:16] IA */ - { - int IS = (value >> 22) & 0x07; - int IL = (value >> 19) & 0x07; - int IA = (value >> 16) & 0x07; - - IA = IA + 1; - IS = 64 << IS; - IL = 2 << IL; - rt_kprintf(" Icache-%dKB:%dway*%dset*%dbyte", - (IA*IS*IL) >> 10, IA, IS, IL); - } - - /* [15:13] DS, [12:10] DL, [9:7] DA */ - { - int DS = (value >> 13) & 0x07; - int DL = (value >> 10) & 0x07; - int DA = (value >> 7) & 0x07; - - DA = DA + 1; - DS = 64 << DS; - DL = 2 << DL; - rt_kprintf(" Dcache-%dKB:%dway*%dset*%dbyte", - (DA*DS*DL) >> 10, DA, DS, DL); - } - - /* [6] C2 */ - if(value & (1UL<<6)) - rt_kprintf(" CP2"); - - /* [5] MD */ - if(value & (1UL<<5)) - rt_kprintf(" MDMX-ASE"); - - /* [4] PC */ - if(value & (1UL<<4)) - rt_kprintf(" performa-count"); - - /* [3] WR */ - if(value & (1UL<<3)) - rt_kprintf(" Watch"); - - /* [2] CA */ - if(value & (1UL<<2)) - rt_kprintf(" MIPS16e"); - - /* [1] EP */ - if(value & (1UL<<1)) - rt_kprintf(" EJTAG"); - - /* [0] FP */ - if(value & (1UL<<0)) - rt_kprintf(" FPU"); -} - -static void CP0_config2_analyze(unsigned long value) -{ - /* [31] M */ - if(value & (1UL<<31)) - rt_kprintf(" M"); -} - -static void CP0_config3_analyze(unsigned long value) -{ - /* [31] M */ - if(value & (1UL<<31)) - rt_kprintf(" M"); -} - -static void list_mips(void) -{ - unsigned long value; - unsigned long num = 0; - - rt_kprintf("MIPS coprocessor register:\r\n"); - - rt_kprintf("( 0,0) INDEX : 0x%08X\r\n", read_c0_index()); - rt_kprintf("( 1,0) RANDOM : 0x%08X\r\n", read_c0_random()); - rt_kprintf("( 2,0) ENTRYLO0 : 0x%08X\r\n", read_c0_entrylo0()); - rt_kprintf("( 3,0) ENTRYLO1 : 0x%08X\r\n", read_c0_entrylo1()); - rt_kprintf("( 4,0) CONTEXT : 0x%08X\r\n", read_c0_context()); - rt_kprintf("( 5,0) PAGEMASK : 0x%08X\r\n", read_c0_pagemask()); - rt_kprintf("( 6,0) WIRED : 0x%08X\r\n", read_c0_wired()); - rt_kprintf("( 7,0) INFO : 0x%08X\r\n", read_c0_info()); - rt_kprintf("( 8,0) BADVADDR : 0x%08X\r\n", read_c0_badvaddr()); - rt_kprintf("( 9,0) COUNT : 0x%08X\r\n", read_c0_count()); - rt_kprintf("(10,0) ENTRYHI : 0x%08X\r\n", read_c0_entryhi()); - rt_kprintf("(11,0) COMPARE : 0x%08X\r\n", read_c0_compare()); - - value = read_c0_status(); - rt_kprintf("(12,0) STATUS : 0x%08X", value); - CP0_status_analyze(value); - rt_kprintf("\r\n"); - - /* - rt_kprintf("(12,1) INTCTL : 0x%08X\r\n", __read_32bit_c0_register(12, 1)); - rt_kprintf("(12,2) SRSCTL : 0x%08X\r\n", __read_32bit_c0_register(12, 2)); - */ - - rt_kprintf("(13,0) CAUSE : 0x%08X\r\n", read_c0_cause()); - rt_kprintf("(14,0) EPC : 0x%08X\r\n", read_c0_epc()); - rt_kprintf("(15,0) PRID : 0x%08X\r\n", read_c0_prid()); - rt_kprintf("(15,1) EBASE : 0x%08X\r\n", read_c0_ebase()); - - value = read_c0_config(); - rt_kprintf("(16,0) CONFIG : 0x%08X", value); - CP0_config0_analyze(value); - rt_kprintf("\r\n"); - if(value & (1UL << 31)) - { - value = read_c0_config1(); - rt_kprintf("(16,1) CONFIG1 : 0x%08X", value); - CP0_config1_analyze(value); - rt_kprintf("\r\n"); - - if(value & (1UL << 31)) - { - value = read_c0_config2(); - rt_kprintf("(16,2) CONFIG2 : 0x%08X\r\n", value); - CP0_config2_analyze(value); - rt_kprintf("\r\n"); - - if(value & (1UL << 31)) - { - value = read_c0_config3(); - rt_kprintf("(16,3) CONFIG3 : 0x%08X\r\n", value); - CP0_config3_analyze(value); - rt_kprintf("\r\n"); - } - } - } - - rt_kprintf("(17,0) LLADDR : 0x%08X\r\n", __read_32bit_c0_register($17, 0)); - rt_kprintf("(18,0) WATCHLO : 0x%08X\r\n", __read_32bit_c0_register($18, 0)); - rt_kprintf("(19,0) WATCHHI : 0x%08X\r\n", __read_32bit_c0_register($19, 0)); - rt_kprintf("(20,0) XCONTEXT : 0x%08X\r\n", __read_32bit_c0_register($20, 0)); - rt_kprintf("(21,0) FRAMEMASK : 0x%08X\r\n", __read_32bit_c0_register($21, 0)); - rt_kprintf("(22,0) DIAGNOSTIC: 0x%08X\r\n", __read_32bit_c0_register($22, 0)); - rt_kprintf("(23,0) DEBUG : 0x%08X\r\n", __read_32bit_c0_register($23, 0)); - rt_kprintf("(24,0) DEPC : 0x%08X\r\n", __read_32bit_c0_register($24, 0)); - - rt_kprintf("(25,0) PERFCTL0 : 0x%08X\r\n", __read_32bit_c0_register($25, 0)); - rt_kprintf("(26,0) ECC : 0x%08X\r\n", __read_32bit_c0_register($26, 0)); - rt_kprintf("(27,0) CACHEERR : 0x%08X\r\n", __read_32bit_c0_register($27, 0)); - rt_kprintf("(28,0) TAGLO : 0x%08X\r\n", __read_32bit_c0_register($28, 0)); - rt_kprintf("(29,0) TAGHI : 0x%08X\r\n", __read_32bit_c0_register($29, 0)); - - /* - rt_kprintf("(30,0) ERROREPC : 0x%08X\r\n", __read_32bit_c0_register($30, 0)); - rt_kprintf("(31,0) DESAVE : 0x%08X\r\n", __read_32bit_c0_register($31, 0)); - */ - - - rt_kprintf("\r\n"); -} -FINSH_FUNCTION_EXPORT(list_mips, list CPU info) -#endif /* RT_USING_FINSH */ - diff --git a/libcpu/mips/xburst/stack.c b/libcpu/mips/xburst/stack.c deleted file mode 100644 index ceba8b9d9d..0000000000 --- a/libcpu/mips/xburst/stack.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * File : stack.c - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-07-07 Bernard porting to Ingenic CPU - */ -#include <rtthread.h> - -/** - * @addtogroup Ingenic - */ -/*@{*/ - -extern rt_uint32_t cp0_get_cause(void); -extern rt_uint32_t cp0_get_status(void); -extern rt_uint32_t cp0_get_hi(void); -extern rt_uint32_t cp0_get_lo(void); - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - static rt_uint32_t g_sr = 0; - - if (g_sr == 0) - { - g_sr = cp0_get_status(); - g_sr &= 0xfffffffe; - g_sr |= 0x0403; - } - - /** Start at stack top */ - stk = (rt_uint32_t *)stack_addr; - *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ - *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ - *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ - *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ - *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ - *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ - *(--stk) = (rt_uint32_t) texit; /* ra */ - *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ - *(--stk) = (rt_uint32_t) stack_addr; /* sp */ - *(--stk) = (rt_uint32_t) 0x0000001c; /* gp */ - *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ - *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ - *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ - *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ - *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ - *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ - *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ - *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ - *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ - *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ - *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ - *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ - *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ - *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ - *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ - *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ - *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ - *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ - *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ - *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ - *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ - *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ - *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ - *(--stk) = (rt_uint32_t) parameter; /* a0 */ - *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ - *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ - *(--stk) = (rt_uint32_t) 0x00000001; /* at */ - *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - -/*@}*/ diff --git a/libcpu/mips/xburst/stack.h b/libcpu/mips/xburst/stack.h deleted file mode 100644 index 5bb7206c11..0000000000 --- a/libcpu/mips/xburst/stack.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * File : stack.h - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes -*/ - -#ifndef __STACK_H__ -#define __STACK_H__ - -#define SYSTEM_STACK 0x80003fe8 /* the kernel system stack address */ - -#endif diff --git a/libcpu/mips/xburst/start_gcc.S b/libcpu/mips/xburst/start_gcc.S deleted file mode 100644 index 322c2beae8..0000000000 --- a/libcpu/mips/xburst/start_gcc.S +++ /dev/null @@ -1,150 +0,0 @@ -/* - * File : start_gcc.S - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-09-04 bernard porting to Jz47xx - */ - -#include "../common/mips.inc" -#include "../common/stackframe.h" -#include "stack.h" - - .section ".start", "ax" - .set noreorder - - /* the program entry */ - .globl _start -_start: - .set noreorder - la ra, _start - - li t1, 0x00800000 - mtc0 t1, CP0_CAUSE - - /* init cp0 registers. */ - li t0, 0x0000FC00 /* BEV = 0 and mask all interrupt */ - mtc0 t0, CP0_STATUS - - /* setup stack pointer */ - li sp, SYSTEM_STACK - la gp, _gp - - /* init caches, assumes a 4way * 128set * 32byte I/D cache */ - mtc0 zero, CP0_TAGLO /* TAGLO reg */ - mtc0 zero, CP0_TAGHI /* TAGHI reg */ - li t0, 3 /* enable cache for kseg0 accesses */ - mtc0 t0, CP0_CONFIG /* CONFIG reg */ - la t0, 0x80000000 /* an idx op should use an unmappable address */ - ori t1, t0, 0x4000 /* 16kB cache */ - -_cache_loop: - cache 0x8, 0(t0) /* index store icache tag */ - cache 0x9, 0(t0) /* index store dcache tag */ - bne t0, t1, _cache_loop - addiu t0, t0, 0x20 /* 32 bytes per cache line */ - nop - - /* invalidate BTB */ - mfc0 t0, CP0_CONFIG - nop - ori t0, 2 - mtc0 t0, CP0_CONFIG - nop - - /* copy IRAM section */ - la t0, _iramcopy - la t1, _iramstart - la t2, _iramend -_iram_loop: - lw t3, 0(t0) - sw t3, 0(t1) - addiu t1, 4 - bne t1, t2, _iram_loop - addiu t0, 4 - /* clear bss */ - la t0, __bss_start - la t1, __bss_end -_clr_bss_loop: - sw zero, 0(t0) - bne t0, t1, _clr_bss_loop - addiu t0, t0, 4 - - /* jump to RT-Thread RTOS */ - jal rtthread_startup - nop - - /* restart, never die */ - j _start - nop - .set reorder - - .globl cp0_get_cause -cp0_get_cause: - mfc0 v0, CP0_CAUSE - jr ra - nop - - .globl cp0_get_status -cp0_get_status: - mfc0 v0, CP0_STATUS - jr ra - nop - - .globl cp0_get_hi -cp0_get_hi: - mfhi v0 - jr ra - nop - - .globl cp0_get_lo -cp0_get_lo: - mflo v0 - jr ra - nop - - .extern tlb_refill_handler - .extern cache_error_handler - - /* Exception Handler */ - /* 0x0 - TLB refill handler */ - .section .vectors.1, "ax", %progbits - j tlb_refill_handler - nop - - /* 0x100 - Cache error handler */ - .section .vectors.2, "ax", %progbits - j cache_error_handler - nop - - /* 0x180 - Exception/Interrupt handler */ - .section .vectors.3, "ax", %progbits - j _general_exception_handler - nop - - /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */ - .section .vectors.4, "ax", %progbits - j _irq_handler - nop - - .section .vectors, "ax", %progbits - .extern mips_irq_handle - - /* general exception handler */ -_general_exception_handler: - .set noreorder - mfc0 k1, CP0_CAUSE - andi k1, k1, 0x7c - srl k1, k1, 2 - lw k0, sys_exception_handlers(k1) - jr k0 - nop - .set reorder - - /* interrupt handler */ -_irq_handler: - .set noreorder - la k0, mips_irq_handle - jr k0 - nop - .set reorder diff --git a/libcpu/mips/xburst/x1000.h b/libcpu/mips/xburst/x1000.h deleted file mode 100644 index 71d11783a3..0000000000 --- a/libcpu/mips/xburst/x1000.h +++ /dev/null @@ -1,329 +0,0 @@ -/* - * File : x1000.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2015-11-19 Urey the first version - */ - -#ifndef X1000_H__ -#define X1000_H__ - -#ifndef __ASSEMBLY__ - -// typedef unsigned int size_t; -#define u64 unsigned long long -#define u32 unsigned int -#define u16 unsigned short -#define u8 unsigned char - -#define U64 unsigned long long -#define U32 unsigned int -#define U16 unsigned short -#define U8 unsigned char - -#define S64 signed long long -#define S32 int -#define S16 short int -#define S8 signed char - -#define cache_unroll(base,op) \ - __asm__ __volatile__(" \ - .set noreorder; \ - .set mips3; \ - cache %1, (%0); \ - .set mips0; \ - .set reorder" \ - : \ - : "r" (base), \ - "i" (op)); - -/* cpu pipeline flush */ -static inline void jz_sync(void) -{ - __asm__ volatile ("sync"); -} - -static inline void writeb(u8 value, u32 address) -{ - *((volatile u8 *) address) = value; -} -static inline void writew( u16 value, u32 address) -{ - *((volatile u16 *) address) = value; -} -static inline void writel(u32 value, u32 address) -{ - *((volatile u32 *) address) = value; -} - -static inline u8 readb(u32 address) -{ - return *((volatile u8 *)address); -} - -static inline u16 readw(u32 address) -{ - return *((volatile u16 *)address); -} - -static inline u32 readl(u32 address) -{ - return *((volatile u32 *)address); -} - -static inline void jz_writeb(u32 address, u8 value) -{ - *((volatile u8 *)address) = value; -} - -static inline void jz_writew(u32 address, u16 value) -{ - *((volatile u16 *)address) = value; -} - -static inline void jz_writel(u32 address, u32 value) -{ - *((volatile u32 *)address) = value; -} - -static inline u8 jz_readb(u32 address) -{ - return *((volatile u8 *)address); -} - -static inline u16 jz_readw(u32 address) -{ - return *((volatile u16 *)address); -} - -static inline u32 jz_readl(u32 address) -{ - return *((volatile u32 *)address); -} - -#define REG8(addr) *((volatile u8 *)(addr)) -#define REG16(addr) *((volatile u16 *)(addr)) -#define REG32(addr) *((volatile u32 *)(addr)) - -#define BIT(n) (0x01u << (n)) - -#else - -#define REG8(addr) (addr) -#define REG16(addr) (addr) -#define REG32(addr) (addr) - -#endif /* !ASSEMBLY */ - - -//---------------------------------------------------------------------- -// Register Definitions -// -/* AHB0 BUS Devices Base */ -#define HARB0_BASE 0xB3000000 -#define EMC_BASE 0xB3010000 -#define DDRC_BASE 0xB3020000 -#define MDMAC_BASE 0xB3030000 -#define LCD_BASE 0xB3050000 -#define TVE_BASE 0xB3050000 -#define SLCD_BASE 0xB3050000 -#define CIM_BASE 0xB3060000 -#define IPU_BASE 0xB3080000 -/* AHB1 BUS Devices Base */ -#define HARB1_BASE 0xB3200000 -#define DMAGP0_BASE 0xB3210000 -#define DMAGP1_BASE 0xB3220000 -#define DMAGP2_BASE 0xB3230000 -#define MC_BASE 0xB3250000 -#define ME_BASE 0xB3260000 -#define DEBLK_BASE 0xB3270000 -#define IDCT_BASE 0xB3280000 -#define CABAC_BASE 0xB3290000 -#define TCSM0_BASE 0xB32B0000 -#define TCSM1_BASE 0xB32C0000 -#define SRAM_BASE 0xB32D0000 -/* AHB2 BUS Devices Base */ -#define HARB2_BASE 0xB3400000 -#define NEMC_BASE 0xB3410000 -#define DMAC_BASE 0xB3420000 -#define UHC_BASE 0xB3430000 -#define UDC_BASE 0xB3440000 -#define GPS_BASE 0xB3480000 -#define ETHC_BASE 0xB34B0000 -#define BCH_BASE 0xB34D0000 -#define MSC0_BASE 0xB3450000 -#define MSC1_BASE 0xB3460000 -#define MSC2_BASE 0xB3470000 - -/* APB BUS Devices Base */ -#define CPM_BASE 0xB0000000 -#define INTC_BASE 0xB0001000 -#define TCU_BASE 0xB0002000 -#define WDT_BASE 0xB0002000 -#define OST_BASE 0xB2000000 /* OS Timer */ -#define RTC_BASE 0xB0003000 -#define GPIO_BASE 0xB0010000 -#define AIC_BASE 0xB0020000 -#define DMIC_BASE 0xB0021000 -#define ICDC_BASE 0xB0020000 -#define UART0_BASE 0xB0030000 -#define UART1_BASE 0xB0031000 -#define UART2_BASE 0xB0032000 -#define UART3_BASE 0xB0033000 -#define SCC_BASE 0xB0040000 -#define SSI0_BASE 0xB0043000 -#define SSI1_BASE 0xB0044000 -#define SSI2_BASE 0xB0045000 -#define I2C0_BASE 0xB0050000 -#define I2C1_BASE 0xB0051000 -#define PS2_BASE 0xB0060000 -#define SADC_BASE 0xB0070000 -#define OWI_BASE 0xB0072000 -#define TSSI_BASE 0xB0073000 - -/* NAND CHIP Base Address*/ -#define NEMC_CS1_IOBASE 0Xbb000000 -#define NEMC_CS2_IOBASE 0Xba000000 -#define NEMC_CS3_IOBASE 0Xb9000000 -#define NEMC_CS4_IOBASE 0Xb8000000 -#define NEMC_CS5_IOBASE 0Xb7000000 -#define NEMC_CS6_IOBASE 0Xb6000000 - -/********************************************************************************************************* -** WDT -*********************************************************************************************************/ -#define WDT_TDR (WDT_BASE + 0x00) -#define WDT_TCER (WDT_BASE + 0x04) -#define WDT_TCNT (WDT_BASE + 0x08) -#define WDT_TCSR (WDT_BASE + 0x0C) - -#define REG_WDT_TDR REG16(WDT_TDR) -#define REG_WDT_TCER REG8(WDT_TCER) -#define REG_WDT_TCNT REG16(WDT_TCNT) -#define REG_WDT_TCSR REG16(WDT_TCSR) - -#define WDT_TSCR_WDTSC (1 << 16) - -#define WDT_TCSR_PRESCALE_1 (0 << 3) -#define WDT_TCSR_PRESCALE_4 (1 << 3) -#define WDT_TCSR_PRESCALE_16 (2 << 3) -#define WDT_TCSR_PRESCALE_64 (3 << 3) -#define WDT_TCSR_PRESCALE_256 (4 << 3) -#define WDT_TCSR_PRESCALE_1024 (5 << 3) - -#define WDT_TCSR_EXT_EN (1 << 2) -#define WDT_TCSR_RTC_EN (1 << 1) -#define WDT_TCSR_PCK_EN (1 << 0) - -#define WDT_TCER_TCEN (1 << 0) - -/********************************************************************************************************* -** �ж�Դ -*********************************************************************************************************/ -/* INTC (Interrupt Controller) */ -#define INTC_ISR(n) (INTC_BASE + 0x00 + (n) * 0x20) -#define INTC_IMR(n) (INTC_BASE + 0x04 + (n) * 0x20) -#define INTC_IMSR(n) (INTC_BASE + 0x08 + (n) * 0x20) -#define INTC_IMCR(n) (INTC_BASE + 0x0c + (n) * 0x20) -#define INTC_IPR(n) (INTC_BASE + 0x10 + (n) * 0x20) - -#define REG_INTC_ISR(n) REG32(INTC_ISR((n))) -#define REG_INTC_IMR(n) REG32(INTC_IMR((n))) -#define REG_INTC_IMSR(n) REG32(INTC_IMSR((n))) -#define REG_INTC_IMCR(n) REG32(INTC_IMCR((n))) -#define REG_INTC_IPR(n) REG32(INTC_IPR((n))) - -// interrupt controller interrupts -#define IRQ_DMIC 0 -#define IRQ_AIC0 1 -#define IRQ_RESERVED2 2 -#define IRQ_RESERVED3 3 -#define IRQ_RESERVED4 4 -#define IRQ_RESERVED5 5 -#define IRQ_RESERVED6 6 -#define IRQ_SFC 7 -#define IRQ_SSI0 8 -#define IRQ_RESERVED9 9 -#define IRQ_PDMA 10 -#define IRQ_PDMAD 11 -#define IRQ_RESERVED12 12 -#define IRQ_RESERVED13 13 -#define IRQ_GPIO3 14 -#define IRQ_GPIO2 15 -#define IRQ_GPIO1 16 -#define IRQ_GPIO0 17 -#define IRQ_RESERVED18 18 -#define IRQ_RESERVED19 19 -#define IRQ_RESERVED20 20 -#define IRQ_OTG 21 -#define IRQ_RESERVED22 22 -#define IRQ_AES 23 -#define IRQ_RESERVED24 24 -#define IRQ_TCU2 25 -#define IRQ_TCU1 26 -#define IRQ_TCU0 27 -#define IRQ_RESERVED28 28 -#define IRQ_RESERVED29 29 -#define IRQ_CIM 30 -#define IRQ_LCD 31 -#define IRQ_RTC 32 -#define IRQ_RESERVED33 33 -#define IRQ_RESERVED34 34 -#define IRQ_RESERVED35 35 -#define IRQ_MSC1 36 -#define IRQ_MSC0 37 -#define IRQ_SCC 38 -#define IRQ_RESERVED39 39 -#define IRQ_PCM0 40 -#define IRQ_RESERVED41 41 -#define IRQ_RESERVED42 42 -#define IRQ_RESERVED43 43 -#define IRQ_HARB2 44 -#define IRQ_RESERVED45 45 -#define IRQ_HARB0 46 -#define IRQ_CPM 47 -#define IRQ_RESERVED48 48 -#define IRQ_UART2 49 -#define IRQ_UART1 50 -#define IRQ_UART0 51 -#define IRQ_DDR 52 -#define IRQ_RESERVED53 53 -#define IRQ_EFUSE 54 -#define IRQ_MAC 55 -#define IRQ_RESERVED56 56 -#define IRQ_RESERVED57 57 -#define IRQ_I2C2 58 -#define IRQ_I2C1 59 -#define IRQ_I2C0 60 -#define IRQ_PDMAM 61 -#define IRQ_JPEG 62 -#define IRQ_RESERVED63 63 - -#define IRQ_INTC_MAX 63 - -#ifndef __ASSEMBLY__ - -#define __intc_unmask_irq(n) (REG_INTC_IMCR((n)/32) = (1 << ((n)%32))) -#define __intc_mask_irq(n) (REG_INTC_IMSR((n)/32) = (1 << ((n)%32))) -#define __intc_ack_irq(n) (REG_INTC_IPR((n)/32) = (1 << ((n)%32))) /* A dummy ack, as the Pending Register is Read Only. Should we remove __intc_ack_irq() */ - -#endif /* !__ASSEMBLY__ */ - -#endif /* _JZ_M150_H_ */ |