diff options
Diffstat (limited to 'libcpu/ppc')
| -rw-r--r-- | libcpu/ppc/common/ptrace.h | 200 | ||||
| -rw-r--r-- | libcpu/ppc/common/stack.c | 176 | ||||
| -rw-r--r-- | libcpu/ppc/ppc405/cache.h | 46 | ||||
| -rw-r--r-- | libcpu/ppc/ppc405/context.h | 96 | ||||
| -rw-r--r-- | libcpu/ppc/ppc405/context_gcc.S | 420 | ||||
| -rw-r--r-- | libcpu/ppc/ppc405/include/asm/ppc405.h | 1960 | ||||
| -rw-r--r-- | libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h | 122 | ||||
| -rw-r--r-- | libcpu/ppc/ppc405/include/asm/ppc4xx.h | 268 | ||||
| -rw-r--r-- | libcpu/ppc/ppc405/include/asm/ppc_defs.h | 146 | ||||
| -rw-r--r-- | libcpu/ppc/ppc405/include/asm/processor.h | 2476 | ||||
| -rw-r--r-- | libcpu/ppc/ppc405/include/asm/ptrace.h | 214 | ||||
| -rw-r--r-- | libcpu/ppc/ppc405/include/asm/types.h | 148 | ||||
| -rw-r--r-- | libcpu/ppc/ppc405/include/config.h | 116 | ||||
| -rw-r--r-- | libcpu/ppc/ppc405/interrupt.c | 266 | ||||
| -rw-r--r-- | libcpu/ppc/ppc405/io.h | 186 | ||||
| -rw-r--r-- | libcpu/ppc/ppc405/serial.c | 638 | ||||
| -rw-r--r-- | libcpu/ppc/ppc405/traps.c | 416 |
17 files changed, 3947 insertions, 3947 deletions
diff --git a/libcpu/ppc/common/ptrace.h b/libcpu/ppc/common/ptrace.h index 860d1a7c60..d60e7fdcef 100644 --- a/libcpu/ppc/common/ptrace.h +++ b/libcpu/ppc/common/ptrace.h @@ -1,100 +1,100 @@ -#ifndef _PPC_PTRACE_H
-#define _PPC_PTRACE_H
-
-/*
- * This struct defines the way the registers are stored on the
- * kernel stack during a system call or other kernel entry.
- *
- * this should only contain volatile regs
- * since we can keep non-volatile in the thread_struct
- * should set this up when only volatiles are saved
- * by intr code.
- *
- * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
- * that the overall structure is a multiple of 16 bytes in length.
- *
- * Note that the offsets of the fields in this struct correspond with
- * the PT_* values below. This simplifies arch/ppc/kernel/ptrace.c.
- */
-
-#ifndef __ASSEMBLY__
-#define PPC_REG unsigned long
-
-struct pt_regs {
- PPC_REG gpr[32];
- PPC_REG nip;
- PPC_REG msr;
- PPC_REG orig_gpr3; /* Used for restarting system calls */
- PPC_REG ctr;
- PPC_REG link;
- PPC_REG xer;
- PPC_REG ccr;
- PPC_REG mq; /* 601 only (not used at present) */
- /* Used on APUS to hold IPL value. */
- PPC_REG trap; /* Reason for being here */
- PPC_REG dar; /* Fault registers */
- PPC_REG dsisr;
- PPC_REG result; /* Result of a system call */
-}__attribute__((packed)) CELL_STACK_FRAME_t;
-#endif
-
-#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */
-
-/* Size of stack frame allocated when calling signal handler. */
-#define __SIGNAL_FRAMESIZE 64
-
-#define instruction_pointer(regs) ((regs)->nip)
-#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
-
-/*
- * Offsets used by 'ptrace' system call interface.
- * These can't be changed without breaking binary compatibility
- * with MkLinux, etc.
- */
-#define PT_R0 0
-#define PT_R1 1
-#define PT_R2 2
-#define PT_R3 3
-#define PT_R4 4
-#define PT_R5 5
-#define PT_R6 6
-#define PT_R7 7
-#define PT_R8 8
-#define PT_R9 9
-#define PT_R10 10
-#define PT_R11 11
-#define PT_R12 12
-#define PT_R13 13
-#define PT_R14 14
-#define PT_R15 15
-#define PT_R16 16
-#define PT_R17 17
-#define PT_R18 18
-#define PT_R19 19
-#define PT_R20 20
-#define PT_R21 21
-#define PT_R22 22
-#define PT_R23 23
-#define PT_R24 24
-#define PT_R25 25
-#define PT_R26 26
-#define PT_R27 27
-#define PT_R28 28
-#define PT_R29 29
-#define PT_R30 30
-#define PT_R31 31
-
-#define PT_NIP 32
-#define PT_MSR 33
-#define PT_ORIG_R3 34
-#define PT_CTR 35
-#define PT_LNK 36
-#define PT_XER 37
-#define PT_CCR 38
-#define PT_MQ 39
-
-#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */
-#define PT_FPR31 (PT_FPR0 + 2*31)
-#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
-
-#endif
+#ifndef _PPC_PTRACE_H +#define _PPC_PTRACE_H + +/* + * This struct defines the way the registers are stored on the + * kernel stack during a system call or other kernel entry. + * + * this should only contain volatile regs + * since we can keep non-volatile in the thread_struct + * should set this up when only volatiles are saved + * by intr code. + * + * Since this is going on the stack, *CARE MUST BE TAKEN* to insure + * that the overall structure is a multiple of 16 bytes in length. + * + * Note that the offsets of the fields in this struct correspond with + * the PT_* values below. This simplifies arch/ppc/kernel/ptrace.c. + */ + +#ifndef __ASSEMBLY__ +#define PPC_REG unsigned long + +struct pt_regs { + PPC_REG gpr[32]; + PPC_REG nip; + PPC_REG msr; + PPC_REG orig_gpr3; /* Used for restarting system calls */ + PPC_REG ctr; + PPC_REG link; + PPC_REG xer; + PPC_REG ccr; + PPC_REG mq; /* 601 only (not used at present) */ + /* Used on APUS to hold IPL value. */ + PPC_REG trap; /* Reason for being here */ + PPC_REG dar; /* Fault registers */ + PPC_REG dsisr; + PPC_REG result; /* Result of a system call */ +}__attribute__((packed)) CELL_STACK_FRAME_t; +#endif + +#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ + +/* Size of stack frame allocated when calling signal handler. */ +#define __SIGNAL_FRAMESIZE 64 + +#define instruction_pointer(regs) ((regs)->nip) +#define user_mode(regs) (((regs)->msr & MSR_PR) != 0) + +/* + * Offsets used by 'ptrace' system call interface. + * These can't be changed without breaking binary compatibility + * with MkLinux, etc. + */ +#define PT_R0 0 +#define PT_R1 1 +#define PT_R2 2 +#define PT_R3 3 +#define PT_R4 4 +#define PT_R5 5 +#define PT_R6 6 +#define PT_R7 7 +#define PT_R8 8 +#define PT_R9 9 +#define PT_R10 10 +#define PT_R11 11 +#define PT_R12 12 +#define PT_R13 13 +#define PT_R14 14 +#define PT_R15 15 +#define PT_R16 16 +#define PT_R17 17 +#define PT_R18 18 +#define PT_R19 19 +#define PT_R20 20 +#define PT_R21 21 +#define PT_R22 22 +#define PT_R23 23 +#define PT_R24 24 +#define PT_R25 25 +#define PT_R26 26 +#define PT_R27 27 +#define PT_R28 28 +#define PT_R29 29 +#define PT_R30 30 +#define PT_R31 31 + +#define PT_NIP 32 +#define PT_MSR 33 +#define PT_ORIG_R3 34 +#define PT_CTR 35 +#define PT_LNK 36 +#define PT_XER 37 +#define PT_CCR 38 +#define PT_MQ 39 + +#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ +#define PT_FPR31 (PT_FPR0 + 2*31) +#define PT_FPSCR (PT_FPR0 + 2*32 + 1) + +#endif diff --git a/libcpu/ppc/common/stack.c b/libcpu/ppc/common/stack.c index 05ae5abb80..570e9ba046 100644 --- a/libcpu/ppc/common/stack.c +++ b/libcpu/ppc/common/stack.c @@ -1,88 +1,88 @@ -/*
- * File : stack.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2011-02-14 Fred first implementation for
- */
-
-#include <rtthread.h>
-
-/**
- * @addtogroup PowerPC
- */
-/*@{*/
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
- rt_uint8_t *stack_addr, void *texit)
-{
- unsigned long *stk;
- rt_uint32_t msr;
-
- __asm__ __volatile__("mfmsr %0\n" : "=r" (msr));
- msr |= 0x00028000;
-
- stk = (unsigned long *)stack_addr;
- --stk;
- *(--stk) = msr; /* srr0: machine status register */
- *(--stk) = (rt_uint32_t)tentry; /* srr1: entry point */
- *(--stk) = (rt_uint32_t)texit; /* lr: link register */
- *(--stk) = 0x0F0F0F0F; /* ctr: counter register */
- *(--stk) = 0x0F0F0F0F; /* xer: fixed-point exception register */
- *(--stk) = 0x0F0F0F0F; /* cr : condition register */
- *(--stk) = 0x00; /* usprg0 */
-
- *(--stk) = 0x31; /* r31 */
- *(--stk) = 0x30; /* r30 */
- *(--stk) = 0x29; /* r29 */
- *(--stk) = 0x28; /* r28 */
- *(--stk) = 0x27; /* r27 */
- *(--stk) = 0x26; /* r26 */
- *(--stk) = 0x25; /* r25 */
- *(--stk) = 0x24; /* r24 */
- *(--stk) = 0x23; /* r23 */
- *(--stk) = 0x22; /* r22 */
- *(--stk) = 0x21; /* r21 */
- *(--stk) = 0x20; /* r20 */
- *(--stk) = 0x19; /* r19 */
- *(--stk) = 0x18; /* r18 */
- *(--stk) = 0x17; /* r17 */
- *(--stk) = 0x16; /* r16 */
- *(--stk) = 0x15; /* r15 */
- *(--stk) = 0x14; /* r14 */
- *(--stk) = 0x13; /* r13: thread id */
- *(--stk) = 0x12; /* r12 */
- *(--stk) = 0x11; /* r11 */
- *(--stk) = 0x10; /* r10 */
- *(--stk) = 0x09; /* r09 */
- *(--stk) = 0x08; /* r08 */
- *(--stk) = 0x07; /* r07 */
- *(--stk) = 0x06; /* r06 */
- *(--stk) = 0x05; /* r05 */
- *(--stk) = 0x04; /* r04 */
- *(--stk) = (rt_uint32_t)parameter; /* r03: parameter and return */
- *(--stk) = 0x02; /* r02: toc */
- /* r01: sp */
- *(--stk) = 0x0; /* r00 */
-
- /* return task's current stack address */
- return (rt_uint8_t *)stk;
-}
-
-/*@}*/
+/* + * File : stack.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006-2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-02-14 Fred first implementation for + */ + +#include <rtthread.h> + +/** + * @addtogroup PowerPC + */ +/*@{*/ + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + unsigned long *stk; + rt_uint32_t msr; + + __asm__ __volatile__("mfmsr %0\n" : "=r" (msr)); + msr |= 0x00028000; + + stk = (unsigned long *)stack_addr; + --stk; + *(--stk) = msr; /* srr0: machine status register */ + *(--stk) = (rt_uint32_t)tentry; /* srr1: entry point */ + *(--stk) = (rt_uint32_t)texit; /* lr: link register */ + *(--stk) = 0x0F0F0F0F; /* ctr: counter register */ + *(--stk) = 0x0F0F0F0F; /* xer: fixed-point exception register */ + *(--stk) = 0x0F0F0F0F; /* cr : condition register */ + *(--stk) = 0x00; /* usprg0 */ + + *(--stk) = 0x31; /* r31 */ + *(--stk) = 0x30; /* r30 */ + *(--stk) = 0x29; /* r29 */ + *(--stk) = 0x28; /* r28 */ + *(--stk) = 0x27; /* r27 */ + *(--stk) = 0x26; /* r26 */ + *(--stk) = 0x25; /* r25 */ + *(--stk) = 0x24; /* r24 */ + *(--stk) = 0x23; /* r23 */ + *(--stk) = 0x22; /* r22 */ + *(--stk) = 0x21; /* r21 */ + *(--stk) = 0x20; /* r20 */ + *(--stk) = 0x19; /* r19 */ + *(--stk) = 0x18; /* r18 */ + *(--stk) = 0x17; /* r17 */ + *(--stk) = 0x16; /* r16 */ + *(--stk) = 0x15; /* r15 */ + *(--stk) = 0x14; /* r14 */ + *(--stk) = 0x13; /* r13: thread id */ + *(--stk) = 0x12; /* r12 */ + *(--stk) = 0x11; /* r11 */ + *(--stk) = 0x10; /* r10 */ + *(--stk) = 0x09; /* r09 */ + *(--stk) = 0x08; /* r08 */ + *(--stk) = 0x07; /* r07 */ + *(--stk) = 0x06; /* r06 */ + *(--stk) = 0x05; /* r05 */ + *(--stk) = 0x04; /* r04 */ + *(--stk) = (rt_uint32_t)parameter; /* r03: parameter and return */ + *(--stk) = 0x02; /* r02: toc */ + /* r01: sp */ + *(--stk) = 0x0; /* r00 */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + +/*@}*/ diff --git a/libcpu/ppc/ppc405/cache.h b/libcpu/ppc/ppc405/cache.h index 8157591373..930124547b 100644 --- a/libcpu/ppc/ppc405/cache.h +++ b/libcpu/ppc/ppc405/cache.h @@ -1,23 +1,23 @@ -#ifndef __CACHE_H__
-#define __CACHE_H__
-
-#include <asm/processor.h>
-
-#if !defined(__ASSEMBLY__)
-void flush_dcache_range(unsigned long start, unsigned long stop);
-void clean_dcache_range(unsigned long start, unsigned long stop);
-void invalidate_dcache_range(unsigned long start, unsigned long stop);
-void flush_dcache(void);
-void invalidate_dcache(void);
-void invalidate_icache(void);
-
-void icache_enable(void);
-void icache_disable(void);
-unsigned long icache_status(void);
-
-void dcache_enable(void);
-void dcache_disable(void);
-unsigned long dcache_status(void);
-#endif
-
-#endif
+#ifndef __CACHE_H__ +#define __CACHE_H__ + +#include <asm/processor.h> + +#if !defined(__ASSEMBLY__) +void flush_dcache_range(unsigned long start, unsigned long stop); +void clean_dcache_range(unsigned long start, unsigned long stop); +void invalidate_dcache_range(unsigned long start, unsigned long stop); +void flush_dcache(void); +void invalidate_dcache(void); +void invalidate_icache(void); + +void icache_enable(void); +void icache_disable(void); +unsigned long icache_status(void); + +void dcache_enable(void); +void dcache_disable(void); +unsigned long dcache_status(void); +#endif + +#endif diff --git a/libcpu/ppc/ppc405/context.h b/libcpu/ppc/ppc405/context.h index 54dadbc215..8b4d55d698 100644 --- a/libcpu/ppc/ppc405/context.h +++ b/libcpu/ppc/ppc405/context.h @@ -1,48 +1,48 @@ -#ifndef __CONTEXT_H__
-#define __CONTEXT_H__
-
-#define MSR_ME (1<<12) /* Machine Check Enable */
-#define MSR_EE (1<<15) /* External Interrupt Enable */
-#define MSR_CE (1<<17) /* Critical Interrupt Enable */
-
-#define GPR0 0
-#define GPR2 4
-#define GPR3 8
-#define GPR4 12
-#define GPR5 16
-#define GPR6 20
-#define GPR7 24
-#define GPR8 28
-#define GPR9 32
-#define GPR10 36
-#define GPR11 40
-#define GPR12 44
-#define GPR13 48
-#define GPR14 52
-#define GPR15 56
-#define GPR16 60
-#define GPR17 64
-#define GPR18 68
-#define GPR19 72
-#define GPR20 76
-#define GPR21 80
-#define GPR22 84
-#define GPR23 88
-#define GPR24 92
-#define GPR25 96
-#define GPR26 100
-#define GPR27 104
-#define GPR28 108
-#define GPR29 112
-#define GPR30 116
-#define GPR31 120
-#define USPRG0 (GPR31 + 4)
-#define CR (USPRG0 + 4)
-#define XER (CR + 4)
-#define CTR (XER + 4)
-#define LR (CTR + 4)
-#define SRR0 (LR + 4)
-#define SRR1 (SRR0 + 4)
-#define STACK_FRAME_SIZE (SRR1 + 4)
-
-#endif
+#ifndef __CONTEXT_H__ +#define __CONTEXT_H__ + +#define MSR_ME (1<<12) /* Machine Check Enable */ +#define MSR_EE (1<<15) /* External Interrupt Enable */ +#define MSR_CE (1<<17) /* Critical Interrupt Enable */ + +#define GPR0 0 +#define GPR2 4 +#define GPR3 8 +#define GPR4 12 +#define GPR5 16 +#define GPR6 20 +#define GPR7 24 +#define GPR8 28 +#define GPR9 32 +#define GPR10 36 +#define GPR11 40 +#define GPR12 44 +#define GPR13 48 +#define GPR14 52 +#define GPR15 56 +#define GPR16 60 +#define GPR17 64 +#define GPR18 68 +#define GPR19 72 +#define GPR20 76 +#define GPR21 80 +#define GPR22 84 +#define GPR23 88 +#define GPR24 92 +#define GPR25 96 +#define GPR26 100 +#define GPR27 104 +#define GPR28 108 +#define GPR29 112 +#define GPR30 116 +#define GPR31 120 +#define USPRG0 (GPR31 + 4) +#define CR (USPRG0 + 4) +#define XER (CR + 4) +#define CTR (XER + 4) +#define LR (CTR + 4) +#define SRR0 (LR + 4) +#define SRR1 (SRR0 + 4) +#define STACK_FRAME_SIZE (SRR1 + 4) + +#endif diff --git a/libcpu/ppc/ppc405/context_gcc.S b/libcpu/ppc/ppc405/context_gcc.S index e43f96d801..f6a53dce3d 100644 --- a/libcpu/ppc/ppc405/context_gcc.S +++ b/libcpu/ppc/ppc405/context_gcc.S @@ -1,210 +1,210 @@ -#include "context.h"
-#define SPRG0 0x110 /* Special Purpose Register General 0 */
-#define SPRG1 0x111 /* Special Purpose Register General 1 */
-
- .globl rt_hw_interrupt_disable
- .globl rt_hw_interrupt_enable
- .globl rt_hw_context_switch
- .globl rt_hw_context_switch_to
- .globl rt_hw_context_switch_interrupt
- .globl rt_hw_systemcall_entry
-
-/*
- * rt_base_t rt_hw_interrupt_disable();
- * return the interrupt status and disable interrupt
- */
-#if 0
-rt_hw_interrupt_disable:
- mfmsr r3 /* Disable interrupts */
- li r4,0
- ori r4,r4,MSR_EE
- andc r4,r4,r3
- SYNC /* Some chip revs need this... */
- mtmsr r4
- SYNC
- blr
-#else
-rt_hw_interrupt_disable:
- addis r4, r0, 0xFFFD
- ori r4, r4, 0x7FFF
- mfmsr r3
- and r4, r4, 3 /* Clear bits 14 and 16, corresponding to... */
- mtmsr r4 /* ...critical and non-critical interrupts */
- blr
-#endif
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level);
- * restore interrupt
- */
-rt_hw_interrupt_enable:
- mtmsr r3
- SYNC
- blr
-
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
- * r3 --> from
- * r4 --> to
- *
- * r1: stack pointer
- */
-rt_hw_systemcall_entry:
- mtspr SPRG0,r3 /* save r3 to SPRG0 */
- mtspr SPRG1,r4 /* save r4 to SPRG1 */
-
- lis r3,rt_thread_switch_interrput_flag@h
- ori r3,r3,rt_thread_switch_interrput_flag@l
- lwz r4,0(r3)
- cmpi cr0,0,r4,0x0 /* whether is 0 */
- beq _no_switch /* no switch, exit */
- li r4,0x0 /* set rt_thread_switch_interrput_flag to 0 */
- stw r4,0(r3)
-
- /* load from thread to r3 */
- lis r3,rt_interrupt_from_thread@h /* set rt_interrupt_from_thread */
- ori r3,r3,rt_interrupt_from_thread@l
- lwz r3,0(r3)
-
- cmpi cr0,0,r3,0x0 /* whether is 0 */
- beq _restore /* it's first switch, goto _restore */
-
- /* save r1:sp to thread[from] stack pointer */
- subi r1, r1, STACK_FRAME_SIZE
- stw r1, 0(r3)
-
- /* restore r3, r4 from SPRG */
- mfspr r3,SPRG0
- mfspr r4,SPRG0
-
- /* save registers */
- stw r0,GPR0(r1) /* save general purpose registers 0 */
- stmw r2,GPR2(r1) /* save general purpose registers 2-31 */
-
- mfusprg0 r0 /* save usprg0 */
- stw r0,USPRG0(r1)
- mfcr r0, /* save cr */
- stw r0,CR(r1)
- mfxer r0 /* save xer */
- stw r0,XER(r1)
- mfctr r0 /* save ctr */
- stw r0,CTR(r1)
- mflr r0 /* save lr */
- stw r0, LR(r1)
-
- mfsrr0 r0 /* save SRR0 and SRR1 */
- stw r0,SRR0(r1)
- mfsrr1 r0
- stw r0,SRR1(r1)
-
-_restore:
- /* get thread[to] stack pointer */
- lis r4,rt_interrupt_to_thread@h
- ori r4,r4,rt_interrupt_to_thread@l
- lwz r1,0(r4)
- lwz r1,0(r1)
-
- lwz r0,SRR1(r1) /* restore SRR1 and SRR0 */
- mtsrr1 r0
- lwz r0,SRR0(r1)
- mtsrr0 r0
-
- lwz r0,LR(r1) /* restore lr */
- mtlr r0
- lwz r0,CTR(r1) /* restore ctr */
- mtctr r0
- lwz r0,XER(r1) /* restore xer */
- mtxer r0
- lwz r0,CR(r1) /* restore cr */
- mtcr r0
- lwz r0,USPRG0(r1) /* restore usprg0 */
- // mtusprg0 r0
-
- lmw r2, GPR2(r1) /* restore general register */
- lwz r0,GPR0(r1)
- addi r1, r1, STACK_FRAME_SIZE
- /* RFI will restore status register and thus the correct priority*/
- rfi
-
-_no_switch:
- /* restore r3, r4 from SPRG */
- mfspr r3,SPRG0
- mfspr r4,SPRG0
- rfi
-
- /* void rt_hw_context_switch_to(to); */
- .globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
- /* set rt_thread_switch_interrput_flag = 1 */
- lis r5,rt_thread_switch_interrput_flag@h
- ori r5,r5,rt_thread_switch_interrput_flag@l
- li r6, 0x01
- stw r6,0(r5)
-
- /* set rt_interrupt_from_thread = 0 */
- lis r5,rt_interrupt_from_thread@h
- ori r5,r5,rt_interrupt_from_thread@l
- li r6, 0x00
- stw r6,0(r5)
-
- /* set rt_interrupt_from_thread = to */
- lis r5,rt_interrupt_to_thread@h
- ori r5,r5,rt_interrupt_to_thread@l
- stw r3,0(r5)
-
- /* trigger a system call */
- sc
-
- blr
-
- /* void rt_hw_context_switch(from, to); */
- .globl rt_hw_context_switch
-rt_hw_context_switch:
- /* compare rt_thread_switch_interrupt_flag and set it */
- lis r5,rt_thread_switch_interrput_flag@h
- ori r5,r5,rt_thread_switch_interrput_flag@l
- lwz r6,0(r5)
- cmpi cr0,0,r6,0x1 /* whether is 1 */
- beq _reswitch /* set already, goto _reswitch */
- li r6,0x1 /* set rt_thread_switch_interrput_flag to 1*/
- stw r6,0(r5)
-
- /* set rt_interrupt_from_thread to 'from' */
- lis r5,rt_interrupt_from_thread@h
- ori r5,r5,rt_interrupt_from_thread@l
- stw r3,0(r5)
-
-_reswitch:
- /* set rt_interrupt_to_thread to 'to' */
- lis r6,rt_interrupt_to_thread@h
- ori r6,r6,rt_interrupt_to_thread@l
- stw r4,0(r6)
-
- /* trigger a system call */
- sc
-
- blr
-
- .globl rt_hw_context_switch_interrupt
-rt_hw_context_switch_interrupt:
- /* compare rt_thread_switch_interrupt_flag and set it */
- lis r5,rt_thread_switch_interrput_flag@h
- ori r5,r5,rt_thread_switch_interrput_flag@l
- lwz r6,0(r5)
- cmpi cr0,0,r6,0x1 /* whether is 1 */
- beq _int_reswitch /* set already, goto _reswitch */
- li r6,0x1 /* set rt_thread_switch_interrput_flag to 1*/
- stw r6,0(r5)
-
- /* set rt_interrupt_from_thread to 'from' */
- lis r5,rt_interrupt_from_thread@h
- ori r5,r5,rt_interrupt_from_thread@l
- stw r3,0(r5)
-
-_int_reswitch:
- /* set rt_interrupt_to_thread to 'to' */
- lis r6,rt_interrupt_to_thread@h
- ori r6,r6,rt_interrupt_to_thread@l
- stw r4,0(r6)
-
- blr
+#include "context.h" +#define SPRG0 0x110 /* Special Purpose Register General 0 */ +#define SPRG1 0x111 /* Special Purpose Register General 1 */ + + .globl rt_hw_interrupt_disable + .globl rt_hw_interrupt_enable + .globl rt_hw_context_switch + .globl rt_hw_context_switch_to + .globl rt_hw_context_switch_interrupt + .globl rt_hw_systemcall_entry + +/* + * rt_base_t rt_hw_interrupt_disable(); + * return the interrupt status and disable interrupt + */ +#if 0 +rt_hw_interrupt_disable: + mfmsr r3 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r4,r4,r3 + SYNC /* Some chip revs need this... */ + mtmsr r4 + SYNC + blr +#else +rt_hw_interrupt_disable: + addis r4, r0, 0xFFFD + ori r4, r4, 0x7FFF + mfmsr r3 + and r4, r4, 3 /* Clear bits 14 and 16, corresponding to... */ + mtmsr r4 /* ...critical and non-critical interrupts */ + blr +#endif + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + * restore interrupt + */ +rt_hw_interrupt_enable: + mtmsr r3 + SYNC + blr + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * r3 --> from + * r4 --> to + * + * r1: stack pointer + */ +rt_hw_systemcall_entry: + mtspr SPRG0,r3 /* save r3 to SPRG0 */ + mtspr SPRG1,r4 /* save r4 to SPRG1 */ + + lis r3,rt_thread_switch_interrput_flag@h + ori r3,r3,rt_thread_switch_interrput_flag@l + lwz r4,0(r3) + cmpi cr0,0,r4,0x0 /* whether is 0 */ + beq _no_switch /* no switch, exit */ + li r4,0x0 /* set rt_thread_switch_interrput_flag to 0 */ + stw r4,0(r3) + + /* load from thread to r3 */ + lis r3,rt_interrupt_from_thread@h /* set rt_interrupt_from_thread */ + ori r3,r3,rt_interrupt_from_thread@l + lwz r3,0(r3) + + cmpi cr0,0,r3,0x0 /* whether is 0 */ + beq _restore /* it's first switch, goto _restore */ + + /* save r1:sp to thread[from] stack pointer */ + subi r1, r1, STACK_FRAME_SIZE + stw r1, 0(r3) + + /* restore r3, r4 from SPRG */ + mfspr r3,SPRG0 + mfspr r4,SPRG0 + + /* save registers */ + stw r0,GPR0(r1) /* save general purpose registers 0 */ + stmw r2,GPR2(r1) /* save general purpose registers 2-31 */ + + mfusprg0 r0 /* save usprg0 */ + stw r0,USPRG0(r1) + mfcr r0, /* save cr */ + stw r0,CR(r1) + mfxer r0 /* save xer */ + stw r0,XER(r1) + mfctr r0 /* save ctr */ + stw r0,CTR(r1) + mflr r0 /* save lr */ + stw r0, LR(r1) + + mfsrr0 r0 /* save SRR0 and SRR1 */ + stw r0,SRR0(r1) + mfsrr1 r0 + stw r0,SRR1(r1) + +_restore: + /* get thread[to] stack pointer */ + lis r4,rt_interrupt_to_thread@h + ori r4,r4,rt_interrupt_to_thread@l + lwz r1,0(r4) + lwz r1,0(r1) + + lwz r0,SRR1(r1) /* restore SRR1 and SRR0 */ + mtsrr1 r0 + lwz r0,SRR0(r1) + mtsrr0 r0 + + lwz r0,LR(r1) /* restore lr */ + mtlr r0 + lwz r0,CTR(r1) /* restore ctr */ + mtctr r0 + lwz r0,XER(r1) /* restore xer */ + mtxer r0 + lwz r0,CR(r1) /* restore cr */ + mtcr r0 + lwz r0,USPRG0(r1) /* restore usprg0 */ + // mtusprg0 r0 + + lmw r2, GPR2(r1) /* restore general register */ + lwz r0,GPR0(r1) + addi r1, r1, STACK_FRAME_SIZE + /* RFI will restore status register and thus the correct priority*/ + rfi + +_no_switch: + /* restore r3, r4 from SPRG */ + mfspr r3,SPRG0 + mfspr r4,SPRG0 + rfi + + /* void rt_hw_context_switch_to(to); */ + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + /* set rt_thread_switch_interrput_flag = 1 */ + lis r5,rt_thread_switch_interrput_flag@h + ori r5,r5,rt_thread_switch_interrput_flag@l + li r6, 0x01 + stw r6,0(r5) + + /* set rt_interrupt_from_thread = 0 */ + lis r5,rt_interrupt_from_thread@h + ori r5,r5,rt_interrupt_from_thread@l + li r6, 0x00 + stw r6,0(r5) + + /* set rt_interrupt_from_thread = to */ + lis r5,rt_interrupt_to_thread@h + ori r5,r5,rt_interrupt_to_thread@l + stw r3,0(r5) + + /* trigger a system call */ + sc + + blr + + /* void rt_hw_context_switch(from, to); */ + .globl rt_hw_context_switch +rt_hw_context_switch: + /* compare rt_thread_switch_interrupt_flag and set it */ + lis r5,rt_thread_switch_interrput_flag@h + ori r5,r5,rt_thread_switch_interrput_flag@l + lwz r6,0(r5) + cmpi cr0,0,r6,0x1 /* whether is 1 */ + beq _reswitch /* set already, goto _reswitch */ + li r6,0x1 /* set rt_thread_switch_interrput_flag to 1*/ + stw r6,0(r5) + + /* set rt_interrupt_from_thread to 'from' */ + lis r5,rt_interrupt_from_thread@h + ori r5,r5,rt_interrupt_from_thread@l + stw r3,0(r5) + +_reswitch: + /* set rt_interrupt_to_thread to 'to' */ + lis r6,rt_interrupt_to_thread@h + ori r6,r6,rt_interrupt_to_thread@l + stw r4,0(r6) + + /* trigger a system call */ + sc + + blr + + .globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + /* compare rt_thread_switch_interrupt_flag and set it */ + lis r5,rt_thread_switch_interrput_flag@h + ori r5,r5,rt_thread_switch_interrput_flag@l + lwz r6,0(r5) + cmpi cr0,0,r6,0x1 /* whether is 1 */ + beq _int_reswitch /* set already, goto _reswitch */ + li r6,0x1 /* set rt_thread_switch_interrput_flag to 1*/ + stw r6,0(r5) + + /* set rt_interrupt_from_thread to 'from' */ + lis r5,rt_interrupt_from_thread@h + ori r5,r5,rt_interrupt_from_thread@l + stw r3,0(r5) + +_int_reswitch: + /* set rt_interrupt_to_thread to 'to' */ + lis r6,rt_interrupt_to_thread@h + ori r6,r6,rt_interrupt_to_thread@l + stw r4,0(r6) + + blr diff --git a/libcpu/ppc/ppc405/include/asm/ppc405.h b/libcpu/ppc/ppc405/include/asm/ppc405.h index c15f2e3cf2..c2562047cb 100644 --- a/libcpu/ppc/ppc405/include/asm/ppc405.h +++ b/libcpu/ppc/ppc405/include/asm/ppc405.h @@ -1,980 +1,980 @@ -/*----------------------------------------------------------------------------+
-|
-| This source code has been made available to you by IBM on an AS-IS
-| basis. Anyone receiving this source is licensed under IBM
-| copyrights to use it in any way he or she deems fit, including
-| copying it, modifying it, compiling it, and redistributing it either
-| with or without modifications. No license under IBM patents or
-| patent applications is to be implied by the copyright license.
-|
-| Any user of this software should understand that IBM cannot provide
-| technical support for this software and will not be responsible for
-| any consequences resulting from the use of this software.
-|
-| Any person who transfers this source code or any derivative work
-| must include the IBM copyright notice, this paragraph, and the
-| preceding two paragraphs in the transferred software.
-|
-| COPYRIGHT I B M CORPORATION 1999
-| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
-+----------------------------------------------------------------------------*/
-
-#ifndef __PPC405_H__
-#define __PPC405_H__
-
-/* Define bits and masks for real-mode storage attribute control registers */
-#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27)
-#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
-
-/******************************************************************************
- * Special for PPC405GP
- ******************************************************************************/
-
-/******************************************************************************
- * DMA
- ******************************************************************************/
-#define DMA_DCR_BASE 0x100
-#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
-#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
-#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */
-#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */
-#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */
-#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
-#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
-#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */
-#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */
-#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */
-#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
-#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
-#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */
-#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */
-#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */
-#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */
-#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */
-#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */
-#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */
-#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */
-#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
-#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
-#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */
-
-#ifndef CONFIG_405EP
-/******************************************************************************
- * Decompression Controller
- ******************************************************************************/
-#define DECOMP_DCR_BASE 0x14
-#define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */
-#define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */
- /* values for kiar register - indirect addressing of these regs */
- #define kitor0 0x00 /* index table origin register 0 */
- #define kitor1 0x01 /* index table origin register 1 */
- #define kitor2 0x02 /* index table origin register 2 */
- #define kitor3 0x03 /* index table origin register 3 */
- #define kaddr0 0x04 /* address decode definition regsiter 0 */
- #define kaddr1 0x05 /* address decode definition regsiter 1 */
- #define kconf 0x40 /* decompression core config register */
- #define kid 0x41 /* decompression core ID register */
- #define kver 0x42 /* decompression core version # reg */
- #define kpear 0x50 /* bus error addr reg (PLB addr) */
- #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/
- #define kesr0 0x52 /* bus error status reg 0 (R/clear) */
- #define kesr0s 0x53 /* bus error status reg 0 (set) */
- /* There are 0x400 of the following registers, from krom0 to krom3ff*/
- /* Only the first one is given here. */
- #define krom0 0x400 /* SRAM/ROM read/write */
-#endif
-
-/******************************************************************************
- * Power Management
- ******************************************************************************/
-#ifdef CONFIG_405EX
-#define POWERMAN_DCR_BASE 0xb0
-#else
-#define POWERMAN_DCR_BASE 0xb8
-#endif
-#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */
-#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */
-#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */
-
-/******************************************************************************
- * Extrnal Bus Controller
- ******************************************************************************/
- /* values for ebccfga register - indirect addressing of these regs */
- #define pb0cr 0x00 /* periph bank 0 config reg */
- #define pb1cr 0x01 /* periph bank 1 config reg */
- #define pb2cr 0x02 /* periph bank 2 config reg */
- #define pb3cr 0x03 /* periph bank 3 config reg */
- #define pb4cr 0x04 /* periph bank 4 config reg */
-#ifndef CONFIG_405EP
- #define pb5cr 0x05 /* periph bank 5 config reg */
- #define pb6cr 0x06 /* periph bank 6 config reg */
- #define pb7cr 0x07 /* periph bank 7 config reg */
-#endif
- #define pb0ap 0x10 /* periph bank 0 access parameters */
- #define pb1ap 0x11 /* periph bank 1 access parameters */
- #define pb2ap 0x12 /* periph bank 2 access parameters */
- #define pb3ap 0x13 /* periph bank 3 access parameters */
- #define pb4ap 0x14 /* periph bank 4 access parameters */
-#ifndef CONFIG_405EP
- #define pb5ap 0x15 /* periph bank 5 access parameters */
- #define pb6ap 0x16 /* periph bank 6 access parameters */
- #define pb7ap 0x17 /* periph bank 7 access parameters */
-#endif
- #define pbear 0x20 /* periph bus error addr reg */
- #define pbesr0 0x21 /* periph bus error status reg 0 */
- #define pbesr1 0x22 /* periph bus error status reg 1 */
- #define epcr 0x23 /* external periph control reg */
-#define EBC0_CFG 0x23 /* external bus configuration reg */
-
-#ifdef CONFIG_405EP
-/******************************************************************************
- * Control
- ******************************************************************************/
-#define CNTRL_DCR_BASE 0x0f0
-#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */
-#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */
-#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */
-#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */
-#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */
-#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */
-
-#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
-#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
-#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
-#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/
-#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
-#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
-#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
-#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
-#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
-#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
-
-/* Bit definitions */
-#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
-#define PLLMR0_CPU_DIV_BYPASS 0x00000000
-#define PLLMR0_CPU_DIV_2 0x00100000
-#define PLLMR0_CPU_DIV_3 0x00200000
-#define PLLMR0_CPU_DIV_4 0x00300000
-
-#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
-#define PLLMR0_CPU_PLB_DIV_1 0x00000000
-#define PLLMR0_CPU_PLB_DIV_2 0x00010000
-#define PLLMR0_CPU_PLB_DIV_3 0x00020000
-#define PLLMR0_CPU_PLB_DIV_4 0x00030000
-
-#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
-#define PLLMR0_OPB_PLB_DIV_1 0x00000000
-#define PLLMR0_OPB_PLB_DIV_2 0x00001000
-#define PLLMR0_OPB_PLB_DIV_3 0x00002000
-#define PLLMR0_OPB_PLB_DIV_4 0x00003000
-
-#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
-#define PLLMR0_EXB_PLB_DIV_2 0x00000000
-#define PLLMR0_EXB_PLB_DIV_3 0x00000100
-#define PLLMR0_EXB_PLB_DIV_4 0x00000200
-#define PLLMR0_EXB_PLB_DIV_5 0x00000300
-
-#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
-#define PLLMR0_MAL_PLB_DIV_1 0x00000000
-#define PLLMR0_MAL_PLB_DIV_2 0x00000010
-#define PLLMR0_MAL_PLB_DIV_3 0x00000020
-#define PLLMR0_MAL_PLB_DIV_4 0x00000030
-
-#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
-#define PLLMR0_PCI_PLB_DIV_1 0x00000000
-#define PLLMR0_PCI_PLB_DIV_2 0x00000001
-#define PLLMR0_PCI_PLB_DIV_3 0x00000002
-#define PLLMR0_PCI_PLB_DIV_4 0x00000003
-
-#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
-#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
-#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
-#define PLLMR1_FBMUL_DIV_16 0x00000000
-#define PLLMR1_FBMUL_DIV_1 0x00100000
-#define PLLMR1_FBMUL_DIV_2 0x00200000
-#define PLLMR1_FBMUL_DIV_3 0x00300000
-#define PLLMR1_FBMUL_DIV_4 0x00400000
-#define PLLMR1_FBMUL_DIV_5 0x00500000
-#define PLLMR1_FBMUL_DIV_6 0x00600000
-#define PLLMR1_FBMUL_DIV_7 0x00700000
-#define PLLMR1_FBMUL_DIV_8 0x00800000
-#define PLLMR1_FBMUL_DIV_9 0x00900000
-#define PLLMR1_FBMUL_DIV_10 0x00A00000
-#define PLLMR1_FBMUL_DIV_11 0x00B00000
-#define PLLMR1_FBMUL_DIV_12 0x00C00000
-#define PLLMR1_FBMUL_DIV_13 0x00D00000
-#define PLLMR1_FBMUL_DIV_14 0x00E00000
-#define PLLMR1_FBMUL_DIV_15 0x00F00000
-
-#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
-#define PLLMR1_FWDVA_DIV_8 0x00000000
-#define PLLMR1_FWDVA_DIV_7 0x00010000
-#define PLLMR1_FWDVA_DIV_6 0x00020000
-#define PLLMR1_FWDVA_DIV_5 0x00030000
-#define PLLMR1_FWDVA_DIV_4 0x00040000
-#define PLLMR1_FWDVA_DIV_3 0x00050000
-#define PLLMR1_FWDVA_DIV_2 0x00060000
-#define PLLMR1_FWDVA_DIV_1 0x00070000
-#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
-#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
-
-/* Defines for CPC0_EPRCSR register */
-#define CPC0_EPRCSR_E0NFE 0x80000000
-#define CPC0_EPRCSR_E1NFE 0x40000000
-#define CPC0_EPRCSR_E1RPP 0x00000080
-#define CPC0_EPRCSR_E0RPP 0x00000040
-#define CPC0_EPRCSR_E1ERP 0x00000020
-#define CPC0_EPRCSR_E0ERP 0x00000010
-#define CPC0_EPRCSR_E1PCI 0x00000002
-#define CPC0_EPRCSR_E0PCI 0x00000001
-
-/* Defines for CPC0_PCI Register */
-#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */
-#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */
-#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/
-
-/* Defines for CPC0_BOOR Register */
-#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
-
-/* Defines for CPC0_PLLMR1 Register fields */
-#define PLL_ACTIVE 0x80000000
-#define CPC0_PLLMR1_SSCS 0x80000000
-#define PLL_RESET 0x40000000
-#define CPC0_PLLMR1_PLLR 0x40000000
- /* Feedback multiplier */
-#define PLL_FBKDIV 0x00F00000
-#define CPC0_PLLMR1_FBDV 0x00F00000
-#define PLL_FBKDIV_16 0x00000000
-#define PLL_FBKDIV_1 0x00100000
-#define PLL_FBKDIV_2 0x00200000
-#define PLL_FBKDIV_3 0x00300000
-#define PLL_FBKDIV_4 0x00400000
-#define PLL_FBKDIV_5 0x00500000
-#define PLL_FBKDIV_6 0x00600000
-#define PLL_FBKDIV_7 0x00700000
-#define PLL_FBKDIV_8 0x00800000
-#define PLL_FBKDIV_9 0x00900000
-#define PLL_FBKDIV_10 0x00A00000
-#define PLL_FBKDIV_11 0x00B00000
-#define PLL_FBKDIV_12 0x00C00000
-#define PLL_FBKDIV_13 0x00D00000
-#define PLL_FBKDIV_14 0x00E00000
-#define PLL_FBKDIV_15 0x00F00000
- /* Forward A divisor */
-#define PLL_FWDDIVA 0x00070000
-#define CPC0_PLLMR1_FWDVA 0x00070000
-#define PLL_FWDDIVA_8 0x00000000
-#define PLL_FWDDIVA_7 0x00010000
-#define PLL_FWDDIVA_6 0x00020000
-#define PLL_FWDDIVA_5 0x00030000
-#define PLL_FWDDIVA_4 0x00040000
-#define PLL_FWDDIVA_3 0x00050000
-#define PLL_FWDDIVA_2 0x00060000
-#define PLL_FWDDIVA_1 0x00070000
- /* Forward B divisor */
-#define PLL_FWDDIVB 0x00007000
-#define CPC0_PLLMR1_FWDVB 0x00007000
-#define PLL_FWDDIVB_8 0x00000000
-#define PLL_FWDDIVB_7 0x00001000
-#define PLL_FWDDIVB_6 0x00002000
-#define PLL_FWDDIVB_5 0x00003000
-#define PLL_FWDDIVB_4 0x00004000
-#define PLL_FWDDIVB_3 0x00005000
-#define PLL_FWDDIVB_2 0x00006000
-#define PLL_FWDDIVB_1 0x00007000
- /* PLL tune bits */
-#define PLL_TUNE_MASK 0x000003FF
-#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
-#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
-#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
-#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
-#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
-#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
-#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
-
-/* Defines for CPC0_PLLMR0 Register fields */
- /* CPU divisor */
-#define PLL_CPUDIV 0x00300000
-#define CPC0_PLLMR0_CCDV 0x00300000
-#define PLL_CPUDIV_1 0x00000000
-#define PLL_CPUDIV_2 0x00100000
-#define PLL_CPUDIV_3 0x00200000
-#define PLL_CPUDIV_4 0x00300000
- /* PLB divisor */
-#define PLL_PLBDIV 0x00030000
-#define CPC0_PLLMR0_CBDV 0x00030000
-#define PLL_PLBDIV_1 0x00000000
-#define PLL_PLBDIV_2 0x00010000
-#define PLL_PLBDIV_3 0x00020000
-#define PLL_PLBDIV_4 0x00030000
- /* OPB divisor */
-#define PLL_OPBDIV 0x00003000
-#define CPC0_PLLMR0_OPDV 0x00003000
-#define PLL_OPBDIV_1 0x00000000
-#define PLL_OPBDIV_2 0x00001000
-#define PLL_OPBDIV_3 0x00002000
-#define PLL_OPBDIV_4 0x00003000
- /* EBC divisor */
-#define PLL_EXTBUSDIV 0x00000300
-#define CPC0_PLLMR0_EPDV 0x00000300
-#define PLL_EXTBUSDIV_2 0x00000000
-#define PLL_EXTBUSDIV_3 0x00000100
-#define PLL_EXTBUSDIV_4 0x00000200
-#define PLL_EXTBUSDIV_5 0x00000300
- /* MAL divisor */
-#define PLL_MALDIV 0x00000030
-#define CPC0_PLLMR0_MPDV 0x00000030
-#define PLL_MALDIV_1 0x00000000
-#define PLL_MALDIV_2 0x00000010
-#define PLL_MALDIV_3 0x00000020
-#define PLL_MALDIV_4 0x00000030
- /* PCI divisor */
-#define PLL_PCIDIV 0x00000003
-#define CPC0_PLLMR0_PPFD 0x00000003
-#define PLL_PCIDIV_1 0x00000000
-#define PLL_PCIDIV_2 0x00000001
-#define PLL_PCIDIV_3 0x00000002
-#define PLL_PCIDIV_4 0x00000003
-
-/*
- *-------------------------------------------------------------------------------
- * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
- * assuming a 33.3MHz input clock to the 405EP.
- *-------------------------------------------------------------------------------
- */
-#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
- PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
- PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
- PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
- PLL_MALDIV_1 | PLL_PCIDIV_3)
-#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
- PLL_MALDIV_1 | PLL_PCIDIV_1)
-#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-
-/*
- * PLL Voltage Controlled Oscillator (VCO) definitions
- * Maximum and minimum values (in MHz) for correct PLL operation.
- */
-#define VCO_MIN 500
-#define VCO_MAX 1000
-#elif defined(CONFIG_405EZ)
-#define sdrnand0 0x4000
-#define sdrultra0 0x4040
-#define sdrultra1 0x4050
-#define sdricintstat 0x4510
-
-#define SDR_NAND0_NDEN 0x80000000
-#define SDR_NAND0_NDBTEN 0x40000000
-#define SDR_NAND0_NDBADR_MASK 0x30000000
-#define SDR_NAND0_NDBPG_MASK 0x0f000000
-#define SDR_NAND0_NDAREN 0x00800000
-#define SDR_NAND0_NDRBEN 0x00400000
-
-#define SDR_ULTRA0_NDGPIOBP 0x80000000
-#define SDR_ULTRA0_CSN_MASK 0x78000000
-#define SDR_ULTRA0_CSNSEL0 0x40000000
-#define SDR_ULTRA0_CSNSEL1 0x20000000
-#define SDR_ULTRA0_CSNSEL2 0x10000000
-#define SDR_ULTRA0_CSNSEL3 0x08000000
-#define SDR_ULTRA0_EBCRDYEN 0x04000000
-#define SDR_ULTRA0_SPISSINEN 0x02000000
-#define SDR_ULTRA0_NFSRSTEN 0x01000000
-
-#define SDR_ULTRA1_LEDNENABLE 0x40000000
-
-#define SDR_ICRX_STAT 0x80000000
-#define SDR_ICTX0_STAT 0x40000000
-#define SDR_ICTX1_STAT 0x20000000
-
-#define SDR_PINSTP 0x40
-
-/******************************************************************************
- * Control
- ******************************************************************************/
-/* CPR Registers */
-#define cprclkupd 0x020 /* CPR_CLKUPD */
-#define cprpllc 0x040 /* CPR_PLLC */
-#define cprplld 0x060 /* CPR_PLLD */
-#define cprprimad 0x080 /* CPR_PRIMAD */
-#define cprperd0 0x0e0 /* CPR_PERD0 */
-#define cprperd1 0x0e1 /* CPR_PERD1 */
-#define cprperc0 0x180 /* CPR_PERC0 */
-#define cprmisc0 0x181 /* CPR_MISC0 */
-#define cprmisc1 0x182 /* CPR_MISC1 */
-
-#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */
-#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
-#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
-
-#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
-
-#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
-#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
-#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
-
-#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
-#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
-#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
-#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
-
-#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
-#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
-#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
-#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
-
-#else /* #ifdef CONFIG_405EP */
-/******************************************************************************
- * Control
- ******************************************************************************/
-#define CNTRL_DCR_BASE 0x0b0
-#define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */
-#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */
-#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */
-#define reset (CNTRL_DCR_BASE+0x3) /* reset register */
-#define strap (CNTRL_DCR_BASE+0x4) /* strap register */
-
-#define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */
-#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */
-#define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */
-
-/* CPC0_ECR/CPC0_EIRR: PPC405GPr only */
-#define CPC0_EIRR (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */
-#define CPC0_ECR (0xaa) /* edge conditioner register */
-
-#define ecr (0xaa) /* edge conditioner register (405gpr) */
-
-/* Bit definitions */
-#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
-#define PLLMR_FWD_DIV_BYPASS 0xE0000000
-#define PLLMR_FWD_DIV_3 0xA0000000
-#define PLLMR_FWD_DIV_4 0x80000000
-#define PLLMR_FWD_DIV_6 0x40000000
-
-#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
-#define PLLMR_FB_DIV_1 0x02000000
-#define PLLMR_FB_DIV_2 0x04000000
-#define PLLMR_FB_DIV_3 0x06000000
-#define PLLMR_FB_DIV_4 0x08000000
-
-#define PLLMR_TUNING_MASK 0x01F80000
-
-#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
-#define PLLMR_CPU_PLB_DIV_1 0x00000000
-#define PLLMR_CPU_PLB_DIV_2 0x00020000
-#define PLLMR_CPU_PLB_DIV_3 0x00040000
-#define PLLMR_CPU_PLB_DIV_4 0x00060000
-
-#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
-#define PLLMR_OPB_PLB_DIV_1 0x00000000
-#define PLLMR_OPB_PLB_DIV_2 0x00008000
-#define PLLMR_OPB_PLB_DIV_3 0x00010000
-#define PLLMR_OPB_PLB_DIV_4 0x00018000
-
-#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
-#define PLLMR_PCI_PLB_DIV_1 0x00000000
-#define PLLMR_PCI_PLB_DIV_2 0x00002000
-#define PLLMR_PCI_PLB_DIV_3 0x00004000
-#define PLLMR_PCI_PLB_DIV_4 0x00006000
-
-#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
-#define PLLMR_EXB_PLB_DIV_2 0x00000000
-#define PLLMR_EXB_PLB_DIV_3 0x00000800
-#define PLLMR_EXB_PLB_DIV_4 0x00001000
-#define PLLMR_EXB_PLB_DIV_5 0x00001800
-
-/* definitions for PPC405GPr (new mode strapping) */
-#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
-
-#define PSR_PLL_FWD_MASK 0xC0000000
-#define PSR_PLL_FDBACK_MASK 0x30000000
-#define PSR_PLL_TUNING_MASK 0x0E000000
-#define PSR_PLB_CPU_MASK 0x01800000
-#define PSR_OPB_PLB_MASK 0x00600000
-#define PSR_PCI_PLB_MASK 0x00180000
-#define PSR_EB_PLB_MASK 0x00060000
-#define PSR_ROM_WIDTH_MASK 0x00018000
-#define PSR_ROM_LOC 0x00004000
-#define PSR_PCI_ASYNC_EN 0x00001000
-#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
-#define PSR_PCI_ARBIT_EN 0x00000400
-#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
-
-#ifndef CONFIG_IOP480
-/*
- * PLL Voltage Controlled Oscillator (VCO) definitions
- * Maximum and minimum values (in MHz) for correct PLL operation.
- */
-#define VCO_MIN 400
-#define VCO_MAX 800
-#endif /* #ifndef CONFIG_IOP480 */
-#endif /* #ifdef CONFIG_405EP */
-
-/******************************************************************************
- * Memory Access Layer
- ******************************************************************************/
-#if defined(CONFIG_405EZ)
-#define MAL_DCR_BASE 0x380
-#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
-#define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/
-#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
-#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
-#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/
-#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
-#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
-#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
-/* 0x08-0x0F Reserved */
-#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/
-#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
-#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
-#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
-/* 0x14-0x1F Reserved */
-#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */
-#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */
-#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */
-#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */
-#define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */
-#define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */
-#define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */
-#define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */
-#define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */
-#define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */
-#define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */
-#define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */
-#define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */
-#define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */
-#define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */
-#define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */
-#define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */
-#define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */
-#define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */
-#define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */
-#define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */
-#define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */
-#define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */
-#define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */
-#define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */
-#define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */
-#define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */
-#define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */
-#define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */
-#define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */
-#define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */
-#define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */
-#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */
-#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */
-#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */
-#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */
-#define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */
-#define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */
-#define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */
-#define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */
-#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */
-#define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */
-#define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */
-#define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */
-#define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */
-#define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */
-#define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */
-#define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */
-#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */
-#define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */
-#define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */
-#define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */
-#define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */
-#define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */
-#define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */
-#define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */
-#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */
-#define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */
-#define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */
-#define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */
-#define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */
-#define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */
-#define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */
-#define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */
-#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
-#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
-#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
-#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
-#define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */
-#define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */
-#define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */
-#define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */
-#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */
-#define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */
-#define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */
-#define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */
-#define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */
-#define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */
-#define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */
-#define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */
-#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */
-#define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */
-#define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */
-#define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */
-#define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */
-#define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */
-#define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */
-#define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */
-#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */
-#define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */
-#define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */
-#define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */
-#define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */
-#define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */
-#define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */
-#define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */
-
-#else /* !defined(CONFIG_405EZ) */
-
-#define MAL_DCR_BASE 0x180
-#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
-#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
-#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
-#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
-#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
-#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
-#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
-#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
-#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
-#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
-#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
-#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
-#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
-#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
-#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */
-#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
-#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
-#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
-#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
-#endif /* defined(CONFIG_405EZ) */
-
-/*-----------------------------------------------------------------------------
-| IIC Register Offsets
-'----------------------------------------------------------------------------*/
-#define IICMDBUF 0x00
-#define IICSDBUF 0x02
-#define IICLMADR 0x04
-#define IICHMADR 0x05
-#define IICCNTL 0x06
-#define IICMDCNTL 0x07
-#define IICSTS 0x08
-#define IICEXTSTS 0x09
-#define IICLSADR 0x0A
-#define IICHSADR 0x0B
-#define IICCLKDIV 0x0C
-#define IICINTRMSK 0x0D
-#define IICXFRCNT 0x0E
-#define IICXTCNTLSS 0x0F
-#define IICDIRECTCNTL 0x10
-
-/*-----------------------------------------------------------------------------
-| UART Register Offsets
-'----------------------------------------------------------------------------*/
-#define DATA_REG 0x00
-#define DL_LSB 0x00
-#define DL_MSB 0x01
-#define INT_ENABLE 0x01
-#define FIFO_CONTROL 0x02
-#define LINE_CONTROL 0x03
-#define MODEM_CONTROL 0x04
-#define LINE_STATUS 0x05
-#define MODEM_STATUS 0x06
-#define SCRATCH 0x07
-
-/******************************************************************************
- * On Chip Memory
- ******************************************************************************/
-#if defined(CONFIG_405EZ)
-#define OCM_DCR_BASE 0x020
-#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */
-#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */
-#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */
-#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */
-#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */
-#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */
-#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */
-#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */
-#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */
-#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */
-#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */
-#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */
-#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/
-#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/
-#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/
-#else
-#define OCM_DCR_BASE 0x018
-#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */
-#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
-#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */
-#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */
-#endif /* CONFIG_405EZ */
-
-/******************************************************************************
- * GPIO macro register defines
- ******************************************************************************/
-#if defined(CONFIG_405EZ)
-/* Only the 405EZ has 2 GPIOs */
-#define GPIO_BASE 0xEF600700
-#define GPIO0_OR (GPIO_BASE+0x0)
-#define GPIO0_TCR (GPIO_BASE+0x4)
-#define GPIO0_OSRL (GPIO_BASE+0x8)
-#define GPIO0_OSRH (GPIO_BASE+0xC)
-#define GPIO0_TSRL (GPIO_BASE+0x10)
-#define GPIO0_TSRH (GPIO_BASE+0x14)
-#define GPIO0_ODR (GPIO_BASE+0x18)
-#define GPIO0_IR (GPIO_BASE+0x1C)
-#define GPIO0_RR1 (GPIO_BASE+0x20)
-#define GPIO0_RR2 (GPIO_BASE+0x24)
-#define GPIO0_RR3 (GPIO_BASE+0x28)
-#define GPIO0_ISR1L (GPIO_BASE+0x30)
-#define GPIO0_ISR1H (GPIO_BASE+0x34)
-#define GPIO0_ISR2L (GPIO_BASE+0x38)
-#define GPIO0_ISR2H (GPIO_BASE+0x3C)
-#define GPIO0_ISR3L (GPIO_BASE+0x40)
-#define GPIO0_ISR3H (GPIO_BASE+0x44)
-
-#define GPIO1_BASE 0xEF600800
-#define GPIO1_OR (GPIO1_BASE+0x0)
-#define GPIO1_TCR (GPIO1_BASE+0x4)
-#define GPIO1_OSRL (GPIO1_BASE+0x8)
-#define GPIO1_OSRH (GPIO1_BASE+0xC)
-#define GPIO1_TSRL (GPIO1_BASE+0x10)
-#define GPIO1_TSRH (GPIO1_BASE+0x14)
-#define GPIO1_ODR (GPIO1_BASE+0x18)
-#define GPIO1_IR (GPIO1_BASE+0x1C)
-#define GPIO1_RR1 (GPIO1_BASE+0x20)
-#define GPIO1_RR2 (GPIO1_BASE+0x24)
-#define GPIO1_RR3 (GPIO1_BASE+0x28)
-#define GPIO1_ISR1L (GPIO1_BASE+0x30)
-#define GPIO1_ISR1H (GPIO1_BASE+0x34)
-#define GPIO1_ISR2L (GPIO1_BASE+0x38)
-#define GPIO1_ISR2H (GPIO1_BASE+0x3C)
-#define GPIO1_ISR3L (GPIO1_BASE+0x40)
-#define GPIO1_ISR3H (GPIO1_BASE+0x44)
-
-#elif defined(CONFIG_405EX)
-#define GPIO_BASE 0xEF600800
-#define GPIO0_OR (GPIO_BASE+0x0)
-#define GPIO0_TCR (GPIO_BASE+0x4)
-#define GPIO0_OSRL (GPIO_BASE+0x8)
-#define GPIO0_OSRH (GPIO_BASE+0xC)
-#define GPIO0_TSRL (GPIO_BASE+0x10)
-#define GPIO0_TSRH (GPIO_BASE+0x14)
-#define GPIO0_ODR (GPIO_BASE+0x18)
-#define GPIO0_IR (GPIO_BASE+0x1C)
-#define GPIO0_RR1 (GPIO_BASE+0x20)
-#define GPIO0_RR2 (GPIO_BASE+0x24)
-#define GPIO0_ISR1L (GPIO_BASE+0x30)
-#define GPIO0_ISR1H (GPIO_BASE+0x34)
-#define GPIO0_ISR2L (GPIO_BASE+0x38)
-#define GPIO0_ISR2H (GPIO_BASE+0x3C)
-#define GPIO0_ISR3L (GPIO_BASE+0x40)
-#define GPIO0_ISR3H (GPIO_BASE+0x44)
-
-#else /* !405EZ */
-
-#define GPIO_BASE 0xEF600700
-#define GPIO0_OR (GPIO_BASE+0x0)
-#define GPIO0_TCR (GPIO_BASE+0x4)
-#define GPIO0_OSRH (GPIO_BASE+0x8)
-#define GPIO0_OSRL (GPIO_BASE+0xC)
-#define GPIO0_TSRH (GPIO_BASE+0x10)
-#define GPIO0_TSRL (GPIO_BASE+0x14)
-#define GPIO0_ODR (GPIO_BASE+0x18)
-#define GPIO0_IR (GPIO_BASE+0x1C)
-#define GPIO0_RR1 (GPIO_BASE+0x20)
-#define GPIO0_RR2 (GPIO_BASE+0x24)
-#define GPIO0_ISR1H (GPIO_BASE+0x30)
-#define GPIO0_ISR1L (GPIO_BASE+0x34)
-#define GPIO0_ISR2H (GPIO_BASE+0x38)
-#define GPIO0_ISR2L (GPIO_BASE+0x3C)
-
-#endif /* CONFIG_405EZ */
-
-#define GPIO0_BASE GPIO_BASE
-
-#if defined(CONFIG_405EX)
-#define SDR0_SRST 0x0200
-
-/*
- * Software Reset Register
- */
-#define SDR0_SRST_BGO PPC_REG_VAL(0, 1)
-#define SDR0_SRST_PLB4 PPC_REG_VAL(1, 1)
-#define SDR0_SRST_EBC PPC_REG_VAL(2, 1)
-#define SDR0_SRST_OPB PPC_REG_VAL(3, 1)
-#define SDR0_SRST_UART0 PPC_REG_VAL(4, 1)
-#define SDR0_SRST_UART1 PPC_REG_VAL(5, 1)
-#define SDR0_SRST_IIC0 PPC_REG_VAL(6, 1)
-#define SDR0_SRST_BGI PPC_REG_VAL(7, 1)
-#define SDR0_SRST_GPIO PPC_REG_VAL(8, 1)
-#define SDR0_SRST_GPT PPC_REG_VAL(9, 1)
-#define SDR0_SRST_DMC PPC_REG_VAL(10, 1)
-#define SDR0_SRST_RGMII PPC_REG_VAL(11, 1)
-#define SDR0_SRST_EMAC0 PPC_REG_VAL(12, 1)
-#define SDR0_SRST_EMAC1 PPC_REG_VAL(13, 1)
-#define SDR0_SRST_CPM PPC_REG_VAL(14, 1)
-#define SDR0_SRST_EPLL PPC_REG_VAL(15, 1)
-#define SDR0_SRST_UIC PPC_REG_VAL(16, 1)
-#define SDR0_SRST_UPRST PPC_REG_VAL(17, 1)
-#define SDR0_SRST_IIC1 PPC_REG_VAL(18, 1)
-#define SDR0_SRST_SCP PPC_REG_VAL(19, 1)
-#define SDR0_SRST_UHRST PPC_REG_VAL(20, 1)
-#define SDR0_SRST_DMA PPC_REG_VAL(21, 1)
-#define SDR0_SRST_DMAC PPC_REG_VAL(22, 1)
-#define SDR0_SRST_MAL PPC_REG_VAL(23, 1)
-#define SDR0_SRST_EBM PPC_REG_VAL(24, 1)
-#define SDR0_SRST_GPTR PPC_REG_VAL(25, 1)
-#define SDR0_SRST_PE0 PPC_REG_VAL(26, 1)
-#define SDR0_SRST_PE1 PPC_REG_VAL(27, 1)
-#define SDR0_SRST_CRYP PPC_REG_VAL(28, 1)
-#define SDR0_SRST_PKP PPC_REG_VAL(29, 1)
-#define SDR0_SRST_AHB PPC_REG_VAL(30, 1)
-#define SDR0_SRST_NDFC PPC_REG_VAL(31, 1)
-
-#define sdr_uart0 0x0120 /* UART0 Config */
-#define sdr_uart1 0x0121 /* UART1 Config */
-#define sdr_mfr 0x4300 /* SDR0_MFR reg */
-
-/* Defines for CPC0_EPRCSR register */
-#define CPC0_EPRCSR_E0NFE 0x80000000
-#define CPC0_EPRCSR_E1NFE 0x40000000
-#define CPC0_EPRCSR_E1RPP 0x00000080
-#define CPC0_EPRCSR_E0RPP 0x00000040
-#define CPC0_EPRCSR_E1ERP 0x00000020
-#define CPC0_EPRCSR_E0ERP 0x00000010
-#define CPC0_EPRCSR_E1PCI 0x00000002
-#define CPC0_EPRCSR_E0PCI 0x00000001
-
-#define cpr0_clkupd 0x020
-#define cpr0_pllc 0x040
-#define cpr0_plld 0x060
-#define cpr0_cpud 0x080
-#define cpr0_plbd 0x0a0
-#define cpr0_opbd 0x0c0
-#define cpr0_perd 0x0e0
-#define cpr0_ahbd 0x100
-#define cpr0_icfg 0x140
-
-#define SDR_PINSTP 0x0040
-#define sdr_sdcs 0x0060
-
-#define SDR0_SDCS_SDD (0x80000000 >> 31)
-
-/* CUST0 Customer Configuration Register0 */
-#define SDR0_CUST0 0x4000
-#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
-#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
-#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
-#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
-
-#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
-#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
-#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
-
-#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
-#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
-#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
-
-#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
-#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
-#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
-
-#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
-#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
-#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
-
-#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
-#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
-
-#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
-#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
-#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
-
-#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
-#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
-#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
-
-#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
-#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
-#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
-#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
-
-#define SDR0_PFC0 0x4100
-#define SDR0_PFC1 0x4101
-#define SDR0_PFC1_U1ME 0x02000000
-#define SDR0_PFC1_U0ME 0x00080000
-#define SDR0_PFC1_U0IM 0x00040000
-#define SDR0_PFC1_SIS 0x00020000
-#define SDR0_PFC1_DMAAEN 0x00010000
-#define SDR0_PFC1_DMADEN 0x00008000
-#define SDR0_PFC1_USBEN 0x00004000
-#define SDR0_PFC1_AHBSWAP 0x00000020
-#define SDR0_PFC1_USBBIGEN 0x00000010
-#define SDR0_PFC1_GPT_FREQ 0x0000000f
-#endif
-
-/* General Purpose Timer (GPT) Register Offsets */
-#define GPT0_TBC 0x00000000
-#define GPT0_IM 0x00000018
-#define GPT0_ISS 0x0000001C
-#define GPT0_ISC 0x00000020
-#define GPT0_IE 0x00000024
-#define GPT0_COMP0 0x00000080
-#define GPT0_COMP1 0x00000084
-#define GPT0_COMP2 0x00000088
-#define GPT0_COMP3 0x0000008C
-#define GPT0_COMP4 0x00000090
-#define GPT0_COMP5 0x00000094
-#define GPT0_COMP6 0x00000098
-#define GPT0_MASK0 0x000000C0
-#define GPT0_MASK1 0x000000C4
-#define GPT0_MASK2 0x000000C8
-#define GPT0_MASK3 0x000000CC
-#define GPT0_MASK4 0x000000D0
-#define GPT0_MASK5 0x000000D4
-#define GPT0_MASK6 0x000000D8
-#define GPT0_DCT0 0x00000110
-#define GPT0_DCIS 0x0000011C
-
-#endif /* __PPC405_H__ */
+/*----------------------------------------------------------------------------+ +| +| This source code has been made available to you by IBM on an AS-IS +| basis. Anyone receiving this source is licensed under IBM +| copyrights to use it in any way he or she deems fit, including +| copying it, modifying it, compiling it, and redistributing it either +| with or without modifications. No license under IBM patents or +| patent applications is to be implied by the copyright license. +| +| Any user of this software should understand that IBM cannot provide +| technical support for this software and will not be responsible for +| any consequences resulting from the use of this software. +| +| Any person who transfers this source code or any derivative work +| must include the IBM copyright notice, this paragraph, and the +| preceding two paragraphs in the transferred software. +| +| COPYRIGHT I B M CORPORATION 1999 +| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M ++----------------------------------------------------------------------------*/ + +#ifndef __PPC405_H__ +#define __PPC405_H__ + +/* Define bits and masks for real-mode storage attribute control registers */ +#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27) +#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1) + +/****************************************************************************** + * Special for PPC405GP + ******************************************************************************/ + +/****************************************************************************** + * DMA + ******************************************************************************/ +#define DMA_DCR_BASE 0x100 +#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ +#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ +#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */ +#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */ +#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */ +#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ +#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ +#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */ +#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */ +#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */ +#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ +#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ +#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */ +#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */ +#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */ +#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */ +#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */ +#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */ +#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */ +#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */ +#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ +#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ +#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */ + +#ifndef CONFIG_405EP +/****************************************************************************** + * Decompression Controller + ******************************************************************************/ +#define DECOMP_DCR_BASE 0x14 +#define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */ +#define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */ + /* values for kiar register - indirect addressing of these regs */ + #define kitor0 0x00 /* index table origin register 0 */ + #define kitor1 0x01 /* index table origin register 1 */ + #define kitor2 0x02 /* index table origin register 2 */ + #define kitor3 0x03 /* index table origin register 3 */ + #define kaddr0 0x04 /* address decode definition regsiter 0 */ + #define kaddr1 0x05 /* address decode definition regsiter 1 */ + #define kconf 0x40 /* decompression core config register */ + #define kid 0x41 /* decompression core ID register */ + #define kver 0x42 /* decompression core version # reg */ + #define kpear 0x50 /* bus error addr reg (PLB addr) */ + #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/ + #define kesr0 0x52 /* bus error status reg 0 (R/clear) */ + #define kesr0s 0x53 /* bus error status reg 0 (set) */ + /* There are 0x400 of the following registers, from krom0 to krom3ff*/ + /* Only the first one is given here. */ + #define krom0 0x400 /* SRAM/ROM read/write */ +#endif + +/****************************************************************************** + * Power Management + ******************************************************************************/ +#ifdef CONFIG_405EX +#define POWERMAN_DCR_BASE 0xb0 +#else +#define POWERMAN_DCR_BASE 0xb8 +#endif +#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */ +#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */ +#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */ + +/****************************************************************************** + * Extrnal Bus Controller + ******************************************************************************/ + /* values for ebccfga register - indirect addressing of these regs */ + #define pb0cr 0x00 /* periph bank 0 config reg */ + #define pb1cr 0x01 /* periph bank 1 config reg */ + #define pb2cr 0x02 /* periph bank 2 config reg */ + #define pb3cr 0x03 /* periph bank 3 config reg */ + #define pb4cr 0x04 /* periph bank 4 config reg */ +#ifndef CONFIG_405EP + #define pb5cr 0x05 /* periph bank 5 config reg */ + #define pb6cr 0x06 /* periph bank 6 config reg */ + #define pb7cr 0x07 /* periph bank 7 config reg */ +#endif + #define pb0ap 0x10 /* periph bank 0 access parameters */ + #define pb1ap 0x11 /* periph bank 1 access parameters */ + #define pb2ap 0x12 /* periph bank 2 access parameters */ + #define pb3ap 0x13 /* periph bank 3 access parameters */ + #define pb4ap 0x14 /* periph bank 4 access parameters */ +#ifndef CONFIG_405EP + #define pb5ap 0x15 /* periph bank 5 access parameters */ + #define pb6ap 0x16 /* periph bank 6 access parameters */ + #define pb7ap 0x17 /* periph bank 7 access parameters */ +#endif + #define pbear 0x20 /* periph bus error addr reg */ + #define pbesr0 0x21 /* periph bus error status reg 0 */ + #define pbesr1 0x22 /* periph bus error status reg 1 */ + #define epcr 0x23 /* external periph control reg */ +#define EBC0_CFG 0x23 /* external bus configuration reg */ + +#ifdef CONFIG_405EP +/****************************************************************************** + * Control + ******************************************************************************/ +#define CNTRL_DCR_BASE 0x0f0 +#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ +#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */ +#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ +#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ +#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */ +#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */ + +#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ +#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ +#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/ +#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ +#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ +#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ +#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ +#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ +#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ + +/* Bit definitions */ +#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */ +#define PLLMR0_CPU_DIV_BYPASS 0x00000000 +#define PLLMR0_CPU_DIV_2 0x00100000 +#define PLLMR0_CPU_DIV_3 0x00200000 +#define PLLMR0_CPU_DIV_4 0x00300000 + +#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */ +#define PLLMR0_CPU_PLB_DIV_1 0x00000000 +#define PLLMR0_CPU_PLB_DIV_2 0x00010000 +#define PLLMR0_CPU_PLB_DIV_3 0x00020000 +#define PLLMR0_CPU_PLB_DIV_4 0x00030000 + +#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */ +#define PLLMR0_OPB_PLB_DIV_1 0x00000000 +#define PLLMR0_OPB_PLB_DIV_2 0x00001000 +#define PLLMR0_OPB_PLB_DIV_3 0x00002000 +#define PLLMR0_OPB_PLB_DIV_4 0x00003000 + +#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ +#define PLLMR0_EXB_PLB_DIV_2 0x00000000 +#define PLLMR0_EXB_PLB_DIV_3 0x00000100 +#define PLLMR0_EXB_PLB_DIV_4 0x00000200 +#define PLLMR0_EXB_PLB_DIV_5 0x00000300 + +#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ +#define PLLMR0_MAL_PLB_DIV_1 0x00000000 +#define PLLMR0_MAL_PLB_DIV_2 0x00000010 +#define PLLMR0_MAL_PLB_DIV_3 0x00000020 +#define PLLMR0_MAL_PLB_DIV_4 0x00000030 + +#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */ +#define PLLMR0_PCI_PLB_DIV_1 0x00000000 +#define PLLMR0_PCI_PLB_DIV_2 0x00000001 +#define PLLMR0_PCI_PLB_DIV_3 0x00000002 +#define PLLMR0_PCI_PLB_DIV_4 0x00000003 + +#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */ +#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */ +#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ +#define PLLMR1_FBMUL_DIV_16 0x00000000 +#define PLLMR1_FBMUL_DIV_1 0x00100000 +#define PLLMR1_FBMUL_DIV_2 0x00200000 +#define PLLMR1_FBMUL_DIV_3 0x00300000 +#define PLLMR1_FBMUL_DIV_4 0x00400000 +#define PLLMR1_FBMUL_DIV_5 0x00500000 +#define PLLMR1_FBMUL_DIV_6 0x00600000 +#define PLLMR1_FBMUL_DIV_7 0x00700000 +#define PLLMR1_FBMUL_DIV_8 0x00800000 +#define PLLMR1_FBMUL_DIV_9 0x00900000 +#define PLLMR1_FBMUL_DIV_10 0x00A00000 +#define PLLMR1_FBMUL_DIV_11 0x00B00000 +#define PLLMR1_FBMUL_DIV_12 0x00C00000 +#define PLLMR1_FBMUL_DIV_13 0x00D00000 +#define PLLMR1_FBMUL_DIV_14 0x00E00000 +#define PLLMR1_FBMUL_DIV_15 0x00F00000 + +#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ +#define PLLMR1_FWDVA_DIV_8 0x00000000 +#define PLLMR1_FWDVA_DIV_7 0x00010000 +#define PLLMR1_FWDVA_DIV_6 0x00020000 +#define PLLMR1_FWDVA_DIV_5 0x00030000 +#define PLLMR1_FWDVA_DIV_4 0x00040000 +#define PLLMR1_FWDVA_DIV_3 0x00050000 +#define PLLMR1_FWDVA_DIV_2 0x00060000 +#define PLLMR1_FWDVA_DIV_1 0x00070000 +#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ +#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ + +/* Defines for CPC0_EPRCSR register */ +#define CPC0_EPRCSR_E0NFE 0x80000000 +#define CPC0_EPRCSR_E1NFE 0x40000000 +#define CPC0_EPRCSR_E1RPP 0x00000080 +#define CPC0_EPRCSR_E0RPP 0x00000040 +#define CPC0_EPRCSR_E1ERP 0x00000020 +#define CPC0_EPRCSR_E0ERP 0x00000010 +#define CPC0_EPRCSR_E1PCI 0x00000002 +#define CPC0_EPRCSR_E0PCI 0x00000001 + +/* Defines for CPC0_PCI Register */ +#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */ +#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */ +#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/ + +/* Defines for CPC0_BOOR Register */ +#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ + +/* Defines for CPC0_PLLMR1 Register fields */ +#define PLL_ACTIVE 0x80000000 +#define CPC0_PLLMR1_SSCS 0x80000000 +#define PLL_RESET 0x40000000 +#define CPC0_PLLMR1_PLLR 0x40000000 + /* Feedback multiplier */ +#define PLL_FBKDIV 0x00F00000 +#define CPC0_PLLMR1_FBDV 0x00F00000 +#define PLL_FBKDIV_16 0x00000000 +#define PLL_FBKDIV_1 0x00100000 +#define PLL_FBKDIV_2 0x00200000 +#define PLL_FBKDIV_3 0x00300000 +#define PLL_FBKDIV_4 0x00400000 +#define PLL_FBKDIV_5 0x00500000 +#define PLL_FBKDIV_6 0x00600000 +#define PLL_FBKDIV_7 0x00700000 +#define PLL_FBKDIV_8 0x00800000 +#define PLL_FBKDIV_9 0x00900000 +#define PLL_FBKDIV_10 0x00A00000 +#define PLL_FBKDIV_11 0x00B00000 +#define PLL_FBKDIV_12 0x00C00000 +#define PLL_FBKDIV_13 0x00D00000 +#define PLL_FBKDIV_14 0x00E00000 +#define PLL_FBKDIV_15 0x00F00000 + /* Forward A divisor */ +#define PLL_FWDDIVA 0x00070000 +#define CPC0_PLLMR1_FWDVA 0x00070000 +#define PLL_FWDDIVA_8 0x00000000 +#define PLL_FWDDIVA_7 0x00010000 +#define PLL_FWDDIVA_6 0x00020000 +#define PLL_FWDDIVA_5 0x00030000 +#define PLL_FWDDIVA_4 0x00040000 +#define PLL_FWDDIVA_3 0x00050000 +#define PLL_FWDDIVA_2 0x00060000 +#define PLL_FWDDIVA_1 0x00070000 + /* Forward B divisor */ +#define PLL_FWDDIVB 0x00007000 +#define CPC0_PLLMR1_FWDVB 0x00007000 +#define PLL_FWDDIVB_8 0x00000000 +#define PLL_FWDDIVB_7 0x00001000 +#define PLL_FWDDIVB_6 0x00002000 +#define PLL_FWDDIVB_5 0x00003000 +#define PLL_FWDDIVB_4 0x00004000 +#define PLL_FWDDIVB_3 0x00005000 +#define PLL_FWDDIVB_2 0x00006000 +#define PLL_FWDDIVB_1 0x00007000 + /* PLL tune bits */ +#define PLL_TUNE_MASK 0x000003FF +#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ +#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ +#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ +#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ +#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ +#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ +#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ + +/* Defines for CPC0_PLLMR0 Register fields */ + /* CPU divisor */ +#define PLL_CPUDIV 0x00300000 +#define CPC0_PLLMR0_CCDV 0x00300000 +#define PLL_CPUDIV_1 0x00000000 +#define PLL_CPUDIV_2 0x00100000 +#define PLL_CPUDIV_3 0x00200000 +#define PLL_CPUDIV_4 0x00300000 + /* PLB divisor */ +#define PLL_PLBDIV 0x00030000 +#define CPC0_PLLMR0_CBDV 0x00030000 +#define PLL_PLBDIV_1 0x00000000 +#define PLL_PLBDIV_2 0x00010000 +#define PLL_PLBDIV_3 0x00020000 +#define PLL_PLBDIV_4 0x00030000 + /* OPB divisor */ +#define PLL_OPBDIV 0x00003000 +#define CPC0_PLLMR0_OPDV 0x00003000 +#define PLL_OPBDIV_1 0x00000000 +#define PLL_OPBDIV_2 0x00001000 +#define PLL_OPBDIV_3 0x00002000 +#define PLL_OPBDIV_4 0x00003000 + /* EBC divisor */ +#define PLL_EXTBUSDIV 0x00000300 +#define CPC0_PLLMR0_EPDV 0x00000300 +#define PLL_EXTBUSDIV_2 0x00000000 +#define PLL_EXTBUSDIV_3 0x00000100 +#define PLL_EXTBUSDIV_4 0x00000200 +#define PLL_EXTBUSDIV_5 0x00000300 + /* MAL divisor */ +#define PLL_MALDIV 0x00000030 +#define CPC0_PLLMR0_MPDV 0x00000030 +#define PLL_MALDIV_1 0x00000000 +#define PLL_MALDIV_2 0x00000010 +#define PLL_MALDIV_3 0x00000020 +#define PLL_MALDIV_4 0x00000030 + /* PCI divisor */ +#define PLL_PCIDIV 0x00000003 +#define CPC0_PLLMR0_PPFD 0x00000003 +#define PLL_PCIDIV_1 0x00000000 +#define PLL_PCIDIV_2 0x00000001 +#define PLL_PCIDIV_3 0x00000002 +#define PLL_PCIDIV_4 0x00000003 + +/* + *------------------------------------------------------------------------------- + * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, + * assuming a 33.3MHz input clock to the 405EP. + *------------------------------------------------------------------------------- + */ +#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ + PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ + PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_2) +#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_3) +#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) +#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_1) +#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) + +/* + * PLL Voltage Controlled Oscillator (VCO) definitions + * Maximum and minimum values (in MHz) for correct PLL operation. + */ +#define VCO_MIN 500 +#define VCO_MAX 1000 +#elif defined(CONFIG_405EZ) +#define sdrnand0 0x4000 +#define sdrultra0 0x4040 +#define sdrultra1 0x4050 +#define sdricintstat 0x4510 + +#define SDR_NAND0_NDEN 0x80000000 +#define SDR_NAND0_NDBTEN 0x40000000 +#define SDR_NAND0_NDBADR_MASK 0x30000000 +#define SDR_NAND0_NDBPG_MASK 0x0f000000 +#define SDR_NAND0_NDAREN 0x00800000 +#define SDR_NAND0_NDRBEN 0x00400000 + +#define SDR_ULTRA0_NDGPIOBP 0x80000000 +#define SDR_ULTRA0_CSN_MASK 0x78000000 +#define SDR_ULTRA0_CSNSEL0 0x40000000 +#define SDR_ULTRA0_CSNSEL1 0x20000000 +#define SDR_ULTRA0_CSNSEL2 0x10000000 +#define SDR_ULTRA0_CSNSEL3 0x08000000 +#define SDR_ULTRA0_EBCRDYEN 0x04000000 +#define SDR_ULTRA0_SPISSINEN 0x02000000 +#define SDR_ULTRA0_NFSRSTEN 0x01000000 + +#define SDR_ULTRA1_LEDNENABLE 0x40000000 + +#define SDR_ICRX_STAT 0x80000000 +#define SDR_ICTX0_STAT 0x40000000 +#define SDR_ICTX1_STAT 0x20000000 + +#define SDR_PINSTP 0x40 + +/****************************************************************************** + * Control + ******************************************************************************/ +/* CPR Registers */ +#define cprclkupd 0x020 /* CPR_CLKUPD */ +#define cprpllc 0x040 /* CPR_PLLC */ +#define cprplld 0x060 /* CPR_PLLD */ +#define cprprimad 0x080 /* CPR_PRIMAD */ +#define cprperd0 0x0e0 /* CPR_PERD0 */ +#define cprperd1 0x0e1 /* CPR_PERD1 */ +#define cprperc0 0x180 /* CPR_PERC0 */ +#define cprmisc0 0x181 /* CPR_MISC0 */ +#define cprmisc1 0x182 /* CPR_MISC1 */ + +#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ +#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ +#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */ + +#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ + +#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */ +#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */ +#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */ + +#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */ +#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */ +#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */ +#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */ + +#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */ +#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */ +#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */ +#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */ + +#else /* #ifdef CONFIG_405EP */ +/****************************************************************************** + * Control + ******************************************************************************/ +#define CNTRL_DCR_BASE 0x0b0 +#define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */ +#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */ +#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */ +#define reset (CNTRL_DCR_BASE+0x3) /* reset register */ +#define strap (CNTRL_DCR_BASE+0x4) /* strap register */ + +#define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */ +#define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */ + +/* CPC0_ECR/CPC0_EIRR: PPC405GPr only */ +#define CPC0_EIRR (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */ +#define CPC0_ECR (0xaa) /* edge conditioner register */ + +#define ecr (0xaa) /* edge conditioner register (405gpr) */ + +/* Bit definitions */ +#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ +#define PLLMR_FWD_DIV_BYPASS 0xE0000000 +#define PLLMR_FWD_DIV_3 0xA0000000 +#define PLLMR_FWD_DIV_4 0x80000000 +#define PLLMR_FWD_DIV_6 0x40000000 + +#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */ +#define PLLMR_FB_DIV_1 0x02000000 +#define PLLMR_FB_DIV_2 0x04000000 +#define PLLMR_FB_DIV_3 0x06000000 +#define PLLMR_FB_DIV_4 0x08000000 + +#define PLLMR_TUNING_MASK 0x01F80000 + +#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */ +#define PLLMR_CPU_PLB_DIV_1 0x00000000 +#define PLLMR_CPU_PLB_DIV_2 0x00020000 +#define PLLMR_CPU_PLB_DIV_3 0x00040000 +#define PLLMR_CPU_PLB_DIV_4 0x00060000 + +#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */ +#define PLLMR_OPB_PLB_DIV_1 0x00000000 +#define PLLMR_OPB_PLB_DIV_2 0x00008000 +#define PLLMR_OPB_PLB_DIV_3 0x00010000 +#define PLLMR_OPB_PLB_DIV_4 0x00018000 + +#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */ +#define PLLMR_PCI_PLB_DIV_1 0x00000000 +#define PLLMR_PCI_PLB_DIV_2 0x00002000 +#define PLLMR_PCI_PLB_DIV_3 0x00004000 +#define PLLMR_PCI_PLB_DIV_4 0x00006000 + +#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */ +#define PLLMR_EXB_PLB_DIV_2 0x00000000 +#define PLLMR_EXB_PLB_DIV_3 0x00000800 +#define PLLMR_EXB_PLB_DIV_4 0x00001000 +#define PLLMR_EXB_PLB_DIV_5 0x00001800 + +/* definitions for PPC405GPr (new mode strapping) */ +#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */ + +#define PSR_PLL_FWD_MASK 0xC0000000 +#define PSR_PLL_FDBACK_MASK 0x30000000 +#define PSR_PLL_TUNING_MASK 0x0E000000 +#define PSR_PLB_CPU_MASK 0x01800000 +#define PSR_OPB_PLB_MASK 0x00600000 +#define PSR_PCI_PLB_MASK 0x00180000 +#define PSR_EB_PLB_MASK 0x00060000 +#define PSR_ROM_WIDTH_MASK 0x00018000 +#define PSR_ROM_LOC 0x00004000 +#define PSR_PCI_ASYNC_EN 0x00001000 +#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */ +#define PSR_PCI_ARBIT_EN 0x00000400 +#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */ + +#ifndef CONFIG_IOP480 +/* + * PLL Voltage Controlled Oscillator (VCO) definitions + * Maximum and minimum values (in MHz) for correct PLL operation. + */ +#define VCO_MIN 400 +#define VCO_MAX 800 +#endif /* #ifndef CONFIG_IOP480 */ +#endif /* #ifdef CONFIG_405EP */ + +/****************************************************************************** + * Memory Access Layer + ******************************************************************************/ +#if defined(CONFIG_405EZ) +#define MAL_DCR_BASE 0x380 +#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ +#define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/ +#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ +#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ +#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/ +#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ +#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ +#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ +/* 0x08-0x0F Reserved */ +#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/ +#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ +#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ +#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ +/* 0x14-0x1F Reserved */ +#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */ +#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */ +#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */ +#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */ +#define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */ +#define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */ +#define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */ +#define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */ +#define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */ +#define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */ +#define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */ +#define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */ +#define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */ +#define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */ +#define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */ +#define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */ +#define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */ +#define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */ +#define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */ +#define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */ +#define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */ +#define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */ +#define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */ +#define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */ +#define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */ +#define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */ +#define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */ +#define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */ +#define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */ +#define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */ +#define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */ +#define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */ +#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */ +#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */ +#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */ +#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */ +#define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */ +#define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */ +#define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */ +#define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */ +#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */ +#define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */ +#define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */ +#define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */ +#define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */ +#define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */ +#define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */ +#define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */ +#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */ +#define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */ +#define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */ +#define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */ +#define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */ +#define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */ +#define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */ +#define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */ +#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */ +#define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */ +#define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */ +#define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */ +#define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */ +#define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */ +#define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */ +#define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */ +#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ +#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ +#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ +#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ +#define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */ +#define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */ +#define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */ +#define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */ +#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */ +#define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */ +#define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */ +#define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */ +#define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */ +#define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */ +#define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */ +#define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */ +#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */ +#define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */ +#define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */ +#define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */ +#define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */ +#define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */ +#define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */ +#define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */ +#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ +#define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */ +#define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */ +#define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */ +#define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */ +#define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */ +#define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */ +#define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */ + +#else /* !defined(CONFIG_405EZ) */ + +#define MAL_DCR_BASE 0x180 +#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ +#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ +#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ +#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ +#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ +#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ +#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ +#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ +#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ +#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ +#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ +#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ +#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ +#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ +#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ +#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ +#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ +#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ +#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ +#endif /* defined(CONFIG_405EZ) */ + +/*----------------------------------------------------------------------------- +| IIC Register Offsets +'----------------------------------------------------------------------------*/ +#define IICMDBUF 0x00 +#define IICSDBUF 0x02 +#define IICLMADR 0x04 +#define IICHMADR 0x05 +#define IICCNTL 0x06 +#define IICMDCNTL 0x07 +#define IICSTS 0x08 +#define IICEXTSTS 0x09 +#define IICLSADR 0x0A +#define IICHSADR 0x0B +#define IICCLKDIV 0x0C +#define IICINTRMSK 0x0D +#define IICXFRCNT 0x0E +#define IICXTCNTLSS 0x0F +#define IICDIRECTCNTL 0x10 + +/*----------------------------------------------------------------------------- +| UART Register Offsets +'----------------------------------------------------------------------------*/ +#define DATA_REG 0x00 +#define DL_LSB 0x00 +#define DL_MSB 0x01 +#define INT_ENABLE 0x01 +#define FIFO_CONTROL 0x02 +#define LINE_CONTROL 0x03 +#define MODEM_CONTROL 0x04 +#define LINE_STATUS 0x05 +#define MODEM_STATUS 0x06 +#define SCRATCH 0x07 + +/****************************************************************************** + * On Chip Memory + ******************************************************************************/ +#if defined(CONFIG_405EZ) +#define OCM_DCR_BASE 0x020 +#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */ +#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */ +#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */ +#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */ +#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */ +#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */ +#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */ +#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */ +#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */ +#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */ +#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */ +#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */ +#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/ +#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/ +#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/ +#else +#define OCM_DCR_BASE 0x018 +#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */ +#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ +#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */ +#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */ +#endif /* CONFIG_405EZ */ + +/****************************************************************************** + * GPIO macro register defines + ******************************************************************************/ +#if defined(CONFIG_405EZ) +/* Only the 405EZ has 2 GPIOs */ +#define GPIO_BASE 0xEF600700 +#define GPIO0_OR (GPIO_BASE+0x0) +#define GPIO0_TCR (GPIO_BASE+0x4) +#define GPIO0_OSRL (GPIO_BASE+0x8) +#define GPIO0_OSRH (GPIO_BASE+0xC) +#define GPIO0_TSRL (GPIO_BASE+0x10) +#define GPIO0_TSRH (GPIO_BASE+0x14) +#define GPIO0_ODR (GPIO_BASE+0x18) +#define GPIO0_IR (GPIO_BASE+0x1C) +#define GPIO0_RR1 (GPIO_BASE+0x20) +#define GPIO0_RR2 (GPIO_BASE+0x24) +#define GPIO0_RR3 (GPIO_BASE+0x28) +#define GPIO0_ISR1L (GPIO_BASE+0x30) +#define GPIO0_ISR1H (GPIO_BASE+0x34) +#define GPIO0_ISR2L (GPIO_BASE+0x38) +#define GPIO0_ISR2H (GPIO_BASE+0x3C) +#define GPIO0_ISR3L (GPIO_BASE+0x40) +#define GPIO0_ISR3H (GPIO_BASE+0x44) + +#define GPIO1_BASE 0xEF600800 +#define GPIO1_OR (GPIO1_BASE+0x0) +#define GPIO1_TCR (GPIO1_BASE+0x4) +#define GPIO1_OSRL (GPIO1_BASE+0x8) +#define GPIO1_OSRH (GPIO1_BASE+0xC) +#define GPIO1_TSRL (GPIO1_BASE+0x10) +#define GPIO1_TSRH (GPIO1_BASE+0x14) +#define GPIO1_ODR (GPIO1_BASE+0x18) +#define GPIO1_IR (GPIO1_BASE+0x1C) +#define GPIO1_RR1 (GPIO1_BASE+0x20) +#define GPIO1_RR2 (GPIO1_BASE+0x24) +#define GPIO1_RR3 (GPIO1_BASE+0x28) +#define GPIO1_ISR1L (GPIO1_BASE+0x30) +#define GPIO1_ISR1H (GPIO1_BASE+0x34) +#define GPIO1_ISR2L (GPIO1_BASE+0x38) +#define GPIO1_ISR2H (GPIO1_BASE+0x3C) +#define GPIO1_ISR3L (GPIO1_BASE+0x40) +#define GPIO1_ISR3H (GPIO1_BASE+0x44) + +#elif defined(CONFIG_405EX) +#define GPIO_BASE 0xEF600800 +#define GPIO0_OR (GPIO_BASE+0x0) +#define GPIO0_TCR (GPIO_BASE+0x4) +#define GPIO0_OSRL (GPIO_BASE+0x8) +#define GPIO0_OSRH (GPIO_BASE+0xC) +#define GPIO0_TSRL (GPIO_BASE+0x10) +#define GPIO0_TSRH (GPIO_BASE+0x14) +#define GPIO0_ODR (GPIO_BASE+0x18) +#define GPIO0_IR (GPIO_BASE+0x1C) +#define GPIO0_RR1 (GPIO_BASE+0x20) +#define GPIO0_RR2 (GPIO_BASE+0x24) +#define GPIO0_ISR1L (GPIO_BASE+0x30) +#define GPIO0_ISR1H (GPIO_BASE+0x34) +#define GPIO0_ISR2L (GPIO_BASE+0x38) +#define GPIO0_ISR2H (GPIO_BASE+0x3C) +#define GPIO0_ISR3L (GPIO_BASE+0x40) +#define GPIO0_ISR3H (GPIO_BASE+0x44) + +#else /* !405EZ */ + +#define GPIO_BASE 0xEF600700 +#define GPIO0_OR (GPIO_BASE+0x0) +#define GPIO0_TCR (GPIO_BASE+0x4) +#define GPIO0_OSRH (GPIO_BASE+0x8) +#define GPIO0_OSRL (GPIO_BASE+0xC) +#define GPIO0_TSRH (GPIO_BASE+0x10) +#define GPIO0_TSRL (GPIO_BASE+0x14) +#define GPIO0_ODR (GPIO_BASE+0x18) +#define GPIO0_IR (GPIO_BASE+0x1C) +#define GPIO0_RR1 (GPIO_BASE+0x20) +#define GPIO0_RR2 (GPIO_BASE+0x24) +#define GPIO0_ISR1H (GPIO_BASE+0x30) +#define GPIO0_ISR1L (GPIO_BASE+0x34) +#define GPIO0_ISR2H (GPIO_BASE+0x38) +#define GPIO0_ISR2L (GPIO_BASE+0x3C) + +#endif /* CONFIG_405EZ */ + +#define GPIO0_BASE GPIO_BASE + +#if defined(CONFIG_405EX) +#define SDR0_SRST 0x0200 + +/* + * Software Reset Register + */ +#define SDR0_SRST_BGO PPC_REG_VAL(0, 1) +#define SDR0_SRST_PLB4 PPC_REG_VAL(1, 1) +#define SDR0_SRST_EBC PPC_REG_VAL(2, 1) +#define SDR0_SRST_OPB PPC_REG_VAL(3, 1) +#define SDR0_SRST_UART0 PPC_REG_VAL(4, 1) +#define SDR0_SRST_UART1 PPC_REG_VAL(5, 1) +#define SDR0_SRST_IIC0 PPC_REG_VAL(6, 1) +#define SDR0_SRST_BGI PPC_REG_VAL(7, 1) +#define SDR0_SRST_GPIO PPC_REG_VAL(8, 1) +#define SDR0_SRST_GPT PPC_REG_VAL(9, 1) +#define SDR0_SRST_DMC PPC_REG_VAL(10, 1) +#define SDR0_SRST_RGMII PPC_REG_VAL(11, 1) +#define SDR0_SRST_EMAC0 PPC_REG_VAL(12, 1) +#define SDR0_SRST_EMAC1 PPC_REG_VAL(13, 1) +#define SDR0_SRST_CPM PPC_REG_VAL(14, 1) +#define SDR0_SRST_EPLL PPC_REG_VAL(15, 1) +#define SDR0_SRST_UIC PPC_REG_VAL(16, 1) +#define SDR0_SRST_UPRST PPC_REG_VAL(17, 1) +#define SDR0_SRST_IIC1 PPC_REG_VAL(18, 1) +#define SDR0_SRST_SCP PPC_REG_VAL(19, 1) +#define SDR0_SRST_UHRST PPC_REG_VAL(20, 1) +#define SDR0_SRST_DMA PPC_REG_VAL(21, 1) +#define SDR0_SRST_DMAC PPC_REG_VAL(22, 1) +#define SDR0_SRST_MAL PPC_REG_VAL(23, 1) +#define SDR0_SRST_EBM PPC_REG_VAL(24, 1) +#define SDR0_SRST_GPTR PPC_REG_VAL(25, 1) +#define SDR0_SRST_PE0 PPC_REG_VAL(26, 1) +#define SDR0_SRST_PE1 PPC_REG_VAL(27, 1) +#define SDR0_SRST_CRYP PPC_REG_VAL(28, 1) +#define SDR0_SRST_PKP PPC_REG_VAL(29, 1) +#define SDR0_SRST_AHB PPC_REG_VAL(30, 1) +#define SDR0_SRST_NDFC PPC_REG_VAL(31, 1) + +#define sdr_uart0 0x0120 /* UART0 Config */ +#define sdr_uart1 0x0121 /* UART1 Config */ +#define sdr_mfr 0x4300 /* SDR0_MFR reg */ + +/* Defines for CPC0_EPRCSR register */ +#define CPC0_EPRCSR_E0NFE 0x80000000 +#define CPC0_EPRCSR_E1NFE 0x40000000 +#define CPC0_EPRCSR_E1RPP 0x00000080 +#define CPC0_EPRCSR_E0RPP 0x00000040 +#define CPC0_EPRCSR_E1ERP 0x00000020 +#define CPC0_EPRCSR_E0ERP 0x00000010 +#define CPC0_EPRCSR_E1PCI 0x00000002 +#define CPC0_EPRCSR_E0PCI 0x00000001 + +#define cpr0_clkupd 0x020 +#define cpr0_pllc 0x040 +#define cpr0_plld 0x060 +#define cpr0_cpud 0x080 +#define cpr0_plbd 0x0a0 +#define cpr0_opbd 0x0c0 +#define cpr0_perd 0x0e0 +#define cpr0_ahbd 0x100 +#define cpr0_icfg 0x140 + +#define SDR_PINSTP 0x0040 +#define sdr_sdcs 0x0060 + +#define SDR0_SDCS_SDD (0x80000000 >> 31) + +/* CUST0 Customer Configuration Register0 */ +#define SDR0_CUST0 0x4000 +#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ +#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ +#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ +#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ + +#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ +#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ +#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ + +#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ +#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ +#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ + +#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ +#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) +#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) + +#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ +#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) +#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) + +#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ + +#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ +#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ +#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ + +#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ +#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) +#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) + +#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ +#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ +#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ + +#define SDR0_PFC0 0x4100 +#define SDR0_PFC1 0x4101 +#define SDR0_PFC1_U1ME 0x02000000 +#define SDR0_PFC1_U0ME 0x00080000 +#define SDR0_PFC1_U0IM 0x00040000 +#define SDR0_PFC1_SIS 0x00020000 +#define SDR0_PFC1_DMAAEN 0x00010000 +#define SDR0_PFC1_DMADEN 0x00008000 +#define SDR0_PFC1_USBEN 0x00004000 +#define SDR0_PFC1_AHBSWAP 0x00000020 +#define SDR0_PFC1_USBBIGEN 0x00000010 +#define SDR0_PFC1_GPT_FREQ 0x0000000f +#endif + +/* General Purpose Timer (GPT) Register Offsets */ +#define GPT0_TBC 0x00000000 +#define GPT0_IM 0x00000018 +#define GPT0_ISS 0x0000001C +#define GPT0_ISC 0x00000020 +#define GPT0_IE 0x00000024 +#define GPT0_COMP0 0x00000080 +#define GPT0_COMP1 0x00000084 +#define GPT0_COMP2 0x00000088 +#define GPT0_COMP3 0x0000008C +#define GPT0_COMP4 0x00000090 +#define GPT0_COMP5 0x00000094 +#define GPT0_COMP6 0x00000098 +#define GPT0_MASK0 0x000000C0 +#define GPT0_MASK1 0x000000C4 +#define GPT0_MASK2 0x000000C8 +#define GPT0_MASK3 0x000000CC +#define GPT0_MASK4 0x000000D0 +#define GPT0_MASK5 0x000000D4 +#define GPT0_MASK6 0x000000D8 +#define GPT0_DCT0 0x00000110 +#define GPT0_DCIS 0x0000011C + +#endif /* __PPC405_H__ */ diff --git a/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h b/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h index e70b99bda6..cdb542c2da 100644 --- a/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h +++ b/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h @@ -1,61 +1,61 @@ -#ifndef _PPC4xx_UIC_H_
-#define _PPC4xx_UIC_H_
-
-/*
- * Define the number of UIC's
- */
-#define UIC_MAX 1
-#define IRQ_MAX UIC_MAX * 32
-
-/* UIC0 dcr base address */
-#define UIC0_DCR_BASE 0xc0
-
-/*
- * UIC register
- */
-#define UIC_SR 0x0 /* UIC status */
-#define UIC_ER 0x2 /* UIC enable */
-#define UIC_CR 0x3 /* UIC critical */
-#define UIC_PR 0x4 /* UIC polarity */
-#define UIC_TR 0x5 /* UIC triggering */
-#define UIC_MSR 0x6 /* UIC masked status */
-#define UIC_VR 0x7 /* UIC vector */
-#define UIC_VCR 0x8 /* UIC vector configuration */
-
-#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
-#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
-#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
-#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
-#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
-#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
-#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
-#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
-
-/* The following is for compatibility with 405 code */
-#define uicsr uic0sr
-#define uicer uic0er
-#define uiccr uic0cr
-#define uicpr uic0pr
-#define uictr uic0tr
-#define uicmsr uic0msr
-#define uicvr uic0vr
-#define uicvcr uic0vcr
-
-/* the interrupt vector definitions */
-#define VECNUM_MAL_SERR 10
-#define VECNUM_MAL_TXEOB 11
-#define VECNUM_MAL_RXEOB 12
-#define VECNUM_MAL_TXDE 13
-#define VECNUM_MAL_RXDE 14
-#define VECNUM_ETH0 15
-#define VECNUM_ETH1_OFFS 2
-#define VECNUM_EIRQ6 29
-
-/*
- * Mask definitions (used for example in 4xx_enet.c)
- */
-#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f))
-/* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */
-#define UIC_NR(vec) ((vec) >> 5)
-
-#endif /* _PPC4xx_UIC_H_ */
+#ifndef _PPC4xx_UIC_H_ +#define _PPC4xx_UIC_H_ + +/* + * Define the number of UIC's + */ +#define UIC_MAX 1 +#define IRQ_MAX UIC_MAX * 32 + +/* UIC0 dcr base address */ +#define UIC0_DCR_BASE 0xc0 + +/* + * UIC register + */ +#define UIC_SR 0x0 /* UIC status */ +#define UIC_ER 0x2 /* UIC enable */ +#define UIC_CR 0x3 /* UIC critical */ +#define UIC_PR 0x4 /* UIC polarity */ +#define UIC_TR 0x5 /* UIC triggering */ +#define UIC_MSR 0x6 /* UIC masked status */ +#define UIC_VR 0x7 /* UIC vector */ +#define UIC_VCR 0x8 /* UIC vector configuration */ + +#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ +#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ +#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ +#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ +#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ +#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ +#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ +#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ + +/* The following is for compatibility with 405 code */ +#define uicsr uic0sr +#define uicer uic0er +#define uiccr uic0cr +#define uicpr uic0pr +#define uictr uic0tr +#define uicmsr uic0msr +#define uicvr uic0vr +#define uicvcr uic0vcr + +/* the interrupt vector definitions */ +#define VECNUM_MAL_SERR 10 +#define VECNUM_MAL_TXEOB 11 +#define VECNUM_MAL_RXEOB 12 +#define VECNUM_MAL_TXDE 13 +#define VECNUM_MAL_RXDE 14 +#define VECNUM_ETH0 15 +#define VECNUM_ETH1_OFFS 2 +#define VECNUM_EIRQ6 29 + +/* + * Mask definitions (used for example in 4xx_enet.c) + */ +#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f)) +/* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */ +#define UIC_NR(vec) ((vec) >> 5) + +#endif /* _PPC4xx_UIC_H_ */ diff --git a/libcpu/ppc/ppc405/include/asm/ppc4xx.h b/libcpu/ppc/ppc405/include/asm/ppc4xx.h index bf055f0879..57fe7ab221 100644 --- a/libcpu/ppc/ppc405/include/asm/ppc4xx.h +++ b/libcpu/ppc/ppc405/include/asm/ppc4xx.h @@ -1,134 +1,134 @@ -/*----------------------------------------------------------------------------+
-|
-| This source code has been made available to you by IBM on an AS-IS
-| basis. Anyone receiving this source is licensed under IBM
-| copyrights to use it in any way he or she deems fit, including
-| copying it, modifying it, compiling it, and redistributing it either
-| with or without modifications. No license under IBM patents or
-| patent applications is to be implied by the copyright license.
-|
-| Any user of this software should understand that IBM cannot provide
-| technical support for this software and will not be responsible for
-| any consequences resulting from the use of this software.
-|
-| Any person who transfers this source code or any derivative work
-| must include the IBM copyright notice, this paragraph, and the
-| preceding two paragraphs in the transferred software.
-|
-| COPYRIGHT I B M CORPORATION 1999
-| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
-+----------------------------------------------------------------------------*/
-
-#ifndef __PPC4XX_H__
-#define __PPC4XX_H__
-
-/*
- * Configure which SDRAM/DDR/DDR2 controller is equipped
- */
-#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
-
-#include <asm/ppc405.h>
-#include <asm/ppc4xx-uic.h>
-
-/*
- * Macro for generating register field mnemonics
- */
-#define PPC_REG_BITS 32
-#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
-
-/*
- * Elide casts when assembling register mnemonics
- */
-#ifndef __ASSEMBLY__
-#define static_cast(type, val) (type)(val)
-#else
-#define static_cast(type, val) (val)
-#endif
-
-/*
- * Common stuff for 4xx (405 and 440)
- */
-
-#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
-#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
-
-#define RESET_VECTOR 0xfffffffc
-#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache
- line aligned data. */
-
-#define CPR0_DCR_BASE 0x0C
-#define cprcfga (CPR0_DCR_BASE+0x0)
-#define cprcfgd (CPR0_DCR_BASE+0x1)
-
-#define SDR_DCR_BASE 0x0E
-#define sdrcfga (SDR_DCR_BASE+0x0)
-#define sdrcfgd (SDR_DCR_BASE+0x1)
-
-#define SDRAM_DCR_BASE 0x10
-#define memcfga (SDRAM_DCR_BASE+0x0)
-#define memcfgd (SDRAM_DCR_BASE+0x1)
-
-#define EBC_DCR_BASE 0x12
-#define ebccfga (EBC_DCR_BASE+0x0)
-#define ebccfgd (EBC_DCR_BASE+0x1)
-
-/*
- * Macros for indirect DCR access
- */
-#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0)
-#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0)
-
-#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0)
-#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0)
-
-#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0)
-#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0)
-
-#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0)
-#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0)
-
-#ifndef __ASSEMBLY__
-
-typedef struct
-{
- unsigned long freqDDR;
- unsigned long freqEBC;
- unsigned long freqOPB;
- unsigned long freqPCI;
- unsigned long freqPLB;
- unsigned long freqTmrClk;
- unsigned long freqUART;
- unsigned long freqProcessor;
- unsigned long freqVCOHz;
- unsigned long freqVCOMhz; /* in MHz */
- unsigned long pciClkSync; /* PCI clock is synchronous */
- unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
- unsigned long pllExtBusDiv;
- unsigned long pllFbkDiv;
- unsigned long pllFwdDiv;
- unsigned long pllFwdDivA;
- unsigned long pllFwdDivB;
- unsigned long pllOpbDiv;
- unsigned long pllPciDiv;
- unsigned long pllPlbDiv;
-} PPC4xx_SYS_INFO;
-
-static inline rt_uint32_t get_mcsr(void)
-{
- rt_uint32_t val;
-
- asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
- return val;
-}
-
-static inline void set_mcsr(rt_uint32_t val)
-{
- asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
-}
-
-#endif /* __ASSEMBLY__ */
-
-/* for multi-cpu support */
-#define NA_OR_UNKNOWN_CPU -1
-
-#endif /* __PPC4XX_H__ */
+/*----------------------------------------------------------------------------+ +| +| This source code has been made available to you by IBM on an AS-IS +| basis. Anyone receiving this source is licensed under IBM +| copyrights to use it in any way he or she deems fit, including +| copying it, modifying it, compiling it, and redistributing it either +| with or without modifications. No license under IBM patents or +| patent applications is to be implied by the copyright license. +| +| Any user of this software should understand that IBM cannot provide +| technical support for this software and will not be responsible for +| any consequences resulting from the use of this software. +| +| Any person who transfers this source code or any derivative work +| must include the IBM copyright notice, this paragraph, and the +| preceding two paragraphs in the transferred software. +| +| COPYRIGHT I B M CORPORATION 1999 +| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M ++----------------------------------------------------------------------------*/ + +#ifndef __PPC4XX_H__ +#define __PPC4XX_H__ + +/* + * Configure which SDRAM/DDR/DDR2 controller is equipped + */ +#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */ + +#include <asm/ppc405.h> +#include <asm/ppc4xx-uic.h> + +/* + * Macro for generating register field mnemonics + */ +#define PPC_REG_BITS 32 +#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit))) + +/* + * Elide casts when assembling register mnemonics + */ +#ifndef __ASSEMBLY__ +#define static_cast(type, val) (type)(val) +#else +#define static_cast(type, val) (val) +#endif + +/* + * Common stuff for 4xx (405 and 440) + */ + +#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ +#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) + +#define RESET_VECTOR 0xfffffffc +#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache + line aligned data. */ + +#define CPR0_DCR_BASE 0x0C +#define cprcfga (CPR0_DCR_BASE+0x0) +#define cprcfgd (CPR0_DCR_BASE+0x1) + +#define SDR_DCR_BASE 0x0E +#define sdrcfga (SDR_DCR_BASE+0x0) +#define sdrcfgd (SDR_DCR_BASE+0x1) + +#define SDRAM_DCR_BASE 0x10 +#define memcfga (SDRAM_DCR_BASE+0x0) +#define memcfgd (SDRAM_DCR_BASE+0x1) + +#define EBC_DCR_BASE 0x12 +#define ebccfga (EBC_DCR_BASE+0x0) +#define ebccfgd (EBC_DCR_BASE+0x1) + +/* + * Macros for indirect DCR access + */ +#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0) +#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0) + +#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0) +#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0) + +#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0) +#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0) + +#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0) +#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0) + +#ifndef __ASSEMBLY__ + +typedef struct +{ + unsigned long freqDDR; + unsigned long freqEBC; + unsigned long freqOPB; + unsigned long freqPCI; + unsigned long freqPLB; + unsigned long freqTmrClk; + unsigned long freqUART; + unsigned long freqProcessor; + unsigned long freqVCOHz; + unsigned long freqVCOMhz; /* in MHz */ + unsigned long pciClkSync; /* PCI clock is synchronous */ + unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ + unsigned long pllExtBusDiv; + unsigned long pllFbkDiv; + unsigned long pllFwdDiv; + unsigned long pllFwdDivA; + unsigned long pllFwdDivB; + unsigned long pllOpbDiv; + unsigned long pllPciDiv; + unsigned long pllPlbDiv; +} PPC4xx_SYS_INFO; + +static inline rt_uint32_t get_mcsr(void) +{ + rt_uint32_t val; + + asm volatile("mfspr %0, 0x23c" : "=r" (val) :); + return val; +} + +static inline void set_mcsr(rt_uint32_t val) +{ + asm volatile("mtspr 0x23c, %0" : "=r" (val) :); +} + +#endif /* __ASSEMBLY__ */ + +/* for multi-cpu support */ +#define NA_OR_UNKNOWN_CPU -1 + +#endif /* __PPC4XX_H__ */ diff --git a/libcpu/ppc/ppc405/include/asm/ppc_defs.h b/libcpu/ppc/ppc405/include/asm/ppc_defs.h index dd1e42a925..88aed26009 100644 --- a/libcpu/ppc/ppc405/include/asm/ppc_defs.h +++ b/libcpu/ppc/ppc405/include/asm/ppc_defs.h @@ -1,73 +1,73 @@ -/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, [email protected].
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * WARNING! This file is automatically generated - DO NOT EDIT!
- */
-#define STACK_FRAME_OVERHEAD 16
-#define INT_FRAME_SIZE 192
-#define GPR0 16
-#define GPR1 20
-#define GPR2 24
-#define GPR3 28
-#define GPR4 32
-#define GPR5 36
-#define GPR6 40
-#define GPR7 44
-#define GPR8 48
-#define GPR9 52
-#define GPR10 56
-#define GPR11 60
-#define GPR12 64
-#define GPR13 68
-#define GPR14 72
-#define GPR15 76
-#define GPR16 80
-#define GPR17 84
-#define GPR18 88
-#define GPR19 92
-#define GPR20 96
-#define GPR21 100
-#define GPR22 104
-#define GPR23 108
-#define GPR24 112
-#define GPR25 116
-#define GPR26 120
-#define GPR27 124
-#define GPR28 128
-#define GPR29 132
-#define GPR30 136
-#define GPR31 140
-#define _NIP 144
-#define _MSR 148
-#define ORIG_GPR3 152
-#define _CTR 156
-#define _LINK 160
-#define _XER 164
-#define _CCR 168
-#define _MQ 172
-#define TRAP 176
-#define _DAR 180
-#define _DSISR 184
-#define RESULT 188
-
+/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, [email protected]. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * WARNING! This file is automatically generated - DO NOT EDIT! + */ +#define STACK_FRAME_OVERHEAD 16 +#define INT_FRAME_SIZE 192 +#define GPR0 16 +#define GPR1 20 +#define GPR2 24 +#define GPR3 28 +#define GPR4 32 +#define GPR5 36 +#define GPR6 40 +#define GPR7 44 +#define GPR8 48 +#define GPR9 52 +#define GPR10 56 +#define GPR11 60 +#define GPR12 64 +#define GPR13 68 +#define GPR14 72 +#define GPR15 76 +#define GPR16 80 +#define GPR17 84 +#define GPR18 88 +#define GPR19 92 +#define GPR20 96 +#define GPR21 100 +#define GPR22 104 +#define GPR23 108 +#define GPR24 112 +#define GPR25 116 +#define GPR26 120 +#define GPR27 124 +#define GPR28 128 +#define GPR29 132 +#define GPR30 136 +#define GPR31 140 +#define _NIP 144 +#define _MSR 148 +#define ORIG_GPR3 152 +#define _CTR 156 +#define _LINK 160 +#define _XER 164 +#define _CCR 168 +#define _MQ 172 +#define TRAP 176 +#define _DAR 180 +#define _DSISR 184 +#define RESULT 188 + diff --git a/libcpu/ppc/ppc405/include/asm/processor.h b/libcpu/ppc/ppc405/include/asm/processor.h index fead870558..7aeeb01dc5 100644 --- a/libcpu/ppc/ppc405/include/asm/processor.h +++ b/libcpu/ppc/ppc405/include/asm/processor.h @@ -1,1238 +1,1238 @@ -#ifndef __ASM_PPC_PROCESSOR_H
-#define __ASM_PPC_PROCESSOR_H
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
-
-#include <config.h>
-
-#include <asm/ptrace.h>
-#include <asm/types.h>
-
-/* Machine State Register (MSR) Fields */
-
-#ifdef CONFIG_PPC64BRIDGE
-#define MSR_SF (1<<63)
-#define MSR_ISF (1<<61)
-#endif /* CONFIG_PPC64BRIDGE */
-#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
-#define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */
-#define MSR_SPE (1<<25) /* Enable SPE(e500) */
-#define MSR_POW (1<<18) /* Enable Power Management */
-#define MSR_WE (1<<18) /* Wait State Enable */
-#define MSR_TGPR (1<<17) /* TLB Update registers in use */
-#define MSR_CE (1<<17) /* Critical Interrupt Enable */
-#define MSR_ILE (1<<16) /* Interrupt Little Endian */
-#define MSR_EE (1<<15) /* External Interrupt Enable */
-#define MSR_PR (1<<14) /* Problem State / Privilege Level */
-#define MSR_FP (1<<13) /* Floating Point enable */
-#define MSR_ME (1<<12) /* Machine Check Enable */
-#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
-#define MSR_SE (1<<10) /* Single Step */
-#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
-#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
-#define MSR_BE (1<<9) /* Branch Trace */
-#define MSR_DE (1<<9) /* Debug Exception Enable */
-#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
-#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
-#define MSR_IR (1<<5) /* Instruction Relocate */
-#define MSR_IS (1<<5) /* Book E Instruction space */
-#define MSR_DR (1<<4) /* Data Relocate */
-#define MSR_DS (1<<4) /* Book E Data space */
-#define MSR_PE (1<<3) /* Protection Enable */
-#define MSR_PX (1<<2) /* Protection Exclusive Mode */
-#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */
-#define MSR_RI (1<<1) /* Recoverable Exception */
-#define MSR_LE (1<<0) /* Little Endian */
-
-#ifdef CONFIG_APUS_FAST_EXCEPT
-#define MSR_ MSR_ME|MSR_IP|MSR_RI
-#else
-#define MSR_ MSR_ME|MSR_RI
-#endif
-
-#ifndef CONFIG_E500
-#define MSR_KERNEL MSR_|MSR_IR|MSR_DR
-#else
-#define MSR_KERNEL MSR_ME
-#endif
-
-/* Floating Point Status and Control Register (FPSCR) Fields */
-
-#define FPSCR_FX 0x80000000 /* FPU exception summary */
-#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
-#define FPSCR_VX 0x20000000 /* Invalid operation summary */
-#define FPSCR_OX 0x10000000 /* Overflow exception summary */
-#define FPSCR_UX 0x08000000 /* Underflow exception summary */
-#define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
-#define FPSCR_XX 0x02000000 /* Inexact exception summary */
-#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
-#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
-#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
-#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
-#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
-#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
-#define FPSCR_FR 0x00040000 /* Fraction rounded */
-#define FPSCR_FI 0x00020000 /* Fraction inexact */
-#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
-#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
-#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
-#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
-#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
-#define FPSCR_VE 0x00000080 /* Invalid op exception enable */
-#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
-#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
-#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
-#define FPSCR_XE 0x00000008 /* FP inexact exception enable */
-#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
-#define FPSCR_RN 0x00000003 /* FPU rounding control */
-
-/* Special Purpose Registers (SPRNs)*/
-
-/* PPC440 Architecture is BOOK-E */
-#ifdef CONFIG_440
-#define CONFIG_BOOKE
-#endif
-
-#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
-#ifdef CONFIG_BOOKE
-#define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */
-#endif
-#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
-#define SPRN_CTR 0x009 /* Count Register */
-#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
-#ifndef CONFIG_BOOKE
-#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
-#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
-#else
-#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */
-#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */
-#endif /* CONFIG_BOOKE */
-#define SPRN_DAR 0x013 /* Data Address Register */
-#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
-#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
-#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
-#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
-#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
-#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
-#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
-#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
-#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
-#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
-#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
-#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
-#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
-#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
-#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
-#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */
-#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
-#define DBCR_EDM 0x80000000
-#define DBCR_IDM 0x40000000
-#define DBCR_RST(x) (((x) & 0x3) << 28)
-#define DBCR_RST_NONE 0
-#define DBCR_RST_CORE 1
-#define DBCR_RST_CHIP 2
-#define DBCR_RST_SYSTEM 3
-#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
-#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
-#define DBCR_EDE 0x02000000 /* Exception Debug Event */
-#define DBCR_TDE 0x01000000 /* TRAP Debug Event */
-#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
-#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
-#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
-#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
-#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
-#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
-#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
-#define DAC_BYTE 0
-#define DAC_HALF 1
-#define DAC_WORD 2
-#define DAC_QUAD 3
-#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
-#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
-#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
-#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
-#define DBCR_SED 0x00000020 /* Second Exception Debug Event */
-#define DBCR_STD 0x00000010 /* Second Trap Debug Event */
-#define DBCR_SIA 0x00000008 /* Second IAC Enable */
-#define DBCR_SDA 0x00000004 /* Second DAC Enable */
-#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
-#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
-#ifndef CONFIG_BOOKE
-#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
-#else
-#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */
-#endif /* CONFIG_BOOKE */
-#ifndef CONFIG_BOOKE
-#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
-#define SPRN_DBSR 0x3F0 /* Debug Status Register */
-#else
-#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */
-#ifdef CONFIG_BOOKE
-#define SPRN_DBDR 0x3f3 /* Debug Data Register */
-#endif
-#define SPRN_DBSR 0x130 /* Book E Debug Status Register */
-#define DBSR_IC 0x08000000 /* Book E Instruction Completion */
-#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */
-#endif /* CONFIG_BOOKE */
-#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
-#define DCCR_NOCACHE 0 /* Noncacheable */
-#define DCCR_CACHE 1 /* Cacheable */
-#ifndef CONFIG_BOOKE
-#define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */
-#define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */
-#endif
-#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
-#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
-#define DCWR_COPY 0 /* Copy-back */
-#define DCWR_WRITE 1 /* Write-through */
-#ifndef CONFIG_BOOKE
-#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
-#else
-#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */
-#endif /* CONFIG_BOOKE */
-#define SPRN_DEC 0x016 /* Decrement Register */
-#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
-#ifdef CONFIG_BOOKE
-#define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */
-#define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */
-#define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */
-#define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */
-#endif
-#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
-#ifdef CONFIG_BOOKE
-#define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */
-#define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */
-#define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */
-#define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */
-#define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */
-#endif
-#define SPRN_EAR 0x11A /* External Address Register */
-#ifndef CONFIG_BOOKE
-#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
-#else
-#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */
-#endif /* CONFIG_BOOKE */
-#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
-#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
-#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
-#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
-#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
-#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
-#define ESR_PTR 0x02000000 /* Program Exception - Trap */
-#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
-#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
-#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
-#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
-#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
-#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
-
-#define HID0_ICE_SHIFT 15
-#define HID0_DCE_SHIFT 14
-#define HID0_DLOCK_SHIFT 12
-
-#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
-#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
-#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
-#define HID0_SBCLK (1<<27)
-#define HID0_EICE (1<<26)
-#define HID0_ECLK (1<<25)
-#define HID0_PAR (1<<24)
-#define HID0_DOZE (1<<23)
-#define HID0_NAP (1<<22)
-#define HID0_SLEEP (1<<21)
-#define HID0_DPM (1<<20)
-#define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */
-#define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */
-#define HID0_TBEN (1<<14) /* Time Base Enable */
-#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
-#define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */
-#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
-#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */
-#define HID0_DCI HID0_DCFI
-#define HID0_SPD (1<<9) /* Speculative disable */
-#define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */
-#define HID0_SGE (1<<7) /* Store Gathering Enable */
-#define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */
-#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
-#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */
-#define HID0_ABE (1<<3) /* Address Broadcast Enable */
-#define HID0_BHTE (1<<2) /* Branch History Table Enable */
-#define HID0_BTCD (1<<1) /* Branch target cache disable */
-#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
-#define HID1_RFXE (1<<17) /* Read Fault Exception Enable */
-#define HID1_ASTME (1<<13) /* Address bus streaming mode */
-#define HID1_ABE (1<<12) /* Address broadcast enable */
-#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
-#ifndef CONFIG_BOOKE
-#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
-#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
-#else
-#define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */
-#define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */
-#endif /* CONFIG_BOOKE */
-#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
-#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
-#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
-#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
-#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
-#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
-#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
-#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
-#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
-#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
-#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
-#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
-#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
-#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
-#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
-#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
-#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
-#define ICCR_NOCACHE 0 /* Noncacheable */
-#define ICCR_CACHE 1 /* Cacheable */
-#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
-#ifdef CONFIG_BOOKE
-#define SPRN_ICDBTRL 0x39e /* instruction cache debug tag register low */
-#define SPRN_ICDBTRH 0x39f /* instruction cache debug tag register high */
-#endif
-#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
-#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
-#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
-#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
-#ifdef CONFIG_BOOKE
-#define SPRN_INV0 0x370 /* Instruction Cache Normal Victim 0 */
-#define SPRN_INV1 0x371 /* Instruction Cache Normal Victim 1 */
-#define SPRN_INV2 0x372 /* Instruction Cache Normal Victim 2 */
-#define SPRN_INV3 0x373 /* Instruction Cache Normal Victim 3 */
-#define SPRN_ITV0 0x374 /* Instruction Cache Transient Victim 0 */
-#define SPRN_ITV1 0x375 /* Instruction Cache Transient Victim 1 */
-#define SPRN_ITV2 0x376 /* Instruction Cache Transient Victim 2 */
-#define SPRN_ITV3 0x377 /* Instruction Cache Transient Victim 3 */
-#define SPRN_IVLIM 0x399 /* Instruction Cache Victim Limit */
-#endif
-#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
-#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
-#define SPRN_LR 0x008 /* Link Register */
-#define SPRN_MBAR 0x137 /* System memory base address */
-#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
-#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
-#ifdef CONFIG_BOOKE
-#define SPRN_MMUCR 0x3b2 /* MMU Control Register */
-#endif
-#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
-#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
-#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
-#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
-#ifndef CONFIG_BOOKE
-#define SPRN_PID 0x3B1 /* Process ID */
-#define SPRN_PIR 0x3FF /* Processor Identification Register */
-#else
-#define SPRN_PID 0x030 /* Book E Process ID */
-#define SPRN_PIR 0x11E /* Book E Processor Identification Register */
-#endif /* CONFIG_BOOKE */
-#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
-#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
-#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
-#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */
-#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
-#define SPRN_PVR 0x11F /* Processor Version Register */
-#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
-#ifdef CONFIG_BOOKE
-#define SPRN_RSTCFG 0x39b /* Reset Configuration */
-#endif
-#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
-#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
-#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
-#define SGR_NORMAL 0
-#define SGR_GUARDED 1
-#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
-#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
-#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
-#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
-#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
-#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
-#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
-#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
-#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
-#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
-#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
-#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
-#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
-
-#ifdef CONFIG_BOOKE
-#define SPRN_SVR 0x3FF /* System Version Register */
-#else
-#define SPRN_SVR 0x11E /* System Version Register */
-#endif
-#define SPRN_TBHI 0x3DC /* Time Base High */
-#define SPRN_TBHU 0x3CC /* Time Base High User-mode */
-#define SPRN_TBLO 0x3DD /* Time Base Low */
-#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
-#define SPRN_TBRL 0x10C /* Time Base Read Lower Register */
-#define SPRN_TBRU 0x10D /* Time Base Read Upper Register */
-#define SPRN_TBWL 0x11C /* Time Base Write Lower Register */
-#define SPRN_TBWU 0x11D /* Time Base Write Upper Register */
-#ifndef CONFIG_BOOKE
-#define SPRN_TCR 0x3DA /* Timer Control Register */
-#else
-#define SPRN_TCR 0x154 /* Book E Timer Control Register */
-#endif /* CONFIG_BOOKE */
-#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
-#define WP_2_17 0 /* 2^17 clocks */
-#define WP_2_21 1 /* 2^21 clocks */
-#define WP_2_25 2 /* 2^25 clocks */
-#define WP_2_29 3 /* 2^29 clocks */
-#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
-#define WRC_NONE 0 /* No reset will occur */
-#define WRC_CORE 1 /* Core reset will occur */
-#define WRC_CHIP 2 /* Chip reset will occur */
-#define WRC_SYSTEM 3 /* System reset will occur */
-#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
-#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
-#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
-#define FP_2_9 0 /* 2^9 clocks */
-#define FP_2_13 1 /* 2^13 clocks */
-#define FP_2_17 2 /* 2^17 clocks */
-#define FP_2_21 3 /* 2^21 clocks */
-#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
-#define TCR_ARE 0x00400000 /* Auto Reload Enable */
-#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
-#define THRM1_TIN (1<<0)
-#define THRM1_TIV (1<<1)
-#define THRM1_THRES (0x7f<<2)
-#define THRM1_TID (1<<29)
-#define THRM1_TIE (1<<30)
-#define THRM1_V (1<<31)
-#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
-#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
-#define THRM3_E (1<<31)
-#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
-#ifndef CONFIG_BOOKE
-#define SPRN_TSR 0x3D8 /* Timer Status Register */
-#else
-#define SPRN_TSR 0x150 /* Book E Timer Status Register */
-#endif /* CONFIG_BOOKE */
-#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
-#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
-#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
-#define WRS_NONE 0 /* No WDT reset occurred */
-#define WRS_CORE 1 /* WDT forced core reset */
-#define WRS_CHIP 2 /* WDT forced chip reset */
-#define WRS_SYSTEM 3 /* WDT forced system reset */
-#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
-#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
-#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
-#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
-#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
-#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
-#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
-#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
-#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
-#define SPRN_XER 0x001 /* Fixed Point Exception Register */
-#define SPRN_ZPR 0x3B0 /* Zone Protection Register */
-
-/* Book E definitions */
-#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
-#define SPRN_CSRR0 0x03A /* Critical SRR0 */
-#define SPRN_CSRR1 0x03B /* Critical SRR0 */
-#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
-#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
-#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
-#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
-#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
-#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
-#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
-#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
-#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
-#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
-#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
-#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
-#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
-#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
-#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
-#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
-#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
-#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
-#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
-#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
-#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
-#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
-#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
-#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
-#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
-#define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */
-#define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */
-#define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */
-#define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */
-#define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */
-#define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */
-
-/* e500 definitions */
-#define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */
-#define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */
-#define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */
-#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */
-#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
-#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
-#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
-#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */
-#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
-#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
-#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
-#define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */
-#define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */
-#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
-#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
-#define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */
-#define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */
-#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */
-#define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */
-#define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */
-#define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */
-#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */
-#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */
-#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */
-#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */
-#define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */
-
-#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
-#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
-#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
-#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
-#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
-#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
-#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
-#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
-#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
-#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
-#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
-
-#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
-#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
-#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
-#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
-#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
-
-#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */
-#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */
-#define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */
-#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
-#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
-#define SPRN_PID1 0x279 /* Process ID Register 1 */
-#define SPRN_PID2 0x27a /* Process ID Register 2 */
-#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
-#define SPRN_MCAR 0x23d /* Machine Check Address register */
-#define MCSR_MCS 0x80000000 /* Machine Check Summary */
-#define MCSR_IB 0x40000000 /* Instruction PLB Error */
-#if defined(CONFIG_440)
-#define MCSR_DRB 0x20000000 /* Data Read PLB Error */
-#define MCSR_DWB 0x10000000 /* Data Write PLB Error */
-#else
-#define MCSR_DB 0x20000000 /* Data PLB Error */
-#endif /* defined(CONFIG_440) */
-#define MCSR_TLBP 0x08000000 /* TLB Parity Error */
-#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
-#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
-#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
-#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
-#define ESR_ST 0x00800000 /* Store Operation */
-
-#if defined(CONFIG_MPC86xx)
-#define SPRN_MSSCR0 0x3f6
-#define SPRN_MSSSR0 0x3f7
-#endif
-
-/* Short-hand versions for a number of the above SPRNs */
-
-#define CTR SPRN_CTR /* Counter Register */
-#define DAR SPRN_DAR /* Data Address Register */
-#define DABR SPRN_DABR /* Data Address Breakpoint Register */
-#define DAC1 SPRN_DAC1 /* Data Address Register 1 */
-#define DAC2 SPRN_DAC2 /* Data Address Register 2 */
-#define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */
-#define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */
-#define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */
-#define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */
-#define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */
-#define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */
-#define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */
-#define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */
-#define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */
-#define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */
-#define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */
-#define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */
-#define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */
-#define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */
-#define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */
-#define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */
-#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */
-#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */
-#define DBSR SPRN_DBSR /* Debug Status Register */
-#define DCMP SPRN_DCMP /* Data TLB Compare Register */
-#define DEC SPRN_DEC /* Decrement Register */
-#define DMISS SPRN_DMISS /* Data TLB Miss Register */
-#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
-#define EAR SPRN_EAR /* External Address Register */
-#define ESR SPRN_ESR /* Exception Syndrome Register */
-#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
-#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
-#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
-#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */
-#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
-#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */
-#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */
-#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */
-#define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */
-#define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */
-#define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */
-#define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */
-#define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */
-#define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */
-#define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */
-#define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */
-#define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */
-#define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */
-#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */
-#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */
-#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */
-#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
-#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */
-#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
-#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
-#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
-#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
-#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
-#define LR SPRN_LR
-#define MBAR SPRN_MBAR /* System memory base address */
-#if defined(CONFIG_MPC86xx)
-#define MSSCR0 SPRN_MSSCR0
-#endif
-#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
-#define PIR SPRN_PIR
-#endif
-#define SVR SPRN_SVR /* System-On-Chip Version Register */
-#define PVR SPRN_PVR /* Processor Version */
-#define RPA SPRN_RPA /* Required Physical Address Register */
-#define SDR1 SPRN_SDR1 /* MMU hash base register */
-#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
-#define SPR1 SPRN_SPRG1
-#define SPR2 SPRN_SPRG2
-#define SPR3 SPRN_SPRG3
-#define SPRG0 SPRN_SPRG0
-#define SPRG1 SPRN_SPRG1
-#define SPRG2 SPRN_SPRG2
-#define SPRG3 SPRN_SPRG3
-#define SPRG4 SPRN_SPRG4
-#define SPRG5 SPRN_SPRG5
-#define SPRG6 SPRN_SPRG6
-#define SPRG7 SPRN_SPRG7
-#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
-#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
-#define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */
-#define SRR3 SPRN_SRR3 /* Save and Restore Register 3 */
-#define SVR SPRN_SVR /* System Version Register */
-#define TBRL SPRN_TBRL /* Time Base Read Lower Register */
-#define TBRU SPRN_TBRU /* Time Base Read Upper Register */
-#define TBWL SPRN_TBWL /* Time Base Write Lower Register */
-#define TBWU SPRN_TBWU /* Time Base Write Upper Register */
-#define TCR SPRN_TCR /* Timer Control Register */
-#define TSR SPRN_TSR /* Timer Status Register */
-#define ICTC 1019
-#define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */
-#define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */
-#define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */
-#define XER SPRN_XER
-
-#define DECAR SPRN_DECAR
-#define CSRR0 SPRN_CSRR0
-#define CSRR1 SPRN_CSRR1
-#define IVPR SPRN_IVPR
-#define USPRG0 SPRN_USPRG
-#define SPRG4R SPRN_SPRG4R
-#define SPRG5R SPRN_SPRG5R
-#define SPRG6R SPRN_SPRG6R
-#define SPRG7R SPRN_SPRG7R
-#define SPRG4W SPRN_SPRG4W
-#define SPRG5W SPRN_SPRG5W
-#define SPRG6W SPRN_SPRG6W
-#define SPRG7W SPRN_SPRG7W
-#define DEAR SPRN_DEAR
-#define DBCR2 SPRN_DBCR2
-#define IAC3 SPRN_IAC3
-#define IAC4 SPRN_IAC4
-#define DVC1 SPRN_DVC1
-#define DVC2 SPRN_DVC2
-#define IVOR0 SPRN_IVOR0
-#define IVOR1 SPRN_IVOR1
-#define IVOR2 SPRN_IVOR2
-#define IVOR3 SPRN_IVOR3
-#define IVOR4 SPRN_IVOR4
-#define IVOR5 SPRN_IVOR5
-#define IVOR6 SPRN_IVOR6
-#define IVOR7 SPRN_IVOR7
-#define IVOR8 SPRN_IVOR8
-#define IVOR9 SPRN_IVOR9
-#define IVOR10 SPRN_IVOR10
-#define IVOR11 SPRN_IVOR11
-#define IVOR12 SPRN_IVOR12
-#define IVOR13 SPRN_IVOR13
-#define IVOR14 SPRN_IVOR14
-#define IVOR15 SPRN_IVOR15
-#define IVOR32 SPRN_IVOR32
-#define IVOR33 SPRN_IVOR33
-#define IVOR34 SPRN_IVOR34
-#define IVOR35 SPRN_IVOR35
-#define MCSRR0 SPRN_MCSRR0
-#define MCSRR1 SPRN_MCSRR1
-#define L1CSR0 SPRN_L1CSR0
-#define L1CSR1 SPRN_L1CSR1
-#define L1CSR2 SPRN_L1CSR2
-#define L1CFG0 SPRN_L1CFG0
-#define L1CFG1 SPRN_L1CFG1
-#define L2CFG0 SPRN_L2CFG0
-#define L2CSR0 SPRN_L2CSR0
-#define L2CSR1 SPRN_L2CSR1
-#define MCSR SPRN_MCSR
-#define MMUCSR0 SPRN_MMUCSR0
-#define BUCSR SPRN_BUCSR
-#define PID0 SPRN_PID
-#define PID1 SPRN_PID1
-#define PID2 SPRN_PID2
-#define MAS0 SPRN_MAS0
-#define MAS1 SPRN_MAS1
-#define MAS2 SPRN_MAS2
-#define MAS3 SPRN_MAS3
-#define MAS4 SPRN_MAS4
-#define MAS5 SPRN_MAS5
-#define MAS6 SPRN_MAS6
-#define MAS7 SPRN_MAS7
-
-#if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx)
-#define DAR_DEAR DEAR
-#else
-#define DAR_DEAR DAR
-#endif
-
-/* Device Control Registers */
-
-#define DCRN_BEAR 0x090 /* Bus Error Address Register */
-#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */
-#define BESR_DSES 0x80000000 /* Data-Side Error Status */
-#define BESR_DMES 0x40000000 /* DMA Error Status */
-#define BESR_RWS 0x20000000 /* Read/Write Status */
-#define BESR_ETMASK 0x1C000000 /* Error Type */
-#define ET_PROT 0
-#define ET_PARITY 1
-#define ET_NCFG 2
-#define ET_BUSERR 4
-#define ET_BUSTO 6
-#define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */
-#define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */
-#define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */
-#define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */
-#define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */
-#define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */
-#define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */
-#define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */
-#define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */
-#define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */
-#define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */
-#define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */
-#define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */
-#define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */
-#define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */
-#define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */
-#define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */
-#define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */
-#define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */
-#define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */
-#define DCRN_DMASR 0x0E0 /* DMA Status Register */
-#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */
-#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */
-#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */
-#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */
-#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */
-#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */
-#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */
-#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */
-#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */
-#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */
-#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */
-#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */
-#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */
-#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */
-#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */
-#define DCRN_EXISR 0x040 /* External Interrupt Status Register */
-#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */
-#define IOCR_E0TE 0x80000000
-#define IOCR_E0LP 0x40000000
-#define IOCR_E1TE 0x20000000
-#define IOCR_E1LP 0x10000000
-#define IOCR_E2TE 0x08000000
-#define IOCR_E2LP 0x04000000
-#define IOCR_E3TE 0x02000000
-#define IOCR_E3LP 0x01000000
-#define IOCR_E4TE 0x00800000
-#define IOCR_E4LP 0x00400000
-#define IOCR_EDT 0x00080000
-#define IOCR_SOR 0x00040000
-#define IOCR_EDO 0x00008000
-#define IOCR_2XC 0x00004000
-#define IOCR_ATC 0x00002000
-#define IOCR_SPD 0x00001000
-#define IOCR_BEM 0x00000800
-#define IOCR_PTD 0x00000400
-#define IOCR_ARE 0x00000080
-#define IOCR_DRC 0x00000020
-#define IOCR_RDM(x) (((x) & 0x3) << 3)
-#define IOCR_TCS 0x00000004
-#define IOCR_SCS 0x00000002
-#define IOCR_SPC 0x00000001
-
-/* System-On-Chip Version Register */
-
-/* System-On-Chip Version Register (SVR) field extraction */
-
-#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
-#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
-
-#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */
-#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */
-#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */
-#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */
-#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */
-#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */
-#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */
-
-/* Processor Version Register */
-
-/* Processor Version Register (PVR) field extraction */
-
-#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
-#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
-
-/*
- * AMCC has further subdivided the standard PowerPC 16-bit version and
- * revision subfields of the PVR for the PowerPC 403s into the following:
- */
-
-#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
-#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
-#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
-#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
-#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
-#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
-
-/* e600 core PVR fields */
-
-#define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */
-#define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */
-#define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */
-#define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */
-
-/* Processor Version Numbers */
-
-#define PVR_403GA 0x00200000
-#define PVR_403GB 0x00200100
-#define PVR_403GC 0x00200200
-#define PVR_403GCX 0x00201400
-#define PVR_405GP 0x40110000
-#define PVR_405GP_RB 0x40110040
-#define PVR_405GP_RC 0x40110082
-#define PVR_405GP_RD 0x401100C4
-#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */
-#define PVR_405CR_RA 0x40110041
-#define PVR_405CR_RB 0x401100C5
-#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */
-#define PVR_405EP_RA 0x51210950
-#define PVR_405GPR_RB 0x50910951
-#define PVR_405EZ_RA 0x41511460
-#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A/B with Security */
-#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */
-#define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */
-#define PVR_405EX2_RA 0x12911475 /* 405EX rev A/B without Security */
-#define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */
-#define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */
-#define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */
-#define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */
-#define PVR_440GP_RB 0x40120440
-#define PVR_440GP_RC 0x40120481
-#define PVR_440EP_RA 0x42221850
-#define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
-#define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
-#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
-#define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
-#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */
-#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */
-#define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */
-#define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */
-#define PVR_440GX_RA 0x51B21850
-#define PVR_440GX_RB 0x51B21851
-#define PVR_440GX_RC 0x51B21892
-#define PVR_440GX_RF 0x51B21894
-#define PVR_405EP_RB 0x51210950
-#define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */
-#define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */
-#define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */
-#define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */
-#define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */
-#define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */
-#define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */
-#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */
-#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */
-#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */
-#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */
-#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */
-#define PVR_460SX_RA 0x13541800 /* 460SX rev A */
-#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */
-#define PVR_460GX_RA 0x13541802 /* 460GX rev A */
-#define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */
-#define PVR_601 0x00010000
-#define PVR_602 0x00050000
-#define PVR_603 0x00030000
-#define PVR_603e 0x00060000
-#define PVR_603ev 0x00070000
-#define PVR_603r 0x00071000
-#define PVR_604 0x00040000
-#define PVR_604e 0x00090000
-#define PVR_604r 0x000A0000
-#define PVR_620 0x00140000
-#define PVR_740 0x00080000
-#define PVR_750 PVR_740
-#define PVR_740P 0x10080000
-#define PVR_750P PVR_740P
-#define PVR_7400 0x000C0000
-#define PVR_7410 0x800C0000
-#define PVR_7450 0x80000000
-
-#define PVR_85xx 0x80200000
-#define PVR_85xx_REV1 (PVR_85xx | 0x0010)
-#define PVR_85xx_REV2 (PVR_85xx | 0x0020)
-
-#define PVR_86xx 0x80040000
-
-#define PVR_VIRTEX5 0x7ff21912
-
-/*
- * For the 8xx processors, all of them report the same PVR family for
- * the PowerPC core. The various versions of these processors must be
- * differentiated by the version number in the Communication Processor
- * Module (CPM).
- */
-#define PVR_821 0x00500000
-#define PVR_823 PVR_821
-#define PVR_850 PVR_821
-#define PVR_860 PVR_821
-#define PVR_7400 0x000C0000
-#define PVR_8240 0x00810100
-
-/*
- * PowerQUICC II family processors report different PVR values depending
- * on silicon process (HiP3, HiP4, HiP7, etc.)
- */
-#define PVR_8260 PVR_8240
-#define PVR_8260_HIP3 0x00810101
-#define PVR_8260_HIP4 0x80811014
-#define PVR_8260_HIP7 0x80822011
-#define PVR_8260_HIP7R1 0x80822013
-#define PVR_8260_HIP7RA 0x80822014
-
-/*
- * MPC 52xx
- */
-#define PVR_5200 0x80822011
-#define PVR_5200B 0x80822014
-
-/*
- * System Version Register
- */
-
-/* System Version Register (SVR) field extraction */
-
-#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
-#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */
-
-#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */
-
-#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */
-#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */
-
-#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/
-#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/
-
-/* Some parts define SVR[0:23] as the SOC version */
-#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */
-
-/* whether MPC8xxxE (i.e. has SEC) */
-#if defined(CONFIG_MPC85xx)
-#define IS_E_PROCESSOR(svr) (svr & 0x80000)
-#else
-#if defined(CONFIG_MPC83xx)
-#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000))
-#endif
-#endif
-
-/*
- * SVR_SOC_VER() Version Values
- */
-
-#define SVR_8533 0x803400
-#define SVR_8533_E 0x803C00
-#define SVR_8535 0x803701
-#define SVR_8535_E 0x803F01
-#define SVR_8536 0x803700
-#define SVR_8536_E 0x803F00
-#define SVR_8540 0x803000
-#define SVR_8541 0x807200
-#define SVR_8541_E 0x807A00
-#define SVR_8543 0x803200
-#define SVR_8543_E 0x803A00
-#define SVR_8544 0x803401
-#define SVR_8544_E 0x803C01
-#define SVR_8545 0x803102
-#define SVR_8545_E 0x803902
-#define SVR_8547_E 0x803901
-#define SVR_8548 0x803100
-#define SVR_8548_E 0x803900
-#define SVR_8555 0x807100
-#define SVR_8555_E 0x807900
-#define SVR_8560 0x807000
-#define SVR_8567 0x807600
-#define SVR_8567_E 0x807E00
-#define SVR_8568 0x807500
-#define SVR_8568_E 0x807D00
-#define SVR_8569 0x808000
-#define SVR_8569_E 0x808800
-#define SVR_8572 0x80E000
-#define SVR_8572_E 0x80E800
-#define SVR_P2020 0x80E200
-#define SVR_P2020_E 0x80EA00
-
-#define SVR_8610 0x80A000
-#define SVR_8641 0x809000
-#define SVR_8641D 0x809001
-
-#define _GLOBAL(n)\
- .globl n;\
-n:
-
-/* Macros for setting and retrieving special purpose registers */
-
-#define stringify(s) tostring(s)
-#define tostring(s) #s
-
-#define mfdcr(rn) ({unsigned int rval; \
- asm volatile("mfdcr %0," stringify(rn) \
- : "=r" (rval)); rval;})
-#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v))
-
-#define mfmsr() ({unsigned int rval; \
- asm volatile("mfmsr %0" : "=r" (rval)); rval;})
-#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
-
-#define mfspr(rn) ({unsigned int rval; \
- asm volatile("mfspr %0," stringify(rn) \
- : "=r" (rval)); rval;})
-#define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v))
-
-#define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v))
-
-/* Segment Registers */
-
-#define SR0 0
-#define SR1 1
-#define SR2 2
-#define SR3 3
-#define SR4 4
-#define SR5 5
-#define SR6 6
-#define SR7 7
-#define SR8 8
-#define SR9 9
-#define SR10 10
-#define SR11 11
-#define SR12 12
-#define SR13 13
-#define SR14 14
-#define SR15 15
-
-#ifndef __ASSEMBLY__
-
-struct cpu_type {
- char name[15];
- u32 soc_ver;
-};
-
-struct cpu_type *identify_cpu(u32 ver);
-
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
-#define CPU_TYPE_ENTRY(n, v) \
- { .name = #n, .soc_ver = SVR_##v, }
-#else
-#if defined(CONFIG_MPC83xx)
-#define CPU_TYPE_ENTRY(x) {#x, SPR_##x}
-#endif
-#endif
-
-
-#ifndef CONFIG_MACH_SPECIFIC
-extern int _machine;
-extern int have_of;
-#endif /* CONFIG_MACH_SPECIFIC */
-
-/* what kind of prep workstation we are */
-extern int _prep_type;
-/*
- * This is used to identify the board type from a given PReP board
- * vendor. Board revision is also made available.
- */
-extern unsigned char ucSystemType;
-extern unsigned char ucBoardRev;
-extern unsigned char ucBoardRevMaj, ucBoardRevMin;
-
-struct task_struct;
-void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
-void release_thread(struct task_struct *);
-
-/*
- * Create a new kernel thread.
- */
-extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
-
-/*
- * Bus types
- */
-#define EISA_bus 0
-#define EISA_bus__is_a_macro /* for versions in ksyms.c */
-#define MCA_bus 0
-#define MCA_bus__is_a_macro /* for versions in ksyms.c */
-
-/* Lazy FPU handling on uni-processor */
-extern struct task_struct *last_task_used_math;
-extern struct task_struct *last_task_used_altivec;
-
-/*
- * this is the minimum allowable io space due to the location
- * of the io areas on prep (first one at 0x80000000) but
- * as soon as I get around to remapping the io areas with the BATs
- * to match the mac we can raise this. -- Cort
- */
-#define TASK_SIZE (0x80000000UL)
-
-/* This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
-
-typedef struct {
- unsigned long seg;
-} mm_segment_t;
-
-struct thread_struct {
- unsigned long ksp; /* Kernel stack pointer */
- unsigned long wchan; /* Event task is sleeping on */
- struct pt_regs *regs; /* Pointer to saved register state */
- mm_segment_t fs; /* for get_fs() validation */
- void *pgdir; /* root of page-table tree */
- signed long last_syscall;
- double fpr[32]; /* Complete floating point set */
- unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */
- unsigned long fpscr; /* Floating point status */
-#ifdef CONFIG_ALTIVEC
- vector128 vr[32]; /* Complete AltiVec set */
- vector128 vscr; /* AltiVec status */
- unsigned long vrsave;
-#endif /* CONFIG_ALTIVEC */
-};
-
-#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
-
-#define INIT_THREAD { \
- INIT_SP, /* ksp */ \
- 0, /* wchan */ \
- (struct pt_regs *)INIT_SP - 1, /* regs */ \
- KERNEL_DS, /*fs*/ \
- swapper_pg_dir, /* pgdir */ \
- 0, /* last_syscall */ \
- {0}, 0, 0 \
-}
-
-/*
- * Note: the vm_start and vm_end fields here should *not*
- * be in kernel space. (Could vm_end == vm_start perhaps?)
- */
-#define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \
- PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
- 1, NULL, NULL }
-
-/*
- * Return saved PC of a blocked thread. For now, this is the "user" PC
- */
-static inline unsigned long thread_saved_pc(struct thread_struct *t)
-{
- return (t->regs) ? t->regs->nip : 0;
-}
-
-#define copy_segments(tsk, mm) do { } while (0)
-#define release_segments(mm) do { } while (0)
-#define forget_segments() do { } while (0)
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define KSTK_EIP(tsk) ((tsk)->thread.regs->nip)
-#define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1])
-
-/*
- * NOTE! The task struct and the stack go together
- */
-#define THREAD_SIZE (2*PAGE_SIZE)
-#define alloc_task_struct() \
- ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
-#define free_task_struct(p) free_pages((unsigned long)(p),1)
-#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count)
-
-/* in process.c - for early bootup debug -- Cort */
-int ll_printk(const char *, ...);
-void ll_puts(const char *);
-
-#define init_task (init_task_union.task)
-#define init_stack (init_task_union.stack)
-
-/* In misc.c */
-void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
-
-#endif /* ndef ASSEMBLY*/
-
-#ifdef CONFIG_MACH_SPECIFIC
-#if defined(CONFIG_8xx)
-#define _machine _MACH_8xx
-#define have_of 0
-#elif defined(CONFIG_OAK)
-#define _machine _MACH_oak
-#define have_of 0
-#elif defined(CONFIG_WALNUT)
-#define _machine _MACH_walnut
-#define have_of 0
-#elif defined(CONFIG_APUS)
-#define _machine _MACH_apus
-#define have_of 0
-#elif defined(CONFIG_GEMINI)
-#define _machine _MACH_gemini
-#define have_of 0
-#elif defined(CONFIG_8260)
-#define _machine _MACH_8260
-#define have_of 0
-#elif defined(CONFIG_SANDPOINT)
-#define _machine _MACH_sandpoint
-#elif defined(CONFIG_HIDDEN_DRAGON)
-#define _machine _MACH_hidden_dragon
-#define have_of 0
-#else
-#error "Machine not defined correctly"
-#endif
-#endif /* CONFIG_MACH_SPECIFIC */
-
-#endif /* __ASM_PPC_PROCESSOR_H */
+#ifndef __ASM_PPC_PROCESSOR_H +#define __ASM_PPC_PROCESSOR_H + +/* + * Default implementation of macro that returns current + * instruction pointer ("program counter"). + */ +#define current_text_addr() ({ __label__ _l; _l: &&_l;}) + +#include <config.h> + +#include <asm/ptrace.h> +#include <asm/types.h> + +/* Machine State Register (MSR) Fields */ + +#ifdef CONFIG_PPC64BRIDGE +#define MSR_SF (1<<63) +#define MSR_ISF (1<<61) +#endif /* CONFIG_PPC64BRIDGE */ +#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ +#define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */ +#define MSR_SPE (1<<25) /* Enable SPE(e500) */ +#define MSR_POW (1<<18) /* Enable Power Management */ +#define MSR_WE (1<<18) /* Wait State Enable */ +#define MSR_TGPR (1<<17) /* TLB Update registers in use */ +#define MSR_CE (1<<17) /* Critical Interrupt Enable */ +#define MSR_ILE (1<<16) /* Interrupt Little Endian */ +#define MSR_EE (1<<15) /* External Interrupt Enable */ +#define MSR_PR (1<<14) /* Problem State / Privilege Level */ +#define MSR_FP (1<<13) /* Floating Point enable */ +#define MSR_ME (1<<12) /* Machine Check Enable */ +#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ +#define MSR_SE (1<<10) /* Single Step */ +#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ +#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ +#define MSR_BE (1<<9) /* Branch Trace */ +#define MSR_DE (1<<9) /* Debug Exception Enable */ +#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ +#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ +#define MSR_IR (1<<5) /* Instruction Relocate */ +#define MSR_IS (1<<5) /* Book E Instruction space */ +#define MSR_DR (1<<4) /* Data Relocate */ +#define MSR_DS (1<<4) /* Book E Data space */ +#define MSR_PE (1<<3) /* Protection Enable */ +#define MSR_PX (1<<2) /* Protection Exclusive Mode */ +#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ +#define MSR_RI (1<<1) /* Recoverable Exception */ +#define MSR_LE (1<<0) /* Little Endian */ + +#ifdef CONFIG_APUS_FAST_EXCEPT +#define MSR_ MSR_ME|MSR_IP|MSR_RI +#else +#define MSR_ MSR_ME|MSR_RI +#endif + +#ifndef CONFIG_E500 +#define MSR_KERNEL MSR_|MSR_IR|MSR_DR +#else +#define MSR_KERNEL MSR_ME +#endif + +/* Floating Point Status and Control Register (FPSCR) Fields */ + +#define FPSCR_FX 0x80000000 /* FPU exception summary */ +#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ +#define FPSCR_VX 0x20000000 /* Invalid operation summary */ +#define FPSCR_OX 0x10000000 /* Overflow exception summary */ +#define FPSCR_UX 0x08000000 /* Underflow exception summary */ +#define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */ +#define FPSCR_XX 0x02000000 /* Inexact exception summary */ +#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ +#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ +#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ +#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ +#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ +#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ +#define FPSCR_FR 0x00040000 /* Fraction rounded */ +#define FPSCR_FI 0x00020000 /* Fraction inexact */ +#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ +#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ +#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ +#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ +#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ +#define FPSCR_VE 0x00000080 /* Invalid op exception enable */ +#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ +#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ +#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ +#define FPSCR_XE 0x00000008 /* FP inexact exception enable */ +#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ +#define FPSCR_RN 0x00000003 /* FPU rounding control */ + +/* Special Purpose Registers (SPRNs)*/ + +/* PPC440 Architecture is BOOK-E */ +#ifdef CONFIG_440 +#define CONFIG_BOOKE +#endif + +#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ +#ifdef CONFIG_BOOKE +#define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */ +#endif +#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ +#define SPRN_CTR 0x009 /* Count Register */ +#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ +#ifndef CONFIG_BOOKE +#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ +#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ +#else +#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */ +#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */ +#endif /* CONFIG_BOOKE */ +#define SPRN_DAR 0x013 /* Data Address Register */ +#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ +#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ +#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ +#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ +#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ +#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ +#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ +#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ +#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ +#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ +#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ +#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ +#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ +#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ +#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ +#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */ +#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ +#define DBCR_EDM 0x80000000 +#define DBCR_IDM 0x40000000 +#define DBCR_RST(x) (((x) & 0x3) << 28) +#define DBCR_RST_NONE 0 +#define DBCR_RST_CORE 1 +#define DBCR_RST_CHIP 2 +#define DBCR_RST_SYSTEM 3 +#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ +#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ +#define DBCR_EDE 0x02000000 /* Exception Debug Event */ +#define DBCR_TDE 0x01000000 /* TRAP Debug Event */ +#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ +#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ +#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ +#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ +#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ +#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ +#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ +#define DAC_BYTE 0 +#define DAC_HALF 1 +#define DAC_WORD 2 +#define DAC_QUAD 3 +#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ +#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ +#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ +#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ +#define DBCR_SED 0x00000020 /* Second Exception Debug Event */ +#define DBCR_STD 0x00000010 /* Second Trap Debug Event */ +#define DBCR_SIA 0x00000008 /* Second IAC Enable */ +#define DBCR_SDA 0x00000004 /* Second DAC Enable */ +#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ +#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ +#ifndef CONFIG_BOOKE +#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ +#else +#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */ +#endif /* CONFIG_BOOKE */ +#ifndef CONFIG_BOOKE +#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ +#define SPRN_DBSR 0x3F0 /* Debug Status Register */ +#else +#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ +#ifdef CONFIG_BOOKE +#define SPRN_DBDR 0x3f3 /* Debug Data Register */ +#endif +#define SPRN_DBSR 0x130 /* Book E Debug Status Register */ +#define DBSR_IC 0x08000000 /* Book E Instruction Completion */ +#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ +#endif /* CONFIG_BOOKE */ +#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ +#define DCCR_NOCACHE 0 /* Noncacheable */ +#define DCCR_CACHE 1 /* Cacheable */ +#ifndef CONFIG_BOOKE +#define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */ +#define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */ +#endif +#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ +#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ +#define DCWR_COPY 0 /* Copy-back */ +#define DCWR_WRITE 1 /* Write-through */ +#ifndef CONFIG_BOOKE +#define SPRN_DEAR 0x3D5 /* Data Error Address Register */ +#else +#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */ +#endif /* CONFIG_BOOKE */ +#define SPRN_DEC 0x016 /* Decrement Register */ +#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ +#ifdef CONFIG_BOOKE +#define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */ +#define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */ +#define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */ +#define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */ +#endif +#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ +#ifdef CONFIG_BOOKE +#define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */ +#define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */ +#define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */ +#define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */ +#define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */ +#endif +#define SPRN_EAR 0x11A /* External Address Register */ +#ifndef CONFIG_BOOKE +#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ +#else +#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */ +#endif /* CONFIG_BOOKE */ +#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ +#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ +#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ +#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ +#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ +#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ +#define ESR_PTR 0x02000000 /* Program Exception - Trap */ +#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ +#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ +#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ +#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ +#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ +#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ + +#define HID0_ICE_SHIFT 15 +#define HID0_DCE_SHIFT 14 +#define HID0_DLOCK_SHIFT 12 + +#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ +#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ +#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ +#define HID0_SBCLK (1<<27) +#define HID0_EICE (1<<26) +#define HID0_ECLK (1<<25) +#define HID0_PAR (1<<24) +#define HID0_DOZE (1<<23) +#define HID0_NAP (1<<22) +#define HID0_SLEEP (1<<21) +#define HID0_DPM (1<<20) +#define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */ +#define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */ +#define HID0_TBEN (1<<14) /* Time Base Enable */ +#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ +#define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */ +#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ +#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */ +#define HID0_DCI HID0_DCFI +#define HID0_SPD (1<<9) /* Speculative disable */ +#define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */ +#define HID0_SGE (1<<7) /* Store Gathering Enable */ +#define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */ +#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ +#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */ +#define HID0_ABE (1<<3) /* Address Broadcast Enable */ +#define HID0_BHTE (1<<2) /* Branch History Table Enable */ +#define HID0_BTCD (1<<1) /* Branch target cache disable */ +#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ +#define HID1_RFXE (1<<17) /* Read Fault Exception Enable */ +#define HID1_ASTME (1<<13) /* Address bus streaming mode */ +#define HID1_ABE (1<<12) /* Address broadcast enable */ +#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ +#ifndef CONFIG_BOOKE +#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ +#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ +#else +#define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */ +#define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */ +#endif /* CONFIG_BOOKE */ +#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ +#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ +#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ +#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ +#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ +#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ +#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ +#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ +#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ +#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ +#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ +#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ +#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ +#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ +#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ +#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ +#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ +#define ICCR_NOCACHE 0 /* Noncacheable */ +#define ICCR_CACHE 1 /* Cacheable */ +#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ +#ifdef CONFIG_BOOKE +#define SPRN_ICDBTRL 0x39e /* instruction cache debug tag register low */ +#define SPRN_ICDBTRH 0x39f /* instruction cache debug tag register high */ +#endif +#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ +#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ +#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ +#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ +#ifdef CONFIG_BOOKE +#define SPRN_INV0 0x370 /* Instruction Cache Normal Victim 0 */ +#define SPRN_INV1 0x371 /* Instruction Cache Normal Victim 1 */ +#define SPRN_INV2 0x372 /* Instruction Cache Normal Victim 2 */ +#define SPRN_INV3 0x373 /* Instruction Cache Normal Victim 3 */ +#define SPRN_ITV0 0x374 /* Instruction Cache Transient Victim 0 */ +#define SPRN_ITV1 0x375 /* Instruction Cache Transient Victim 1 */ +#define SPRN_ITV2 0x376 /* Instruction Cache Transient Victim 2 */ +#define SPRN_ITV3 0x377 /* Instruction Cache Transient Victim 3 */ +#define SPRN_IVLIM 0x399 /* Instruction Cache Victim Limit */ +#endif +#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ +#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ +#define SPRN_LR 0x008 /* Link Register */ +#define SPRN_MBAR 0x137 /* System memory base address */ +#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */ +#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */ +#ifdef CONFIG_BOOKE +#define SPRN_MMUCR 0x3b2 /* MMU Control Register */ +#endif +#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ +#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ +#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ +#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ +#ifndef CONFIG_BOOKE +#define SPRN_PID 0x3B1 /* Process ID */ +#define SPRN_PIR 0x3FF /* Processor Identification Register */ +#else +#define SPRN_PID 0x030 /* Book E Process ID */ +#define SPRN_PIR 0x11E /* Book E Processor Identification Register */ +#endif /* CONFIG_BOOKE */ +#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ +#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */ +#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */ +#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */ +#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */ +#define SPRN_PVR 0x11F /* Processor Version Register */ +#define SPRN_RPA 0x3D6 /* Required Physical Address Register */ +#ifdef CONFIG_BOOKE +#define SPRN_RSTCFG 0x39b /* Reset Configuration */ +#endif +#define SPRN_SDA 0x3BF /* Sampled Data Address Register */ +#define SPRN_SDR1 0x019 /* MMU Hash Base Register */ +#define SPRN_SGR 0x3B9 /* Storage Guarded Register */ +#define SGR_NORMAL 0 +#define SGR_GUARDED 1 +#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ +#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ +#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ +#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ +#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ +#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ +#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ +#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ +#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ +#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ +#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ +#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ +#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ + +#ifdef CONFIG_BOOKE +#define SPRN_SVR 0x3FF /* System Version Register */ +#else +#define SPRN_SVR 0x11E /* System Version Register */ +#endif +#define SPRN_TBHI 0x3DC /* Time Base High */ +#define SPRN_TBHU 0x3CC /* Time Base High User-mode */ +#define SPRN_TBLO 0x3DD /* Time Base Low */ +#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ +#define SPRN_TBRL 0x10C /* Time Base Read Lower Register */ +#define SPRN_TBRU 0x10D /* Time Base Read Upper Register */ +#define SPRN_TBWL 0x11C /* Time Base Write Lower Register */ +#define SPRN_TBWU 0x11D /* Time Base Write Upper Register */ +#ifndef CONFIG_BOOKE +#define SPRN_TCR 0x3DA /* Timer Control Register */ +#else +#define SPRN_TCR 0x154 /* Book E Timer Control Register */ +#endif /* CONFIG_BOOKE */ +#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ +#define WP_2_17 0 /* 2^17 clocks */ +#define WP_2_21 1 /* 2^21 clocks */ +#define WP_2_25 2 /* 2^25 clocks */ +#define WP_2_29 3 /* 2^29 clocks */ +#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ +#define WRC_NONE 0 /* No reset will occur */ +#define WRC_CORE 1 /* Core reset will occur */ +#define WRC_CHIP 2 /* Chip reset will occur */ +#define WRC_SYSTEM 3 /* System reset will occur */ +#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ +#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ +#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ +#define FP_2_9 0 /* 2^9 clocks */ +#define FP_2_13 1 /* 2^13 clocks */ +#define FP_2_17 2 /* 2^17 clocks */ +#define FP_2_21 3 /* 2^21 clocks */ +#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ +#define TCR_ARE 0x00400000 /* Auto Reload Enable */ +#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ +#define THRM1_TIN (1<<0) +#define THRM1_TIV (1<<1) +#define THRM1_THRES (0x7f<<2) +#define THRM1_TID (1<<29) +#define THRM1_TIE (1<<30) +#define THRM1_V (1<<31) +#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ +#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ +#define THRM3_E (1<<31) +#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ +#ifndef CONFIG_BOOKE +#define SPRN_TSR 0x3D8 /* Timer Status Register */ +#else +#define SPRN_TSR 0x150 /* Book E Timer Status Register */ +#endif /* CONFIG_BOOKE */ +#define TSR_ENW 0x80000000 /* Enable Next Watchdog */ +#define TSR_WIS 0x40000000 /* WDT Interrupt Status */ +#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ +#define WRS_NONE 0 /* No WDT reset occurred */ +#define WRS_CORE 1 /* WDT forced core reset */ +#define WRS_CHIP 2 /* WDT forced chip reset */ +#define WRS_SYSTEM 3 /* WDT forced system reset */ +#define TSR_PIS 0x08000000 /* PIT Interrupt Status */ +#define TSR_FIS 0x04000000 /* FIT Interrupt Status */ +#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ +#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ +#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ +#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ +#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ +#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ +#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ +#define SPRN_XER 0x001 /* Fixed Point Exception Register */ +#define SPRN_ZPR 0x3B0 /* Zone Protection Register */ + +/* Book E definitions */ +#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ +#define SPRN_CSRR0 0x03A /* Critical SRR0 */ +#define SPRN_CSRR1 0x03B /* Critical SRR0 */ +#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ +#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */ +#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ +#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ +#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ +#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ +#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ +#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ +#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ +#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ +#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ +#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ +#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ +#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */ +#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ +#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */ +#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */ +#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */ +#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */ +#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */ +#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */ +#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */ +#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */ +#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */ +#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */ +#define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */ +#define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */ +#define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */ +#define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */ +#define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */ +#define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */ + +/* e500 definitions */ +#define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */ +#define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */ +#define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */ +#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */ +#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ +#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ +#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ +#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */ +#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ +#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ +#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ +#define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */ +#define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */ +#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ +#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ +#define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */ +#define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */ +#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */ +#define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */ +#define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */ +#define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */ +#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */ +#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */ +#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */ +#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */ +#define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */ + +#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ +#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ +#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */ +#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ +#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ +#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ +#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ +#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ +#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ +#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ +#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */ + +#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ +#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ +#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ +#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ +#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ + +#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */ +#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */ +#define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */ +#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ +#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ +#define SPRN_PID1 0x279 /* Process ID Register 1 */ +#define SPRN_PID2 0x27a /* Process ID Register 2 */ +#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */ +#define SPRN_MCAR 0x23d /* Machine Check Address register */ +#define MCSR_MCS 0x80000000 /* Machine Check Summary */ +#define MCSR_IB 0x40000000 /* Instruction PLB Error */ +#if defined(CONFIG_440) +#define MCSR_DRB 0x20000000 /* Data Read PLB Error */ +#define MCSR_DWB 0x10000000 /* Data Write PLB Error */ +#else +#define MCSR_DB 0x20000000 /* Data PLB Error */ +#endif /* defined(CONFIG_440) */ +#define MCSR_TLBP 0x08000000 /* TLB Parity Error */ +#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ +#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ +#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ +#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ +#define ESR_ST 0x00800000 /* Store Operation */ + +#if defined(CONFIG_MPC86xx) +#define SPRN_MSSCR0 0x3f6 +#define SPRN_MSSSR0 0x3f7 +#endif + +/* Short-hand versions for a number of the above SPRNs */ + +#define CTR SPRN_CTR /* Counter Register */ +#define DAR SPRN_DAR /* Data Address Register */ +#define DABR SPRN_DABR /* Data Address Breakpoint Register */ +#define DAC1 SPRN_DAC1 /* Data Address Register 1 */ +#define DAC2 SPRN_DAC2 /* Data Address Register 2 */ +#define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */ +#define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */ +#define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */ +#define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */ +#define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */ +#define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */ +#define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */ +#define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */ +#define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */ +#define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */ +#define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */ +#define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */ +#define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */ +#define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */ +#define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */ +#define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */ +#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */ +#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */ +#define DBSR SPRN_DBSR /* Debug Status Register */ +#define DCMP SPRN_DCMP /* Data TLB Compare Register */ +#define DEC SPRN_DEC /* Decrement Register */ +#define DMISS SPRN_DMISS /* Data TLB Miss Register */ +#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */ +#define EAR SPRN_EAR /* External Address Register */ +#define ESR SPRN_ESR /* Exception Syndrome Register */ +#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */ +#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */ +#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */ +#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */ +#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ +#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */ +#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */ +#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */ +#define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */ +#define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */ +#define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */ +#define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */ +#define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */ +#define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */ +#define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */ +#define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */ +#define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */ +#define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */ +#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */ +#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */ +#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */ +#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */ +#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */ +#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ +#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ +#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ +#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ +#define L2CR SPRN_L2CR /* PPC 750 L2 control register */ +#define LR SPRN_LR +#define MBAR SPRN_MBAR /* System memory base address */ +#if defined(CONFIG_MPC86xx) +#define MSSCR0 SPRN_MSSCR0 +#endif +#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) +#define PIR SPRN_PIR +#endif +#define SVR SPRN_SVR /* System-On-Chip Version Register */ +#define PVR SPRN_PVR /* Processor Version */ +#define RPA SPRN_RPA /* Required Physical Address Register */ +#define SDR1 SPRN_SDR1 /* MMU hash base register */ +#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */ +#define SPR1 SPRN_SPRG1 +#define SPR2 SPRN_SPRG2 +#define SPR3 SPRN_SPRG3 +#define SPRG0 SPRN_SPRG0 +#define SPRG1 SPRN_SPRG1 +#define SPRG2 SPRN_SPRG2 +#define SPRG3 SPRN_SPRG3 +#define SPRG4 SPRN_SPRG4 +#define SPRG5 SPRN_SPRG5 +#define SPRG6 SPRN_SPRG6 +#define SPRG7 SPRN_SPRG7 +#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */ +#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */ +#define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */ +#define SRR3 SPRN_SRR3 /* Save and Restore Register 3 */ +#define SVR SPRN_SVR /* System Version Register */ +#define TBRL SPRN_TBRL /* Time Base Read Lower Register */ +#define TBRU SPRN_TBRU /* Time Base Read Upper Register */ +#define TBWL SPRN_TBWL /* Time Base Write Lower Register */ +#define TBWU SPRN_TBWU /* Time Base Write Upper Register */ +#define TCR SPRN_TCR /* Timer Control Register */ +#define TSR SPRN_TSR /* Timer Status Register */ +#define ICTC 1019 +#define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */ +#define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */ +#define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */ +#define XER SPRN_XER + +#define DECAR SPRN_DECAR +#define CSRR0 SPRN_CSRR0 +#define CSRR1 SPRN_CSRR1 +#define IVPR SPRN_IVPR +#define USPRG0 SPRN_USPRG +#define SPRG4R SPRN_SPRG4R +#define SPRG5R SPRN_SPRG5R +#define SPRG6R SPRN_SPRG6R +#define SPRG7R SPRN_SPRG7R +#define SPRG4W SPRN_SPRG4W +#define SPRG5W SPRN_SPRG5W +#define SPRG6W SPRN_SPRG6W +#define SPRG7W SPRN_SPRG7W +#define DEAR SPRN_DEAR +#define DBCR2 SPRN_DBCR2 +#define IAC3 SPRN_IAC3 +#define IAC4 SPRN_IAC4 +#define DVC1 SPRN_DVC1 +#define DVC2 SPRN_DVC2 +#define IVOR0 SPRN_IVOR0 +#define IVOR1 SPRN_IVOR1 +#define IVOR2 SPRN_IVOR2 +#define IVOR3 SPRN_IVOR3 +#define IVOR4 SPRN_IVOR4 +#define IVOR5 SPRN_IVOR5 +#define IVOR6 SPRN_IVOR6 +#define IVOR7 SPRN_IVOR7 +#define IVOR8 SPRN_IVOR8 +#define IVOR9 SPRN_IVOR9 +#define IVOR10 SPRN_IVOR10 +#define IVOR11 SPRN_IVOR11 +#define IVOR12 SPRN_IVOR12 +#define IVOR13 SPRN_IVOR13 +#define IVOR14 SPRN_IVOR14 +#define IVOR15 SPRN_IVOR15 +#define IVOR32 SPRN_IVOR32 +#define IVOR33 SPRN_IVOR33 +#define IVOR34 SPRN_IVOR34 +#define IVOR35 SPRN_IVOR35 +#define MCSRR0 SPRN_MCSRR0 +#define MCSRR1 SPRN_MCSRR1 +#define L1CSR0 SPRN_L1CSR0 +#define L1CSR1 SPRN_L1CSR1 +#define L1CSR2 SPRN_L1CSR2 +#define L1CFG0 SPRN_L1CFG0 +#define L1CFG1 SPRN_L1CFG1 +#define L2CFG0 SPRN_L2CFG0 +#define L2CSR0 SPRN_L2CSR0 +#define L2CSR1 SPRN_L2CSR1 +#define MCSR SPRN_MCSR +#define MMUCSR0 SPRN_MMUCSR0 +#define BUCSR SPRN_BUCSR +#define PID0 SPRN_PID +#define PID1 SPRN_PID1 +#define PID2 SPRN_PID2 +#define MAS0 SPRN_MAS0 +#define MAS1 SPRN_MAS1 +#define MAS2 SPRN_MAS2 +#define MAS3 SPRN_MAS3 +#define MAS4 SPRN_MAS4 +#define MAS5 SPRN_MAS5 +#define MAS6 SPRN_MAS6 +#define MAS7 SPRN_MAS7 + +#if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx) +#define DAR_DEAR DEAR +#else +#define DAR_DEAR DAR +#endif + +/* Device Control Registers */ + +#define DCRN_BEAR 0x090 /* Bus Error Address Register */ +#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */ +#define BESR_DSES 0x80000000 /* Data-Side Error Status */ +#define BESR_DMES 0x40000000 /* DMA Error Status */ +#define BESR_RWS 0x20000000 /* Read/Write Status */ +#define BESR_ETMASK 0x1C000000 /* Error Type */ +#define ET_PROT 0 +#define ET_PARITY 1 +#define ET_NCFG 2 +#define ET_BUSERR 4 +#define ET_BUSTO 6 +#define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */ +#define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */ +#define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */ +#define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */ +#define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */ +#define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */ +#define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */ +#define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */ +#define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */ +#define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */ +#define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */ +#define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */ +#define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */ +#define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */ +#define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */ +#define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */ +#define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */ +#define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */ +#define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */ +#define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */ +#define DCRN_DMASR 0x0E0 /* DMA Status Register */ +#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */ +#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ +#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ +#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ +#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ +#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ +#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ +#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ +#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ +#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ +#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ +#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ +#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ +#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ +#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ +#define DCRN_EXISR 0x040 /* External Interrupt Status Register */ +#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */ +#define IOCR_E0TE 0x80000000 +#define IOCR_E0LP 0x40000000 +#define IOCR_E1TE 0x20000000 +#define IOCR_E1LP 0x10000000 +#define IOCR_E2TE 0x08000000 +#define IOCR_E2LP 0x04000000 +#define IOCR_E3TE 0x02000000 +#define IOCR_E3LP 0x01000000 +#define IOCR_E4TE 0x00800000 +#define IOCR_E4LP 0x00400000 +#define IOCR_EDT 0x00080000 +#define IOCR_SOR 0x00040000 +#define IOCR_EDO 0x00008000 +#define IOCR_2XC 0x00004000 +#define IOCR_ATC 0x00002000 +#define IOCR_SPD 0x00001000 +#define IOCR_BEM 0x00000800 +#define IOCR_PTD 0x00000400 +#define IOCR_ARE 0x00000080 +#define IOCR_DRC 0x00000020 +#define IOCR_RDM(x) (((x) & 0x3) << 3) +#define IOCR_TCS 0x00000004 +#define IOCR_SCS 0x00000002 +#define IOCR_SPC 0x00000001 + +/* System-On-Chip Version Register */ + +/* System-On-Chip Version Register (SVR) field extraction */ + +#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ +#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ + +#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */ +#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */ +#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */ +#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */ +#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */ +#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ +#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ + +/* Processor Version Register */ + +/* Processor Version Register (PVR) field extraction */ + +#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ +#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ + +/* + * AMCC has further subdivided the standard PowerPC 16-bit version and + * revision subfields of the PVR for the PowerPC 403s into the following: + */ + +#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ +#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ +#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ +#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ +#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ +#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ + +/* e600 core PVR fields */ + +#define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */ +#define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */ +#define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */ +#define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */ + +/* Processor Version Numbers */ + +#define PVR_403GA 0x00200000 +#define PVR_403GB 0x00200100 +#define PVR_403GC 0x00200200 +#define PVR_403GCX 0x00201400 +#define PVR_405GP 0x40110000 +#define PVR_405GP_RB 0x40110040 +#define PVR_405GP_RC 0x40110082 +#define PVR_405GP_RD 0x401100C4 +#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */ +#define PVR_405CR_RA 0x40110041 +#define PVR_405CR_RB 0x401100C5 +#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ +#define PVR_405EP_RA 0x51210950 +#define PVR_405GPR_RB 0x50910951 +#define PVR_405EZ_RA 0x41511460 +#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A/B with Security */ +#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */ +#define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */ +#define PVR_405EX2_RA 0x12911475 /* 405EX rev A/B without Security */ +#define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */ +#define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */ +#define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */ +#define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */ +#define PVR_440GP_RB 0x40120440 +#define PVR_440GP_RC 0x40120481 +#define PVR_440EP_RA 0x42221850 +#define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ +#define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ +#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ +#define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ +#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */ +#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */ +#define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */ +#define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */ +#define PVR_440GX_RA 0x51B21850 +#define PVR_440GX_RB 0x51B21851 +#define PVR_440GX_RC 0x51B21892 +#define PVR_440GX_RF 0x51B21894 +#define PVR_405EP_RB 0x51210950 +#define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */ +#define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */ +#define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */ +#define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */ +#define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */ +#define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */ +#define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */ +#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */ +#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */ +#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */ +#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ +#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */ +#define PVR_460SX_RA 0x13541800 /* 460SX rev A */ +#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ +#define PVR_460GX_RA 0x13541802 /* 460GX rev A */ +#define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */ +#define PVR_601 0x00010000 +#define PVR_602 0x00050000 +#define PVR_603 0x00030000 +#define PVR_603e 0x00060000 +#define PVR_603ev 0x00070000 +#define PVR_603r 0x00071000 +#define PVR_604 0x00040000 +#define PVR_604e 0x00090000 +#define PVR_604r 0x000A0000 +#define PVR_620 0x00140000 +#define PVR_740 0x00080000 +#define PVR_750 PVR_740 +#define PVR_740P 0x10080000 +#define PVR_750P PVR_740P +#define PVR_7400 0x000C0000 +#define PVR_7410 0x800C0000 +#define PVR_7450 0x80000000 + +#define PVR_85xx 0x80200000 +#define PVR_85xx_REV1 (PVR_85xx | 0x0010) +#define PVR_85xx_REV2 (PVR_85xx | 0x0020) + +#define PVR_86xx 0x80040000 + +#define PVR_VIRTEX5 0x7ff21912 + +/* + * For the 8xx processors, all of them report the same PVR family for + * the PowerPC core. The various versions of these processors must be + * differentiated by the version number in the Communication Processor + * Module (CPM). + */ +#define PVR_821 0x00500000 +#define PVR_823 PVR_821 +#define PVR_850 PVR_821 +#define PVR_860 PVR_821 +#define PVR_7400 0x000C0000 +#define PVR_8240 0x00810100 + +/* + * PowerQUICC II family processors report different PVR values depending + * on silicon process (HiP3, HiP4, HiP7, etc.) + */ +#define PVR_8260 PVR_8240 +#define PVR_8260_HIP3 0x00810101 +#define PVR_8260_HIP4 0x80811014 +#define PVR_8260_HIP7 0x80822011 +#define PVR_8260_HIP7R1 0x80822013 +#define PVR_8260_HIP7RA 0x80822014 + +/* + * MPC 52xx + */ +#define PVR_5200 0x80822011 +#define PVR_5200B 0x80822014 + +/* + * System Version Register + */ + +/* System Version Register (SVR) field extraction */ + +#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ +#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */ + +#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */ + +#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ +#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ + +#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ +#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ + +/* Some parts define SVR[0:23] as the SOC version */ +#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */ + +/* whether MPC8xxxE (i.e. has SEC) */ +#if defined(CONFIG_MPC85xx) +#define IS_E_PROCESSOR(svr) (svr & 0x80000) +#else +#if defined(CONFIG_MPC83xx) +#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) +#endif +#endif + +/* + * SVR_SOC_VER() Version Values + */ + +#define SVR_8533 0x803400 +#define SVR_8533_E 0x803C00 +#define SVR_8535 0x803701 +#define SVR_8535_E 0x803F01 +#define SVR_8536 0x803700 +#define SVR_8536_E 0x803F00 +#define SVR_8540 0x803000 +#define SVR_8541 0x807200 +#define SVR_8541_E 0x807A00 +#define SVR_8543 0x803200 +#define SVR_8543_E 0x803A00 +#define SVR_8544 0x803401 +#define SVR_8544_E 0x803C01 +#define SVR_8545 0x803102 +#define SVR_8545_E 0x803902 +#define SVR_8547_E 0x803901 +#define SVR_8548 0x803100 +#define SVR_8548_E 0x803900 +#define SVR_8555 0x807100 +#define SVR_8555_E 0x807900 +#define SVR_8560 0x807000 +#define SVR_8567 0x807600 +#define SVR_8567_E 0x807E00 +#define SVR_8568 0x807500 +#define SVR_8568_E 0x807D00 +#define SVR_8569 0x808000 +#define SVR_8569_E 0x808800 +#define SVR_8572 0x80E000 +#define SVR_8572_E 0x80E800 +#define SVR_P2020 0x80E200 +#define SVR_P2020_E 0x80EA00 + +#define SVR_8610 0x80A000 +#define SVR_8641 0x809000 +#define SVR_8641D 0x809001 + +#define _GLOBAL(n)\ + .globl n;\ +n: + +/* Macros for setting and retrieving special purpose registers */ + +#define stringify(s) tostring(s) +#define tostring(s) #s + +#define mfdcr(rn) ({unsigned int rval; \ + asm volatile("mfdcr %0," stringify(rn) \ + : "=r" (rval)); rval;}) +#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v)) + +#define mfmsr() ({unsigned int rval; \ + asm volatile("mfmsr %0" : "=r" (rval)); rval;}) +#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) + +#define mfspr(rn) ({unsigned int rval; \ + asm volatile("mfspr %0," stringify(rn) \ + : "=r" (rval)); rval;}) +#define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v)) + +#define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v)) + +/* Segment Registers */ + +#define SR0 0 +#define SR1 1 +#define SR2 2 +#define SR3 3 +#define SR4 4 +#define SR5 5 +#define SR6 6 +#define SR7 7 +#define SR8 8 +#define SR9 9 +#define SR10 10 +#define SR11 11 +#define SR12 12 +#define SR13 13 +#define SR14 14 +#define SR15 15 + +#ifndef __ASSEMBLY__ + +struct cpu_type { + char name[15]; + u32 soc_ver; +}; + +struct cpu_type *identify_cpu(u32 ver); + +#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) +#define CPU_TYPE_ENTRY(n, v) \ + { .name = #n, .soc_ver = SVR_##v, } +#else +#if defined(CONFIG_MPC83xx) +#define CPU_TYPE_ENTRY(x) {#x, SPR_##x} +#endif +#endif + + +#ifndef CONFIG_MACH_SPECIFIC +extern int _machine; +extern int have_of; +#endif /* CONFIG_MACH_SPECIFIC */ + +/* what kind of prep workstation we are */ +extern int _prep_type; +/* + * This is used to identify the board type from a given PReP board + * vendor. Board revision is also made available. + */ +extern unsigned char ucSystemType; +extern unsigned char ucBoardRev; +extern unsigned char ucBoardRevMaj, ucBoardRevMin; + +struct task_struct; +void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp); +void release_thread(struct task_struct *); + +/* + * Create a new kernel thread. + */ +extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); + +/* + * Bus types + */ +#define EISA_bus 0 +#define EISA_bus__is_a_macro /* for versions in ksyms.c */ +#define MCA_bus 0 +#define MCA_bus__is_a_macro /* for versions in ksyms.c */ + +/* Lazy FPU handling on uni-processor */ +extern struct task_struct *last_task_used_math; +extern struct task_struct *last_task_used_altivec; + +/* + * this is the minimum allowable io space due to the location + * of the io areas on prep (first one at 0x80000000) but + * as soon as I get around to remapping the io areas with the BATs + * to match the mac we can raise this. -- Cort + */ +#define TASK_SIZE (0x80000000UL) + +/* This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) + +typedef struct { + unsigned long seg; +} mm_segment_t; + +struct thread_struct { + unsigned long ksp; /* Kernel stack pointer */ + unsigned long wchan; /* Event task is sleeping on */ + struct pt_regs *regs; /* Pointer to saved register state */ + mm_segment_t fs; /* for get_fs() validation */ + void *pgdir; /* root of page-table tree */ + signed long last_syscall; + double fpr[32]; /* Complete floating point set */ + unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */ + unsigned long fpscr; /* Floating point status */ +#ifdef CONFIG_ALTIVEC + vector128 vr[32]; /* Complete AltiVec set */ + vector128 vscr; /* AltiVec status */ + unsigned long vrsave; +#endif /* CONFIG_ALTIVEC */ +}; + +#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) + +#define INIT_THREAD { \ + INIT_SP, /* ksp */ \ + 0, /* wchan */ \ + (struct pt_regs *)INIT_SP - 1, /* regs */ \ + KERNEL_DS, /*fs*/ \ + swapper_pg_dir, /* pgdir */ \ + 0, /* last_syscall */ \ + {0}, 0, 0 \ +} + +/* + * Note: the vm_start and vm_end fields here should *not* + * be in kernel space. (Could vm_end == vm_start perhaps?) + */ +#define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \ + PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \ + 1, NULL, NULL } + +/* + * Return saved PC of a blocked thread. For now, this is the "user" PC + */ +static inline unsigned long thread_saved_pc(struct thread_struct *t) +{ + return (t->regs) ? t->regs->nip : 0; +} + +#define copy_segments(tsk, mm) do { } while (0) +#define release_segments(mm) do { } while (0) +#define forget_segments() do { } while (0) + +unsigned long get_wchan(struct task_struct *p); + +#define KSTK_EIP(tsk) ((tsk)->thread.regs->nip) +#define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1]) + +/* + * NOTE! The task struct and the stack go together + */ +#define THREAD_SIZE (2*PAGE_SIZE) +#define alloc_task_struct() \ + ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) +#define free_task_struct(p) free_pages((unsigned long)(p),1) +#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) + +/* in process.c - for early bootup debug -- Cort */ +int ll_printk(const char *, ...); +void ll_puts(const char *); + +#define init_task (init_task_union.task) +#define init_stack (init_task_union.stack) + +/* In misc.c */ +void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); + +#endif /* ndef ASSEMBLY*/ + +#ifdef CONFIG_MACH_SPECIFIC +#if defined(CONFIG_8xx) +#define _machine _MACH_8xx +#define have_of 0 +#elif defined(CONFIG_OAK) +#define _machine _MACH_oak +#define have_of 0 +#elif defined(CONFIG_WALNUT) +#define _machine _MACH_walnut +#define have_of 0 +#elif defined(CONFIG_APUS) +#define _machine _MACH_apus +#define have_of 0 +#elif defined(CONFIG_GEMINI) +#define _machine _MACH_gemini +#define have_of 0 +#elif defined(CONFIG_8260) +#define _machine _MACH_8260 +#define have_of 0 +#elif defined(CONFIG_SANDPOINT) +#define _machine _MACH_sandpoint +#elif defined(CONFIG_HIDDEN_DRAGON) +#define _machine _MACH_hidden_dragon +#define have_of 0 +#else +#error "Machine not defined correctly" +#endif +#endif /* CONFIG_MACH_SPECIFIC */ + +#endif /* __ASM_PPC_PROCESSOR_H */ diff --git a/libcpu/ppc/ppc405/include/asm/ptrace.h b/libcpu/ppc/ppc405/include/asm/ptrace.h index 8019543ab1..d531de889b 100644 --- a/libcpu/ppc/ppc405/include/asm/ptrace.h +++ b/libcpu/ppc/ppc405/include/asm/ptrace.h @@ -1,107 +1,107 @@ -#ifndef _PPC_PTRACE_H
-#define _PPC_PTRACE_H
-
-/*
- * This struct defines the way the registers are stored on the
- * kernel stack during a system call or other kernel entry.
- *
- * this should only contain volatile regs
- * since we can keep non-volatile in the thread_struct
- * should set this up when only volatiles are saved
- * by intr code.
- *
- * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
- * that the overall structure is a multiple of 16 bytes in length.
- *
- * Note that the offsets of the fields in this struct correspond with
- * the PT_* values below. This simplifies arch/ppc/kernel/ptrace.c.
- */
-
-#include <config.h>
-
-#ifndef __ASSEMBLY__
-#ifdef CONFIG_PPC64BRIDGE
-#define PPC_REG unsigned long /*long*/
-#else
-#define PPC_REG unsigned long
-#endif
-struct pt_regs {
- PPC_REG gpr[32];
- PPC_REG nip;
- PPC_REG msr;
- PPC_REG orig_gpr3; /* Used for restarting system calls */
- PPC_REG ctr;
- PPC_REG link;
- PPC_REG xer;
- PPC_REG ccr;
- PPC_REG mq; /* 601 only (not used at present) */
- /* Used on APUS to hold IPL value. */
- PPC_REG trap; /* Reason for being here */
- PPC_REG dar; /* Fault registers */
- PPC_REG dsisr;
- PPC_REG result; /* Result of a system call */
-}__attribute__((packed)) CELL_STACK_FRAME_t;
-#endif
-
-#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */
-
-/* Size of stack frame allocated when calling signal handler. */
-#define __SIGNAL_FRAMESIZE 64
-
-#define instruction_pointer(regs) ((regs)->nip)
-#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
-
-/*
- * Offsets used by 'ptrace' system call interface.
- * These can't be changed without breaking binary compatibility
- * with MkLinux, etc.
- */
-#define PT_R0 0
-#define PT_R1 1
-#define PT_R2 2
-#define PT_R3 3
-#define PT_R4 4
-#define PT_R5 5
-#define PT_R6 6
-#define PT_R7 7
-#define PT_R8 8
-#define PT_R9 9
-#define PT_R10 10
-#define PT_R11 11
-#define PT_R12 12
-#define PT_R13 13
-#define PT_R14 14
-#define PT_R15 15
-#define PT_R16 16
-#define PT_R17 17
-#define PT_R18 18
-#define PT_R19 19
-#define PT_R20 20
-#define PT_R21 21
-#define PT_R22 22
-#define PT_R23 23
-#define PT_R24 24
-#define PT_R25 25
-#define PT_R26 26
-#define PT_R27 27
-#define PT_R28 28
-#define PT_R29 29
-#define PT_R30 30
-#define PT_R31 31
-
-#define PT_NIP 32
-#define PT_MSR 33
-#ifdef __KERNEL__
-#define PT_ORIG_R3 34
-#endif
-#define PT_CTR 35
-#define PT_LNK 36
-#define PT_XER 37
-#define PT_CCR 38
-#define PT_MQ 39
-
-#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */
-#define PT_FPR31 (PT_FPR0 + 2*31)
-#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
-
-#endif
+#ifndef _PPC_PTRACE_H +#define _PPC_PTRACE_H + +/* + * This struct defines the way the registers are stored on the + * kernel stack during a system call or other kernel entry. + * + * this should only contain volatile regs + * since we can keep non-volatile in the thread_struct + * should set this up when only volatiles are saved + * by intr code. + * + * Since this is going on the stack, *CARE MUST BE TAKEN* to insure + * that the overall structure is a multiple of 16 bytes in length. + * + * Note that the offsets of the fields in this struct correspond with + * the PT_* values below. This simplifies arch/ppc/kernel/ptrace.c. + */ + +#include <config.h> + +#ifndef __ASSEMBLY__ +#ifdef CONFIG_PPC64BRIDGE +#define PPC_REG unsigned long /*long*/ +#else +#define PPC_REG unsigned long +#endif +struct pt_regs { + PPC_REG gpr[32]; + PPC_REG nip; + PPC_REG msr; + PPC_REG orig_gpr3; /* Used for restarting system calls */ + PPC_REG ctr; + PPC_REG link; + PPC_REG xer; + PPC_REG ccr; + PPC_REG mq; /* 601 only (not used at present) */ + /* Used on APUS to hold IPL value. */ + PPC_REG trap; /* Reason for being here */ + PPC_REG dar; /* Fault registers */ + PPC_REG dsisr; + PPC_REG result; /* Result of a system call */ +}__attribute__((packed)) CELL_STACK_FRAME_t; +#endif + +#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ + +/* Size of stack frame allocated when calling signal handler. */ +#define __SIGNAL_FRAMESIZE 64 + +#define instruction_pointer(regs) ((regs)->nip) +#define user_mode(regs) (((regs)->msr & MSR_PR) != 0) + +/* + * Offsets used by 'ptrace' system call interface. + * These can't be changed without breaking binary compatibility + * with MkLinux, etc. + */ +#define PT_R0 0 +#define PT_R1 1 +#define PT_R2 2 +#define PT_R3 3 +#define PT_R4 4 +#define PT_R5 5 +#define PT_R6 6 +#define PT_R7 7 +#define PT_R8 8 +#define PT_R9 9 +#define PT_R10 10 +#define PT_R11 11 +#define PT_R12 12 +#define PT_R13 13 +#define PT_R14 14 +#define PT_R15 15 +#define PT_R16 16 +#define PT_R17 17 +#define PT_R18 18 +#define PT_R19 19 +#define PT_R20 20 +#define PT_R21 21 +#define PT_R22 22 +#define PT_R23 23 +#define PT_R24 24 +#define PT_R25 25 +#define PT_R26 26 +#define PT_R27 27 +#define PT_R28 28 +#define PT_R29 29 +#define PT_R30 30 +#define PT_R31 31 + +#define PT_NIP 32 +#define PT_MSR 33 +#ifdef __KERNEL__ +#define PT_ORIG_R3 34 +#endif +#define PT_CTR 35 +#define PT_LNK 36 +#define PT_XER 37 +#define PT_CCR 38 +#define PT_MQ 39 + +#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ +#define PT_FPR31 (PT_FPR0 + 2*31) +#define PT_FPSCR (PT_FPR0 + 2*32 + 1) + +#endif diff --git a/libcpu/ppc/ppc405/include/asm/types.h b/libcpu/ppc/ppc405/include/asm/types.h index ac4133ffd4..6413895325 100644 --- a/libcpu/ppc/ppc405/include/asm/types.h +++ b/libcpu/ppc/ppc405/include/asm/types.h @@ -1,74 +1,74 @@ -#ifndef _PPC_TYPES_H
-#define _PPC_TYPES_H
-
-
-#ifndef __ASSEMBLY__
-
-typedef enum bool
- {
- FALSE = 0,
- TRUE = 1
- }BOOL;
-
-typedef unsigned short umode_t;
-
-typedef __signed__ char __s8;
-typedef unsigned char __u8;
-
-typedef __signed__ short __s16;
-typedef unsigned short __u16;
-
-typedef __signed__ int __s32;
-typedef unsigned int __u32;
-
-#if defined(__GNUC__)
-__extension__ typedef __signed__ long long __s64;
-__extension__ typedef unsigned long long __u64;
-#endif
-
-typedef struct {
- __u32 u[4];
-} __attribute__((aligned(16))) vector128;
-
-#ifdef __KERNEL__
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-typedef signed char s8;
-typedef unsigned char u8;
-
-typedef signed short s16;
-typedef unsigned short u16;
-
-typedef signed int s32;
-typedef unsigned int u32;
-
-typedef signed long long s64;
-typedef unsigned long long u64;
-
-typedef char INT8;
-typedef short INT16;
-typedef int INT32;
-typedef long long INT64;
-typedef unsigned char UINT8;
-typedef unsigned short UINT16;
-typedef unsigned int UINT32;
-typedef unsigned long long UINT64;
-
-#define BITS_PER_LONG 32
-
-/* DMA addresses are 32-bits wide */
-typedef u32 dma_addr_t;
-
-#ifdef CONFIG_PHYS_64BIT
-typedef unsigned long long phys_addr_t;
-typedef unsigned long long phys_size_t;
-#else
-typedef unsigned long phys_addr_t;
-typedef unsigned long phys_size_t;
-#endif
-
-#endif /* __KERNEL__ */
-#endif /* __ASSEMBLY__ */
-
-#endif
+#ifndef _PPC_TYPES_H +#define _PPC_TYPES_H + + +#ifndef __ASSEMBLY__ + +typedef enum bool + { + FALSE = 0, + TRUE = 1 + }BOOL; + +typedef unsigned short umode_t; + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) +__extension__ typedef __signed__ long long __s64; +__extension__ typedef unsigned long long __u64; +#endif + +typedef struct { + __u32 u[4]; +} __attribute__((aligned(16))) vector128; + +#ifdef __KERNEL__ +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +typedef char INT8; +typedef short INT16; +typedef int INT32; +typedef long long INT64; +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef unsigned long long UINT64; + +#define BITS_PER_LONG 32 + +/* DMA addresses are 32-bits wide */ +typedef u32 dma_addr_t; + +#ifdef CONFIG_PHYS_64BIT +typedef unsigned long long phys_addr_t; +typedef unsigned long long phys_size_t; +#else +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; +#endif + +#endif /* __KERNEL__ */ +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/libcpu/ppc/ppc405/include/config.h b/libcpu/ppc/ppc405/include/config.h index 55a930aa89..dc01549b01 100644 --- a/libcpu/ppc/ppc405/include/config.h +++ b/libcpu/ppc/ppc405/include/config.h @@ -1,58 +1,58 @@ -#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_405EP 1 /* this is a PPC405 CPU */
-#define CONFIG_4xx 1 /* member of PPC4xx family */
-
-#define CONFIG_SYS_DCACHE_SIZE (16 << 10)/* For AMCC 405 CPUs */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-
-#define CONFIG_SYS_CLK_RECFG 0 /* Config the sys clks */
-#define CONFIG_SYS_CLK_FREQ 33333333 /*3300000*//* external frequency to pll */
-#define CONFIG_SYS_HZ 100
-#define CONFIG_SYS_PIT_RELOAD (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ)
-
-/*
- * UART
- */
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- * baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#define CONFIG_SYS_BASE_BAUD 691200
-#define CONFIG_UART1_CONSOLE 1
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- */
-#define CONFIG_SYS_FLASH_BASE 0xFFE00000
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_ADDR0 0x555
-#define CONFIG_SYS_FLASH_ADDR1 0x2aa
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
-
-#endif /* __CONFIG_H */
+#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_405EP 1 /* this is a PPC405 CPU */ +#define CONFIG_4xx 1 /* member of PPC4xx family */ + +#define CONFIG_SYS_DCACHE_SIZE (16 << 10)/* For AMCC 405 CPUs */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ + +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) + +#define CONFIG_SYS_CLK_RECFG 0 /* Config the sys clks */ +#define CONFIG_SYS_CLK_FREQ 33333333 /*3300000*//* external frequency to pll */ +#define CONFIG_SYS_HZ 100 +#define CONFIG_SYS_PIT_RELOAD (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) + +/* + * UART + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/* + * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. + * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. + * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. + * The Linux BASE_BAUD define should match this configuration. + * baseBaud = cpuClock/(uartDivisor*16) + * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, + * set Linux BASE_BAUD to 403200. + */ +#define CONFIG_SYS_BASE_BAUD 691200 +#define CONFIG_UART1_CONSOLE 1 + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + */ +#define CONFIG_SYS_FLASH_BASE 0xFFE00000 + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CONFIG_SYS_FLASH_ADDR0 0x555 +#define CONFIG_SYS_FLASH_ADDR1 0x2aa +#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short + +#endif /* __CONFIG_H */ diff --git a/libcpu/ppc/ppc405/interrupt.c b/libcpu/ppc/ppc405/interrupt.c index 6edb81739f..d0e174612c 100644 --- a/libcpu/ppc/ppc405/interrupt.c +++ b/libcpu/ppc/ppc405/interrupt.c @@ -1,133 +1,133 @@ -/*
- * File : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date Author Notes
- * 2009-01-05 Bernard first version
- */
-
-#include <rtthread.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/* interrupt nest */
-extern volatile rt_uint8_t rt_interrupt_nest;
-
-/* exception and interrupt handler table */
-#define MAX_HANDLERS 32
-rt_isr_handler_t isr_table[MAX_HANDLERS];
-
-rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrput_flag;
-
-rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector)
-{
- rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
- return RT_NULL;
-}
-
-void uic_irq_ack(unsigned int vec)
-{
- mtdcr(uic0sr, UIC_MASK(vec));
-}
-
-void uic_int_handler (unsigned int vec)
-{
- rt_interrupt_enter();
-
- /* Allow external interrupts to the CPU. */
- if (isr_table [vec] != 0)
- {
- (*isr_table[vec])(vec);
- }
- uic_irq_ack(vec);
-
- rt_interrupt_leave();
-}
-
-/* handler for UIC interrupt */
-void uic_interrupt(rt_uint32_t uic_base, int vec_base)
-{
- int vec;
- rt_uint32_t uic_msr;
- rt_uint32_t msr_shift;
-
- /*
- * Read masked interrupt status register to determine interrupt source
- */
- uic_msr = get_dcr(uic_base + UIC_MSR);
- msr_shift = uic_msr;
- vec = vec_base;
-
- while (msr_shift != 0)
- {
- if (msr_shift & 0x80000000)
- uic_int_handler(vec);
-
- /*
- * Shift msr to next position and increment vector
- */
- msr_shift <<= 1;
- vec++;
- }
-}
-
-void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
-{
- int intVal;
-
- if (((int)vector < 0) || ((int) vector >= MAX_HANDLERS))
- {
- return; /* out of range */
- }
-
- /* install the handler in the system interrupt table */
- intVal = rt_hw_interrupt_disable (); /* lock interrupts to prevent races */
-
- if (*old_handler != RT_NULL) *old_handler = isr_table[vector];
- if (new_handler != RT_NULL) isr_table[vector] = new_handler;
-
- rt_hw_interrupt_enable (intVal);
-}
-
-void rt_hw_interrupt_mask(int vector)
-{
- mtdcr(uic0er, mfdcr(uic0er) & ~UIC_MASK(vector));
-}
-
-void rt_hw_interrupt_unmask(int vector)
-{
- mtdcr(uic0er, mfdcr(uic0er) | UIC_MASK(vector));
-}
-
-void rt_hw_interrupt_init()
-{
- int vector;
- rt_uint32_t pit_value;
-
- pit_value = RT_TICK_PER_SECOND * (100000000 / RT_CPU_FREQ);
-
- /* enable pit */
- mtspr(SPRN_PIT, pit_value);
- mtspr(SPRN_TCR, 0x4400000);
-
- /* set default interrupt handler */
- for (vector = 0; vector < MAX_HANDLERS; vector++)
- {
- isr_table [vector] = (rt_isr_handler_t)rt_hw_interrupt_handle;
- }
-
- /* initialize interrupt nest, and context in thread sp */
- rt_interrupt_nest = 0;
- rt_interrupt_from_thread = 0;
- rt_interrupt_to_thread = 0;
- rt_thread_switch_interrput_flag = 0;
-}
-
-/*@}*/
+/* + * File : interrupt.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-01-05 Bernard first version + */ + +#include <rtthread.h> +#include <asm/ppc4xx.h> +#include <asm/processor.h> + +/* interrupt nest */ +extern volatile rt_uint8_t rt_interrupt_nest; + +/* exception and interrupt handler table */ +#define MAX_HANDLERS 32 +rt_isr_handler_t isr_table[MAX_HANDLERS]; + +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrput_flag; + +rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector) +{ + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + return RT_NULL; +} + +void uic_irq_ack(unsigned int vec) +{ + mtdcr(uic0sr, UIC_MASK(vec)); +} + +void uic_int_handler (unsigned int vec) +{ + rt_interrupt_enter(); + + /* Allow external interrupts to the CPU. */ + if (isr_table [vec] != 0) + { + (*isr_table[vec])(vec); + } + uic_irq_ack(vec); + + rt_interrupt_leave(); +} + +/* handler for UIC interrupt */ +void uic_interrupt(rt_uint32_t uic_base, int vec_base) +{ + int vec; + rt_uint32_t uic_msr; + rt_uint32_t msr_shift; + + /* + * Read masked interrupt status register to determine interrupt source + */ + uic_msr = get_dcr(uic_base + UIC_MSR); + msr_shift = uic_msr; + vec = vec_base; + + while (msr_shift != 0) + { + if (msr_shift & 0x80000000) + uic_int_handler(vec); + + /* + * Shift msr to next position and increment vector + */ + msr_shift <<= 1; + vec++; + } +} + +void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) +{ + int intVal; + + if (((int)vector < 0) || ((int) vector >= MAX_HANDLERS)) + { + return; /* out of range */ + } + + /* install the handler in the system interrupt table */ + intVal = rt_hw_interrupt_disable (); /* lock interrupts to prevent races */ + + if (*old_handler != RT_NULL) *old_handler = isr_table[vector]; + if (new_handler != RT_NULL) isr_table[vector] = new_handler; + + rt_hw_interrupt_enable (intVal); +} + +void rt_hw_interrupt_mask(int vector) +{ + mtdcr(uic0er, mfdcr(uic0er) & ~UIC_MASK(vector)); +} + +void rt_hw_interrupt_unmask(int vector) +{ + mtdcr(uic0er, mfdcr(uic0er) | UIC_MASK(vector)); +} + +void rt_hw_interrupt_init() +{ + int vector; + rt_uint32_t pit_value; + + pit_value = RT_TICK_PER_SECOND * (100000000 / RT_CPU_FREQ); + + /* enable pit */ + mtspr(SPRN_PIT, pit_value); + mtspr(SPRN_TCR, 0x4400000); + + /* set default interrupt handler */ + for (vector = 0; vector < MAX_HANDLERS; vector++) + { + isr_table [vector] = (rt_isr_handler_t)rt_hw_interrupt_handle; + } + + /* initialize interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrput_flag = 0; +} + +/*@}*/ diff --git a/libcpu/ppc/ppc405/io.h b/libcpu/ppc/ppc405/io.h index 917cb5e3df..32fcd56307 100644 --- a/libcpu/ppc/ppc405/io.h +++ b/libcpu/ppc/ppc405/io.h @@ -1,93 +1,93 @@ -#ifndef __IO_H__
-#define __IO_H__
-
-#define __iomem
-
-/*
- * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
- *
- * Read operations have additional twi & isync to make sure the read
- * is actually performed (i.e. the data has come back) before we start
- * executing any following instructions.
- */
-static inline int in_8(const volatile unsigned char __iomem *addr)
-{
- int ret;
-
- __asm__ __volatile__(
- "sync; lbz%U1%X1 %0,%1;\n"
- "twi 0,%0,0;\n"
- "isync" : "=r" (ret) : "m" (*addr));
- return ret;
-}
-
-static inline void out_8(volatile unsigned char __iomem *addr, int val)
-{
- __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
-}
-
-extern inline int in_le16(const volatile unsigned short __iomem *addr)
-{
- int ret;
-
- __asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
- "twi 0,%0,0;\n"
- "isync" : "=r" (ret) :
- "r" (addr), "m" (*addr));
- return ret;
-}
-
-extern inline int in_be16(const volatile unsigned short __iomem *addr)
-{
- int ret;
-
- __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
- "twi 0,%0,0;\n"
- "isync" : "=r" (ret) : "m" (*addr));
- return ret;
-}
-
-extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
-{
- __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
- "r" (val), "r" (addr));
-}
-
-extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
-{
- __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
-}
-
-extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
-{
- unsigned ret;
-
- __asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
- "twi 0,%0,0;\n"
- "isync" : "=r" (ret) :
- "r" (addr), "m" (*addr));
- return ret;
-}
-
-extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
-{
- unsigned ret;
-
- __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
- "twi 0,%0,0;\n"
- "isync" : "=r" (ret) : "m" (*addr));
- return ret;
-}
-
-extern inline void out_le32(volatile unsigned __iomem *addr, int val)
-{
- __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
- "r" (val), "r" (addr));
-}
-
-extern inline void out_be32(volatile unsigned __iomem *addr, int val)
-{
- __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
-}
-
-#endif
+#ifndef __IO_H__ +#define __IO_H__ + +#define __iomem + +/* + * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. + * + * Read operations have additional twi & isync to make sure the read + * is actually performed (i.e. the data has come back) before we start + * executing any following instructions. + */ +static inline int in_8(const volatile unsigned char __iomem *addr) +{ + int ret; + + __asm__ __volatile__( + "sync; lbz%U1%X1 %0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : "m" (*addr)); + return ret; +} + +static inline void out_8(volatile unsigned char __iomem *addr, int val) +{ + __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); +} + +extern inline int in_le16(const volatile unsigned short __iomem *addr) +{ + int ret; + + __asm__ __volatile__("sync; lhbrx %0,0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; +} + +extern inline int in_be16(const volatile unsigned short __iomem *addr) +{ + int ret; + + __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : "m" (*addr)); + return ret; +} + +extern inline void out_le16(volatile unsigned short __iomem *addr, int val) +{ + __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) : + "r" (val), "r" (addr)); +} + +extern inline void out_be16(volatile unsigned short __iomem *addr, int val) +{ + __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); +} + +extern inline unsigned in_le32(const volatile unsigned __iomem *addr) +{ + unsigned ret; + + __asm__ __volatile__("sync; lwbrx %0,0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; +} + +extern inline unsigned in_be32(const volatile unsigned __iomem *addr) +{ + unsigned ret; + + __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : "m" (*addr)); + return ret; +} + +extern inline void out_le32(volatile unsigned __iomem *addr, int val) +{ + __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) : + "r" (val), "r" (addr)); +} + +extern inline void out_be32(volatile unsigned __iomem *addr, int val) +{ + __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); +} + +#endif diff --git a/libcpu/ppc/ppc405/serial.c b/libcpu/ppc/ppc405/serial.c index 4c1a605adc..ca935fafdd 100644 --- a/libcpu/ppc/ppc405/serial.c +++ b/libcpu/ppc/ppc405/serial.c @@ -1,319 +1,319 @@ -#include <rthw.h>
-#include <rtthread.h>
-
-#include "io.h"
-#include <asm/ppc4xx-intvec.h>
-
-#define UART0_BASE 0xef600300
-#define UART1_BASE 0xef600400
-#define UCR0_MASK 0x0000007f
-#define UCR1_MASK 0x00007f00
-#define UCR0_UDIV_POS 0
-#define UCR1_UDIV_POS 8
-#define UDIV_MAX 127
-
-#define UART_RBR 0x00
-#define UART_THR 0x00
-#define UART_IER 0x01
-#define UART_IIR 0x02
-#define UART_FCR 0x02
-#define UART_LCR 0x03
-#define UART_MCR 0x04
-#define UART_LSR 0x05
-#define UART_MSR 0x06
-#define UART_SCR 0x07
-#define UART_DLL 0x00
-#define UART_DLM 0x01
-
-/*-----------------------------------------------------------------------------+
- | Line Status Register.
- +-----------------------------------------------------------------------------*/
-#define asyncLSRDataReady1 0x01
-#define asyncLSROverrunError1 0x02
-#define asyncLSRParityError1 0x04
-#define asyncLSRFramingError1 0x08
-#define asyncLSRBreakInterrupt1 0x10
-#define asyncLSRTxHoldEmpty1 0x20
-#define asyncLSRTxShiftEmpty1 0x40
-#define asyncLSRRxFifoError1 0x80
-
-/* PPC405 serial device */
-struct rt_ppc405_serial
-{
- /* inherit from device */
- struct rt_device parent;
-
- rt_uint32_t hw_base;
- rt_uint32_t irqno;
- rt_uint32_t baudrate;
-
- /* reception field */
- rt_uint16_t save_index, read_index;
- rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
-};
-struct rt_ppc405_serial ppc405_serial;
-
-/* serial character device */
-static rt_err_t rt_serial_init (rt_device_t dev)
-{
- return RT_EOK;
-}
-
-static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
-{
- struct rt_ppc405_serial* device;
- device = (struct rt_ppc405_serial*) dev;
-
- RT_ASSERT(device != RT_NULL);
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- /* Enable "RX Data Available" Interrupt on UART */
- out_8((rt_uint8_t*)device->hw_base + UART_IER, 0x01);
- /* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */
- out_8((rt_uint8_t*)device->hw_base + UART_FCR, 1);
-
- /* init UART rx interrupt */
- rt_hw_interrupt_unmask(device->irqno);
- }
-
- return RT_EOK;
-}
-
-static rt_err_t rt_serial_close(rt_device_t dev)
-{
- struct rt_ppc405_serial* device;
- device = (struct rt_ppc405_serial*) dev;
-
- RT_ASSERT(device != RT_NULL);
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- /* mask UART rx interrupt */
- rt_hw_interrupt_mask(device->irqno);
- }
-
- return RT_EOK;
-}
-
-static rt_err_t rt_serial_control(rt_device_t dev, rt_uint8_t cmd, void *args)
-{
- return RT_EOK;
-}
-
-static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
-{
- rt_uint8_t* ptr;
- struct rt_ppc405_serial* device;
-
- device = (struct rt_ppc405_serial*) dev;
- RT_ASSERT(device != RT_NULL);
-
- /* point to buffer */
- ptr = (rt_uint8_t*) buffer;
-
- if (dev->flag & RT_DEVICE_FLAG_INT_RX)
- {
- while (size)
- {
- /* interrupt receive */
- rt_base_t level;
-
- /* disable interrupt */
- level = rt_hw_interrupt_disable();
- if (device->read_index != device->save_index)
- {
- *ptr = device->rx_buffer[device->read_index];
-
- device->read_index ++;
- if (device->read_index >= RT_UART_RX_BUFFER_SIZE)
- device->read_index = 0;
- }
- else
- {
- /* no data in rx buffer */
-
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
- break;
- }
-
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
-
- ptr ++; size --;
- }
-
- return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
- }
- else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
- {
- /* not support right now */
- RT_ASSERT(0);
- }
-
- /* polling mode */
- RT_ASSERT(0);
-
- return (rt_size_t)ptr - (rt_size_t)buffer;
-}
-
-static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
-{
- char *ptr;
- struct rt_ppc405_serial* device;
-
- device = (struct rt_ppc405_serial*) dev;
- RT_ASSERT(device != RT_NULL);
-
- if (dev->flag & RT_DEVICE_FLAG_INT_TX)
- {
- /* not support */
- RT_ASSERT(0);
- }
- else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
- {
- /* not support */
- RT_ASSERT(0);
- }
-
- /* polling write */
- ptr = (char *)buffer;
-
- if (dev->flag & RT_DEVICE_FLAG_STREAM)
- {
- /* stream mode */
- while (size)
- {
- if (*ptr == '\n')
- {
- while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);
- out_8((rt_uint8_t*)device->hw_base + UART_THR, '\r');
- }
-
- while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);
- out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr);
-
- ptr ++;
- size --;
- }
- }
- else
- {
- while (size)
- {
- while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);
- out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr);
-
- ptr ++;
- size --;
- }
- }
-
- return (rt_size_t) ptr - (rt_size_t) buffer;
-}
-
-void rt_serial_set_baudrate(struct rt_ppc405_serial* device)
-{
- rt_uint32_t bdiv;
-
- bdiv = 115200;
- out_8((rt_uint8_t *)device->hw_base + UART_DLL, bdiv); /* set baudrate divisor */
- out_8((rt_uint8_t *)device->hw_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
-}
-
-void rt_serial_isr(int irqno)
-{
- unsigned char status;
- struct rt_ppc405_serial *device;
-
- device = (struct rt_ppc405_serial*) &ppc405_serial;
- status = in_8((rt_uint8_t *)device->hw_base + UART_LSR);
-
- if (status & 0x01)
- {
- rt_base_t level;
-
- while (status & 0x01)
- {
- /* disable interrupt */
- level = rt_hw_interrupt_disable();
-
- /* read character */
- device->rx_buffer[device->save_index] = (0xff & (int) in_8((rt_uint8_t *)device->hw_base));
- device->save_index ++;
- if (device->save_index >= RT_UART_RX_BUFFER_SIZE)
- device->save_index = 0;
-
- /* if the next position is read index, discard this 'read char' */
- if (device->save_index == device->read_index)
- {
- device->read_index ++;
- if (device->read_index >= RT_UART_RX_BUFFER_SIZE)
- device->read_index = 0;
- }
-
- /* enable interrupt */
- rt_hw_interrupt_enable(level);
-
- /* check error */
- if ((status & ( asyncLSRFramingError1 |
- asyncLSROverrunError1 |
- asyncLSRParityError1 |
- asyncLSRBreakInterrupt1 )) != 0)
- {
- out_8((rt_uint8_t *)device->hw_base + UART_LSR,
- asyncLSRFramingError1 |
- asyncLSROverrunError1 |
- asyncLSRParityError1 |
- asyncLSRBreakInterrupt1);
- }
-
- status = in_8((rt_uint8_t *)device->hw_base + UART_LSR);
- }
-
- /* invoke callback */
- if(device->parent.rx_indicate != RT_NULL)
- {
- device->parent.rx_indicate(&device->parent, 1);
- }
- }
-}
-
-void rt_hw_serial_init(void)
-{
- volatile rt_uint8_t val;
- struct rt_ppc405_serial* device;
-
- device = (struct rt_ppc405_serial*) &ppc405_serial;
- device->parent.type = RT_Device_Class_Char;
-
- device->hw_base = UART0_BASE;
- device->baudrate = 115200;
- device->irqno = VECNUM_U0;
- rt_hw_interrupt_install(device->irqno, rt_serial_isr, RT_NULL); /* install isr */
-
- rt_memset(device->rx_buffer, 0, sizeof(device->rx_buffer));
- device->read_index = device->save_index = 0;
-
- out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x80); /* set DLAB bit */
- /* setup baudrate */
- rt_serial_set_baudrate(device);
- out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
- out_8((rt_uint8_t *)device->hw_base + UART_FCR, 0x00); /* disable FIFO */
- out_8((rt_uint8_t *)device->hw_base + UART_MCR, 0x00); /* no modem control DTR RTS */
- val = in_8((rt_uint8_t *)device->hw_base + UART_LSR); /* clear line status */
- val = in_8((rt_uint8_t *)device->hw_base + UART_RBR); /* read receive buffer */
- out_8((rt_uint8_t *)device->hw_base + UART_SCR, 0x00); /* set scratchpad */
- out_8((rt_uint8_t *)device->hw_base + UART_IER, 0x00); /* set interrupt enable reg */
-
- device->parent.type = RT_Device_Class_Char;
- device->parent.init = rt_serial_init;
- device->parent.open = rt_serial_open;
- device->parent.close = rt_serial_close;
- device->parent.read = rt_serial_read;
- device->parent.write = rt_serial_write;
- device->parent.control = rt_serial_control;
- device->parent.user_data = RT_NULL;
-
- rt_device_register(&device->parent,
- "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM);
-}
+#include <rthw.h> +#include <rtthread.h> + +#include "io.h" +#include <asm/ppc4xx-intvec.h> + +#define UART0_BASE 0xef600300 +#define UART1_BASE 0xef600400 +#define UCR0_MASK 0x0000007f +#define UCR1_MASK 0x00007f00 +#define UCR0_UDIV_POS 0 +#define UCR1_UDIV_POS 8 +#define UDIV_MAX 127 + +#define UART_RBR 0x00 +#define UART_THR 0x00 +#define UART_IER 0x01 +#define UART_IIR 0x02 +#define UART_FCR 0x02 +#define UART_LCR 0x03 +#define UART_MCR 0x04 +#define UART_LSR 0x05 +#define UART_MSR 0x06 +#define UART_SCR 0x07 +#define UART_DLL 0x00 +#define UART_DLM 0x01 + +/*-----------------------------------------------------------------------------+ + | Line Status Register. + +-----------------------------------------------------------------------------*/ +#define asyncLSRDataReady1 0x01 +#define asyncLSROverrunError1 0x02 +#define asyncLSRParityError1 0x04 +#define asyncLSRFramingError1 0x08 +#define asyncLSRBreakInterrupt1 0x10 +#define asyncLSRTxHoldEmpty1 0x20 +#define asyncLSRTxShiftEmpty1 0x40 +#define asyncLSRRxFifoError1 0x80 + +/* PPC405 serial device */ +struct rt_ppc405_serial +{ + /* inherit from device */ + struct rt_device parent; + + rt_uint32_t hw_base; + rt_uint32_t irqno; + rt_uint32_t baudrate; + + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; +}; +struct rt_ppc405_serial ppc405_serial; + +/* serial character device */ +static rt_err_t rt_serial_init (rt_device_t dev) +{ + return RT_EOK; +} + +static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) +{ + struct rt_ppc405_serial* device; + device = (struct rt_ppc405_serial*) dev; + + RT_ASSERT(device != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* Enable "RX Data Available" Interrupt on UART */ + out_8((rt_uint8_t*)device->hw_base + UART_IER, 0x01); + /* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */ + out_8((rt_uint8_t*)device->hw_base + UART_FCR, 1); + + /* init UART rx interrupt */ + rt_hw_interrupt_unmask(device->irqno); + } + + return RT_EOK; +} + +static rt_err_t rt_serial_close(rt_device_t dev) +{ + struct rt_ppc405_serial* device; + device = (struct rt_ppc405_serial*) dev; + + RT_ASSERT(device != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* mask UART rx interrupt */ + rt_hw_interrupt_mask(device->irqno); + } + + return RT_EOK; +} + +static rt_err_t rt_serial_control(rt_device_t dev, rt_uint8_t cmd, void *args) +{ + return RT_EOK; +} + +static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + struct rt_ppc405_serial* device; + + device = (struct rt_ppc405_serial*) dev; + RT_ASSERT(device != RT_NULL); + + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (device->read_index != device->save_index) + { + *ptr = device->rx_buffer[device->read_index]; + + device->read_index ++; + if (device->read_index >= RT_UART_RX_BUFFER_SIZE) + device->read_index = 0; + } + else + { + /* no data in rx buffer */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + ptr ++; size --; + } + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } + + /* polling mode */ + RT_ASSERT(0); + + return (rt_size_t)ptr - (rt_size_t)buffer; +} + +static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + char *ptr; + struct rt_ppc405_serial* device; + + device = (struct rt_ppc405_serial*) dev; + RT_ASSERT(device != RT_NULL); + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* not support */ + RT_ASSERT(0); + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) + { + /* not support */ + RT_ASSERT(0); + } + + /* polling write */ + ptr = (char *)buffer; + + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + { + while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); + out_8((rt_uint8_t*)device->hw_base + UART_THR, '\r'); + } + + while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); + out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr); + + ptr ++; + size --; + } + } + else + { + while (size) + { + while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); + out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr); + + ptr ++; + size --; + } + } + + return (rt_size_t) ptr - (rt_size_t) buffer; +} + +void rt_serial_set_baudrate(struct rt_ppc405_serial* device) +{ + rt_uint32_t bdiv; + + bdiv = 115200; + out_8((rt_uint8_t *)device->hw_base + UART_DLL, bdiv); /* set baudrate divisor */ + out_8((rt_uint8_t *)device->hw_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */ +} + +void rt_serial_isr(int irqno) +{ + unsigned char status; + struct rt_ppc405_serial *device; + + device = (struct rt_ppc405_serial*) &ppc405_serial; + status = in_8((rt_uint8_t *)device->hw_base + UART_LSR); + + if (status & 0x01) + { + rt_base_t level; + + while (status & 0x01) + { + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + /* read character */ + device->rx_buffer[device->save_index] = (0xff & (int) in_8((rt_uint8_t *)device->hw_base)); + device->save_index ++; + if (device->save_index >= RT_UART_RX_BUFFER_SIZE) + device->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (device->save_index == device->read_index) + { + device->read_index ++; + if (device->read_index >= RT_UART_RX_BUFFER_SIZE) + device->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + /* check error */ + if ((status & ( asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1 )) != 0) + { + out_8((rt_uint8_t *)device->hw_base + UART_LSR, + asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1); + } + + status = in_8((rt_uint8_t *)device->hw_base + UART_LSR); + } + + /* invoke callback */ + if(device->parent.rx_indicate != RT_NULL) + { + device->parent.rx_indicate(&device->parent, 1); + } + } +} + +void rt_hw_serial_init(void) +{ + volatile rt_uint8_t val; + struct rt_ppc405_serial* device; + + device = (struct rt_ppc405_serial*) &ppc405_serial; + device->parent.type = RT_Device_Class_Char; + + device->hw_base = UART0_BASE; + device->baudrate = 115200; + device->irqno = VECNUM_U0; + rt_hw_interrupt_install(device->irqno, rt_serial_isr, RT_NULL); /* install isr */ + + rt_memset(device->rx_buffer, 0, sizeof(device->rx_buffer)); + device->read_index = device->save_index = 0; + + out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x80); /* set DLAB bit */ + /* setup baudrate */ + rt_serial_set_baudrate(device); + out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out_8((rt_uint8_t *)device->hw_base + UART_FCR, 0x00); /* disable FIFO */ + out_8((rt_uint8_t *)device->hw_base + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in_8((rt_uint8_t *)device->hw_base + UART_LSR); /* clear line status */ + val = in_8((rt_uint8_t *)device->hw_base + UART_RBR); /* read receive buffer */ + out_8((rt_uint8_t *)device->hw_base + UART_SCR, 0x00); /* set scratchpad */ + out_8((rt_uint8_t *)device->hw_base + UART_IER, 0x00); /* set interrupt enable reg */ + + device->parent.type = RT_Device_Class_Char; + device->parent.init = rt_serial_init; + device->parent.open = rt_serial_open; + device->parent.close = rt_serial_close; + device->parent.read = rt_serial_read; + device->parent.write = rt_serial_write; + device->parent.control = rt_serial_control; + device->parent.user_data = RT_NULL; + + rt_device_register(&device->parent, + "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM); +} diff --git a/libcpu/ppc/ppc405/traps.c b/libcpu/ppc/ppc405/traps.c index 292927b328..1deecbc92b 100644 --- a/libcpu/ppc/ppc405/traps.c +++ b/libcpu/ppc/ppc405/traps.c @@ -1,208 +1,208 @@ -#include <rtthread.h>
-#include <asm/processor.h>
-#include <asm/ppc4xx-uic.h>
-
-/* Returns 0 if exception not found and fixup otherwise. */
-extern unsigned long search_exception_table(unsigned long);
-
-/* THIS NEEDS CHANGING to use the board info structure.
- */
-#define END_OF_MEM 0x800000
-#define UICB0_ALL 0
-
-#define ESR_MCI 0x80000000
-#define ESR_PIL 0x08000000
-#define ESR_PPR 0x04000000
-#define ESR_PTR 0x02000000
-#define ESR_DST 0x00800000
-#define ESR_DIZ 0x00400000
-#define ESR_U0F 0x00008000
-
-rt_inline void set_tsr(unsigned long val)
-{
- mtspr(SPRN_TSR, val);
-}
-
-rt_inline rt_uint32_t get_esr(void)
-{
- rt_uint32_t val;
-
- val = mfspr(SPRN_ESR);
- return val;
-}
-
-/*
- * Trap & Exception support
- */
-
-void print_backtrace(unsigned long *sp)
-{
- int cnt = 0;
- unsigned long i;
-
- rt_kprintf("Call backtrace: ");
- while (sp) {
- if ((rt_uint32_t)sp > END_OF_MEM)
- break;
-
- i = sp[1];
- if (cnt++ % 7 == 0)
- rt_kprintf("\n");
- rt_kprintf("%08lX ", i);
- if (cnt > 32) break;
- sp = (unsigned long *)*sp;
- }
- rt_kprintf("\n");
-}
-
-void show_regs(struct pt_regs * regs)
-{
- int i;
-
- rt_kprintf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DEAR: %08lX\n",
- regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
- rt_kprintf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
- regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
- regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
- regs->msr&MSR_IR ? 1 : 0,
- regs->msr&MSR_DR ? 1 : 0);
-
- rt_kprintf("\n");
- for (i = 0; i < 32; i++) {
- if ((i % 8) == 0) {
- rt_kprintf("GPR%02d: ", i);
- }
-
- rt_kprintf("%08lX ", regs->gpr[i]);
- if ((i % 8) == 7) {
- rt_kprintf("\n");
- }
- }
-}
-
-void panic(const char *fmt, ...)
-{
- while(1);
-}
-
-void
-_exception(int signr, struct pt_regs *regs)
-{
- show_regs(regs);
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("Exception");
-}
-
-unsigned long
-search_exception_table(unsigned long addr)
-{
- unsigned long ret = 0;
-
- /* There is only the kernel to search. */
- // ret = search_one_table(__start___ex_table, __stop___ex_table-1, addr);
- /* if the serial port does not hang in exception, rt_kprintf can be used */
- if (ret) return ret;
-
- return 0;
-}
-
-/*
- * Handle external interrupts
- */
-void external_interrupt(struct pt_regs *regs)
-{
- u32 uic_msr;
-
- /*
- * Read masked interrupt status register to determine interrupt source
- */
- uic_msr = mfdcr(uic0msr);
-
- mtdcr(uic0sr, (uic_msr & UICB0_ALL));
-
- if (uic_msr & ~(UICB0_ALL))
- {
- uic_interrupt(UIC0_DCR_BASE, 0);
- }
-
- return;
-}
-
-void MachineCheckException(struct pt_regs *regs)
-{
- unsigned long fixup, val;
-
- if ((fixup = search_exception_table(regs->nip)) != 0) {
- regs->nip = fixup;
- val = mfspr(MCSR);
- /* Clear MCSR */
- mtspr(SPRN_MCSR, val);
- return;
- }
-
- rt_kprintf("Machine Check Exception.\n");
- rt_kprintf("Caused by (from msr): ");
- rt_kprintf("regs %p ", regs);
-
- val = get_esr();
-
- if (val& ESR_IMCP) {
- rt_kprintf("Instruction");
- mtspr(ESR, val & ~ESR_IMCP);
- } else {
- rt_kprintf("Data");
- }
- rt_kprintf(" machine check.\n");
-
- show_regs(regs);
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("machine check");
-}
-
-void AlignmentException(struct pt_regs *regs)
-{
- show_regs(regs);
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("Alignment Exception");
-}
-
-void ProgramCheckException(struct pt_regs *regs)
-{
- long esr_val;
-
- show_regs(regs);
-
- esr_val = get_esr();
- if( esr_val & ESR_PIL )
- rt_kprintf( "** Illegal Instruction **\n" );
- else if( esr_val & ESR_PPR )
- rt_kprintf( "** Privileged Instruction **\n" );
- else if( esr_val & ESR_PTR )
- rt_kprintf( "** Trap Instruction **\n" );
-
- print_backtrace((unsigned long *)regs->gpr[1]);
- panic("Program Check Exception");
-}
-
-void DecrementerPITException(struct pt_regs *regs)
-{
- /* reset PIT interrupt */
- set_tsr(0x08000000);
-
- /* increase a OS Tick */
- rt_tick_increase();
-}
-
-void UnknownException(struct pt_regs *regs)
-{
-
- rt_kprintf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
- regs->nip, regs->msr, regs->trap);
- _exception(0, regs);
-}
-
-void DebugException(struct pt_regs *regs)
-{
- rt_kprintf("Debugger trap at @ %lx @regs %lx\n", regs->nip, (rt_uint32_t)regs );
- show_regs(regs);
-}
+#include <rtthread.h> +#include <asm/processor.h> +#include <asm/ppc4xx-uic.h> + +/* Returns 0 if exception not found and fixup otherwise. */ +extern unsigned long search_exception_table(unsigned long); + +/* THIS NEEDS CHANGING to use the board info structure. + */ +#define END_OF_MEM 0x800000 +#define UICB0_ALL 0 + +#define ESR_MCI 0x80000000 +#define ESR_PIL 0x08000000 +#define ESR_PPR 0x04000000 +#define ESR_PTR 0x02000000 +#define ESR_DST 0x00800000 +#define ESR_DIZ 0x00400000 +#define ESR_U0F 0x00008000 + +rt_inline void set_tsr(unsigned long val) +{ + mtspr(SPRN_TSR, val); +} + +rt_inline rt_uint32_t get_esr(void) +{ + rt_uint32_t val; + + val = mfspr(SPRN_ESR); + return val; +} + +/* + * Trap & Exception support + */ + +void print_backtrace(unsigned long *sp) +{ + int cnt = 0; + unsigned long i; + + rt_kprintf("Call backtrace: "); + while (sp) { + if ((rt_uint32_t)sp > END_OF_MEM) + break; + + i = sp[1]; + if (cnt++ % 7 == 0) + rt_kprintf("\n"); + rt_kprintf("%08lX ", i); + if (cnt > 32) break; + sp = (unsigned long *)*sp; + } + rt_kprintf("\n"); +} + +void show_regs(struct pt_regs * regs) +{ + int i; + + rt_kprintf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DEAR: %08lX\n", + regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); + rt_kprintf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", + regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, + regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, + regs->msr&MSR_IR ? 1 : 0, + regs->msr&MSR_DR ? 1 : 0); + + rt_kprintf("\n"); + for (i = 0; i < 32; i++) { + if ((i % 8) == 0) { + rt_kprintf("GPR%02d: ", i); + } + + rt_kprintf("%08lX ", regs->gpr[i]); + if ((i % 8) == 7) { + rt_kprintf("\n"); + } + } +} + +void panic(const char *fmt, ...) +{ + while(1); +} + +void +_exception(int signr, struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Exception"); +} + +unsigned long +search_exception_table(unsigned long addr) +{ + unsigned long ret = 0; + + /* There is only the kernel to search. */ + // ret = search_one_table(__start___ex_table, __stop___ex_table-1, addr); + /* if the serial port does not hang in exception, rt_kprintf can be used */ + if (ret) return ret; + + return 0; +} + +/* + * Handle external interrupts + */ +void external_interrupt(struct pt_regs *regs) +{ + u32 uic_msr; + + /* + * Read masked interrupt status register to determine interrupt source + */ + uic_msr = mfdcr(uic0msr); + + mtdcr(uic0sr, (uic_msr & UICB0_ALL)); + + if (uic_msr & ~(UICB0_ALL)) + { + uic_interrupt(UIC0_DCR_BASE, 0); + } + + return; +} + +void MachineCheckException(struct pt_regs *regs) +{ + unsigned long fixup, val; + + if ((fixup = search_exception_table(regs->nip)) != 0) { + regs->nip = fixup; + val = mfspr(MCSR); + /* Clear MCSR */ + mtspr(SPRN_MCSR, val); + return; + } + + rt_kprintf("Machine Check Exception.\n"); + rt_kprintf("Caused by (from msr): "); + rt_kprintf("regs %p ", regs); + + val = get_esr(); + + if (val& ESR_IMCP) { + rt_kprintf("Instruction"); + mtspr(ESR, val & ~ESR_IMCP); + } else { + rt_kprintf("Data"); + } + rt_kprintf(" machine check.\n"); + + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("machine check"); +} + +void AlignmentException(struct pt_regs *regs) +{ + show_regs(regs); + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Alignment Exception"); +} + +void ProgramCheckException(struct pt_regs *regs) +{ + long esr_val; + + show_regs(regs); + + esr_val = get_esr(); + if( esr_val & ESR_PIL ) + rt_kprintf( "** Illegal Instruction **\n" ); + else if( esr_val & ESR_PPR ) + rt_kprintf( "** Privileged Instruction **\n" ); + else if( esr_val & ESR_PTR ) + rt_kprintf( "** Trap Instruction **\n" ); + + print_backtrace((unsigned long *)regs->gpr[1]); + panic("Program Check Exception"); +} + +void DecrementerPITException(struct pt_regs *regs) +{ + /* reset PIT interrupt */ + set_tsr(0x08000000); + + /* increase a OS Tick */ + rt_tick_increase(); +} + +void UnknownException(struct pt_regs *regs) +{ + + rt_kprintf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", + regs->nip, regs->msr, regs->trap); + _exception(0, regs); +} + +void DebugException(struct pt_regs *regs) +{ + rt_kprintf("Debugger trap at @ %lx @regs %lx\n", regs->nip, (rt_uint32_t)regs ); + show_regs(regs); +} |