4 files changed, 6 insertions, 6 deletions
diff --git a/libcpu/risc-v/common/cpuport.c b/libcpu/risc-v/common/cpuport.c
index 6cb8aaf3e7..622e1bd321 100644
--- a/libcpu/risc-v/common/cpuport.c
+++ b/libcpu/risc-v/common/cpuport.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/risc-v/common/cpuport.h b/libcpu/risc-v/common/cpuport.h
index d6cec2f0cf..e625d9f91f 100644
--- a/libcpu/risc-v/common/cpuport.h
+++ b/libcpu/risc-v/common/cpuport.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -30,13 +30,13 @@
 #define FSTORE                  fsd
 #define FLOAD                   fld
 #define FREGBYTES               8
-#define rv_floatreg_t           rt_int64_t  	       
+#define rv_floatreg_t           rt_int64_t
 #endif
 #ifdef ARCH_RISCV_FPU_S
 #define FSTORE                  fsw
 #define FLOAD                   flw
 #define FREGBYTES               4
-#define rv_floatreg_t           rt_int32_t  	       
+#define rv_floatreg_t           rt_int32_t
 #endif
 #endif
 
diff --git a/libcpu/risc-v/common/riscv-ops.h b/libcpu/risc-v/common/riscv-ops.h
index 0b321c6de4..35d009ad53 100644
--- a/libcpu/risc-v/common/riscv-ops.h
+++ b/libcpu/risc-v/common/riscv-ops.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/risc-v/common/riscv-plic.h b/libcpu/risc-v/common/riscv-plic.h
index 1da14b2e45..53e19d2962 100644
--- a/libcpu/risc-v/common/riscv-plic.h
+++ b/libcpu/risc-v/common/riscv-plic.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *