17 files changed, 237 insertions, 37 deletions
diff --git a/libcpu/risc-v/common/cpuport.c b/libcpu/risc-v/common/cpuport.c
index 6cb8aaf3e7..622e1bd321 100644
--- a/libcpu/risc-v/common/cpuport.c
+++ b/libcpu/risc-v/common/cpuport.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/risc-v/common/cpuport.h b/libcpu/risc-v/common/cpuport.h
index d6cec2f0cf..e625d9f91f 100644
--- a/libcpu/risc-v/common/cpuport.h
+++ b/libcpu/risc-v/common/cpuport.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -30,13 +30,13 @@
 #define FSTORE                  fsd
 #define FLOAD                   fld
 #define FREGBYTES               8
-#define rv_floatreg_t           rt_int64_t  	       
+#define rv_floatreg_t           rt_int64_t
 #endif
 #ifdef ARCH_RISCV_FPU_S
 #define FSTORE                  fsw
 #define FLOAD                   flw
 #define FREGBYTES               4
-#define rv_floatreg_t           rt_int32_t  	       
+#define rv_floatreg_t           rt_int32_t
 #endif
 #endif
 
diff --git a/libcpu/risc-v/common/riscv-ops.h b/libcpu/risc-v/common/riscv-ops.h
index 0b321c6de4..35d009ad53 100644
--- a/libcpu/risc-v/common/riscv-ops.h
+++ b/libcpu/risc-v/common/riscv-ops.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/risc-v/common/riscv-plic.h b/libcpu/risc-v/common/riscv-plic.h
index 1da14b2e45..53e19d2962 100644
--- a/libcpu/risc-v/common/riscv-plic.h
+++ b/libcpu/risc-v/common/riscv-plic.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/risc-v/juicevm/SConscript b/libcpu/risc-v/juicevm/SConscript
new file mode 100755
index 0000000000..20f325b692
--- /dev/null
+++ b/libcpu/risc-v/juicevm/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/risc-v/juicevm/interrupt.c b/libcpu/risc-v/juicevm/interrupt.c
new file mode 100755
index 0000000000..24b8be7f0c
--- /dev/null
+++ b/libcpu/risc-v/juicevm/interrupt.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021/04/24     Juice      The first version
+ */
+
+#include <rthw.h>
+
+#include <board.h>
+
+typedef void (*irq_handler_t)(void);
+extern const irq_handler_t isrTable[];
+
+uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc, uintptr_t *sp)
+{
+    uint32_t intNum;
+    if (mcause & 0x80000000) /* For external interrupt. */
+    {
+    }
+    else
+    {
+        intNum = mcause & 0x1FUL;
+        /* Now call the real irq handler for intNum */
+        if (intNum <= 24)
+        {
+            if (isrTable[intNum])isrTable[intNum]();
+        }
+    }
+}
diff --git a/libcpu/risc-v/juicevm/interrupt_gcc.S b/libcpu/risc-v/juicevm/interrupt_gcc.S
new file mode 100755
index 0000000000..8406926b5f
--- /dev/null
+++ b/libcpu/risc-v/juicevm/interrupt_gcc.S
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021/04/24     Juice      The first version
+ */
+
+#include "cpuport.h"
+
+.section      .text.entry
+.align 2
+.global trap_entry
+trap_entry:
+
+/* save thread context to thread stack */
+addi sp, sp, -32 * REGBYTES
+
+STORE x1,   1 * REGBYTES(sp)
+
+csrr  x1, mstatus
+STORE x1,   2 * REGBYTES(sp)
+
+csrr  x1, mepc
+STORE x1, 0 * REGBYTES(sp)
+
+STORE x4,   4 * REGBYTES(sp)
+STORE x5,   5 * REGBYTES(sp)
+STORE x6,   6 * REGBYTES(sp)
+STORE x7,   7 * REGBYTES(sp)
+STORE x8,   8 * REGBYTES(sp)
+STORE x9,   9 * REGBYTES(sp)
+STORE x10, 10 * REGBYTES(sp)
+STORE x11, 11 * REGBYTES(sp)
+STORE x12, 12 * REGBYTES(sp)
+STORE x13, 13 * REGBYTES(sp)
+STORE x14, 14 * REGBYTES(sp)
+STORE x15, 15 * REGBYTES(sp)
+STORE x16, 16 * REGBYTES(sp)
+STORE x17, 17 * REGBYTES(sp)
+STORE x18, 18 * REGBYTES(sp)
+STORE x19, 19 * REGBYTES(sp)
+STORE x20, 20 * REGBYTES(sp)
+STORE x21, 21 * REGBYTES(sp)
+STORE x22, 22 * REGBYTES(sp)
+STORE x23, 23 * REGBYTES(sp)
+STORE x24, 24 * REGBYTES(sp)
+STORE x25, 25 * REGBYTES(sp)
+STORE x26, 26 * REGBYTES(sp)
+STORE x27, 27 * REGBYTES(sp)
+STORE x28, 28 * REGBYTES(sp)
+STORE x29, 29 * REGBYTES(sp)
+STORE x30, 30 * REGBYTES(sp)
+STORE x31, 31 * REGBYTES(sp)
+
+/* switch to interrupt stack */
+move  s0, sp
+
+/* handle interrupt */
+call  rt_interrupt_enter
+csrr  a0, mcause
+csrr  a1, mepc
+mv    a2, s0
+call  handle_trap
+call  rt_interrupt_leave
+
+
+/* switch to from_thread stack */
+move  sp, s0
+
+/* need to switch new thread */
+la    s0, rt_thread_switch_interrupt_flag
+lw    s2, 0(s0)
+beqz  s2, spurious_interrupt
+sw    zero, 0(s0)
+
+la    s0, rt_interrupt_from_thread
+LOAD  s1, 0(s0)
+STORE sp, 0(s1)
+
+la    s0, rt_interrupt_to_thread
+LOAD  s1, 0(s0)
+LOAD  sp, 0(s1)
+
+spurious_interrupt:
+tail rt_hw_context_switch_exit
diff --git a/libcpu/risc-v/juicevm/startup_gcc.S b/libcpu/risc-v/juicevm/startup_gcc.S
new file mode 100755
index 0000000000..1a41c731fb
--- /dev/null
+++ b/libcpu/risc-v/juicevm/startup_gcc.S
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021/04/24     Juice      The first version
+ */
+
+
+.global   _start
+.section ".start", "ax"
+_start:
+.align 3
+csrw mideleg, 0
+csrw medeleg, 0
+csrw mie, 0
+csrw mip, 0
+la t0, trap_entry
+csrw mtvec, t0
+
+li x1, 0
+li x2, 0
+li x3, 0
+li x4, 0
+li x5, 0
+li x6, 0
+li x7, 0
+li x8, 0
+li x9, 0
+li x10, 0
+li x11, 0
+li x12, 0
+li x13, 0
+li x14, 0
+li x15, 0
+li x16, 0
+li x17, 0
+li x18, 0
+li x19, 0
+li x20, 0
+li x21, 0
+li x22, 0
+li x23, 0
+li x24, 0
+li x25, 0
+li x26, 0
+li x27, 0
+li x28, 0
+li x29, 0
+li x30, 0
+li x31, 0
+
+/* set to initial state of FPU and disable interrupt */
+li t0, 0
+csrs mstatus, t0
+
+.option push
+.option norelax
+la gp, __global_pointer$
+la   sp, __stack
+call entry
+call exit
+.option pop
diff --git a/libcpu/risc-v/k210/cpuport_smp.c b/libcpu/risc-v/k210/cpuport_smp.c
index 8c57dfeafc..113df9b3e2 100644
--- a/libcpu/risc-v/k210/cpuport_smp.c
+++ b/libcpu/risc-v/k210/cpuport_smp.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/risc-v/k210/interrupt.c b/libcpu/risc-v/k210/interrupt.c
index b582599daf..934acbdbf8 100644
--- a/libcpu/risc-v/k210/interrupt.c
+++ b/libcpu/risc-v/k210/interrupt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/risc-v/k210/tick.c b/libcpu/risc-v/k210/tick.c
index 144f7f1fff..2a76b50b6d 100644
--- a/libcpu/risc-v/k210/tick.c
+++ b/libcpu/risc-v/k210/tick.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/risc-v/k210/tick.h b/libcpu/risc-v/k210/tick.h
index 0821004263..0bfd6f62e8 100644
--- a/libcpu/risc-v/k210/tick.h
+++ b/libcpu/risc-v/k210/tick.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/risc-v/nuclei/cpuport.c b/libcpu/risc-v/nuclei/cpuport.c
index 717e9bb1c7..e74d174a54 100644
--- a/libcpu/risc-v/nuclei/cpuport.c
+++ b/libcpu/risc-v/nuclei/cpuport.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  * Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
@@ -26,23 +26,23 @@
 
 /**
  * @brief from thread used interrupt context switch
- * 
+ *
  */
 volatile rt_ubase_t  rt_interrupt_from_thread = 0;
 /**
  * @brief to thread used interrupt context switch
- * 
+ *
  */
 volatile rt_ubase_t  rt_interrupt_to_thread   = 0;
 /**
  * @brief flag to indicate context switch in interrupt or not
- * 
+ *
  */
 volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0;
 
 /**
  * @brief thread stack frame of saved context
- * 
+ *
  */
 struct rt_hw_stack_frame
 {
@@ -121,7 +121,7 @@ rt_uint8_t *rt_hw_stack_init(void       *tentry,
 
 /**
  * @brief Do rt-thread context switch in interrupt context
- * 
+ *
  * @param from thread sp of from thread
  * @param to thread sp of to thread
  */
@@ -137,7 +137,7 @@ void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to)
 
 /**
  * @brief Do rt-thread context switch in task context
- * 
+ *
  * @param from thread sp of from thread
  * @param to thread sp of to thread
  */
@@ -150,7 +150,7 @@ void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to)
 
 /**
  * @brief shutdown CPU
- * 
+ *
  */
 RT_WEAK void rt_hw_cpu_shutdown()
 {
@@ -166,9 +166,9 @@ RT_WEAK void rt_hw_cpu_shutdown()
 
 /**
  * @brief Do extra task switch code
- * 
+ *
  * @details
- * 
+ *
  * - Clear software timer interrupt request flag
  * - clear rt_thread_switch_interrupt_flag to 0
  */
@@ -181,9 +181,9 @@ void rt_hw_taskswitch(void)
 
 /**
  * @brief Setup systimer and software timer interrupt
- * 
- * @details 
- * 
+ *
+ * @details
+ *
  * - Set Systimer interrupt as NON-VECTOR interrupt with lowest interrupt level
  * - Set software timer interrupt as VECTOR interrupt with lowest interrupt level
  * - Enable these two interrupts
@@ -216,7 +216,7 @@ void rt_hw_ticksetup(void)
 
 /**
  * @brief This is the timer interrupt service routine.
- * 
+ *
  */
 void SysTick_Handler(void)
 {
@@ -235,13 +235,13 @@ void SysTick_Handler(void)
 
 /**
  * @brief Disable cpu interrupt
- * 
+ *
  * @details
- * 
+ *
  * - Disable cpu interrupt by clear MIE bit in MSTATUS
  * - Return the previous value in MSTATUS before clear MIE bit
- * 
- * @return the previous value in MSTATUS before clear MIE bit 
+ *
+ * @return the previous value in MSTATUS before clear MIE bit
  */
 rt_base_t rt_hw_interrupt_disable(void)
 {
@@ -250,7 +250,7 @@ rt_base_t rt_hw_interrupt_disable(void)
 
 /**
  * @brief Restore previous saved interrupt status
- * 
+ *
  * @param level previous saved MSTATUS value
  */
 void rt_hw_interrupt_enable(rt_base_t level)
diff --git a/libcpu/risc-v/nuclei/cpuport.h b/libcpu/risc-v/nuclei/cpuport.h
index 3736f0078a..1f9634d4b1 100644
--- a/libcpu/risc-v/nuclei/cpuport.h
+++ b/libcpu/risc-v/nuclei/cpuport.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  * Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
diff --git a/libcpu/risc-v/rv32m1/interrupt.c b/libcpu/risc-v/rv32m1/interrupt.c
index 72cb344ff7..8da0dcfda6 100644
--- a/libcpu/risc-v/rv32m1/interrupt.c
+++ b/libcpu/risc-v/rv32m1/interrupt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/risc-v/t-head/e906/cpuport.c b/libcpu/risc-v/t-head/e906/cpuport.c
index 998bfdc340..0eaf5ffbce 100644
--- a/libcpu/risc-v/t-head/e906/cpuport.c
+++ b/libcpu/risc-v/t-head/e906/cpuport.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -131,7 +131,7 @@ rt_uint8_t *rt_hw_stack_init(void       *tentry,
 
 
 /**
- * This function will disable global interrupt 
+ * This function will disable global interrupt
  *
  * @param none
  *
@@ -145,7 +145,7 @@ rt_base_t rt_hw_interrupt_disable(void)
 }
 
 /**
- * This function will ennable global interrupt 
+ * This function will ennable global interrupt
  *
  * @param level not used
  *
diff --git a/libcpu/risc-v/t-head/e906/cpuport.h b/libcpu/risc-v/t-head/e906/cpuport.h
index 90efc07653..20302f44aa 100644
--- a/libcpu/risc-v/t-head/e906/cpuport.h
+++ b/libcpu/risc-v/t-head/e906/cpuport.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -42,13 +42,13 @@
 #define FSTORE                  fsd
 #define FLOAD                   fld
 #define FREGBYTES               8
-#define rv_floatreg_t           rt_int64_t  	       
+#define rv_floatreg_t           rt_int64_t
 #endif
 #ifdef ARCH_RISCV_FPU_S
 #define FSTORE                  fsw
 #define FLOAD                   flw
 #define FREGBYTES               4
-#define rv_floatreg_t           rt_int32_t  	       
+#define rv_floatreg_t           rt_int32_t
 #endif
 #endif