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-rw-r--r--libcpu/mips/loongson/cpu.c7
-rw-r--r--libcpu/mips/loongson/interrupt.c5
-rw-r--r--libcpu/mips/loongson/stack.c4
-rw-r--r--libcpu/mips/loongson_1b/cache.c19
-rw-r--r--libcpu/mips/loongson_1b/context_gcc.S1
-rw-r--r--libcpu/mips/loongson_1b/cpuport.c8
-rw-r--r--libcpu/mips/loongson_1b/exception.c1
-rw-r--r--libcpu/mips/loongson_1b/interrupt.c9
-rw-r--r--libcpu/mips/loongson_1b/start_gcc.S132
9 files changed, 99 insertions, 87 deletions
diff --git a/libcpu/mips/loongson/cpu.c b/libcpu/mips/loongson/cpu.c
index 06673bcbb9..49b310d01c 100644
--- a/libcpu/mips/loongson/cpu.c
+++ b/libcpu/mips/loongson/cpu.c
@@ -16,15 +16,16 @@
#include <soc3210.h>
/**
- * @addtogroup Loogonson SoC3210
+ * @addtogroup Loongson SoC3210
*/
+
/*@{*/
/**
* this function will reset CPU
*
*/
-void rt_hw_cpu_reset()
+void rt_hw_cpu_reset(void)
{
/* open the watch-dog */
WD_TIMER = 0x01; /* watch dog will be timeout after 1 tick */
@@ -38,7 +39,7 @@ void rt_hw_cpu_reset()
* this function will shutdown CPU
*
*/
-void rt_hw_cpu_shutdown()
+void rt_hw_cpu_shutdown(void)
{
rt_kprintf("shutdown...\n");
diff --git a/libcpu/mips/loongson/interrupt.c b/libcpu/mips/loongson/interrupt.c
index 20cc2f8b9b..d70b58da97 100644
--- a/libcpu/mips/loongson/interrupt.c
+++ b/libcpu/mips/loongson/interrupt.c
@@ -25,8 +25,9 @@ void rt_interrupt_dispatch(void *ptreg);
void rt_hw_timer_handler();
/**
- * @addtogroup Loogonson SoC3210
+ * @addtogroup Loongson SoC3210
*/
+
/*@{*/
void rt_hw_interrupt_handler(int vector)
@@ -37,7 +38,7 @@ void rt_hw_interrupt_handler(int vector)
/**
* This function will initialize hardware interrupt
*/
-void rt_hw_interrupt_init()
+void rt_hw_interrupt_init(void)
{
rt_int32_t index;
diff --git a/libcpu/mips/loongson/stack.c b/libcpu/mips/loongson/stack.c
index 187845da58..60e9aa4fb4 100644
--- a/libcpu/mips/loongson/stack.c
+++ b/libcpu/mips/loongson/stack.c
@@ -12,11 +12,13 @@
* 2010-05-17 swkyer first version
* 2010-07-07 Bernard porting to Jz47xx
*/
+
#include <rtthread.h>
/**
- * @addtogroup Loogonson SoC3210
+ * @addtogroup Loongson SoC3210
*/
+
/*@{*/
extern rt_uint32_t cp0_get_cause(void);
diff --git a/libcpu/mips/loongson_1b/cache.c b/libcpu/mips/loongson_1b/cache.c
index 5782156380..550d4160ff 100644
--- a/libcpu/mips/loongson_1b/cache.c
+++ b/libcpu/mips/loongson_1b/cache.c
@@ -12,6 +12,7 @@
* 2010-07-09 Bernard first version
* 2011-08-08 lgnq modified for LS1B
*/
+
#include "../common/mipsregs.h"
#define K0BASE 0x80000000
@@ -43,10 +44,9 @@ typedef struct cacheop_t
static cacheop_t cacheop, *pcacheop;
static cacheinfo_t cacheinfo, *pcacheinfo;
-int identify_cpu (void)
+int identify_cpu(void)
{
unsigned int cpu_id;
- void invalidate_cache (void);
pcacheop = &cacheop;
pcacheinfo = &cacheinfo;
@@ -112,8 +112,7 @@ void invalidate_writeback_dcache_all(void)
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
- start = K0BASE;
- while(start < end)
+ while (start < end)
{
Writeback_Invalidate_Dcache(start); //hit writeback invalidate
start += pcacheinfo->dcacheline_size;
@@ -127,7 +126,7 @@ void invalidate_writeback_dcache(unsigned long addr, int size)
start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
- while(start <end)
+ while (start <end)
{
Writeback_Invalidate_Dcache(start);
start += pcacheinfo->dcacheline_size;
@@ -139,18 +138,18 @@ void invalidate_icache_all(void)
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->icache_size);
- while(start < end)
+ while (start < end)
{
pcacheop->Invalidate_Icache(start);
start += pcacheinfo->icacheline_size;
}
}
-void invalidate_dcache_all()
+void invalidate_dcache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
- while(start <end)
+ while (start <end)
{
Invalidate_Dcache_Fill_Gc3210I(start);
start += pcacheinfo->icacheline_size;
@@ -163,7 +162,7 @@ void init_dcache(void)
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
- while(start < end)
+ while (start < end)
{
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
@@ -190,7 +189,7 @@ void rt_hw_cache_init(void)
/*
* 3. invalidate instruction cache;
*/
- while(start < end)
+ while (start < end)
{
pcacheop->Invalidate_Icache(start); //index invalidate icache
start += pcacheinfo->icacheline_size;
diff --git a/libcpu/mips/loongson_1b/context_gcc.S b/libcpu/mips/loongson_1b/context_gcc.S
index e6f710e048..ec8e0b1258 100644
--- a/libcpu/mips/loongson_1b/context_gcc.S
+++ b/libcpu/mips/loongson_1b/context_gcc.S
@@ -13,6 +13,7 @@
* 2010-09-11 bernard port to Loongson SoC3210
* 2011-08-08 lgnq port to Loongson LS1B
*/
+
#include "../common/mips.inc"
#include "../common/stackframe.h"
diff --git a/libcpu/mips/loongson_1b/cpuport.c b/libcpu/mips/loongson_1b/cpuport.c
index 6182d39901..9917b0cce0 100644
--- a/libcpu/mips/loongson_1b/cpuport.c
+++ b/libcpu/mips/loongson_1b/cpuport.c
@@ -12,19 +12,21 @@
* 2010-07-09 Bernard first version
* 2010-09-11 Bernard add CPU reset implementation
*/
+
#include <rtthread.h>
#include "ls1b.h"
/**
- * @addtogroup Loogonson LS1B
+ * @addtogroup Loongson LS1B
*/
+
/*@{*/
/**
* this function will reset CPU
*
*/
-void rt_hw_cpu_reset()
+void rt_hw_cpu_reset(void)
{
/* open the watch-dog */
WDT_EN = 0x01; /* watch dog enable */
@@ -39,7 +41,7 @@ void rt_hw_cpu_reset()
* this function will shutdown CPU
*
*/
-void rt_hw_cpu_shutdown()
+void rt_hw_cpu_shutdown(void)
{
rt_kprintf("shutdown...\n");
diff --git a/libcpu/mips/loongson_1b/exception.c b/libcpu/mips/loongson_1b/exception.c
index fcc768fb85..f46ddfa14a 100644
--- a/libcpu/mips/loongson_1b/exception.c
+++ b/libcpu/mips/loongson_1b/exception.c
@@ -19,6 +19,7 @@
/**
* @addtogroup Loongson
*/
+
/*@{*/
/**
diff --git a/libcpu/mips/loongson_1b/interrupt.c b/libcpu/mips/loongson_1b/interrupt.c
index 14dc820190..ddba29f489 100644
--- a/libcpu/mips/loongson_1b/interrupt.c
+++ b/libcpu/mips/loongson_1b/interrupt.c
@@ -12,13 +12,15 @@
* 2010-10-15 Bernard first version
* 2010-10-15 lgnq modified for LS1B
*/
+
#include <rtthread.h>
#include "ls1b.h"
#define MAX_INTR 32
extern rt_uint32_t rt_interrupt_nest;
-rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
+rt_uint32_t rt_interrupt_from_thread;
+rt_uint32_t rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
static rt_isr_handler_t irq_handle_table[MAX_INTR];
@@ -29,8 +31,9 @@ static struct ls1b_intc_regs volatile *ls1b_hw0_icregs
= (struct ls1b_intc_regs volatile *)(LS1B_INTREG_BASE);
/**
- * @addtogroup Loogonson LS1B
+ * @addtogroup Loongson LS1B
*/
+
/*@{*/
void rt_hw_interrupt_handler(int vector)
@@ -41,7 +44,7 @@ void rt_hw_interrupt_handler(int vector)
/**
* This function will initialize hardware interrupt
*/
-void rt_hw_interrupt_init()
+void rt_hw_interrupt_init(void)
{
rt_int32_t index;
diff --git a/libcpu/mips/loongson_1b/start_gcc.S b/libcpu/mips/loongson_1b/start_gcc.S
index 964e334ead..dc6e51849a 100644
--- a/libcpu/mips/loongson_1b/start_gcc.S
+++ b/libcpu/mips/loongson_1b/start_gcc.S
@@ -12,17 +12,18 @@
* 2010-05-17 swkyer first version
* 2010-09-04 bernard porting to Jz47xx
*/
+
#include "../common/mips.inc"
#include "../common/stackframe.h"
- .section ".start", "ax"
- .set noreorder
+ .section ".start", "ax"
+ .set noreorder
- /* the program entry */
- .globl _start
+ /* the program entry */
+ .globl _start
_start:
- .set noreorder
- la ra, _start
+ .set noreorder
+ la ra, _start
/* disable interrupt */
mfc0 t0, CP0_STATUS
@@ -32,104 +33,105 @@ _start:
/* disable cache */
mfc0 t0, CP0_CONFIG
- and t0, 0xfffffff8
- or t0, 0x2 # disable,!default value is not it!
+ and t0, 0xfffffff8
+ or t0, 0x2 # disable,!default value is not it!
mtc0 t0, CP0_CONFIG # Set CPU to disable cache.
nop
- /* setup stack pointer */
- li sp, SYSTEM_STACK
- la gp, _gp
+ /* setup stack pointer */
+ li sp, SYSTEM_STACK
+ la gp, _gp
- /* clear bss */
- la t0, __bss_start
- la t1, __bss_end
+ /* clear bss */
+ la t0, __bss_start
+ la t1, __bss_end
_clr_bss_loop:
- sw zero, 0(t0)
- bne t0, t1, _clr_bss_loop
- addiu t0, t0, 4
+ sw zero, 0(t0)
+ bne t0, t1, _clr_bss_loop
+ addiu t0, t0, 4
- /* jump to RT-Thread RTOS */
- jal rtthread_startup
- nop
+ /* jump to RT-Thread RTOS */
+ jal rtthread_startup
+ nop
- /* restart, never die */
- j _start
- nop
- .set reorder
+ /* restart, never die */
+ j _start
+ nop
+ .set reorder
- .globl cp0_get_cause
+ .globl cp0_get_cause
cp0_get_cause:
- mfc0 v0, CP0_CAUSE
- jr ra
- nop
+ mfc0 v0, CP0_CAUSE
+ jr ra
+ nop
- .globl cp0_get_status
+ .globl cp0_get_status
cp0_get_status:
- mfc0 v0, CP0_STATUS
- jr ra
- nop
+ mfc0 v0, CP0_STATUS
+ jr ra
+ nop
- .globl cp0_get_hi
+ .globl cp0_get_hi
cp0_get_hi:
- mfhi v0
- jr ra
- nop
+ mfhi v0
+ jr ra
+ nop
- .globl cp0_get_lo
+ .globl cp0_get_lo
cp0_get_lo:
- mflo v0
- jr ra
- nop
+ mflo v0
+ jr ra
+ nop
.extern tlb_refill_handler
.extern cache_error_handler
/* Exception Handler */
+
/* 0x0 - TLB refill handler */
- .section .vectors.1, "ax", %progbits
+ .section .vectors.1, "ax", %progbits
.global tlb_refill_exception
.type tlb_refill_exception,@function
tlb_refill_exception:
- j tlb_refill_handler
- nop
+ j tlb_refill_handler
+ nop
/* 0x100 - Cache error handler */
- .section .vectors.2, "ax", %progbits
- j cache_error_handler
- nop
+ .section .vectors.2, "ax", %progbits
+ j cache_error_handler
+ nop
/* 0x180 - Exception/Interrupt handler */
- .section .vectors.3, "ax", %progbits
+ .section .vectors.3, "ax", %progbits
.global general_exception
.type general_exception,@function
general_exception:
- j _general_exception_handler
- nop
+ j _general_exception_handler
+ nop
/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
- .section .vectors.4, "ax", %progbits
+ .section .vectors.4, "ax", %progbits
.global irq_exception
.type irq_exception,@function
irq_exception:
- j _irq_handler
- nop
+ j _irq_handler
+ nop
- .section .vectors, "ax", %progbits
+ .section .vectors, "ax", %progbits
.extern mips_irq_handle
- /* general exception handler */
+ /* general exception handler */
_general_exception_handler:
- .set noreorder
- la k0, mips_irq_handle
- jr k0
- nop
- .set reorder
+ .set noreorder
+ la k0, mips_irq_handle
+ jr k0
+ nop
+ .set reorder
- /* interrupt handler */
+ /* interrupt handler */
_irq_handler:
- .set noreorder
- la k0, mips_irq_handle
- jr k0
- nop
- .set reorder
+ .set noreorder
+ la k0, mips_irq_handle
+ jr k0
+ nop
+ .set reorder
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-30 14:18:25 +0000