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-rw-r--r--libcpu/aarch64/common/context_gcc.S2
-rw-r--r--libcpu/aarch64/common/gicv3.c6
-rw-r--r--libcpu/aarch64/common/gicv3.h7
-rw-r--r--libcpu/aarch64/common/interrupt.c4
-rw-r--r--libcpu/aarch64/cortex-a/entry_point.S5
-rw-r--r--libcpu/arm/cortex-a/cpuport.c2
-rw-r--r--libcpu/arm/cortex-a/interrupt.c3
-rw-r--r--libcpu/arm/cortex-a/start_gcc.S101
8 files changed, 73 insertions, 57 deletions
diff --git a/libcpu/aarch64/common/context_gcc.S b/libcpu/aarch64/common/context_gcc.S
index 0a611cbf48..6afc676ae3 100644
--- a/libcpu/aarch64/common/context_gcc.S
+++ b/libcpu/aarch64/common/context_gcc.S
@@ -24,7 +24,7 @@ rt_hw_cpu_id_set:
/*
int rt_hw_cpu_id(void)
*/
-.global rt_hw_cpu_id
+.weak rt_hw_cpu_id
.type rt_hw_cpu_id, @function
rt_hw_cpu_id:
mrs x0, tpidr_el1 /* MPIDR_EL1: Multi-Processor Affinity Register */
diff --git a/libcpu/aarch64/common/gicv3.c b/libcpu/aarch64/common/gicv3.c
index 18fdcddc7f..35864fea2f 100644
--- a/libcpu/aarch64/common/gicv3.c
+++ b/libcpu/aarch64/common/gicv3.c
@@ -45,9 +45,9 @@ extern rt_uint64_t rt_cpu_mpidr_early[];
struct arm_gic
{
rt_uint64_t offset; /* the first interrupt index in the vector table */
- rt_uint64_t redist_hw_base[RT_CPUS_NR]; /* the pointer of the gic redistributor */
+ rt_uint64_t redist_hw_base[ARM_GIC_CPU_NUM]; /* the pointer of the gic redistributor */
rt_uint64_t dist_hw_base; /* the base address of the gic distributor */
- rt_uint64_t cpu_hw_base[RT_CPUS_NR]; /* the base address of the gic cpu interface */
+ rt_uint64_t cpu_hw_base[ARM_GIC_CPU_NUM]; /* the base address of the gic cpu interface */
};
/* 'ARM_GIC_MAX_NR' is the number of cores */
@@ -737,7 +737,7 @@ int arm_gic_redist_init(rt_uint64_t index, rt_uint64_t redist_base)
if (master_cpu_id < 0)
{
- master_cpu_id = cpu_id;
+ master_cpu_id = 0;
rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, &master_cpu_id, sizeof(master_cpu_id));
}
diff --git a/libcpu/aarch64/common/gicv3.h b/libcpu/aarch64/common/gicv3.h
index cdc7720b37..fbcf3fb4d9 100644
--- a/libcpu/aarch64/common/gicv3.h
+++ b/libcpu/aarch64/common/gicv3.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -18,6 +18,11 @@
#if defined(BSP_USING_GIC) && defined(BSP_USING_GICV3)
+
+#ifndef ARM_GIC_CPU_NUM
+#define ARM_GIC_CPU_NUM RT_CPUS_NR
+#endif
+
#define GICV3_ROUTED_TO_ALL 1UL
#define GICV3_ROUTED_TO_SPEC 0UL
diff --git a/libcpu/aarch64/common/interrupt.c b/libcpu/aarch64/common/interrupt.c
index e30223a696..dc142dd9e8 100644
--- a/libcpu/aarch64/common/interrupt.c
+++ b/libcpu/aarch64/common/interrupt.c
@@ -109,11 +109,11 @@ void rt_hw_interrupt_init(void)
/* initialize ARM GIC */
#ifdef RT_USING_SMART
- gic_dist_base = (rt_uint64_t)rt_ioremap((void*)platform_get_gic_dist_base(), 0x2000);
+ gic_dist_base = (rt_uint64_t)rt_ioremap((void*)platform_get_gic_dist_base(), 0x40000);
gic_cpu_base = (rt_uint64_t)rt_ioremap((void*)platform_get_gic_cpu_base(), 0x1000);
#ifdef BSP_USING_GICV3
gic_rdist_base = (rt_uint64_t)rt_ioremap((void*)platform_get_gic_redist_base(),
- RT_CPUS_NR * (2 << 16));
+ ARM_GIC_CPU_NUM * (2 << 16));
#endif
#else
gic_dist_base = platform_get_gic_dist_base();
diff --git a/libcpu/aarch64/cortex-a/entry_point.S b/libcpu/aarch64/cortex-a/entry_point.S
index c1f14c28b0..112987c88d 100644
--- a/libcpu/aarch64/cortex-a/entry_point.S
+++ b/libcpu/aarch64/cortex-a/entry_point.S
@@ -120,7 +120,7 @@ __start:
adr x1, __start /* install early page table */
ldr x0, =~0x1fffff
and x0, x1, x0
- add x1, x0, #0x1000
+ add x1, x0, #0x1000
msr ttbr0_el1, x0
msr ttbr1_el1, x1
@@ -130,7 +130,10 @@ __start:
ldr x2, =__start
GET_PHY x3, __start
sub x3, x3, x2
+#else
+ mov x3,0
#endif
+
ldr x2, =0x40000000 /* map 1G memory for kernel space */
bl rt_hw_mem_setup_early
diff --git a/libcpu/arm/cortex-a/cpuport.c b/libcpu/arm/cortex-a/cpuport.c
index e3ce568243..ec523f2aa7 100644
--- a/libcpu/arm/cortex-a/cpuport.c
+++ b/libcpu/arm/cortex-a/cpuport.c
@@ -13,7 +13,7 @@
#include <rtthread.h>
#include <board.h>
-int rt_hw_cpu_id(void)
+rt_weak int rt_hw_cpu_id(void)
{
int cpu_id;
__asm__ volatile (
diff --git a/libcpu/arm/cortex-a/interrupt.c b/libcpu/arm/cortex-a/interrupt.c
index bfb3b27170..6fd74aaf76 100644
--- a/libcpu/arm/cortex-a/interrupt.c
+++ b/libcpu/arm/cortex-a/interrupt.c
@@ -100,8 +100,7 @@ void rt_hw_interrupt_init(void)
/* initialize ARM GIC */
#ifdef RT_USING_SMART
- gic_dist_base = (uint32_t)rt_ioremap((void*)platform_get_gic_dist_base(), 0x2000);
- gic_cpu_base = (uint32_t)rt_ioremap((void*)platform_get_gic_cpu_base(), 0x1000);
+ gic_dist_base = (uint32_t)rt_ioremap((void*)platform_get_gic_dist_base(), 0x10000);
#else
gic_dist_base = platform_get_gic_dist_base();
#endif
diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S
index 658ff5a649..1283686439 100644
--- a/libcpu/arm/cortex-a/start_gcc.S
+++ b/libcpu/arm/cortex-a/start_gcc.S
@@ -208,13 +208,22 @@ bss_loop:
_rtthread_startup:
.word rtthread_startup
+.weak rt_asm_cpu_id
+rt_asm_cpu_id:
+ mov r9, lr
+ mrc p15, 0, r0, c0, c0, 5
+ and r0, r0, #0xf
+ mov lr, r9
+
stack_setup:
#ifdef RT_USING_SMP
/* cpu id */
- mrc p15, 0, r0, c0, c0, 5
- and r0, r0, #0xf
+ mov r10, lr
+ bl rt_asm_cpu_id
+ mov lr, r10
add r0, r0, #1
+
#else
mov r0, #1
#endif
@@ -300,6 +309,50 @@ _halt:
wfe
b _halt
+#ifdef RT_USING_SMP
+
+.global rt_secondary_cpu_entry
+rt_secondary_cpu_entry:
+#ifdef RT_USING_SMART
+ ldr r0, =_reset
+ adr r5, _reset
+ sub r5, r5, r0
+
+ ldr lr, =after_enable_mmu_n
+ ldr r0, =init_mtbl
+ add r0, r5
+ b enable_mmu
+
+after_enable_mmu_n:
+ ldr r0, =MMUTable
+ add r0, r5
+ bl rt_hw_mmu_switch
+#endif
+
+#ifdef RT_USING_FPU
+ mov r4, #0xfffffff
+ mcr p15, 0, r4, c1, c0, 2
+#endif
+
+ mrc p15, 0, r1, c1, c0, 1
+ mov r0, #(1<<6)
+ orr r1, r0
+ mcr p15, 0, r1, c1, c0, 1 /* enable smp */
+
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, #(1<<13)
+ mcr p15, 0, r0, c1, c0, 0
+
+ bl stack_setup
+
+ /* initialize the mmu table and enable mmu */
+#ifndef RT_USING_SMART
+ bl rt_hw_mmu_init
+#endif
+
+ b rt_hw_secondary_cpu_bsp_start
+#endif
+
/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */
.section .text.isr, "ax"
.align 5
@@ -616,50 +669,6 @@ rt_hw_clz:
clz r0, r0
bx lr
-#ifdef RT_USING_SMP
-
-.global rt_secondary_cpu_entry
-rt_secondary_cpu_entry:
-#ifdef RT_USING_SMART
- ldr r0, =_reset
- adr r5, _reset
- sub r5, r5, r0
-
- ldr lr, =after_enable_mmu_n
- ldr r0, =init_mtbl
- add r0, r5
- b enable_mmu
-
-after_enable_mmu_n:
- ldr r0, =MMUTable
- add r0, r5
- bl rt_hw_mmu_switch
-#endif
-
-#ifdef RT_USING_FPU
- mov r4, #0xfffffff
- mcr p15, 0, r4, c1, c0, 2
-#endif
-
- mrc p15, 0, r1, c1, c0, 1
- mov r0, #(1<<6)
- orr r1, r0
- mcr p15, 0, r1, c1, c0, 1 /* enable smp */
-
- mrc p15, 0, r0, c1, c0, 0
- bic r0, #(1<<13)
- mcr p15, 0, r0, c1, c0, 0
-
- bl stack_setup
-
- /* initialize the mmu table and enable mmu */
-#ifndef RT_USING_SMART
- bl rt_hw_mmu_init
-#endif
-
- b rt_hw_secondary_cpu_bsp_start
-#endif
-
#ifndef RT_CPUS_NR
#define RT_CPUS_NR 1
#endif
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-30 12:05:45 +0000