4 files changed, 8 insertions, 1 deletions
diff --git a/libcpu/risc-v/ch32/context_gcc.S b/libcpu/risc-v/ch32/context_gcc.S
index 3d6af17934..5e6567a79f 100644
--- a/libcpu/risc-v/ch32/context_gcc.S
+++ b/libcpu/risc-v/ch32/context_gcc.S
@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2021-09-09     WCH        the first version
+ * 2022-12-27     WangShun   Merge WCH series mcu port files
  */
 
 #include "cpuport.h"
diff --git a/libcpu/risc-v/ch32/cpuport.c b/libcpu/risc-v/ch32/cpuport.c
index e42bab949e..c1c609c58d 100644
--- a/libcpu/risc-v/ch32/cpuport.c
+++ b/libcpu/risc-v/ch32/cpuport.c
@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2021-09-09     WCH        the first version
+ * 2022-12-27     WangShun   Merge WCH series mcu port files
  */
 
 #include <rthw.h>
diff --git a/libcpu/risc-v/ch32/interrupt_gcc.S b/libcpu/risc-v/ch32/interrupt_gcc.S
index 96c61ddd33..4d16a5b054 100644
--- a/libcpu/risc-v/ch32/interrupt_gcc.S
+++ b/libcpu/risc-v/ch32/interrupt_gcc.S
@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2021-09-09     WCH        the first version
+ * 2022-12-27     WangShun   Merge WCH series mcu port files
  */
  
 #include "cpuport.h"
diff --git a/libcpu/risc-v/common/context_gcc.S b/libcpu/risc-v/common/context_gcc.S
index e458268e11..dbb5f8f4b5 100644
--- a/libcpu/risc-v/common/context_gcc.S
+++ b/libcpu/risc-v/common/context_gcc.S
@@ -8,6 +8,7 @@
  * 2018/10/28     Bernard      The unify RISC-V porting implementation
  * 2018/12/27     Jesven       Add SMP support
  * 2020/11/20     BalanceTWK   Add FPU support
+ * 2022/12/28     WangShun     Add macro to distinguish whether FPU is supported
  */
 
 #define __ASSEMBLY__
@@ -212,8 +213,11 @@ rt_hw_context_switch_exit:
     csrw mepc, a0
 
     LOAD x1,   1 * REGBYTES(sp)
-
+    #ifdef ARCH_RISCV_FPU
     li    t0, 0x00007800
+    #else
+    li    t0, 0x00001800
+    #endif
     csrw  mstatus, t0
     LOAD a0,   2 * REGBYTES(sp)
     csrs mstatus, a0