summaryrefslogtreecommitdiff
path: root/libcpu
diff options
context:
space:
mode:
Diffstat (limited to 'libcpu')
-rw-r--r--libcpu/risc-v/SConscript4
-rw-r--r--libcpu/risc-v/ch32/SConscript (renamed from libcpu/risc-v/ch32v3/SConscript)0
-rw-r--r--libcpu/risc-v/ch32/context_gcc.S (renamed from libcpu/risc-v/ch32v3/context_gcc.S)4
-rw-r--r--libcpu/risc-v/ch32/cpuport.c (renamed from libcpu/risc-v/ch32v3/cpuport.c)31
-rw-r--r--libcpu/risc-v/ch32/cpuport.h (renamed from libcpu/risc-v/ch32v1/cpuport.h)0
-rw-r--r--libcpu/risc-v/ch32/interrupt_gcc.S (renamed from libcpu/risc-v/ch32v3/interrupt_gcc.S)8
-rw-r--r--libcpu/risc-v/ch32v1/SConscript14
-rw-r--r--libcpu/risc-v/ch32v1/context_gcc.S211
-rw-r--r--libcpu/risc-v/ch32v1/cpuport.c199
-rw-r--r--libcpu/risc-v/ch32v1/interrupt_gcc.S191
-rw-r--r--libcpu/risc-v/ch32v3/cpuport.h44
11 files changed, 41 insertions, 665 deletions
diff --git a/libcpu/risc-v/SConscript b/libcpu/risc-v/SConscript
index 6639ea7a22..b18bccbe5d 100644
--- a/libcpu/risc-v/SConscript
+++ b/libcpu/risc-v/SConscript
@@ -18,9 +18,7 @@ elif rtconfig.CPU == "virt64" :
group = group
elif rtconfig.CPU == "c906" :
group = group
-elif rtconfig.CPU == "ch32v1" :
- group = group
-elif rtconfig.CPU == "ch32v3" :
+elif rtconfig.CPU == "ch32" :
group = group
elif rtconfig.CPU == "hpmicro":
group = group
diff --git a/libcpu/risc-v/ch32v3/SConscript b/libcpu/risc-v/ch32/SConscript
index 383d80e528..383d80e528 100644
--- a/libcpu/risc-v/ch32v3/SConscript
+++ b/libcpu/risc-v/ch32/SConscript
diff --git a/libcpu/risc-v/ch32v3/context_gcc.S b/libcpu/risc-v/ch32/context_gcc.S
index f8622f0700..3d6af17934 100644
--- a/libcpu/risc-v/ch32v3/context_gcc.S
+++ b/libcpu/risc-v/ch32/context_gcc.S
@@ -137,7 +137,11 @@ rt_hw_context_switch_exit:
LOAD x1, 1 * REGBYTES(sp)
/* keep machine mode */
+ #if defined (SOC_RISCV_SERIES_CH32V3)
li a0, 0x7800
+ #else
+ li a0, 0x1800
+ #endif
csrs mstatus, a0
/* resume MPIE */
LOAD a0, 2*REGBYTES(sp)
diff --git a/libcpu/risc-v/ch32v3/cpuport.c b/libcpu/risc-v/ch32/cpuport.c
index b36e731554..e42bab949e 100644
--- a/libcpu/risc-v/ch32v3/cpuport.c
+++ b/libcpu/risc-v/ch32/cpuport.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -10,7 +10,16 @@
#include <rthw.h>
#include <rtthread.h>
+#if defined (SOC_RISCV_SERIES_CH32V1)
+#include "ch32v10x.h"
+#elif defined (SOC_RISCV_SERIES_CH32V2)
+#include "ch32v20x.h"
+#elif defined (SOC_RISCV_SERIES_CH32V3)
#include "ch32v30x.h"
+#else
+#error "CH32 architecture doesn't support!"
+#endif
+
#include "cpuport.h"
#ifndef RT_USING_SMP
@@ -124,9 +133,13 @@ rt_uint8_t *rt_hw_stack_init(void *tentry,
frame->ra = (rt_ubase_t)texit;
frame->a0 = (rt_ubase_t)parameter;
frame->epc = (rt_ubase_t)tentry;
-
+ #if defined (SOC_RISCV_SERIES_CH32V3)
/* force to machine mode(MPP=11) and set MPIE to 1 and FS=11 */
frame->mstatus = 0x00007880;
+ #else
+ /* force to machine mode(MPP=11) and set MPIE to 1 */
+ frame->mstatus = 0x00001880;
+ #endif
return stk;
}
@@ -135,7 +148,12 @@ rt_uint8_t *rt_hw_stack_init(void *tentry,
*/
void sw_setpend(void)
{
+ /*CH32V103 does not support systick software interrupt*/
+ #if defined (SOC_RISCV_SERIES_CH32V1)
+ NVIC_SetPendingIRQ(Software_IRQn);
+ #else
SysTick->CTLR |= (1<<31);
+ #endif
}
/*
@@ -143,7 +161,12 @@ void sw_setpend(void)
*/
void sw_clearpend(void)
{
+ /*CH32V103 does not support systick software interrupt*/
+ #if defined (SOC_RISCV_SERIES_CH32V1)
+ NVIC_ClearPendingIRQ(Software_IRQn);
+ #else
SysTick->CTLR &= ~(1<<31);
+ #endif
}
/*
@@ -152,7 +175,11 @@ void sw_clearpend(void)
rt_base_t rt_hw_interrupt_disable(void)
{
rt_base_t value=0;
+ #if defined (SOC_RISCV_SERIES_CH32V3)
asm("csrrw %0, mstatus, %1":"=r"(value):"r"(0x7800));
+ #else
+ asm("csrrw %0, mstatus, %1":"=r"(value):"r"(0x1800));
+ #endif
return value;
}
diff --git a/libcpu/risc-v/ch32v1/cpuport.h b/libcpu/risc-v/ch32/cpuport.h
index c37f3bbb5b..c37f3bbb5b 100644
--- a/libcpu/risc-v/ch32v1/cpuport.h
+++ b/libcpu/risc-v/ch32/cpuport.h
diff --git a/libcpu/risc-v/ch32v3/interrupt_gcc.S b/libcpu/risc-v/ch32/interrupt_gcc.S
index ce5cdb210d..96c61ddd33 100644
--- a/libcpu/risc-v/ch32v3/interrupt_gcc.S
+++ b/libcpu/risc-v/ch32/interrupt_gcc.S
@@ -58,8 +58,10 @@ SW_handler:
STORE t0, 2 * REGBYTES(sp)
/* Temporarily disable HPE */
+ #if defined (SOC_RISCV_SERIES_CH32V3)
li t0, 0x20
csrs 0x804, t0
+ #endif
STORE x1, 1 * REGBYTES(sp)
STORE x4, 4 * REGBYTES(sp)
@@ -120,9 +122,13 @@ SW_handler:
csrw mepc, a0
1: LOAD x1, 1 * REGBYTES(sp)
-
+ #if defined (SOC_RISCV_SERIES_CH32V3)
li t0,0x7800
csrs mstatus, t0
+ #else
+ li t0,0x1800
+ csrs mstatus, t0
+ #endif
LOAD t0, 2*REGBYTES(sp)
csrs mstatus, t0
diff --git a/libcpu/risc-v/ch32v1/SConscript b/libcpu/risc-v/ch32v1/SConscript
deleted file mode 100644
index 20f325b692..0000000000
--- a/libcpu/risc-v/ch32v1/SConscript
+++ /dev/null
@@ -1,14 +0,0 @@
-# RT-Thread building script for component
-
-from building import *
-
-Import('rtconfig')
-
-cwd = GetCurrentDir()
-src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
-CPPPATH = [cwd]
-ASFLAGS = ''
-
-group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
-
-Return('group')
diff --git a/libcpu/risc-v/ch32v1/context_gcc.S b/libcpu/risc-v/ch32v1/context_gcc.S
deleted file mode 100644
index 5cf2d39cf8..0000000000
--- a/libcpu/risc-v/ch32v1/context_gcc.S
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2021-09-09 WCH the first version
- */
-
-#include "cpuport.h"
-
-/*
- * #ifdef RT_USING_SMP
- * void rt_hw_context_switch_to(rt_ubase_t to, stuct rt_thread *to_thread);
- * #else
- * void rt_hw_context_switch_to(rt_ubase_t to);
- * #endif
- * a0 --> to
- * a1 --> to_thread
- */
- .globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
- /* first save interrupt stack */
- la t0, _eusrstack
- addi t0, t0, -512
- csrw mscratch,t0
-
- LOAD sp, (a0)
- LOAD a0, 2 * REGBYTES(sp)
- csrw mstatus, a0
- j rt_hw_context_switch_exit
-
-
-/*
- * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);
- * a0 --> from
- * a1 --> to
- */
- .globl rt_hw_context_switch
-rt_hw_context_switch:
- /* switch in thread */
-#ifdef ARCH_RISCV_FPU
- addi sp, sp, -32*FREGBYTES
-
- FSTORE f0, 0 * FREGBYTES(sp)
- FSTORE f1, 1 * FREGBYTES(sp)
- FSTORE f2, 2 * FREGBYTES(sp)
- FSTORE f3, 3 * FREGBYTES(sp)
- FSTORE f4, 4 * FREGBYTES(sp)
- FSTORE f5, 5 * FREGBYTES(sp)
- FSTORE f6, 6 * FREGBYTES(sp)
- FSTORE f7, 7 * FREGBYTES(sp)
- FSTORE f8, 8 * FREGBYTES(sp)
- FSTORE f9, 9 * FREGBYTES(sp)
- FSTORE f10, 10 * FREGBYTES(sp)
- FSTORE f11, 11 * FREGBYTES(sp)
- FSTORE f12, 12 * FREGBYTES(sp)
- FSTORE f13, 13 * FREGBYTES(sp)
- FSTORE f14, 14 * FREGBYTES(sp)
- FSTORE f15, 15 * FREGBYTES(sp)
- FSTORE f16, 16 * FREGBYTES(sp)
- FSTORE f17, 17 * FREGBYTES(sp)
- FSTORE f18, 18 * FREGBYTES(sp)
- FSTORE f19, 19 * FREGBYTES(sp)
- FSTORE f20, 20 * FREGBYTES(sp)
- FSTORE f21, 21 * FREGBYTES(sp)
- FSTORE f22, 22 * FREGBYTES(sp)
- FSTORE f23, 23 * FREGBYTES(sp)
- FSTORE f24, 24 * FREGBYTES(sp)
- FSTORE f25, 25 * FREGBYTES(sp)
- FSTORE f26, 26 * FREGBYTES(sp)
- FSTORE f27, 27 * FREGBYTES(sp)
- FSTORE f28, 28 * FREGBYTES(sp)
- FSTORE f29, 29 * FREGBYTES(sp)
- FSTORE f30, 30 * FREGBYTES(sp)
- FSTORE f31, 31 * FREGBYTES(sp)
-#endif
-
- addi sp, sp, -32 * REGBYTES
- /* save from sp */
- STORE sp, 0(a0)
- /* save ra to epc */
- STORE x1, 0 * REGBYTES(sp)
- STORE x1, 1 * REGBYTES(sp)
- STORE x5, 5 * REGBYTES(sp)
-
- csrr t0, mstatus
- andi t0, t0, 8
- /* if MIE be enabled,set MPIE */
- beqz t0, 1f
- li t0, 0x80
-
-1: STORE t0, 2 * REGBYTES(sp)
- STORE x4, 4 * REGBYTES(sp)
-
- STORE x6, 6 * REGBYTES(sp)
- STORE x7, 7 * REGBYTES(sp)
- STORE x8, 8 * REGBYTES(sp)
- STORE x9, 9 * REGBYTES(sp)
- STORE x10, 10 * REGBYTES(sp)
- STORE x11, 11 * REGBYTES(sp)
- STORE x12, 12 * REGBYTES(sp)
- STORE x13, 13 * REGBYTES(sp)
- STORE x14, 14 * REGBYTES(sp)
- STORE x15, 15 * REGBYTES(sp)
- STORE x16, 16 * REGBYTES(sp)
- STORE x17, 17 * REGBYTES(sp)
- STORE x18, 18 * REGBYTES(sp)
- STORE x19, 19 * REGBYTES(sp)
- STORE x20, 20 * REGBYTES(sp)
- STORE x21, 21 * REGBYTES(sp)
- STORE x22, 22 * REGBYTES(sp)
- STORE x23, 23 * REGBYTES(sp)
- STORE x24, 24 * REGBYTES(sp)
- STORE x25, 25 * REGBYTES(sp)
- STORE x26, 26 * REGBYTES(sp)
- STORE x27, 27 * REGBYTES(sp)
- STORE x28, 28 * REGBYTES(sp)
- STORE x29, 29 * REGBYTES(sp)
- STORE x30, 30 * REGBYTES(sp)
- STORE x31, 31 * REGBYTES(sp)
-
- /* get "to" thread sp */
- LOAD sp, 0(a1)
- j rt_hw_context_switch_exit
-
-
-.global rt_hw_context_switch_exit
-rt_hw_context_switch_exit:
- /* resw ra to mepc */
- LOAD a0, 0 * REGBYTES(sp)
- csrw mepc, a0
-
- LOAD x1, 1 * REGBYTES(sp)
- /* keep machine mode */
- li a0, 0x1800
- csrs mstatus, a0
- /* resume MPIE */
- LOAD a0, 2*REGBYTES(sp)
- csrs mstatus, a0
-
- LOAD x4, 4 * REGBYTES(sp)
- LOAD x5, 5 * REGBYTES(sp)
- LOAD x6, 6 * REGBYTES(sp)
- LOAD x7, 7 * REGBYTES(sp)
- LOAD x8, 8 * REGBYTES(sp)
- LOAD x9, 9 * REGBYTES(sp)
- LOAD x10, 10 * REGBYTES(sp)
- LOAD x11, 11 * REGBYTES(sp)
- LOAD x12, 12 * REGBYTES(sp)
- LOAD x13, 13 * REGBYTES(sp)
- LOAD x14, 14 * REGBYTES(sp)
- LOAD x15, 15 * REGBYTES(sp)
- LOAD x16, 16 * REGBYTES(sp)
- LOAD x17, 17 * REGBYTES(sp)
- LOAD x18, 18 * REGBYTES(sp)
- LOAD x19, 19 * REGBYTES(sp)
- LOAD x20, 20 * REGBYTES(sp)
- LOAD x21, 21 * REGBYTES(sp)
- LOAD x22, 22 * REGBYTES(sp)
- LOAD x23, 23 * REGBYTES(sp)
- LOAD x24, 24 * REGBYTES(sp)
- LOAD x25, 25 * REGBYTES(sp)
- LOAD x26, 26 * REGBYTES(sp)
- LOAD x27, 27 * REGBYTES(sp)
- LOAD x28, 28 * REGBYTES(sp)
- LOAD x29, 29 * REGBYTES(sp)
- LOAD x30, 30 * REGBYTES(sp)
- LOAD x31, 31 * REGBYTES(sp)
- addi sp, sp, 32 * REGBYTES
-
- /* load float reg */
-#ifdef ARCH_RISCV_FPU
-
- FLOAD f0, 0 * FREGBYTES(sp)
- FLOAD f1, 1 * FREGBYTES(sp)
- FLOAD f2, 2 * FREGBYTES(sp)
- FLOAD f3, 3 * FREGBYTES(sp)
- FLOAD f4, 4 * FREGBYTES(sp)
- FLOAD f5, 5 * FREGBYTES(sp)
- FLOAD f6, 6 * FREGBYTES(sp)
- FLOAD f7, 7 * FREGBYTES(sp)
- FLOAD f8, 8 * FREGBYTES(sp)
- FLOAD f9, 9 * FREGBYTES(sp)
- FLOAD f10, 10 * FREGBYTES(sp)
- FLOAD f11, 11 * FREGBYTES(sp)
- FLOAD f12, 12 * FREGBYTES(sp)
- FLOAD f13, 13 * FREGBYTES(sp)
- FLOAD f14, 14 * FREGBYTES(sp)
- FLOAD f15, 15 * FREGBYTES(sp)
- FLOAD f16, 16 * FREGBYTES(sp)
- FLOAD f17, 17 * FREGBYTES(sp)
- FLOAD f18, 18 * FREGBYTES(sp)
- FLOAD f19, 19 * FREGBYTES(sp)
- FLOAD f20, 20 * FREGBYTES(sp)
- FLOAD f21, 21 * FREGBYTES(sp)
- FLOAD f22, 22 * FREGBYTES(sp)
- FLOAD f23, 23 * FREGBYTES(sp)
- FLOAD f24, 24 * FREGBYTES(sp)
- FLOAD f25, 25 * FREGBYTES(sp)
- FLOAD f26, 26 * FREGBYTES(sp)
- FLOAD f27, 27 * FREGBYTES(sp)
- FLOAD f28, 28 * FREGBYTES(sp)
- FLOAD f29, 29 * FREGBYTES(sp)
- FLOAD f30, 30 * FREGBYTES(sp)
- FLOAD f31, 31 * FREGBYTES(sp)
- addi sp, sp, 32 * FREGBYTES
-#endif
-
- mret
diff --git a/libcpu/risc-v/ch32v1/cpuport.c b/libcpu/risc-v/ch32v1/cpuport.c
deleted file mode 100644
index 14bf15ccc2..0000000000
--- a/libcpu/risc-v/ch32v1/cpuport.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2021-09-09 WCH the first version
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-#include "ch32v10x.h"
-#include "cpuport.h"
-
-#ifndef RT_USING_SMP
-volatile rt_ubase_t rt_interrupt_from_thread = 0;
-volatile rt_ubase_t rt_interrupt_to_thread = 0;
-volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0;
-#endif
-
-struct rt_hw_stack_frame
-{
- rt_ubase_t epc; /* epc - epc - program counter */
- rt_ubase_t ra; /* x1 - ra - return address for jumps */
- rt_ubase_t mstatus; /* - machine status register */
- rt_ubase_t gp; /* x3 - gp - global pointer */
- rt_ubase_t tp; /* x4 - tp - thread pointer */
- rt_ubase_t t0; /* x5 - t0 - temporary register 0 */
- rt_ubase_t t1; /* x6 - t1 - temporary register 1 */
- rt_ubase_t t2; /* x7 - t2 - temporary register 2 */
- rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */
- rt_ubase_t s1; /* x9 - s1 - saved register 1 */
- rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */
- rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */
- rt_ubase_t a2; /* x12 - a2 - function argument 2 */
- rt_ubase_t a3; /* x13 - a3 - function argument 3 */
- rt_ubase_t a4; /* x14 - a4 - function argument 4 */
- rt_ubase_t a5; /* x15 - a5 - function argument 5 */
- rt_ubase_t a6; /* x16 - a6 - function argument 6 */
- rt_ubase_t a7; /* x17 - s7 - function argument 7 */
- rt_ubase_t s2; /* x18 - s2 - saved register 2 */
- rt_ubase_t s3; /* x19 - s3 - saved register 3 */
- rt_ubase_t s4; /* x20 - s4 - saved register 4 */
- rt_ubase_t s5; /* x21 - s5 - saved register 5 */
- rt_ubase_t s6; /* x22 - s6 - saved register 6 */
- rt_ubase_t s7; /* x23 - s7 - saved register 7 */
- rt_ubase_t s8; /* x24 - s8 - saved register 8 */
- rt_ubase_t s9; /* x25 - s9 - saved register 9 */
- rt_ubase_t s10; /* x26 - s10 - saved register 10 */
- rt_ubase_t s11; /* x27 - s11 - saved register 11 */
- rt_ubase_t t3; /* x28 - t3 - temporary register 3 */
- rt_ubase_t t4; /* x29 - t4 - temporary register 4 */
- rt_ubase_t t5; /* x30 - t5 - temporary register 5 */
- rt_ubase_t t6; /* x31 - t6 - temporary register 6 */
-
-/* float register */
-#ifdef ARCH_RISCV_FPU
- rv_floatreg_t f0; /* f0 */
- rv_floatreg_t f1; /* f1 */
- rv_floatreg_t f2; /* f2 */
- rv_floatreg_t f3; /* f3 */
- rv_floatreg_t f4; /* f4 */
- rv_floatreg_t f5; /* f5 */
- rv_floatreg_t f6; /* f6 */
- rv_floatreg_t f7; /* f7 */
- rv_floatreg_t f8; /* f8 */
- rv_floatreg_t f9; /* f9 */
- rv_floatreg_t f10; /* f10 */
- rv_floatreg_t f11; /* f11 */
- rv_floatreg_t f12; /* f12 */
- rv_floatreg_t f13; /* f13 */
- rv_floatreg_t f14; /* f14 */
- rv_floatreg_t f15; /* f15 */
- rv_floatreg_t f16; /* f16 */
- rv_floatreg_t f17; /* f17 */
- rv_floatreg_t f18; /* f18 */
- rv_floatreg_t f19; /* f19 */
- rv_floatreg_t f20; /* f20 */
- rv_floatreg_t f21; /* f21 */
- rv_floatreg_t f22; /* f22 */
- rv_floatreg_t f23; /* f23 */
- rv_floatreg_t f24; /* f24 */
- rv_floatreg_t f25; /* f25 */
- rv_floatreg_t f26; /* f26 */
- rv_floatreg_t f27; /* f27 */
- rv_floatreg_t f28; /* f28 */
- rv_floatreg_t f29; /* f29 */
- rv_floatreg_t f30; /* f30 */
- rv_floatreg_t f31; /* f31 */
-#endif
-};
-
-/*
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry,
- void *parameter,
- rt_uint8_t *stack_addr,
- void *texit)
-{
- struct rt_hw_stack_frame *frame;
- rt_uint8_t *stk;
- int i;
-
- stk = stack_addr + sizeof(rt_ubase_t);
- stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES);
- stk -= sizeof(struct rt_hw_stack_frame);
-
- frame = (struct rt_hw_stack_frame *)stk;
-
- for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++)
- {
- ((rt_ubase_t *)frame)[i] = 0xdeadbeef;
- }
-
- frame->ra = (rt_ubase_t)texit;
- frame->a0 = (rt_ubase_t)parameter;
- frame->epc = (rt_ubase_t)tentry;
-
- /* force to machine mode(MPP=11) and set MPIE to 1 and FS=11 */
- frame->mstatus = 0x00001880;
- return stk;
-}
-
-/*
- * trigger soft interrupt
- */
-void sw_setpend(void)
-{
- NVIC_SetPendingIRQ(Software_IRQn);
-}
-
-/*
- * clear soft interrupt
- */
-void sw_clearpend(void)
-{
- NVIC_ClearPendingIRQ(Software_IRQn);
-}
-
-/*
- * disable interrupt and save mstatus
- */
-rt_base_t rt_hw_interrupt_disable(void)
-{
- register rt_base_t value = 0;
- asm("csrrw %0, mstatus, %1":"=r"(value):"r"(0x1800));
- return value;
-}
-
-/*
- * enable interrupt and resume mstatus
- */
-void rt_hw_interrupt_enable(rt_base_t level)
-{
- asm("csrw mstatus, %0": :"r"(level));
-}
-
-
-/*
- * #ifdef RT_USING_SMP
- * void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
- * #else
- * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
- * #endif
- */
-void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread, rt_thread_t to_thread)
-{
- if (rt_thread_switch_interrupt_flag == 0)
- rt_interrupt_from_thread = from;
-
- rt_interrupt_to_thread = to;
- rt_thread_switch_interrupt_flag = 1;
- /* switch just in sw_handler */
- sw_setpend();
-}
-
-
-
-/* shutdown CPU */
-void rt_hw_cpu_shutdown(void)
-{
- rt_base_t level;
- rt_kprintf("shutdown...\n");
-
- level = rt_hw_interrupt_disable();
- while (level)
- {
- RT_ASSERT(0);
- }
-}
diff --git a/libcpu/risc-v/ch32v1/interrupt_gcc.S b/libcpu/risc-v/ch32v1/interrupt_gcc.S
deleted file mode 100644
index 56410c37d9..0000000000
--- a/libcpu/risc-v/ch32v1/interrupt_gcc.S
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2021-09-09 WCH the first version
- */
-
-#include "cpuport.h"
-
-.global SW_handler
-.align 2
-SW_handler:
- /* save all from thread context */
-#ifdef ARCH_RISCV_FPU
- addi sp, sp, -32 * FREGBYTES
- FSTORE f0, 0 * FREGBYTES(sp)
- FSTORE f1, 1 * FREGBYTES(sp)
- FSTORE f2, 2 * FREGBYTES(sp)
- FSTORE f3, 3 * FREGBYTES(sp)
- FSTORE f4, 4 * FREGBYTES(sp)
- FSTORE f5, 5 * FREGBYTES(sp)
- FSTORE f6, 6 * FREGBYTES(sp)
- FSTORE f7, 7 * FREGBYTES(sp)
- FSTORE f8, 8 * FREGBYTES(sp)
- FSTORE f9, 9 * FREGBYTES(sp)
- FSTORE f10, 10 * FREGBYTES(sp)
- FSTORE f11, 11 * FREGBYTES(sp)
- FSTORE f12, 12 * FREGBYTES(sp)
- FSTORE f13, 13 * FREGBYTES(sp)
- FSTORE f14, 14 * FREGBYTES(sp)
- FSTORE f15, 15 * FREGBYTES(sp)
- FSTORE f16, 16 * FREGBYTES(sp)
- FSTORE f17, 17 * FREGBYTES(sp)
- FSTORE f18, 18 * FREGBYTES(sp)
- FSTORE f19, 19 * FREGBYTES(sp)
- FSTORE f20, 20 * FREGBYTES(sp)
- FSTORE f21, 21 * FREGBYTES(sp)
- FSTORE f22, 22 * FREGBYTES(sp)
- FSTORE f23, 23 * FREGBYTES(sp)
- FSTORE f24, 24 * FREGBYTES(sp)
- FSTORE f25, 25 * FREGBYTES(sp)
- FSTORE f26, 26 * FREGBYTES(sp)
- FSTORE f27, 27 * FREGBYTES(sp)
- FSTORE f28, 28 * FREGBYTES(sp)
- FSTORE f29, 29 * FREGBYTES(sp)
- FSTORE f30, 30 * FREGBYTES(sp)
- FSTORE f31, 31 * FREGBYTES(sp)
-#endif
-
- addi sp, sp, -32 * REGBYTES
- STORE x5, 5 * REGBYTES(sp)
-
- /* saved MPIE */
- li t0, 0x80
- STORE t0, 2 * REGBYTES(sp)
-
- STORE x1, 1 * REGBYTES(sp)
- STORE x4, 4 * REGBYTES(sp)
- STORE x6, 6 * REGBYTES(sp)
- STORE x7, 7 * REGBYTES(sp)
- STORE x8, 8 * REGBYTES(sp)
- STORE x9, 9 * REGBYTES(sp)
- STORE x10, 10 * REGBYTES(sp)
- STORE x11, 11 * REGBYTES(sp)
- STORE x12, 12 * REGBYTES(sp)
- STORE x13, 13 * REGBYTES(sp)
- STORE x14, 14 * REGBYTES(sp)
- STORE x15, 15 * REGBYTES(sp)
- STORE x16, 16 * REGBYTES(sp)
- STORE x17, 17 * REGBYTES(sp)
- STORE x18, 18 * REGBYTES(sp)
- STORE x19, 19 * REGBYTES(sp)
- STORE x20, 20 * REGBYTES(sp)
- STORE x21, 21 * REGBYTES(sp)
- STORE x22, 22 * REGBYTES(sp)
- STORE x23, 23 * REGBYTES(sp)
- STORE x24, 24 * REGBYTES(sp)
- STORE x25, 25 * REGBYTES(sp)
- STORE x26, 26 * REGBYTES(sp)
- STORE x27, 27 * REGBYTES(sp)
- STORE x28, 28 * REGBYTES(sp)
- STORE x29, 29 * REGBYTES(sp)
- STORE x30, 30 * REGBYTES(sp)
- STORE x31, 31 * REGBYTES(sp)
-
- /* switch to interrupt stack */
- csrrw sp,mscratch,sp
- call rt_interrupt_enter
- /* clear interrupt */
- jal sw_clearpend
- call rt_interrupt_leave
- /* switch to from thread stack */
- csrrw sp,mscratch,sp
-
- /* if rt_thread_switch_interrupt_flag=1,then clear it */
- la s0, rt_thread_switch_interrupt_flag
- lw s2, 0(s0)
- beqz s2, 1f
- sw zero, 0(s0)
-#1:
- csrr a0, mepc
- STORE a0, 0 * REGBYTES(sp)
-
- la s0, rt_interrupt_from_thread
- LOAD s1, 0(s0)
- STORE sp, 0(s1)
-
- la s0, rt_interrupt_to_thread
- LOAD s1, 0(s0)
- LOAD sp, 0(s1)
-
- LOAD a0, 0 * REGBYTES(sp)
- csrw mepc, a0
-
-1: LOAD x1, 1 * REGBYTES(sp)
-
- li t0,0x1800
- csrs mstatus, t0
- LOAD t0, 2*REGBYTES(sp)
- csrs mstatus, t0
-
- LOAD x4, 4 * REGBYTES(sp)
- LOAD x5, 5 * REGBYTES(sp)
- LOAD x6, 6 * REGBYTES(sp)
- LOAD x7, 7 * REGBYTES(sp)
- LOAD x8, 8 * REGBYTES(sp)
- LOAD x9, 9 * REGBYTES(sp)
- LOAD x10, 10 * REGBYTES(sp)
- LOAD x11, 11 * REGBYTES(sp)
- LOAD x12, 12 * REGBYTES(sp)
- LOAD x13, 13 * REGBYTES(sp)
- LOAD x14, 14 * REGBYTES(sp)
- LOAD x15, 15 * REGBYTES(sp)
- LOAD x16, 16 * REGBYTES(sp)
- LOAD x17, 17 * REGBYTES(sp)
- LOAD x18, 18 * REGBYTES(sp)
- LOAD x19, 19 * REGBYTES(sp)
- LOAD x20, 20 * REGBYTES(sp)
- LOAD x21, 21 * REGBYTES(sp)
- LOAD x22, 22 * REGBYTES(sp)
- LOAD x23, 23 * REGBYTES(sp)
- LOAD x24, 24 * REGBYTES(sp)
- LOAD x25, 25 * REGBYTES(sp)
- LOAD x26, 26 * REGBYTES(sp)
- LOAD x27, 27 * REGBYTES(sp)
- LOAD x28, 28 * REGBYTES(sp)
- LOAD x29, 29 * REGBYTES(sp)
- LOAD x30, 30 * REGBYTES(sp)
- LOAD x31, 31 * REGBYTES(sp)
- addi sp, sp, 32 * REGBYTES
-
- /* load float reg */
-#ifdef ARCH_RISCV_FPU
- FLOAD f0, 0 * FREGBYTES(sp)
- FLOAD f1, 1 * FREGBYTES(sp)
- FLOAD f2, 2 * FREGBYTES(sp)
- FLOAD f3, 3 * FREGBYTES(sp)
- FLOAD f4, 4 * FREGBYTES(sp)
- FLOAD f5, 5 * FREGBYTES(sp)
- FLOAD f6, 6 * FREGBYTES(sp)
- FLOAD f7, 7 * FREGBYTES(sp)
- FLOAD f8, 8 * FREGBYTES(sp)
- FLOAD f9, 9 * FREGBYTES(sp)
- FLOAD f10, 10 * FREGBYTES(sp)
- FLOAD f11, 11 * FREGBYTES(sp)
- FLOAD f12, 12 * FREGBYTES(sp)
- FLOAD f13, 13 * FREGBYTES(sp)
- FLOAD f14, 14 * FREGBYTES(sp)
- FLOAD f15, 15 * FREGBYTES(sp)
- FLOAD f16, 16 * FREGBYTES(sp)
- FLOAD f17, 17 * FREGBYTES(sp)
- FLOAD f18, 18 * FREGBYTES(sp)
- FLOAD f19, 19 * FREGBYTES(sp)
- FLOAD f20, 20 * FREGBYTES(sp)
- FLOAD f21, 21 * FREGBYTES(sp)
- FLOAD f22, 22 * FREGBYTES(sp)
- FLOAD f23, 23 * FREGBYTES(sp)
- FLOAD f24, 24 * FREGBYTES(sp)
- FLOAD f25, 25 * FREGBYTES(sp)
- FLOAD f26, 26 * FREGBYTES(sp)
- FLOAD f27, 27 * FREGBYTES(sp)
- FLOAD f28, 28 * FREGBYTES(sp)
- FLOAD f29, 29 * FREGBYTES(sp)
- FLOAD f30, 30 * FREGBYTES(sp)
- FLOAD f31, 31 * FREGBYTES(sp)
- addi sp, sp, 32 * FREGBYTES
-#endif
- mret
diff --git a/libcpu/risc-v/ch32v3/cpuport.h b/libcpu/risc-v/ch32v3/cpuport.h
deleted file mode 100644
index 5034b2386c..0000000000
--- a/libcpu/risc-v/ch32v3/cpuport.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date Author Notes
- * 2021-09-09 WCH the first version
- */
-
-#ifndef CPUPORT_H__
-#define CPUPORT_H__
-
-/* bytes of register width */
-//#define ARCH_RISCV_FPU
-#define ARCH_RISCV_FPU_S
-
-#ifdef ARCH_CPU_64BIT
-#define STORE sd
-#define LOAD ld
-#define REGBYTES 8
-#else
-#define STORE sw
-#define LOAD lw
-#define REGBYTES 4
-#endif
-
-/* FPU */
-#ifdef ARCH_RISCV_FPU
-#ifdef ARCH_RISCV_FPU_D
-#define FSTORE fsd
-#define FLOAD fld
-#define FREGBYTES 8
-#define rv_floatreg_t rt_int64_t
-#endif
-#ifdef ARCH_RISCV_FPU_S
-#define FSTORE fsw
-#define FLOAD flw
-#define FREGBYTES 4
-#define rv_floatreg_t rt_int32_t
-#endif
-#endif
-
-#endif
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-30 15:10:35 +0000