diff options
Diffstat (limited to 'libcpu')
307 files changed, 16436 insertions, 16074 deletions
diff --git a/libcpu/Kconfig b/libcpu/Kconfig index 239fa58346..ae2767dec9 100644 --- a/libcpu/Kconfig +++ b/libcpu/Kconfig @@ -4,6 +4,10 @@ config ARCH_CPU_64BIT config ARCH_ARM bool +config RT_USING_CPU_FFS + bool + default n + config ARCH_ARM_CORTEX_M bool select ARCH_ARM @@ -18,6 +22,7 @@ config ARCH_ARM_CORTEX_M0 config ARCH_ARM_CORTEX_M3 bool select ARCH_ARM_CORTEX_M + select RT_USING_CPU_FFS config ARCH_ARM_MPU bool @@ -26,10 +31,12 @@ config ARCH_ARM_MPU config ARCH_ARM_CORTEX_M4 bool select ARCH_ARM_CORTEX_M + select RT_USING_CPU_FFS config ARCH_ARM_CORTEX_M7 bool select ARCH_ARM_CORTEX_M + select RT_USING_CPU_FFS config ARCH_ARM_CORTEX_R bool @@ -67,9 +74,19 @@ config ARCH_ARM_CORTEX_A9 bool select ARCH_ARM_CORTEX_A +config ARCH_ARMV8 + bool + config ARCH_MIPS bool +config ARCH_MIPS64 + bool + select ARCH_CPU_64BIT + +config ARCH_CPU_64BIT + bool + config ARCH_MIPS_XBURST bool select ARCH_MIPS diff --git a/libcpu/SConscript b/libcpu/SConscript index 568da67cc9..6092707e6d 100644 --- a/libcpu/SConscript +++ b/libcpu/SConscript @@ -1,38 +1,15 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -arch = rtconfig.ARCH -comm = rtconfig.ARCH + '/common' -path = rtconfig.ARCH + '/' + rtconfig.CPU -src = [] -ASFLAGS = '' - -# The set of source files associated with this SConscript file. -if rtconfig.PLATFORM == 'armcc': - src += Glob(path + '/*.c') + Glob(path + '/*_rvds.S') - src += Glob(comm + '/*.c') + Glob(comm + '/*_rvds.S') - -if rtconfig.PLATFORM == 'gcc': - src += Glob(path + '/*_init.S') - src += Glob(path + '/*.c') + Glob(path + '/*_gcc.S') - src += Glob(comm + '/*.c') + Glob(comm + '/*_gcc.S') +# RT-Thread building script for bridge -if rtconfig.PLATFORM == 'iar': - src += Glob(path + '/*.c') + Glob(path + '/*_iar.S') - src += Glob(comm + '/*.c') + Glob(comm + '/*_iar.S') - -if rtconfig.PLATFORM == 'cl': - src = Glob(path + '/*.c') - -if rtconfig.PLATFORM == 'mingw': - src = Glob(path + '/*.c') +import os +from building import * -if rtconfig.PLATFORM == 'armcc' and rtconfig.ARCH == 'arm' and rtconfig.CPU == 'arm926': - ASFLAGS = ' --cpreproc' +Import('rtconfig') -CPPPATH = [RTT_ROOT + '/libcpu/' + arch + '/' + rtconfig.CPU, RTT_ROOT + '/libcpu/' + arch + '/common'] +cwd = GetCurrentDir() +group = [] +list = os.listdir(cwd) -group = DefineGroup(rtconfig.CPU.upper(), src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) +if rtconfig.ARCH in list: + group = group + SConscript(os.path.join(rtconfig.ARCH, 'SConscript')) Return('group') diff --git a/libcpu/aarch64/SConscript b/libcpu/aarch64/SConscript new file mode 100644 index 0000000000..5fca2b473b --- /dev/null +++ b/libcpu/aarch64/SConscript @@ -0,0 +1,19 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +group = [] +list = os.listdir(cwd) + +# add common code files +group = group + SConscript(os.path.join('common', 'SConscript')) + +# cpu porting code files +if rtconfig.CPU != 'common': + group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) + +Return('group') diff --git a/libcpu/aarch64/common/SConscript b/libcpu/aarch64/common/SConscript new file mode 100644 index 0000000000..72fb8e26c3 --- /dev/null +++ b/libcpu/aarch64/common/SConscript @@ -0,0 +1,24 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*.S') +CPPPATH = [cwd] + +group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH) + +# build for sub-directory +list = os.listdir(cwd) +objs = [] + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) +group = group + objs + + +Return('group') diff --git a/libcpu/aarch64/common/armv8.h b/libcpu/aarch64/common/armv8.h new file mode 100644 index 0000000000..4350890544 --- /dev/null +++ b/libcpu/aarch64/common/armv8.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-09-15 Bernard first version + */ + +#ifndef __ARMV8_H__ +#define __ARMV8_H__ + +/* the exception stack without VFP registers */ +struct rt_hw_exp_stack +{ + unsigned long long pc; + unsigned long long spsr; + unsigned long long x30; + unsigned long long xz; + unsigned long long x28; + unsigned long long x29; + unsigned long long x26; + unsigned long long x27; + unsigned long long x24; + unsigned long long x25; + unsigned long long x22; + unsigned long long x23; + unsigned long long x20; + unsigned long long x21; + unsigned long long x18; + unsigned long long x19; + unsigned long long x16; + unsigned long long x17; + unsigned long long x14; + unsigned long long x15; + unsigned long long x12; + unsigned long long x13; + unsigned long long x10; + unsigned long long x11; + unsigned long long x8; + unsigned long long x9; + unsigned long long x6; + unsigned long long x7; + unsigned long long x4; + unsigned long long x5; + unsigned long long x2; + unsigned long long x3; + unsigned long long x0; + unsigned long long x1; +}; + +#define SP_ELx ( ( unsigned long long ) 0x01 ) +#define SP_EL0 ( ( unsigned long long ) 0x00 ) +#define PSTATE_EL1 ( ( unsigned long long ) 0x04 ) +#define PSTATE_EL2 ( ( unsigned long long ) 0x08 ) +#define PSTATE_EL3 ( ( unsigned long long ) 0x0c ) + +rt_ubase_t rt_hw_get_current_el(void); +void rt_hw_set_elx_env(void); +void rt_hw_set_current_vbar(rt_ubase_t addr); + +#endif diff --git a/libcpu/aarch64/common/cache.S b/libcpu/aarch64/common/cache.S new file mode 100644 index 0000000000..7f295a2b02 --- /dev/null +++ b/libcpu/aarch64/common/cache.S @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-03-17 bigmagic first version + */ + +/* + * void __asm_dcache_level(level) + * + * flush or invalidate one level cache. + * + * x0: cache level + * x1: 0 clean & invalidate, 1 invalidate only + * x2~x9: clobbered + */ +.globl __asm_dcache_level +__asm_dcache_level: + lsl x12, x0, #1 + msr csselr_el1, x12 /* select cache level */ + isb /* sync change of cssidr_el1 */ + mrs x6, ccsidr_el1 /* read the new cssidr_el1 */ + and x2, x6, #7 /* x2 <- log2(cache line size)-4 */ + add x2, x2, #4 /* x2 <- log2(cache line size) */ + mov x3, #0x3ff + and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */ + clz w5, w3 /* bit position of #ways */ + mov x4, #0x7fff + and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */ + /* x12 <- cache level << 1 */ + /* x2 <- line length offset */ + /* x3 <- number of cache ways - 1 */ + /* x4 <- number of cache sets - 1 */ + /* x5 <- bit position of #ways */ + +loop_set: + mov x6, x3 /* x6 <- working copy of #ways */ +loop_way: + lsl x7, x6, x5 + orr x9, x12, x7 /* map way and level to cisw value */ + lsl x7, x4, x2 + orr x9, x9, x7 /* map set number to cisw value */ + tbz w1, #0, 1f + dc isw, x9 + b 2f +1: dc cisw, x9 /* clean & invalidate by set/way */ +2: subs x6, x6, #1 /* decrement the way */ + b.ge loop_way + subs x4, x4, #1 /* decrement the set */ + b.ge loop_set + + ret + +/* + * void __asm_flush_dcache_all(int invalidate_only) + * + * x0: 0 clean & invalidate, 1 invalidate only + * + * flush or invalidate all data cache by SET/WAY. + */ +.globl __asm_dcache_all +__asm_dcache_all: + mov x1, x0 + dsb sy + mrs x10, clidr_el1 /* read clidr_el1 */ + lsr x11, x10, #24 + and x11, x11, #0x7 /* x11 <- loc */ + cbz x11, finished /* if loc is 0, exit */ + mov x15, lr + mov x0, #0 /* start flush at cache level 0 */ + /* x0 <- cache level */ + /* x10 <- clidr_el1 */ + /* x11 <- loc */ + /* x15 <- return address */ + +loop_level: + lsl x12, x0, #1 + add x12, x12, x0 /* x0 <- tripled cache level */ + lsr x12, x10, x12 + and x12, x12, #7 /* x12 <- cache type */ + cmp x12, #2 + b.lt skip /* skip if no cache or icache */ + bl __asm_dcache_level /* x1 = 0 flush, 1 invalidate */ +skip: + add x0, x0, #1 /* increment cache level */ + cmp x11, x0 + b.gt loop_level + + mov x0, #0 + msr csselr_el1, x0 /* restore csselr_el1 */ + dsb sy + isb + mov lr, x15 + +finished: + ret + +.globl __asm_flush_dcache_all +__asm_flush_dcache_all: + mov x0, #0 + b __asm_dcache_all + +.globl __asm_invalidate_dcache_all +__asm_invalidate_dcache_all: + mov x0, #0x1 + b __asm_dcache_all + +/* + * void __asm_flush_dcache_range(start, end) + * + * clean & invalidate data cache in the range + * + * x0: start address + * x1: end address + */ +.globl __asm_flush_dcache_range +__asm_flush_dcache_range: + mrs x3, ctr_el0 + lsr x3, x3, #16 + and x3, x3, #0xf + mov x2, #4 + lsl x2, x2, x3 /* cache line size */ + + /* x2 <- minimal cache line size in cache system */ + sub x3, x2, #1 + bic x0, x0, x3 +1: dc civac, x0 /* clean & invalidate data or unified cache */ + add x0, x0, x2 + cmp x0, x1 + b.lo 1b + dsb sy + ret + +/* + * void __asm_invalidate_icache_all(void) + * + * invalidate all tlb entries. + */ +.globl __asm_invalidate_icache_all +__asm_invalidate_icache_all: + ic ialluis + isb sy + ret + +.globl __asm_flush_l3_cache +__asm_flush_l3_cache: + mov x0, #0 /* return status as success */ + ret
\ No newline at end of file diff --git a/libcpu/aarch64/common/context_gcc.S b/libcpu/aarch64/common/context_gcc.S new file mode 100644 index 0000000000..934db7ed84 --- /dev/null +++ b/libcpu/aarch64/common/context_gcc.S @@ -0,0 +1,351 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-10-06 ZhaoXiaowei the first version + */ + + /* + *enable gtimer + */ +.globl rt_hw_gtimer_enable +rt_hw_gtimer_enable: + MOV X0,#1 + MSR CNTP_CTL_EL0,X0 + RET + +/* + *set gtimer CNTP_TVAL_EL0 value + */ +.globl rt_hw_set_gtimer_val +rt_hw_set_gtimer_val: + MSR CNTP_TVAL_EL0,X0 + RET + +/* + *get gtimer CNTP_TVAL_EL0 value + */ +.globl rt_hw_get_gtimer_val +rt_hw_get_gtimer_val: + MRS X0,CNTP_TVAL_EL0 + RET + + +.globl rt_hw_get_cntpct_val +rt_hw_get_cntpct_val: + MRS X0, CNTPCT_EL0 + RET + +/* + *get gtimer frq value + */ +.globl rt_hw_get_gtimer_frq +rt_hw_get_gtimer_frq: + MRS X0,CNTFRQ_EL0 + RET + +.macro SAVE_CONTEXT + + /* Switch to use the EL0 stack pointer. */ + MSR SPSEL, #0 + + /* Save the entire context. */ + STP X0, X1, [SP, #-0x10]! + STP X2, X3, [SP, #-0x10]! + STP X4, X5, [SP, #-0x10]! + STP X6, X7, [SP, #-0x10]! + STP X8, X9, [SP, #-0x10]! + STP X10, X11, [SP, #-0x10]! + STP X12, X13, [SP, #-0x10]! + STP X14, X15, [SP, #-0x10]! + STP X16, X17, [SP, #-0x10]! + STP X18, X19, [SP, #-0x10]! + STP X20, X21, [SP, #-0x10]! + STP X22, X23, [SP, #-0x10]! + STP X24, X25, [SP, #-0x10]! + STP X26, X27, [SP, #-0x10]! + STP X28, X29, [SP, #-0x10]! + STP X30, XZR, [SP, #-0x10]! + + MRS X0, CurrentEL + CMP X0, 0xc + B.EQ 3f + CMP X0, 0x8 + B.EQ 2f + CMP X0, 0x4 + B.EQ 1f + B . +3: + MRS X3, SPSR_EL3 + /* Save the ELR. */ + MRS X2, ELR_EL3 + B 0f +2: + MRS X3, SPSR_EL2 + /* Save the ELR. */ + MRS X2, ELR_EL2 + B 0f +1: + MRS X3, SPSR_EL1 + MRS X2, ELR_EL1 + B 0f +0: + + STP X2, X3, [SP, #-0x10]! + + MOV X0, SP /* Move SP into X0 for saving. */ + + /* Switch to use the ELx stack pointer. */ + MSR SPSEL, #1 + + .endm + +.macro SAVE_CONTEXT_T + + /* Switch to use the EL0 stack pointer. */ + MSR SPSEL, #0 + + /* Save the entire context. */ + STP X0, X1, [SP, #-0x10]! + STP X2, X3, [SP, #-0x10]! + STP X4, X5, [SP, #-0x10]! + STP X6, X7, [SP, #-0x10]! + STP X8, X9, [SP, #-0x10]! + STP X10, X11, [SP, #-0x10]! + STP X12, X13, [SP, #-0x10]! + STP X14, X15, [SP, #-0x10]! + STP X16, X17, [SP, #-0x10]! + STP X18, X19, [SP, #-0x10]! + STP X20, X21, [SP, #-0x10]! + STP X22, X23, [SP, #-0x10]! + STP X24, X25, [SP, #-0x10]! + STP X26, X27, [SP, #-0x10]! + STP X28, X29, [SP, #-0x10]! + STP X30, XZR, [SP, #-0x10]! + + MRS X0, CurrentEL + CMP X0, 0xc + B.EQ 3f + CMP X0, 0x8 + B.EQ 2f + CMP X0, 0x4 + B.EQ 1f + B . +3: + MRS X3, SPSR_EL3 + MOV X2, X30 + B 0f +2: + MRS X3, SPSR_EL2 + MOV X2, X30 + B 0f +1: + MRS X3, SPSR_EL1 + MOV X2, X30 + B 0f +0: + + STP X2, X3, [SP, #-0x10]! + + MOV X0, SP /* Move SP into X0 for saving. */ + + /* Switch to use the ELx stack pointer. */ + MSR SPSEL, #1 + + .endm + +.macro RESTORE_CONTEXT + + /* Switch to use the EL0 stack pointer. */ + MSR SPSEL, #0 + + /* Set the SP to point to the stack of the task being restored. */ + MOV SP, X0 + + LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */ + + MRS X0, CurrentEL + CMP X0, 0xc + B.EQ 3f + CMP X0, 0x8 + B.EQ 2f + CMP X0, 0x4 + B.EQ 1f + B . +3: + MSR SPSR_EL3, X3 + MSR ELR_EL3, X2 + B 0f +2: + MSR SPSR_EL2, X3 + MSR ELR_EL2, X2 + B 0f +1: + MSR SPSR_EL1, X3 + MSR ELR_EL1, X2 + B 0f +0: + + LDP X30, XZR, [SP], #0x10 + LDP X28, X29, [SP], #0x10 + LDP X26, X27, [SP], #0x10 + LDP X24, X25, [SP], #0x10 + LDP X22, X23, [SP], #0x10 + LDP X20, X21, [SP], #0x10 + LDP X18, X19, [SP], #0x10 + LDP X16, X17, [SP], #0x10 + LDP X14, X15, [SP], #0x10 + LDP X12, X13, [SP], #0x10 + LDP X10, X11, [SP], #0x10 + LDP X8, X9, [SP], #0x10 + LDP X6, X7, [SP], #0x10 + LDP X4, X5, [SP], #0x10 + LDP X2, X3, [SP], #0x10 + LDP X0, X1, [SP], #0x10 + + /* Switch to use the ELx stack pointer. _RB_ Might not be required. */ + MSR SPSEL, #1 + + ERET + + .endm + +.text +/* + * rt_base_t rt_hw_interrupt_disable(); + */ +.globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + MRS X0, DAIF + MSR DAIFSet, #3 + DSB SY + RET + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ +.globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + DSB SY + MOV X1, #0xC0 + ANDS X0, X0, X1 + B.NE rt_hw_interrupt_enable_exit + MSR DAIFClr, #3 +rt_hw_interrupt_enable_exit: + RET + +/* + * void rt_hw_context_switch_to(rt_ubase_t to); + * r0 --> to + */ +.globl rt_hw_context_switch_to +rt_hw_context_switch_to: + LDR X0, [X0] + RESTORE_CONTEXT + +.text +/* + * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to); + * r0 --> from + * r1 --> to + */ +.globl rt_hw_context_switch +rt_hw_context_switch: + + MOV X8,X0 + MOV X9,X1 + + SAVE_CONTEXT_T + + STR X0, [X8] // store sp in preempted tasks TCB + LDR X0, [X9] // get new task stack pointer + + RESTORE_CONTEXT + +/* + * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to); + */ +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread +.globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + ADR X2, rt_thread_switch_interrupt_flag + LDR X3, [X2] + CMP X3, #1 + B.EQ _reswitch + ADR X4, rt_interrupt_from_thread // set rt_interrupt_from_thread + MOV X3, #1 // set rt_thread_switch_interrupt_flag to 1 + STR X0, [X4] + STR X3, [X2] +_reswitch: + ADR X2, rt_interrupt_to_thread // set rt_interrupt_to_thread + STR X1, [X2] + RET + +.text + +// -- Exception handlers ---------------------------------- + + .align 8 +.globl vector_fiq +vector_fiq: + SAVE_CONTEXT + STP X0, X1, [SP, #-0x10]! + BL rt_hw_trap_fiq + LDP X0, X1, [SP], #0x10 + RESTORE_CONTEXT + +.globl rt_interrupt_enter +.globl rt_interrupt_leave +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread + + +// ------------------------------------------------------------------- + + .align 8 +.globl vector_irq +vector_irq: + SAVE_CONTEXT + STP X0, X1, [SP, #-0x10]! + + BL rt_interrupt_enter + BL rt_hw_trap_irq + BL rt_interrupt_leave + + LDP X0, X1, [SP], #0x10 + + // if rt_thread_switch_interrupt_flag set, jump to + // rt_hw_context_switch_interrupt_do and don't return + ADR X1, rt_thread_switch_interrupt_flag + LDR X2, [X1] + CMP X2, #1 + B.NE vector_irq_exit + + MOV X2, #0 // clear flag + STR X2, [X1] + + ADR X3, rt_interrupt_from_thread + LDR X4, [X3] + STR x0, [X4] // store sp in preempted tasks's TCB + + ADR x3, rt_interrupt_to_thread + LDR X4, [X3] + LDR x0, [X4] // get new task's stack pointer + +vector_irq_exit: + RESTORE_CONTEXT + +// ------------------------------------------------- + + .align 8 + .globl vector_error +vector_error: + SAVE_CONTEXT + BL rt_hw_trap_error + B . diff --git a/libcpu/aarch64/common/cp15.h b/libcpu/aarch64/common/cp15.h new file mode 100644 index 0000000000..f3ffd6f857 --- /dev/null +++ b/libcpu/aarch64/common/cp15.h @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-09-15 Bernard first version + */ + +#ifndef __CP15_H__ +#define __CP15_H__ + +#ifndef __STATIC_FORCEINLINE +#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif + +#define __WFI() __asm__ volatile ("wfi":::"memory") + +#define __WFE() __asm__ volatile ("wfe":::"memory") + +#define __SEV() __asm__ volatile ("sev") + +__STATIC_FORCEINLINE void __ISB(void) +{ + __asm__ volatile ("isb 0xF":::"memory"); +} + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __asm__ volatile ("dsb 0xF":::"memory"); +} + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ + +__STATIC_FORCEINLINE void __DMB(void) +{ + __asm__ volatile ("dmb 0xF":::"memory"); +} + +#ifdef RT_USING_SMP +static inline void send_ipi_msg(int cpu, int ipi_vector) +{ + IPI_MAILBOX_SET(cpu) = 1 << ipi_vector; +} + +static inline void setup_bootstrap_addr(int cpu, int addr) +{ + CORE_MAILBOX3_SET(cpu) = addr; +} + +static inline void enable_cpu_ipi_intr(int cpu) +{ + COREMB_INTCTL(cpu) = IPI_MAILBOX_INT_MASK; +} + +static inline void enable_cpu_timer_intr(int cpu) +{ + CORETIMER_INTCTL(cpu) = 0x8; +} + +static inline void enable_cntv(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 1; + asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL +} + +static inline void disable_cntv(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 0; + asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL +} + +static inline void mask_cntv(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 2; + asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL +} + +static inline void unmask_cntv(void) +{ + rt_uint32_t cntv_ctl; + cntv_ctl = 1; + asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL +} + +static inline rt_uint64_t read_cntvct(void) +{ + rt_uint32_t val,val1; + asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (val),"=r" (val1)); + return (val); +} + +static inline rt_uint64_t read_cntvoff(void) +{ + + rt_uint64_t val; + asm volatile("mrrc p15, 4, %Q0, %R0, c14" : "=r" (val)); + return (val); +} + +static inline rt_uint32_t read_cntv_tval(void) +{ + rt_uint32_t val; + asm volatile ("mrc p15, 0, %0, c14, c3, 0" : "=r"(val) ); + return val; +} + + +static inline void write_cntv_tval(rt_uint32_t val) +{ + asm volatile ("mcr p15, 0, %0, c14, c3, 0" :: "r"(val) ); + return; +} + +static inline rt_uint32_t read_cntfrq(void) +{ + rt_uint32_t val; + asm volatile ("mrc p15, 0, %0, c14, c0, 0" : "=r"(val) ); + return val; +} + + +static inline rt_uint32_t read_cntctrl(void) +{ + rt_uint32_t val; + asm volatile ("mrc p15, 0, %0, c14, c1, 0" : "=r"(val) ); + return val; +} + +static inline uint32_t write_cntctrl(uint32_t val) +{ + + asm volatile ("mcr p15, 0, %0, c14, c1, 0" : :"r"(val) ); + return val; +} +#endif + +unsigned long rt_cpu_get_smp_id(void); + +void rt_cpu_mmu_disable(void); +void rt_cpu_mmu_enable(void); +void rt_cpu_tlb_set(volatile unsigned long*); + +void rt_cpu_dcache_clean_flush(void); +void rt_cpu_icache_flush(void); + +void rt_cpu_vector_set_base(rt_ubase_t addr); +void rt_hw_mmu_init(void); +void rt_hw_vector_init(void); + +void set_timer_counter(unsigned int counter); +void set_timer_control(unsigned int control); +#endif diff --git a/libcpu/aarch64/common/cpu.c b/libcpu/aarch64/common/cpu.c new file mode 100644 index 0000000000..962a53a071 --- /dev/null +++ b/libcpu/aarch64/common/cpu.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-09-15 Bernard first version + * 2019-07-28 zdzn add smp support + */ + +#include <rthw.h> +#include <rtthread.h> +#include <board.h> +#include "cp15.h" + +int rt_hw_cpu_id(void) +{ + int cpu_id; + rt_base_t value; + + __asm__ volatile ( + "mrs %0, mpidr_el1" + :"=r"(value) + ); + cpu_id = value & 0xf; + return cpu_id; +}; + +#ifdef RT_USING_SMP +void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock) +{ + lock->slock = 0; +} + +void rt_hw_spin_lock(rt_hw_spinlock_t *lock) +{ + unsigned long tmp; + unsigned long newval; + rt_hw_spinlock_t lockval; + __asm__ __volatile__( + "pld [%0]" + ::"r"(&lock->slock) + ); + + __asm__ __volatile__( + "1: ldrex %0, [%3]\n" + " add %1, %0, %4\n" + " strex %2, %1, [%3]\n" + " teq %2, #0\n" + " bne 1b" + : "=&r" (lockval), "=&r" (newval), "=&r" (tmp) + : "r" (&lock->slock), "I" (1 << 16) + : "cc"); + + while (lockval.tickets.next != lockval.tickets.owner) { + __WFE(); + lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner); + } + + __DMB(); +} + +void rt_hw_spin_unlock(rt_hw_spinlock_t *lock) +{ + __DMB(); + lock->tickets.owner++; + __DSB(); + __SEV(); +} +#endif /*RT_USING_SMP*/ + +/** + * @addtogroup ARM CPU + */ +/*@{*/ + +/** shutdown CPU */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} + +/*@}*/ diff --git a/libcpu/aarch64/common/cpu_gcc.S b/libcpu/aarch64/common/cpu_gcc.S new file mode 100644 index 0000000000..b8c8b8768c --- /dev/null +++ b/libcpu/aarch64/common/cpu_gcc.S @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Date Author Notes + * 2018-10-06 ZhaoXiaowei the first version + */ + +.text +.globl rt_hw_get_current_el +rt_hw_get_current_el: + MRS X0, CurrentEL + CMP X0, 0xc + B.EQ 3f + CMP X0, 0x8 + B.EQ 2f + CMP X0, 0x4 + B.EQ 1f + + LDR X0, =0 + B 0f +3: + LDR X0, =3 + B 0f +2: + LDR X0, =2 + B 0f +1: + LDR X0, =1 + B 0f +0: + RET + + +.globl rt_hw_set_current_vbar +rt_hw_set_current_vbar: + MRS X1, CurrentEL + CMP X1, 0xc + B.EQ 3f + CMP X1, 0x8 + B.EQ 2f + CMP X1, 0x4 + B.EQ 1f + B 0f +3: + MSR VBAR_EL3,X0 + B 0f +2: + MSR VBAR_EL2,X0 + B 0f +1: + MSR VBAR_EL1,X0 + B 0f +0: + RET + + +.globl rt_hw_set_elx_env +rt_hw_set_elx_env: + MRS X1, CurrentEL + CMP X1, 0xc + B.EQ 3f + CMP X1, 0x8 + B.EQ 2f + CMP X1, 0x4 + B.EQ 1f + B 0f +3: + MRS X0, SCR_EL3 + ORR X0, X0, #0xF /* SCR_EL3.NS|IRQ|FIQ|EA */ + MSR SCR_EL3, X0 + B 0f +2: + MRS X0, HCR_EL2 + ORR X0, X0, #0x38 + MSR HCR_EL2, X0 + B 0f +1: + B 0f +0: + RET diff --git a/libcpu/aarch64/common/gic/SConscript b/libcpu/aarch64/common/gic/SConscript new file mode 100644 index 0000000000..b114ba7678 --- /dev/null +++ b/libcpu/aarch64/common/gic/SConscript @@ -0,0 +1,24 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd] + +gic400_group = Split(''' +gic_pl400.c +''') + +gic500_group = Split(''' +gic_pl500.c +''') + +src = () +if GetDepend('BSP_USING_GIC400'): + src = gic400_group +if GetDepend('BSP_USING_GIC500'): + src = gic500_group + +group = DefineGroup('gic', src, depend = ['BSP_USING_GIC'], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/aarch64/common/gic/gic_pl400.c b/libcpu/aarch64/common/gic/gic_pl400.c new file mode 100644 index 0000000000..1f4d868636 --- /dev/null +++ b/libcpu/aarch64/common/gic/gic_pl400.c @@ -0,0 +1,261 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + * 2014-04-03 Grissiom many enhancements + * 2018-11-22 Jesven add rt_hw_ipi_send() + * add rt_hw_ipi_handler_install() + */ +#include <rtthread.h> + +#include "gic_pl400.h" +#include "cp15.h" + +#define ARM_GIC_MAX_NR 1 +struct arm_gic +{ + rt_uint32_t offset; /* the first interrupt index in the vector table */ + + rt_uint32_t dist_hw_base; /* the base address of the gic distributor */ + rt_uint32_t cpu_hw_base; /* the base addrees of the gic cpu interface */ +}; + +/* 'ARM_GIC_MAX_NR' is the number of cores */ +static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; + +static unsigned int _gic_max_irq; + +int arm_gic_get_active_irq(rt_uint32_t index) +{ + int irq; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base); + irq += _gic_table[index].offset; + return irq; +} + +void arm_gic_ack(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_mask(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_clear_pending(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_clear_active(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +/* Set up the cpu mask for the specific interrupt */ +void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) +{ + rt_uint32_t old_tgt; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); + + old_tgt &= ~(0x0FFUL << ((irq % 4)*8)); + old_tgt |= cpumask << ((irq % 4)*8); + + GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; +} + +void arm_gic_umask(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_dump_type(rt_uint32_t index) +{ + unsigned int gic_type; + + gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); + rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", + (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf, + _gic_table[index].dist_hw_base, + _gic_max_irq, + gic_type & (1 << 10) ? "has" : "no", + gic_type); +} + +void arm_gic_dump(rt_uint32_t index) +{ + unsigned int i, k; + + k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); + rt_kprintf("--- high pending priority: %d(%08x)\n", k, k); + rt_kprintf("--- hw mask ---\n"); + for (i = 0; i < _gic_max_irq / 32; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, + i * 32)); + } + rt_kprintf("\n--- hw pending ---\n"); + for (i = 0; i < _gic_max_irq / 32; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, + i * 32)); + } + rt_kprintf("\n--- hw active ---\n"); + for (i = 0; i < _gic_max_irq / 32; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, + i * 32)); + } + rt_kprintf("\n"); +} +#ifdef RT_USING_FINSH +#include <finsh.h> +FINSH_FUNCTION_EXPORT_ALIAS(arm_gic_dump, gic, show gic status); +#endif + +int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) +{ + unsigned int gic_type, i; + rt_uint32_t cpumask = 1 << 0; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + _gic_table[index].dist_hw_base = dist_base; + _gic_table[index].offset = irq_start; + + /* Find out how many interrupts are supported. */ + gic_type = GIC_DIST_TYPE(dist_base); + _gic_max_irq = ((gic_type & 0x1f) + 1) * 32; + + /* + * The GIC only supports up to 1020 interrupt sources. + * Limit this to either the architected maximum, or the + * platform maximum. + */ + if (_gic_max_irq > 1020) + _gic_max_irq = 1020; + if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */ + _gic_max_irq = ARM_GIC_NR_IRQS; + + cpumask |= cpumask << 8; + cpumask |= cpumask << 16; + cpumask |= cpumask << 24; + + GIC_DIST_CTRL(dist_base) = 0x0; + + /* Set all global interrupts to be level triggered, active low. */ + for (i = 32; i < _gic_max_irq; i += 16) + GIC_DIST_CONFIG(dist_base, i) = 0x0; + + /* Set all global interrupts to this CPU only. */ + for (i = 32; i < _gic_max_irq; i += 4) + GIC_DIST_TARGET(dist_base, i) = cpumask; + + /* Set priority on all interrupts. */ + for (i = 0; i < _gic_max_irq; i += 4) + GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0; + + /* Disable all interrupts. */ + for (i = 0; i < _gic_max_irq; i += 32) + GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff; + +#if 0 + /* All interrupts defaults to IGROUP1(IRQ). */ + for (i = 0; i < _gic_max_irq; i += 32) + GIC_DIST_IGROUP(dist_base, i) = 0xffffffff; +#endif + for (i = 0; i < _gic_max_irq; i += 32) + GIC_DIST_IGROUP(dist_base, i) = 0; + + /* Enable group0 and group1 interrupt forwarding. */ + GIC_DIST_CTRL(dist_base) = 0x01; + + return 0; +} + +int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + _gic_table[index].cpu_hw_base = cpu_base; + + GIC_CPU_PRIMASK(cpu_base) = 0xf0; + GIC_CPU_BINPOINT(cpu_base) = 0x7; + /* Enable CPU interrupt */ + GIC_CPU_CTRL(cpu_base) = 0x01; + + return 0; +} + +void arm_gic_set_group(rt_uint32_t index, int vector, int group) +{ + /* As for GICv2, there are only group0 and group1. */ + RT_ASSERT(group <= 1); + RT_ASSERT(vector < _gic_max_irq); + + if (group == 0) + { + GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, + vector) &= ~(1 << (vector % 32)); + } + else if (group == 1) + { + GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, + vector) |= (1 << (vector % 32)); + } +} + diff --git a/libcpu/aarch64/common/gic/gic_pl400.h b/libcpu/aarch64/common/gic/gic_pl400.h new file mode 100644 index 0000000000..fa20846ea2 --- /dev/null +++ b/libcpu/aarch64/common/gic/gic_pl400.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + */ + +#ifndef __GIC_PL400_H__ +#define __GIC_PL400_H__ + +#include <rthw.h> +#include <board.h> + +#define __REG32(x) (*((volatile unsigned int*)((rt_uint64_t)x))) + +#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00) +#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04) +#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08) +#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c) +#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10) +#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14) +#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18) + +#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000) +#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004) +#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4) +#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4) +#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4) +#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4) +#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4) +#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380 + ((n)/32) * 4) +#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4) +#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4) +#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4) +#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00) +#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10 + ((n)/4) * 4) +#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8) + +int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start); +int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base); + +void arm_gic_mask(rt_uint32_t index, int irq); +void arm_gic_umask(rt_uint32_t index, int irq); +void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask); +void arm_gic_set_group(rt_uint32_t index, int vector, int group); + +int arm_gic_get_active_irq(rt_uint32_t index); +void arm_gic_ack(rt_uint32_t index, int irq); + +void arm_gic_clear_active(rt_uint32_t index, int irq); +void arm_gic_clear_pending(rt_uint32_t index, int irq); + +void arm_gic_dump_type(rt_uint32_t index); +void arm_gic_dump(rt_uint32_t index); + +#endif + diff --git a/libcpu/aarch64/common/mmu.c b/libcpu/aarch64/common/mmu.c new file mode 100644 index 0000000000..b799143084 --- /dev/null +++ b/libcpu/aarch64/common/mmu.c @@ -0,0 +1,367 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-02-20 bigmagic first version + */ +#include <mmu.h> +#include <stddef.h> +#include <rthw.h> + +#define TTBR_CNP 1 + +typedef unsigned long int uint64_t; + +static unsigned long main_tbl[512 * 20] __attribute__((aligned (4096))); + +#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0) + +#define PMD_TYPE_SECT (1 << 0) + +#define PMD_TYPE_TABLE (3 << 0) + +#define PTE_TYPE_PAGE (3 << 0) + +#define BITS_PER_VA 39 + +/* Granule size of 4KB is being used */ +#define GRANULE_SIZE_SHIFT 12 +#define GRANULE_SIZE (1 << GRANULE_SIZE_SHIFT) +#define XLAT_ADDR_MASK ((1UL << BITS_PER_VA) - GRANULE_SIZE) + +#define PMD_TYPE_MASK (3 << 0) + +int free_idx = 1; + +void __asm_invalidate_icache_all(void); +void __asm_flush_dcache_all(void); +int __asm_flush_l3_cache(void); +void __asm_flush_dcache_range(unsigned long long start, unsigned long long end); +void __asm_invalidate_dcache_all(void); +void __asm_invalidate_icache_all(void); + +void mmu_memset(char *dst, char v, size_t len) +{ + while (len--) + { + *dst++ = v; + } +} + +static unsigned long __page_off = 0; +static unsigned long get_free_page(void) +{ + __page_off += 512; + return (unsigned long)(main_tbl + __page_off); +} + + +static inline unsigned int get_sctlr(void) +{ + unsigned int val; + asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc"); + return val; +} + +static inline void set_sctlr(unsigned int val) +{ + asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); + asm volatile("isb"); +} + +void mmu_init(void) +{ + unsigned long val64; + unsigned long val32; + + val64 = 0x007f6eUL; + __asm__ volatile("msr MAIR_EL1, %0\n dsb sy\n"::"r"(val64)); + __asm__ volatile("mrs %0, MAIR_EL1\n dsb sy\n":"=r"(val64)); + + //TCR_EL1 + val32 = (16UL << 0)//48bit + | (0x0UL << 6) + | (0x0UL << 7) + | (0x3UL << 8) + | (0x3UL << 10)//Inner Shareable + | (0x2UL << 12) + | (0x0UL << 14)//4K + | (0x0UL << 16) + | (0x0UL << 22) + | (0x1UL << 23) + | (0x2UL << 30) + | (0x1UL << 32) + | (0x0UL << 35) + | (0x0UL << 36) + | (0x0UL << 37) + | (0x0UL << 38); + __asm__ volatile("msr TCR_EL1, %0\n"::"r"(val32)); + __asm__ volatile("mrs %0, TCR_EL1\n":"=r"(val32)); + + __asm__ volatile("msr TTBR0_EL1, %0\n dsb sy\n"::"r"(main_tbl)); + __asm__ volatile("mrs %0, TTBR0_EL1\n dsb sy\n":"=r"(val64)); + + mmu_memset((char *)main_tbl, 0, 4096); +} + +void mmu_enable(void) +{ + unsigned long val64; + unsigned long val32; + + __asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val64)); + val64 &= ~0x1000; //disable I + __asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\n isb sy\n"::"r"(val64)); + + __asm__ volatile("IC IALLUIS\n dsb sy\n isb sy\n"); + __asm__ volatile("tlbi vmalle1\n dsb sy\n isb sy\n"); + + //SCTLR_EL1, turn on mmu + __asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val32)); + val32 |= 0x1005; //enable mmu, I C M + __asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\nisb sy\n"::"r"(val32)); + rt_hw_icache_enable(); + rt_hw_dcache_enable(); + +} + +static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) +{ + int level; + unsigned long* cur_lv_tbl = lv0_tbl; + unsigned long page; + unsigned long off; + int level_shift = 39; + + if (va & (0x200000UL - 1)) + { + return MMU_MAP_ERROR_VANOTALIGN; + } + if (pa & (0x200000UL - 1)) + { + return MMU_MAP_ERROR_PANOTALIGN; + } + for (level = 0; level < 2; level++) + { + off = (va >> level_shift); + off &= MMU_LEVEL_MASK; + if ((cur_lv_tbl[off] & 1) == 0) + { + page = get_free_page(); + if (!page) + { + return MMU_MAP_ERROR_NOPAGE; + } + mmu_memset((char *)page, 0, 4096); + cur_lv_tbl[off] = page | 0x3UL; + } + page = cur_lv_tbl[off]; + if (!(page & 0x2)) + { + //is block! error! + return MMU_MAP_ERROR_CONFLICT; + } + cur_lv_tbl = (unsigned long*)(page & 0x0000fffffffff000UL); + level_shift -= 9; + } + attr &= 0xfff0000000000ffcUL; + pa |= (attr | 0x1UL); //block + off = (va >> 21); + off &= MMU_LEVEL_MASK; + cur_lv_tbl[off] = pa; + return 0; +} + +int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long attr) +{ + int i; + int ret; + + if (va & (0x200000 - 1)) + { + return -1; + } + if (pa & (0x200000 - 1)) + { + return -1; + } + for (i = 0; i < count; i++) + { + ret = map_single_page_2M((unsigned long *)main_tbl, va, pa, attr); + va += 0x200000; + pa += 0x200000; + if (ret != 0) + { + return ret; + } + } + return 0; +} + +static void set_table(uint64_t *pt, uint64_t *table_addr) +{ + uint64_t val; + val = (0x3UL | (uint64_t)table_addr); + *pt = val; +} + +void mmu_memset2(unsigned char *dst, char v, int len) +{ + while (len--) + { + *dst++ = v; + } +} + +static uint64_t *create_table(void) +{ + uint64_t *new_table = (uint64_t *)((unsigned char *)&main_tbl[0] + free_idx * 4096); //+ free_idx * GRANULE_SIZE; + /* Mark all entries as invalid */ + mmu_memset2((unsigned char *)new_table, 0, 4096); + free_idx++; + return new_table; +} + +static int pte_type(uint64_t *pte) +{ + return *pte & PMD_TYPE_MASK; +} + +static int level2shift(int level) +{ + /* Page is 12 bits wide, every level translates 9 bits */ + return (12 + 9 * (3 - level)); +} + +static uint64_t *get_level_table(uint64_t *pte) +{ + uint64_t *table = (uint64_t *)(*pte & XLAT_ADDR_MASK); + + if (pte_type(pte) != PMD_TYPE_TABLE) + { + table = create_table(); + set_table(pte, table); + } + return table; +} + +static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t attr) +{ + uint64_t block_size = 0; + uint64_t block_shift = 0; + uint64_t *pte; + uint64_t idx = 0; + uint64_t addr = 0; + uint64_t *table = 0; + int level = 0; + + addr = virt; + while (size) + { + table = &main_tbl[0]; + for (level = 0; level < 4; level++) + { + block_shift = level2shift(level); + idx = addr >> block_shift; + idx = idx%512; + block_size = (uint64_t)(1L << block_shift); + pte = table + idx; + + if (size >= block_size && IS_ALIGNED(addr, block_size)) + { + attr &= 0xfff0000000000ffcUL; + if(level != 3) + { + *pte = phys | (attr | 0x1UL); + } + else + { + *pte = phys | (attr | 0x3UL); + } + addr += block_size; + phys += block_size; + size -= block_size; + break; + } + table = get_level_table(pte); + } + } +} + +void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned long attr) +{ + map_region(va, pa, size, attr); +} + +void rt_hw_dcache_enable(void) +{ + if (!(get_sctlr() & CR_M)) + { + rt_kprintf("please init mmu!\n"); + } + else + { + set_sctlr(get_sctlr() | CR_C); + } +} + +void rt_hw_dcache_flush_all(void) +{ + int ret; + + __asm_flush_dcache_all(); + ret = __asm_flush_l3_cache(); + if (ret) + { + rt_kprintf("flushing dcache returns 0x%x\n", ret); + } + else + { + rt_kprintf("flushing dcache successfully.\n"); + } +} + +void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size) +{ + __asm_flush_dcache_range(start_addr, start_addr + size); +} +void rt_hw_dcache_invalidate_range(unsigned long start_addr,unsigned long size) +{ + __asm_flush_dcache_range(start_addr, start_addr + size); +} + +void rt_hw_dcache_invalidate_all(void) +{ + __asm_invalidate_dcache_all(); +} + +void rt_hw_dcache_disable(void) +{ + /* if cache isn't enabled no need to disable */ + if(!(get_sctlr() & CR_C)) + { + rt_kprintf("need enable cache!\n"); + return; + } + set_sctlr(get_sctlr() & ~CR_C); +} + +//icache +void rt_hw_icache_enable(void) +{ + __asm_invalidate_icache_all(); + set_sctlr(get_sctlr() | CR_I); +} + +void rt_hw_icache_invalidate_all(void) +{ + __asm_invalidate_icache_all(); +} + +void rt_hw_icache_disable(void) +{ + set_sctlr(get_sctlr() & ~CR_I); +}
\ No newline at end of file diff --git a/libcpu/aarch64/common/mmu.h b/libcpu/aarch64/common/mmu.h new file mode 100644 index 0000000000..6a66472c79 --- /dev/null +++ b/libcpu/aarch64/common/mmu.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-02-20 bigmagic first version + */ + +#ifndef __MMU_H__ +#define __MMU_H__ + +/* + * CR1 bits (CP#15 CR1) + */ +#define CR_M (1 << 0) /* MMU enable */ +#define CR_A (1 << 1) /* Alignment abort enable */ +#define CR_C (1 << 2) /* Dcache enable */ +#define CR_W (1 << 3) /* Write buffer enable */ +#define CR_P (1 << 4) /* 32-bit exception handler */ +#define CR_D (1 << 5) /* 32-bit data address range */ +#define CR_L (1 << 6) /* Implementation defined */ +#define CR_B (1 << 7) /* Big endian */ +#define CR_S (1 << 8) /* System MMU protection */ +#define CR_R (1 << 9) /* ROM MMU protection */ +#define CR_F (1 << 10) /* Implementation defined */ +#define CR_Z (1 << 11) /* Implementation defined */ +#define CR_I (1 << 12) /* Icache enable */ +#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ +#define CR_RR (1 << 14) /* Round Robin cache replacement */ +#define CR_L4 (1 << 15) /* LDR pc can set T bit */ +#define CR_DT (1 << 16) +#define CR_IT (1 << 18) +#define CR_ST (1 << 19) +#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ +#define CR_U (1 << 22) /* Unaligned access operation */ +#define CR_XP (1 << 23) /* Extended page tables */ +#define CR_VE (1 << 24) /* Vectored interrupts */ +#define CR_EE (1 << 25) /* Exception (Big) Endian */ +#define CR_TRE (1 << 28) /* TEX remap enable */ +#define CR_AFE (1 << 29) /* Access flag enable */ +#define CR_TE (1 << 30) /* Thumb exception enable */ + +#define MMU_LEVEL_MASK 0x1ffUL +#define MMU_MAP_ERROR_VANOTALIGN -1 +#define MMU_MAP_ERROR_PANOTALIGN -2 +#define MMU_MAP_ERROR_NOPAGE -3 +#define MMU_MAP_ERROR_CONFLICT -4 + +#define MEM_ATTR_MEMORY ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x1UL << 2)) +#define MEM_ATTR_IO ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x2UL << 2)) + +#define BUS_ADDRESS(phys) (((phys) & ~0xC0000000) | 0xC0000000) + +void mmu_init(void); + +void mmu_enable(void); + +int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long attr); + +void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned long attr); + +//dcache +void rt_hw_dcache_enable(void); +void rt_hw_dcache_flush_all(void); +void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size); +void rt_hw_dcache_invalidate_range(unsigned long start_addr,unsigned long size); +void rt_hw_dcache_invalidate_all(void); +void rt_hw_dcache_disable(void); + +//icache +void rt_hw_icache_enable(void); +void rt_hw_icache_invalidate_all(void); +void rt_hw_icache_disable(void); + + +#endif /*__MMU_H__*/ diff --git a/libcpu/aarch64/common/startup_gcc.S b/libcpu/aarch64/common/startup_gcc.S new file mode 100644 index 0000000000..ea4268148c --- /dev/null +++ b/libcpu/aarch64/common/startup_gcc.S @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + + .global Reset_Handler + .section ".start", "ax" +Reset_Handler: + nop diff --git a/libcpu/aarch64/common/vector_gcc.S b/libcpu/aarch64/common/vector_gcc.S new file mode 100644 index 0000000000..fc88cce7f8 --- /dev/null +++ b/libcpu/aarch64/common/vector_gcc.S @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Date Author Notes + * 2018-10-06 ZhaoXiaowei the first version + */ + +.text + +.globl system_vectors +.globl vector_error +.globl vector_irq +.globl vector_fiq + +system_vectors: +.align 11 + .set VBAR, system_vectors + .org VBAR + // Exception from CurrentEL (EL1) with SP_EL0 (SPSEL=1) + .org (VBAR + 0x00 + 0) + B vector_error // Synchronous + .org (VBAR + 0x80 + 0) + B vector_irq // IRQ/vIRQ + .org (VBAR + 0x100 + 0) + B vector_fiq // FIQ/vFIQ + .org (VBAR + 0x180 + 0) + B vector_error // Error/vError + + // Exception from CurrentEL (EL1) with SP_ELn + .org (VBAR + 0x200 + 0) + B vector_error // Synchronous + .org (VBAR + 0x280 + 0) + B vector_irq // IRQ/vIRQ + .org (VBAR + 0x300 + 0) + B vector_fiq // FIQ/vFIQ + .org (VBAR + 0x380 + 0) + B vector_error + + // Exception from lower EL, aarch64 + .org (VBAR + 0x400 + 0) + B vector_error + .org (VBAR + 0x480 + 0) + B vector_error + .org (VBAR + 0x500 + 0) + B vector_error + .org (VBAR + 0x580 + 0) + B vector_error + + // Exception from lower EL, aarch32 + .org (VBAR + 0x600 + 0) + B vector_error + .org (VBAR + 0x680 + 0) + B vector_error + .org (VBAR + 0x700 + 0) + B vector_error + .org (VBAR + 0x780 + 0) + B vector_error + .org (VBAR + 0x800 + 0) + B vector_error diff --git a/libcpu/aarch64/cortex-a53/SConscript b/libcpu/aarch64/cortex-a53/SConscript new file mode 100644 index 0000000000..c6a4817802 --- /dev/null +++ b/libcpu/aarch64/cortex-a53/SConscript @@ -0,0 +1,13 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*.S') +CPPPATH = [cwd] + +group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/aarch64/cortex-a53/entry_point.S b/libcpu/aarch64/cortex-a53/entry_point.S new file mode 100644 index 0000000000..6d2c69226b --- /dev/null +++ b/libcpu/aarch64/cortex-a53/entry_point.S @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Date Author Notes + * 2020-01-15 bigmagic the first version + */ + +.section ".text.entrypoint" + +.set EL1_stack, __el1_stack + +.global _start + +// This symbol is set to 0x80000 in ld script. That is the address that raspi3's firmware +// loads 'kernel8.img' file in. +_start: + // read cpu id, stop slave cores + mrs x1, mpidr_el1 // MPIDR_EL1: Multi-Processor Affinity Register + and x1, x1, #3 + cbz x1, .L__cpu_0 // .L prefix is the local label in ELF + + // cpu id > 0, stop + // cpu id == 0 will also goto here after returned from entry() if possible +.L__current_cpu_idle: + wfe + b .L__current_cpu_idle + +.L__cpu_0: // cpu id == 0 + + // set stack before our code + + /* Define stack pointer for current exception level */ + // ldr x2, =EL1_stack + // mov sp, x2 + + ldr x1, =_start + + // set up EL1 + mrs x0, CurrentEL // CurrentEL Register. bit 2, 3. Others reserved + and x0, x0, #12 // clear reserved bits + + // running at EL3? + cmp x0, #12 // 1100b. So, EL3 + bne .L__not_in_el3 // 11? !EL3 -> 5: + + // should never be executed, just for completeness. (EL3) + mov x2, #0x5b1 + msr scr_el3, x2 // SCR_ELn Secure Configuration Register + mov x2, #0x3c9 + msr spsr_el3, x2 // SPSR_ELn. Saved Program Status Register. 1111001001 + adr x2, .L__not_in_el3 + msr elr_el3, x2 + eret // Exception Return: from EL3, continue from .L__not_in_el3 + + // running at EL2 or EL1 +.L__not_in_el3: + cmp x0, #4 // 0x04 0100 EL1 + beq .L__in_el1 // EL1 -> 5: + + // in EL2 + msr sp_el1, x1 // Set sp of EL1 to _start + + // enable CNTP for EL1 + mrs x0, cnthctl_el2 // Counter-timer Hypervisor Control register + orr x0, x0, #3 + msr cnthctl_el2, x0 + msr cntvoff_el2, xzr + + // enable AArch64 in EL1 + mov x0, #(1 << 31) // AArch64 + orr x0, x0, #(1 << 1) // SWIO hardwired on Pi3 + msr hcr_el2, x0 + mrs x0, hcr_el2 + + // change execution level to EL1 + mov x2, #0x3c4 + msr spsr_el2, x2 // 1111000100 + adr x2, .L__in_el1 + msr elr_el2, x2 + eret // exception return. from EL2. continue from .L__in_el1 + +.L__in_el1: + mov sp, x1 // in EL1. Set sp to _start + + // Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction + mov x1, #0x00300000 // Don't trap any SIMD/FP instructions in both EL0 and EL1 + msr cpacr_el1, x1 + + mrs x1, sctlr_el1 + orr x1, x1, #(1 << 12) + bic x1, x1, #(3 << 3) + bic x1, x1, #(1 << 1) + msr sctlr_el1, x1 + + // clear bss + ldr x1, =__bss_start + ldr w2, =__bss_size + +.L__clean_bss_loop: + cbz w2, .L__jump_to_entry + str xzr, [x1], #8 + sub w2, w2, #1 + cbnz w2, .L__clean_bss_loop + + // jump to C code, should not return +.L__jump_to_entry: + bl entry + // for failsafe, halt this core too + b .L__current_cpu_idle diff --git a/libcpu/aarch64/cortex-a53/interrupt.c b/libcpu/aarch64/cortex-a53/interrupt.c new file mode 100644 index 0000000000..a412ca1953 --- /dev/null +++ b/libcpu/aarch64/cortex-a53/interrupt.c @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/5/3 Bernard first version + * 2019-07-28 zdzn add smp support + * 2019-08-09 zhangjun fixup the problem of smp startup and scheduling issues, + * write addr to mailbox3 to startup smp, and we use mailbox0 for ipi + */ + +#include <rthw.h> +#include <board.h> +#include <rtthread.h> + +#include "cp15.h" +#include "armv8.h" +#include "interrupt.h" + +#define MAX_HANDLERS 72 + +#ifdef RT_USING_SMP +#define rt_interrupt_nest rt_cpu_self()->irq_nest +#else +extern volatile rt_uint8_t rt_interrupt_nest; +#endif + +extern int system_vectors; + +/* exception and interrupt handler table */ +struct rt_irq_desc isr_table[MAX_HANDLERS]; + +rt_ubase_t rt_interrupt_from_thread; +rt_ubase_t rt_interrupt_to_thread; +rt_ubase_t rt_thread_switch_interrupt_flag; + +void rt_hw_vector_init(void) +{ + rt_hw_set_current_vbar((rt_ubase_t)&system_vectors); // cpu_gcc.S +} + +static void default_isr_handler(int vector, void *param) +{ +#ifdef RT_USING_SMP + rt_kprintf("cpu %d unhandled irq: %d\n", rt_hw_cpu_id(),vector); +#else + rt_kprintf("unhandled irq: %d\n",vector); +#endif +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + rt_uint32_t index; + + /* mask all of interrupts */ + IRQ_DISABLE_BASIC = 0x000000ff; + IRQ_DISABLE1 = 0xffffffff; + IRQ_DISABLE2 = 0xffffffff; + for (index = 0; index < MAX_HANDLERS; index ++) + { + isr_table[index].handler = default_isr_handler; + isr_table[index].param = NULL; +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX); + isr_table[index].counter = 0; +#endif + } + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + if (vector < 32) + { + IRQ_DISABLE1 = (1 << vector); + } + else if (vector<64) + { + vector = vector % 32; + IRQ_DISABLE2 = (1 << vector); + } + else + { + vector = vector - 64; + IRQ_DISABLE_BASIC = (1 << vector); + } +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + if (vector < 32) + { + IRQ_ENABLE1 = (1 << vector); + } + else if (vector < 64) + { + vector = vector % 32; + IRQ_ENABLE2 = (1 << vector); + } + else + { + vector = vector - 64; + IRQ_ENABLE_BASIC = (1 << vector); + } +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if (vector < MAX_HANDLERS) + { + old_handler = isr_table[vector].handler; + + if (handler != RT_NULL) + { +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); +#endif /* RT_USING_INTERRUPT_INFO */ + isr_table[vector].handler = handler; + isr_table[vector].param = param; + } + } + + return old_handler; +} + +#ifdef RT_USING_SMP +void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) +{ + __DSB(); + if(cpu_mask & 0x1) + { + send_ipi_msg(0, ipi_vector); + } + if(cpu_mask & 0x2) + { + send_ipi_msg(1, ipi_vector); + } + if(cpu_mask & 0x4) + { + send_ipi_msg(2, ipi_vector); + } + if(cpu_mask & 0x8) + { + send_ipi_msg(3, ipi_vector); + } + __DSB(); +} +#endif + +#ifdef RT_USING_SMP +void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler) +{ + /* note: ipi_vector maybe different with irq_vector */ + rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER"); +} +#endif diff --git a/libcpu/aarch64/cortex-a53/interrupt.h b/libcpu/aarch64/cortex-a53/interrupt.h new file mode 100644 index 0000000000..8e741ed4e6 --- /dev/null +++ b/libcpu/aarch64/cortex-a53/interrupt.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-16 bigmagic first version + */ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#include <rthw.h> +#include <board.h> + +#include "raspi.h" + +#define INT_IRQ 0x00 +#define INT_FIQ 0x01 + +void rt_hw_interrupt_init(void); +void rt_hw_interrupt_mask(int vector); +void rt_hw_interrupt_umask(int vector); + +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name); + +#endif diff --git a/libcpu/aarch64/cortex-a53/stack.c b/libcpu/aarch64/cortex-a53/stack.c new file mode 100644 index 0000000000..68222c2c67 --- /dev/null +++ b/libcpu/aarch64/cortex-a53/stack.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-09-23 Bernard the first version + * 2011-10-05 Bernard add thumb mode + */ +#include <rtthread.h> +#include <board.h> + +#include <armv8.h> + +#define INITIAL_SPSR_EL3 (PSTATE_EL3 | SP_EL0) +#define INITIAL_SPSR_EL2 (PSTATE_EL2 | SP_EL0) +#define INITIAL_SPSR_EL1 (PSTATE_EL1 | SP_EL0) + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + rt_ubase_t *stk; + rt_ubase_t current_el; + + stk = (rt_ubase_t*)stack_addr; + + *(--stk) = ( rt_ubase_t ) 11; /* X1 */ + *(--stk) = ( rt_ubase_t ) parameter; /* X0 */ + *(--stk) = ( rt_ubase_t ) 33; /* X3 */ + *(--stk) = ( rt_ubase_t ) 22; /* X2 */ + *(--stk) = ( rt_ubase_t ) 55; /* X5 */ + *(--stk) = ( rt_ubase_t ) 44; /* X4 */ + *(--stk) = ( rt_ubase_t ) 77; /* X7 */ + *(--stk) = ( rt_ubase_t ) 66; /* X6 */ + *(--stk) = ( rt_ubase_t ) 99; /* X9 */ + *(--stk) = ( rt_ubase_t ) 88; /* X8 */ + *(--stk) = ( rt_ubase_t ) 11; /* X11 */ + *(--stk) = ( rt_ubase_t ) 10; /* X10 */ + *(--stk) = ( rt_ubase_t ) 13; /* X13 */ + *(--stk) = ( rt_ubase_t ) 12; /* X12 */ + *(--stk) = ( rt_ubase_t ) 15; /* X15 */ + *(--stk) = ( rt_ubase_t ) 14; /* X14 */ + *(--stk) = ( rt_ubase_t ) 17; /* X17 */ + *(--stk) = ( rt_ubase_t ) 16; /* X16 */ + *(--stk) = ( rt_ubase_t ) 19; /* X19 */ + *(--stk) = ( rt_ubase_t ) 18; /* X18 */ + *(--stk) = ( rt_ubase_t ) 21; /* X21 */ + *(--stk) = ( rt_ubase_t ) 20; /* X20 */ + *(--stk) = ( rt_ubase_t ) 23; /* X23 */ + *(--stk) = ( rt_ubase_t ) 22; /* X22 */ + *(--stk) = ( rt_ubase_t ) 25; /* X25 */ + *(--stk) = ( rt_ubase_t ) 24; /* X24 */ + *(--stk) = ( rt_ubase_t ) 27; /* X27 */ + *(--stk) = ( rt_ubase_t ) 26; /* X26 */ + *(--stk) = ( rt_ubase_t ) 29; /* X29 */ + *(--stk) = ( rt_ubase_t ) 28; /* X28 */ + *(--stk) = ( rt_ubase_t ) 0; /* XZR - has no effect, used so there are an even number of registers. */ + *(--stk) = ( rt_ubase_t ) texit; /* X30 - procedure call link register. */ + + current_el = rt_hw_get_current_el(); + + if(current_el == 3) + { + *(--stk) = INITIAL_SPSR_EL3; + } + else if(current_el == 2) + { + *(--stk) = INITIAL_SPSR_EL2; + } + else + { + *(--stk) = INITIAL_SPSR_EL1; + } + + *(--stk) = ( rt_ubase_t ) tentry; /* Exception return address. */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} diff --git a/libcpu/aarch64/cortex-a53/trap.c b/libcpu/aarch64/cortex-a53/trap.c new file mode 100644 index 0000000000..41d4d620f6 --- /dev/null +++ b/libcpu/aarch64/cortex-a53/trap.c @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Date Author Notes + * 2018-10-06 ZhaoXiaowei the first version + */ + +#include <rtthread.h> +#include <rthw.h> + +#include "interrupt.h" +#include "armv8.h" + +extern struct rt_thread *rt_current_thread; +#ifdef RT_USING_FINSH +extern long list_thread(void); +#endif + +/** + * this function will show registers of CPU + * + * @param regs the registers point + */ +void rt_hw_show_register(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3); + rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7); + rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11); + rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15); + rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19); + rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23); + rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27); + rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30); + rt_kprintf("spsr:0x%16.16lx\n", regs->spsr); + rt_kprintf("return pc:0x%16.16lx\n", regs->pc); +} + +/** + * When comes across an instruction which it cannot handle, + * it takes the undefined instruction trap. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_error(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("error exception:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +#define GIC_ACK_INTID_MASK (0x000003ff) +#define CORE0_IRQ_SOURCE (0x40000060) + +void rt_hw_trap_irq(void) +{ + void *param; + uint32_t irq; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + uint32_t value = 0; + value = IRQ_PEND_BASIC & 0x3ff; +#ifdef BSP_USING_CORETIMER + uint32_t int_source = HWREG32(CORE0_IRQ_SOURCE) & 0x3ff; + if (int_source & 0x02) + { + isr_func = isr_table[IRQ_ARM_TIMER].handler; + #ifdef RT_USING_INTERRUPT_INFO + isr_table[IRQ_ARM_TIMER].counter++; + #endif + if (isr_func) + { + param = isr_table[IRQ_ARM_TIMER].param; + isr_func(IRQ_ARM_TIMER, param); + } + } +#endif + /* local interrupt*/ + if (value) + { + if (value & (1 << 8)) + { + value = IRQ_PEND1; + irq = __rt_ffs(value) - 1; + } + else if (value & (1 << 9)) + { + value = IRQ_PEND2; + irq = __rt_ffs(value) + 31; + } + else + { + value &= 0x0f; + irq = __rt_ffs(value) + 63; + } + + /* get interrupt service routine */ + isr_func = isr_table[irq].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[irq].counter++; +#endif + if (isr_func) + { + /* Interrupt for myself. */ + param = isr_table[irq].param; + /* turn to interrupt service routine */ + isr_func(irq, param); + } + } +} + +void rt_hw_trap_fiq(void) +{ + void *param; + uint32_t irq; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + uint32_t value = 0; + value = IRQ_PEND_BASIC & 0x3ff; +#ifdef RT_USING_SMP + uint32_t mailbox_data; + uint32_t cpu_id = rt_hw_cpu_id(); + uint32_t int_source = CORE_IRQSOURCE(cpu_id); + mailbox_data = IPI_MAILBOX_CLEAR(cpu_id); + if (int_source & 0x0f) + { + if (int_source & 0x08) + { + isr_func = isr_table[IRQ_ARM_TIMER].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[IRQ_ARM_TIMER].counter++; +#endif + if (isr_func) + { + param = isr_table[IRQ_ARM_TIMER].param; + isr_func(IRQ_ARM_TIMER, param); + } + } + } + if (int_source & 0xf0) + { + /*it's a ipi interrupt*/ + if (mailbox_data & 0x1) + { + /* clear mailbox */ + IPI_MAILBOX_CLEAR(cpu_id) = mailbox_data; + isr_func = isr_table[IRQ_ARM_MAILBOX].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[IRQ_ARM_MAILBOX].counter++; +#endif + if (isr_func) + { + param = isr_table[IRQ_ARM_MAILBOX].param; + isr_func(IRQ_ARM_MAILBOX, param); + } + } + else + CORE_MAILBOX3_CLEAR(cpu_id) = mailbox_data; + } +#endif + /* local interrupt*/ + if (value) + { + if (value & (1 << 8)) + { + value = IRQ_PEND1; + irq = __rt_ffs(value) - 1; + } + else if (value & (1 << 9)) + { + value = IRQ_PEND2; + irq = __rt_ffs(value) + 31; + } + else + { + value &= 0x0f; + irq = __rt_ffs(value) + 63; + } + + /* get interrupt service routine */ + isr_func = isr_table[irq].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[irq].counter++; +#endif + if (irq > 1) + rt_kprintf("interrupt fiq %d\n", irq); + if (isr_func) + { + /* Interrupt for myself. */ + param = isr_table[irq].param; + /* turn to interrupt service routine */ + isr_func(irq, param); + } + } +} diff --git a/libcpu/aarch64/cortex-a72/SConscript b/libcpu/aarch64/cortex-a72/SConscript new file mode 100644 index 0000000000..c6a4817802 --- /dev/null +++ b/libcpu/aarch64/cortex-a72/SConscript @@ -0,0 +1,13 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*.S') +CPPPATH = [cwd] + +group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/aarch64/cortex-a72/entry_point.S b/libcpu/aarch64/cortex-a72/entry_point.S new file mode 100644 index 0000000000..6d2c69226b --- /dev/null +++ b/libcpu/aarch64/cortex-a72/entry_point.S @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Date Author Notes + * 2020-01-15 bigmagic the first version + */ + +.section ".text.entrypoint" + +.set EL1_stack, __el1_stack + +.global _start + +// This symbol is set to 0x80000 in ld script. That is the address that raspi3's firmware +// loads 'kernel8.img' file in. +_start: + // read cpu id, stop slave cores + mrs x1, mpidr_el1 // MPIDR_EL1: Multi-Processor Affinity Register + and x1, x1, #3 + cbz x1, .L__cpu_0 // .L prefix is the local label in ELF + + // cpu id > 0, stop + // cpu id == 0 will also goto here after returned from entry() if possible +.L__current_cpu_idle: + wfe + b .L__current_cpu_idle + +.L__cpu_0: // cpu id == 0 + + // set stack before our code + + /* Define stack pointer for current exception level */ + // ldr x2, =EL1_stack + // mov sp, x2 + + ldr x1, =_start + + // set up EL1 + mrs x0, CurrentEL // CurrentEL Register. bit 2, 3. Others reserved + and x0, x0, #12 // clear reserved bits + + // running at EL3? + cmp x0, #12 // 1100b. So, EL3 + bne .L__not_in_el3 // 11? !EL3 -> 5: + + // should never be executed, just for completeness. (EL3) + mov x2, #0x5b1 + msr scr_el3, x2 // SCR_ELn Secure Configuration Register + mov x2, #0x3c9 + msr spsr_el3, x2 // SPSR_ELn. Saved Program Status Register. 1111001001 + adr x2, .L__not_in_el3 + msr elr_el3, x2 + eret // Exception Return: from EL3, continue from .L__not_in_el3 + + // running at EL2 or EL1 +.L__not_in_el3: + cmp x0, #4 // 0x04 0100 EL1 + beq .L__in_el1 // EL1 -> 5: + + // in EL2 + msr sp_el1, x1 // Set sp of EL1 to _start + + // enable CNTP for EL1 + mrs x0, cnthctl_el2 // Counter-timer Hypervisor Control register + orr x0, x0, #3 + msr cnthctl_el2, x0 + msr cntvoff_el2, xzr + + // enable AArch64 in EL1 + mov x0, #(1 << 31) // AArch64 + orr x0, x0, #(1 << 1) // SWIO hardwired on Pi3 + msr hcr_el2, x0 + mrs x0, hcr_el2 + + // change execution level to EL1 + mov x2, #0x3c4 + msr spsr_el2, x2 // 1111000100 + adr x2, .L__in_el1 + msr elr_el2, x2 + eret // exception return. from EL2. continue from .L__in_el1 + +.L__in_el1: + mov sp, x1 // in EL1. Set sp to _start + + // Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction + mov x1, #0x00300000 // Don't trap any SIMD/FP instructions in both EL0 and EL1 + msr cpacr_el1, x1 + + mrs x1, sctlr_el1 + orr x1, x1, #(1 << 12) + bic x1, x1, #(3 << 3) + bic x1, x1, #(1 << 1) + msr sctlr_el1, x1 + + // clear bss + ldr x1, =__bss_start + ldr w2, =__bss_size + +.L__clean_bss_loop: + cbz w2, .L__jump_to_entry + str xzr, [x1], #8 + sub w2, w2, #1 + cbnz w2, .L__clean_bss_loop + + // jump to C code, should not return +.L__jump_to_entry: + bl entry + // for failsafe, halt this core too + b .L__current_cpu_idle diff --git a/libcpu/aarch64/cortex-a72/interrupt.c b/libcpu/aarch64/cortex-a72/interrupt.c new file mode 100644 index 0000000000..3b689dceb3 --- /dev/null +++ b/libcpu/aarch64/cortex-a72/interrupt.c @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-16 bigmagic first version + */ + +#include <rthw.h> +#include <rtthread.h> +#include <gic_pl400.h> +#include <board.h> +#include <armv8.h> + +#define MAX_HANDLERS 256 +#define GIC_ACK_INTID_MASK 0x000003ff + +#ifdef RT_USING_SMP +#define rt_interrupt_nest rt_cpu_self()->irq_nest +#else +extern volatile rt_uint8_t rt_interrupt_nest; +#endif + +extern int system_vectors; + +/* exception and interrupt handler table */ +struct rt_irq_desc isr_table[MAX_HANDLERS]; + +rt_ubase_t rt_interrupt_from_thread; +rt_ubase_t rt_interrupt_to_thread; +rt_ubase_t rt_thread_switch_interrupt_flag; + +void rt_hw_vector_init(void) +{ + rt_hw_set_current_vbar((rt_ubase_t)&system_vectors); // cpu_gcc.S +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + + rt_uint32_t gic_cpu_base = 0; + rt_uint32_t gic_dist_base = 0; + + /* initialize ARM GIC */ + gic_dist_base = GIC_PL400_DISTRIBUTOR_PPTR; + gic_cpu_base = GIC_PL400_CONTROLLER_PPTR; + arm_gic_dist_init(0, gic_dist_base, 0); + arm_gic_cpu_init(0, gic_cpu_base); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if (vector < MAX_HANDLERS) + { + old_handler = isr_table[vector].handler; + + if (handler != RT_NULL) + { +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); +#endif /* RT_USING_INTERRUPT_INFO */ + isr_table[vector].handler = handler; + isr_table[vector].param = param; + } + } + + return old_handler; +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + arm_gic_mask(0, vector); +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + arm_gic_umask(0, vector); +} + +/** + * This function returns the active interrupt number. + * @param none + */ +int rt_hw_interrupt_get_irq(void) +{ + return arm_gic_get_active_irq(0) & GIC_ACK_INTID_MASK; +} + +/** + * This function acknowledges the interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_ack(int vector) +{ + arm_gic_ack(0, vector); +} diff --git a/libcpu/aarch64/cortex-a72/interrupt.h b/libcpu/aarch64/cortex-a72/interrupt.h new file mode 100644 index 0000000000..0d2d4867c7 --- /dev/null +++ b/libcpu/aarch64/cortex-a72/interrupt.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-16 bigmagic first version + */ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#include <rthw.h> +#include <board.h> + +#define INT_IRQ 0x00 +#define INT_FIQ 0x01 + +void rt_hw_interrupt_init(void); +void rt_hw_interrupt_mask(int vector); +void rt_hw_interrupt_umask(int vector); + +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name); + +#endif diff --git a/libcpu/aarch64/cortex-a72/stack.c b/libcpu/aarch64/cortex-a72/stack.c new file mode 100644 index 0000000000..68222c2c67 --- /dev/null +++ b/libcpu/aarch64/cortex-a72/stack.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-09-23 Bernard the first version + * 2011-10-05 Bernard add thumb mode + */ +#include <rtthread.h> +#include <board.h> + +#include <armv8.h> + +#define INITIAL_SPSR_EL3 (PSTATE_EL3 | SP_EL0) +#define INITIAL_SPSR_EL2 (PSTATE_EL2 | SP_EL0) +#define INITIAL_SPSR_EL1 (PSTATE_EL1 | SP_EL0) + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + rt_ubase_t *stk; + rt_ubase_t current_el; + + stk = (rt_ubase_t*)stack_addr; + + *(--stk) = ( rt_ubase_t ) 11; /* X1 */ + *(--stk) = ( rt_ubase_t ) parameter; /* X0 */ + *(--stk) = ( rt_ubase_t ) 33; /* X3 */ + *(--stk) = ( rt_ubase_t ) 22; /* X2 */ + *(--stk) = ( rt_ubase_t ) 55; /* X5 */ + *(--stk) = ( rt_ubase_t ) 44; /* X4 */ + *(--stk) = ( rt_ubase_t ) 77; /* X7 */ + *(--stk) = ( rt_ubase_t ) 66; /* X6 */ + *(--stk) = ( rt_ubase_t ) 99; /* X9 */ + *(--stk) = ( rt_ubase_t ) 88; /* X8 */ + *(--stk) = ( rt_ubase_t ) 11; /* X11 */ + *(--stk) = ( rt_ubase_t ) 10; /* X10 */ + *(--stk) = ( rt_ubase_t ) 13; /* X13 */ + *(--stk) = ( rt_ubase_t ) 12; /* X12 */ + *(--stk) = ( rt_ubase_t ) 15; /* X15 */ + *(--stk) = ( rt_ubase_t ) 14; /* X14 */ + *(--stk) = ( rt_ubase_t ) 17; /* X17 */ + *(--stk) = ( rt_ubase_t ) 16; /* X16 */ + *(--stk) = ( rt_ubase_t ) 19; /* X19 */ + *(--stk) = ( rt_ubase_t ) 18; /* X18 */ + *(--stk) = ( rt_ubase_t ) 21; /* X21 */ + *(--stk) = ( rt_ubase_t ) 20; /* X20 */ + *(--stk) = ( rt_ubase_t ) 23; /* X23 */ + *(--stk) = ( rt_ubase_t ) 22; /* X22 */ + *(--stk) = ( rt_ubase_t ) 25; /* X25 */ + *(--stk) = ( rt_ubase_t ) 24; /* X24 */ + *(--stk) = ( rt_ubase_t ) 27; /* X27 */ + *(--stk) = ( rt_ubase_t ) 26; /* X26 */ + *(--stk) = ( rt_ubase_t ) 29; /* X29 */ + *(--stk) = ( rt_ubase_t ) 28; /* X28 */ + *(--stk) = ( rt_ubase_t ) 0; /* XZR - has no effect, used so there are an even number of registers. */ + *(--stk) = ( rt_ubase_t ) texit; /* X30 - procedure call link register. */ + + current_el = rt_hw_get_current_el(); + + if(current_el == 3) + { + *(--stk) = INITIAL_SPSR_EL3; + } + else if(current_el == 2) + { + *(--stk) = INITIAL_SPSR_EL2; + } + else + { + *(--stk) = INITIAL_SPSR_EL1; + } + + *(--stk) = ( rt_ubase_t ) tentry; /* Exception return address. */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} diff --git a/libcpu/aarch64/cortex-a72/trap.c b/libcpu/aarch64/cortex-a72/trap.c new file mode 100644 index 0000000000..d93aa18fd6 --- /dev/null +++ b/libcpu/aarch64/cortex-a72/trap.c @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Date Author Notes + * 2018-10-06 ZhaoXiaowei the first version + */ + +#include <rtthread.h> +#include <rthw.h> + +#include "interrupt.h" +#include "armv8.h" + +extern struct rt_thread *rt_current_thread; +#ifdef RT_USING_FINSH +extern long list_thread(void); +#endif + +/** + * this function will show registers of CPU + * + * @param regs the registers point + */ +void rt_hw_show_register(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3); + rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7); + rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11); + rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15); + rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19); + rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23); + rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27); + rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30); + rt_kprintf("spsr:0x%16.16lx\n", regs->spsr); + rt_kprintf("return pc:0x%16.16lx\n", regs->pc); +} + +/** + * When comes across an instruction which it cannot handle, + * it takes the undefined instruction trap. + * + * @param regs system registers + * + * @note never invoke this function in application + */ +void rt_hw_trap_error(struct rt_hw_exp_stack *regs) +{ + rt_kprintf("error exception:\n"); + rt_hw_show_register(regs); +#ifdef RT_USING_FINSH + list_thread(); +#endif + rt_hw_cpu_shutdown(); +} + +#define GIC_ACK_INTID_MASK 0x000003ff + +int rt_hw_interrupt_get_irq(void); +void rt_hw_interrupt_ack(int fiq_irq); + +void rt_hw_trap_irq(void) +{ + void *param; + int ir; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + + ir = rt_hw_interrupt_get_irq(); + if (ir == 1023) + { + /* Spurious interrupt */ + return; + } + + /* get interrupt service routine */ + isr_func = isr_table[ir].handler; +#ifdef RT_USING_INTERRUPT_INFO + isr_table[ir].counter++; +#endif + if (isr_func) + { + /* Interrupt for myself. */ + param = isr_table[ir].param; + /* turn to interrupt service routine */ + isr_func(ir, param); + } + + /* end of interrupt */ + rt_hw_interrupt_ack(ir); + +} + +void rt_hw_trap_fiq(void) +{ +} diff --git a/libcpu/arc/SConscript b/libcpu/arc/SConscript new file mode 100644 index 0000000000..3c69b578fa --- /dev/null +++ b/libcpu/arc/SConscript @@ -0,0 +1,17 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +group = [] + +# add common code files +group = group + SConscript(os.path.join('common', 'SConscript')) + +# cpu porting code files +group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) + +Return('group') diff --git a/libcpu/arc/common/SConscript b/libcpu/arc/common/SConscript new file mode 100644 index 0000000000..1c77347e61 --- /dev/null +++ b/libcpu/arc/common/SConscript @@ -0,0 +1,10 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + + +group = DefineGroup('cpu', src, depend = [], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arc/em/SConscript b/libcpu/arc/em/SConscript new file mode 100644 index 0000000000..ff1d8c134d --- /dev/null +++ b/libcpu/arc/em/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +src += Glob('*.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arc/em/contex_gcc_mw.S b/libcpu/arc/em/contex_gcc_mw.S new file mode 100644 index 0000000000..81b291c1c8 --- /dev/null +++ b/libcpu/arc/em/contex_gcc_mw.S @@ -0,0 +1,364 @@ +/* + * Copyright (c) 2018, Synopsys, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#define __ASSEMBLY__ +#include "include/arc/arc.h" +#include "include/arc/arc_asm_common.h" + +.global rt_interrupt_enter; +.global rt_interrupt_leave; +.global context_switch_reqflg; +.global rt_interrupt_from_thread; +.global rt_interrupt_to_thread; +.global exc_nest_count; +.global set_hw_stack_check; + + .text + .align 4 +dispatcher: + st sp, [r0] + ld sp, [r1] +#if ARC_FEATURE_STACK_CHECK +#if ARC_FEATURE_SEC_PRESENT + lr r0, [AUX_SEC_STAT] + bclr r0, r0, AUX_SEC_STAT_BIT_SSC + sflag r0 +#else + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_SC + kflag r0 +#endif + jl set_hw_stack_check +#if ARC_FEATURE_SEC_PRESENT + lr r0, [AUX_SEC_STAT] + bset r0, r0, AUX_SEC_STAT_BIT_SSC + sflag r0 +#else + lr r0, [AUX_STATUS32] + bset r0, r0, AUX_STATUS_BIT_SC + kflag r0 +#endif +#endif + pop r0 + j [r0] + +/* return routine when task dispatch happened in task context */ +dispatch_r: + RESTORE_NONSCRATCH_REGS + j [blink] + +/* + * rt_base_t rt_hw_interrupt_disable(); + */ + .global rt_hw_interrupt_disable + .align 4 +rt_hw_interrupt_disable: + clri r0 + j [blink] + + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ + .global rt_hw_interrupt_enable + .align 4 +rt_hw_interrupt_enable: + seti r0 + j [blink] + + + .global rt_hw_context_switch_interrupt + .align 4 +rt_hw_context_switch_interrupt: + st r0, [rt_interrupt_from_thread] + st r1, [rt_interrupt_to_thread] + mov r0, 1 + st r0, [context_switch_reqflg] + j [blink] + + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * r0 --> from + * r1 --> to + */ + .global rt_hw_context_switch + .align 4 +rt_hw_context_switch: + SAVE_NONSCRATCH_REGS + mov r2, dispatch_r + push r2 + b dispatcher + + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * r0 --> to + */ + .global rt_hw_context_switch_to + .align 4 +rt_hw_context_switch_to: + ld sp, [r0] +#if ARC_FEATURE_STACK_CHECK + mov r1, r0 +#if ARC_FEATURE_SEC_PRESENT + lr r0, [AUX_SEC_STAT] + bclr r0, r0, AUX_SEC_STAT_BIT_SSC + sflag r0 +#else + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_SC + kflag r0 +#endif + jl set_hw_stack_check +#if ARC_FEATURE_SEC_PRESENT + lr r0, [AUX_SEC_STAT] + bset r0, r0, AUX_SEC_STAT_BIT_SSC + sflag r0 +#else + lr r0, [AUX_STATUS32] + bset r0, r0, AUX_STATUS_BIT_SC + kflag r0 +#endif +#endif + pop r0 + j [r0] + + .global start_r + .align 4 +start_r: + pop blink; + pop r1 + pop r2 + pop r0 + + j_s.d [r1] + kflag r2 + +/* + * int __rt_ffs(int value); + * r0 --> value + */ + .global __rt_ffs + .align 4 +__rt_ffs: + breq r0, 0, __rt_ffs_return + ffs r1, r0 + add r0, r1, 1 +__rt_ffs_return: + j [blink] + +/****** exceptions and interrupts handing ******/ +/****** entry for exception handling ******/ + .global exc_entry_cpu + .align 4 +exc_entry_cpu: + + EXCEPTION_PROLOGUE + + mov blink, sp + mov r3, sp /* as exception handler's para(p_excinfo) */ + + ld r0, [exc_nest_count] + add r1, r0, 1 + st r1, [exc_nest_count] + brne r0, 0, exc_handler_1 +/* change to exception stack if interrupt happened in task context */ + mov sp, _e_stack +exc_handler_1: + PUSH blink + + lr r0, [AUX_ECR] + lsr r0, r0, 16 + mov r1, exc_int_handler_table + ld.as r2, [r1, r0] + + mov r0, r3 + jl [r2] + +/* interrupts are not allowed */ +ret_exc: + POP sp + mov r1, exc_nest_count + ld r0, [r1] + sub r0, r0, 1 + st r0, [r1] + brne r0, 0, ret_exc_1 /* nest exception case */ + lr r1, [AUX_IRQ_ACT] /* nest interrupt case */ + brne r1, 0, ret_exc_1 + + ld r0, [context_switch_reqflg] + brne r0, 0, ret_exc_2 +ret_exc_1: /* return from non-task context, interrupts or exceptions are nested */ + EXCEPTION_EPILOGUE + rtie + +/* there is a dispatch request */ +ret_exc_2: + /* clear dispatch request */ + mov r0, 0 + st r0, [context_switch_reqflg] + + SAVE_CALLEE_REGS /* save callee save registers */ + + /* clear exception bit to do exception exit by SW */ + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_AE + kflag r0 + + mov r1, ret_exc_r /* save return address */ + PUSH r1 + + ld r0, [rt_interrupt_from_thread] + ld r1, [rt_interrupt_to_thread] + b dispatcher + +ret_exc_r: + /* recover exception status */ + lr r0, [AUX_STATUS32] + bset r0, r0, AUX_STATUS_BIT_AE + kflag r0 + + RESTORE_CALLEE_REGS + EXCEPTION_EPILOGUE + rtie + +/****** entry for normal interrupt exception handling ******/ + .global exc_entry_int /* entry for interrupt handling */ + .align 4 +exc_entry_int: +#if ARC_FEATURE_FIRQ == 1 +/* check whether it is P0 interrupt */ +#if ARC_FEATURE_RGF_NUM_BANKS > 1 + lr r0, [AUX_IRQ_ACT] + btst r0, 0 + jnz exc_entry_firq +#else + PUSH r10 + lr r10, [AUX_IRQ_ACT] + btst r10, 0 + POP r10 + jnz exc_entry_firq +#endif +#endif + INTERRUPT_PROLOGUE + + mov blink, sp + + clri /* disable interrupt */ + ld r3, [exc_nest_count] + add r2, r3, 1 + st r2, [exc_nest_count] + seti /* enable higher priority interrupt */ + + brne r3, 0, irq_handler_1 +/* change to exception stack if interrupt happened in task context */ + mov sp, _e_stack +#if ARC_FEATURE_STACK_CHECK +#if ARC_FEATURE_SEC_PRESENT + lr r0, [AUX_SEC_STAT] + bclr r0, r0, AUX_SEC_STAT_BIT_SSC + sflag r0 +#else + lr r0, [AUX_STATUS32] + bclr r0, r0, AUX_STATUS_BIT_SC + kflag r0 +#endif +#endif +irq_handler_1: + PUSH blink + + jl rt_interrupt_enter + + lr r0, [AUX_IRQ_CAUSE] + sr r0, [AUX_IRQ_SELECT] + mov r1, exc_int_handler_table + ld.as r2, [r1, r0] /* r2 = exc_int_handler_table + irqno *4 */ +/* handle software triggered interrupt */ + lr r3, [AUX_IRQ_HINT] + cmp r3, r0 + bne.d irq_hint_handled + xor r3, r3, r3 + sr r3, [AUX_IRQ_HINT] +irq_hint_handled: + lr r3, [AUX_IRQ_PRIORITY] + PUSH r3 /* save irq priority */ + + jl [r2] /* jump to interrupt handler */ + jl rt_interrupt_leave +ret_int: + clri /* disable interrupt */ + POP r3 /* irq priority */ + POP sp + mov r1, exc_nest_count + ld r0, [r1] + sub r0, r0, 1 + st r0, [r1] +/* if there are multi-bits set in IRQ_ACT, it's still in nest interrupt */ + lr r0, [AUX_IRQ_CAUSE] + sr r0, [AUX_IRQ_SELECT] + lr r3, [AUX_IRQ_PRIORITY] + lr r1, [AUX_IRQ_ACT] + bclr r2, r1, r3 + brne r2, 0, ret_int_1 + + ld r0, [context_switch_reqflg] + brne r0, 0, ret_int_2 +ret_int_1: /* return from non-task context */ + INTERRUPT_EPILOGUE + rtie +/* there is a dispatch request */ +ret_int_2: + /* clear dispatch request */ + mov r0, 0 + st r0, [context_switch_reqflg] + + /* interrupt return by SW */ + lr r10, [AUX_IRQ_ACT] + PUSH r10 + bclr r10, r10, r3 /* clear related bits in IRQ_ACT */ + sr r10, [AUX_IRQ_ACT] + + SAVE_CALLEE_REGS /* save callee save registers */ + mov r1, ret_int_r /* save return address */ + PUSH r1 + + ld r0, [rt_interrupt_from_thread] + ld r1, [rt_interrupt_to_thread] + b dispatcher + +ret_int_r: + RESTORE_CALLEE_REGS + /* recover AUX_IRQ_ACT to restore the interrup status */ + POPAX AUX_IRQ_ACT + INTERRUPT_EPILOGUE + rtie + +/****** entry for fast irq exception handling ******/ + .global exc_entry_firq + .weak exc_entry_firq + .align 4 +exc_entry_firq: + SAVE_FIQ_EXC_REGS + + lr r0, [AUX_IRQ_CAUSE] + mov r1, exc_int_handler_table +/* r2 = _kernel_exc_tbl + irqno *4 */ + ld.as r2, [r1, r0] + +/* for the case of software triggered interrupt */ + lr r3, [AUX_IRQ_HINT] + cmp r3, r0 + bne.d firq_hint_handled + xor r3, r3, r3 + sr r3, [AUX_IRQ_HINT] +firq_hint_handled: +/* jump to interrupt handler */ + mov r0, sp + jl [r2] + +firq_return: + RESTORE_FIQ_EXC_REGS + rtie diff --git a/libcpu/arc/em/cpuport.c b/libcpu/arc/em/cpuport.c new file mode 100644 index 0000000000..34f538881f --- /dev/null +++ b/libcpu/arc/em/cpuport.c @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2018, Synopsys, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include <rtthread.h> + +#include "arc/arc_exception.h" + +#if ARC_FEATURE_STACK_CHECK +#define ARC_INIT_STATUS ((1 << AUX_STATUS_BIT_SC) | AUX_STATUS_MASK_IE | ((-1 - INT_PRI_MIN) << 1) | STATUS32_RESET_VALUE) +#else +#define ARC_INIT_STATUS (AUX_STATUS_MASK_IE | ((-1 - INT_PRI_MIN) << 1) | STATUS32_RESET_VALUE) +#endif + +extern void start_r(void); + + +rt_uint32_t context_switch_reqflg; +rt_uint32_t rt_interrupt_from_thread; +rt_uint32_t rt_interrupt_to_thread; +rt_uint32_t exc_nest_count; + +struct init_stack_frame { + rt_uint32_t pc; + rt_uint32_t blink; + rt_uint32_t task; + rt_uint32_t status32; + rt_uint32_t r0; +}; + +/** + * shutdown CPU + */ +void rt_hw_cpu_shutdown(void) +{ + +} + +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) +{ + struct init_stack_frame *stack_frame; + rt_uint8_t *stk; + + stk = stack_addr + sizeof(rt_uint32_t); + stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8); + stk -= sizeof(struct init_stack_frame); + + stack_frame = (struct init_stack_frame *)stk; + + stack_frame->pc = (rt_uint32_t)start_r; + stack_frame->blink = (rt_uint32_t)texit; + stack_frame->task = (rt_uint32_t)tentry; + stack_frame->status32 = ARC_INIT_STATUS; + stack_frame->r0 = (rt_uint32_t)parameter; + + return stk; +} + + +/** + * This function set the hook, which is invoked on fault exception handling. + * + * @param exception_handle the exception handling hook function. + */ +void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context)) +{ + exception_handle = exception_handle; +} + +void set_hw_stack_check(rt_uint32_t *from, rt_uint32_t *to) +{ + struct rt_thread *rt_thread_to; + if (to != NULL) { + rt_thread_to = rt_container_of(to, struct rt_thread, sp); +#if ARC_FEATURE_SEC_PRESENT + arc_aux_write(AUX_S_KSTACK_TOP, (uint32_t)(rt_thread_to->stack_addr)); + arc_aux_write(AUX_S_KSTACK_BASE, (uint32_t)(rt_thread_to->stack_addr)+rt_thread_to->stack_size); +#else + arc_aux_write(AUX_KSTACK_TOP, (uint32_t)(rt_thread_to->stack_addr)); + arc_aux_write(AUX_KSTACK_BASE, (uint32_t)(rt_thread_to->stack_addr)+rt_thread_to->stack_size); +#endif + } +} diff --git a/libcpu/arm/AT91SAM7S/SConscript b/libcpu/arm/AT91SAM7S/SConscript new file mode 100644 index 0000000000..9ff30a796b --- /dev/null +++ b/libcpu/arm/AT91SAM7S/SConscript @@ -0,0 +1,23 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arm/AT91SAM7S/context_rvds.S b/libcpu/arm/AT91SAM7S/context_rvds.S index 641ec7a6b1..78e3df9736 100644 --- a/libcpu/arm/AT91SAM7S/context_rvds.S +++ b/libcpu/arm/AT91SAM7S/context_rvds.S @@ -1,43 +1,39 @@ -;/* -; * File : context_rvds.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006, RT-Thread Development Team -; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE -; * -; * Change Logs: -; * Date Author Notes -; * 2009-01-20 Bernard first version -; */ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-01-20 Bernard first version + */ NOINT EQU 0xc0 ; disable interrupt in psr - AREA |.text|, CODE, READONLY, ALIGN=2 - ARM - REQUIRE8 - PRESERVE8 + AREA |.text|, CODE, READONLY, ALIGN=2 + ARM + REQUIRE8 + PRESERVE8 ;/* ; * rt_base_t rt_hw_interrupt_disable(); ; */ rt_hw_interrupt_disable PROC - EXPORT rt_hw_interrupt_disable - MRS r0, cpsr - ORR r1, r0, #NOINT - MSR cpsr_c, r1 - BX lr - ENDP + EXPORT rt_hw_interrupt_disable + MRS r0, cpsr + ORR r1, r0, #NOINT + MSR cpsr_c, r1 + BX lr + ENDP ;/* ; * void rt_hw_interrupt_enable(rt_base_t level); ; */ rt_hw_interrupt_enable PROC - EXPORT rt_hw_interrupt_enable - MSR cpsr_c, r0 - BX lr - ENDP + EXPORT rt_hw_interrupt_enable + MSR cpsr_c, r0 + BX lr + ENDP ;/* ; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); @@ -45,63 +41,63 @@ rt_hw_interrupt_enable PROC ; * r1 --> to ; */ rt_hw_context_switch PROC - EXPORT rt_hw_context_switch - STMFD sp!, {lr} ; push pc (lr should be pushed in place of PC) - STMFD sp!, {r0-r12, lr} ; push lr & register file + EXPORT rt_hw_context_switch + STMFD sp!, {lr} ; push pc (lr should be pushed in place of PC) + STMFD sp!, {r0-r12, lr} ; push lr & register file - MRS r4, cpsr - STMFD sp!, {r4} ; push cpsr - MRS r4, spsr - STMFD sp!, {r4} ; push spsr + MRS r4, cpsr + STMFD sp!, {r4} ; push cpsr + MRS r4, spsr + STMFD sp!, {r4} ; push spsr - STR sp, [r0] ; store sp in preempted tasks TCB - LDR sp, [r1] ; get new task stack pointer + STR sp, [r0] ; store sp in preempted tasks TCB + LDR sp, [r1] ; get new task stack pointer - LDMFD sp!, {r4} ; pop new task spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task cpsr - MSR cpsr_cxsf, r4 + LDMFD sp!, {r4} ; pop new task spsr + MSR spsr_cxsf, r4 + LDMFD sp!, {r4} ; pop new task cpsr + MSR cpsr_cxsf, r4 - LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP + LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc + ENDP ;/* ; * void rt_hw_context_switch_to(rt_uint32 to); ; * r0 --> to ; */ rt_hw_context_switch_to PROC - EXPORT rt_hw_context_switch_to - LDR sp, [r0] ; get new task stack pointer + EXPORT rt_hw_context_switch_to + LDR sp, [r0] ; get new task stack pointer - LDMFD sp!, {r4} ; pop new task spsr - MSR spsr_cxsf, r4 - LDMFD sp!, {r4} ; pop new task cpsr - MSR cpsr_cxsf, r4 + LDMFD sp!, {r4} ; pop new task spsr + MSR spsr_cxsf, r4 + LDMFD sp!, {r4} ; pop new task cpsr + MSR cpsr_cxsf, r4 - LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc - ENDP + LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc + ENDP ;/* ; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); ; */ - IMPORT rt_thread_switch_interrupt_flag - IMPORT rt_interrupt_from_thread - IMPORT rt_interrupt_to_thread + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread rt_hw_context_switch_interrupt PROC - EXPORT rt_hw_context_switch_interrupt - LDR r2, =rt_thread_switch_interrupt_flag - LDR r3, [r2] - CMP r3, #1 - BEQ _reswitch - MOV r3, #1 ; set rt_thread_switch_interrupt_flag to 1 - STR r3, [r2] - LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread - STR r0, [r2] + EXPORT rt_hw_context_switch_interrupt + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 ; set rt_thread_switch_interrupt_flag to 1 + STR r3, [r2] + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] _reswitch - LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread - STR r1, [r2] - BX lr - ENDP + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + BX lr + ENDP - END
\ No newline at end of file + END
\ No newline at end of file diff --git a/libcpu/arm/AT91SAM7X/SConscript b/libcpu/arm/AT91SAM7X/SConscript new file mode 100644 index 0000000000..9ff30a796b --- /dev/null +++ b/libcpu/arm/AT91SAM7X/SConscript @@ -0,0 +1,23 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arm/AT91SAM7X/context_rvds.S b/libcpu/arm/AT91SAM7X/context_rvds.S index 641ec7a6b1..0d8bf56237 100644 --- a/libcpu/arm/AT91SAM7X/context_rvds.S +++ b/libcpu/arm/AT91SAM7X/context_rvds.S @@ -1,16 +1,12 @@ -;/* -; * File : context_rvds.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006, RT-Thread Development Team -; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE -; * -; * Change Logs: -; * Date Author Notes -; * 2009-01-20 Bernard first version -; */ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-01-20 Bernard first version + */ NOINT EQU 0xc0 ; disable interrupt in psr diff --git a/libcpu/arm/SConscript b/libcpu/arm/SConscript new file mode 100644 index 0000000000..f6ea13fb91 --- /dev/null +++ b/libcpu/arm/SConscript @@ -0,0 +1,16 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() + +# add common code files +group = SConscript(os.path.join('common', 'SConscript')) + +# cpu porting code files +group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) + +Return('group') diff --git a/libcpu/arm/am335x/SConscript b/libcpu/arm/am335x/SConscript new file mode 100644 index 0000000000..9ff30a796b --- /dev/null +++ b/libcpu/arm/am335x/SConscript @@ -0,0 +1,23 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arm/am335x/start_gcc.S b/libcpu/arm/am335x/start_gcc.S index 6b76fb04a4..7e996e2a80 100644 --- a/libcpu/arm/am335x/start_gcc.S +++ b/libcpu/arm/am335x/start_gcc.S @@ -33,6 +33,7 @@ .globl stack_start .globl stack_top +.align 3 stack_start: .rept ISR_Stack_Size .long 0 diff --git a/libcpu/arm/arm926/SConscript b/libcpu/arm/arm926/SConscript new file mode 100644 index 0000000000..00785a135b --- /dev/null +++ b/libcpu/arm/arm926/SConscript @@ -0,0 +1,25 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] +ASFLAGS = '' + +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + ASFLAGS = ' --cpreproc' + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/arm/arm926/context_gcc.S b/libcpu/arm/arm926/context_gcc.S index 5152618d24..f69aa9f5ba 100644 --- a/libcpu/arm/arm926/context_gcc.S +++ b/libcpu/arm/arm926/context_gcc.S @@ -1,21 +1,7 @@ ;/* -; * File : context_iar.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006, RT-Thread Development Team +; * Copyright (c) 2006-2018, RT-Thread Development Team ; * -; * This program is free software; you can redistribute it and/or modify -; * it under the terms of the GNU General Public License as published by -; * the Free Software Foundation; either version 2 of the License, or -; * (at your option) any later version. -; * -; * This program is distributed in the hope that it will be useful, -; * but WITHOUT ANY WARRANTY; without even the implied warranty of -; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; * GNU General Public License for more details. -; * -; * You should have received a copy of the GNU General Public License along -; * with this program; if not, write to the Free Software Foundation, Inc., -; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes @@ -24,6 +10,7 @@ #define NOINT 0xC0 +.text ;/* ; * rt_base_t rt_hw_interrupt_disable(); ; */ diff --git a/libcpu/arm/arm926/context_iar.S b/libcpu/arm/arm926/context_iar.S index 14110e5220..902552734e 100644 --- a/libcpu/arm/arm926/context_iar.S +++ b/libcpu/arm/arm926/context_iar.S @@ -1,27 +1,13 @@ -;/* -; * File : context_iar.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006, RT-Thread Development Team -; * -; * This program is free software; you can redistribute it and/or modify -; * it under the terms of the GNU General Public License as published by -; * the Free Software Foundation; either version 2 of the License, or -; * (at your option) any later version. -; * -; * This program is distributed in the hope that it will be useful, -; * but WITHOUT ANY WARRANTY; without even the implied warranty of -; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; * GNU General Public License for more details. -; * -; * You should have received a copy of the GNU General Public License along -; * with this program; if not, write to the Free Software Foundation, Inc., -; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -; * -; * Change Logs: -; * Date Author Notes -; * 2011-08-14 weety copy from mini2440 -; * 2015-04-15 ArdaFu convert from context_gcc.s -; */ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-08-14 weety copy from mini2440 + * 2015-04-15 ArdaFu convert from context_gcc.s + */ #define NOINT 0xc0 diff --git a/libcpu/arm/arm926/context_rvds.S b/libcpu/arm/arm926/context_rvds.S index 32bd235fef..03eff68d4c 100644 --- a/libcpu/arm/arm926/context_rvds.S +++ b/libcpu/arm/arm926/context_rvds.S @@ -1,24 +1,10 @@ ;/* -; * file : context_rvds.s -; * this file is part of rt-thread rtos -; * copyright (c) 2006, rt-thread development team +; * Copyright (c) 2006-2018, RT-Thread Development Team ; * -; * this program is free software; you can redistribute it and/or modify -; * it under the terms of the gnu general public license as published by -; * the free software foundation; either version 2 of the license, or -; * (at your option) any later version. +; * SPDX-License-Identifier: Apache-2.0 ; * -; * this program is distributed in the hope that it will be useful, -; * but without any warranty; without even the implied warranty of -; * merchantability or fitness for a particular purpose. see the -; * gnu general public license for more details. -; * -; * you should have received a copy of the gnu general public license along -; * with this program; if not, write to the free software foundation, inc., -; * 51 franklin street, fifth floor, boston, ma 02110-1301 usa. -; * -; * change logs: -; * date author notes +; * Change Logs: +; * Date Author Notes ; * 2011-08-14 weety copy from mini2440 ; */ diff --git a/libcpu/arm/arm926/cpuport.c b/libcpu/arm/arm926/cpuport.c index 1efb23e896..035e97d543 100644 --- a/libcpu/arm/arm926/cpuport.c +++ b/libcpu/arm/arm926/cpuport.c @@ -23,30 +23,30 @@ rt_inline rt_uint32_t cp15_rd(void) { rt_uint32_t i; - __asm volatile("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + __asm volatile("mrc p15, 0, %0, c1, c0, 0":"=r"(i)); return i; } rt_inline void cache_enable(rt_uint32_t bit) { __asm volatile(\ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + : "r"(bit) \ + : "memory"); } rt_inline void cache_disable(rt_uint32_t bit) { __asm volatile(\ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + : "r"(bit) \ + : "memory"); } #endif @@ -152,7 +152,7 @@ void rt_hw_cpu_reset() rt_kprintf("Restarting system...\n"); machine_reset(); - while(1); /* loop forever and wait for reset to happen */ + while (1); /* loop forever and wait for reset to happen */ /* NEVER REACHED */ } @@ -206,21 +206,7 @@ int __rt_ffs(int value) #elif defined(__GNUC__) || defined(__ICCARM__) int __rt_ffs(int value) { - register rt_uint32_t x; - - if (value == 0) - return value; - - __asm - ( - "rsb %[temp], %[val], #0\n" - "and %[temp], %[temp], %[val]\n" - "clz %[temp], %[temp]\n" - "rsb %[temp], %[temp], #32\n" - :[temp] "=r"(x) - :[val] "r"(value) - ); - return x; + return __builtin_ffs(value); } #endif diff --git a/libcpu/arm/arm926/machine.c b/libcpu/arm/arm926/machine.c new file mode 100644 index 0000000000..aa26d10ec6 --- /dev/null +++ b/libcpu/arm/arm926/machine.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-02-08 RT-Thread the first version + */ + +#include <rthw.h> +#include <rtthread.h> + +RT_WEAK void machine_reset(void) +{ + rt_kprintf("reboot system...\n"); + rt_hw_interrupt_disable(); + while (1); +} + +RT_WEAK void machine_shutdown(void) +{ + rt_kprintf("shutdown...\n"); + rt_hw_interrupt_disable(); + while (1); +} + diff --git a/libcpu/arm/arm926/mmu.c b/libcpu/arm/arm926/mmu.c index f1e475189b..19d70b9b0b 100644 --- a/libcpu/arm/arm926/mmu.c +++ b/libcpu/arm/arm926/mmu.c @@ -140,7 +140,7 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while(ptr < buffer + size) + while (ptr < buffer + size) { __asm volatile { MCR p15, 0, ptr, c7, c14, 1 } ptr += CACHE_LINE_SIZE; @@ -211,18 +211,18 @@ void mmu_setttbase(register rt_uint32_t i) * set by page table entry */ value = 0; - asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); + asm volatile("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); value = 0x55555555; - asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); + asm volatile("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); - asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); + asm volatile("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); } void mmu_set_domain(register rt_uint32_t i) { - asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); + asm volatile("mcr p15,0, %0, c3, c0, 0": :"r"(i)); } void mmu_enable() @@ -321,7 +321,7 @@ void mmu_disable_alignfault() void mmu_clean_invalidated_cache_index(int index) { - asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); + asm volatile("mcr p15, 0, %0, c7, c14, 2": :"r"(index)); } void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) @@ -330,9 +330,9 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while(ptr < buffer + size) + while (ptr < buffer + size) { - asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); + asm volatile("mcr p15, 0, %0, c7, c14, 1": :"r"(ptr)); ptr += CACHE_LINE_SIZE; } @@ -347,7 +347,7 @@ void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) while (ptr < buffer + size) { - asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); + asm volatile("mcr p15, 0, %0, c7, c10, 1": :"r"(ptr)); ptr += CACHE_LINE_SIZE; } @@ -361,7 +361,7 @@ void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) while (ptr < buffer + size) { - asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); + asm volatile("mcr p15, 0, %0, c7, c6, 1": :"r"(ptr)); ptr += CACHE_LINE_SIZE; } @@ -369,19 +369,19 @@ void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) void mmu_invalidate_tlb() { - asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); + asm volatile("mcr p15, 0, %0, c8, c7, 0": :"r"(0)); } void mmu_invalidate_icache() { - asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); + asm volatile("mcr p15, 0, %0, c7, c5, 0": :"r"(0)); } void mmu_invalidate_dcache_all() { - asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0)); + asm volatile("mcr p15, 0, %0, c7, c6, 0": :"r"(0)); } #endif @@ -389,10 +389,10 @@ void mmu_invalidate_dcache_all() /* level1 page table */ #if defined(__ICCARM__) #pragma data_alignment=(16*1024) -static volatile rt_uint32_t _page_table[4*1024]; +static volatile rt_uint32_t _page_table[4 * 1024]; #else -static volatile rt_uint32_t _page_table[4*1024] \ - __attribute__((aligned(16*1024))); +static volatile rt_uint32_t _page_table[4 * 1024] \ +__attribute__((aligned(16 * 1024))); #endif void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, @@ -401,11 +401,11 @@ void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, volatile rt_uint32_t *pTT; volatile int nSec; int i = 0; - pTT=(rt_uint32_t *)_page_table+(vaddrStart>>20); - nSec=(vaddrEnd>>20)-(vaddrStart>>20); - for(i=0; i<=nSec; i++) + pTT = (rt_uint32_t *)_page_table + (vaddrStart >> 20); + nSec = (vaddrEnd >> 20) - (vaddrStart >> 20); + for (i = 0; i <= nSec; i++) { - *pTT = attr |(((paddrStart>>20)+i)<<20); + *pTT = attr | (((paddrStart >> 20) + i) << 20); pTT++; } } diff --git a/libcpu/arm/arm926/mmu.h b/libcpu/arm/arm926/mmu.h index 7b930f5358..36fdbeacd8 100644 --- a/libcpu/arm/arm926/mmu.h +++ b/libcpu/arm/arm926/mmu.h @@ -5,6 +5,7 @@ * * Change Logs: * Date Author Notes + * 2018-02-08 RT-Thread the first version */ #ifndef __MMU_H__ @@ -45,5 +46,7 @@ struct mem_desc }; void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size); - +void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size); +void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); +void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); #endif diff --git a/libcpu/arm/arm926/stack.c b/libcpu/arm/arm926/stack.c index fa98feb824..f90bfa8c22 100644 --- a/libcpu/arm/arm926/stack.c +++ b/libcpu/arm/arm926/stack.c @@ -38,7 +38,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, stack_addr += sizeof(rt_uint32_t); stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); - stk = (rt_uint32_t *)stack_addr; + stk = (rt_uint32_t *)stack_addr; *(--stk) = (rt_uint32_t)tentry; /* entry point */ *(--stk) = (rt_uint32_t)texit; /* lr */ diff --git a/libcpu/arm/arm926/start_gcc.S b/libcpu/arm/arm926/start_gcc.S index fee8e018cb..35c1f1722e 100644 --- a/libcpu/arm/arm926/start_gcc.S +++ b/libcpu/arm/arm926/start_gcc.S @@ -11,295 +11,320 @@ * 2015-06-04 aozima Align stack address to 8 byte. */ -#include "rt_low_level_init.h" +.equ MODE_USR, 0x10 +.equ MODE_FIQ, 0x11 +.equ MODE_IRQ, 0x12 +.equ MODE_SVC, 0x13 +.equ MODE_ABT, 0x17 +.equ MODE_UND, 0x1B +.equ MODE_SYS, 0x1F +.equ MODEMASK, 0x1F +.equ NOINT, 0xC0 -#define S_FRAME_SIZE (18*4) //72 +.equ I_BIT, 0x80 +.equ F_BIT, 0x40 -@#define S_SPSR (17*4) //SPSR -@#define S_CPSR (16*4) //CPSR -#define S_PC (15*4) //R15 -@#define S_LR (14*4) //R14 -@#define S_SP (13*4) //R13 +.equ UND_STACK_SIZE, 0x00000100 +.equ SVC_STACK_SIZE, 0x00000100 +.equ ABT_STACK_SIZE, 0x00000100 +.equ FIQ_STACK_SIZE, 0x00000100 +.equ IRQ_STACK_SIZE, 0x00000100 +.equ SYS_STACK_SIZE, 0x00000100 -@#define S_IP (12*4) //R12 -@#define S_FP (11*4) //R11 -@#define S_R10 (10*4) -@#define S_R9 (9*4) -@#define S_R8 (8*4) -@#define S_R7 (7*4) -@#define S_R6 (6*4) -@#define S_R5 (5*4) -@#define S_R4 (4*4) -@#define S_R3 (3*4) -@#define S_R2 (2*4) -@#define S_R1 (1*4) -@#define S_R0 (0*4) + /* + *************************************** + * Interrupt vector table + *************************************** + */ +.section .vectors +.code 32 -#define MODE_SYS 0x1F -#define MODE_FIQ 0x11 -#define MODE_IRQ 0x12 -#define MODE_SVC 0x13 -#define MODE_ABT 0x17 -#define MODE_UND 0x1B -#define MODEMASK 0x1F +.global system_vectors +system_vectors: + ldr pc, _vector_reset + ldr pc, _vector_undef + ldr pc, _vector_swi + ldr pc, _vector_pabt + ldr pc, _vector_dabt + ldr pc, _vector_resv + ldr pc, _vector_irq + ldr pc, _vector_fiq -#define NOINT 0xC0 +_vector_reset: + .word reset +_vector_undef: + .word vector_undef +_vector_swi: + .word vector_swi +_vector_pabt: + .word vector_pabt +_vector_dabt: + .word vector_dabt +_vector_resv: + .word vector_resv +_vector_irq: + .word vector_irq +_vector_fiq: + .word vector_fiq -@;----------------------- Stack and Heap Definitions --------------------------- - .section .nobss, "w" +.balignl 16,0xdeadbeef - .space UND_STK_SIZE + /* + *************************************** + * Stack and Heap Definitions + *************************************** + */ + .section .data + .space UND_STACK_SIZE .align 3 - .global UND_STACK_START -UND_STACK_START: + .global und_stack_start +und_stack_start: - .space ABT_STK_SIZE + .space ABT_STACK_SIZE .align 3 - .global ABT_STACK_START -ABT_STACK_START: + .global abt_stack_start +abt_stack_start: - .space FIQ_STK_SIZE + .space FIQ_STACK_SIZE .align 3 - .global FIQ_STACK_START -FIQ_STACK_START: + .global fiq_stack_start +fiq_stack_start: - .space IRQ_STK_SIZE + .space IRQ_STACK_SIZE .align 3 - .global IRQ_STACK_START -IRQ_STACK_START: + .global irq_stack_start +irq_stack_start: - .skip SYS_STK_SIZE + .skip SYS_STACK_SIZE .align 3 - .global SYS_STACK_START -SYS_STACK_START: + .global sys_stack_start +sys_stack_start: - .space SVC_STK_SIZE + .space SVC_STACK_SIZE .align 3 - .global SVC_STACK_START -SVC_STACK_START: - -@;--------------Jump vector table----------------------------------------------- - .section .init, "ax" - .arm + .global svc_stack_start +svc_stack_start: - .global start -start: - LDR PC, vector_reset - LDR PC, vector_undef - LDR PC, vector_swi - LDR PC, vector_pabt - LDR PC, vector_dabt - LDR PC, vector_resv - LDR PC, vector_irq - LDR PC, vector_fiq +/* + *************************************** + * Startup Code + *************************************** + */ + .section .text + .global reset +reset: + /* Enter svc mode and mask interrupts */ + mrs r0, cpsr + bic r0, r0, #MODEMASK + orr r0, r0, #MODE_SVC|NOINT + msr cpsr_cxsf, r0 -vector_reset: - .word Reset_Handler -vector_undef: - .word Undef_Handler -vector_swi: - .word SWI_Handler -vector_pabt: - .word PAbt_Handler -vector_dabt: - .word DAbt_Handler -vector_resv: - .word Resv_Handler -vector_irq: - .word IRQ_Handler -vector_fiq: - .word FIQ_Handler + /* init cpu */ + bl cpu_init_crit + + /* todo:copyself to link address */ + + /* Copy vector to the correct address */ + ldr r0, =system_vectors + mrc p15, 0, r2, c1, c0, 0 + ands r2, r2, #(1 << 13) + ldreq r1, =0x00000000 + ldrne r1, =0xffff0000 + ldmia r0!, {r2-r8, r10} + stmia r1!, {r2-r8, r10} + ldmia r0!, {r2-r8, r10} + stmia r1!, {r2-r8, r10} - .balignl 16,0xdeadbeef + /* turn off the watchdog */ + ldr r0, =0x01C20CB8 + mov r1, #0x0 + str r1, [r0] -@;----------------- Reset Handler --------------------------------------------- - .global rt_low_level_init - .global main - .global Reset_Handler -Reset_Handler: - @; Set the cpu to SVC32 mode - MRS R0, CPSR - BIC R0, R0, #MODEMASK - ORR R0, R0, #MODE_SVC|NOINT - MSR CPSR_cxsf, R0 + /* mask all IRQs source */ + ldr r1, =0xffffffff + ldr r0, =0x01C20430 + str r1, [r0], #0x04 + str r1, [r0] + + /* Call low level init function */ + ldr sp, =svc_stack_start + ldr r0, =rt_low_level_init + blx r0 - @; Set CO-Processor - @; little-end锛宒isbale I/D Cache MMU, vector table is 0x00000000 - MRC P15, 0, R0, C1, C0, 0 @; Read CP15 - LDR R1, =0x00003085 @; set clear bits - BIC R0, R0, R1 - MCR P15, 0, R0, C1, C0, 0 @; Write CP15 + /* init stack */ + bl stack_setup + + /* clear bss */ + mov r0, #0 + ldr r1, =__bss_start + ldr r2, =__bss_end + +bss_clear_loop: + cmp r1, r2 + strlo r0, [r1], #4 + blo bss_clear_loop + + /* call c++ constructors of global objects */ + /* + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ + +ctor_loop: + cmp r0, r1 + beq ctor_end + ldr r2, [r0], #4 + stmfd sp!, {r0-r1} + mov lr, pc + bx r2 + ldmfd sp!, {r0-r1} + b ctor_loop +ctor_end: + */ + /* start RT-Thread Kernel */ + ldr pc, _rtthread_startup +_rtthread_startup: + .word rtthread_startup - @; Call low level init function, - @; disable and clear all IRQs, Init MMU, Init interrupt controller, etc. - LDR SP, =SVC_STACK_START - LDR R0, =rt_low_level_init - BLX R0 -Setup_Stack: - @; Setup Stack for each mode - MRS R0, CPSR - BIC R0, R0, #MODEMASK - ORR R1, R0, #MODE_UND|NOINT - MSR CPSR_cxsf, R1 @; Undef mode - LDR SP, =UND_STACK_START +cpu_init_crit: + /* invalidate I/D caches */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 + mcr p15, 0, r0, c8, c7, 0 - ORR R1, R0, #MODE_ABT|NOINT - MSR CPSR_cxsf, R1 @; Abort mode - LDR SP, =ABT_STACK_START + /* disable MMU stuff and caches */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 + bic r0, r0, #0x00000087 + orr r0, r0, #0x00000002 + orr r0, r0, #0x00001000 + mcr p15, 0, r0, c1, c0, 0 - ORR R1, R0, #MODE_IRQ|NOINT - MSR CPSR_cxsf, R1 @; IRQ mode - LDR SP, =IRQ_STACK_START + bx lr + +stack_setup: + /* Setup Stack for each mode */ + mrs r0, cpsr + bic r0, r0, #MODEMASK - ORR R1, R0, #MODE_FIQ|NOINT - MSR CPSR_cxsf, R1 @; FIQ mode - LDR SP, =FIQ_STACK_START + orr r1, r0, #MODE_UND|NOINT + msr cpsr_cxsf, r1 + ldr sp, =und_stack_start - ORR R1, R0, #MODE_SYS|NOINT - MSR CPSR_cxsf,R1 @; SYS/User mode - LDR SP, =SYS_STACK_START + orr r1, r0, #MODE_ABT|NOINT + msr cpsr_cxsf, r1 + ldr sp, =abt_stack_start - ORR R1, R0, #MODE_SVC|NOINT - MSR CPSR_cxsf, R1 @; SVC mode - LDR SP, =SVC_STACK_START + orr r1, r0, #MODE_IRQ|NOINT + msr cpsr_cxsf, r1 + ldr sp, =irq_stack_start - @; clear .bss - MOV R0, #0 @; get a zero - LDR R1, =__bss_start__ @; bss start - LDR R2, =__bss_end__ @; bss end + orr r1, r0, #MODE_FIQ|NOINT + msr cpsr_cxsf, r1 + ldr sp, =fiq_stack_start -bss_clear_loop: - CMP R1, R2 @; check if data to clear - STRLO R0, [R1], #4 @; clear 4 bytes - BLO bss_clear_loop @; loop until done + orr r1, r0, #MODE_SYS|NOINT + msr cpsr_cxsf,r1 + ldr sp, =sys_stack_start - @; call C++ constructors of global objects - LDR R0, =__ctors_start__ - LDR R1, =__ctors_end__ + orr r1, r0, #MODE_SVC|NOINT + msr cpsr_cxsf, r1 + ldr sp, =svc_stack_start -ctor_loop: - CMP R0, R1 - BEQ ctor_end - LDR R2, [R0], #4 - STMFD SP!, {R0-R1} - MOV LR, PC - BX R2 - LDMFD SP!, {R0-R1} - B ctor_loop -ctor_end: + bx lr + +/* + *************************************** + * exception handlers + *************************************** + */ + /* Interrupt */ +vector_fiq: + stmfd sp!,{r0-r7,lr} + bl rt_hw_trap_fiq + ldmfd sp!,{r0-r7,lr} + subs pc, lr, #4 - @; Enter the C code - LDR R0, =rtthread_startup - BLX R0 +vector_irq: + stmfd sp!, {r0-r12,lr} -@;----------------- Exception Handler ----------------------------------------- - .global rt_hw_trap_udef - .global rt_hw_trap_swi - .global rt_hw_trap_pabt - .global rt_hw_trap_dabt - .global rt_hw_trap_resv - .global rt_hw_trap_irq - .global rt_hw_trap_fiq + bl rt_interrupt_enter + bl rt_hw_trap_irq + bl rt_interrupt_leave - .global rt_interrupt_enter - .global rt_interrupt_leave - .global rt_thread_switch_interrupt_flag - .global rt_interrupt_from_thread - .global rt_interrupt_to_thread - - .align 5 -Undef_Handler: - SUB SP, SP, #S_FRAME_SIZE - STMIA SP, {R0 - R12} @; Calling R0-R12 - ADD R8, SP, #S_PC - STMDB R8, {SP, LR} @; Calling SP, LR - STR LR, [R8, #0] @; Save calling PC - MRS R6, SPSR - STR R6, [R8, #4] @; Save CPSR - STR R0, [R8, #8] @; Save SPSR - MOV R0, SP - BL rt_hw_trap_udef - - .align 5 -SWI_Handler: - BL rt_hw_trap_swi - - .align 5 -PAbt_Handler: - BL rt_hw_trap_pabt + ldr r0, =rt_thread_switch_interrupt_flag + ldr r1, [r0] + cmp r1, #1 + beq rt_hw_context_switch_interrupt_do - .align 5 -DAbt_Handler: - SUB SP, SP, #S_FRAME_SIZE - STMIA SP, {R0 - R12} @; Calling R0-R12 - ADD R8, SP, #S_PC - STMDB R8, {SP, LR} @; Calling SP, LR - STR LR, [R8, #0] @; Save calling PC - MRS R6, SPSR - STR R6, [R8, #4] @; Save CPSR - STR R0, [R8, #8] @; Save SPSR - MOV R0, SP - BL rt_hw_trap_dabt + ldmfd sp!, {r0-r12,lr} + subs pc, lr, #4 - .align 5 -Resv_Handler: - BL rt_hw_trap_resv +rt_hw_context_switch_interrupt_do: + mov r1, #0 + str r1, [r0] - .align 5 -FIQ_Handler: - STMFD SP!, {R0-R7,LR} - BL rt_hw_trap_fiq - LDMFD SP!, {R0-R7,LR} - SUBS PC, LR, #4 + mov r1, sp + add sp, sp, #4*4 + ldmfd sp!, {r4-r12,lr} + mrs r0, spsr + sub r2, lr, #4 - .align 5 -IRQ_Handler: - STMFD SP!, {R0-R12,LR} - BL rt_interrupt_enter - BL rt_hw_trap_irq - BL rt_interrupt_leave + msr cpsr_c, #I_BIT|F_BIT|MODE_SVC - @; If rt_thread_switch_interrupt_flag set, - @; jump to rt_hw_context_switch_interrupt_do and don't return - LDR R0, =rt_thread_switch_interrupt_flag - LDR R1, [R0] - CMP R1, #1 - BEQ rt_hw_context_switch_interrupt_do + stmfd sp!, {r2} + stmfd sp!, {r4-r12,lr} + ldmfd r1, {r1-r4} + stmfd sp!, {r1-r4} + stmfd sp!, {r0} - LDMFD SP!, {R0-R12,LR} - SUBS PC, LR, #4 + ldr r4, =rt_interrupt_from_thread + ldr r5, [r4] + str sp, [r5] -@;------ void rt_hw_context_switch_interrupt_do(rt_base_t flag) ----------------- -rt_hw_context_switch_interrupt_do: - MOV R1, #0 @; Clear flag - STR R1, [R0] @; Save to flag variable + ldr r6, =rt_interrupt_to_thread + ldr r6, [r6] + ldr sp, [r6] - LDMFD SP!, {R0-R12,LR} @; Reload saved registers - STMFD SP, {R0-R2} @; Save R0-R2 - SUB R1, SP, #4*3 @; Save old task's SP to R1 - SUB R2, LR, #4 @; Save old task's PC to R2 + ldmfd sp!, {r4} + msr spsr_cxsf, r4 - MRS R0, SPSR @; Get CPSR of interrupt thread + ldmfd sp!, {r0-r12,lr,pc}^ - MSR CPSR_c, #MODE_SVC|NOINT @; Switch to SVC mode and no interrupt + /* Exception */ +.macro push_svc_reg + sub sp, sp, #17 * 4 + stmia sp, {r0 - r12} + mov r0, sp + mrs r6, spsr + str lr, [r0, #15*4] + str r6, [r0, #16*4] + str sp, [r0, #13*4] + str lr, [r0, #14*4] +.endm - STMFD SP!, {R2} @; Push old task's PC - STMFD SP!, {R3-R12,LR} @; Push old task's LR,R12-R3 - LDMFD R1, {R1-R3} - STMFD SP!, {R1-R3} @; Push old task's R2-R0 - STMFD SP!, {R0} @; Push old task's CPSR +vector_swi: + push_svc_reg + bl rt_hw_trap_swi + b . - LDR R4, =rt_interrupt_from_thread - LDR R5, [R4] @; R5 = stack ptr in old tasks's TCB - STR SP, [R5] @; Store SP in preempted tasks's TCB +vector_undef: + push_svc_reg + bl rt_hw_trap_udef + b . - LDR R6, =rt_interrupt_to_thread - LDR R6, [R6] @; R6 = stack ptr in new tasks's TCB - LDR SP, [R6] @; Get new task's stack pointer +vector_pabt: + push_svc_reg + bl rt_hw_trap_pabt + b . - LDMFD SP!, {R4} @; Pop new task's SPSR - MSR SPSR_cxsf, R4 +vector_dabt: + push_svc_reg + bl rt_hw_trap_dabt + b . - LDMFD SP!, {R0-R12,LR,PC}^ @; pop new task's R0-R12,LR & PC SPSR 2 CPSR +vector_resv: + push_svc_reg + bl rt_hw_trap_resv + b . diff --git a/libcpu/arm/arm926/start_iar.S b/libcpu/arm/arm926/start_iar.S index 880f2d9706..080acd57b6 100644 --- a/libcpu/arm/arm926/start_iar.S +++ b/libcpu/arm/arm926/start_iar.S @@ -1,21 +1,7 @@ ;/* -; * File : start.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006, RT-Thread Development Team +; * Copyright (c) 2006-2018, RT-Thread Development Team ; * -; * This program is free software; you can redistribute it and/or modify -; * it under the terms of the GNU General Public License as published by -; * the Free Software Foundation; either version 2 of the License, or -; * (at your option) any later version. -; * -; * This program is distributed in the hope that it will be useful, -; * but WITHOUT ANY WARRANTY; without even the implied warranty of -; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; * GNU General Public License for more details. -; * -; * You should have received a copy of the GNU General Public License along -; * with this program; if not, write to the Free Software Foundation, Inc., -; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes diff --git a/libcpu/arm/arm926/start_rvds.S b/libcpu/arm/arm926/start_rvds.S index 9f789b97f7..fc7e84ffaa 100644 --- a/libcpu/arm/arm926/start_rvds.S +++ b/libcpu/arm/arm926/start_rvds.S @@ -1,21 +1,7 @@ ;/* -; * File : start_rvds.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006, RT-Thread Development Team +; * Copyright (c) 2006-2018, RT-Thread Development Team ; * -; * This program is free software; you can redistribute it and/or modify -; * it under the terms of the GNU General Public License as published by -; * the Free Software Foundation; either version 2 of the License, or -; * (at your option) any later version. -; * -; * This program is distributed in the hope that it will be useful, -; * but WITHOUT ANY WARRANTY; without even the implied warranty of -; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; * GNU General Public License for more details. -; * -; * You should have received a copy of the GNU General Public License along -; * with this program; if not, write to the Free Software Foundation, Inc., -; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes @@ -25,28 +11,16 @@ ; * 2015-06-04 aozima Align stack address to 8 byte. ; */ -#include "rt_low_level_init.h" +UND_STK_SIZE EQU 512 +SVC_STK_SIZE EQU 4096 +ABT_STK_SIZE EQU 512 +IRQ_STK_SIZE EQU 1024 +FIQ_STK_SIZE EQU 1024 +SYS_STK_SIZE EQU 512 +Heap_Size EQU 512 S_FRAME_SIZE EQU (18*4) ;72 -;S_SPSR EQU (17*4) ;SPSR -;S_CPSR EQU (16*4) ;CPSR S_PC EQU (15*4) ;R15 -;S_LR EQU (14*4) ;R14 -;S_SP EQU (13*4) ;R13 - -;S_IP EQU (12*4) ;R12 -;S_FP EQU (11*4) ;R11 -;S_R10 EQU (10*4) -;S_R9 EQU (9*4) -;S_R8 EQU (8*4) -;S_R7 EQU (7*4) -;S_R6 EQU (6*4) -;S_R5 EQU (5*4) -;S_R4 EQU (4*4) -;S_R3 EQU (3*4) -;S_R2 EQU (2*4) -;S_R1 EQU (1*4) -;S_R0 EQU (0*4) MODE_USR EQU 0X10 MODE_FIQ EQU 0X11 diff --git a/libcpu/arm/arm926/trap.c b/libcpu/arm/arm926/trap.c index 054cc2741a..9e7ba48037 100644 --- a/libcpu/arm/arm926/trap.c +++ b/libcpu/arm/arm926/trap.c @@ -41,14 +41,18 @@ struct rt_hw_register rt_uint32_t cpsr; rt_uint32_t ORIG_r0; }; - +static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL; +void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context)) +{ + rt_exception_hook = exception_handle; +} /** * this function will show registers of CPU * * @param regs the registers point */ -void rt_hw_show_register (struct rt_hw_register *regs) +void rt_hw_show_register(struct rt_hw_register *regs) { rt_kprintf("Execption:\n"); rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", @@ -74,6 +78,13 @@ void rt_hw_show_register (struct rt_hw_register *regs) */ void rt_hw_trap_udef(struct rt_hw_register *regs) { + if (rt_exception_hook != RT_NULL) + { + rt_err_t result; + + result = rt_exception_hook(regs); + if (result == RT_EOK) return; + } rt_hw_show_register(regs); rt_kprintf("undefined instruction\n"); @@ -96,6 +107,13 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) */ void rt_hw_trap_swi(struct rt_hw_register *regs) { + if (rt_exception_hook != RT_NULL) + { + rt_err_t result; + + result = rt_exception_hook(regs); + if (result == RT_EOK) return; + } rt_hw_show_register(regs); rt_kprintf("software interrupt\n"); @@ -112,6 +130,13 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { + if (rt_exception_hook != RT_NULL) + { + rt_err_t result; + + result = rt_exception_hook(regs); + if (result == RT_EOK) return; + } rt_hw_show_register(regs); rt_kprintf("prefetch abort\n"); @@ -133,6 +158,13 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) */ void rt_hw_trap_dabt(struct rt_hw_register *regs) { + if (rt_exception_hook != RT_NULL) + { + rt_err_t result; + + result = rt_exception_hook(regs); + if (result == RT_EOK) return; + } rt_hw_show_register(regs); rt_kprintf("data abort\n"); @@ -153,55 +185,26 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs) */ void rt_hw_trap_resv(struct rt_hw_register *regs) { + if (rt_exception_hook != RT_NULL) + { + rt_err_t result; + + result = rt_exception_hook(regs); + if (result == RT_EOK) return; + } rt_kprintf("not used\n"); rt_hw_show_register(regs); rt_hw_cpu_shutdown(); } -extern struct rt_irq_desc irq_desc[]; -extern rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq); -extern void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id); - -void rt_hw_trap_irq() -{ - rt_isr_handler_t isr_func; - rt_uint32_t irq; - void *param; - - /* get irq number */ - irq = rt_hw_interrupt_get_active(INT_IRQ); +extern void rt_interrupt_dispatch(rt_uint32_t fiq_irq); - /* get interrupt service routine */ - isr_func = irq_desc[irq].handler; - param = irq_desc[irq].param; - - /* turn to interrupt service routine */ - isr_func(irq, param); - - rt_hw_interrupt_ack(INT_IRQ, irq); -#ifdef RT_USING_INTERRUPT_INFO - irq_desc[irq].counter ++; -#endif +void rt_hw_trap_irq(void) +{ + rt_interrupt_dispatch(INT_IRQ); } -void rt_hw_trap_fiq() +void rt_hw_trap_fiq(void) { - rt_isr_handler_t isr_func; - rt_uint32_t irq; - void *param; - - /* get irq number */ - irq = rt_hw_interrupt_get_active(INT_FIQ); - - /* get interrupt service routine */ - isr_func = irq_desc[irq].handler; - param = irq_desc[irq].param; - - /* turn to interrupt service routine */ - isr_func(irq, param); - - rt_hw_interrupt_ack(INT_FIQ, irq); -#ifdef RT_USING_INTERRUPT_INFO - irq_desc[irq].counter ++; -#endif + rt_interrupt_dispatch(INT_FIQ); } diff --git a/libcpu/arm/armv6/SConscript b/libcpu/arm/armv6/SConscript new file mode 100644 index 0000000000..9ff30a796b --- /dev/null +++ b/libcpu/arm/armv6/SConscript @@ -0,0 +1,23 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arm/common/SConscript b/libcpu/arm/common/SConscript new file mode 100644 index 0000000000..9ff30a796b --- /dev/null +++ b/libcpu/arm/common/SConscript @@ -0,0 +1,23 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arm/common/backtrace.c b/libcpu/arm/common/backtrace.c index f61c69ef01..4fc87b20d1 100644 --- a/libcpu/arm/common/backtrace.c +++ b/libcpu/arm/common/backtrace.c @@ -13,51 +13,51 @@ #ifdef __GNUC__ /* -->High Address,Stack Top -PC<-----| -LR | -IP | -FP | -...... | -PC<-| | -LR | | -IP | | +PC<------| +LR | +IP | +FP | +...... | +PC <-| | +LR | | +IP | | FP---|-- | -...... | -PC | -LR | -IP | +...... | +PC | +LR | +IP | FP--- -->Low Address,Stack Bottom */ void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry) { - rt_uint32_t i, pc, func_entry; + rt_uint32_t i, pc, func_entry; - pc = *fp; - rt_kprintf("[0x%x]\n", pc-0xC); + pc = *fp; + rt_kprintf("[0x%x]\n", pc-0xC); - for(i=0; i<10; i++) - { - fp = (rt_uint32_t *)*(fp - 3); - pc = *fp ; + for(i=0; i<10; i++) + { + fp = (rt_uint32_t *)*(fp - 3); + pc = *fp ; - func_entry = pc - 0xC; + func_entry = pc - 0xC; - if(func_entry <= 0x30000000) break; + if(func_entry <= 0x30000000) break; - if(func_entry == thread_entry) - { - rt_kprintf("EntryPoint:0x%x\n", func_entry); + if(func_entry == thread_entry) + { + rt_kprintf("EntryPoint:0x%x\n", func_entry); - break; - } + break; + } - rt_kprintf("[0x%x]\n", func_entry); - } + rt_kprintf("[0x%x]\n", func_entry); + } } #else void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry) { - /* old compiler implementation */ + /* old compiler implementation */ } #endif diff --git a/libcpu/arm/cortex-a/SConscript b/libcpu/arm/cortex-a/SConscript new file mode 100644 index 0000000000..9ff30a796b --- /dev/null +++ b/libcpu/arm/cortex-a/SConscript @@ -0,0 +1,23 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arm/cortex-a/cache.c b/libcpu/arm/cortex-a/cache.c new file mode 100644 index 0000000000..30af86baa1 --- /dev/null +++ b/libcpu/arm/cortex-a/cache.c @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-29 quanzhao the first version + */ +#include <rthw.h> +#include <rtdef.h> + +rt_inline rt_uint32_t rt_cpu_icache_line_size(void) +{ + rt_uint32_t ctr; + asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r"(ctr)); + return 4 << (ctr & 0xF); +} + +rt_inline rt_uint32_t rt_cpu_dcache_line_size(void) +{ + rt_uint32_t ctr; + asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r"(ctr)); + return 4 << ((ctr >> 16) & 0xF); +} + +void rt_hw_cpu_icache_invalidate(void *addr, int size) +{ + rt_uint32_t line_size = rt_cpu_icache_line_size(); + rt_uint32_t start_addr = (rt_uint32_t)addr; + rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1; + + asm volatile ("dmb":::"memory"); + start_addr &= ~(line_size-1); + end_addr &= ~(line_size-1); + while (start_addr < end_addr) + { + asm volatile ("mcr p15, 0, %0, c7, c5, 1" :: "r"(start_addr)); /* icimvau */ + start_addr += line_size; + } + asm volatile ("dsb\n\tisb":::"memory"); +} + +void rt_hw_cpu_dcache_invalidate(void *addr, int size) +{ + rt_uint32_t line_size = rt_cpu_dcache_line_size(); + rt_uint32_t start_addr = (rt_uint32_t)addr; + rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1; + + asm volatile ("dmb":::"memory"); + start_addr &= ~(line_size-1); + end_addr &= ~(line_size-1); + while (start_addr < end_addr) + { + asm volatile ("mcr p15, 0, %0, c7, c6, 1" :: "r"(start_addr)); /* dcimvac */ + start_addr += line_size; + } + asm volatile ("dsb":::"memory"); +} + +void rt_hw_cpu_dcache_clean(void *addr, int size) +{ + rt_uint32_t line_size = rt_cpu_dcache_line_size(); + rt_uint32_t start_addr = (rt_uint32_t)addr; + rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1; + + asm volatile ("dmb":::"memory"); + start_addr &= ~(line_size-1); + end_addr &= ~(line_size-1); + while (start_addr < end_addr) + { + asm volatile ("mcr p15, 0, %0, c7, c10, 1" :: "r"(start_addr)); /* dccmvac */ + start_addr += line_size; + } + asm volatile ("dsb":::"memory"); +} + +void rt_hw_cpu_icache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_INVALIDATE) + rt_hw_cpu_icache_invalidate(addr, size); +} + +void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_FLUSH) + rt_hw_cpu_dcache_clean(addr, size); + else if (ops == RT_HW_CACHE_INVALIDATE) + rt_hw_cpu_dcache_invalidate(addr, size); +} + +rt_base_t rt_hw_cpu_icache_status(void) +{ + return 0; +} + +rt_base_t rt_hw_cpu_dcache_status(void) +{ + return 0; +} diff --git a/libcpu/arm/cortex-a/context_gcc.S b/libcpu/arm/cortex-a/context_gcc.S index 97b3dbc447..768c5138e9 100644 --- a/libcpu/arm/cortex-a/context_gcc.S +++ b/libcpu/arm/cortex-a/context_gcc.S @@ -8,7 +8,14 @@ * 2013-07-05 Bernard the first version */ +#include "rtconfig.h" .section .text, "ax" + +#ifdef RT_USING_SMP +#define rt_hw_interrupt_disable rt_hw_local_irq_disable +#define rt_hw_interrupt_enable rt_hw_local_irq_enable +#endif + /* * rt_base_t rt_hw_interrupt_disable(); */ @@ -27,17 +34,19 @@ rt_hw_interrupt_enable: bx lr /* - * void rt_hw_context_switch_to(rt_uint32 to); - * r0 --> to + * void rt_hw_context_switch_to(rt_uint32 to, struct rt_thread *to_thread); + * r0 --> to (thread stack) + * r1 --> to_thread */ .globl rt_hw_context_switch_to rt_hw_context_switch_to: ldr sp, [r0] @ get new task stack pointer - ldmfd sp!, {r4} @ pop new task spsr - msr spsr_cxsf, r4 - - ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc +#ifdef RT_USING_SMP + mov r0, r1 + bl rt_cpus_lock_status_restore +#endif /*RT_USING_SMP*/ + b rt_hw_context_switch_exit .section .bss.share.isr _guest_switch_lvl: @@ -47,9 +56,10 @@ _guest_switch_lvl: .section .text.isr, "ax" /* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * r0 --> from - * r1 --> to + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to, struct rt_thread *to_thread); + * r0 --> from (from_thread stack) + * r1 --> to (to_thread stack) + * r2 --> to_thread */ .globl rt_hw_context_switch rt_hw_context_switch: @@ -62,21 +72,67 @@ rt_hw_context_switch: stmfd sp!, {r4} @ push cpsr +#ifdef RT_USING_LWP + stmfd sp, {r13, r14}^ @ push usr_sp usr_lr + sub sp, #8 +#endif +#ifdef RT_USING_FPU + /* fpu context */ + vmrs r6, fpexc + tst r6, #(1<<30) + beq 1f + vstmdb sp!, {d0-d15} + vstmdb sp!, {d16-d31} + vmrs r5, fpscr + stmfd sp!, {r5} +1: + stmfd sp!, {r6} +#endif + str sp, [r0] @ store sp in preempted tasks TCB ldr sp, [r1] @ get new task stack pointer - ldmfd sp!, {r4} @ pop new task cpsr to spsr - msr spsr_cxsf, r4 - ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr +#ifdef RT_USING_SMP + mov r0, r2 + bl rt_cpus_lock_status_restore +#endif /*RT_USING_SMP*/ + b rt_hw_context_switch_exit /* * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); */ +.equ Mode_USR, 0x10 +.equ Mode_FIQ, 0x11 +.equ Mode_IRQ, 0x12 +.equ Mode_SVC, 0x13 +.equ Mode_ABT, 0x17 +.equ Mode_UND, 0x1B +.equ Mode_SYS, 0x1F + +.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled +.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled + .globl rt_thread_switch_interrupt_flag .globl rt_interrupt_from_thread .globl rt_interrupt_to_thread .globl rt_hw_context_switch_interrupt rt_hw_context_switch_interrupt: +#ifdef RT_USING_SMP + /* r0 :svc_mod context + * r1 :addr of from_thread's sp + * r2 :addr of to_thread's sp + * r3 :to_thread's tcb + */ + + str r0, [r1] + + ldr sp, [r2] + mov r0, r3 + bl rt_cpus_lock_status_restore + + b rt_hw_context_switch_exit + +#else /*RT_USING_SMP*/ ldr r2, =rt_thread_switch_interrupt_flag ldr r3, [r2] cmp r3, #1 @@ -89,3 +145,38 @@ _reswitch: ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread str r1, [r2] bx lr +#endif /*RT_USING_SMP*/ + +.global rt_hw_context_switch_exit +rt_hw_context_switch_exit: + +#ifdef RT_USING_SMP +#ifdef RT_USING_SIGNALS + mov r0, sp + cps #Mode_IRQ + bl rt_signal_check + cps #Mode_SVC + mov sp, r0 +#endif +#endif +#ifdef RT_USING_FPU +/* fpu context */ + ldmfd sp!, {r6} + vmsr fpexc, r6 + tst r6, #(1<<30) + beq 1f + ldmfd sp!, {r5} + vmsr fpscr, r5 + vldmia sp!, {d16-d31} + vldmia sp!, {d0-d15} +1: +#endif + +#ifdef RT_USING_LWP + ldmfd sp, {r13, r14}^ /* usr_sp, usr_lr */ + add sp, #8 +#endif + ldmfd sp!, {r1} + msr spsr_cxsf, r1 /* original mode */ + ldmfd sp!, {r0-r12,lr,pc}^ /* irq return */ + diff --git a/libcpu/arm/cortex-a/cp15.h b/libcpu/arm/cortex-a/cp15.h index 486f38200d..97c5b93ad2 100644 --- a/libcpu/arm/cortex-a/cp15.h +++ b/libcpu/arm/cortex-a/cp15.h @@ -5,6 +5,7 @@ * * Change Logs: * Date Author Notes + * 2018-03-25 quanzhao the first version */ #ifndef __CP15_H__ #define __CP15_H__ @@ -15,6 +16,9 @@ void rt_cpu_mmu_disable(void); void rt_cpu_mmu_enable(void); void rt_cpu_tlb_set(volatile unsigned long*); +void rt_cpu_dcache_clean_flush(void); +void rt_cpu_icache_flush(void); + void rt_cpu_vector_set_base(unsigned int addr); #endif diff --git a/libcpu/arm/cortex-a/cp15_gcc.S b/libcpu/arm/cortex-a/cp15_gcc.S index 0e3e60655c..dd2436ffee 100644 --- a/libcpu/arm/cortex-a/cp15_gcc.S +++ b/libcpu/arm/cortex-a/cp15_gcc.S @@ -15,6 +15,11 @@ rt_cpu_get_smp_id: .globl rt_cpu_vector_set_base rt_cpu_vector_set_base: + /* clear SCTRL.V to customize the vector address */ + mrc p15, #0, r1, c1, c0, #0 + bic r1, #(1 << 13) + mcr p15, #0, r1, c1, c0, #0 + /* set up the vector address */ mcr p15, #0, r0, c12, c0, #0 dsb bx lr @@ -36,7 +41,7 @@ rt_hw_cpu_icache_enable: _FLD_MAX_WAY: .word 0x3ff _FLD_MAX_IDX: - .word 0x7ff + .word 0x7fff .globl rt_cpu_dcache_clean_flush rt_cpu_dcache_clean_flush: @@ -84,6 +89,14 @@ finished: pop {r4-r11} bx lr +.globl rt_cpu_icache_flush +rt_cpu_icache_flush: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate + dsb + isb + bx lr + .globl rt_hw_cpu_dcache_disable rt_hw_cpu_dcache_disable: push {r4-r11, lr} diff --git a/libcpu/arm/cortex-a/cpu.c b/libcpu/arm/cortex-a/cpu.c index 2d78715011..7c6bf58a4b 100644 --- a/libcpu/arm/cortex-a/cpu.c +++ b/libcpu/arm/cortex-a/cpu.c @@ -6,28 +6,84 @@ * Change Logs: * Date Author Notes * 2011-09-15 Bernard first version + * 2018-11-22 Jesven add rt_hw_cpu_id() */ #include <rthw.h> #include <rtthread.h> #include <board.h> +#ifdef RT_USING_SMP + +int rt_hw_cpu_id(void) +{ + int cpu_id; + __asm__ volatile ( + "mrc p15, 0, %0, c0, c0, 5" + :"=r"(cpu_id) + ); + cpu_id &= 0xf; + return cpu_id; +}; + +void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock) +{ + lock->slock = 0; +} + +void rt_hw_spin_lock(rt_hw_spinlock_t *lock) +{ + unsigned long tmp; + unsigned long newval; + rt_hw_spinlock_t lockval; + + __asm__ __volatile__( + "pld [%0]" + ::"r"(&lock->slock) + ); + + __asm__ __volatile__( + "1: ldrex %0, [%3]\n" + " add %1, %0, %4\n" + " strex %2, %1, [%3]\n" + " teq %2, #0\n" + " bne 1b" + : "=&r" (lockval), "=&r" (newval), "=&r" (tmp) + : "r" (&lock->slock), "I" (1 << 16) + : "cc"); + + while (lockval.tickets.next != lockval.tickets.owner) { + __asm__ __volatile__("wfe":::"memory"); + lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner); + } + + __asm__ volatile ("dmb":::"memory"); +} + +void rt_hw_spin_unlock(rt_hw_spinlock_t *lock) +{ + __asm__ volatile ("dmb":::"memory"); + lock->tickets.owner++; + __asm__ volatile ("dsb ishst\nsev":::"memory"); +} +#endif /*RT_USING_SMP*/ + /** - * @addtogroup AM33xx + * @addtogroup ARM CPU */ /*@{*/ /** shutdown CPU */ void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } } /*@}*/ diff --git a/libcpu/arm/cortex-a/gic.c b/libcpu/arm/cortex-a/gic.c new file mode 100644 index 0000000000..2e94b88277 --- /dev/null +++ b/libcpu/arm/cortex-a/gic.c @@ -0,0 +1,300 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + * 2014-04-03 Grissiom many enhancements + * 2018-11-22 Jesven add rt_hw_ipi_send() + * add rt_hw_ipi_handler_install() + */ + +#include <rthw.h> +#include <rtthread.h> + +#include "gic.h" +#include "cp15.h" + +struct arm_gic +{ + rt_uint32_t offset; /* the first interrupt index in the vector table */ + + rt_uint32_t dist_hw_base; /* the base address of the gic distributor */ + rt_uint32_t cpu_hw_base; /* the base addrees of the gic cpu interface */ +}; + +/* 'ARM_GIC_MAX_NR' is the number of cores */ +static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; + +#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00) +#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04) +#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08) +#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c) +#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10) +#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14) +#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18) + +#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000) +#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004) +#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4) +#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4) +#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4) +#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4) +#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4) +#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380 + ((n)/32) * 4) +#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4) +#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4) +#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4) +#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00) +#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10 + ((n)/4) * 4) +#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8) + +static unsigned int _gic_max_irq; + +int arm_gic_get_active_irq(rt_uint32_t index) +{ + int irq; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base); + irq += _gic_table[index].offset; + return irq; +} + +void arm_gic_ack(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; +} + +void arm_gic_mask(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_clear_pending(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_clear_active(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; +} + +/* Set up the cpu mask for the specific interrupt */ +void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) +{ + rt_uint32_t old_tgt; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); + + old_tgt &= ~(0x0FFUL << ((irq % 4)*8)); + old_tgt |= cpumask << ((irq % 4)*8); + + GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; +} + +void arm_gic_umask(rt_uint32_t index, int irq) +{ + rt_uint32_t mask = 1 << (irq % 32); + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + irq = irq - _gic_table[index].offset; + RT_ASSERT(irq >= 0); + + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; +} + +void arm_gic_dump_type(rt_uint32_t index) +{ + unsigned int gic_type; + + gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); + rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", + (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf, + _gic_table[index].dist_hw_base, + _gic_max_irq, + gic_type & (1 << 10) ? "has" : "no", + gic_type); +} + +void arm_gic_dump(rt_uint32_t index) +{ + unsigned int i, k; + + k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base); + rt_kprintf("--- high pending priority: %d(%08x)\n", k, k); + rt_kprintf("--- hw mask ---\n"); + for (i = 0; i < _gic_max_irq / 32; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, + i * 32)); + } + rt_kprintf("\n--- hw pending ---\n"); + for (i = 0; i < _gic_max_irq / 32; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, + i * 32)); + } + rt_kprintf("\n--- hw active ---\n"); + for (i = 0; i < _gic_max_irq / 32; i++) + { + rt_kprintf("0x%08x, ", + GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, + i * 32)); + } + rt_kprintf("\n"); +} +#ifdef RT_USING_FINSH +#include <finsh.h> +FINSH_FUNCTION_EXPORT_ALIAS(arm_gic_dump, gic, show gic status); +#endif + +int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) +{ + unsigned int gic_type, i; + rt_uint32_t cpumask = 1 << 0; + + RT_ASSERT(index < ARM_GIC_MAX_NR); + + _gic_table[index].dist_hw_base = dist_base; + _gic_table[index].offset = irq_start; + + /* Find out how many interrupts are supported. */ + gic_type = GIC_DIST_TYPE(dist_base); + _gic_max_irq = ((gic_type & 0x1f) + 1) * 32; + + /* + * The GIC only supports up to 1020 interrupt sources. + * Limit this to either the architected maximum, or the + * platform maximum. + */ + if (_gic_max_irq > 1020) + _gic_max_irq = 1020; + if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */ + _gic_max_irq = ARM_GIC_NR_IRQS; + + cpumask |= cpumask << 8; + cpumask |= cpumask << 16; + cpumask |= cpumask << 24; + + GIC_DIST_CTRL(dist_base) = 0x0; + + /* Set all global interrupts to be level triggered, active low. */ + for (i = 32; i < _gic_max_irq; i += 16) + GIC_DIST_CONFIG(dist_base, i) = 0x0; + + /* Set all global interrupts to this CPU only. */ + for (i = 32; i < _gic_max_irq; i += 4) + GIC_DIST_TARGET(dist_base, i) = cpumask; + + /* Set priority on all interrupts. */ + for (i = 0; i < _gic_max_irq; i += 4) + GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0; + + /* Disable all interrupts. */ + for (i = 0; i < _gic_max_irq; i += 32) + GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff; + +#if 0 + /* All interrupts defaults to IGROUP1(IRQ). */ + for (i = 0; i < _gic_max_irq; i += 32) + GIC_DIST_IGROUP(dist_base, i) = 0xffffffff; +#endif + for (i = 0; i < _gic_max_irq; i += 32) + GIC_DIST_IGROUP(dist_base, i) = 0; + + /* Enable group0 and group1 interrupt forwarding. */ + GIC_DIST_CTRL(dist_base) = 0x01; + + return 0; +} + +int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base) +{ + RT_ASSERT(index < ARM_GIC_MAX_NR); + + _gic_table[index].cpu_hw_base = cpu_base; + + GIC_CPU_PRIMASK(cpu_base) = 0xf0; + GIC_CPU_BINPOINT(cpu_base) = 0x7; + /* Enable CPU interrupt */ + GIC_CPU_CTRL(cpu_base) = 0x01; + + return 0; +} + +void arm_gic_set_group(rt_uint32_t index, int vector, int group) +{ + /* As for GICv2, there are only group0 and group1. */ + RT_ASSERT(group <= 1); + RT_ASSERT(vector < _gic_max_irq); + + if (group == 0) + { + GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, + vector) &= ~(1 << (vector % 32)); + } + else if (group == 1) + { + GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, + vector) |= (1 << (vector % 32)); + } +} + +#ifdef RT_USING_SMP +void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) + { + /* note: ipi_vector maybe different with irq_vector */ + GIC_DIST_SOFTINT(_gic_table[0].dist_hw_base) = (cpu_mask << 16) | ipi_vector; +} +#endif + +#ifdef RT_USING_SMP +void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler) +{ + /* note: ipi_vector maybe different with irq_vector */ + rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER"); +} +#endif diff --git a/libcpu/arm/cortex-a/gic.h b/libcpu/arm/cortex-a/gic.h new file mode 100644 index 0000000000..a16d0467fb --- /dev/null +++ b/libcpu/arm/cortex-a/gic.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version + */ + +#ifndef __GIC_H__ +#define __GIC_H__ + +#include <rthw.h> +#include <board.h> + +int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start); +int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base); + +void arm_gic_mask(rt_uint32_t index, int irq); +void arm_gic_umask(rt_uint32_t index, int irq); +void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask); +void arm_gic_set_group(rt_uint32_t index, int vector, int group); + +int arm_gic_get_active_irq(rt_uint32_t index); +void arm_gic_ack(rt_uint32_t index, int irq); + +void arm_gic_clear_active(rt_uint32_t index, int irq); +void arm_gic_clear_pending(rt_uint32_t index, int irq); + +void arm_gic_dump_type(rt_uint32_t index); +void arm_gic_dump(rt_uint32_t index); + +#endif + diff --git a/libcpu/arm/cortex-a/interrupt.c b/libcpu/arm/cortex-a/interrupt.c index fb6e3ff3e0..b7a70719a9 100644 --- a/libcpu/arm/cortex-a/interrupt.c +++ b/libcpu/arm/cortex-a/interrupt.c @@ -6,68 +6,32 @@ * Change Logs: * Date Author Notes * 2013-07-06 Bernard first version - * 2014-04-03 Grissiom port to VMM + * 2018-11-22 Jesven add smp support */ #include <rthw.h> #include <rtthread.h> +#include "interrupt.h" +#include "gic.h" -#include <irq_numbers.h> -#include <interrupt.h> - -#include <gic.h> -#include "cp15.h" - -#define MAX_HANDLERS IMX_INTERRUPT_COUNT - -extern volatile rt_uint8_t rt_interrupt_nest; /* exception and interrupt handler table */ struct rt_irq_desc isr_table[MAX_HANDLERS]; -rt_uint32_t rt_interrupt_from_thread; -rt_uint32_t rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; +#ifndef RT_USING_SMP +/* Those varibles will be accessed in ISR, so we need to share them. */ +rt_uint32_t rt_interrupt_from_thread = 0; +rt_uint32_t rt_interrupt_to_thread = 0; +rt_uint32_t rt_thread_switch_interrupt_flag = 0; +#endif +const unsigned int VECTOR_BASE = 0x00; extern void rt_cpu_vector_set_base(unsigned int addr); extern int system_vectors; -/* keep compatible with platform SDK */ -void register_interrupt_routine(uint32_t irq_id, irq_hdlr_t isr) -{ - rt_hw_interrupt_install(irq_id, (rt_isr_handler_t)isr, NULL, "unknown"); -} - -void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority) +void rt_hw_vector_init(void) { - gic_set_irq_priority(irq_id, priority); - gic_set_irq_security(irq_id, false); // set IRQ as non-secure - gic_set_cpu_target(irq_id, cpu_id, true); - gic_enable_irq(irq_id, true); -} - -void disable_interrupt(uint32_t irq_id, uint32_t cpu_id) -{ - gic_enable_irq(irq_id, false); - gic_set_cpu_target(irq_id, cpu_id, false); -} - -static void rt_hw_vector_init(void) -{ - int sctrl; - unsigned int *src = (unsigned int *)&system_vectors; - - /* C12-C0 is only active when SCTLR.V = 0 */ - asm volatile ("mrc p15, #0, %0, c1, c0, #0" - :"=r" (sctrl)); - sctrl &= ~(1 << 13); - asm volatile ("mcr p15, #0, %0, c1, c0, #0" - : - :"r" (sctrl)); - - asm volatile ("mcr p15, #0, %0, c12, c0, #0" - : - :"r" (src)); + rt_cpu_vector_set_base((unsigned int)&system_vectors); } /** @@ -75,14 +39,24 @@ static void rt_hw_vector_init(void) */ void rt_hw_interrupt_init(void) { + rt_uint32_t gic_cpu_base; + rt_uint32_t gic_dist_base; + rt_uint32_t gic_irq_start; + + /* initialize vector table */ rt_hw_vector_init(); - gic_init(); - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + /* initialize exceptions table */ + rt_memset(isr_table, 0x00, sizeof(isr_table)); + + /* initialize ARM GIC */ + gic_dist_base = platform_get_gic_dist_base(); + gic_cpu_base = platform_get_gic_cpu_base(); + + gic_irq_start = GIC_IRQ_START; + + arm_gic_dist_init(0, gic_dist_base, gic_irq_start); + arm_gic_cpu_init(0, gic_cpu_base); } /** @@ -91,7 +65,7 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int vector) { - disable_interrupt(vector, 0); + arm_gic_mask(0, vector); } /** @@ -100,10 +74,27 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - enable_interrupt(vector, 0, 0); + arm_gic_umask(0, vector); } /** + * This function returns the active interrupt number. + * @param none + */ +int rt_hw_interrupt_get_irq(void) +{ + return arm_gic_get_active_irq(0) & GIC_ACK_INTID_MASK; +} + +/** + * This function acknowledges the interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_ack(int vector) +{ + arm_gic_ack(0, vector); +} +/** * This function will install a interrupt service routine to a interrupt. * @param vector the interrupt number * @param new_handler the interrupt service routine to be installed @@ -126,23 +117,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, isr_table[vector].handler = handler; isr_table[vector].param = param; } - // arm_gic_set_cpu(0, vector, 1 << rt_cpu_get_smp_id()); } return old_handler; } - -/** - * Trigger a software IRQ - * - * Since we are running in single core, the target CPU are always CPU0. - */ -void rt_hw_interrupt_trigger(int vector) -{ - // arm_gic_trigger(0, 1, vector); -} - -void rt_hw_interrupt_clear(int vector) -{ - gic_write_end_of_irq(vector); -} diff --git a/libcpu/arm/cortex-a/interrupt.h b/libcpu/arm/cortex-a/interrupt.h new file mode 100644 index 0000000000..442187edee --- /dev/null +++ b/libcpu/arm/cortex-a/interrupt.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2013-07-06 Bernard first version + */ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#include <rthw.h> +#include <board.h> + +#define INT_IRQ 0x00 +#define INT_FIQ 0x01 + +void rt_hw_vector_init(void); + +void rt_hw_interrupt_control(int vector, int priority, int route); + +void rt_hw_interrupt_init(void); +void rt_hw_interrupt_mask(int vector); +void rt_hw_interrupt_umask(int vector); + +int rt_hw_interrupt_get_irq(void); +void rt_hw_interrupt_ack(int vector); + +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name); + +#endif diff --git a/libcpu/arm/cortex-a/mmu.c b/libcpu/arm/cortex-a/mmu.c index 58acdd8145..1260f41fe5 100644 --- a/libcpu/arm/cortex-a/mmu.c +++ b/libcpu/arm/cortex-a/mmu.c @@ -13,35 +13,7 @@ #include <board.h> #include "cp15.h" - -#define DESC_SEC (0x2) -#define CB (3<<2) //cache_on, write_back -#define CNB (2<<2) //cache_on, write_through -#define NCB (1<<2) //cache_off,WR_BUF on -#define NCNB (0<<2) //cache_off,WR_BUF off -#define AP_RW (3<<10) //supervisor=RW, user=RW -#define AP_RO (2<<10) //supervisor=RW, user=RO -#define XN (1<<4) // eXecute Never - -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) - -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) - -/* Read/Write, cache, write back */ -#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) -/* Read/Write, cache, write through */ -#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) -/* Read/Write without cache and write buffer */ -#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) -/* Read/Write without cache and write buffer, no execute */ -#define RW_NCNBXN (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN) -/* Read/Write without cache and write buffer */ -#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) +#include "mmu.h" /* dump 2nd level page table */ void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb) @@ -178,18 +150,25 @@ unsigned long rt_hw_set_domain_register(unsigned long domain_val) return old_domain; } +void rt_hw_init_mmu_table(struct mem_desc *mdesc, rt_uint32_t size) +{ + /* set page table */ + for(; size > 0; size--) + { + rt_hw_mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end, + mdesc->paddr_start, mdesc->attr); + mdesc++; + } +} + void rt_hw_mmu_init(void) { + rt_cpu_dcache_clean_flush(); + rt_cpu_icache_flush(); rt_hw_cpu_dcache_disable(); rt_hw_cpu_icache_disable(); rt_cpu_mmu_disable(); - /* set page table */ - /* 4G 1:1 memory */ - rt_hw_mmu_setmtt(0, 0xffffffff-1, 0, RW_CB); - /* IO memory region */ - rt_hw_mmu_setmtt(0x44000000, 0x80000000-1, 0x44000000, RW_NCNBXN); - /*rt_hw_cpu_dump_page_table(MMUTable);*/ rt_hw_set_domain_register(0x55555555); diff --git a/libcpu/arm/cortex-a/mmu.h b/libcpu/arm/cortex-a/mmu.h new file mode 100644 index 0000000000..fbce6df935 --- /dev/null +++ b/libcpu/arm/cortex-a/mmu.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-25 quanzhao the first version + */ +#ifndef __MMU_H_ +#define __MMU_H_ + +#include <rtthread.h> + +#define DESC_SEC (0x2) +#define MEMWBWA ((1<<12)|(3<<2)) /* write back, write allocate */ +#define MEMWB (3<<2) /* write back, no write allocate */ +#define MEMWT (2<<2) /* write through, no write allocate */ +#define SHAREDEVICE (1<<2) /* shared device */ +#define STRONGORDER (0<<2) /* strong ordered */ +#define XN (1<<4) /* eXecute Never */ +#define AP_RW (3<<10) /* supervisor=RW, user=RW */ +#define AP_RO (2<<10) /* supervisor=RW, user=RO */ +#define SHARED (1<<16) /* shareable */ + +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) + +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) + +/* device mapping type */ +#define DEVICE_MEM (SHARED|AP_RW|DOMAIN0|SHAREDEVICE|DESC_SEC|XN) +/* normal memory mapping type */ +#define NORMAL_MEM (SHARED|AP_RW|DOMAIN0|MEMWBWA|DESC_SEC) + +struct mem_desc +{ + rt_uint32_t vaddr_start; + rt_uint32_t vaddr_end; + rt_uint32_t paddr_start; + rt_uint32_t attr; +}; + + +#endif diff --git a/libcpu/arm/cortex-a/stack.c b/libcpu/arm/cortex-a/stack.c index 1d3ebcb9e6..07d795ab5b 100644 --- a/libcpu/arm/cortex-a/stack.c +++ b/libcpu/arm/cortex-a/stack.c @@ -50,13 +50,20 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, *(--stk) = 0xdeadbeef; /* r2 */ *(--stk) = 0xdeadbeef; /* r1 */ *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - /* cpsr */ if ((rt_uint32_t)tentry & 0x01) *(--stk) = SVCMODE | 0x20; /* thumb mode */ else *(--stk) = SVCMODE; /* arm mode */ +#ifdef RT_USING_LWP + *(--stk) = 0; /* user lr */ + *(--stk) = 0; /* user sp*/ +#endif +#ifdef RT_USING_FPU + *(--stk) = 0; /* not use fpu*/ +#endif + /* return task's current stack address */ return (rt_uint8_t *)stk; } diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S index 2f16d16807..2e99db7218 100644 --- a/libcpu/arm/cortex-a/start_gcc.S +++ b/libcpu/arm/cortex-a/start_gcc.S @@ -6,8 +6,11 @@ * Change Logs: * Date Author Notes * 2013-07-05 Bernard the first version + * 2018-11-22 Jesven in the interrupt context, use rt_scheduler_do_irq_switch checks + * and switches to a new thread */ +#include "rtconfig.h" .equ Mode_USR, 0x10 .equ Mode_FIQ, 0x11 .equ Mode_IRQ, 0x12 @@ -19,12 +22,16 @@ .equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled .equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled +#ifdef RT_USING_FPU +.equ UND_Stack_Size, 0x00000400 +#else .equ UND_Stack_Size, 0x00000000 -.equ SVC_Stack_Size, 0x00000100 +#endif +.equ SVC_Stack_Size, 0x00000400 .equ ABT_Stack_Size, 0x00000000 .equ RT_FIQ_STACK_PGSZ, 0x00000000 -.equ RT_IRQ_STACK_PGSZ, 0x00000100 -.equ USR_Stack_Size, 0x00000100 +.equ RT_IRQ_STACK_PGSZ, 0x00000800 +.equ USR_Stack_Size, 0x00000400 #define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ) @@ -34,6 +41,7 @@ .globl stack_start .globl stack_top +.align 3 stack_start: .rept ISR_Stack_Size .byte 0 @@ -44,12 +52,38 @@ stack_top: /* reset entry */ .globl _reset _reset: - bl rt_cpu_mmu_disable +#ifdef ARCH_ARMV8 + /* Check for HYP mode */ + mrs r0, cpsr_all + and r0, r0, #0x1F + mov r8, #0x1A + cmp r0, r8 + beq overHyped + b continue + +overHyped: /* Get out of HYP mode */ + adr r1, continue + msr ELR_hyp, r1 + mrs r1, cpsr_all + and r1, r1, #0x1f ;@ CPSR_MODE_MASK + orr r1, r1, #0x13 ;@ CPSR_MODE_SUPERVISOR + msr SPSR_hyp, r1 + eret + +continue: +#endif /* set the cpu to SVC32 mode and disable interrupt */ - mrs r0, cpsr - bic r0, r0, #0x1f - orr r0, r0, #0x13 - msr cpsr_c, r0 + cps #Mode_SVC + +#ifdef RT_USING_FPU + mov r4, #0xfffffff + mcr p15, 0, r4, c1, c0, 2 +#endif + + /* disable the data alignment check */ + mrc p15, 0, r1, c1, c0, 0 + bic r1, #(1<<1) + mcr p15, 0, r1, c1, c0, 0 /* setup stack */ bl stack_setup @@ -64,6 +98,20 @@ bss_loop: strlo r0,[r1],#4 /* clear 4 bytes */ blo bss_loop /* loop until done */ +#ifdef RT_USING_SMP + mrc p15, 0, r1, c1, c0, 1 + mov r0, #(1<<6) + orr r1, r0 + mcr p15, 0, r1, c1, c0, 1 //enable smp +#endif + + /* initialize the mmu table and enable mmu */ + ldr r0, =platform_mem_desc + ldr r1, =platform_mem_desc_size + ldr r1, [r1] + bl rt_hw_init_mmu_table + bl rt_hw_mmu_init + /* call C++ constructors of global objects */ ldr r0, =__ctors_start__ ldr r1, =__ctors_end__ @@ -137,6 +185,57 @@ vector_fiq: .align 5 .globl vector_irq vector_irq: +#ifdef RT_USING_SMP + clrex + + stmfd sp!, {r0, r1} + cps #Mode_SVC + mov r0, sp /* svc_sp */ + mov r1, lr /* svc_lr */ + + cps #Mode_IRQ + sub lr, #4 + stmfd r0!, {r1, lr} /* svc_lr, svc_pc */ + stmfd r0!, {r2 - r12} + ldmfd sp!, {r1, r2} /* original r0, r1 */ + stmfd r0!, {r1 - r2} + mrs r1, spsr /* original mode */ + stmfd r0!, {r1} + +#ifdef RT_USING_LWP + stmfd r0, {r13, r14}^ /* usr_sp, usr_lr */ + sub r0, #8 +#endif +#ifdef RT_USING_FPU + /* fpu context */ + vmrs r6, fpexc + tst r6, #(1<<30) + beq 1f + vstmdb r0!, {d0-d15} + vstmdb r0!, {d16-d31} + vmrs r5, fpscr + stmfd r0!, {r5} +1: + stmfd r0!, {r6} +#endif + + /* now irq stack is clean */ + /* r0 is task svc_sp */ + /* backup r0 -> r8 */ + mov r8, r0 + + bl rt_interrupt_enter + bl rt_hw_trap_irq + bl rt_interrupt_leave + + cps #Mode_SVC + mov sp, r8 + mov r0, r8 + bl rt_scheduler_do_irq_switch + + b rt_hw_context_switch_exit + +#else stmfd sp!, {r0-r12,lr} bl rt_interrupt_enter @@ -174,6 +273,23 @@ rt_hw_context_switch_interrupt_do: stmfd sp!, {r1-r4} @ push old task's r0-r3 stmfd sp!, {r0} @ push old task's cpsr +#ifdef RT_USING_LWP + stmfd sp, {r13, r14}^ @push usr_sp, usr_lr + sub sp, #8 +#endif +#ifdef RT_USING_FPU + /* fpu context */ + vmrs r6, fpexc + tst r6, #(1<<30) + beq 1f + vstmdb sp!, {d0-d15} + vstmdb sp!, {d16-d31} + vmrs r5, fpscr + stmfd sp!, {r5} +1: + stmfd sp!, {r6} +#endif + ldr r4, =rt_interrupt_from_thread ldr r5, [r4] str sp, [r5] @ store sp in preempted tasks's TCB @@ -182,11 +298,31 @@ rt_hw_context_switch_interrupt_do: ldr r6, [r6] ldr sp, [r6] @ get new task's stack pointer +#ifdef RT_USING_FPU +/* fpu context */ + ldmfd sp!, {r6} + vmsr fpexc, r6 + tst r6, #(1<<30) + beq 1f + ldmfd sp!, {r5} + vmsr fpscr, r5 + vldmia sp!, {d16-d31} + vldmia sp!, {d0-d15} +1: +#endif + +#ifdef RT_USING_LWP + ldmfd sp, {r13, r14}^ @pop usr_sp, usr_lr + add sp, #8 +#endif + ldmfd sp!, {r4} @ pop new task's cpsr to spsr msr spsr_cxsf, r4 ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr +#endif + .macro push_svc_reg sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */ stmia sp, {r0 - r12} @/* Calling r0-r12 */ @@ -200,36 +336,107 @@ rt_hw_context_switch_interrupt_do: .endm .align 5 - .globl vector_swi +.weak vector_swi vector_swi: push_svc_reg bl rt_hw_trap_swi b . .align 5 - .globl vector_undef + .globl vector_undef vector_undef: push_svc_reg + cps #Mode_UND bl rt_hw_trap_undef +#ifdef RT_USING_FPU + ldr lr, [sp, #15*4] + ldmia sp, {r0 - r12} + add sp, sp, #17 * 4 + movs pc, lr +#endif b . .align 5 - .globl vector_pabt + .globl vector_pabt vector_pabt: push_svc_reg bl rt_hw_trap_pabt b . .align 5 - .globl vector_dabt + .globl vector_dabt vector_dabt: push_svc_reg bl rt_hw_trap_dabt b . .align 5 - .globl vector_resv + .globl vector_resv vector_resv: push_svc_reg bl rt_hw_trap_resv b . + +#ifdef RT_USING_SMP +.global set_secondary_cpu_boot_address +set_secondary_cpu_boot_address: + ldr r0, =secondary_cpu_start + + mvn r1, #0 //0xffffffff + ldr r2, =0x10000034 + str r1, [r2] + str r0, [r2, #-4] + mov pc, lr + +.global secondary_cpu_start +secondary_cpu_start: + +#ifdef RT_USING_FPU + mov r4, #0xfffffff + mcr p15, 0, r4, c1, c0, 2 +#endif + + mrc p15, 0, r1, c1, c0, 1 + mov r0, #(1<<6) + orr r1, r0 + mcr p15, 0, r1, c1, c0, 1 //enable smp + + mrc p15, 0, r0, c1, c0, 0 + bic r0, #(1<<13) + mcr p15, 0, r0, c1, c0, 0 + +#ifdef RT_USING_FPU + cps #Mode_UND + ldr sp, =und_stack_2_limit +#endif + + cps #Mode_IRQ + ldr sp, =irq_stack_2_limit + + cps #Mode_FIQ + ldr sp, =irq_stack_2_limit + + cps #Mode_SVC + ldr sp, =svc_stack_2_limit + + /* initialize the mmu table and enable mmu */ + bl rt_hw_mmu_init + + b secondary_cpu_c_start +#endif + +.bss +.align 2 //align to 2~2=4 +svc_stack_2: + .space (1 << 10) +svc_stack_2_limit: + +irq_stack_2: + .space (1 << 10) +irq_stack_2_limit: + +#ifdef RT_USING_FPU +und_stack_2: + .space (1 << 10) +und_stack_2_limit: +#endif diff --git a/libcpu/arm/cortex-a/trap.c b/libcpu/arm/cortex-a/trap.c index f3b2c26e6d..dc232a46ee 100644 --- a/libcpu/arm/cortex-a/trap.c +++ b/libcpu/arm/cortex-a/trap.c @@ -13,10 +13,8 @@ #include <board.h> #include "armv7.h" +#include "interrupt.h" -#include "gic.h" - -extern struct rt_thread *rt_current_thread; #ifdef RT_USING_FINSH extern long list_thread(void); #endif @@ -47,6 +45,39 @@ void rt_hw_show_register(struct rt_hw_exp_stack *regs) */ void rt_hw_trap_undef(struct rt_hw_exp_stack *regs) { +#ifdef RT_USING_FPU + { + uint32_t ins; + uint32_t addr; + + if (regs->cpsr & (1 << 5)) + { + /* thumb mode */ + addr = regs->pc - 2; + ins = (uint32_t)*(uint16_t*)addr; + if ((ins & (3 << 11)) != 0) + { + /* 32 bit ins */ + ins <<= 16; + ins += *(uint16_t*)(addr + 2); + } + } + else + { + addr = regs->pc - 4; + ins = *(uint32_t*)addr; + } + if ((ins & 0xe00) == 0xa00) + { + /* float ins */ + uint32_t val = (1U << 30); + + asm volatile ("vmsr fpexc, %0"::"r"(val):"memory"); + regs->pc = addr; + return; + } + } +#endif rt_kprintf("undefined instruction:\n"); rt_hw_show_register(regs); #ifdef RT_USING_FINSH @@ -130,48 +161,52 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) void rt_hw_trap_irq(void) { void *param; + int ir; rt_isr_handler_t isr_func; extern struct rt_irq_desc isr_table[]; - // vectNum = RESERVED[31:13] | CPUID[12:10] | INTERRUPT_ID[9:0] - // send ack and get ID source - uint32_t vectNum = gic_read_irq_ack(); + ir = rt_hw_interrupt_get_irq(); - // Check that INT_ID isn't 1023 or 1022 (spurious interrupt) - if (vectNum & 0x0200) + if (ir == 1023) { - gic_write_end_of_irq(vectNum); // send end of irq + /* Spurious interrupt */ + return; } - else - { - // copy the local value to the global image of CPUID - unsigned cpu = (vectNum >> 10) & 0x7; - unsigned irq = vectNum & 0x1FF; - - /* skip warning */ - cpu = cpu; - // Call the service routine stored in the handlers array. If there isn't - // one for this IRQ, then call the default handler. - /* get interrupt service routine */ - isr_func = isr_table[irq].handler; + /* get interrupt service routine */ + isr_func = isr_table[ir].handler; #ifdef RT_USING_INTERRUPT_INFO - isr_table[irq].counter++; + isr_table[ir].counter++; #endif - if (isr_func) - { - /* Interrupt for myself. */ - param = isr_table[irq].param; - /* turn to interrupt service routine */ - isr_func(irq, param); - } - - // Signal the end of the irq. - gic_write_end_of_irq(vectNum); + if (isr_func) + { + /* Interrupt for myself. */ + param = isr_table[ir].param; + /* turn to interrupt service routine */ + isr_func(ir, param); } + + /* end of interrupt */ + rt_hw_interrupt_ack(ir); } void rt_hw_trap_fiq(void) { - /* TODO */ + void *param; + int ir; + rt_isr_handler_t isr_func; + extern struct rt_irq_desc isr_table[]; + + ir = rt_hw_interrupt_get_irq(); + + /* get interrupt service routine */ + isr_func = isr_table[ir].handler; + param = isr_table[ir].param; + + /* turn to interrupt service routine */ + isr_func(ir, param); + + /* end of interrupt */ + rt_hw_interrupt_ack(ir); } + diff --git a/libcpu/arm/cortex-m0/SConscript b/libcpu/arm/cortex-m0/SConscript new file mode 100644 index 0000000000..9ff30a796b --- /dev/null +++ b/libcpu/arm/cortex-m0/SConscript @@ -0,0 +1,23 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arm/cortex-m0/context_gcc.S b/libcpu/arm/cortex-m0/context_gcc.S index d9993247e2..a504ee076e 100644 --- a/libcpu/arm/cortex-m0/context_gcc.S +++ b/libcpu/arm/cortex-m0/context_gcc.S @@ -22,7 +22,7 @@ .equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ .equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ .equ NVIC_SHPR3, 0xE000ED20 /* system priority register (3) */ - .equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */ + .equ NVIC_PENDSV_PRI, 0xFFFF0000 /* PendSV and SysTick priority value (lowest) */ .equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */ /* @@ -159,7 +159,7 @@ rt_hw_context_switch_to: MOVS R0, #1 STR R0, [R1] - /* set the PendSV exception priority */ + /* set the PendSV and SysTick exception priority */ LDR R0, =NVIC_SHPR3 LDR R1, =NVIC_PENDSV_PRI LDR R2, [R0,#0x00] /* read */ diff --git a/libcpu/arm/cortex-m0/context_iar.S b/libcpu/arm/cortex-m0/context_iar.S index 67ea808d8c..6f410d1a24 100644 --- a/libcpu/arm/cortex-m0/context_iar.S +++ b/libcpu/arm/cortex-m0/context_iar.S @@ -1,11 +1,7 @@ ;/* -; * File : context_iar.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2009, RT-Thread Development Team +; * Copyright (c) 2006-2018, RT-Thread Development Team ; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes @@ -23,7 +19,7 @@ SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception SECTION .text:CODE(2) @@ -167,7 +163,7 @@ rt_hw_context_switch_to: MOVS r0, #1 STR r0, [r1] - ; set the PendSV exception priority + ; set the PendSV and SysTick exception priority LDR r0, =NVIC_SHPR3 LDR r1, =NVIC_PENDSV_PRI LDR r2, [r0,#0x00] ; read diff --git a/libcpu/arm/cortex-m0/context_rvds.S b/libcpu/arm/cortex-m0/context_rvds.S index bf68592e63..072486587c 100644 --- a/libcpu/arm/cortex-m0/context_rvds.S +++ b/libcpu/arm/cortex-m0/context_rvds.S @@ -1,11 +1,7 @@ ;/* -; * File : context_rvds.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2009, RT-Thread Development Team +; * Copyright (c) 2006-2018, RT-Thread Development Team ; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes @@ -23,7 +19,7 @@ SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception AREA |.text|, CODE, READONLY, ALIGN=2 @@ -172,7 +168,7 @@ rt_hw_context_switch_to PROC MOVS r0, #1 STR r0, [r1] - ; set the PendSV exception priority + ; set the PendSV and SysTick exception priority LDR r0, =NVIC_SHPR3 LDR r1, =NVIC_PENDSV_PRI LDR r2, [r0,#0x00] ; read diff --git a/libcpu/arm/cortex-m0/cpuport.c b/libcpu/arm/cortex-m0/cpuport.c index f5ff8ec113..19aec42230 100644 --- a/libcpu/arm/cortex-m0/cpuport.c +++ b/libcpu/arm/cortex-m0/cpuport.c @@ -114,3 +114,22 @@ void rt_hw_hard_fault_exception(struct exception_stack_frame *contex) while (1); } + +#define SCB_CFSR (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */ +#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */ +#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */ +#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */ +#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C) /* Reset control Address Register */ +#define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */ + +#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */ +#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */ +#define SCB_CFSR_UFSR (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */ + +/** + * reset CPU + */ +RT_WEAK void rt_hw_cpu_reset(void) +{ + SCB_AIRCR = SCB_RESET_VALUE;//((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |SCB_AIRCR_SYSRESETREQ_Msk); +} diff --git a/libcpu/arm/cortex-m23/SConscript b/libcpu/arm/cortex-m23/SConscript new file mode 100644 index 0000000000..9ff30a796b --- /dev/null +++ b/libcpu/arm/cortex-m23/SConscript @@ -0,0 +1,23 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arm/cortex-m23/context_gcc.S b/libcpu/arm/cortex-m23/context_gcc.S new file mode 100644 index 0000000000..48f90413d9 --- /dev/null +++ b/libcpu/arm/cortex-m23/context_gcc.S @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2010-01-25 Bernard first version + * 2012-06-01 aozima set pendsv priority to 0xFF. + * 2012-08-17 aozima fixed bug: store r8 - r11. + * 2013-02-20 aozima port to gcc. + * 2013-06-18 aozima add restore MSP feature. + * 2013-11-04 bright fixed hardfault bug for gcc. + * 2019-03-31 xuzhuoyi port to Cortex-M23. + */ + + .cpu cortex-m23 + .fpu softvfp + .syntax unified + .thumb + .text + + .equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ + .equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ + .equ NVIC_SHPR3, 0xE000ED20 /* system priority register (3) */ + .equ NVIC_PENDSV_PRI, 0xFFFF0000 /* PendSV and SysTick priority value (lowest) */ + .equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */ + +/* + * rt_base_t rt_hw_interrupt_disable(); + */ + .global rt_hw_interrupt_disable + .type rt_hw_interrupt_disable, %function +rt_hw_interrupt_disable: + MRS R0, PRIMASK + CPSID I + BX LR + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ + .global rt_hw_interrupt_enable + .type rt_hw_interrupt_enable, %function +rt_hw_interrupt_enable: + MSR PRIMASK, R0 + BX LR + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * R0 --> from + * R1 --> to + */ + .global rt_hw_context_switch_interrupt + .type rt_hw_context_switch_interrupt, %function + .global rt_hw_context_switch + .type rt_hw_context_switch, %function +rt_hw_context_switch_interrupt: +rt_hw_context_switch: + /* set rt_thread_switch_interrupt_flag to 1 */ + LDR R2, =rt_thread_switch_interrupt_flag + LDR R3, [R2] + CMP R3, #1 + BEQ _reswitch + MOVS R3, #1 + STR R3, [R2] + + LDR R2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */ + STR R0, [R2] + +_reswitch: + LDR R2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */ + STR R1, [R2] + + LDR R0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ + LDR R1, =NVIC_PENDSVSET + STR R1, [R0] + BX LR + +/* R0 --> switch from thread stack + * R1 --> switch to thread stack + * psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack + */ + .global PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + /* disable interrupt to protect context switch */ + MRS R2, PRIMASK + CPSID I + + /* get rt_thread_switch_interrupt_flag */ + LDR R0, =rt_thread_switch_interrupt_flag + LDR R1, [R0] + CMP R1, #0x00 + BEQ pendsv_exit /* pendsv aLReady handled */ + + /* clear rt_thread_switch_interrupt_flag to 0 */ + MOVS R1, #0 + STR R1, [R0] + + LDR R0, =rt_interrupt_from_thread + LDR R1, [R0] + CMP R1, #0x00 + BEQ switch_to_thread /* skip register save at the first time */ + + MRS R1, PSP /* get from thread stack pointer */ + + SUBS R1, R1, #0x20 /* space for {R4 - R7} and {R8 - R11} */ + LDR R0, [R0] + STR R1, [R0] /* update from thread stack pointer */ + + STMIA R1!, {R4 - R7} /* push thread {R4 - R7} register to thread stack */ + + MOV R4, R8 /* mov thread {R8 - R11} to {R4 - R7} */ + MOV R5, R9 + MOV R6, R10 + MOV R7, R11 + STMIA R1!, {R4 - R7} /* push thread {R8 - R11} high register to thread stack */ +switch_to_thread: + LDR R1, =rt_interrupt_to_thread + LDR R1, [R1] + LDR R1, [R1] /* load thread stack pointer */ + + LDMIA R1!, {R4 - R7} /* pop thread {R4 - R7} register from thread stack */ + PUSH {R4 - R7} /* push {R4 - R7} to MSP for copy {R8 - R11} */ + + LDMIA R1!, {R4 - R7} /* pop thread {R8 - R11} high register from thread stack to {R4 - R7} */ + MOV R8, R4 /* mov {R4 - R7} to {R8 - R11} */ + MOV R9, R5 + MOV R10, R6 + MOV R11, R7 + + POP {R4 - R7} /* pop {R4 - R7} from MSP */ + + MSR PSP, R1 /* update stack pointer */ + +pendsv_exit: + /* restore interrupt */ + MSR PRIMASK, R2 + + MOVS R0, #0x03 + RSBS R0, R0, #0x00 + BX R0 +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * R0 --> to + */ + .global rt_hw_context_switch_to + .type rt_hw_context_switch_to, %function +rt_hw_context_switch_to: + LDR R1, =rt_interrupt_to_thread + STR R0, [R1] + + /* set from thread to 0 */ + LDR R1, =rt_interrupt_from_thread + MOVS R0, #0 + STR R0, [R1] + + /* set interrupt flag to 1 */ + LDR R1, =rt_thread_switch_interrupt_flag + MOVS R0, #1 + STR R0, [R1] + + /* set the PendSV and SysTick exception priority */ + LDR R0, =NVIC_SHPR3 + LDR R1, =NVIC_PENDSV_PRI + LDR R2, [R0,#0x00] /* read */ + ORRS R1, R1, R2 /* modify */ + STR R1, [R0] /* write-back */ + + LDR R0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ + LDR R1, =NVIC_PENDSVSET + STR R1, [R0] + NOP + /* restore MSP */ + LDR R0, =SCB_VTOR + LDR R0, [R0] + LDR R0, [R0] + NOP + MSR MSP, R0 + + /* enable interrupts at processor level */ + CPSIE I + + /* never reach here! */ + +/* compatible with old version */ + .global rt_hw_interrupt_thread_switch + .type rt_hw_interrupt_thread_switch, %function +rt_hw_interrupt_thread_switch: + BX LR + NOP + + .global HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + /* get current context */ + MRS R0, PSP /* get fault thread stack pointer */ + PUSH {LR} + BL rt_hw_hard_fault_exception + POP {PC} + + +/* + * rt_uint32_t rt_hw_interrupt_check(void); + * R0 --> state + */ + .global rt_hw_interrupt_check + .type rt_hw_interrupt_check, %function +rt_hw_interrupt_check: + MRS R0, IPSR + BX LR diff --git a/libcpu/arm/cortex-m23/context_iar.S b/libcpu/arm/cortex-m23/context_iar.S new file mode 100644 index 0000000000..c7d85cc5e2 --- /dev/null +++ b/libcpu/arm/cortex-m23/context_iar.S @@ -0,0 +1,207 @@ +;/* +; * Copyright (c) 2006-2019, RT-Thread Development Team +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Change Logs: +; * Date Author Notes +; * 2010-01-25 Bernard first version +; * 2012-06-01 aozima set pendsv priority to 0xFF. +; * 2012-08-17 aozima fixed bug: store r8 - r11. +; * 2013-06-18 aozima add restore MSP feature. +; * 2019-03-31 xuzhuoyi port to Cortex-M23. +; */ + +;/** +; * @addtogroup CORTEX-M23 +; */ +;/*@{*/ + +SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register +NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register +NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) +NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) +NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception + + SECTION .text:CODE(2) + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ + EXPORT rt_hw_interrupt_disable +rt_hw_interrupt_disable: + MRS r0, PRIMASK + CPSID I + BX LR + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ + EXPORT rt_hw_interrupt_enable +rt_hw_interrupt_enable: + MSR PRIMASK, r0 + BX LR + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ + EXPORT rt_hw_context_switch_interrupt + EXPORT rt_hw_context_switch +rt_hw_context_switch_interrupt: +rt_hw_context_switch: + ; set rt_thread_switch_interrupt_flag to 1 + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOVS r3, #0x1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] + +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + +; r0 --> switch from thread stack +; r1 --> switch to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack + EXPORT PendSV_Handler +PendSV_Handler: + + ; disable interrupt to protect context switch + MRS r2, PRIMASK + CPSID I + + ; get rt_thread_switch_interrupt_flag + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #0x00 + BEQ pendsv_exit ; pendsv already handled + + ; clear rt_thread_switch_interrupt_flag to 0 + MOVS r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CMP r1, #0x00 + BEQ switch_to_thread ; skip register save at the first time + + MRS r1, psp ; get from thread stack pointer + + SUBS r1, r1, #0x20 ; space for {r4 - r7} and {r8 - r11} + LDR r0, [r0] + STR r1, [r0] ; update from thread stack pointer + + STMIA r1!, {r4 - r7} ; push thread {r4 - r7} register to thread stack + + MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7} + MOV r5, r9 + MOV r6, r10 + MOV r7, r11 + STMIA r1!, {r4 - r7} ; push thread {r8 - r11} high register to thread stack + +switch_to_thread + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] ; load thread stack pointer + + LDMIA r1!, {r4 - r7} ; pop thread {r4 - r7} register from thread stack + PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11} + + LDMIA r1!, {r4 - r7} ; pop thread {r8 - r11} high register from thread stack to {r4 - r7} + MOV r8, r4 ; mov {r4 - r7} to {r8 - r11} + MOV r9, r5 + MOV r10, r6 + MOV r11, r7 + + POP {r4 - r7} ; pop {r4 - r7} from MSP + + MSR psp, r1 ; update stack pointer + +pendsv_exit + ; restore interrupt + MSR PRIMASK, r2 + + MOVS r0, #0x03 + RSBS r0, r0, #0x00 + BX r0 + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; * this fucntion is used to perform the first thread switch +; */ + EXPORT rt_hw_context_switch_to +rt_hw_context_switch_to: + ; set to thread + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + + ; set from thread to 0 + LDR r1, =rt_interrupt_from_thread + MOVS r0, #0x0 + STR r0, [r1] + + ; set interrupt flag to 1 + LDR r1, =rt_thread_switch_interrupt_flag + MOVS r0, #1 + STR r0, [r1] + + ; set the PendSV and SysTick exception priority + LDR r0, =NVIC_SHPR3 + LDR r1, =NVIC_PENDSV_PRI + LDR r2, [r0,#0x00] ; read + ORRS r1,r1,r2 ; modify + STR r1, [r0] ; write-back + + ; trigger the PendSV exception (causes context switch) + LDR r0, =NVIC_INT_CTRL + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + NOP + + ; restore MSP + LDR r0, =SCB_VTOR + LDR r0, [r0] + LDR r0, [r0] + NOP + MSR msp, r0 + + ; enable interrupts at processor level + CPSIE I + + ; never reach here! + +; compatible with old version + EXPORT rt_hw_interrupt_thread_switch +rt_hw_interrupt_thread_switch: + BX lr + + IMPORT rt_hw_hard_fault_exception + EXPORT HardFault_Handler +HardFault_Handler: + + ; get current context + MRS r0, psp ; get fault thread stack pointer + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {pc} + + END diff --git a/libcpu/arm/cortex-m23/context_rvds.S b/libcpu/arm/cortex-m23/context_rvds.S new file mode 100644 index 0000000000..ca381d0f8f --- /dev/null +++ b/libcpu/arm/cortex-m23/context_rvds.S @@ -0,0 +1,216 @@ +;/* +; * Copyright (c) 2006-2019, RT-Thread Development Team +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Change Logs: +; * Date Author Notes +; * 2010-01-25 Bernard first version +; * 2012-06-01 aozima set pendsv priority to 0xFF. +; * 2012-08-17 aozima fixed bug: store r8 - r11. +; * 2013-06-18 aozima add restore MSP feature. +; * 2019-03-31 xuzhuoyi port to Cortex-M23. +; */ + +;/** +; * @addtogroup CORTEX-M23 +; */ +;/*@{*/ + +SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register +NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register +NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) +NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) +NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception + + AREA |.text|, CODE, READONLY, ALIGN=2 + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ +rt_hw_interrupt_disable PROC + EXPORT rt_hw_interrupt_disable + MRS r0, PRIMASK + CPSID I + BX LR + ENDP + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ +rt_hw_interrupt_enable PROC + EXPORT rt_hw_interrupt_enable + MSR PRIMASK, r0 + BX LR + ENDP + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ +rt_hw_context_switch_interrupt + EXPORT rt_hw_context_switch_interrupt +rt_hw_context_switch PROC + EXPORT rt_hw_context_switch + + ; set rt_thread_switch_interrupt_flag to 1 + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOVS r3, #0x01 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] + +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + ENDP + +; r0 --> switch from thread stack +; r1 --> switch to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack +PendSV_Handler PROC + EXPORT PendSV_Handler + + ; disable interrupt to protect context switch + MRS r2, PRIMASK + CPSID I + + ; get rt_thread_switch_interrupt_flag + LDR r0, =rt_thread_switch_interrupt_flag + LDR r1, [r0] + CMP r1, #0x00 + BEQ pendsv_exit ; pendsv already handled + + ; clear rt_thread_switch_interrupt_flag to 0 + MOVS r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CMP r1, #0x00 + BEQ switch_to_thread ; skip register save at the first time + + MRS r1, psp ; get from thread stack pointer + + SUBS r1, r1, #0x20 ; space for {r4 - r7} and {r8 - r11} + LDR r0, [r0] + STR r1, [r0] ; update from thread stack pointer + + STMIA r1!, {r4 - r7} ; push thread {r4 - r7} register to thread stack + + MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7} + MOV r5, r9 + MOV r6, r10 + MOV r7, r11 + STMIA r1!, {r4 - r7} ; push thread {r8 - r11} high register to thread stack + +switch_to_thread + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] ; load thread stack pointer + + LDMIA r1!, {r4 - r7} ; pop thread {r4 - r7} register from thread stack + PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11} + + LDMIA r1!, {r4 - r7} ; pop thread {r8 - r11} high register from thread stack to {r4 - r7} + MOV r8, r4 ; mov {r4 - r7} to {r8 - r11} + MOV r9, r5 + MOV r10, r6 + MOV r11, r7 + + POP {r4 - r7} ; pop {r4 - r7} from MSP + + MSR psp, r1 ; update stack pointer + +pendsv_exit + ; restore interrupt + MSR PRIMASK, r2 + + MOVS r0, #0x03 + RSBS r0, r0, #0x00 + BX r0 + ENDP + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; * this fucntion is used to perform the first thread switch +; */ +rt_hw_context_switch_to PROC + EXPORT rt_hw_context_switch_to + ; set to thread + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + + ; set from thread to 0 + LDR r1, =rt_interrupt_from_thread + MOVS r0, #0x0 + STR r0, [r1] + + ; set interrupt flag to 1 + LDR r1, =rt_thread_switch_interrupt_flag + MOVS r0, #1 + STR r0, [r1] + + ; set the PendSV and SysTick exception priority + LDR r0, =NVIC_SHPR3 + LDR r1, =NVIC_PENDSV_PRI + LDR r2, [r0,#0x00] ; read + ORRS r1,r1,r2 ; modify + STR r1, [r0] ; write-back + + ; trigger the PendSV exception (causes context switch) + LDR r0, =NVIC_INT_CTRL + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + ; restore MSP + LDR r0, =SCB_VTOR + LDR r0, [r0] + LDR r0, [r0] + MSR msp, r0 + + ; enable interrupts at processor level + CPSIE I + + ; never reach here! + ENDP + +; compatible with old version +rt_hw_interrupt_thread_switch PROC + EXPORT rt_hw_interrupt_thread_switch + BX lr + ENDP + + IMPORT rt_hw_hard_fault_exception + +HardFault_Handler PROC + EXPORT HardFault_Handler + + ; get current context + MRS r0, psp ; get fault thread stack pointer + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {pc} + ENDP + + ALIGN 4 + + END diff --git a/libcpu/arm/cortex-m23/cpuport.c b/libcpu/arm/cortex-m23/cpuport.c new file mode 100644 index 0000000000..842802c866 --- /dev/null +++ b/libcpu/arm/cortex-m23/cpuport.c @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2010-01-25 Bernard first version + * 2012-05-31 aozima Merge all of the C source code into cpuport.c + * 2012-08-17 aozima fixed bug: store r8 - r11. + * 2012-12-23 aozima stack addr align to 8byte. + * 2019-03-31 xuzhuoyi port to Cortex-M23. + */ + +#include <rtthread.h> + +struct exception_stack_frame +{ + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r12; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t psr; +}; + +struct stack_frame +{ + /* r4 ~ r7 low register */ + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + + /* r8 ~ r11 high register */ + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t r11; + + struct exception_stack_frame exception_stack_frame; +}; + +/* flag in interrupt handling */ +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) +{ + struct stack_frame *stack_frame; + rt_uint8_t *stk; + unsigned long i; + + stk = stack_addr + sizeof(rt_uint32_t); + stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8); + stk -= sizeof(struct stack_frame); + + stack_frame = (struct stack_frame *)stk; + + /* init all register */ + for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++) + { + ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef; + } + + stack_frame->exception_stack_frame.r0 = (unsigned long)parameter; /* r0 : argument */ + stack_frame->exception_stack_frame.r1 = 0; /* r1 */ + stack_frame->exception_stack_frame.r2 = 0; /* r2 */ + stack_frame->exception_stack_frame.r3 = 0; /* r3 */ + stack_frame->exception_stack_frame.r12 = 0; /* r12 */ + stack_frame->exception_stack_frame.lr = (unsigned long)texit; /* lr */ + stack_frame->exception_stack_frame.pc = (unsigned long)tentry; /* entry point, pc */ + stack_frame->exception_stack_frame.psr = 0x01000000L; /* PSR */ + + /* return task's current stack address */ + return stk; +} + +extern long list_thread(void); +extern rt_thread_t rt_current_thread; +/** + * fault exception handling + */ +void rt_hw_hard_fault_exception(struct exception_stack_frame *contex) +{ + rt_kprintf("psr: 0x%08x\n", contex->psr); + rt_kprintf(" pc: 0x%08x\n", contex->pc); + rt_kprintf(" lr: 0x%08x\n", contex->lr); + rt_kprintf("r12: 0x%08x\n", contex->r12); + rt_kprintf("r03: 0x%08x\n", contex->r3); + rt_kprintf("r02: 0x%08x\n", contex->r2); + rt_kprintf("r01: 0x%08x\n", contex->r1); + rt_kprintf("r00: 0x%08x\n", contex->r0); + + rt_kprintf("hard fault on thread: %s\n", rt_current_thread->name); + +#ifdef RT_USING_FINSH + list_thread(); +#endif + + while (1); +} + +#define SCB_CFSR (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */ +#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */ +#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */ +#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */ +#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED00) /* Reset control Address Register */ +#define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */ + +#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */ +#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */ +#define SCB_CFSR_UFSR (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */ + +/** + * reset CPU + */ +RT_WEAK void rt_hw_cpu_reset(void) +{ + SCB_AIRCR = SCB_RESET_VALUE;//((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |SCB_AIRCR_SYSRESETREQ_Msk); +} diff --git a/libcpu/arm/cortex-m3/SConscript b/libcpu/arm/cortex-m3/SConscript new file mode 100644 index 0000000000..9ff30a796b --- /dev/null +++ b/libcpu/arm/cortex-m3/SConscript @@ -0,0 +1,23 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arm/cortex-m3/context_gcc.S b/libcpu/arm/cortex-m3/context_gcc.S index d17a8aa12c..2878d20082 100644 --- a/libcpu/arm/cortex-m3/context_gcc.S +++ b/libcpu/arm/cortex-m3/context_gcc.S @@ -24,7 +24,7 @@ .equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */ .equ SHPR3, 0xE000ED20 /* system priority register (3) */ - .equ PENDSV_PRI_LOWEST, 0x00FF0000 /* PendSV priority value (lowest) */ + .equ PENDSV_PRI_LOWEST, 0xFFFF0000 /* PendSV and SysTick priority value (lowest) */ /* * rt_base_t rt_hw_interrupt_disable(); @@ -140,7 +140,7 @@ rt_hw_context_switch_to: MOV R0, #1 STR R0, [R1] - /* set the PendSV exception priority */ + /* set the PendSV and SysTick exception priority */ LDR R0, =SHPR3 LDR R1, =PENDSV_PRI_LOWEST LDR.W R2, [R0,#0] /* read */ diff --git a/libcpu/arm/cortex-m3/context_iar.S b/libcpu/arm/cortex-m3/context_iar.S index 95dee8062d..7c0e69bf59 100644 --- a/libcpu/arm/cortex-m3/context_iar.S +++ b/libcpu/arm/cortex-m3/context_iar.S @@ -1,11 +1,7 @@ ;/* -; * File : context_iar.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team +; * Copyright (c) 2006-2018, RT-Thread Development Team ; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes @@ -23,7 +19,7 @@ SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception SECTION .text:CODE(2) @@ -143,7 +139,7 @@ rt_hw_context_switch_to: MOV r0, #1 STR r0, [r1] - ; set the PendSV exception priority + ; set the PendSV and SysTick exception priority LDR r0, =NVIC_SYSPRI2 LDR r1, =NVIC_PENDSV_PRI LDR.W r2, [r0,#0x00] ; read diff --git a/libcpu/arm/cortex-m3/context_rvds.S b/libcpu/arm/cortex-m3/context_rvds.S index 9a7ff10abe..a661430499 100644 --- a/libcpu/arm/cortex-m3/context_rvds.S +++ b/libcpu/arm/cortex-m3/context_rvds.S @@ -1,11 +1,7 @@ ;/* -; * File : context_rvds.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team +; * Copyright (c) 2006-2018, RT-Thread Development Team ; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes @@ -22,7 +18,7 @@ SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception AREA |.text|, CODE, READONLY, ALIGN=2 @@ -149,7 +145,7 @@ rt_hw_context_switch_to PROC MOV r0, #1 STR r0, [r1] - ; set the PendSV exception priority + ; set the PendSV and SysTick exception priority LDR r0, =NVIC_SYSPRI2 LDR r1, =NVIC_PENDSV_PRI LDR.W r2, [r0,#0x00] ; read diff --git a/libcpu/arm/cortex-m3/cpuport.c b/libcpu/arm/cortex-m3/cpuport.c index a386747750..d58782e2c5 100644 --- a/libcpu/arm/cortex-m3/cpuport.c +++ b/libcpu/arm/cortex-m3/cpuport.c @@ -11,6 +11,7 @@ * 2012-12-23 aozima stack addr align to 8byte. * 2012-12-29 Bernard Add exception hook. * 2013-07-09 aozima enhancement hard fault exception handler. + * 2019-07-03 yangjie add __rt_ffs() for armclang. */ #include <rtthread.h> @@ -382,6 +383,24 @@ __asm int __rt_ffs(int value) exit BX lr } +#elif defined(__CLANG_ARM) +int __rt_ffs(int value) +{ + __asm volatile( + "CMP r0, #0x00 \n" + "BEQ 1f \n" + + "RBIT r0, r0 \n" + "CLZ r0, r0 \n" + "ADDS r0, r0, #0x01 \n" + + "1: \n" + + : "=r"(value) + : "r"(value) + ); + return value; +} #elif defined(__IAR_SYSTEMS_ICC__) int __rt_ffs(int value) { diff --git a/libcpu/arm/cortex-m33/SConscript b/libcpu/arm/cortex-m33/SConscript new file mode 100644 index 0000000000..9ff30a796b --- /dev/null +++ b/libcpu/arm/cortex-m33/SConscript @@ -0,0 +1,23 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arm/cortex-m33/context_gcc.S b/libcpu/arm/cortex-m33/context_gcc.S new file mode 100644 index 0000000000..27596bf787 --- /dev/null +++ b/libcpu/arm/cortex-m33/context_gcc.S @@ -0,0 +1,293 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-10-11 Bernard first version + * 2012-01-01 aozima support context switch load/store FPU register. + * 2013-06-18 aozima add restore MSP feature. + * 2013-06-23 aozima support lazy stack optimized. + * 2018-07-24 aozima enhancement hard fault exception handler. + */ + +/** + * @addtogroup cortex-m4 + */ +/*@{*/ + +.cpu cortex-m4 +.syntax unified +.thumb +.text + +.equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ +.equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ +.equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */ +.equ NVIC_PENDSV_PRI, 0xFFFF0000 /* PendSV and SysTick priority value (lowest) */ +.equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */ + +/* + * rt_base_t rt_hw_interrupt_disable(); + */ +.global rt_hw_interrupt_disable +.type rt_hw_interrupt_disable, %function +rt_hw_interrupt_disable: + MRS r0, PRIMASK + CPSID I + BX LR + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ +.global rt_hw_interrupt_enable +.type rt_hw_interrupt_enable, %function +rt_hw_interrupt_enable: + MSR PRIMASK, r0 + BX LR + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * r0 --> from + * r1 --> to + */ +.global rt_hw_context_switch_interrupt +.type rt_hw_context_switch_interrupt, %function +.global rt_hw_context_switch +.type rt_hw_context_switch, %function + +rt_hw_context_switch_interrupt: +rt_hw_context_switch: + /* set rt_thread_switch_interrupt_flag to 1 */ + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */ + STR r0, [r2] + +_reswitch: + LDR r2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */ + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + +/* r0 --> switch from thread stack + * r1 --> switch to thread stack + * psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack + */ +.global PendSV_Handler +.type PendSV_Handler, %function +PendSV_Handler: + /* disable interrupt to protect context switch */ + MRS r2, PRIMASK + CPSID I + + /* get rt_thread_switch_interrupt_flag */ + LDR r0, =rt_thread_switch_interrupt_flag /* r0 = &rt_thread_switch_interrupt_flag */ + LDR r1, [r0] /* r1 = *r1 */ + CMP r1, #0x00 /* compare r1 == 0x00 */ + BNE schedule + MSR PRIMASK, r2 /* if r1 == 0x00, do msr PRIMASK, r2 */ + BX lr /* if r1 == 0x00, do bx lr */ + +schedule: + PUSH {r2} /* store interrupt state */ + + /* clear rt_thread_switch_interrupt_flag to 0 */ + MOV r1, #0x00 /* r1 = 0x00 */ + STR r1, [r0] /* *r0 = r1 */ + + /* skip register save at the first time */ + LDR r0, =rt_interrupt_from_thread /* r0 = &rt_interrupt_from_thread */ + LDR r1, [r0] /* r1 = *r0 */ + CBZ r1, switch_to_thread /* if r1 == 0, goto switch_to_thread */ + + /* Whether TrustZone thread stack exists */ + LDR r1, =rt_trustzone_current_context /* r1 = &rt_secure_current_context */ + LDR r1, [r1] /* r1 = *r1 */ + CBZ r1, contex_ns_store /* if r1 == 0, goto contex_ns_store */ + + /*call TrustZone fun, Save TrustZone stack */ + STMFD sp!, {r0-r1, lr} /* push register */ + MOV r0, r1 /* r0 = rt_secure_current_context */ + BL rt_trustzone_context_store /* call TrustZone store fun */ + LDMFD sp!, {r0-r1, lr} /* pop register */ + + /* check break from TrustZone */ + MOV r2, lr /* r2 = lr */ + TST r2, #0x40 /* if EXC_RETURN[6] is 1, TrustZone stack was used */ + BEQ contex_ns_store /* if r2 & 0x40 == 0, goto contex_ns_store */ + + /* push PSPLIM CONTROL PSP LR current_context to stack */ + MRS r3, psplim /* r3 = psplim */ + MRS r4, control /* r4 = control */ + MRS r5, psp /* r5 = psp */ + STMFD r5!, {r1-r4} /* push to thread stack */ + + /* update from thread stack pointer */ + LDR r0, [r0] /* r0 = rt_thread_switch_interrupt_flag */ + STR r5, [r0] /* *r0 = r5 */ + b switch_to_thread /* goto switch_to_thread */ + +contex_ns_store: + + MRS r1, psp /* get from thread stack pointer */ + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + TST lr, #0x10 /* if(!EXC_RETURN[4]) */ + VSTMDBEQ r1!, {d8 - d15} /* push FPU register s16~s31 */ +#endif + + STMFD r1!, {r4 - r11} /* push r4 - r11 register */ + + LDR r2, =rt_trustzone_current_context /* r2 = &rt_secure_current_context */ + LDR r2, [r2] /* r2 = *r2 */ + MOV r3, lr /* r3 = lr */ + MRS r4, psplim /* r4 = psplim */ + MRS r5, control /* r5 = control */ + STMFD r1!, {r2-r5} /* push to thread stack */ + + LDR r0, [r0] + STR r1, [r0] /* update from thread stack pointer */ + +switch_to_thread: + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] /* load thread stack pointer */ + + /* update current TrustZone context */ + LDMFD r1!, {r2-r5} /* pop thread stack */ + MSR psplim, r4 /* psplim = r4 */ + MSR control, r5 /* control = r5 */ + MOV lr, r3 /* lr = r3 */ + LDR r6, =rt_trustzone_current_context /* r6 = &rt_secure_current_context */ + STR r2, [r6] /* *r6 = r2 */ + MOV r0, r2 /* r0 = r2 */ + + /* Whether TrustZone thread stack exists */ + CBZ r0, contex_ns_load /* if r0 == 0, goto contex_ns_load */ + PUSH {r1, r3} /* push lr, thread_stack */ + BL rt_trustzone_context_load /* call TrustZone load fun */ + POP {r1, r3} /* pop lr, thread_stack */ + MOV lr, r3 /* lr = r1 */ + TST r3, #0x40 /* if EXC_RETURN[6] is 1, TrustZone stack was used */ + BEQ contex_ns_load /* if r1 & 0x40 == 0, goto contex_ns_load */ + B pendsv_exit + +contex_ns_load: + LDMFD r1!, {r4 - r11} /* pop r4 - r11 register */ + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + TST lr, #0x10 /* if(!EXC_RETURN[4]) */ + VLDMIAEQ r1!, {d8 - d15} /* pop FPU register s16~s31 */ +#endif + +pendsv_exit: + MSR psp, r1 /* update stack pointer */ + /* restore interrupt */ + POP {r2} + MSR PRIMASK, r2 + + BX lr + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * r0 --> to + */ +.global rt_hw_context_switch_to +.type rt_hw_context_switch_to, %function +rt_hw_context_switch_to: + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) + /* CLEAR CONTROL.FPCA */ + MRS r2, CONTROL /* read */ + BIC r2, #0x04 /* modify */ + MSR CONTROL, r2 /* write-back */ +#endif + + /* set from thread to 0 */ + LDR r1, =rt_interrupt_from_thread + MOV r0, #0x0 + STR r0, [r1] + + /* set interrupt flag to 1 */ + LDR r1, =rt_thread_switch_interrupt_flag + MOV r0, #1 + STR r0, [r1] + + /* set the PendSV and SysTick exception priority */ + LDR r0, =NVIC_SYSPRI2 + LDR r1, =NVIC_PENDSV_PRI + LDR.W r2, [r0,#0x00] /* read */ + ORR r1,r1,r2 /* modify */ + STR r1, [r0] /* write-back */ + + LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */ + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + /* restore MSP */ + LDR r0, =SCB_VTOR + LDR r0, [r0] + LDR r0, [r0] + NOP + MSR msp, r0 + + /* enable interrupts at processor level */ + CPSIE F + CPSIE I + + /* never reach here! */ + +/* compatible with old version */ +.global rt_hw_interrupt_thread_switch +.type rt_hw_interrupt_thread_switch, %function +rt_hw_interrupt_thread_switch: + BX lr + NOP + +.global HardFault_Handler +.type HardFault_Handler, %function +HardFault_Handler: + /* get current context */ + MRS r0, msp /* get fault context from handler. */ + TST lr, #0x04 /* if(!EXC_RETURN[2]) */ + BEQ get_sp_done + MRS r0, psp /* get fault context from thread. */ +get_sp_done: + + STMFD r0!, {r4 - r11} /* push r4 - r11 register */ + + LDR r2, =rt_trustzone_current_context /* r2 = &rt_secure_current_context */ + LDR r2, [r2] /* r2 = *r2 */ + MOV r3, lr /* r3 = lr */ + MRS r4, psplim /* r4 = psplim */ + MRS r5, control /* r5 = control */ + STMFD r0!, {r2-r5} /* push to thread stack */ + + STMFD r0!, {lr} /* push exec_return register */ + + TST lr, #0x04 /* if(!EXC_RETURN[2]) */ + BEQ update_msp + MSR psp, r0 /* update stack pointer to PSP. */ + B update_done +update_msp: + MSR msp, r0 /* update stack pointer to MSP. */ +update_done: + + PUSH {LR} + BL rt_hw_hard_fault_exception + POP {LR} + + ORR lr, lr, #0x04 + BX lr diff --git a/libcpu/arm/cortex-m33/context_iar.S b/libcpu/arm/cortex-m33/context_iar.S new file mode 100644 index 0000000000..67cf2727a2 --- /dev/null +++ b/libcpu/arm/cortex-m33/context_iar.S @@ -0,0 +1,300 @@ +;/* +; * Copyright (c) 2006-2018, RT-Thread Development Team +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Change Logs: +; * Date Author Notes +; * 2009-01-17 Bernard first version +; * 2009-09-27 Bernard add protect when contex switch occurs +; * 2012-01-01 aozima support context switch load/store FPU register. +; * 2013-06-18 aozima add restore MSP feature. +; * 2013-06-23 aozima support lazy stack optimized. +; * 2018-07-24 aozima enhancement hard fault exception handler. +; */ + +;/** +; * @addtogroup cortex-m33 +; */ +;/*@{*/ + +SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register +NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register +NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) +NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) +NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception + + SECTION .text:CODE(2) + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + IMPORT rt_trustzone_current_context + IMPORT rt_trustzone_context_load + IMPORT rt_trustzone_context_store + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ + EXPORT rt_hw_interrupt_disable +rt_hw_interrupt_disable: + MRS r0, PRIMASK + CPSID I + BX LR + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ + EXPORT rt_hw_interrupt_enable +rt_hw_interrupt_enable: + MSR PRIMASK, r0 + BX LR + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ + EXPORT rt_hw_context_switch_interrupt + EXPORT rt_hw_context_switch +rt_hw_context_switch_interrupt: +rt_hw_context_switch: + ; set rt_thread_switch_interrupt_flag to 1 + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] + +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + +; r0 --> switch from thread stack +; r1 --> switch to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack + EXPORT PendSV_Handler +PendSV_Handler: + + ; disable interrupt to protect context switch + MRS r2, PRIMASK + CPSID I + + ; get rt_thread_switch_interrupt_flag + LDR r0, =rt_thread_switch_interrupt_flag ; r0 = &rt_thread_switch_interrupt_flag + LDR r1, [r0] ; r1 = *r1 + CMP r1, #0x00 ; compare r1 == 0x00 + BNE schedule + MSR PRIMASK, r2 ; if r1 == 0x00, do msr PRIMASK, r2 + BX lr ; if r1 == 0x00, do bx lr + +schedule + PUSH {r2} ; store interrupt state + + ; clear rt_thread_switch_interrupt_flag to 0 + MOV r1, #0x00 ; r1 = 0x00 + STR r1, [r0] ; *r0 = r1 + + ; skip register save at the first time + LDR r0, =rt_interrupt_from_thread ; r0 = &rt_interrupt_from_thread + LDR r1, [r0] ; r1 = *r0 + CBZ r1, switch_to_thread ; if r1 == 0, goto switch_to_thread + + ; Whether TrustZone thread stack exists + LDR r1, =rt_trustzone_current_context ; r1 = &rt_secure_current_context + LDR r1, [r1] ; r1 = *r1 + CBZ r1, contex_ns_store ; if r1 == 0, goto contex_ns_store + + ;call TrustZone fun, Save TrustZone stack + STMFD sp!, {r0-r1, lr} ; push register + MOV r0, r1 ; r0 = rt_secure_current_context + BL rt_trustzone_context_store ; call TrustZone store fun + LDMFD sp!, {r0-r1, lr} ; pop register + + ; check break from TrustZone + MOV r2, lr ; r2 = lr + TST r2, #0x40 ; if EXC_RETURN[6] is 1, TrustZone stack was used + BEQ contex_ns_store ; if r2 & 0x40 == 0, goto contex_ns_store + + ; push PSPLIM CONTROL PSP LR current_context to stack + MRS r3, psplim ; r3 = psplim + MRS r4, control ; r4 = control + MRS r5, psp ; r5 = psp + STMFD r5!, {r1-r4} ; push to thread stack + + ; update from thread stack pointer + LDR r0, [r0] ; r0 = rt_thread_switch_interrupt_flag + STR r5, [r0] ; *r0 = r5 + b switch_to_thread ; goto switch_to_thread + +contex_ns_store + + MRS r1, psp ; get from thread stack pointer + +#if defined ( __ARMVFP__ ) + TST lr, #0x10 ; if(!EXC_RETURN[4]) + BNE skip_push_fpu + VSTMDB r1!, {d8 - d15} ; push FPU register s16~s31 +skip_push_fpu +#endif + + STMFD r1!, {r4 - r11} ; push r4 - r11 register + + LDR r2, =rt_trustzone_current_context ; r2 = &rt_secure_current_context + LDR r2, [r2] ; r2 = *r2 + MOV r3, lr ; r3 = lr + MRS r4, psplim ; r4 = psplim + MRS r5, control ; r5 = control + STMFD r1!, {r2-r5} ; push to thread stack + + LDR r0, [r0] + STR r1, [r0] ; update from thread stack pointer + +switch_to_thread + + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] ; load thread stack pointer + + ; update current TrustZone context + LDMFD r1!, {r2-r5} ; pop thread stack + MSR psplim, r4 ; psplim = r4 + MSR control, r5 ; control = r5 + MOV lr, r3 ; lr = r3 + LDR r6, =rt_trustzone_current_context ; r6 = &rt_secure_current_context + STR r2, [r6] ; *r6 = r2 + MOV r0, r2 ; r0 = r2 + + ; Whether TrustZone thread stack exists + CBZ r0, contex_ns_load ; if r0 == 0, goto contex_ns_load + PUSH {r1, r3} ; push lr, thread_stack + BL rt_trustzone_context_load ; call TrustZone load fun + POP {r1, r3} ; pop lr, thread_stack + MOV lr, r3 ; lr = r1 + TST r3, #0x40 ; if EXC_RETURN[6] is 1, TrustZone stack was used + BEQ contex_ns_load ; if r1 & 0x40 == 0, goto contex_ns_load + B pendsv_exit + +contex_ns_load + LDMFD r1!, {r4 - r11} ; pop r4 - r11 register + +#if defined ( __ARMVFP__ ) + TST lr, #0x10 ; if(!EXC_RETURN[4]) + BNE skip_pop_fpu + VLDMIA r1!, {d8 - d15} ; pop FPU register s16~s31 +skip_pop_fpu +#endif + +pendsv_exit + MSR psp, r1 ; update stack pointer + ; restore interrupt + POP {r2} + MSR PRIMASK, r2 + + BX lr + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; */ + EXPORT rt_hw_context_switch_to +rt_hw_context_switch_to: + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + +#if defined ( __ARMVFP__ ) + ; CLEAR CONTROL.FPCA + MRS r2, CONTROL ; read + BIC r2, r2, #0x04 ; modify + MSR CONTROL, r2 ; write-back +#endif + + ; set from thread to 0 + LDR r1, =rt_interrupt_from_thread + MOV r0, #0x0 + STR r0, [r1] + + ; set interrupt flag to 1 + LDR r1, =rt_thread_switch_interrupt_flag + MOV r0, #1 + STR r0, [r1] + + ; set the PendSV and SysTick exception priority + LDR r0, =NVIC_SYSPRI2 + LDR r1, =NVIC_PENDSV_PRI + LDR.W r2, [r0,#0x00] ; read + ORR r1,r1,r2 ; modify + STR r1, [r0] ; write-back + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + ; restore MSP + LDR r0, =SCB_VTOR + LDR r0, [r0] + LDR r0, [r0] + NOP + MSR msp, r0 + + ; enable interrupts at processor level + CPSIE F + CPSIE I + + ; never reach here! + +; compatible with old version + EXPORT rt_hw_interrupt_thread_switch +rt_hw_interrupt_thread_switch: + BX lr + + IMPORT rt_hw_hard_fault_exception + EXPORT HardFault_Handler +HardFault_Handler: + + ; get current context + MRS r0, msp ; get fault context from handler. + TST lr, #0x04 ; if(!EXC_RETURN[2]) + BEQ get_sp_done + MRS r0, psp ; get fault context from thread. +get_sp_done + + STMFD r0!, {r4 - r11} ; push r4 - r11 register + + LDR r2, =rt_trustzone_current_context ; r2 = &rt_secure_current_context + LDR r2, [r2] ; r2 = *r2 + MOV r3, lr ; r3 = lr + MRS r4, psplim ; r4 = psplim + MRS r5, control ; r5 = control + STMFD r0!, {r2-r5} ; push to thread stack + + STMFD r0!, {lr} ; push exec_return register + + TST lr, #0x04 ; if(!EXC_RETURN[2]) + BEQ update_msp + MSR psp, r0 ; update stack pointer to PSP. + B update_done +update_msp + MSR msp, r0 ; update stack pointer to MSP. +update_done + + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {lr} + + ORR lr, lr, #0x04 + BX lr + + END diff --git a/libcpu/arm/cortex-m33/context_rvds.S b/libcpu/arm/cortex-m33/context_rvds.S new file mode 100644 index 0000000000..dc22ead7c5 --- /dev/null +++ b/libcpu/arm/cortex-m33/context_rvds.S @@ -0,0 +1,306 @@ +;/* +;* Copyright (c) 2006-2018, RT-Thread Development Team +;* +;* SPDX-License-Identifier: Apache-2.0 +;* +; * Change Logs: +; * Date Author Notes +; * 2009-01-17 Bernard first version. +; * 2012-01-01 aozima support context switch load/store FPU register. +; * 2013-06-18 aozima add restore MSP feature. +; * 2013-06-23 aozima support lazy stack optimized. +; * 2018-07-24 aozima enhancement hard fault exception handler. +; */ + +;/** +; * @addtogroup cortex-m33 +; */ +;/*@{*/ + +SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register +NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register +NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) +NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) +NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception + + AREA |.text|, CODE, READONLY, ALIGN=2 + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_thread_switch_interrupt_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + IMPORT rt_trustzone_current_context + IMPORT rt_trustzone_context_load + IMPORT rt_trustzone_context_store + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ +rt_hw_interrupt_disable PROC + EXPORT rt_hw_interrupt_disable + MRS r0, PRIMASK + CPSID I + BX LR + ENDP + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ +rt_hw_interrupt_enable PROC + EXPORT rt_hw_interrupt_enable + MSR PRIMASK, r0 + BX LR + ENDP + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ +rt_hw_context_switch_interrupt + EXPORT rt_hw_context_switch_interrupt +rt_hw_context_switch PROC + EXPORT rt_hw_context_switch + + ; set rt_thread_switch_interrupt_flag to 1 + LDR r2, =rt_thread_switch_interrupt_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOV r3, #1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] + +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + ENDP + +; r0 --> switch from thread stack +; r1 --> switch to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack +PendSV_Handler PROC + EXPORT PendSV_Handler + + ; disable interrupt to protect context switch + MRS r2, PRIMASK ; R2 = PRIMASK + CPSID I ; disable all interrupt + + ; get rt_thread_switch_interrupt_flag + LDR r0, =rt_thread_switch_interrupt_flag ; r0 = &rt_thread_switch_interrupt_flag + LDR r1, [r0] ; r1 = *r1 + CMP r1, #0x00 ; compare r1 == 0x00 + BNE schedule + MSR PRIMASK, r2 ; if r1 == 0x00, do msr PRIMASK, r2 + BX lr ; if r1 == 0x00, do bx lr + +schedule + PUSH {r2} ; store interrupt state + + ; clear rt_thread_switch_interrupt_flag to 0 + MOV r1, #0x00 ; r1 = 0x00 + STR r1, [r0] ; *r0 = r1 + + ; skip register save at the first time + LDR r0, =rt_interrupt_from_thread ; r0 = &rt_interrupt_from_thread + LDR r1, [r0] ; r1 = *r0 + CBZ r1, switch_to_thread ; if r1 == 0, goto switch_to_thread + + ; Whether TrustZone thread stack exists + LDR r1, =rt_trustzone_current_context ; r1 = &rt_secure_current_context + LDR r1, [r1] ; r1 = *r1 + CBZ r1, contex_ns_store ; if r1 == 0, goto contex_ns_store + + ;call TrustZone fun, Save TrustZone stack + STMFD sp!, {r0-r1, lr} ; push register + MOV r0, r1 ; r0 = rt_secure_current_context + BL rt_trustzone_context_store ; call TrustZone store fun + LDMFD sp!, {r0-r1, lr} ; pop register + + ; check break from TrustZone + MOV r2, lr ; r2 = lr + TST r2, #0x40 ; if EXC_RETURN[6] is 1, TrustZone stack was used + BEQ contex_ns_store ; if r2 & 0x40 == 0, goto contex_ns_store + + ; push PSPLIM CONTROL PSP LR current_context to stack + MRS r3, psplim ; r3 = psplim + MRS r4, control ; r4 = control + MRS r5, psp ; r5 = psp + STMFD r5!, {r1-r4} ; push to thread stack + + ; update from thread stack pointer + LDR r0, [r0] ; r0 = rt_thread_switch_interrupt_flag + STR r5, [r0] ; *r0 = r5 + b switch_to_thread ; goto switch_to_thread + +contex_ns_store + + MRS r1, psp ; get from thread stack pointer + + IF {FPU} != "SoftVFP" + TST lr, #0x10 ; if(!EXC_RETURN[4]) + VSTMFDEQ r1!, {d8 - d15} ; push FPU register s16~s31 + ENDIF + + STMFD r1!, {r4 - r11} ; push r4 - r11 register + + LDR r2, =rt_trustzone_current_context ; r2 = &rt_secure_current_context + LDR r2, [r2] ; r2 = *r2 + MOV r3, lr ; r3 = lr + MRS r4, psplim ; r4 = psplim + MRS r5, control ; r5 = control + STMFD r1!, {r2-r5} ; push to thread stack + + LDR r0, [r0] + STR r1, [r0] ; update from thread stack pointer + +switch_to_thread + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] ; load thread stack pointer + + ; update current TrustZone context + LDMFD r1!, {r2-r5} ; pop thread stack + MSR psplim, r4 ; psplim = r4 + MSR control, r5 ; control = r5 + MOV lr, r3 ; lr = r3 + LDR r6, =rt_trustzone_current_context ; r6 = &rt_secure_current_context + STR r2, [r6] ; *r6 = r2 + MOV r0, r2 ; r0 = r2 + + ; Whether TrustZone thread stack exists + CBZ r0, contex_ns_load ; if r0 == 0, goto contex_ns_load + PUSH {r1, r3} ; push lr, thread_stack + BL rt_trustzone_context_load ; call TrustZone load fun + POP {r1, r3} ; pop lr, thread_stack + MOV lr, r3 ; lr = r1 + TST r3, #0x40 ; if EXC_RETURN[6] is 1, TrustZone stack was used + BEQ contex_ns_load ; if r1 & 0x40 == 0, goto contex_ns_load + B pendsv_exit + +contex_ns_load + LDMFD r1!, {r4 - r11} ; pop r4 - r11 register + + IF {FPU} != "SoftVFP" + TST lr, #0x10 ; if(!EXC_RETURN[4]) + VLDMFDEQ r1!, {d8 - d15} ; pop FPU register s16~s31 + ENDIF + +pendsv_exit + MSR psp, r1 ; update stack pointer + ; restore interrupt + POP {r2} + MSR PRIMASK, r2 + + BX lr + ENDP + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; * this fucntion is used to perform the first thread switch +; */ +rt_hw_context_switch_to PROC + EXPORT rt_hw_context_switch_to + ; set to thread + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + + IF {FPU} != "SoftVFP" + ; CLEAR CONTROL.FPCA + MRS r2, CONTROL ; read + BIC r2, #0x04 ; modify + MSR CONTROL, r2 ; write-back + ENDIF + + ; set from thread to 0 + LDR r1, =rt_interrupt_from_thread + MOV r0, #0x0 + STR r0, [r1] + + ; set interrupt flag to 1 + LDR r1, =rt_thread_switch_interrupt_flag + MOV r0, #1 + STR r0, [r1] + + ; set the PendSV and SysTick exception priority + LDR r0, =NVIC_SYSPRI2 + LDR r1, =NVIC_PENDSV_PRI + LDR.W r2, [r0,#0x00] ; read + ORR r1,r1,r2 ; modify + STR r1, [r0] ; write-back + + ; trigger the PendSV exception (causes context switch) + LDR r0, =NVIC_INT_CTRL + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + ; restore MSP + LDR r0, =SCB_VTOR + LDR r0, [r0] + LDR r0, [r0] + MSR msp, r0 + + ; enable interrupts at processor level + CPSIE F + CPSIE I + + ; never reach here! + ENDP + +; compatible with old version +rt_hw_interrupt_thread_switch PROC + EXPORT rt_hw_interrupt_thread_switch + BX lr + ENDP + + IMPORT rt_hw_hard_fault_exception + EXPORT HardFault_Handler +HardFault_Handler PROC + + ; get current context + MRS r0, msp ;get fault context from handler + TST lr, #0x04 ;if(!EXC_RETURN[2]) + BEQ get_sp_done + MRS r0, psp ;get fault context from thread +get_sp_done + + STMFD r0!, {r4 - r11} ; push r4 - r11 register + + LDR r2, =rt_trustzone_current_context ; r2 = &rt_secure_current_context + LDR r2, [r2] ; r2 = *r2 + MOV r3, lr ; r3 = lr + MRS r4, psplim ; r4 = psplim + MRS r5, control ; r5 = control + STMFD r0!, {r2-r5} ; push to thread stack + + STMFD r0!, {lr} ; push exec_return register + + TST lr, #0x04 ; if(!EXC_RETURN[2]) + BEQ update_msp + MSR psp, r0 ; update stack pointer to PSP + B update_done +update_msp + MSR msp, r0 ; update stack pointer to MSP +update_done + + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {lr} + + ORR lr, lr, #0x04 + BX lr + ENDP + + ALIGN 4 + + END diff --git a/libcpu/arm/cortex-m33/cpuport.c b/libcpu/arm/cortex-m33/cpuport.c new file mode 100644 index 0000000000..a589ba3462 --- /dev/null +++ b/libcpu/arm/cortex-m33/cpuport.c @@ -0,0 +1,510 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-10-21 Bernard the first version. + * 2011-10-27 aozima update for cortex-M4 FPU. + * 2011-12-31 aozima fixed stack align issues. + * 2012-01-01 aozima support context switch load/store FPU register. + * 2012-12-11 lgnq fixed the coding style. + * 2012-12-23 aozima stack addr align to 8byte. + * 2012-12-29 Bernard Add exception hook. + * 2013-06-23 aozima support lazy stack optimized. + * 2018-07-24 aozima enhancement hard fault exception handler. + * 2019-07-03 yangjie add __rt_ffs() for armclang. + */ + +#include <rtthread.h> + +#if /* ARMCC */ ( (defined ( __CC_ARM ) && defined ( __TARGET_FPU_VFP )) \ + /* Clang */ || (defined ( __CLANG_ARM ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) \ + /* IAR */ || (defined ( __ICCARM__ ) && defined ( __ARMVFP__ )) \ + /* GNU */ || (defined ( __GNUC__ ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) ) +#define USE_FPU 1 +#else +#define USE_FPU 0 +#endif + +/* exception and interrupt handler table */ +rt_uint32_t rt_interrupt_from_thread; +rt_uint32_t rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +/* exception hook */ +static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL; + +struct exception_stack_frame +{ + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r12; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t psr; +}; + +struct stack_frame +{ + rt_uint32_t tz; + rt_uint32_t lr; + rt_uint32_t psplim; + rt_uint32_t control; + + /* r4 ~ r11 register */ + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t r11; + + struct exception_stack_frame exception_stack_frame; +}; + +struct exception_stack_frame_fpu +{ + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r12; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t psr; + +#if USE_FPU + /* FPU register */ + rt_uint32_t S0; + rt_uint32_t S1; + rt_uint32_t S2; + rt_uint32_t S3; + rt_uint32_t S4; + rt_uint32_t S5; + rt_uint32_t S6; + rt_uint32_t S7; + rt_uint32_t S8; + rt_uint32_t S9; + rt_uint32_t S10; + rt_uint32_t S11; + rt_uint32_t S12; + rt_uint32_t S13; + rt_uint32_t S14; + rt_uint32_t S15; + rt_uint32_t FPSCR; + rt_uint32_t NO_NAME; +#endif +}; + +struct stack_frame_fpu +{ + rt_uint32_t flag; + + /* r4 ~ r11 register */ + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t r11; + +#if USE_FPU + /* FPU register s16 ~ s31 */ + rt_uint32_t s16; + rt_uint32_t s17; + rt_uint32_t s18; + rt_uint32_t s19; + rt_uint32_t s20; + rt_uint32_t s21; + rt_uint32_t s22; + rt_uint32_t s23; + rt_uint32_t s24; + rt_uint32_t s25; + rt_uint32_t s26; + rt_uint32_t s27; + rt_uint32_t s28; + rt_uint32_t s29; + rt_uint32_t s30; + rt_uint32_t s31; +#endif + + struct exception_stack_frame_fpu exception_stack_frame; +}; + +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) +{ + struct stack_frame *stack_frame; + rt_uint8_t *stk; + unsigned long i; + + stk = stack_addr + sizeof(rt_uint32_t); + stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8); + stk -= sizeof(struct stack_frame); + + stack_frame = (struct stack_frame *)stk; + + /* init all register */ + for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++) + { + ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef; + } + + stack_frame->exception_stack_frame.r0 = (unsigned long)parameter; /* r0 : argument */ + stack_frame->exception_stack_frame.r1 = 0; /* r1 */ + stack_frame->exception_stack_frame.r2 = 0; /* r2 */ + stack_frame->exception_stack_frame.r3 = 0; /* r3 */ + stack_frame->exception_stack_frame.r12 = 0; /* r12 */ + stack_frame->exception_stack_frame.lr = (unsigned long)texit; /* lr */ + stack_frame->exception_stack_frame.pc = (unsigned long)tentry; /* entry point, pc */ + stack_frame->exception_stack_frame.psr = 0x01000000L; /* PSR */ + + stack_frame->tz = 0x00; + stack_frame->lr = 0xFFFFFFBC; + stack_frame->psplim = 0x00; + stack_frame->control = 0x00; + + /* return task's current stack address */ + return stk; +} + +/** + * This function set the hook, which is invoked on fault exception handling. + * + * @param exception_handle the exception handling hook function. + */ +void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context)) +{ + rt_exception_hook = exception_handle; +} + +#define SCB_CFSR (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */ +#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */ +#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */ +#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */ +#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C) /* Reset control Address Register */ +#define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */ + +#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */ +#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */ +#define SCB_CFSR_UFSR (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */ + +#ifdef RT_USING_FINSH +static void usage_fault_track(void) +{ + rt_kprintf("usage fault:\n"); + rt_kprintf("SCB_CFSR_UFSR:0x%02X ", SCB_CFSR_UFSR); + + if(SCB_CFSR_UFSR & (1<<0)) + { + /* [0]:UNDEFINSTR */ + rt_kprintf("UNDEFINSTR "); + } + + if(SCB_CFSR_UFSR & (1<<1)) + { + /* [1]:INVSTATE */ + rt_kprintf("INVSTATE "); + } + + if(SCB_CFSR_UFSR & (1<<2)) + { + /* [2]:INVPC */ + rt_kprintf("INVPC "); + } + + if(SCB_CFSR_UFSR & (1<<3)) + { + /* [3]:NOCP */ + rt_kprintf("NOCP "); + } + + if(SCB_CFSR_UFSR & (1<<8)) + { + /* [8]:UNALIGNED */ + rt_kprintf("UNALIGNED "); + } + + if(SCB_CFSR_UFSR & (1<<9)) + { + /* [9]:DIVBYZERO */ + rt_kprintf("DIVBYZERO "); + } + + rt_kprintf("\n"); +} + +static void bus_fault_track(void) +{ + rt_kprintf("bus fault:\n"); + rt_kprintf("SCB_CFSR_BFSR:0x%02X ", SCB_CFSR_BFSR); + + if(SCB_CFSR_BFSR & (1<<0)) + { + /* [0]:IBUSERR */ + rt_kprintf("IBUSERR "); + } + + if(SCB_CFSR_BFSR & (1<<1)) + { + /* [1]:PRECISERR */ + rt_kprintf("PRECISERR "); + } + + if(SCB_CFSR_BFSR & (1<<2)) + { + /* [2]:IMPRECISERR */ + rt_kprintf("IMPRECISERR "); + } + + if(SCB_CFSR_BFSR & (1<<3)) + { + /* [3]:UNSTKERR */ + rt_kprintf("UNSTKERR "); + } + + if(SCB_CFSR_BFSR & (1<<4)) + { + /* [4]:STKERR */ + rt_kprintf("STKERR "); + } + + if(SCB_CFSR_BFSR & (1<<7)) + { + rt_kprintf("SCB->BFAR:%08X\n", SCB_BFAR); + } + else + { + rt_kprintf("\n"); + } +} + +static void mem_manage_fault_track(void) +{ + rt_kprintf("mem manage fault:\n"); + rt_kprintf("SCB_CFSR_MFSR:0x%02X ", SCB_CFSR_MFSR); + + if(SCB_CFSR_MFSR & (1<<0)) + { + /* [0]:IACCVIOL */ + rt_kprintf("IACCVIOL "); + } + + if(SCB_CFSR_MFSR & (1<<1)) + { + /* [1]:DACCVIOL */ + rt_kprintf("DACCVIOL "); + } + + if(SCB_CFSR_MFSR & (1<<3)) + { + /* [3]:MUNSTKERR */ + rt_kprintf("MUNSTKERR "); + } + + if(SCB_CFSR_MFSR & (1<<4)) + { + /* [4]:MSTKERR */ + rt_kprintf("MSTKERR "); + } + + if(SCB_CFSR_MFSR & (1<<7)) + { + /* [7]:MMARVALID */ + rt_kprintf("SCB->MMAR:%08X\n", SCB_MMAR); + } + else + { + rt_kprintf("\n"); + } +} + +static void hard_fault_track(void) +{ + if(SCB_HFSR & (1UL<<1)) + { + /* [1]:VECTBL, Indicates hard fault is caused by failed vector fetch. */ + rt_kprintf("failed vector fetch\n"); + } + + if(SCB_HFSR & (1UL<<30)) + { + /* [30]:FORCED, Indicates hard fault is taken because of bus fault, + memory management fault, or usage fault. */ + if(SCB_CFSR_BFSR) + { + bus_fault_track(); + } + + if(SCB_CFSR_MFSR) + { + mem_manage_fault_track(); + } + + if(SCB_CFSR_UFSR) + { + usage_fault_track(); + } + } + + if(SCB_HFSR & (1UL<<31)) + { + /* [31]:DEBUGEVT, Indicates hard fault is triggered by debug event. */ + rt_kprintf("debug event\n"); + } +} +#endif /* RT_USING_FINSH */ + +struct exception_info +{ + rt_uint32_t exc_return; + struct stack_frame stack_frame; +}; + +void rt_hw_hard_fault_exception(struct exception_info *exception_info) +{ + extern long list_thread(void); + struct exception_stack_frame *exception_stack = &exception_info->stack_frame.exception_stack_frame; + struct stack_frame *context = &exception_info->stack_frame; + + if (rt_exception_hook != RT_NULL) + { + rt_err_t result; + + result = rt_exception_hook(exception_stack); + if (result == RT_EOK) return; + } + + rt_kprintf("psr: 0x%08x\n", context->exception_stack_frame.psr); + + rt_kprintf("r00: 0x%08x\n", context->exception_stack_frame.r0); + rt_kprintf("r01: 0x%08x\n", context->exception_stack_frame.r1); + rt_kprintf("r02: 0x%08x\n", context->exception_stack_frame.r2); + rt_kprintf("r03: 0x%08x\n", context->exception_stack_frame.r3); + rt_kprintf("r04: 0x%08x\n", context->r4); + rt_kprintf("r05: 0x%08x\n", context->r5); + rt_kprintf("r06: 0x%08x\n", context->r6); + rt_kprintf("r07: 0x%08x\n", context->r7); + rt_kprintf("r08: 0x%08x\n", context->r8); + rt_kprintf("r09: 0x%08x\n", context->r9); + rt_kprintf("r10: 0x%08x\n", context->r10); + rt_kprintf("r11: 0x%08x\n", context->r11); + rt_kprintf("r12: 0x%08x\n", context->exception_stack_frame.r12); + rt_kprintf(" lr: 0x%08x\n", context->exception_stack_frame.lr); + rt_kprintf(" pc: 0x%08x\n", context->exception_stack_frame.pc); + + if (exception_info->exc_return & (1 << 2)) + { + rt_kprintf("hard fault on thread: %s\r\n\r\n", rt_thread_self()->name); + +#ifdef RT_USING_FINSH + list_thread(); +#endif + } + else + { + rt_kprintf("hard fault on handler\r\n\r\n"); + } + + if ( (exception_info->exc_return & 0x10) == 0) + { + rt_kprintf("FPU active!\r\n"); + } + +#ifdef RT_USING_FINSH + hard_fault_track(); +#endif /* RT_USING_FINSH */ + + while (1); +} + +/** + * shutdown CPU + */ +void rt_hw_cpu_shutdown(void) +{ + rt_kprintf("shutdown...\n"); + + RT_ASSERT(0); +} + +/** + * reset CPU + */ +RT_WEAK void rt_hw_cpu_reset(void) +{ + SCB_AIRCR = SCB_RESET_VALUE; +} + +#ifdef RT_USING_CPU_FFS +/** + * This function finds the first bit set (beginning with the least significant bit) + * in value and return the index of that bit. + * + * Bits are numbered starting at 1 (the least significant bit). A return value of + * zero from any of these functions means that the argument was zero. + * + * @return return the index of the first bit set. If value is 0, then this function + * shall return 0. + */ +#if defined(__CC_ARM) +__asm int __rt_ffs(int value) +{ + CMP r0, #0x00 + BEQ exit + + RBIT r0, r0 + CLZ r0, r0 + ADDS r0, r0, #0x01 + +exit + BX lr +} +#elif defined(__CLANG_ARM) +int __rt_ffs(int value) +{ + __asm volatile( + "CMP r0, #0x00 \n" + "BEQ 1f \n" + + "RBIT r0, r0 \n" + "CLZ r0, r0 \n" + "ADDS r0, r0, #0x01 \n" + + "1: \n" + "BX lr \n" + + : "=r"(value) + : "r"(value) + ); + return value; +} +#elif defined(__IAR_SYSTEMS_ICC__) +int __rt_ffs(int value) +{ + if (value == 0) return value; + + asm("RBIT %0, %1" : "=r"(value) : "r"(value)); + asm("CLZ %0, %1" : "=r"(value) : "r"(value)); + asm("ADDS %0, %1, #0x01" : "=r"(value) : "r"(value)); + + return value; +} +#elif defined(__GNUC__) +int __rt_ffs(int value) +{ + return __builtin_ffs(value); +} +#endif + +#endif diff --git a/libcpu/arm/cortex-m33/syscall_gcc.S b/libcpu/arm/cortex-m33/syscall_gcc.S new file mode 100644 index 0000000000..d7d16fb8a0 --- /dev/null +++ b/libcpu/arm/cortex-m33/syscall_gcc.S @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-25 tyx first version + */ + +.cpu cortex-m4 +.syntax unified +.thumb +.text + +/* + * int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2); + */ +.global tzcall +.type tzcall, %function +tzcall: + SVC 1 /* call SVC 1 */ + BX LR + +tzcall_entry: + PUSH {R1, R4, LR} + MOV R4, R1 /* copy thread SP to R4 */ + LDMFD R4!, {r0 - r3} /* pop user stack, get input arg0, arg1, arg2 */ + STMFD R4!, {r0 - r3} /* push stack, user stack recovery */ + BL rt_secure_svc_handle /* call fun */ + POP {R1, R4, LR} + STR R0, [R1] /* update return value */ + BX LR /* return to thread */ + +syscall_entry: + BX LR /* return to user app */ + +.global SVC_Handler +.type SVC_Handler, %function +SVC_Handler: + + /* get SP, save to R1 */ + MRS R1, MSP /* get fault context from handler. */ + TST LR, #0x04 /* if(!EXC_RETURN[2]) */ + BEQ get_sp_done + MRS R1, PSP /* get fault context from thread. */ +get_sp_done: + + /* get svc index */ + LDR R0, [R1, #24] + LDRB R0, [R0, #-2] + + /* if svc == 0, do system call */ + CMP R0, #0x0 + BEQ syscall_entry + + /* if svc == 1, do TrustZone call */ + CMP R0, #0x1 + BEQ tzcall_entry diff --git a/libcpu/arm/cortex-m33/syscall_iar.S b/libcpu/arm/cortex-m33/syscall_iar.S new file mode 100644 index 0000000000..aa30ead9e3 --- /dev/null +++ b/libcpu/arm/cortex-m33/syscall_iar.S @@ -0,0 +1,63 @@ +;/* +; * Copyright (c) 2006-2018, RT-Thread Development Team +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Change Logs: +; * Date Author Notes +; * 2019-10-25 tyx first version +; */ + +;/* +; * @addtogroup cortex-m33 +; */ + + SECTION .text:CODE(2) + THUMB + REQUIRE8 + PRESERVE8 + +;/* +; * int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2); +; */ +.global tzcall +.type tzcall, %function +tzcall: + SVC 1 ;/* call SVC 1 */ + BX LR + +tzcall_entry: + PUSH {R1, R4, LR} + MOV R4, R1 ;/* copy thread SP to R4 */ + LDMFD R4!, {r0 - r3} ;/* pop user stack, get input arg0, arg1, arg2 */ + STMFD R4!, {r0 - r3} ;/* push stack, user stack recovery */ + BL rt_secure_svc_handle ;/* call fun */ + POP {R1, R4, LR} + STR R0, [R1] ;/* update return value */ + BX LR ;/* return to thread */ + +syscall_entry: + BX LR ;/* return to user app */ + +.global SVC_Handler +.type SVC_Handler, %function +SVC_Handler: + + ;/* get SP, save to R1 */ + MRS R1, MSP ;/* get fault context from handler. */ + TST LR, #0x04 ;/* if(!EXC_RETURN[2]) */ + BEQ get_sp_done + MRS R1, PSP ;/* get fault context from thread. */ +get_sp_done: + + ;/* get svc index */ + LDR R0, [R1, #24] + LDRB R0, [R0, #-2] + + ;/* if svc == 0, do system call */ + CMP R0, #0x0 + BEQ syscall_entry + + ;/* if svc == 1, do TrustZone call */ + CMP R0, #0x1 + BEQ tzcall_entry diff --git a/libcpu/arm/cortex-m33/syscall_rvds.S b/libcpu/arm/cortex-m33/syscall_rvds.S new file mode 100644 index 0000000000..95ee247ee5 --- /dev/null +++ b/libcpu/arm/cortex-m33/syscall_rvds.S @@ -0,0 +1,74 @@ +;/* +; * Copyright (c) 2006-2018, RT-Thread Development Team +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Change Logs: +; * Date Author Notes +; * 2019-10-25 tyx first version +; */ + + AREA |.text|, CODE, READONLY, ALIGN=2 + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_secure_svc_handle + +;/* +; * int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2); +; */ +tzcall PROC + EXPORT tzcall + SVC 1 ;call SVC 1 + BX LR + + ENDP + +tzcall_entry PROC + PUSH {R1, R4, LR} + MOV R4, R1 ; copy thread SP to R4 + LDMFD R4!, {r0 - r3} ; pop user stack, get input arg0, arg1, arg2 + STMFD R4!, {r0 - r3} ; push stack, user stack recovery + BL rt_secure_svc_handle ; call fun + POP {R1, R4, LR} + STR R0, [R1] ; update return value + BX LR ; return to thread + + ENDP + +syscall_entry PROC + BX LR ; return to user app + + ENDP + +;/* +; * void SVC_Handler(void); +; */ +SVC_Handler PROC + EXPORT SVC_Handler + + ; get SP, save to R1 + MRS R1, MSP ;get fault context from handler + TST LR, #0x04 ;if(!EXC_RETURN[2]) + BEQ get_sp_done + MRS R1, PSP ;get fault context from thread +get_sp_done + + ; get svc index + LDR R0, [R1, #24] + LDRB R0, [R0, #-2] + + ;if svc == 0, do system call + CMP R0, #0x0 + BEQ syscall_entry + + ;if svc == 1, do TrustZone call + CMP R0, #0x1 + BEQ tzcall_entry + + ENDP + + ALIGN + + END
\ No newline at end of file diff --git a/libcpu/arm/cortex-m33/trustzone.c b/libcpu/arm/cortex-m33/trustzone.c new file mode 100644 index 0000000000..86654a7199 --- /dev/null +++ b/libcpu/arm/cortex-m33/trustzone.c @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-28 tyx the first version. + */ + +#include <rtthread.h> + +extern void TZ_InitContextSystem_S(void); +extern rt_uint32_t TZ_AllocModuleContext_S (rt_uint32_t module); +extern rt_uint32_t TZ_FreeModuleContext_S(rt_uint32_t id); +extern rt_uint32_t TZ_LoadContext_S(rt_uint32_t id); +extern rt_uint32_t TZ_StoreContext_S(rt_uint32_t id); +extern int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2); + +#define TZ_INIT_CONTEXT_ID (0x1001) +#define TZ_ALLOC_CONTEXT_ID (0x1002) +#define TZ_FREE_CONTEXT_ID (0x1003) + +rt_ubase_t rt_trustzone_current_context; + +#if defined(__CC_ARM) +static __inline rt_uint32_t __get_IPSR(void) +{ + register rt_uint32_t result __asm("ipsr"); + return(result); +} +#elif defined(__CLANG_ARM) +__attribute__((always_inline)) static __inline rt_uint32_t __get_IPSR(void) +{ + rt_uint32_t result; + + __asm volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} +#elif defined(__IAR_SYSTEMS_ICC__) +_Pragma("inline=forced") static inline int __get_IPSR(int value) +{ + rt_uint32_t result; + + asm("MRS %0, ipsr" : "=r"(result)); + return result; +} +#elif defined(__GNUC__) +__attribute__((always_inline)) static inline rt_uint32_t __get_IPSR(void) +{ + rt_uint32_t result; + + __asm volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} +#endif + +void rt_trustzone_init(void) +{ + static rt_uint8_t _init; + + if (_init) + return; + tzcall(TZ_INIT_CONTEXT_ID, 0, 0, 0); + _init = 1; +} + +rt_err_t rt_trustzone_enter(rt_ubase_t module) +{ + rt_trustzone_init(); + if (tzcall(TZ_ALLOC_CONTEXT_ID, module, 0, 0)) + { + return RT_EOK; + } + return -RT_ERROR; +} + +rt_err_t rt_trustzone_exit(void) +{ + tzcall(TZ_FREE_CONTEXT_ID, 0, 0, 0); + return RT_EOK; +} + +void rt_trustzone_context_store(rt_ubase_t context) +{ + TZ_StoreContext_S(context); +} + +void rt_trustzone_context_load(rt_ubase_t context) +{ + TZ_LoadContext_S(context); +} + +int rt_secure_svc_handle(int svc_id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2) +{ + rt_ubase_t tmp; + int res = 0; + + switch (svc_id) + { + case TZ_INIT_CONTEXT_ID: + TZ_InitContextSystem_S(); + break; + case TZ_ALLOC_CONTEXT_ID: + res = TZ_AllocModuleContext_S(arg0); + if (res <= 0) + { + rt_kprintf("Alloc Context Failed\n"); + } + else + { + rt_trustzone_current_context = res; + TZ_LoadContext_S(res); + } + break; + case TZ_FREE_CONTEXT_ID: + TZ_FreeModuleContext_S(rt_trustzone_current_context); + rt_trustzone_current_context = 0; + break; + } + return res; +} + diff --git a/libcpu/arm/cortex-m4/SConscript b/libcpu/arm/cortex-m4/SConscript new file mode 100644 index 0000000000..9ff30a796b --- /dev/null +++ b/libcpu/arm/cortex-m4/SConscript @@ -0,0 +1,23 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arm/cortex-m4/context_gcc.S b/libcpu/arm/cortex-m4/context_gcc.S index 420f4f8ae3..f569a35863 100644 --- a/libcpu/arm/cortex-m4/context_gcc.S +++ b/libcpu/arm/cortex-m4/context_gcc.S @@ -25,7 +25,7 @@ .equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ .equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ .equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */ -.equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */ +.equ NVIC_PENDSV_PRI, 0xFFFF0000 /* PendSV and SysTick priority value (lowest) */ .equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */ /* @@ -182,7 +182,7 @@ rt_hw_context_switch_to: MOV r0, #1 STR r0, [r1] - /* set the PendSV exception priority */ + /* set the PendSV and SysTick exception priority */ LDR r0, =NVIC_SYSPRI2 LDR r1, =NVIC_PENDSV_PRI LDR.W r2, [r0,#0x00] /* read */ diff --git a/libcpu/arm/cortex-m4/context_iar.S b/libcpu/arm/cortex-m4/context_iar.S index bf707d0d53..18d6a3f784 100644 --- a/libcpu/arm/cortex-m4/context_iar.S +++ b/libcpu/arm/cortex-m4/context_iar.S @@ -1,11 +1,7 @@ ;/* -; * File : context_iar.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team +; * Copyright (c) 2006-2018, RT-Thread Development Team ; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes @@ -25,7 +21,7 @@ SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception SECTION .text:CODE(2) @@ -190,7 +186,7 @@ rt_hw_context_switch_to: MOV r0, #1 STR r0, [r1] - ; set the PendSV exception priority + ; set the PendSV and SysTick exception priority LDR r0, =NVIC_SYSPRI2 LDR r1, =NVIC_PENDSV_PRI LDR.W r2, [r0,#0x00] ; read diff --git a/libcpu/arm/cortex-m4/context_rvds.S b/libcpu/arm/cortex-m4/context_rvds.S index f6d2447c5e..3f948bc349 100644 --- a/libcpu/arm/cortex-m4/context_rvds.S +++ b/libcpu/arm/cortex-m4/context_rvds.S @@ -20,7 +20,7 @@ SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception AREA |.text|, CODE, READONLY, ALIGN=2 @@ -186,7 +186,7 @@ rt_hw_context_switch_to PROC MOV r0, #1 STR r0, [r1] - ; set the PendSV exception priority + ; set the PendSV and SysTick exception priority LDR r0, =NVIC_SYSPRI2 LDR r1, =NVIC_PENDSV_PRI LDR.W r2, [r0,#0x00] ; read diff --git a/libcpu/arm/cortex-m4/cpuport.c b/libcpu/arm/cortex-m4/cpuport.c index 18f027895b..dc8a9aab59 100644 --- a/libcpu/arm/cortex-m4/cpuport.c +++ b/libcpu/arm/cortex-m4/cpuport.c @@ -14,6 +14,7 @@ * 2012-12-29 Bernard Add exception hook. * 2013-06-23 aozima support lazy stack optimized. * 2018-07-24 aozima enhancement hard fault exception handler. + * 2019-07-03 yangjie add __rt_ffs() for armclang. */ #include <rtthread.h> @@ -453,7 +454,7 @@ RT_WEAK void rt_hw_cpu_reset(void) * @return return the index of the first bit set. If value is 0, then this function * shall return 0. */ -#if defined(__CC_ARM) || defined(__CLANG_ARM) +#if defined(__CC_ARM) __asm int __rt_ffs(int value) { CMP r0, #0x00 @@ -466,6 +467,24 @@ __asm int __rt_ffs(int value) exit BX lr } +#elif defined(__CLANG_ARM) +int __rt_ffs(int value) +{ + __asm volatile( + "CMP r0, #0x00 \n" + "BEQ 1f \n" + + "RBIT r0, r0 \n" + "CLZ r0, r0 \n" + "ADDS r0, r0, #0x01 \n" + + "1: \n" + + : "=r"(value) + : "r"(value) + ); + return value; +} #elif defined(__IAR_SYSTEMS_ICC__) int __rt_ffs(int value) { diff --git a/libcpu/arm/cortex-m7/SConscript b/libcpu/arm/cortex-m7/SConscript new file mode 100644 index 0000000000..9ff30a796b --- /dev/null +++ b/libcpu/arm/cortex-m7/SConscript @@ -0,0 +1,23 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arm/cortex-m7/context_gcc.S b/libcpu/arm/cortex-m7/context_gcc.S index 420f4f8ae3..f569a35863 100644 --- a/libcpu/arm/cortex-m7/context_gcc.S +++ b/libcpu/arm/cortex-m7/context_gcc.S @@ -25,7 +25,7 @@ .equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ .equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ .equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */ -.equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */ +.equ NVIC_PENDSV_PRI, 0xFFFF0000 /* PendSV and SysTick priority value (lowest) */ .equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */ /* @@ -182,7 +182,7 @@ rt_hw_context_switch_to: MOV r0, #1 STR r0, [r1] - /* set the PendSV exception priority */ + /* set the PendSV and SysTick exception priority */ LDR r0, =NVIC_SYSPRI2 LDR r1, =NVIC_PENDSV_PRI LDR.W r2, [r0,#0x00] /* read */ diff --git a/libcpu/arm/cortex-m7/context_iar.S b/libcpu/arm/cortex-m7/context_iar.S index bf707d0d53..18d6a3f784 100644 --- a/libcpu/arm/cortex-m7/context_iar.S +++ b/libcpu/arm/cortex-m7/context_iar.S @@ -1,11 +1,7 @@ ;/* -; * File : context_iar.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team +; * Copyright (c) 2006-2018, RT-Thread Development Team ; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes @@ -25,7 +21,7 @@ SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception SECTION .text:CODE(2) @@ -190,7 +186,7 @@ rt_hw_context_switch_to: MOV r0, #1 STR r0, [r1] - ; set the PendSV exception priority + ; set the PendSV and SysTick exception priority LDR r0, =NVIC_SYSPRI2 LDR r1, =NVIC_PENDSV_PRI LDR.W r2, [r0,#0x00] ; read diff --git a/libcpu/arm/cortex-m7/context_rvds.S b/libcpu/arm/cortex-m7/context_rvds.S index 1abe477eab..d051f819c1 100644 --- a/libcpu/arm/cortex-m7/context_rvds.S +++ b/libcpu/arm/cortex-m7/context_rvds.S @@ -1,11 +1,7 @@ ;/* -; * File : context_rvds.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team +; * Copyright (c) 2006-2018, RT-Thread Development Team ; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes @@ -24,7 +20,7 @@ SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception AREA |.text|, CODE, READONLY, ALIGN=2 @@ -190,7 +186,7 @@ rt_hw_context_switch_to PROC MOV r0, #1 STR r0, [r1] - ; set the PendSV exception priority + ; set the PendSV and SysTick exception priority LDR r0, =NVIC_SYSPRI2 LDR r1, =NVIC_PENDSV_PRI LDR.W r2, [r0,#0x00] ; read diff --git a/libcpu/arm/cortex-m7/cpu_cache.c b/libcpu/arm/cortex-m7/cpu_cache.c new file mode 100644 index 0000000000..350b819c00 --- /dev/null +++ b/libcpu/arm/cortex-m7/cpu_cache.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-04-02 tanek first implementation + * 2019-04-27 misonyo update to cortex-m7 series + */ + +#include <rthw.h> +#include <rtdef.h> +#include <board.h> + +/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */ +#define L1CACHE_LINESIZE_BYTE (32) + +void rt_hw_cpu_icache_enable(void) +{ + SCB_EnableICache(); +} + +void rt_hw_cpu_icache_disable(void) +{ + SCB_DisableICache(); +} + +rt_base_t rt_hw_cpu_icache_status(void) +{ + return 0; +} + +void rt_hw_cpu_icache_ops(int ops, void* addr, int size) +{ + rt_uint32_t address = (rt_uint32_t)addr & (rt_uint32_t) ~(L1CACHE_LINESIZE_BYTE - 1); + rt_int32_t size_byte = size + address - (rt_uint32_t)addr; + rt_uint32_t linesize = 32U; + if (ops & RT_HW_CACHE_INVALIDATE) + { + __DSB(); + while (size_byte > 0) + { + SCB->ICIMVAU = address; + address += linesize; + size_byte -= linesize; + } + __DSB(); + __ISB(); + } +} + +void rt_hw_cpu_dcache_enable(void) +{ + SCB_EnableDCache(); +} + +void rt_hw_cpu_dcache_disable(void) +{ + SCB_DisableDCache(); +} + +rt_base_t rt_hw_cpu_dcache_status(void) +{ + return 0; +} + +void rt_hw_cpu_dcache_ops(int ops, void* addr, int size) +{ + rt_uint32_t startAddr = (rt_uint32_t)addr & (rt_uint32_t)~(L1CACHE_LINESIZE_BYTE - 1); + rt_uint32_t size_byte = size + (rt_uint32_t)addr - startAddr; + + if (ops & (RT_HW_CACHE_FLUSH | RT_HW_CACHE_INVALIDATE)) + { + SCB_CleanInvalidateDCache_by_Addr((uint32_t *)startAddr, size_byte); + } + else if (ops & RT_HW_CACHE_FLUSH) + { + SCB_CleanDCache_by_Addr((uint32_t *)startAddr, size_byte); + } + else if (ops & RT_HW_CACHE_INVALIDATE) + { + SCB_InvalidateDCache_by_Addr((uint32_t *)startAddr, size_byte); + } + else + { + RT_ASSERT(0); + } +} diff --git a/libcpu/arm/cortex-m7/cpuport.c b/libcpu/arm/cortex-m7/cpuport.c index 18f027895b..e701a52307 100644 --- a/libcpu/arm/cortex-m7/cpuport.c +++ b/libcpu/arm/cortex-m7/cpuport.c @@ -14,6 +14,7 @@ * 2012-12-29 Bernard Add exception hook. * 2013-06-23 aozima support lazy stack optimized. * 2018-07-24 aozima enhancement hard fault exception handler. + * 2019-07-03 yangjie add __rt_ffs() for armclang. */ #include <rtthread.h> @@ -453,7 +454,7 @@ RT_WEAK void rt_hw_cpu_reset(void) * @return return the index of the first bit set. If value is 0, then this function * shall return 0. */ -#if defined(__CC_ARM) || defined(__CLANG_ARM) +#if defined(__CC_ARM) __asm int __rt_ffs(int value) { CMP r0, #0x00 @@ -466,6 +467,24 @@ __asm int __rt_ffs(int value) exit BX lr } +#elif defined(__CLANG_ARM) +int __rt_ffs(int value) +{ + __asm volatile( + "CMP r0, #0x00 \n" + "BEQ 1f \n" + + "RBIT r0, r0 \n" + "CLZ r0, r0 \n" + "ADDS r0, r0, #0x01 \n" + + "1: \n" + + : "=r"(value) + : "r"(value) + ); + return value; +} #elif defined(__IAR_SYSTEMS_ICC__) int __rt_ffs(int value) { diff --git a/libcpu/arm/cortex-r4/SConscript b/libcpu/arm/cortex-r4/SConscript new file mode 100644 index 0000000000..9ff30a796b --- /dev/null +++ b/libcpu/arm/cortex-r4/SConscript @@ -0,0 +1,23 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arm/cortex-r4/context_ccs.asm b/libcpu/arm/cortex-r4/context_ccs.asm index 2b459f8238..9463556743 100644 --- a/libcpu/arm/cortex-r4/context_ccs.asm +++ b/libcpu/arm/cortex-r4/context_ccs.asm @@ -1,14 +1,10 @@ ;/* -; * File : context_ccs.asm -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006, RT-Thread Development Team +; * Copyright (c) 2006-2018, RT-Thread Development Team ; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: -; * Date Author Notes +; * Date Author Notes ; * 2009-01-20 Bernard first version ; * 2011-07-22 Bernard added thumb mode porting ; * 2013-05-24 Grissiom port to CCS diff --git a/libcpu/arm/cortex-r4/start_gcc.S b/libcpu/arm/cortex-r4/start_gcc.S index ab77b98781..a347503ec0 100644 --- a/libcpu/arm/cortex-r4/start_gcc.S +++ b/libcpu/arm/cortex-r4/start_gcc.S @@ -36,6 +36,7 @@ .globl stack_start .globl stack_top +.align 3 stack_start: .rept (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size) .byte 0 diff --git a/libcpu/arm/dm36x/SConscript b/libcpu/arm/dm36x/SConscript new file mode 100644 index 0000000000..9ff30a796b --- /dev/null +++ b/libcpu/arm/dm36x/SConscript @@ -0,0 +1,23 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arm/dm36x/context_rvds.S b/libcpu/arm/dm36x/context_rvds.S index 631da83372..8e0fc4465b 100644 --- a/libcpu/arm/dm36x/context_rvds.S +++ b/libcpu/arm/dm36x/context_rvds.S @@ -1,21 +1,7 @@ ;/* -; * File : context_rvds.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006, RT-Thread Development Team +; * Copyright (c) 2006-2018, RT-Thread Development Team ; * -; * This program is free software; you can redistribute it and/or modify -; * it under the terms of the GNU General Public License as published by -; * the Free Software Foundation; either version 2 of the License, or -; * (at your option) any later version. -; * -; * This program is distributed in the hope that it will be useful, -; * but WITHOUT ANY WARRANTY; without even the implied warranty of -; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; * GNU General Public License for more details. -; * -; * You should have received a copy of the GNU General Public License along -; * with this program; if not, write to the Free Software Foundation, Inc., -; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes diff --git a/libcpu/arm/lpc214x/SConscript b/libcpu/arm/lpc214x/SConscript new file mode 100644 index 0000000000..9ff30a796b --- /dev/null +++ b/libcpu/arm/lpc214x/SConscript @@ -0,0 +1,23 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arm/lpc214x/context_rvds.S b/libcpu/arm/lpc214x/context_rvds.S index 762b67d42e..47ca31cd1f 100644 --- a/libcpu/arm/lpc214x/context_rvds.S +++ b/libcpu/arm/lpc214x/context_rvds.S @@ -1,11 +1,7 @@ ;/* -; * File : context_rvds.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006, RT-Thread Development Team +; * Copyright (c) 2006-2018, RT-Thread Development Team ; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes diff --git a/libcpu/arm/lpc24xx/SConscript b/libcpu/arm/lpc24xx/SConscript new file mode 100644 index 0000000000..9ff30a796b --- /dev/null +++ b/libcpu/arm/lpc24xx/SConscript @@ -0,0 +1,23 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arm/lpc24xx/context_rvds.S b/libcpu/arm/lpc24xx/context_rvds.S index ecd20e4bbe..0d9915f4f1 100644 --- a/libcpu/arm/lpc24xx/context_rvds.S +++ b/libcpu/arm/lpc24xx/context_rvds.S @@ -1,11 +1,7 @@ ;/* -; * File : context_rvds.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006, RT-Thread Development Team +; * Copyright (c) 2006-2018, RT-Thread Development Team ; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes diff --git a/libcpu/arm/realview-a8-vmm/SConscript b/libcpu/arm/realview-a8-vmm/SConscript index 61057c04cc..9ff30a796b 100644 --- a/libcpu/arm/realview-a8-vmm/SConscript +++ b/libcpu/arm/realview-a8-vmm/SConscript @@ -1,17 +1,23 @@ -Import('rtconfig') +# RT-Thread building script for component + from building import * +Import('rtconfig') + cwd = GetCurrentDir() -src = Glob('*.c') +src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + if rtconfig.PLATFORM == 'iar': - src += Glob('*_iar.S') -elif rtconfig.PLATFORM == 'gcc': - src += Glob('*_gcc.S') -elif rtconfig.PLATFORM == 'armcc': - src += Glob('*_rvds.S') + src += Glob('*_iar.S') -group = DefineGroup('AM335x', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/realview-a8-vmm/start_gcc.S b/libcpu/arm/realview-a8-vmm/start_gcc.S index 2ec7fe6c86..879cf992a8 100644 --- a/libcpu/arm/realview-a8-vmm/start_gcc.S +++ b/libcpu/arm/realview-a8-vmm/start_gcc.S @@ -47,6 +47,7 @@ .globl stack_start .globl stack_top +.align 3 stack_start: .rept ISR_Stack_Size .byte 0 diff --git a/libcpu/arm/s3c24x0/SConscript b/libcpu/arm/s3c24x0/SConscript new file mode 100644 index 0000000000..9ff30a796b --- /dev/null +++ b/libcpu/arm/s3c24x0/SConscript @@ -0,0 +1,23 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arm/s3c24x0/context_rvds.S b/libcpu/arm/s3c24x0/context_rvds.S index 54d655afe1..9078f6173a 100644 --- a/libcpu/arm/s3c24x0/context_rvds.S +++ b/libcpu/arm/s3c24x0/context_rvds.S @@ -1,11 +1,7 @@ ;/* -; * File : context_rvds.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006, RT-Thread Development Team +; * Copyright (c) 2006-2018, RT-Thread Development Team ; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes diff --git a/libcpu/arm/s3c24x0/serial.c b/libcpu/arm/s3c24x0/serial.c deleted file mode 100644 index 1eca1b1110..0000000000 --- a/libcpu/arm/s3c24x0/serial.c +++ /dev/null @@ -1,291 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard first version - * 2009-04-20 yi.qiu modified according bernard's stm32 version - */ - -#include <rtthread.h> - -#include "serial.h" - -/** - * @addtogroup S3C24X0 - */ -/*@{*/ - -/* RT-Thread Device Interface */ -/** - * This function initializes serial - */ -static rt_err_t rt_serial_init(rt_device_t dev) -{ - struct serial_device* uart = (struct serial_device*) dev->user_data; - - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_memset(uart->int_rx->rx_buffer, 0, - sizeof(uart->int_rx->rx_buffer)); - uart->int_rx->read_index = uart->int_rx->save_index = 0; - } - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - rt_memset(uart->int_tx->tx_buffer, 0, - sizeof(uart->int_tx->tx_buffer)); - uart->int_tx->write_index = uart->int_tx->save_index = 0; - } - - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } - - return RT_EOK; -} - -/* save a char to serial buffer */ -static void rt_serial_savechar(struct serial_device* uart, char ch) -{ - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; - uart->int_rx->save_index ++; - if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (uart->int_rx->save_index == uart->int_rx->read_index) - { - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); -} - -static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) -{ - RT_ASSERT(dev != RT_NULL); - - return RT_EOK; -} - -static rt_err_t rt_serial_close(rt_device_t dev) -{ - RT_ASSERT(dev != RT_NULL); - - return RT_EOK; -} - -static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) -{ - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - ptr = buffer; - err_code = RT_EOK; - uart = (struct serial_device*)dev->user_data; - - if (ptr == RT_NULL) - { - err_code = -RT_ENOMEM; - rt_set_errno(err_code); - return -RT_ENOMEM; - } - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_base_t level; - - /* interrupt mode Rx */ - while (size) - { - if (uart->int_rx->read_index != uart->int_rx->save_index) - { - *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; - size --; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; - break; - } - } - } - else - { - /* polling mode */ - while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) - { - while (uart->uart_device->ustat & USTAT_RCV_READY) - { - *ptr = uart->uart_device->urxh & 0xff; - ptr ++; - } - } - } - - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; -} - -static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) -{ - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - err_code = RT_EOK; - ptr = (rt_uint8_t*)buffer; - uart = (struct serial_device*)dev->user_data; - - if (ptr == RT_NULL) - { - err_code = -RT_ENOMEM; - rt_set_errno(err_code); - return -RT_ENOMEM; - } - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* interrupt mode Tx */ - while (uart->int_tx->save_index != uart->int_tx->write_index) - { - /* save on tx buffer */ - uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; - - -- size; - - /* move to next position */ - uart->int_tx->save_index ++; - - /* wrap save index */ - if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) - uart->int_tx->save_index = 0; - } - - /* set error code */ - if (size > 0) - err_code = -RT_EFULL; - } - else - { - /* polling mode */ - while (size) - { - /* - * to be polite with serial console add a line feed - * to the carriage return character - */ - if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) - { - while (!(uart->uart_device->ustat & USTAT_TXB_EMPTY)); - uart->uart_device->utxh = '\r'; - } - - while (!(uart->uart_device->ustat & USTAT_TXB_EMPTY)); - uart->uart_device->utxh = (*ptr & 0xFF); - - ++ptr; - --size; - } - } - - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; -} - -static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args) -{ - RT_ASSERT(dev != RT_NULL); - - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - break; - - case RT_DEVICE_CTRL_RESUME: - /* resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - break; - } - - return RT_EOK; -} - -/* - * serial register - */ -rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial) -{ - RT_ASSERT(device != RT_NULL); - - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; - - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); -} - -/* ISR for serial interrupt */ -void rt_hw_serial_isr(rt_device_t device) -{ - struct serial_device* uart = (struct serial_device*) device->user_data; - - /* interrupt mode receive */ - RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); - - /* save on rx buffer */ - while (uart->uart_device->ustat & USTAT_RCV_READY) - { - rt_serial_savechar(uart, uart->uart_device->urxh & 0xff); - } - - /* invoke callback */ - if (device->rx_indicate != RT_NULL) - { - rt_size_t rx_length; - - /* get rx length */ - rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? - UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : - uart->int_rx->save_index - uart->int_rx->read_index; - - device->rx_indicate(device, rx_length); - } -} - -/*@}*/ diff --git a/libcpu/arm/s3c24x0/serial.h b/libcpu/arm/s3c24x0/serial.h deleted file mode 100644 index 8a647ef35f..0000000000 --- a/libcpu/arm/s3c24x0/serial.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ -#ifndef __RT_HW_SERIAL_H__ -#define __RT_HW_SERIAL_H__ - -#include <rthw.h> -#include <rtthread.h> - -#include "s3c24x0.h" - -#define USTAT_RCV_READY 0x01 /* receive data ready */ -#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ -#define BPS 115200 /* serial baudrate */ - -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_BUFFER_SIZE 64 - -struct serial_int_rx -{ - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; -}; - -struct serial_int_tx -{ - rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; - rt_uint32_t write_index, save_index; -}; - -typedef struct uartport -{ - volatile rt_uint32_t ulcon; - volatile rt_uint32_t ucon; - volatile rt_uint32_t ufcon; - volatile rt_uint32_t umcon; - volatile rt_uint32_t ustat; - volatile rt_uint32_t urxb; - volatile rt_uint32_t ufstat; - volatile rt_uint32_t umstat; - volatile rt_uint32_t utxh; - volatile rt_uint32_t urxh; - volatile rt_uint32_t ubrd; -}uartport; - -struct serial_device -{ - uartport* uart_device; - - /* rx structure */ - struct serial_int_rx* int_rx; - - /* tx structure */ - struct serial_int_tx* int_tx; -}; - -rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); - -void rt_hw_serial_isr(rt_device_t device); - -#endif diff --git a/libcpu/arm/s3c24x0/start_gcc.S b/libcpu/arm/s3c24x0/start_gcc.S index 4adc458094..cc2b2f6310 100644 --- a/libcpu/arm/s3c24x0/start_gcc.S +++ b/libcpu/arm/s3c24x0/start_gcc.S @@ -191,7 +191,7 @@ reset: copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ + cmp r0, r2 /* until source end address [r2] */ ble copy_loop /* setup stack */ diff --git a/libcpu/arm/s3c44b0/SConscript b/libcpu/arm/s3c44b0/SConscript new file mode 100644 index 0000000000..9ff30a796b --- /dev/null +++ b/libcpu/arm/s3c44b0/SConscript @@ -0,0 +1,23 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arm/s3c44b0/context_rvds.S b/libcpu/arm/s3c44b0/context_rvds.S index 641ec7a6b1..27ebf8f5e3 100644 --- a/libcpu/arm/s3c44b0/context_rvds.S +++ b/libcpu/arm/s3c44b0/context_rvds.S @@ -1,11 +1,7 @@ ;/* -; * File : context_rvds.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006, RT-Thread Development Team +; * Copyright (c) 2006-2018, RT-Thread Development Team ; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes diff --git a/libcpu/arm/s3c44b0/start_gcc.S b/libcpu/arm/s3c44b0/start_gcc.S index 65b3d422dd..4c448a344f 100644 --- a/libcpu/arm/s3c44b0/start_gcc.S +++ b/libcpu/arm/s3c44b0/start_gcc.S @@ -107,7 +107,7 @@ reset: copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ + cmp r0, r2 /* until source end address [r2] */ ble copy_loop #endif diff --git a/libcpu/arm/sep4020/SConscript b/libcpu/arm/sep4020/SConscript new file mode 100644 index 0000000000..9ff30a796b --- /dev/null +++ b/libcpu/arm/sep4020/SConscript @@ -0,0 +1,23 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +if rtconfig.PLATFORM == 'iar': + src += Glob('*_iar.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/arm/sep4020/context_rvds.S b/libcpu/arm/sep4020/context_rvds.S index 641ec7a6b1..27ebf8f5e3 100644 --- a/libcpu/arm/sep4020/context_rvds.S +++ b/libcpu/arm/sep4020/context_rvds.S @@ -1,11 +1,7 @@ ;/* -; * File : context_rvds.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006, RT-Thread Development Team +; * Copyright (c) 2006-2018, RT-Thread Development Team ; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes diff --git a/libcpu/arm/zynq7000/SConscript b/libcpu/arm/zynq7000/SConscript index 2ad51b573e..9ff30a796b 100644 --- a/libcpu/arm/zynq7000/SConscript +++ b/libcpu/arm/zynq7000/SConscript @@ -1,17 +1,23 @@ -Import('rtconfig') +# RT-Thread building script for component + from building import * +Import('rtconfig') + cwd = GetCurrentDir() -src = Glob('*.c') +src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] +if rtconfig.PLATFORM == 'armcc': + src += Glob('*_rvds.S') + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + if rtconfig.PLATFORM == 'iar': - src += Glob('*_iar.S') -elif rtconfig.PLATFORM == 'gcc': - src += Glob('*_gcc.S') -elif rtconfig.PLATFORM == 'armcc': - src += Glob('*_rvds.S') + src += Glob('*_iar.S') -group = DefineGroup('AM1808', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/arm/zynq7000/context_gcc.S b/libcpu/arm/zynq7000/context_gcc.S index 3dbf3c861d..98f98a0244 100644 --- a/libcpu/arm/zynq7000/context_gcc.S +++ b/libcpu/arm/zynq7000/context_gcc.S @@ -1,21 +1,11 @@ /* - * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd + * Copyright (c) 2006-2018, Shanghai Real-Thread Technology Co., Ltd * - * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * Change Logs: + * Date Author Notes + * 2009-01-20 Bernard first version */ #define NOINT 0xc0 diff --git a/libcpu/arm/zynq7000/cp15.h b/libcpu/arm/zynq7000/cp15.h index bd6a23f1b2..75d81736ab 100644 --- a/libcpu/arm/zynq7000/cp15.h +++ b/libcpu/arm/zynq7000/cp15.h @@ -1,25 +1,16 @@ -#ifndef __CP15_H__ -#define __CP15_H__ /* - * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier: Apache-2.0 * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version */ +#ifndef __CP15_H__ +#define __CP15_H__ + unsigned long rt_cpu_get_smp_id(void); void rt_cpu_mmu_disable(void); diff --git a/libcpu/arm/zynq7000/gic.c b/libcpu/arm/zynq7000/gic.c index 498446db43..76404d4c46 100644 --- a/libcpu/arm/zynq7000/gic.c +++ b/libcpu/arm/zynq7000/gic.c @@ -1,21 +1,11 @@ /* - * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd + * Copyright (c) 2006-2018, RT-Thread Development Team * - * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version */ #include <rtthread.h> @@ -47,7 +37,7 @@ static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; #define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + (n/32) * 4) #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + (n/32) * 4) #define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200) -#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + (n/32) * 4) #define GIC_DIST_ACTIVE_BIT(hw_base) __REG32((hw_base) + 0x300) #define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + (n/4) * 4) #define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + (n/4) * 4) @@ -78,9 +68,8 @@ void arm_gic_ack(rt_uint32_t index, int irq) irq = irq - _gic_table[index].offset; RT_ASSERT(irq >= 0); - GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; } void arm_gic_mask(rt_uint32_t index, int irq) diff --git a/libcpu/arm/zynq7000/gic.h b/libcpu/arm/zynq7000/gic.h index 4b89538948..8fcdf05f6f 100644 --- a/libcpu/arm/zynq7000/gic.h +++ b/libcpu/arm/zynq7000/gic.h @@ -1,21 +1,11 @@ /* - * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd + * Copyright (c) 2006-2018, RT-Thread Development Team * - * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version */ #ifndef __GIC_H__ diff --git a/libcpu/arm/zynq7000/interrupt.h b/libcpu/arm/zynq7000/interrupt.h index 07eafc84e5..da266c42a2 100644 --- a/libcpu/arm/zynq7000/interrupt.h +++ b/libcpu/arm/zynq7000/interrupt.h @@ -1,25 +1,16 @@ -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ /* - * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (c) 2006-2018, RT-Thread Development Team * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier: Apache-2.0 * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version */ +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + void rt_hw_interrupt_clear(int vector); #endif /* end of include guard: __INTERRUPT_H__ */ diff --git a/libcpu/arm/zynq7000/mmu.c b/libcpu/arm/zynq7000/mmu.c index 2a58fabe4f..fbdacca10f 100644 --- a/libcpu/arm/zynq7000/mmu.c +++ b/libcpu/arm/zynq7000/mmu.c @@ -1,21 +1,11 @@ /* - * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd + * Copyright (c) 2006-2018, RT-Thread Development Team * - * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version */ #include <rtthread.h> diff --git a/libcpu/arm/zynq7000/start_gcc.S b/libcpu/arm/zynq7000/start_gcc.S index 6904c45587..18056f0ad9 100644 --- a/libcpu/arm/zynq7000/start_gcc.S +++ b/libcpu/arm/zynq7000/start_gcc.S @@ -33,6 +33,7 @@ .globl stack_start .globl stack_top +.align 3 .bss stack_start: .rept ISR_Stack_Size diff --git a/libcpu/arm/zynq7000/trap.c b/libcpu/arm/zynq7000/trap.c index 9bf58f916c..6243ea82b4 100644 --- a/libcpu/arm/zynq7000/trap.c +++ b/libcpu/arm/zynq7000/trap.c @@ -1,21 +1,11 @@ /* - * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd + * Copyright (c) 2006-2018, RT-Thread Development Team * - * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * Change Logs: + * Date Author Notes + * 2013-07-20 Bernard first version */ #include <rtthread.h> diff --git a/libcpu/avr32/SConscript b/libcpu/avr32/SConscript new file mode 100644 index 0000000000..4f1441895c --- /dev/null +++ b/libcpu/avr32/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +group = [] +list = os.listdir(cwd) + +# cpu porting code files +group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) + +Return('group') diff --git a/libcpu/avr32/uc3/SConscript b/libcpu/avr32/uc3/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/avr32/uc3/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/blackfin/SConscript b/libcpu/blackfin/SConscript new file mode 100644 index 0000000000..4f1441895c --- /dev/null +++ b/libcpu/blackfin/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +group = [] +list = os.listdir(cwd) + +# cpu porting code files +group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) + +Return('group') diff --git a/libcpu/blackfin/bf53x/SConscript b/libcpu/blackfin/bf53x/SConscript new file mode 100644 index 0000000000..af9ba4bc81 --- /dev/null +++ b/libcpu/blackfin/bf53x/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_vdsp.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/c-sky/SConscript b/libcpu/c-sky/SConscript new file mode 100644 index 0000000000..640e46a4fb --- /dev/null +++ b/libcpu/c-sky/SConscript @@ -0,0 +1,18 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +group = [] +list = os.listdir(cwd) + +# add common code files +group = group + SConscript(os.path.join('common', 'SConscript')) + +# cpu porting code files +group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) + +Return('group') diff --git a/libcpu/c-sky/ck802/SConscript b/libcpu/c-sky/ck802/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/c-sky/ck802/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/c-sky/common/SConscript b/libcpu/c-sky/common/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/c-sky/common/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/ia32/SConscript b/libcpu/ia32/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/ia32/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/m16c/SConscript b/libcpu/m16c/SConscript new file mode 100644 index 0000000000..4f1441895c --- /dev/null +++ b/libcpu/m16c/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +group = [] +list = os.listdir(cwd) + +# cpu porting code files +group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) + +Return('group') diff --git a/libcpu/m16c/m16c62p/SConscript b/libcpu/m16c/m16c62p/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/m16c/m16c62p/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/mips/SConscript b/libcpu/mips/SConscript new file mode 100644 index 0000000000..5fca2b473b --- /dev/null +++ b/libcpu/mips/SConscript @@ -0,0 +1,19 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +group = [] +list = os.listdir(cwd) + +# add common code files +group = group + SConscript(os.path.join('common', 'SConscript')) + +# cpu porting code files +if rtconfig.CPU != 'common': + group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) + +Return('group') diff --git a/libcpu/mips/common/Kconfig b/libcpu/mips/common/Kconfig new file mode 100644 index 0000000000..a4dd748214 --- /dev/null +++ b/libcpu/mips/common/Kconfig @@ -0,0 +1,9 @@ +menu "RT-Thread MIPS CPU" + + config RT_USING_FPU + bool "Using Float Point Unit" + default n + help + Using Float Point Unit in code. + +endmenu diff --git a/libcpu/mips/common/SConscript b/libcpu/mips/common/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/mips/common/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/mips/common/asm.h b/libcpu/mips/common/asm.h index 190e8b110e..1b39eea05a 100644 --- a/libcpu/mips/common/asm.h +++ b/libcpu/mips/common/asm.h @@ -1,114 +1,112 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. + * Assembly Macros For MIPS * - * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle - * Copyright (C) 1999 by Silicon Graphics, Inc. - * Copyright (C) 2001 MIPS Technologies, Inc. - * Copyright (C) 2002 Maciej W. Rozycki + * Copyright (c) 2006-2019, RT-Thread Development Team * - * Some useful macros for MIPS assembler code + * SPDX-License-Identifier: Apache-2.0 * - * Some of the routines below contain useless nops that will be optimized - * away by gas in -O mode. These nops are however required to fill delay - * slots in noreorder mode. + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version */ + + #ifndef __ASM_H__ #define __ASM_H__ +#include <rtconfig.h> /* * LEAF - declare leaf routine */ #define LEAF(symbol) \ - .globl symbol; \ - .align 2; \ - .type symbol,@function; \ - .ent symbol,0; \ + .globl symbol; \ + .align 2; \ + .type symbol,@function; \ + .ent symbol,0; \ symbol: .frame sp,0,ra /* * NESTED - declare nested routine entry point */ #define NESTED(symbol, framesize, rpc) \ - .globl symbol; \ - .align 2; \ - .type symbol,@function; \ - .ent symbol,0; \ + .globl symbol; \ + .align 2; \ + .type symbol,@function; \ + .ent symbol,0; \ symbol: .frame sp, framesize, rpc /* * END - mark end of function */ #define END(function) \ - .end function; \ - .size function,.-function + .end function; \ + .size function,.-function /* * EXPORT - export definition of symbol */ #define EXPORT(symbol) \ - .globl symbol; \ + .globl symbol; \ symbol: /* * FEXPORT - export definition of a function symbol */ #define FEXPORT(symbol) \ - .globl symbol; \ - .type symbol,@function; \ + .globl symbol; \ + .type symbol,@function; \ symbol: /* * Global data declaration with size. */ #define EXPORTS(name,sz) \ - .globl name; \ - .type name,@object; \ - .size name,sz; \ + .globl name; \ + .type name,@object; \ + .size name,sz; \ name: /* * Weak data declaration with size. */ #define WEXPORT(name,sz) \ - .weakext name; \ - .type name,@object; \ - .size name,sz; \ + .weakext name; \ + .type name,@object; \ + .size name,sz; \ name: /* * Global data reference with size. */ #define IMPORT(name, size) \ - .extern name,size + .extern name,size /* * Global zeroed data. */ #define BSS(name,size) \ - .type name,@object; \ - .comm name,size + .type name,@object; \ + .comm name,size /* * Local zeroed data. */ #define LBSS(name,size) \ - .lcomm name,size + .lcomm name,size /* * ABS - export absolute symbol */ #define ABS(symbol,value) \ - .globl symbol; \ + .globl symbol; \ symbol = value #define TEXT(msg) \ - .pushsection .data; \ + .pushsection .data; \ 8: .asciiz msg; \ - .popsection; + .popsection; #define ENTRY(name) \ @@ -120,7 +118,94 @@ symbol = value /* * Macros to handle different pointer/register sizes for 32/64-bit code */ +#if defined ARCH_MIPS64 +/* + * Size of a register + */ +#define SZREG 8 + +/* + * Use the following macros in assemblercode to load/store registers, + * pointers etc. + */ +#define REG_S sd +#define REG_L ld +#define REG_SUBU dsubu +#define REG_ADDU daddu + +/* + * How to add/sub/load/store/shift C int variables. + */ +#define INT_ADD dadd +#define INT_ADDU daddu +#define INT_ADDI daddi +#define INT_ADDIU daddiu +#define INT_SUB dsub +#define INT_SUBU dsubu +#define INT_L ld +#define INT_S sd +#define INT_SLL dsll +#define INT_SLLV dsllv +#define INT_SRL dsrl +#define INT_SRLV dsrlv +#define INT_SRA dsra +#define INT_SRAV dsrav + +/* + * Use the following macros in assemblercode to load/store registers, + * pointers etc. + */ +#define LONG_ADD dadd +#define LONG_ADDU daddu +#define LONG_ADDI daddi +#define LONG_ADDIU daddiu +#define LONG_SUB dsub +#define LONG_SUBU dsubu +#define LONG_L ld +#define LONG_S sd +#define LONG_SP sdp +#define LONG_SLL dsll +#define LONG_SLLV dsllv +#define LONG_SRL dsrl +#define LONG_SRLV dsrlv +#define LONG_SRA dsra +#define LONG_SRAV dsrav + +#define LONG .dword +#define LONGSIZE 8 +#define LONGMASK 7 +#define LONGLOG 3 + +/* + * How to add/sub/load/store/shift pointers. + */ +#define PTR_ADD dadd +#define PTR_ADDU daddu +#define PTR_ADDI daddi +#define PTR_ADDIU daddiu +#define PTR_SUB dsub +#define PTR_SUBU dsubu +#define PTR_L ld +#define PTR_S sd +#define PTR_LA dla +#define PTR_LI dli +#define PTR_SLL dsll +#define PTR_SLLV dsllv +#define PTR_SRL dsrl +#define PTR_SRLV dsrlv +#define PTR_SRA dsra +#define PTR_SRAV dsrav + +#define PTR_SCALESHIFT 3 + +#define PTR .dword +#define PTRSIZE 8 +#define PTRLOG 3 + +#define MFC0 dmfc0 +#define MTC0 dmtc0 +#else /* * Size of a register */ @@ -214,6 +299,7 @@ symbol = value #define MFC0 mfc0 #define MTC0 mtc0 +#endif #define SSNOP sll zero, zero, 1 diff --git a/libcpu/mips/common/cache.h b/libcpu/mips/common/cache.h deleted file mode 100644 index 1c7cf41324..0000000000 --- a/libcpu/mips/common/cache.h +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Cache operations for the cache instruction. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle - * (C) Copyright 1999 Silicon Graphics, Inc. - */ -#ifndef __CACHE_H__ -#define __CACHE_H__ - - -#define KUSEG 0x00000000 -#define KSEG0 0x80000000 -#define KSEG1 0xa0000000 -#define KSEG2 0xc0000000 -#define KSEG3 0xe0000000 - -/* - * Cache Operations available on all MIPS processors with R4000-style caches - */ -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 - -#define Hit_Invalidate_I 0x10 -#define Hit_Invalidate_D 0x11 -#define Hit_Writeback_Inv_D 0x15 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 - -/* - *The lock state is cleared by executing an Index -Invalidate, Index Writeback Invalidate, Hit -Invalidate, or Hit Writeback Invalidate -operation to the locked line, or via an Index -Store Tag operation with the lock bit reset in -the TagLo register. - */ -#define Fetch_And_Lock_I 0x1c -#define Fetch_And_Lock_D 0x1d -/* - * R4000-specific cacheops - */ -#define Create_Dirty_Excl_D 0x0d -#define Fill 0x14 - -/* - * R4000SC and R4400SC-specific cacheops - */ -#define Index_Invalidate_SI 0x02 -#define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_SD 0x1b -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f - -/* - * R5000-specific cacheops - */ -#define R5K_Page_Invalidate_S 0x17 - -/* - * RM7000-specific cacheops - */ -#define Page_Invalidate_T 0x16 - -/* - * R1000-specific cacheops - * - * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. - * Most of the _S cacheops are identical to the R4000SC _SD cacheops. - */ -#define Index_Writeback_Inv_S 0x03 -#define Index_Load_Tag_S 0x07 -#define Index_Store_Tag_S 0x0B -#define Hit_Invalidate_S 0x13 -#define Cache_Barrier 0x14 -#define Hit_Writeback_Inv_S 0x17 -#define Index_Load_Data_I 0x18 -#define Index_Load_Data_D 0x19 -#define Index_Load_Data_S 0x1b -#define Index_Store_Data_I 0x1c -#define Index_Store_Data_D 0x1d -#define Index_Store_Data_S 0x1f - - -#ifndef __ASSEMBLER__ - -#ifndef dcache_size -#define dcache_size (g_mips_core.dcache_ways * g_mips_core.dcache_lines_per_way * g_mips_core.dcache_line_size) -#endif - -#ifndef icache_size -#define icache_size (g_mips_core.dcache_ways * g_mips_core.dcache_lines_per_way * g_mips_core.dcache_line_size) -#endif - -#ifndef cpu_dcache_line_size -#define cpu_dcache_line_size() g_mips_core.icache_line_size -#endif - -#ifndef cpu_icache_line_size -#define cpu_icache_line_size() g_mips_core.icache_line_size -#endif - -#define cache_op(op, addr) \ - __asm__ __volatile__( \ - " .set noreorder \n" \ - " .set mips3\n\t \n" \ - " cache %0, %1 \n" \ - " .set mips0 \n" \ - " .set reorder" \ - : \ - : "i" (op), "m" (*(unsigned char *)(addr))) - -#define cache16_unroll32(base, op) \ - __asm__ __volatile__( \ - " .set noreorder \n" \ - " .set mips3 \n" \ - " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \ - " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \ - " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \ - " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \ - " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \ - " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \ - " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \ - " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \ - " cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \ - " cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \ - " cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \ - " cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \ - " cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \ - " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \ - " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \ - " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \ - " .set mips0 \n" \ - " .set reorder \n" \ - : \ - : "r" (base), \ - "i" (op)); - - -static inline void flush_icache_line_indexed(rt_ubase_t addr) -{ - cache_op(Index_Invalidate_I, addr); -} - -static inline void flush_dcache_line_indexed(rt_ubase_t addr) -{ - cache_op(Index_Writeback_Inv_D, addr); -} - -static inline void flush_icache_line(rt_ubase_t addr) -{ - cache_op(Hit_Invalidate_I, addr); -} - -static inline void lock_icache_line(rt_ubase_t addr) -{ - cache_op(Fetch_And_Lock_I, addr); -} - -static inline void lock_dcache_line(rt_ubase_t addr) -{ - cache_op(Fetch_And_Lock_D, addr); -} - -static inline void flush_dcache_line(rt_ubase_t addr) -{ - cache_op(Hit_Writeback_Inv_D, addr); -} - -static inline void invalidate_dcache_line(rt_ubase_t addr) -{ - cache_op(Hit_Invalidate_D, addr); -} - -static inline void blast_dcache16(void) -{ - rt_ubase_t start = KSEG0; - rt_ubase_t end = start + dcache_size; - rt_ubase_t addr; - - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr, Index_Writeback_Inv_D); -} - -static inline void inv_dcache16(void) -{ - rt_ubase_t start = KSEG0; - rt_ubase_t end = start + dcache_size; - rt_ubase_t addr; - - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr, Hit_Invalidate_D); -} - -static inline void blast_icache16(void) -{ - rt_ubase_t start = KSEG0; - rt_ubase_t end = start + icache_size; - rt_ubase_t addr; - - for (addr = start; addr < end; addr += 0x200) - cache16_unroll32(addr, Index_Invalidate_I); -} - - - -void r4k_cache_init(void); -void r4k_cache_flush_all(void); -void r4k_icache_flush_all(void); -void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size); -void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size); -void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size); -void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size); - -#endif /*end of __ASSEMBLER__ */ - -#endif /* end of __CACHE_H__ */ diff --git a/libcpu/mips/common/context_gcc.S b/libcpu/mips/common/context_gcc.S new file mode 100644 index 0000000000..3fdbe374c9 --- /dev/null +++ b/libcpu/mips/common/context_gcc.S @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + * 2020-07-26 lizhirui Fixed some problems + */ + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ +#endif + +#include "mips_regs.h" +#include "stackframe.h" + + .section ".text", "ax" + .set noreorder + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) + * a0 --> from + * a1 --> to + */ + .globl rt_hw_context_switch +rt_hw_context_switch: + MTC0 ra, CP0_EPC + SAVE_ALL + + REG_S sp, 0(a0) /* store sp in preempted tasks TCB */ + REG_L sp, 0(a1) /* get new task stack pointer */ + + RESTORE_ALL_AND_RET + +/* + * void rt_hw_context_switch_to(rt_uint32 to)/* + * a0 --> to + */ + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + REG_L sp, 0(a0) /* get new task stack pointer */ + RESTORE_ALL_AND_RET + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* + */ + .globl rt_thread_switch_interrupt_flag + .globl rt_interrupt_from_thread + .globl rt_interrupt_to_thread + .globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + PTR_LA t0, rt_thread_switch_interrupt_flag + REG_L t1, 0(t0) + nop + bnez t1, _reswitch + nop + li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ + LONG_S t1, 0(t0) + PTR_LA t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ + LONG_S a0, 0(t0) +_reswitch: + PTR_LA t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ + LONG_S a1, 0(t0) + jr ra + nop + +/* + * void rt_hw_context_switch_interrupt_do(rt_base_t flag) + */ + .globl rt_interrupt_enter + .globl rt_interrupt_leave + .globl rt_general_exc_dispatch + .globl mips_irq_handle +mips_irq_handle: + SAVE_ALL + + /* let k0 keep the current context sp */ + move k0, sp + /* switch to kernel stack */ + PTR_LA sp, _system_stack + + jal rt_interrupt_enter + nop + /* Get Old SP from k0 as paremeter in a0 */ + move a0, k0 + jal rt_general_exc_dispatch + nop + jal rt_interrupt_leave + nop + + /* switch sp back to thread context */ + move sp, k0 + + /* + * if rt_thread_switch_interrupt_flag set, jump to + * rt_hw_context_switch_interrupt_do and do not return + */ + PTR_LA k0, rt_thread_switch_interrupt_flag + LONG_L k1, 0(k0) + beqz k1, spurious_interrupt + nop + LONG_S zero, 0(k0) /* clear flag */ + nop + + /* + * switch to the new thread + */ + PTR_LA k0, rt_interrupt_from_thread + LONG_L k1, 0(k0) + nop + LONG_S sp, 0(k1) /* store sp in preempted task TCB */ + + PTR_LA k0, rt_interrupt_to_thread + LONG_L k1, 0(k0) + nop + LONG_L sp, 0(k1) /* get new task stack pointer */ + j spurious_interrupt + nop + +spurious_interrupt: + RESTORE_ALL_AND_RET + .set reorder diff --git a/libcpu/mips/common/entry_gcc.S b/libcpu/mips/common/entry_gcc.S new file mode 100644 index 0000000000..d1a0704809 --- /dev/null +++ b/libcpu/mips/common/entry_gcc.S @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + */ + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ +#endif + +#include <mips.h> +#include <rtconfig.h> + +#include "asm.h" +#include <rtconfig.h> + + .section ".start", "ax" + .set noreorder + + /* the program entry */ + .globl _rtthread_entry +_rtthread_entry: +#ifndef RT_USING_SELF_BOOT + .globl _start +_start: +#endif + PTR_LA ra, _rtthread_entry + + /* disable interrupt */ + MTC0 zero, CP0_CAUSE + MTC0 zero, CP0_STATUS # Set CPU to disable interrupt. + ehb + +#ifdef ARCH_MIPS64 + dli t0, ST0_KX + MTC0 t0, CP0_STATUS +#endif + + /* setup stack pointer */ + PTR_LA sp, _system_stack + PTR_LA gp, _gp + + bal rt_cpu_early_init + nop + + /* clear bss */ + PTR_LA t0, __bss_start + PTR_LA t1, __bss_end + +_clr_bss_loop: + sw zero, 0(t0) + bne t1, t0, _clr_bss_loop + addu t0, 4 + /* jump to RT-Thread RTOS */ + jal rtthread_startup + nop + + /* restart, never die */ + j _start + nop diff --git a/libcpu/mips/common/exception.c b/libcpu/mips/common/exception.c new file mode 100644 index 0000000000..3da8ecead6 --- /dev/null +++ b/libcpu/mips/common/exception.c @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + */ + +#include <rtthread.h> +#include <rthw.h> +#include "exception.h" +#include "mips_regs.h" + +/** + * @addtogroup MIPS + */ + +/*@{*/ + +extern rt_ubase_t __ebase_entry; +rt_ubase_t rt_interrupt_from_thread; +rt_ubase_t rt_interrupt_to_thread; +rt_ubase_t rt_thread_switch_interrupt_flag; + +const char *exception_name[] = { + "Interrupt", + "(X)TLB Modify Exception", + "(X)TLB Read/Fetch Exception", + "(X)TLB Write Exception", + "Address Read/Fetch Exception", + "Address Write Exception", + "", + "", + "Syscall", + "Breakpoint", + "Reversed Instruction Exception", + "Coprocessor Unit Invalid", + "Overflow", + "Trap", + "FPU Exception in Vector Instruction", + "FPU Exception", + "Loongson Custom Exception", + "", + "", + "(X)TLB Read Denied Exception", + "(X)TLB Execute Denied Exception", + "Vector Module Disabled Exception", + "", + "", + "", + "", + "", + "", + "", + "", + "Cache Error Exception", + "" + }; + +rt_base_t rt_hw_interrupt_disable(void) +{ + rt_base_t status = read_c0_status(); + clear_c0_status(ST0_IE); + return status; +} + +void rt_hw_interrupt_enable(rt_base_t level) +{ + write_c0_status(level); +} + +/** + * exception handle table + */ +#define RT_EXCEPTION_MAX 32 +exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX]; + +/** + * setup the exception handle + */ +exception_func_t rt_set_except_vector(int n, exception_func_t func) +{ + exception_func_t old_handler = sys_exception_handlers[n]; + + if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func)) + { + return 0; + } + + sys_exception_handlers[n] = func; + + return old_handler; +} + +void mips_dump_regs(struct pt_regs *regs) +{ + int i, j; + for (i = 0; i < 32 / 4; i++) + { + for (j = 0; j < 4; j++) + { + int reg = 4 * i + j; + rt_kprintf("%d: 0x%08x, ", reg, regs->regs[reg]); + } + rt_kprintf("\n"); + } +} + +void tlb_refill_handler(void) +{ + rt_kprintf("TLB-Miss Happens, EPC: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); +} + +void cache_error_handler(void) +{ + rt_kprintf("Cache Exception Happens, EPC: 0x%08x\n", read_c0_epc()); + rt_hw_cpu_shutdown(); +} + +static void unhandled_exception_handle(struct pt_regs *regs) +{ + rt_kprintf("Unknown Exception, EPC: 0x%p, CAUSE: 0x%08x\n", read_c0_epc(), read_c0_cause()); + rt_kprintf("Exception Name:%s\n",exception_name[(read_c0_cause() >> 2) & 0x1f]); +#ifdef SOC_LS2K1000 + rt_kprintf("ExeCode = 0x%08x,BadAddr = 0x%p\n",(read_c0_cause() >> 2) & 0x1f,mmu_tlb_get_bad_vaddr()); +#else + rt_kprintf("ExeCode = 0x%08x\n",(read_c0_cause() >> 2) & 0x1f); +#endif + rt_kprintf("ST0: 0x%08x ",regs->cp0_status); + rt_kprintf("ErrorPC: 0x%p\n",read_c0_errorepc()); + mips_dump_regs(regs); + rt_hw_cpu_shutdown(); +} + +static void install_default_exception_handler(void) +{ + rt_int32_t i; + + for (i = 0; i < RT_EXCEPTION_MAX; i++) + sys_exception_handlers[i] = + (exception_func_t)unhandled_exception_handle; +} + +int rt_hw_exception_init(void) +{ + rt_ubase_t ebase = (rt_ubase_t)&__ebase_entry; +#ifdef ARCH_MIPS64 + ebase |= 0xffffffff00000000; +#endif + write_c0_ebase(ebase); + clear_c0_status(ST0_BEV | ST0_ERL | ST0_EXL); + clear_c0_status(ST0_IM | ST0_IE); + set_c0_status(ST0_CU0); + /* install the default exception handler */ + install_default_exception_handler(); + + return RT_EOK; +} + +void rt_general_exc_dispatch(struct pt_regs *regs) +{ + rt_ubase_t cause, exccode; + cause = read_c0_cause(); + exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; + + if (exccode == 0) + { + rt_ubase_t status, pending; + + status = read_c0_status(); + pending = (cause & CAUSEF_IP) & (status & ST0_IM); + if (pending & CAUSEF_IP0) + rt_do_mips_cpu_irq(0); + if (pending & CAUSEF_IP1) + rt_do_mips_cpu_irq(1); + if (pending & CAUSEF_IP2) + rt_do_mips_cpu_irq(2); + if (pending & CAUSEF_IP3) + rt_do_mips_cpu_irq(3); + if (pending & CAUSEF_IP4) + rt_do_mips_cpu_irq(4); + if (pending & CAUSEF_IP5) + rt_do_mips_cpu_irq(5); + if (pending & CAUSEF_IP6) + rt_do_mips_cpu_irq(6); + if (pending & CAUSEF_IP7) + rt_do_mips_cpu_irq(7); + } + else + { + if (sys_exception_handlers[exccode]) + sys_exception_handlers[exccode](regs); + } +} + +/* Mask means disable the interrupt */ +void mips_mask_cpu_irq(rt_uint32_t irq) +{ + clear_c0_status(1 << (STATUSB_IP0 + irq)); +} + +/* Unmask means enable the interrupt */ +void mips_unmask_cpu_irq(rt_uint32_t irq) +{ + set_c0_status(1 << (STATUSB_IP0 + irq)); +} + +/*@}*/ diff --git a/libcpu/mips/common/exception.h b/libcpu/mips/common/exception.h index 2cb03d20e7..68107f6235 100644 --- a/libcpu/mips/common/exception.h +++ b/libcpu/mips/common/exception.h @@ -1,166 +1,28 @@ /* - * File : cpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team + * Copyright (c) 2006-2019, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2010-05-17 swkyer first version + * 2019-12-04 Jiaxun Yang Initial version */ + #ifndef __EXCEPTION_H__ #define __EXCEPTION_H__ +#include "ptrace.h" -/* - * important register numbers - */ -#define REG_EPC 37 -#define REG_FP 72 -#define REG_SP 29 - -/* - * Stack layout for the GDB exception handler - * Derived from the stack layout described in asm-mips/stackframe.h - * - * The first PTRSIZE*6 bytes are argument save space for C subroutines. - */ -#define NUMREGS 90 - -#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */ -#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */ -#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */ -#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */ -#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */ -#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */ -#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */ -#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */ -#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */ -#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */ -#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */ -#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */ -#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */ -#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */ -#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */ -#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */ -#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */ -#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */ -#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */ -#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */ -#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */ -#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */ -#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */ -#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */ -#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */ -#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */ -#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */ -#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */ -#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */ -#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */ -#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */ -#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */ - -/* - * Saved special registers - */ -#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */ -#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */ -#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */ -#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */ -#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */ -#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */ - -///* -// * Saved floating point registers -// */ -//#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */ -//#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */ -//#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */ -//#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */ -//#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */ -//#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */ -//#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */ -//#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */ -//#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */ -//#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */ -//#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */ -//#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */ -//#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */ -//#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */ -//#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */ -//#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */ -//#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */ -//#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */ -//#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */ -//#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */ -//#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */ -//#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */ -//#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */ -//#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */ -//#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */ -//#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */ -//#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */ -//#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */ -//#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */ -//#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */ -//#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */ -//#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */ -// -//#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */ -//#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */ -//#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */ -// -//#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */ -// -///* -// * Again, CP0 registers -// */ -//#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */ -#define GDB_FR_FRP ((GDB_FR_EPC) + LONGSIZE) /* 72 */ -#define GDB_FR_CP0_INDEX ((GDB_FR_FRP) + LONGSIZE) /* 74 */ - -#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */ -#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */ -#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */ -#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */ -#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */ -#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */ -#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */ -#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */ -#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */ -#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */ -#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */ -#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */ -#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */ -#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */ -#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */ - -#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1)) - -/* - * This is the same as above, but for the high-level - * part of the INT stub. - */ -typedef struct pt_regs_s -{ - /* Saved main processor registers. */ - rt_base_t regs[32]; - /* Saved special registers. */ - rt_base_t cp0_status; - rt_base_t hi; - rt_base_t lo; - rt_base_t cp0_badvaddr; - rt_base_t cp0_cause; - rt_base_t cp0_epc; -} pt_regs_t; +#ifndef __ASSEMBLY__ -typedef void (* exception_func_t)(pt_regs_t *regs); +typedef void (* exception_func_t)(struct pt_regs *regs); +extern int rt_hw_exception_init(void); extern exception_func_t sys_exception_handlers[]; +extern void rt_do_mips_cpu_irq(rt_uint32_t ip); exception_func_t rt_set_except_vector(int n, exception_func_t func); -void install_default_execpt_handle(void); +extern void mips_mask_cpu_irq(rt_uint32_t irq); +extern void mips_unmask_cpu_irq(rt_uint32_t irq); +#endif #endif /* end of __EXCEPTION_H__ */ diff --git a/libcpu/mips/common/exception_gcc.S b/libcpu/mips/common/exception_gcc.S new file mode 100644 index 0000000000..c685928a84 --- /dev/null +++ b/libcpu/mips/common/exception_gcc.S @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + * 2020-07-26 lizhirui Add xtlb exception entry + */ +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ +#endif + +#include <mips.h> + + .section ".exc_vectors", "ax" + .extern tlb_refill_handler + .extern cache_error_handler + .extern mips_irq_handle + + /* 0x0 - TLB refill handler */ + .global tlb_refill_exception + .type tlb_refill_exception,@function +ebase_start: +tlb_refill_exception: + b _general_exception_handler + nop + + /* 0x080 - XTLB refill handler */ + .org ebase_start + 0x080 + b _general_exception_handler + nop + + /* 0x100 - Cache error handler */ + .org ebase_start + 0x100 + j cache_error_handler + nop + + /* 0x180 - Exception/Interrupt handler */ + .global general_exception + .type general_exception,@function + .org ebase_start + 0x180 +general_exception: + b _general_exception_handler + nop + + /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */ + .global irq_exception + .type irq_exception,@function + .org ebase_start + 0x200 +irq_exception: + b _general_exception_handler + nop + + /* general exception handler */ +_general_exception_handler: + .set noreorder + PTR_LA k0, mips_irq_handle + jr k0 + nop + .set reorder + + /* interrupt handler */ +_irq_handler: + .set noreorder + PTR_LA k0, mips_irq_handle + jr k0 + nop + .set reorder diff --git a/libcpu/mips/common/mips.h b/libcpu/mips/common/mips.h index 6a9811ae7e..94f664308c 100644 --- a/libcpu/mips/common/mips.h +++ b/libcpu/mips/common/mips.h @@ -1,39 +1,23 @@ /* - * File : mips.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2019, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2016��9��7�� Urey the first version + * 2016-09-07 Urey first version */ #ifndef _COMMON_MIPS_H_ #define _COMMON_MIPS_H_ #include "mips_cfg.h" - +#include "ptrace.h" #include "mips_types.h" -#include "mips_asm.h" -#include "mips_def.h" +#include "asm.h" #include "mips_regs.h" #include "mips_addrspace.h" #include "mips_cache.h" -#include "mips_context.h" -#include "mips_excpt.h" +#include "exception.h" #endif /* _COMMON_MIPS_H_ */ diff --git a/libcpu/mips/common/mips_addrspace.h b/libcpu/mips/common/mips_addrspace.h index 3b82a4e371..f3bb60662e 100644 --- a/libcpu/mips/common/mips_addrspace.h +++ b/libcpu/mips/common/mips_addrspace.h @@ -1,25 +1,11 @@ /* - * File : mips_addrspace.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2019, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2016��9��12�� Urey the first version + * 2019-12-04 Jiaxun Yang Initial version */ #ifndef _MIPS_ADDRSPACE_H_ @@ -38,7 +24,7 @@ #define _ATYPE_ __PTRDIFF_TYPE__ #define _ATYPE32_ int #define _ATYPE64_ __s64 -#ifdef CONFIG_64BIT +#ifdef ARCH_MIPS64 #define _CONST64_(x) x ## L #else #define _CONST64_(x) x ## LL @@ -68,7 +54,7 @@ #define XPHYSADDR(a) ((_ACAST64_(a)) & \ _CONST64_(0x000000ffffffffff)) -#ifdef CONFIG_64BIT +#ifdef ARCH_MIPS64 /* * Memory segments (64bit kernel mode addresses) @@ -89,6 +75,12 @@ #define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) #define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) +#define KUSEGBASE 0xffffffff00000000 +#define KSEG0BASE 0xffffffff80000000 +#define KSEG1BASE 0xffffffffa0000000 +#define KSEG2BASE 0xffffffffc0000000 +#define KSEG3BASE 0xffffffffe0000000 + #else #define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE) @@ -104,24 +96,25 @@ #define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE) #define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE) -/* - * Memory segments (32bit kernel mode addresses) - * These are the traditional names used in the 32-bit universe. - */ -//#define KUSEGBASE 0x00000000 -//#define KSEG0BASE 0x80000000 -//#define KSEG1BASE 0xa0000000 -//#define KSEG2BASE 0xc0000000 -//#define KSEG3BASE 0xe0000000 - #define CKUSEG 0x00000000 #define CKSEG0 0x80000000 #define CKSEG1 0xa0000000 #define CKSEG2 0xc0000000 #define CKSEG3 0xe0000000 +/* + * Memory segments (32bit kernel mode addresses) + * These are the traditional names used in the 32-bit universe. + */ +#define KUSEGBASE 0x00000000 +#define KSEG0BASE 0x80000000 +#define KSEG1BASE 0xa0000000 +#define KSEG2BASE 0xc0000000 +#define KSEG3BASE 0xe0000000 + #endif + /* * Cache modes for XKPHYS address conversion macros */ @@ -147,14 +140,6 @@ * Returns the uncached address of a sdram address */ #ifndef __ASSEMBLY__ -#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229) -/* We use a 36 bit physical address map here and - cannot access physical memory directly from core */ -#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000) -#else /* !CONFIG_SOC_AU1X00 */ -#define UNCACHED_SDRAM(a) CKSEG1ADDR(a) -#endif /* CONFIG_SOC_AU1X00 */ -#endif /* __ASSEMBLY__ */ /* * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting @@ -162,46 +147,19 @@ * R8000 implements most with its 48-bit physical address space. */ #define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ - -#ifndef CONFIG_CPU_R8000 - -/* - * The R8000 doesn't have the 32-bit compat spaces so we don't define them - * in order to catch bugs in the source code. - */ - #define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000) #define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ -#endif - #define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK) #define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE) +#endif #ifndef __ASSEMBLY__ -/* - * Change virtual addresses to physical addresses and vv. - * These are trivial on the 1:1 Linux/MIPS mapping - */ -static inline phys_addr_t virt_to_phys(volatile void * address) -{ -#ifndef CONFIG_64BIT - return CPHYSADDR(address); -#else - return XPHYSADDR(address); +#define REG8( addr ) (*(volatile u8 *) (addr)) +#define REG16( addr ) (*(volatile u16 *)(addr)) +#define REG32( addr ) (*(volatile u32 *)(addr)) +#define REG64( addr ) (*(volatile u64 *)(addr)) #endif -} - -static inline void * phys_to_virt(unsigned long address) -{ -#ifndef CONFIG_64BIT - return (void *)KSEG0ADDR(address); -#else - return (void *)CKSEG0ADDR(address); -#endif -} -#endif - #endif /* _MIPS_ADDRSPACE_H_ */ diff --git a/libcpu/mips/common/mips_asm.h b/libcpu/mips/common/mips_asm.h deleted file mode 100644 index 8f97e370ab..0000000000 --- a/libcpu/mips/common/mips_asm.h +++ /dev/null @@ -1,447 +0,0 @@ -/* - * File : mips_asm.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��7�� Urey the first version - */ - -#ifndef _MIPS_ASM_H_ -#define _MIPS_ASM_H_ - - -/* ********************************************************************* */ -/* Interface macro & data definition */ - -#ifdef __ASSEMBLY__ - -/******** ASSEMBLER SPECIFIC DEFINITIONS ********/ - -#ifdef __ghs__ -#define ALIGN(x) .##align (1 << (x)) -#else -#define ALIGN(x) .##align (x) -#endif - -#ifdef __ghs__ -#define SET_MIPS3() -#define SET_MIPS0() -#define SET_PUSH() -#define SET_POP() -#else -#define SET_MIPS3() .##set mips3 -#define SET_MIPS0() .##set mips0 -#define SET_PUSH() .##set push -#define SET_POP() .##set pop -#endif - -/* Different assemblers have different requirements for how to - * indicate that the next section is bss : - * - * Some use : .bss - * Others use : .section bss - * - * We select which to use based on _BSS_OLD_, which may be defined - * in makefile. - */ -#ifdef _BSS_OLD_ -#define BSS .##section bss -#else -#define BSS .##bss -#endif - -#define LEAF(name)\ - .##text;\ - .##globl name;\ - .##ent name;\ -name: - - -#define SLEAF(name)\ - .##text;\ - .##ent name;\ -name: - - -#ifdef __ghs__ -#define END(name)\ - .##end name -#else -#define END(name)\ - .##size name,.-name;\ - .##end name -#endif - - -#define EXTERN(name) - -#else - -#define U64 unsigned long long -#define U32 unsigned int -#define U16 unsigned short -#define U8 unsigned char -#define S64 signed long long -#define S32 int -#define S16 short int -#define S8 signed char -//#define bool U8 - -#ifndef _SIZE_T_ -#define _SIZE_T_ -#ifdef __ghs__ - typedef unsigned int size_t; -#else - typedef unsigned long size_t; -#endif -#endif - -/* Sets the result on bPort */ -#define BIT_SET(bPort,bBitMask) (bPort |= bBitMask) -#define BIT_CLR(bPort,bBitMask) (bPort &= ~bBitMask) - -/* Returns the result */ -#define GET_BIT_SET(bPort,bBitMask) (bPort | bBitMask) -#define GET_BIT_CLR(bPort,bBitMask) (bPort & ~bBitMask) - -/* Returns 0 if the condition is False & a non-zero value if it is True */ -#define TEST_BIT_SET(bPort,bBitMask) (bPort & bBitMask) -#define TEST_BIT_CLR(bPort,bBitMask) ((~bPort) & bBitMask) - -/* Split union definitions */ -typedef union tunSU16 -{ - U16 hwHW; - struct tst2U8 - { - U8 bB0; - U8 bB1; - }st2U8; -}tunSU16; - -typedef union tunSU32 -{ - U32 wW; - struct tst2U16 - { - U16 hwHW0; - U16 hwHW1; - }st2U16; - struct tst4U8 - { - U8 bB0; - U8 bB1; - U8 bB2; - U8 bB3; - }st4U8; -}tunSU32; - -#endif /* #ifdef __ASSEMBLY__ */ - - -/******** DEFINITIONS FOR BOTH ASSEMBLER AND C ********/ - - -#define NO_ERR 0x00000000 /* operation completed successfully */ -#define ERR 0xffffffff /* operation completed not successfully */ - -#define False 0 -#define True !False - -#ifndef NULL -#define NULL ((void *)0) -#endif//NULL - -#ifndef MIN -#define MIN(x,y) ((x) < (y) ? (x) : (y)) -#endif//MIN - -#ifndef MAX -#define MAX(x,y) ((x) > (y) ? (x) : (y)) -#endif//MAX - -#define MAXUINT(w) (\ - ((w) == sizeof(U8)) ? 0xFFU :\ - ((w) == sizeof(U16)) ? 0xFFFFU :\ - ((w) == sizeof(U32)) ? 0xFFFFFFFFU : 0\ - ) - -#define MAXINT(w) (\ - ((w) == sizeof(S8)) ? 0x7F :\ - ((w) == sizeof(S16)) ? 0x7FFF :\ - ((w) == sizeof(S32)) ? 0x7FFFFFFF : 0\ - ) - -#define MSK(n) ((1 << (n)) - 1) - -#define KUSEG_MSK 0x80000000 -#define KSEG_MSK 0xE0000000 - -#define KUSEGBASE 0x00000000 -#define KSEG0BASE 0x80000000 -#define KSEG1BASE 0xA0000000 -#define KSSEGBASE 0xC0000000 -#define KSEG3BASE 0xE0000000 - -/* Below macros perform the following functions : - * - * KSEG0 : Converts KSEG0/1 or physical addr (below 0.5GB) to KSEG0. - * KSEG1 : Converts KSEG0/1 or physical addr (below 0.5GB) to KSEG1. - * PHYS : Converts KSEG0/1 or physical addr (below 0.5GB) to physical address. - * KSSEG : Not relevant for converting, but used for determining range. - * KSEG3 : Not relevant for converting, but used for determining range. - * KUSEG : Not relevant for converting, but used for determining range. - * KSEG0A : Same as KSEG0 but operates on register rather than constant. - * KSEG1A : Same as KSEG1 but operates on register rather than constant. - * PHYSA : Same as PHYS but operates on register rather than constant. - * CACHED : Alias for KSEG0 macro . - * (Note that KSEG0 cache attribute is determined by K0 - * field of Config register, but this is typically cached). - * UNCACHED : Alias for KSEG1 macro . - */ -#ifdef __ASSEMBLY__ -#define KSEG0(addr) (((addr) & ~KSEG_MSK) | KSEG0BASE) -#define KSEG1(addr) (((addr) & ~KSEG_MSK) | KSEG1BASE) -#define KSSEG(addr) (((addr) & ~KSEG_MSK) | KSSEGBASE) -#define KSEG3(addr) (((addr) & ~KSEG_MSK) | KSEG3BASE) -#define KUSEG(addr) (((addr) & ~KUSEG_MSK) | KUSEGBASE) -#define PHYS(addr) ( (addr) & ~KSEG_MSK) -#define KSEG0A(reg) and reg, ~KSEG_MSK; or reg, KSEG0BASE -#define KSEG1A(reg) and reg, ~KSEG_MSK; or reg, KSEG1BASE -#define PHYSA(reg) and reg, ~KSEG_MSK -#else -#define KSEG0(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG0BASE) -#define KSEG1(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG1BASE) -#define KSSEG(addr) (((U32)(addr) & ~KSEG_MSK) | KSSEGBASE) -#define KSEG3(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG3BASE) -#define KUSEG(addr) (((U32)(addr) & ~KUSEG_MSK) | KUSEGBASE) -#define PHYS(addr) ((U32)(addr) & ~KSEG_MSK) -#endif - -#define CACHED(addr) KSEG0(addr) -#define UNCACHED(addr) KSEG1(addr) - - -#ifdef __ASSEMBLY__ -/* Macroes to access variables at constant addresses - * Compensates for signed 16 bit displacement - * Typical use: li a0, HIKSEG1(ATLAS_ASCIIWORD) - * sw v1, LO_OFFS(ATLAS_ASCIIWORD)(a0) - */ -#define HIKSEG0(addr) ((KSEG0(addr) + 0x8000) & 0xffff0000) -#define HIKSEG1(addr) ((KSEG1(addr) + 0x8000) & 0xffff0000) -#define HI_PART(addr) (((addr) + 0x8000) & 0xffff0000) -#define LO_OFFS(addr) ((addr) & 0xffff) -#endif - - -/* Most/Least significant 32 bit from 64 bit double word */ -#define HI32(data64) ((U32)(data64 >> 32)) -#define LO32(data64) ((U32)(data64 & 0xFFFFFFFF)) - -#if ((!defined(__ASSEMBLY__)) && (!defined(__LANGUAGE_ASSEMBLY))) -#define REG8( addr ) (*(volatile U8 *) (addr)) -#define REG16( addr ) (*(volatile U16 *)(addr)) -#define REG32( addr ) (*(volatile U32 *)(addr)) -#define REG64( addr ) (*(volatile U64 *)(addr)) -#endif - -/* Register field mapping */ -#define REGFIELD(reg, rfld) (((reg) & rfld##_MSK) >> rfld##_SHF) - -/* absolute register address, access */ -#define REGA(addr) REG32(addr) - -/* physical register address, access: base address + offsett */ -#define REGP(base,phys) REG32( (U32)(base) + (phys) ) - -/* relative register address, access: base address + offsett */ -#define REG(base,offs) REG32( (U32)(base) + offs##_##OFS ) - -/* relative register address, access: base address + offsett */ -#define REG_8(base,offs) REG8( (U32)(base) + offs##_##OFS ) - -/* relative register address, access: base address + offsett */ -#define REG_16(base,offs) REG16( (U32)(base) + offs##_##OFS ) - -/* relative register address, access: base address + offsett */ -#define REG_64(base,offs) REG64( (U32)(base) + offs##_##OFS ) - -/************************************** - * Macroes not used by YAMON any more - * (kept for backwards compatibility) - */ -/* register read field */ -#define REGARD(addr,fld) ((REGA(addr) & addr##_##fld##_##MSK) \ - >> addr##_##fld##_##SHF) - -/* register write numeric field value */ -#define REGAWRI(addr,fld,intval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\ - | ((intval) << addr##_##fld##_##SHF)) - -/* register write enumerated field value */ -#define REGAWRE(addr,fld,enumval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\ - | ((addr##_##fld##_##enumval) << addr##_##fld##_##SHF)) - - -/* Examples: - * - * exccode = REGARD(CPU_CAUSE,EXC); - * - * REGA(SDR_CONTROL) = REGAWRI(OSG_CONTROL,TMO,17) - * | REGAWRE(OSG_CONTROL,DTYPE,PC1); - */ - - -/* register read field */ -#define REGRD(base,offs,fld) ((REG(base,offs) & offs##_##fld##_##MSK) \ - >> offs##_##fld##_##SHF) - -/* register write numeric field value */ -#define REGWRI(base,offs,fld,intval)((REG(base,offs)& ~(offs##_##fld##_##MSK))\ - | (((intval) << offs##_##fld##_##SHF) & offs##_##fld##_##MSK)) - -/* register write enumerated field value */ -#define REGWRE(base,offs,fld,enumval)((REG(base,offs) & ~(offs##_##fld##_##MSK))\ - | ((offs##_##fld##_##enumval) << offs##_##fld##_##SHF)) - - -/* physical register read field */ -#define REGPRD(base,phys,fld) ((REGP(base,phys) & phys##_##fld##_##MSK) \ - >> phys##_##fld##_##SHF) - -/* physical register write numeric field value */ -#define REGPWRI(base,phys,fld,intval)((REGP(base,phys)& ~(phys##_##fld##_##MSK))\ - | ((intval) << phys##_##fld##_##SHF)) - -/* physical register write enumerated field value */ -#define REGPWRE(base,phys,fld,enumval)((REGP(base,phys) & ~(phys##_##fld##_##MSK))\ - | ((phys##_##fld##_##enumval) << phys##_##fld##_##SHF)) -/* - * End of macroes not used by YAMON any more - *********************************************/ - -/* Endian related macros */ - -#define SWAP_BYTEADDR32( addr ) ( (addr) ^ 0x3 ) -#define SWAP_U16ADDR32( addr ) ( (addr) ^ 0x2 ) - -/* Set byte address to little endian format */ -#ifdef EL -#define SWAP_BYTEADDR_EL(addr) addr -#else -#define SWAP_BYTEADDR_EL(addr) SWAP_BYTEADDR32( addr ) -#endif - -/* Set byte address to big endian format */ -#ifdef EB -#define SWAP_BYTEADDR_EB(addr) addr -#else -#define SWAP_BYTEADDR_EB(addr) SWAP_BYTEADDR32( addr ) -#endif - -/* Set U16 address to little endian format */ -#ifdef EL -#define SWAP_U16ADDR_EL(addr) addr -#else -#define SWAP_U16ADDR_EL(addr) SWAP_U16ADDR32( addr ) -#endif - -/* Set U16 address to big endian format */ -#ifdef EB -#define SWAP_U16ADDR_EB(addr) addr -#else -#define SWAP_U16ADDR_EB(addr) SWAP_U16ADDR32( addr ) -#endif - -#ifdef EL -#define REGW32LE(addr, data) REG32(addr) = (data) -#define REGR32LE(addr, data) (data) = REG32(addr) -#else -#define REGW32LE(addr, data) REG32(addr) = SWAPEND32(data) -#define REGR32LE(addr, data) (data) = REG32(addr), (data) = SWAPEND32(data) -#endif - -/* Set of 'LE'-macros, convert by BE: */ -#ifdef EL -#define CPU_TO_LE32( value ) (value) -#define LE32_TO_CPU( value ) (value) - -#define CPU_TO_LE16( value ) (value) -#define LE16_TO_CPU( value ) (value) -#else -#define CPU_TO_LE32( value ) ( ( ((U32)value) << 24) | \ - ((0x0000FF00UL & ((U32)value)) << 8) | \ - ((0x00FF0000UL & ((U32)value)) >> 8) | \ - ( ((U32)value) >> 24) ) -#define LE32_TO_CPU( value ) CPU_TO_LE32( value ) - -#define CPU_TO_LE16( value ) ( ((U16)(((U16)value) << 8)) | \ - ((U16)(((U16)value) >> 8)) ) -#define LE16_TO_CPU( value ) CPU_TO_LE16( value ) -#endif - -/* Set of 'BE'-macros, convert by LE: */ -#ifdef EB -#define CPU_TO_BE32( value ) (value) -#define BE32_TO_CPU( value ) (value) - -#define CPU_TO_BE16( value ) (value) -#define BE16_TO_CPU( value ) (value) -#else -#define CPU_TO_BE32( value ) ( ( ((U32)value) << 24) | \ - ((0x0000FF00UL & ((U32)value)) << 8) | \ - ((0x00FF0000UL & ((U32)value)) >> 8) | \ - ( ((U32)value) >> 24) ) -#define BE32_TO_CPU( value ) CPU_TO_BE32( value ) - -#define CPU_TO_BE16( value ) ( ((U16)(((U16)value) << 8)) | \ - ((U16)(((U16)value) >> 8)) ) -#define BE16_TO_CPU( value ) CPU_TO_BE16( value ) -#endif - - -/* Control characters */ -#define CTRL_A ('A'-0x40) -#define CTRL_B ('B'-0x40) -#define CTRL_C ('C'-0x40) -#define CTRL_D ('D'-0x40) -#define CTRL_E ('E'-0x40) -#define CTRL_F ('F'-0x40) -#define CTRL_H ('H'-0x40) -#define CTRL_K ('K'-0x40) -#define CTRL_N ('N'-0x40) -#define CTRL_P ('P'-0x40) -#define CTRL_U ('U'-0x40) -#define BACKSPACE 0x08 -#define DEL 0x7F -#define TAB 0x09 -#define CR 0x0D /* Enter Key */ -#define LF 0x0A -#define ESC 0x1B -#define SP 0x20 -#define CSI 0x9B - - -/* DEF2STR(x) converts #define symbol to string */ -#define DEF2STR1(x) #x -#define DEF2STR(x) DEF2STR1(x) - - -#endif /* _MIPS_ASM_H_ */ diff --git a/libcpu/mips/common/mips_cache.c b/libcpu/mips/common/mips_cache.c index 1c979b7106..8c86bb131a 100644 --- a/libcpu/mips/common/mips_cache.c +++ b/libcpu/mips/common/mips_cache.c @@ -19,7 +19,7 @@ * * Change Logs: * Date Author Notes - * 2016��9��7�� Urey the first version + * 2016-09-07 Urey the first version */ #include <rtthread.h> diff --git a/libcpu/mips/common/mips_cache.h b/libcpu/mips/common/mips_cache.h index a947041073..438dd76cde 100644 --- a/libcpu/mips/common/mips_cache.h +++ b/libcpu/mips/common/mips_cache.h @@ -19,7 +19,7 @@ * * Change Logs: * Date Author Notes - * 2016��9��10�� Urey the first version + * 2016-09-07 Urey the first version */ #ifndef _MIPS_CACHE_H_ @@ -38,11 +38,7 @@ #define INDEX_LOAD_TAG_D 0x05 #define INDEX_STORE_TAG_I 0x08 #define INDEX_STORE_TAG_D 0x09 -#if defined(CONFIG_CPU_LOONGSON2) -#define HIT_INVALIDATE_I 0x00 -#else #define HIT_INVALIDATE_I 0x10 -#endif #define HIT_INVALIDATE_D 0x11 #define HIT_WRITEBACK_INV_D 0x15 diff --git a/libcpu/mips/common/mips_cfg.h b/libcpu/mips/common/mips_cfg.h index 3f0575d65a..f7e38b4af4 100644 --- a/libcpu/mips/common/mips_cfg.h +++ b/libcpu/mips/common/mips_cfg.h @@ -19,7 +19,7 @@ * * Change Logs: * Date Author Notes - * 2016��9��10�� Urey the first version + * 2016-09-07 Urey the first version */ #ifndef _MIPS_CFG_H_ @@ -30,12 +30,12 @@ typedef struct mips32_core_cfg { uint16_t icache_line_size; -// uint16_t icache_lines_per_way; -// uint16_t icache_ways; + uint16_t icache_lines_per_way; + uint16_t icache_ways; uint16_t icache_size; uint16_t dcache_line_size; -// uint16_t dcache_lines_per_way; -// uint16_t dcache_ways; + uint16_t dcache_lines_per_way; + uint16_t dcache_ways; uint16_t dcache_size; uint16_t max_tlb_entries; /* number of tlb entry */ diff --git a/libcpu/mips/common/mips_context.h b/libcpu/mips/common/mips_context.h deleted file mode 100644 index 60d573784d..0000000000 --- a/libcpu/mips/common/mips_context.h +++ /dev/null @@ -1,280 +0,0 @@ -/* - * File : mips_context_asm.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��7�� Urey the first version - */ - -#ifndef _MIPS_CONTEXT_ASM_H_ -#define _MIPS_CONTEXT_ASM_H_ - -#define CONTEXT_SIZE ( STK_CTX_SIZE + FPU_ADJ ) -#ifdef __mips_hard_float -#define FPU_ADJ (32 * 4 + 8) /* FP0-FP31 + CP1_STATUS */ -#define FPU_CTX ( CONTEXT_SIZE - FPU_ADJ ) -#else -#define FPU_ADJ 0 -#endif - - - -#ifdef __ASSEMBLY__ - -#ifdef __mips_hard_float -.global _fpctx_save -.global _fpctx_load -#endif - -.macro SAVE_CONTEXT - .set push - .set noat - .set noreorder - .set volatile - - //save SP - move k1, sp - move k0, sp - subu sp, k1, CONTEXT_SIZE - sw k0, (29 * 4)(sp) - - //save REG - sw $0, ( 0 * 4)(sp) - sw $1, ( 1 * 4)(sp) - sw $2, ( 2 * 4)(sp) - sw $3, ( 3 * 4)(sp) - sw $4, ( 4 * 4)(sp) - sw $5, ( 5 * 4)(sp) - sw $6, ( 6 * 4)(sp) - sw $7, ( 7 * 4)(sp) - sw $8, ( 8 * 4)(sp) - sw $9, ( 9 * 4)(sp) - sw $10, (10 * 4)(sp) - sw $11, (11 * 4)(sp) - sw $12, (12 * 4)(sp) - sw $13, (13 * 4)(sp) - sw $14, (14 * 4)(sp) - sw $15, (15 * 4)(sp) - sw $16, (16 * 4)(sp) - sw $17, (17 * 4)(sp) - sw $18, (18 * 4)(sp) - sw $19, (19 * 4)(sp) - sw $20, (20 * 4)(sp) - sw $21, (21 * 4)(sp) - sw $22, (22 * 4)(sp) - sw $23, (23 * 4)(sp) - sw $24, (24 * 4)(sp) - sw $25, (25 * 4)(sp) - /* K0 K1 */ - sw $28, (28 * 4)(sp) - /* SP */ - sw $30, (30 * 4)(sp) - sw $31, (31 * 4)(sp) - - /* STATUS CAUSE EPC.... */ - mfc0 $2, CP0_STATUS - sw $2, STK_OFFSET_SR(sp) - - mfc0 $2, CP0_CAUSE - sw $2, STK_OFFSET_CAUSE(sp) - - mfc0 $2, CP0_BADVADDR - sw $2, STK_OFFSET_BADVADDR(sp) - - MFC0 $2, CP0_EPC - sw $2, STK_OFFSET_EPC(sp) - - mfhi $2 - sw $2, STK_OFFSET_HI(sp) - - mflo $2 - sw $2, STK_OFFSET_LO(sp) -#ifdef __mips_hard_float - add a0, sp,STK_CTX_SIZE - - mfc0 t0, CP0_STATUS - .set push - .set at - or t0, M_StatusCU1 - .set push - mtc0 t0, CP0_STATUS - - cfc1 t0, CP1_STATUS - sw t0 , 0x00(a0) - swc1 $f0,(0x04 * 1)(a0) - swc1 $f1,(0x04 * 2)(a0) - swc1 $f2,(0x04 * 3)(a0) - swc1 $f3,(0x04 * 4)(a0) - swc1 $f4,(0x04 * 5)(a0) - swc1 $f5,(0x04 * 6)(a0) - swc1 $f6,(0x04 * 7)(a0) - swc1 $f7,(0x04 * 8)(a0) - swc1 $f8,(0x04 * 9)(a0) - swc1 $f9,(0x04 * 10)(a0) - swc1 $f10,(0x04 * 11)(a0) - swc1 $f11,(0x04 * 12)(a0) - swc1 $f12,(0x04 * 13)(a0) - swc1 $f13,(0x04 * 14)(a0) - swc1 $f14,(0x04 * 15)(a0) - swc1 $f15,(0x04 * 16)(a0) - swc1 $f16,(0x04 * 17)(a0) - swc1 $f17,(0x04 * 18)(a0) - swc1 $f18,(0x04 * 19)(a0) - swc1 $f19,(0x04 * 20)(a0) - swc1 $f20,(0x04 * 21)(a0) - swc1 $f21,(0x04 * 22)(a0) - swc1 $f22,(0x04 * 23)(a0) - swc1 $f23,(0x04 * 24)(a0) - swc1 $f24,(0x04 * 25)(a0) - swc1 $f25,(0x04 * 26)(a0) - swc1 $f26,(0x04 * 27)(a0) - swc1 $f27,(0x04 * 28)(a0) - swc1 $f28,(0x04 * 29)(a0) - swc1 $f29,(0x04 * 30)(a0) - swc1 $f30,(0x04 * 31)(a0) - swc1 $f31,(0x04 * 32)(a0) - - nop -#endif - - //restore a0 - lw a0, (REG_A0 * 4)(sp) - - .set pop -.endm - - -.macro RESTORE_CONTEXT - .set push - .set noat - .set noreorder - .set volatile - -#ifdef __mips_hard_float - add a0, sp,STK_CTX_SIZE - - mfc0 t0, CP0_STATUS - .set push - .set at - or t0, M_StatusCU1 - .set noat - mtc0 t0, CP0_STATUS - - lw t0 , 0x00(a0) - lwc1 $f0,(0x04 * 1)(a0) - lwc1 $f1,(0x04 * 2)(a0) - lwc1 $f2,(0x04 * 3)(a0) - lwc1 $f3,(0x04 * 4)(a0) - lwc1 $f4,(0x04 * 5)(a0) - lwc1 $f5,(0x04 * 6)(a0) - lwc1 $f6,(0x04 * 7)(a0) - lwc1 $f7,(0x04 * 8)(a0) - lwc1 $f8,(0x04 * 9)(a0) - lwc1 $f9,(0x04 * 10)(a0) - lwc1 $f10,(0x04 * 11)(a0) - lwc1 $f11,(0x04 * 12)(a0) - lwc1 $f12,(0x04 * 13)(a0) - lwc1 $f13,(0x04 * 14)(a0) - lwc1 $f14,(0x04 * 15)(a0) - lwc1 $f15,(0x04 * 16)(a0) - lwc1 $f16,(0x04 * 17)(a0) - lwc1 $f17,(0x04 * 18)(a0) - lwc1 $f18,(0x04 * 19)(a0) - lwc1 $f19,(0x04 * 20)(a0) - lwc1 $f20,(0x04 * 21)(a0) - lwc1 $f21,(0x04 * 22)(a0) - lwc1 $f22,(0x04 * 23)(a0) - lwc1 $f23,(0x04 * 24)(a0) - lwc1 $f24,(0x04 * 25)(a0) - lwc1 $f25,(0x04 * 26)(a0) - lwc1 $f26,(0x04 * 27)(a0) - lwc1 $f27,(0x04 * 28)(a0) - lwc1 $f28,(0x04 * 29)(a0) - lwc1 $f29,(0x04 * 30)(a0) - lwc1 $f30,(0x04 * 31)(a0) - lwc1 $f31,(0x04 * 32)(a0) - ctc1 t0, CP1_STATUS ;/* restore fpp status reg */ - - nop -#endif - - /* ͨ�üĴ��� */ - /* ZERO */ - lw $1, ( 1 * 4)(sp) - /* V0 */ - lw $3, ( 3 * 4)(sp) - lw $4, ( 4 * 4)(sp) - lw $5, ( 5 * 4)(sp) - lw $6, ( 6 * 4)(sp) - lw $7, ( 7 * 4)(sp) - lw $8, ( 8 * 4)(sp) - lw $9, ( 9 * 4)(sp) - lw $10, (10 * 4)(sp) - lw $11, (11 * 4)(sp) - lw $12, (12 * 4)(sp) - lw $13, (13 * 4)(sp) - lw $14, (14 * 4)(sp) - lw $15, (15 * 4)(sp) - lw $16, (16 * 4)(sp) - lw $17, (17 * 4)(sp) - lw $18, (18 * 4)(sp) - lw $19, (19 * 4)(sp) - lw $20, (20 * 4)(sp) - lw $21, (21 * 4)(sp) - lw $22, (22 * 4)(sp) - lw $23, (23 * 4)(sp) - lw $24, (24 * 4)(sp) - lw $25, (25 * 4)(sp) - lw $26, (26 * 4)(sp) - lw $27, (27 * 4)(sp) - lw $28, (28 * 4)(sp) - /* SP */ - lw $30, (30 * 4)(sp) - lw $31, (31 * 4)(sp) - - - /* STATUS CAUSE EPC.... */ - lw $2, STK_OFFSET_HI(sp) - mthi $2 - lw $2, STK_OFFSET_LO(sp) - mtlo $2 - - lw $2, STK_OFFSET_SR(sp) - mtc0 $2, CP0_STATUS - - lw $2, STK_OFFSET_BADVADDR(sp) - mtc0 $2, CP0_BADVADDR - - lw $2, STK_OFFSET_CAUSE(sp) - mtc0 $2, CP0_CAUSE - - lw $2, STK_OFFSET_EPC(sp) - MTC0 $2, CP0_EPC - - //restore $2 - lw $2, ( 2 * 4)(sp) - //restore sp - lw $29, (29 * 4)(sp) - - eret - nop - .set pop -.endm -#endif -#endif /* _MIPS_CONTEXT_ASM_H_ */ diff --git a/libcpu/mips/common/mips_def.h b/libcpu/mips/common/mips_def.h deleted file mode 100644 index 70da2deccf..0000000000 --- a/libcpu/mips/common/mips_def.h +++ /dev/null @@ -1,2310 +0,0 @@ -/* - * File : mips_def.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��7�� Urey the first version - */ - -#ifndef _COMMON_MIPS_DEF_H_ -#define _COMMON_MIPS_DEF_H_ - - -/* - ************************************************************************ - * I N S T R U C T I O N F O R M A T S * - ************************************************************************ - * - * The following definitions describe each field in an instruction. There - * is one diagram for each type of instruction, with field definitions - * following the diagram for that instruction. Note that if a field of - * the same name and position is defined in an earlier diagram, it is - * not defined again in the subsequent diagram. Only new fields are - * defined for each diagram. - * - * R-Type (operate) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | | rs | rt | rd | sa | | - * | Opcode | | | Tcode | func | - * | | Bcode | | sel | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define S_InstnOpcode 26 -#define M_InstnOpcode (0x3f << S_InstnOpcode) -#define S_InstnRS 21 -#define M_InstnRS (0x1f << S_InstnRS) -#define S_InstnRT 16 -#define M_InstnRT (0x1f << S_InstnRT) -#define S_InstnRD 11 -#define M_InstnRD (0x1f << S_InstnRD) -#define S_InstnSA 6 -#define M_InstnSA (0x1f << S_InstnSA) -#define S_InstnTcode 6 -#define M_InstnTcode (0x3ff << S_InstnTcode) -#define S_InstnBcode 6 -#define M_InstnBcode (0xfffff << S_InstnBcode) -#define S_InstnFunc 0 -#define M_InstnFunc (0x3f << S_InstnFunc) -#define S_InstnSel 0 -#define M_InstnSel (0x7 << S_InstnSel) - -/* - * I-Type (load, store, branch, immediate) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | rs | rt | Offset | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define S_InstnOffset 0 -#define M_InstnOffset (0xffff << S_InstnOffset) - -/* - * I-Type (pref) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | rs | hint | Offset | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define S_InstnHint S_InstnRT -#define M_InstnHint M_InstnRT - -/* - * J-Type (jump) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | JIndex | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define S_InstnJIndex 0 -#define M_InstnJIndex (0x03ffffff << S_InstnJIndex) - -/* - * FP R-Type (operate) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | fmt | ft | fs | fd | func | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define S_InstnFmt S_InstnRS -#define M_InstnFmt M_InstnRS -#define S_InstnFT S_InstnRT -#define M_InstnFT M_InstnRT -#define S_InstnFS S_InstnRD -#define M_InstnFS M_InstnRD -#define S_InstnFD S_InstnSA -#define M_InstnFD M_InstnSA - -/* - * FP R-Type (cpu <-> cpu data movement)) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | sub | rt | fs | 0 | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define S_InstnSub S_InstnRS -#define M_InstnSub M_InstnRS - -/* - * FP R-Type (compare) - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | | | | | | |C| | - * | Opcode | fmt | ft | fs | cc |0|A| func | - * | | | | | | |B| | - * | | | | | | |S| | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define S_InstnCCcmp 8 -#define M_InstnCCcmp (0x7 << S_InstnCCcmp) -#define S_InstnCABS 6 -#define M_InstnCABS (0x1 << S_InstnCABS) - -/* - * FP R-Type (FPR conditional move on FP cc) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | fmt | cc |n|t| fs | fd | func | - * | | | |d|f| | | | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define S_InstnCC 18 -#define M_InstnCC (0x7 << S_InstnCC) -#define S_InstnND 17 -#define M_InstnND (0x1 << S_InstnND) -#define S_InstnTF 16 -#define M_InstnTF (0x1 << S_InstnTF) - -/* - * FP R-Type (3-operand operate) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | fr | ft | fs | fd | op4 | fmt3| - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define S_InstnFR S_InstnRS -#define M_InstnFR M_InstnRS -#define S_InstnOp4 3 -#define M_InstnOp4 (0x7 << S_InstnOp4) -#define S_InstnFmt3 0 -#define M_InstnFmt3 (0x7 << S_InstnFmt3) - -/* - * FP R-Type (Indexed load, store) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | rs | rt | 0 | fd | func | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ -/* - * FP R-Type (prefx) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | rs | rt | hint | 0 | func | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define S_InstnHintX S_InstnRD -#define M_InstnHintX M_InstnRD - -/* - * FP R-Type (GPR conditional move on FP cc) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | rs | cc |n|t| rd | 0 | func | - * | | | |d|f| | | | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -/* - * FP I-Type (load, store) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | rs | ft | Offset | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -/* - * FP I-Type (branch) - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Opcode | fmt | cc |n|t| Offset | - * | | | |d|f| | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - - -/* - ************************************************************************* - * V I R T U A L A D D R E S S D E F I N I T I O N S * - ************************************************************************* - */ - -#ifdef MIPSADDR64 -#define A_K0BASE UNS64Const(0xffffffff80000000) -#define A_K1BASE UNS64Const(0xffffffffa0000000) -#define A_K2BASE UNS64Const(0xffffffffc0000000) -#define A_K3BASE UNS64Const(0xffffffffe0000000) -#define A_REGION UNS64Const(0xc000000000000000) -#define A_XKPHYS_ATTR UNS64Const(0x3800000000000000) -#else -#define A_K0BASE 0x80000000 -#define A_K1BASE 0xa0000000 -#define A_K2BASE 0xc0000000 -#define A_K3BASE 0xe0000000 -#endif -#define M_KMAPPED 0x40000000 /* KnSEG address is mapped if bit is one */ - - -#ifdef MIPS_Model64 - -#define S_VMAP64 62 -#define M_VMAP64 UNS64Const(0xc000000000000000) - -#define K_VMode11 3 -#define K_VMode10 2 -#define K_VMode01 1 -#define K_VMode00 0 - -#define S_KSEG3 29 -#define M_KSEG3 (0x7 << S_KSEG3) -#define K_KSEG3 7 - -#define S_SSEG 29 -#define M_SSEG (0x7 << S_KSEG3) -#define K_SSEG 6 - -#define S_KSSEG 29 -#define M_KSSEG (0x7 << S_KSEG3) -#define K_KSSEG 6 - -#define S_KSEG1 29 -#define M_KSEG1 (0x7 << S_KSEG3) -#define K_KSEG1 5 - -#define S_KSEG0 29 -#define M_KSEG0 (0x7 << S_KSEG3) -#define K_KSEG0 4 - -#define S_XKSEG 29 -#define M_XKSEG (0x7 << S_KSEG3) -#define K_XKSEG 3 - -#define S_USEG 31 -#define M_USEG (0x1 << S_USEG) -#define K_USEG 0 - -#define S_EjtagProbeMem 20 -#define M_EjtagProbeMem (0x1 << S_EjtagProbeMem) -#define K_EjtagProbeMem 0 - - - -#else - -#define S_KSEG3 29 -#define M_KSEG3 (0x7 << S_KSEG3) -#define K_KSEG3 7 - -#define S_KSSEG 29 -#define M_KSSEG (0x7 << S_KSSEG) -#define K_KSSEG 6 - -#define S_SSEG 29 -#define M_SSEG (0x7 << S_SSEG) -#define K_SSEG 6 - -#define S_KSEG1 29 -#define M_KSEG1 (0x7 << S_KSEG1) -#define K_KSEG1 5 - -#define S_KSEG0 29 -#define M_KSEG0 (0x7 << S_KSEG0) -#define K_KSEG0 4 - -#define S_KUSEG 31 -#define M_KUSEG (0x1 << S_KUSEG) -#define K_KUSEG 0 - -#define S_SUSEG 31 -#define M_SUSEG (0x1 << S_SUSEG) -#define K_SUSEG 0 - -#define S_USEG 31 -#define M_USEG (0x1 << S_USEG) -#define K_USEG 0 - -#define K_EjtagLower 0xff200000 -#define K_EjtagUpper 0xff3fffff - -#define S_EjtagProbeMem 20 -#define M_EjtagProbeMem (0x1 << S_EjtagProbeMem) -#define K_EjtagProbeMem 0 - -#endif - - - -/* - ************************************************************************* - * C A C H E I N S T R U C T I O N O P E R A T I O N C O D E S * - ************************************************************************* - */ - -/* - * Cache encodings - */ -#define K_CachePriI 0 /* Primary Icache */ -#define K_CachePriD 1 /* Primary Dcache */ -#define K_CachePriU 1 /* Unified primary */ -#define K_CacheTerU 2 /* Unified Tertiary */ -#define K_CacheSecU 3 /* Unified secondary */ - - -/* - * Function encodings - */ -#define S_CacheFunc 2 /* Amount to shift function encoding within 5-bit field */ -#define K_CacheIndexInv 0 /* Index invalidate */ -#define K_CacheIndexWBInv 0 /* Index writeback invalidate */ -#define K_CacheIndexLdTag 1 /* Index load tag */ -#define K_CacheIndexStTag 2 /* Index store tag */ -#define K_CacheHitInv 4 /* Hit Invalidate */ -#define K_CacheFill 5 /* Fill (Icache only) */ -#define K_CacheHitWBInv 5 /* Hit writeback invalidate */ -#define K_CacheHitWB 6 /* Hit writeback */ -#define K_CacheFetchLock 7 /* Fetch and lock */ - -#define ICIndexInv ((K_CacheIndexInv << S_CacheFunc) | K_CachePriI) -#define DCIndexWBInv ((K_CacheIndexWBInv << S_CacheFunc) | K_CachePriD) -#define DCIndexInv DCIndexWBInv -#define ICIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriI) -#define DCIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriD) -#define ICIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriI) -#define DCIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriD) -#define ICHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriI) -#define DCHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriD) -#define ICFill ((K_CacheFill << S_CacheFunc) | K_CachePriI) -#define DCHitWBInv ((K_CacheHitWBInv << S_CacheFunc) | K_CachePriD) -#define DCHitWB ((K_CacheHitWB << S_CacheFunc) | K_CachePriD) -#define ICFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriI) -#define DCFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriD) - - -/* - ************************************************************************* - * P R E F E T C H I N S T R U C T I O N H I N T S * - ************************************************************************* - */ - -#define PrefLoad 0 -#define PrefStore 1 -#define PrefLoadStreamed 4 -#define PrefStoreStreamed 5 -#define PrefLoadRetained 6 -#define PrefStoreRetained 7 -#define PrefWBInval 25 -#define PrefNudge 25 - - -/* - ************************************************************************* - * C P U R E G I S T E R D E F I N I T I O N S * - ************************************************************************* - */ - - -/* - ************************************************************************* - * S O F T W A R E G P R N A M E S * - ************************************************************************* - */ -#ifdef __ASSEMBLY__ -#define zero $0 -#define AT $1 -#define v0 $2 -#define v1 $3 -#define a0 $4 -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 -#define s0 $16 -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 -#define t9 $25 -#define k0 $26 -#define k1 $27 -#define gp $28 -#define sp $29 -#define fp $30 -#define ra $31 - -/* - * The following registers are used by the AVP environment and - * are not part of the normal software definitions. - */ - -#ifdef MIPSAVPENV -#define repc $25 /* Expected exception PC */ -#define tid $30 /* Current test case address */ -#endif - - -/* - ************************************************************************* - * H A R D W A R E G P R N A M E S * - ************************************************************************* - * - * In the AVP environment, several of the `r' names are removed from the - * name space because they are used by the kernel for special purposes. - * Removing them causes assembly rather than runtime errors for tests that - * use the `r' names. - * - * - r25 (repc) is used as the expected PC on an exception - * - r26-r27 (k0, k1) are used in the exception handler - * - r30 (tid) is used as the current test address - */ - -#define r0 $0 -#define r1 $1 -#define r2 $2 -#define r3 $3 -#define r4 $4 -#define r5 $5 -#define r6 $6 -#define r7 $7 -#define r8 $8 -#define r9 $9 -#define r10 $10 -#define r11 $11 -#define r12 $12 -#define r13 $13 -#define r14 $14 -#define r15 $15 -#define r16 $16 -#define r17 $17 -#define r18 $18 -#define r19 $19 -#define r20 $20 -#define r21 $21 -#define r22 $22 -#define r23 $23 -#define r24 $24 -#ifdef MIPSAVPENV -#define r25 r25_unknown -#define r26 r26_unknown -#define r27 r27_unknown -#else -#define r25 $25 -#define r26 $26 -#define r27 $27 -#endif -#define r28 $28 -#define r29 $29 -#ifdef MIPSAVPENV -#define r30 r30_unknown -#else -#define r30 $30 -#endif -#define r31 $31 - -#endif - -/* - ************************************************************************* - * H A R D W A R E G P R I N D I C E S * - ************************************************************************* - * - * These definitions provide the index (number) of the GPR, as opposed - * to the assembler register name ($n). - */ - -#define R_r0 0 -#define R_r1 1 -#define R_r2 2 -#define R_r3 3 -#define R_r4 4 -#define R_r5 5 -#define R_r6 6 -#define R_r7 7 -#define R_r8 8 -#define R_r9 9 -#define R_r10 10 -#define R_r11 11 -#define R_r12 12 -#define R_r13 13 -#define R_r14 14 -#define R_r15 15 -#define R_r16 16 -#define R_r17 17 -#define R_r18 18 -#define R_r19 19 -#define R_r20 20 -#define R_r21 21 -#define R_r22 22 -#define R_r23 23 -#define R_r24 24 -#define R_r25 25 -#define R_r26 26 -#define R_r27 27 -#define R_r28 28 -#define R_r29 29 -#define R_r30 30 -#define R_r31 31 -#define R_hi 32 /* Hi register */ -#define R_lo 33 /* Lo register */ - - -/* - ************************************************************************* - * S O F T W A R E G P R M A S K S * - ************************************************************************* - * - * These definitions provide the bit mask corresponding to the GPR number - */ - -#define M_AT (1<<1) -#define M_v0 (1<<2) -#define M_v1 (1<<3) -#define M_a0 (1<<4) -#define M_a1 (1<<5) -#define M_a2 (1<<6) -#define M_a3 (1<<7) -#define M_t0 (1<<8) -#define M_t1 (1<<9) -#define M_t2 (1<<10) -#define M_t3 (1<<11) -#define M_t4 (1<<12) -#define M_t5 (1<<13) -#define M_t6 (1<<14) -#define M_t7 (1<<15) -#define M_s0 (1<<16) -#define M_s1 (1<<17) -#define M_s2 (1<<18) -#define M_s3 (1<<19) -#define M_s4 (1<<20) -#define M_s5 (1<<21) -#define M_s6 (1<<22) -#define M_s7 (1<<23) -#define M_t8 (1<<24) -#define M_t9 (1<<25) -#define M_k0 (1<<26) -#define M_k1 (1<<27) -#define M_gp (1<<28) -#define M_sp (1<<29) -#define M_fp (1<<30) -#define M_ra (1<<31) - - -/* - ************************************************************************* - * C P 0 R E G I S T E R D E F I N I T I O N S * - ************************************************************************* - * Each register has the following definitions: - * - * C0_rrr The register number (as a $n value) - * R_C0_rrr The register index (as an integer corresponding - * to the register number) - * - * Each field in a register has the following definitions: - * - * S_rrrfff The shift count required to right-justify - * the field. This corresponds to the bit - * number of the right-most bit in the field. - * M_rrrfff The Mask required to isolate the field. - * - * Register diagrams included below as comments correspond to the - * MIPS32 and MIPS64 architecture specifications. Refer to other - * sources for register diagrams for older architectures. - */ - - -/* - ************************************************************************ - * I N D E X R E G I S T E R ( 0 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |P| 0 | Index | Index - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Index $0 -#define R_C0_Index 0 -#define C0_INX C0_Index /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_IndexP 31 /* Probe failure (R)*/ -#define M_IndexP (0x1 << S_IndexP) - -#define S_IndexIndex 0 /* TLB index (R/W)*/ -#define M_IndexIndex (0x3f << S_IndexIndex) - -#define M_Index0Fields 0x7fffffc0 -#define M_IndexRFields 0x80000000 - - -/* - ************************************************************************ - * R A N D O M R E G I S T E R ( 1 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | 0 | Index | Random - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Random $1 -#define R_C0_Random 1 -#define C0_RAND $1 /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_RandomIndex 0 /* TLB random index (R)*/ -#define M_RandomIndex (0x3f << S_RandomIndex) - -#define M_Random0Fields 0xffffffc0 -#define M_RandomRFields 0x0000003f - - -/* - ************************************************************************ - * E N T R Y L O 0 R E G I S T E R ( 2 ) * - ************************************************************************ - * - * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Fill (0) //| 0 | PFN | C |D|V|G| EntryLo0 - * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_EntryLo0 $2 -#define R_C0_EntryLo0 2 -#define C0_TLBLO_0 C0_EntryLo0 /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_EntryLoPFN 6 /* PFN (R/W) */ -#define M_EntryLoPFN (0xffffff << S_EntryLoPFN) -#define S_EntryLoC 3 /* Coherency attribute (R/W) */ -#define M_EntryLoC (0x7 << S_EntryLoC) -#define S_EntryLoD 2 /* Dirty (R/W) */ -#define M_EntryLoD (0x1 << S_EntryLoD) -#define S_EntryLoV 1 /* Valid (R/W) */ -#define M_EntryLoV (0x1 << S_EntryLoV) -#define S_EntryLoG 0 /* Global (R/W) */ -#define M_EntryLoG (0x1 << S_EntryLoG) -#define M_EntryLoOddPFN (0x1 << S_EntryLoPFN) /* Odd PFN bit */ -#define S_EntryLo_RS K_PageAlign /* Right-justify PFN */ -#define S_EntryLo_LS S_EntryLoPFN /* Position PFN to appropriate position */ - -#define M_EntryLo0Fields 0x00000000 -#define M_EntryLoRFields 0xc0000000 -#define M_EntryLo0Fields64 UNS64Const(0x0000000000000000) -#define M_EntryLoRFields64 UNS64Const(0xffffffffc0000000) - -/* - * Cache attribute values in the C field of EntryLo and the - * K0 field of Config - */ -#define K_CacheAttrCWTnWA 0 /* Cacheable, write-thru, no write allocate */ -#define K_CacheAttrCWTWA 1 /* Cacheable, write-thru, write allocate */ -#define K_CacheAttrU 2 /* Uncached */ -#define K_CacheAttrC 3 /* Cacheable */ -#define K_CacheAttrCN 3 /* Cacheable, non-coherent */ -#define K_CacheAttrCCE 4 /* Cacheable, coherent, exclusive */ -#define K_CacheAttrCCS 5 /* Cacheable, coherent, shared */ -#define K_CacheAttrCCU 6 /* Cacheable, coherent, update */ -#define K_CacheAttrUA 7 /* Uncached accelerated */ - - -/* - ************************************************************************ - * E N T R Y L O 1 R E G I S T E R ( 3 ) * - ************************************************************************ - * - * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Fill (0) //| 0 | PFN | C |D|V|G| EntryLo1 - * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_EntryLo1 $3 -#define R_C0_EntryLo1 3 -#define C0_TLBLO_1 C0_EntryLo1 /* OBSOLETE - DO NOT USE IN NEW CODE */ - -/* - * Field definitions are as given for EntryLo0 above - */ - - -/* - ************************************************************************ - * C O N T E X T R E G I S T E R ( 4 ) * - ************************************************************************ - * - * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | // PTEBase | BadVPN<31:13> | 0 | Context - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Context $4 -#define R_C0_Context 4 -#define C0_CTXT C0_Context /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_ContextPTEBase 23 /* PTE base (R/W) */ -#define M_ContextPTEBase (0x1ff << S_ContextPTEBase) -#define S_ContextBadVPN 4 /* BadVPN2 (R) */ -#define M_ContextBadVPN (0x7ffff << S_ContextBadVPN) -#define S_ContextBadVPN_LS 9 /* Position BadVPN to bit 31 */ -#define S_ContextBadVPN_RS 13 /* Right-justify shifted BadVPN field */ - -#define M_Context0Fields 0x0000000f -#define M_ContextRFields 0x007ffff0 -#define M_Context0Fields64 UNS64Const(0x000000000000000f) -#define M_ContextRFields64 UNS64Const(0x00000000007ffff0) - - -/* - ************************************************************************ - * P A G E M A S K R E G I S T E R ( 5 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | 0 | Mask | 0 | PageMask - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_PageMask $5 -#define R_C0_PageMask 5 /* Mask (R/W) */ -#define C0_PGMASK C0_PageMask /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_PageMaskMask 13 -#define M_PageMaskMask (0xfff << S_PageMaskMask) - -#define M_PageMask0Fields 0xfe001fff -#define M_PageMaskRFields 0x00000000 - -/* - * Values in the Mask field - */ -#define K_PageMask4K 0x000 /* K_PageMasknn values are values for use */ -#define K_PageMask16K 0x003 /* with KReqPageAttributes or KReqPageMask macros */ -#define K_PageMask64K 0x00f -#define K_PageMask256K 0x03f -#define K_PageMask1M 0x0ff -#define K_PageMask4M 0x3ff -#define K_PageMask16M 0xfff - -#define M_PageMask4K (K_PageMask4K << S_PageMaskMask) /* M_PageMasknn values are masks */ -#define M_PageMask16K (K_PageMask16K << S_PageMaskMask) /* in position in the PageMask register */ -#define M_PageMask64K (K_PageMask64K << S_PageMaskMask) -#define M_PageMask256K (K_PageMask256K << S_PageMaskMask) -#define M_PageMask1M (K_PageMask1M << S_PageMaskMask) -#define M_PageMask4M (K_PageMask4M << S_PageMaskMask) -#define M_PageMask16M (K_PageMask16M << S_PageMaskMask) - - -/* - ************************************************************************ - * W I R E D R E G I S T E R ( 6 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | 0 | Index | Wired - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Wired $6 -#define R_C0_Wired 6 -#define C0_TLBWIRED C0_Wired /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_WiredIndex 0 /* TLB wired boundary (R/W) */ -#define M_WiredIndex (0x3f << S_WiredIndex) - -#define M_Wired0Fields 0xffffffc0 -#define M_WiredRFields 0x00000000 - - -/* - ************************************************************************ - * B A D V A D D R R E G I S T E R ( 8 ) * - ************************************************************************ - * - * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | // Bad Virtual Address | BadVAddr - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_BadVAddr $8 -#define R_C0_BadVAddr 8 -#define C0_BADVADDR C0_BadVAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define M_BadVAddrOddPage K_PageSize /* Even/Odd VA bit for pair of PAs */ - -#define M_BadVAddr0Fields 0x00000000 -#define M_BadVAddrRFields 0xffffffff -#define M_BadVAddr0Fields64 UNS64Const(0x0000000000000000) -#define M_BadVAddrRFields64 UNS64Const(0xffffffffffffffff) - -/* - ************************************************************************ - * C O U N T R E G I S T E R ( 9 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Count Value | Count - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Count $9 -#define R_C0_Count 9 -#define C0_COUNT C0_Count /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define M_Count0Fields 0x00000000 -#define M_CountRFields 0x00000000 - - -/* - ************************************************************************ - * E N T R Y H I R E G I S T E R ( 1 0 ) * - ************************************************************************ - * - * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | R | Fill // VPN2 | 0 | ASID | EntryHi - * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_EntryHi $10 -#define R_C0_EntryHi 10 -#define C0_TLBHI C0_EntryHi /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_EntryHiR64 62 /* Region (R/W) */ -#define M_EntryHiR64 UNS64Const(0xc000000000000000) -#define S_EntryHiVPN2 13 /* VPN/2 (R/W) */ -#define M_EntryHiVPN2 (0x7ffff << S_EntryHiVPN2) -#define M_EntryHiVPN264 UNS64Const(0x000000ffffffe000) -#define S_EntryHiASID 0 /* ASID (R/W) */ -#define M_EntryHiASID (0xff << S_EntryHiASID) -#define S_EntryHiVPN_Shf S_EntryHiVPN2 - -#define M_EntryHi0Fields 0x00001f00 -#define M_EntryHiRFields 0x00000000 -#define M_EntryHi0Fields64 UNS64Const(0x0000000000001f00) -#define M_EntryHiRFields64 UNS64Const(0x3fffff0000000000) - - -/* - ************************************************************************ - * C O M P A R E R E G I S T E R ( 1 1 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Compare Value | Compare - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Compare $11 -#define R_C0_Compare 11 -#define C0_COMPARE C0_Compare /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define M_Compare0Fields 0x00000000 -#define M_CompareRFields 0x00000000 - - -/* - ************************************************************************ - * S T A T U S R E G I S T E R ( 1 2 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |C|C|C|C|R|F|R|M|P|B|T|S|M| | R |I|I|I|I|I|I|I|I|K|S|U|U|R|E|E|I| - * |U|U|U|U|P|R|E|X|X|E|S|R|M| | s |M|M|M|M|M|M|M|M|X|X|X|M|s|R|X|E| Status - * |3|2|1|0| | | | | |V| | |I| | v |7|6|5|4|3|2|1|0| | | | |v|L|L| | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Status $12 -#define R_C0_Status 12 -#define C0_SR C0_Status /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_StatusCU 28 /* Coprocessor enable (R/W) */ -#define M_StatusCU (0xf << S_StatusCU) -#define S_StatusCU3 31 -#define M_StatusCU3 (0x1 << S_StatusCU3) -#define S_StatusCU2 30 -#define M_StatusCU2 (0x1 << S_StatusCU2) -#define S_StatusCU1 29 -#define M_StatusCU1 (0x1 << S_StatusCU1) -#define S_StatusCU0 28 -#define M_StatusCU0 (0x1 << S_StatusCU0) -#define S_StatusRP 27 /* Enable reduced power mode (R/W) */ -#define M_StatusRP (0x1 << S_StatusRP) -#define S_StatusFR 26 /* Enable 64-bit FPRs (MIPS64 only) (R/W) */ -#define M_StatusFR (0x1 << S_StatusFR) -#define S_StatusRE 25 /* Enable reverse endian (R/W) */ -#define M_StatusRE (0x1 << S_StatusRE) -#define S_StatusMX 24 /* Enable access to MDMX resources (MIPS64 only) (R/W) */ -#define M_StatusMX (0x1 << S_StatusMX) -#define S_StatusPX 23 /* Enable access to 64-bit instructions/data (MIPS64 only) (R/W) */ -#define M_StatusPX (0x1 << S_StatusPX) -#define S_StatusBEV 22 /* Enable Boot Exception Vectors (R/W) */ -#define M_StatusBEV (0x1 << S_StatusBEV) -#define S_StatusTS 21 /* Denote TLB shutdown (R/W) */ -#define M_StatusTS (0x1 << S_StatusTS) -#define S_StatusSR 20 /* Denote soft reset (R/W) */ -#define M_StatusSR (0x1 << S_StatusSR) -#define S_StatusNMI 19 -#define M_StatusNMI (0x1 << S_StatusNMI) /* Denote NMI (R/W) */ -#define S_StatusIM 8 /* Interrupt mask (R/W) */ -#define M_StatusIM (0xff << S_StatusIM) -#define S_StatusIM7 15 -#define M_StatusIM7 (0x1 << S_StatusIM7) -#define S_StatusIM6 14 -#define M_StatusIM6 (0x1 << S_StatusIM6) -#define S_StatusIM5 13 -#define M_StatusIM5 (0x1 << S_StatusIM5) -#define S_StatusIM4 12 -#define M_StatusIM4 (0x1 << S_StatusIM4) -#define S_StatusIM3 11 -#define M_StatusIM3 (0x1 << S_StatusIM3) -#define S_StatusIM2 10 -#define M_StatusIM2 (0x1 << S_StatusIM2) -#define S_StatusIM1 9 -#define M_StatusIM1 (0x1 << S_StatusIM1) -#define S_StatusIM0 8 -#define M_StatusIM0 (0x1 << S_StatusIM0) -#define S_StatusKX 7 /* Enable access to extended kernel addresses (MIPS64 only) (R/W) */ -#define M_StatusKX (0x1 << S_StatusKX) -#define S_StatusSX 6 /* Enable access to extended supervisor addresses (MIPS64 only) (R/W) */ -#define M_StatusSX (0x1 << S_StatusSX) -#define S_StatusUX 5 /* Enable access to extended user addresses (MIPS64 only) (R/W) */ -#define M_StatusUX (0x1 << S_StatusUX) -#define S_StatusKSU 3 /* Two-bit current mode (R/W) */ -#define M_StatusKSU (0x3 << S_StatusKSU) -#define S_StatusUM 4 /* User mode if supervisor mode not implemented (R/W) */ -#define M_StatusUM (0x1 << S_StatusUM) -#define S_StatusSM 3 /* Supervisor mode (R/W) */ -#define M_StatusSM (0x1 << S_StatusSM) -#define S_StatusERL 2 /* Denotes error level (R/W) */ -#define M_StatusERL (0x1 << S_StatusERL) -#define S_StatusEXL 1 /* Denotes exception level (R/W) */ -#define M_StatusEXL (0x1 << S_StatusEXL) -#define S_StatusIE 0 /* Enables interrupts (R/W) */ -#define M_StatusIE (0x1 << S_StatusIE) - -#define M_Status0Fields 0x00040000 -#define M_StatusRFields 0x058000e0 /* FR, MX, PX, KX, SX, UX unused in MIPS32 */ -#define M_Status0Fields64 0x00040000 -#define M_StatusRFields64 0x00000000 - -/* - * Values in the KSU field - */ -#define K_StatusKSU_U 2 /* User mode in KSU field */ -#define K_StatusKSU_S 1 /* Supervisor mode in KSU field */ -#define K_StatusKSU_K 0 /* Kernel mode in KSU field */ - - -/* - ************************************************************************ - * C A U S E R E G I S T E R ( 1 3 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |B| | C | |I|W| |I|I|I|I|I|I|I|I| | | R | - * |D| | E | Rsvd |V|P| Rsvd |P|P|P|P|P|P|P|P| | ExcCode | s | Cause - * | | | | | | | |7|6|5|4|3|2|1|0| | | v | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Cause $13 -#define R_C0_Cause 13 -#define C0_CAUSE C0_Cause /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_CauseBD 31 -#define M_CauseBD (0x1 << S_CauseBD) -#define S_CauseCE 28 -#define M_CauseCE (0x3<< S_CauseCE) -#define S_CauseIV 23 -#define M_CauseIV (0x1 << S_CauseIV) -#define S_CauseWP 22 -#define M_CauseWP (0x1 << S_CauseWP) -#define S_CauseIP 8 -#define M_CauseIP (0xff << S_CauseIP) -#define S_CauseIPEXT 10 -#define M_CauseIPEXT (0x3f << S_CauseIPEXT) -#define S_CauseIP7 15 -#define M_CauseIP7 (0x1 << S_CauseIP7) -#define S_CauseIP6 14 -#define M_CauseIP6 (0x1 << S_CauseIP6) -#define S_CauseIP5 13 -#define M_CauseIP5 (0x1 << S_CauseIP5) -#define S_CauseIP4 12 -#define M_CauseIP4 (0x1 << S_CauseIP4) -#define S_CauseIP3 11 -#define M_CauseIP3 (0x1 << S_CauseIP3) -#define S_CauseIP2 10 -#define M_CauseIP2 (0x1 << S_CauseIP2) -#define S_CauseIP1 9 -#define M_CauseIP1 (0x1 << S_CauseIP1) -#define S_CauseIP0 8 -#define M_CauseIP0 (0x1 << S_CauseIP0) -#define S_CauseExcCode 2 -#define M_CauseExcCode (0x1f << S_CauseExcCode) - -#define M_Cause0Fields 0x4f3f0083 -#define M_CauseRFields 0xb000fc7c - -/* - * Values in the CE field - */ -#define K_CauseCE0 0 /* Coprocessor 0 in the CE field */ -#define K_CauseCE1 1 /* Coprocessor 1 in the CE field */ -#define K_CauseCE2 2 /* Coprocessor 2 in the CE field */ -#define K_CauseCE3 3 /* Coprocessor 3 in the CE field */ - -/* - * Values in the ExcCode field - */ -#define EX_INT 0 /* Interrupt */ -#define EXC_INT (EX_INT << S_CauseExcCode) -#define EX_MOD 1 /* TLB modified */ -#define EXC_MOD (EX_MOD << S_CauseExcCode) -#define EX_TLBL 2 /* TLB exception (load or ifetch) */ -#define EXC_TLBL (EX_TLBL << S_CauseExcCode) -#define EX_TLBS 3 /* TLB exception (store) */ -#define EXC_TLBS (EX_TLBS << S_CauseExcCode) -#define EX_ADEL 4 /* Address error (load or ifetch) */ -#define EXC_ADEL (EX_ADEL << S_CauseExcCode) -#define EX_ADES 5 /* Address error (store) */ -#define EXC_ADES (EX_ADES << S_CauseExcCode) -#define EX_IBE 6 /* Instruction Bus Error */ -#define EXC_IBE (EX_IBE << S_CauseExcCode) -#define EX_DBE 7 /* Data Bus Error */ -#define EXC_DBE (EX_DBE << S_CauseExcCode) -#define EX_SYS 8 /* Syscall */ -#define EXC_SYS (EX_SYS << S_CauseExcCode) -#define EX_SYSCALL EX_SYS -#define EXC_SYSCALL EXC_SYS -#define EX_BP 9 /* Breakpoint */ -#define EXC_BP (EX_BP << S_CauseExcCode) -#define EX_BREAK EX_BP -#define EXC_BREAK EXC_BP -#define EX_RI 10 /* Reserved instruction */ -#define EXC_RI (EX_RI << S_CauseExcCode) -#define EX_CPU 11 /* CoProcessor Unusable */ -#define EXC_CPU (EX_CPU << S_CauseExcCode) -#define EX_OV 12 /* OVerflow */ -#define EXC_OV (EX_OV << S_CauseExcCode) -#define EX_TR 13 /* Trap instruction */ -#define EXC_TR (EX_TR << S_CauseExcCode) -#define EX_TRAP EX_TR -#define EXC_TRAP EXC_TR -#define EX_FPE 15 /* floating point exception */ -#define EXC_FPE (EX_FPE << S_CauseExcCode) -#define EX_C2E 18 /* COP2 exception */ -#define EXC_C2E (EX_C2E << S_CauseExcCode) -#define EX_MDMX 22 /* MDMX exception */ -#define EXC_MDMX (EX_MDMX << S_CauseExcCode) -#define EX_WATCH 23 /* Watch exception */ -#define EXC_WATCH (EX_WATCH << S_CauseExcCode) -#define EX_MCHECK 24 /* Machine check exception */ -#define EXC_MCHECK (EX_MCHECK << S_CauseExcCode) -#define EX_CacheErr 30 /* Cache error caused re-entry to Debug Mode */ -#define EXC_CacheErr (EX_CacheErr << S_CauseExcCode) - - -/* - ************************************************************************ - * E P C R E G I S T E R ( 1 4 ) * - ************************************************************************ - * - * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | // Exception PC | EPC - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_EPC $14 -#define R_C0_EPC 14 - -#define M_EPC0Fields 0x00000000 -#define M_EPCRFields 0x00000000 -#define M_EPC0Fields64 UNS64Const(0x0000000000000000) -#define M_EPCRFields64 UNS64Const(0x0000000000000000) - -/* - ************************************************************************ - * P R I D R E G I S T E R ( 1 5 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Company Opts | Company ID | Procesor ID | Revision | PRId - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_PRId $15 -#define R_C0_PRId 15 -#define C0_PRID C0_PRID /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_PRIdCoOpt 24 /* Company options (R) */ -#define M_PRIdCoOpt (0xff << S_PRIdCoOpt) -#define S_PRIdCoID 16 /* Company ID (R) */ -#define M_PRIdCoID (0xff << S_PRIdCoID) -#define S_PRIdImp 8 /* Implementation ID (R) */ -#define M_PRIdImp (0xff << S_PRIdImp) -#define S_PRIdRev 0 /* Revision (R) */ -#define M_PRIdRev (0xff << S_PRIdRev) - -#define M_PRId0Fields 0x00000000 -#define M_PRIdRFields 0xffffffff -/* - * Values in the Company ID field - */ -#define K_PRIdCoID_MIPS 1 -#define K_PRIdCoID_Broadcom 2 -#define K_PRIdCoID_Alchemy 3 -#define K_PRIdCoID_SiByte 4 -#define K_PRIdCoID_SandCraft 5 -#define K_PRIdCoID_Philips 6 -#define K_PRIdCoID_NextAvailable 7 /* Next available encoding */ - - -/* - * Values in the implementation number field - */ -#define K_PRIdImp_Jade 0x80 -#define K_PRIdImp_Opal 0x81 -#define K_PRIdImp_Ruby 0x82 -#define K_PRIdImp_JadeLite 0x83 -#define K_PRIdImp_4KEc 0x84 /* Emerald with TLB MMU */ -#define K_PRIdImp_4KEmp 0x85 /* Emerald with FM MMU */ -#define K_PRIdImp_4KSc 0x86 /* Coral */ - -#define K_PRIdImp_R3000 0x01 -#define K_PRIdImp_R4000 0x04 -#define K_PRIdImp_R10000 0x09 -#define K_PRIdImp_R4300 0x0b -#define K_PRIdImp_R5000 0x23 -#define K_PRIdImp_R5200 0x28 -#define K_PRIdImp_R5400 0x54 - -/* - ************************************************************************ - * C O N F I G R E G I S T E R ( 1 6 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |M| |B| A | A | | K | Config - * | | Reserved for Implementations|E| T | R | Reserved | 0 | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Config $16 -#define R_C0_Config 16 -#define C0_CONFIG C0_Config /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_ConfigMore 31 /* Additional config registers present (R) */ -#define M_ConfigMore (0x1 << S_ConfigMore) -#define S_ConfigImpl 16 /* Implementation-specific fields */ -#define M_ConfigImpl (0x7fff << S_ConfigImpl) -#define S_ConfigBE 15 /* Denotes big-endian operation (R) */ -#define M_ConfigBE (0x1 << S_ConfigBE) -#define S_ConfigAT 13 /* Architecture type (R) */ -#define M_ConfigAT (0x3 << S_ConfigAT) -#define S_ConfigAR 10 /* Architecture revision (R) */ -#define M_ConfigAR (0x7 << S_ConfigAR) -#define S_ConfigMT 7 /* MMU Type (R) */ -#define M_ConfigMT (0x7 << S_ConfigMT) -#define S_ConfigK0 0 /* Kseg0 coherency algorithm (R/W) */ -#define M_ConfigK0 (0x7 << S_ConfigK0) - -/* - * The following definitions are technically part of the "reserved for - * implementations" field, but are the semi-standard definition used in - * fixed-mapping MMUs to control the cacheability of kuseg and kseg2/3 - * references. For that reason, they are included here, but may be - * overridden by true implementation-specific definitions - */ -#define S_ConfigK23 28 /* Kseg2/3 coherency algorithm (FM MMU only) (R/W) */ -#define M_ConfigK23 (0x7 << S_ConfigK23) -#define S_ConfigKU 25 /* Kuseg coherency algorithm (FM MMU only) (R/W) */ -#define M_ConfigKU (0x7 << S_ConfigKU) - -#define M_Config0Fields 0x00000078 -#define M_ConfigRFields 0x8000ff80 - -/* - * Values in the AT field - */ -#define K_ConfigAT_MIPS32 0 /* MIPS32 */ -#define K_ConfigAT_MIPS64S 1 /* MIPS64 with 32-bit addresses */ -#define K_ConfigAT_MIPS64 2 /* MIPS64 with 32/64-bit addresses */ - -/* - * Values in the MT field - */ -#define K_ConfigMT_NoMMU 0 /* No MMU */ -#define K_ConfigMT_TLBMMU 1 /* Standard TLB MMU */ -#define K_ConfigMT_BATMMU 2 /* Standard BAT MMU */ -#define K_ConfigMT_FMMMU 3 /* Standard Fixed Mapping MMU */ - - -/* - ************************************************************************ - * C O N F I G 1 R E G I S T E R ( 1 6, SELECT 1 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |M| MMU Size | IS | IL | IA | DS | DL | DA |C|M|P|W|C|E|F| Config1 - * | | | | | | | | |2|D|C|R|A|P|P| - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Config1 $16,1 -#define R_C0_Config1 16 - -#define S_Config1More 31 /* Additional Config registers present (R) */ -#define M_Config1More (0x1 << S_Config1More) -#define S_Config1MMUSize 25 /* Number of MMU entries - 1 (R) */ -#define M_Config1MMUSize (0x3f << S_Config1MMUSize) -#define S_Config1IS 22 /* Icache sets per way (R) */ -#define M_Config1IS (0x7 << S_Config1IS) -#define S_Config1IL 19 /* Icache line size (R) */ -#define M_Config1IL (0x7 << S_Config1IL) -#define S_Config1IA 16 /* Icache associativity - 1 (R) */ -#define M_Config1IA (0x7 << S_Config1IA) -#define S_Config1DS 13 /* Dcache sets per way (R) */ -#define M_Config1DS (0x7 << S_Config1DS) -#define S_Config1DL 10 /* Dcache line size (R) */ -#define M_Config1DL (0x7 << S_Config1DL) -#define S_Config1DA 7 /* Dcache associativity (R) */ -#define M_Config1DA (0x7 << S_Config1DA) -#define S_Config1C2 6 /* Coprocessor 2 present (R) */ -#define M_Config1C2 (0x1 << S_Config1C2) -#define S_Config1MD 5 /* Denotes MDMX present (R) */ -#define M_Config1MD (0x1 << S_Config1MD) -#define S_Config1PC 4 /* Denotes performance counters present (R) */ -#define M_Config1PC (0x1 << S_Config1PC) -#define S_Config1WR 3 /* Denotes watch registers present (R) */ -#define M_Config1WR (0x1 << S_Config1WR) -#define S_Config1CA 2 /* Denotes MIPS-16 present (R) */ -#define M_Config1CA (0x1 << S_Config1CA) -#define S_Config1EP 1 /* Denotes EJTAG present (R) */ -#define M_Config1EP (0x1 << S_Config1EP) -#define S_Config1FP 0 /* Denotes floating point present (R) */ -#define M_Config1FP (0x1 << S_Config1FP) - -#define M_Config10Fields 0x00000060 -#define M_Config1RFields 0x7fffff9f - -/* - * The following macro generates a table that is indexed - * by the Icache or Dcache sets field in Config1 and - * contains the decoded value of sets per way - */ -#define Config1CacheSets() \ - HALF(64); \ - HALF(128); \ - HALF(256); \ - HALF(512); \ - HALF(1024); \ - HALF(2048); \ - HALF(4096); \ - HALF(8192); - -/* - * The following macro generates a table that is indexed - * by the Icache or Dcache line size field in Config1 and - * contains the decoded value of the cache line size, in bytes - */ -#define Config1CacheLineSize() \ - HALF(0); \ - HALF(4); \ - HALF(8); \ - HALF(16); \ - HALF(32); \ - HALF(64); \ - HALF(128); \ - HALF(256); - - -/* - ************************************************************************ - * C O N F I G 2 R E G I S T E R ( 1 6, SELECT 2 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |M| | | | | | | | | | | | |S|T| Config1 - * | | | | | | | | | | | | | |M|L| - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Config2 $16,2 -#define R_C0_Config2 16 - -#define S_Config2More 31 /* Additional Config registers present (R) */ -#define M_Config2More (0x1 << S_Config2More) -#define S_Config2SM 1 /* Denotes SmartMIPS ASE present (R) */ -#define M_Config2SM (0x1 << S_Config2SM) -#define S_Config2TL 0 /* Denotes Tracing Logic present (R) */ -#define M_Config2TL (0x1 << S_Config2TL) - -#define M_Config20Fields 0xfffffffc -#define M_Config2RFields 0x00000003 - -/* - ************************************************************************ - * L L A D D R R E G I S T E R ( 1 7 ) * - ************************************************************************ - * - * 6 6 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | // LL Physical Address | LLAddr - * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_LLAddr $17 -#define R_C0_LLAddr 17 -#define C0_LLADDR C0_LLAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define M_LLAddr0Fields 0x00000000 -#define M_LLAddrRFields 0x00000000 -#define M_LLAddr0Fields64 UNS64Const(0x0000000000000000) -#define M_LLAddrRFields64 UNS64Const(0x0000000000000000) - - -/* - ************************************************************************ - * W A T C H L O R E G I S T E R ( 1 8 ) * - ************************************************************************ - * - * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | // Watch Virtual Address |I|R|W| WatchLo - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_WatchLo $18 -#define R_C0_WatchLo 18 -#define C0_WATCHLO C0_WatchLo /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_WatchLoVAddr 3 /* Watch virtual address (R/W) */ -#define M_WatchLoVAddr (0x1fffffff << S_WatchLoVAddr) -#define S_WatchLoI 2 /* Enable Istream watch (R/W) */ -#define M_WatchLoI (0x1 << S_WatchLoI) -#define S_WatchLoR 1 /* Enable data read watch (R/W) */ -#define M_WatchLoR (0x1 << S_WatchLoR) -#define S_WatchLoW 0 /* Enable data write watch (R/W) */ -#define M_WatchLoW (0x1 << S_WatchLoW) - -#define M_WatchLo0Fields 0x00000000 -#define M_WatchLoRFields 0x00000000 -#define M_WatchLo0Fields64 UNS64Const(0x0000000000000000) -#define M_WatchLoRFields64 UNS64Const(0x0000000000000000) - -#define M_WatchLoEnables (M_WatchLoI | M_WatchLoR | M_WatchLoW) - - -/* - ************************************************************************ - * W A T C H H I R E G I S T E R ( 1 9 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |M|G| Rsvd | ASID | Rsvd | Mask | 0 | WatchHi - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_WatchHi $19 -#define R_C0_WatchHi 19 -#define C0_WATCHHI C0_WatchHi /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_WatchHiM 31 /* Denotes additional Watch registers present (R) */ -#define M_WatchHiM (0x1 << S_WatchHiM) -#define S_WatchHiG 30 /* Enable ASID-independent Watch match (R/W) */ -#define M_WatchHiG (0x1 << S_WatchHiG) -#define S_WatchHiASID 16 /* ASID value to match (R/W) */ -#define M_WatchHiASID (0xff << S_WatchHiASID) -#define S_WatchHiMask 3 /* Address inhibit mask (R/W) */ -#define M_WatchHiMask (0x1ff << S_WatchHiMask) - -#define M_WatchHi0Fields 0x3f00f007 -#define M_WatchHiRFields 0x80000000 - - -/* - ************************************************************************ - * X C O N T E X T R E G I S T E R ( 2 0 ) * - ************************************************************************ - * - * 6 // 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 // 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | // PTEBase | R | BadVPN2<39:13> | 0 | XContext - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_XContext $20 -#define R_C0_XContext 20 -#define C0_EXTCTXT C0_XContext /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_XContextBadVPN2 4 /* BadVPN2 (R) */ -#define S_XContextBadVPN S_XContextBadVPN2 - -#define M_XContext0Fields 0x0000000f - - -/* - ************************************************************************ - * D E B U G R E G I S T E R ( 2 3 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |D|D|N|L|D|H|C|I|M|C|D|I|D|D| | |N|S| |D|D|D|D|D|D| - * |B|M|o|S|o|a|o|B|C|a|B|E|D|D|EJTAG|DExcCode |o|S| |I|I|D|D|B|S| - * |D| |D|N|z|l|u|u|h|c|u|X|B|B| ver | |S|t| |N|B|B|B|p|S| - * | | |C|M|e|t|n|s|e|h|s|I|S|L| | |S| | 0 |T| |S|L| | | Debug - * | | |R| | | |t|E|c|e|E| |I|I| | |t| | | | | | | | | - * | | | | | | |D|P|k|E|P| |m|m| | | | | | | | | | | | - * | | | | | | |M| |P|P| | |p|p| | | | | | | | | | | | - * | | | | | | | | | | | | |r|r| | | | | | | | | | | | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_Debug $23 /* EJTAG */ -#define R_C0_Debug 23 - -#define S_DebugDBD 31 /* Debug branch delay (R) */ -#define M_DebugDBD (0x1 << S_DebugDBD) -#define S_DebugDM 30 /* Debug mode (R) */ -#define M_DebugDM (0x1 << S_DebugDM) -#define S_DebugNoDCR 29 /* No debug control register present (R) */ -#define M_DebugNoDCR (0x1 << S_DebugNoDCR) -#define S_DebugLSNM 28 /* Load/Store Normal Memory (R/W) */ -#define M_DebugLSNM (0x1 << S_DebugLSNM) -#define S_DebugDoze 27 /* Doze (R) */ -#define M_DebugDoze (0x1 << S_DebugDoze) -#define S_DebugHalt 26 /* Halt (R) */ -#define M_DebugHalt (0x1 << S_DebugHalt) -#define S_DebugCountDM 25 /* Count register behavior in debug mode (R/W) */ -#define M_DebugCountDM (0x1 << S_DebugCountDM) -#define S_DebugIBusEP 24 /* Imprecise Instn Bus Error Pending (R/W) */ -#define M_DebugIBusEP (0x1 << S_DebugIBusEP) -#define S_DebugMCheckP 23 /* Imprecise Machine Check Pending (R/W) */ -#define M_DebugMCheckP (0x1 << S_DebugMCheckP) -#define S_DebugCacheEP 22 /* Imprecise Cache Error Pending (R/W) */ -#define M_DebugCacheEP (0x1 << S_DebugCacheEP) -#define S_DebugDBusEP 21 /* Imprecise Data Bus Error Pending (R/W) */ -#define M_DebugDBusEP (0x1 << S_DebugDBusEP) -#define S_DebugIEXI 20 /* Imprecise Exception Inhibit (R/W) */ -#define M_DebugIEXI (0x1 << S_DebugIEXI) -#define S_DebugDDBSImpr 19 /* Debug data break store imprecise (R) */ -#define M_DebugDDBSImpr (0x1 << S_DebugDDBSImpr) -#define S_DebugDDBLImpr 18 /* Debug data break load imprecise (R) */ -#define M_DebugDDBLImpr (0x1 << S_DebugDDBLImpr) -#define S_DebugEJTAGver 15 /* EJTAG version number (R) */ -#define M_DebugEJTAGver (0x7 << S_DebugEJTAGver) -#define S_DebugDExcCode 10 /* Debug exception code (R) */ -#define M_DebugDExcCode (0x1f << S_DebugDExcCode) -#define S_DebugNoSSt 9 /* No single step implemented (R) */ -#define M_DebugNoSSt (0x1 << S_DebugNoSSt) -#define S_DebugSSt 8 /* Single step enable (R/W) */ -#define M_DebugSSt (0x1 << S_DebugSSt) -#define S_DebugDINT 5 /* Debug interrupt (R) */ -#define M_DebugDINT (0x1 << S_DebugDINT) -#define S_DebugDIB 4 /* Debug instruction break (R) */ -#define M_DebugDIB (0x1 << S_DebugDIB) -#define S_DebugDDBS 3 /* Debug data break store (R) */ -#define M_DebugDDBS (0x1 << S_DebugDDBS) -#define S_DebugDDBL 2 /* Debug data break load (R) */ -#define M_DebugDDBL (0x1 << S_DebugDDBL) -#define S_DebugDBp 1 /* Debug breakpoint (R) */ -#define M_DebugDBp (0x1 << S_DebugDBp) -#define S_DebugDSS 0 /* Debug single step (R) */ -#define M_DebugDSS (0x1 << S_DebugDSS) - -#define M_Debug0Fields 0x01f000c0 -#define M_DebugRFields 0xec0ffe3f - - -/* - ************************************************************************ - * D E P C R E G I S T E R ( 2 4 ) * - ************************************************************************ - * - * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | // EJTAG Debug Exception PC | DEPC - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - - -#define C0_DEPC $24 -#define R_C0_DEPC 24 - -#define M_DEEPC0Fields 0x00000000 -#define M_DEEPCRFields 0x00000000 -#define M_DEEPC0Fields64 UNS64Const(0x0000000000000000) -#define M_DEEPCRFields64 UNS64Const(0x0000000000000000) - - -/* - ************************************************************************ - * P E R F C N T R E G I S T E R ( 2 5 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | | | |I| | | |E| - * |M| 0 | Event |E|U|S|K|X| PerfCnt - * | | | | | | | |L| - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Event Count | PerfCnt - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_PerfCnt $25 -#define R_C0_PerfCnt 25 -#define C0_PRFCNT0 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define C0_PRFCNT1 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define S_PerfCntM 31 /* More performance counters exist (R) */ -#define M_PerfCntM (1 << S_PerfCntM) -#define S_PerfCntEvent 5 /* Enabled event (R/W) */ -#define M_PerfCntEvent (0x3f << S_PerfCntEvent) -#define S_PerfCntIE 4 /* Interrupt Enable (R/W) */ -#define M_PerfCntIE (1 << S_PerfCntIE) -#define S_PerfCntU 3 /* Enable counting in User Mode (R/W) */ -#define M_PerfCntU (1 << S_PerfCntU) -#define S_PerfCntS 2 /* Enable counting in Supervisor Mode (R/W) */ -#define M_PerfCntS (1 << S_PerfCntS) -#define S_PerfCntK 1 /* Enable counting in Kernel Mode (R/W) */ -#define M_PerfCntK (1 << S_PerfCntK) -#define S_PerfCntEXL 0 /* Enable counting while EXL==1 (R/W) */ -#define M_PerfCntEXL (1 << S_PerfCntEXL) - -#define M_PerfCnt0Fields 0x7ffff800 -#define M_PerfCntRFields 0x80000000 - - -/* - ************************************************************************ - * E R R C T L R E G I S T E R ( 2 6 ) * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Error Control | ErrCtl - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_ErrCtl $26 -#define R_C0_ErrCtl 26 -#define C0_ECC $26 /* OBSOLETE - DO NOT USE IN NEW CODE */ -#define R_C0_ECC 26 /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define M_ErrCtl0Fields 0x00000000 -#define M_ErrCtlRFields 0x00000000 - - -/* - ************************************************************************ - * C A C H E E R R R E G I S T E R ( 2 7 ) * CacheErr - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | Cache Error Control | CacheErr - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_CacheErr $27 -#define R_C0_CacheErr 27 -#define C0_CACHE_ERR C0_CacheErr /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define M_CacheErr0Fields 0x00000000 -#define M_CachErrRFields 0x00000000 - - -/* - ************************************************************************ - * T A G L O R E G I S T E R ( 2 8 ) * TagLo - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | TagLo | TagLo - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_TagLo $28 -#define R_C0_TagLo 28 -#define C0_TAGLO C0_TagLo /* OBSOLETE - DO NOT USE IN NEW CODE */ - -/* - * Some implementations use separate TagLo registers for the - * instruction and data caches. In those cases, the following - * definitions can be used in relevant code - */ - -#define C0_ITagLo $28,0 -#define C0_DTagLo $28,2 - -#define M_TagLo0Fields 0x00000000 -#define M_TagLoRFields 0x00000000 - - -/* - ************************************************************************ - * D A T A L O R E G I S T E R ( 2 8, SELECT 1 ) * DataLo - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | DataLo | DataLo - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_DataLo $28,1 -#define R_C0_DataLo 28 - -/* - * Some implementations use separate DataLo registers for the - * instruction and data caches. In those cases, the following - * definitions can be used in relevant code - */ - -#define C0_IDataLo $28,1 -#define C0_DDataLo $28,3 - -#define M_DataLo0Fields 0x00000000 -#define M_DataLoRFields 0xffffffff - - -/* - ************************************************************************ - * T A G H I R E G I S T E R ( 2 9 ) * TagHi - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | TagHi | TagHi - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_TagHi $29 -#define R_C0_TagHi 29 -#define C0_TAGHI C0_TagHi /* OBSOLETE - DO NOT USE IN NEW CODE */ - -/* - * Some implementations use separate TagHi registers for the - * instruction and data caches. In those cases, the following - * definitions can be used in relevant code - */ - -#define C0_ITagHi $29,0 -#define C0_DTagHi $29,2 - -#define M_TagHi0Fields 0x00000000 -#define M_TagHiRFields 0x00000000 - - -/* - ************************************************************************ - * D A T A H I R E G I S T E R ( 2 9, SELECT 1 ) * DataHi - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | DataHi | DataHi - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_DataHi $29,1 -#define R_C0_DataHi 29 - -/* - * Some implementations use separate DataHi registers for the - * instruction and data caches. In those cases, the following - * definitions can be used in relevant code - */ - -#define C0_IDataHi $29,1 -#define C0_DDataHi $29,3 - -#define M_DataHi0Fields 0x00000000 -#define M_DataHiRFields 0xffffffff - - -/* - ************************************************************************ - * E R R O R E P C R E G I S T E R ( 3 0 ) * - ************************************************************************ - * - * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | // Error PC | ErrorEPC - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_ErrorEPC $30 -#define R_C0_ErrorEPC 30 -#define C0_ERROR_EPC C0_ErrorEPC /* OBSOLETE - DO NOT USE IN NEW CODE */ - -#define M_ErrorEPC0Fields 0x00000000 -#define M_ErrorEPCRFields 0x00000000 -#define M_ErrorEPC0Fields64 UNS64Const(0x0000000000000000) -#define M_ErrorEPCRFields64 UNS64Const(0x0000000000000000) - - -/* - ************************************************************************ - * D E S A V E R E G I S T E R ( 3 1 ) * - ************************************************************************ - * - * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | // EJTAG Register Save Value | DESAVE - * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C0_DESAVE $31 -#define R_C0_DESAVE 31 - -#define M_DESAVE0Fields 0x00000000 -#define M_DESAVERFields 0x00000000 -#define M_DESAVE0Fields64 UNS64Const(0x0000000000000000) -#define M_DESAVERFields64 UNS64Const(0x0000000000000000) - - -/* - ************************************************************************* - * C P 1 R E G I S T E R D E F I N I T I O N S * - ************************************************************************* - */ - - -/* - ************************************************************************* - * H A R D W A R E F P R N A M E S * - ************************************************************************* - */ - -#define fp0 $f0 -#define fp1 $f1 -#define fp2 $f2 -#define fp3 $f3 -#define fp4 $f4 -#define fp5 $f5 -#define fp6 $f6 -#define fp7 $f7 -#define fp8 $f8 -#define fp9 $f9 -#define fp10 $f10 -#define fp11 $f11 -#define fp12 $f12 -#define fp13 $f13 -#define fp14 $f14 -#define fp15 $f15 -#define fp16 $f16 -#define fp17 $f17 -#define fp18 $f18 -#define fp19 $f19 -#define fp20 $f20 -#define fp21 $f21 -#define fp22 $f22 -#define fp23 $f23 -#define fp24 $f24 -#define fp25 $f25 -#define fp26 $f26 -#define fp27 $f27 -#define fp28 $f28 -#define fp29 $f29 -#define fp30 $f30 -#define fp31 $f31 - -/* - * The following definitions are used to convert an FPR name - * into the corresponding even or odd name, respectively. - * This is used in macro substitution in the AVPs. - */ - -#define fp1_even $f0 -#define fp3_even $f2 -#define fp5_even $f4 -#define fp7_even $f6 -#define fp9_even $f8 -#define fp11_even $f10 -#define fp13_even $f12 -#define fp15_even $f14 -#define fp17_even $f16 -#define fp19_even $f18 -#define fp21_even $f20 -#define fp23_even $f22 -#define fp25_even $f24 -#define fp27_even $f26 -#define fp29_even $f28 -#define fp31_even $f30 - -#define fp0_odd $f1 -#define fp2_odd $f3 -#define fp4_odd $f5 -#define fp6_odd $f7 -#define fp8_odd $f9 -#define fp10_odd $f11 -#define fp12_odd $f13 -#define fp14_odd $f15 -#define fp16_odd $f17 -#define fp18_odd $f19 -#define fp20_odd $f21 -#define fp22_odd $f23 -#define fp24_odd $f25 -#define fp26_odd $f27 -#define fp28_odd $f29 -#define fp30_odd $f31 - - -/* - ************************************************************************* - * H A R D W A R E F P R I N D I C E S * - ************************************************************************* - * - * These definitions provide the index (number) of the FPR, as opposed - * to the assembler register name ($n). - */ - -#define R_fp0 0 -#define R_fp1 1 -#define R_fp2 2 -#define R_fp3 3 -#define R_fp4 4 -#define R_fp5 5 -#define R_fp6 6 -#define R_fp7 7 -#define R_fp8 8 -#define R_fp9 9 -#define R_fp10 10 -#define R_fp11 11 -#define R_fp12 12 -#define R_fp13 13 -#define R_fp14 14 -#define R_fp15 15 -#define R_fp16 16 -#define R_fp17 17 -#define R_fp18 18 -#define R_fp19 19 -#define R_fp20 20 -#define R_fp21 21 -#define R_fp22 22 -#define R_fp23 23 -#define R_fp24 24 -#define R_fp25 25 -#define R_fp26 26 -#define R_fp27 27 -#define R_fp28 28 -#define R_fp29 29 -#define R_fp30 30 -#define R_fp31 31 - - -/* - ************************************************************************* - * H A R D W A R E F C R N A M E S * - ************************************************************************* - */ - -#define fc0 $0 -#define fc25 $25 -#define fc26 $26 -#define fc28 $28 -#define fc31 $31 - - -/* - ************************************************************************* - * H A R D W A R E F C R I N D I C E S * - ************************************************************************* - * - * These definitions provide the index (number) of the FCR, as opposed - * to the assembler register name ($n). - */ - -#define R_fc0 0 -#define R_fc25 25 -#define R_fc26 26 -#define R_fc28 28 -#define R_fc31 31 - - -/* - ************************************************************************* - * H A R D W A R E F C C N A M E S * - ************************************************************************* - */ - -#define cc0 $fcc0 -#define cc1 $fcc1 -#define cc2 $fcc2 -#define cc3 $fcc3 -#define cc4 $fcc4 -#define cc5 $fcc5 -#define cc6 $fcc6 -#define cc7 $fcc7 - - -/* - ************************************************************************* - * H A R D W A R E F C C I N D I C E S * - ************************************************************************* - * - * These definitions provide the index (number) of the CC, as opposed - * to the assembler register name ($n). - */ - -#define R_cc0 0 -#define R_cc1 1 -#define R_cc2 2 -#define R_cc3 3 -#define R_cc4 4 -#define R_cc5 5 -#define R_cc6 6 -#define R_cc7 7 - - -/* - ************************************************************************ - * I M P L E M E N T A T I O N R E G I S T E R * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * |Reserved for Additional|3|P|D|S| Implementation| Revision | FIR - * | Configuration Bits |D|S| | | | | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C1_FIR $0 -#define R_C1_FIR 0 - -#define S_FIRConfigS 16 -#define M_FIRConfigS (0x1 << S_FIRConfigS) -#define S_FIRConfigD 17 -#define M_FIRConfigD (0x1 << S_FIRConfigD) -#define S_FIRConfigPS 18 -#define M_FIRConfigPS (0x1 << S_FIRConfigPS) -#define S_FIRConfig3D 19 -#define M_FIRConfig3D (0x1 << S_FIRConfig3D) -#define M_FIRConfigAll (M_FIRConfigS|M_FIRConfigD|M_FIRConfigPS|M_FIRConfig3D) - -#define S_FIRImp 8 -#define M_FIRImp (0xff << S_FIRImp) - -#define S_FIRRev 0 -#define M_FIRRev (0xff << S_FIRRev) - -#define M_FIR0Fields 0xfff00000 -#define M_FIRRFields 0x000fffff - -/* - ************************************************************************ - * C O N D I T I O N C O D E S R E G I S T E R * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | 0 | CC | FCCR - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C1_FCCR $25 -#define R_C1_FCCR 25 - -#define S_FCCRCC 0 -#define M_FCCRCC (0xff << S_FCCRCC) -#define S_FCCRCC7 7 -#define M_FCCRCC7 (0x1 << S_FCCRCC7) -#define S_FCCRCC6 6 -#define M_FCCRCC6 (0x1 << S_FCCRCC6) -#define S_FCCRCC5 5 -#define M_FCCRCC5 (0x1 << S_FCCRCC5) -#define S_FCCRCC4 4 -#define M_FCCRCC4 (0x1 << S_FCCRCC4) -#define S_FCCRCC3 3 -#define M_FCCRCC3 (0x1 << S_FCCRCC3) -#define S_FCCRCC2 2 -#define M_FCCRCC2 (0x1 << S_FCCRCC2) -#define S_FCCRCC1 1 -#define M_FCCRCC1 (0x1 << S_FCCRCC1) -#define S_FCCRCC0 0 -#define M_FCCRCC0 (0x1 << S_FCCRCC0) - -#define M_FCCR0Fields 0xffffff00 -#define M_FCCRRFields 0x000000ff - - -/* - ************************************************************************ - * E X C E P T I O N S R E G I S T E R * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | 0 | Cause | 0 | Flags | 0 | FEXR - * | |E|V|Z|O|U|I| |V|Z|O|U|I| | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C1_FEXR $26 -#define R_C1_FEXR 26 - -#define S_FEXRExc 12 -#define M_FEXRExc (0x3f << S_FEXRExc) -#define S_FEXRExcE 17 -#define M_FEXRExcE (0x1 << S_FEXRExcE) -#define S_FEXRExcV 16 -#define M_FEXRExcV (0x1 << S_FEXRExcV) -#define S_FEXRExcZ 15 -#define M_FEXRExcZ (0x1 << S_FEXRExcZ) -#define S_FEXRExcO 14 -#define M_FEXRExcO (0x1 << S_FEXRExcO) -#define S_FEXRExcU 13 -#define M_FEXRExcU (0x1 << S_FEXRExcU) -#define S_FEXRExcI 12 -#define M_FEXRExcI (0x1 << S_FEXRExcI) - -#define S_FEXRFlg 2 -#define M_FEXRFlg (0x1f << S_FEXRFlg) -#define S_FEXRFlgV 6 -#define M_FEXRFlgV (0x1 << S_FEXRFlgV) -#define S_FEXRFlgZ 5 -#define M_FEXRFlgZ (0x1 << S_FEXRFlgZ) -#define S_FEXRFlgO 4 -#define M_FEXRFlgO (0x1 << S_FEXRFlgO) -#define S_FEXRFlgU 3 -#define M_FEXRFlgU (0x1 << S_FEXRFlgU) -#define S_FEXRFlgI 2 -#define M_FEXRFlgI (0x1 << S_FEXRFlgI) - -#define M_FEXR0Fields 0xfffc0f83 -#define M_FEXRRFields 0x00000000 - - -/* - ************************************************************************ - * E N A B L E S R E G I S T E R * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | 0 | Enables | 0 |F|RM | FENR - * | |V|Z|O|U|I| |S| | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C1_FENR $28 -#define R_C1_FENR 28 - -#define S_FENREna 7 -#define M_FENREna (0x1f << S_FENREna) -#define S_FENREnaV 11 -#define M_FENREnaV (0x1 << S_FENREnaV) -#define S_FENREnaZ 10 -#define M_FENREnaZ (0x1 << S_FENREnaZ) -#define S_FENREnaO 9 -#define M_FENREnaO (0x1 << S_FENREnaO) -#define S_FENREnaU 8 -#define M_FENREnaU (0x1 << S_FENREnaU) -#define S_FENREnaI 7 -#define M_FENREnaI (0x1 << S_FENREnaI) - -#define S_FENRFS 2 -#define M_FENRFS (0x1 << S_FENRFS) - -#define S_FENRRM 0 -#define M_FENRRM (0x3 << S_FENRRM) - -#define M_FENR0Fields 0xfffff078 -#define M_FENRRFields 0x00000000 - - -/* - ************************************************************************ - * C O N T R O L / S T A T U S R E G I S T E R * - ************************************************************************ - * - * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | FCC |F|C|Imp| 0 | Cause | Enables | Flags | RM| FCSR - * |7|6|5|4|3|2|1|S|C| | |E|V|Z|O|U|I|V|Z|O|U|I|V|Z|O|U|I| | - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - */ - -#define C1_FCSR $31 -#define R_C1_FCSR 31 - -#define S_FCSRFCC7_1 25 /* Floating point condition codes 7..1 (R/W) */ -#define M_FCSRFCC7_1 (0x7f << S_FCSRFCC7_1) -#define S_FCSRCC7 31 -#define M_FCSRCC7 (0x1 << S_FCSRCC7) -#define S_FCSRCC6 30 -#define M_FCSRCC6 (0x1 << S_FCSRCC6) -#define S_FCSRCC5 29 -#define M_FCSRCC5 (0x1 << S_FCSRCC5) -#define S_FCSRCC4 28 -#define M_FCSRCC4 (0x1 << S_FCSRCC4) -#define S_FCSRCC3 27 -#define M_FCSRCC3 (0x1 << S_FCSRCC3) -#define S_FCSRCC2 26 -#define M_FCSRCC2 (0x1 << S_FCSRCC2) -#define S_FCSRCC1 25 -#define M_FCSRCC1 (0x1 << S_FCSRCC1) - -#define S_FCSRFS 24 /* Flush denorms to zero (R/W) */ -#define M_FCSRFS (0x1 << S_FCSRFS) - -#define S_FCSRCC0 23 /* Floating point condition code 0 (R/W) */ -#define M_FCSRCC0 (0x1 << S_FCSRCC0) -#define S_FCSRCC S_FCSRCC0 -#define M_FCSRCC M_FCSRCC0 - -#define S_FCSRImpl 21 /* Implementation-specific control bits (R/W) */ -#define M_FCSRImpl (0x3 << S_FCSRImpl) - -#define S_FCSRExc 12 /* Exception cause (R/W) */ -#define M_FCSRExc (0x3f << S_FCSRExc) -#define S_FCSRExcE 17 -#define M_FCSRExcE (0x1 << S_FCSRExcE) -#define S_FCSRExcV 16 -#define M_FCSRExcV (0x1 << S_FCSRExcV) -#define S_FCSRExcZ 15 -#define M_FCSRExcZ (0x1 << S_FCSRExcZ) -#define S_FCSRExcO 14 -#define M_FCSRExcO (0x1 << S_FCSRExcO) -#define S_FCSRExcU 13 -#define M_FCSRExcU (0x1 << S_FCSRExcU) -#define S_FCSRExcI 12 -#define M_FCSRExcI (0x1 << S_FCSRExcI) - -#define S_FCSREna 7 /* Exception enable (R/W) */ -#define M_FCSREna (0x1f << S_FCSREna) -#define S_FCSREnaV 11 -#define M_FCSREnaV (0x1 << S_FCSREnaV) -#define S_FCSREnaZ 10 -#define M_FCSREnaZ (0x1 << S_FCSREnaZ) -#define S_FCSREnaO 9 -#define M_FCSREnaO (0x1 << S_FCSREnaO) -#define S_FCSREnaU 8 -#define M_FCSREnaU (0x1 << S_FCSREnaU) -#define S_FCSREnaI 7 -#define M_FCSREnaI (0x1 << S_FCSREnaI) - -#define S_FCSRFlg 2 /* Exception flags (R/W) */ -#define M_FCSRFlg (0x1f << S_FCSRFlg) -#define S_FCSRFlgV 6 -#define M_FCSRFlgV (0x1 << S_FCSRFlgV) -#define S_FCSRFlgZ 5 -#define M_FCSRFlgZ (0x1 << S_FCSRFlgZ) -#define S_FCSRFlgO 4 -#define M_FCSRFlgO (0x1 << S_FCSRFlgO) -#define S_FCSRFlgU 3 -#define M_FCSRFlgU (0x1 << S_FCSRFlgU) -#define S_FCSRFlgI 2 -#define M_FCSRFlgI (0x1 << S_FCSRFlgI) - -#define S_FCSRRM 0 /* Rounding mode (R/W) */ -#define M_FCSRRM (0x3 << S_FCSRRM) - -#define M_FCSR0Fields 0x001c0000 -#define M_FCSRRFields 0x00000000 - -/* - * Values in the rounding mode field (of both FCSR and FCCR) - */ -#define K_FCSRRM_RN 0 -#define K_FCSRRM_RZ 1 -#define K_FCSRRM_RP 2 -#define K_FCSRRM_RM 3 - -#endif /* _COMMON_MIPS_DEF_H_ */ diff --git a/libcpu/mips/common/mips_excpt.h b/libcpu/mips/common/mips_excpt.h deleted file mode 100644 index 868b046d3c..0000000000 --- a/libcpu/mips/common/mips_excpt.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * File : mips_excpt.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��7�� Urey the first version - */ - -#ifndef _MIPS_EXCPT_H_ -#define _MIPS_EXCPT_H_ - -#include "mips_regs.h" - -#ifndef __ASSEMBLY__ -typedef void (* exception_func_t)(mips_reg_ctx *regs); - -//extern exception_func_t mips_exception_handlers[]; - -int rt_hw_exception_init(void); -exception_func_t rt_set_except_vector(int n, exception_func_t func); -void install_default_execpt_handle(void); -#endif /* __ASSEMBLY__ */ -#endif /* _MIPS_EXCPT_H_ */ diff --git a/libcpu/mips/common/mips_fpu.h b/libcpu/mips/common/mips_fpu.h new file mode 100644 index 0000000000..50df3746a5 --- /dev/null +++ b/libcpu/mips/common/mips_fpu.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + */ + +#ifndef _MIPS_FPU_H_ +#define _MIPS_FPU_H_ + +#ifndef __ASSEMBLY__ + +#include <mips_regs.h> +/** + * init hardware FPU + */ +#ifdef RT_USING_FPU +rt_inline void rt_hw_fpu_init(void) +{ + rt_uint32_t c0_status = 0; + rt_uint32_t c1_status = 0; + + /* Enable CU1 */ + c0_status = read_c0_status(); + c0_status |= (ST0_CU1 | ST0_FR); + write_c0_status(c0_status); + + /* FCSR Configs */ + c1_status = read_c1_status(); + c1_status |= (FPU_CSR_FS | FPU_CSR_FO | FPU_CSR_FN); /* Set FS, FO, FN */ + c1_status &= ~(FPU_CSR_ALL_E); /* Disable exception */ + c1_status = (c1_status & (~FPU_CSR_RM)) | FPU_CSR_RN; /* Set RN */ + write_c1_status(c1_status); + + return ; +} +#else + rt_inline void rt_hw_fpu_init(void){} /* Do nothing */ +#endif + +#endif + +#endif diff --git a/libcpu/mips/common/mips_regs.h b/libcpu/mips/common/mips_regs.h index 7ea07d3869..a13e24b539 100644 --- a/libcpu/mips/common/mips_regs.h +++ b/libcpu/mips/common/mips_regs.h @@ -1,202 +1,140 @@ /* - * File : mips_regs.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2019, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2016��9��7�� Urey the first version + * 2019-12-04 Jiaxun Yang Initial version */ #ifndef _MIPS_REGS_H_ #define _MIPS_REGS_H_ +#include <rtconfig.h> +#define REG_A0 4 +#define REG_SP 29 +#define REG_GP 28 +#define REG_FP 30 +#define REG_RA 31 +#ifndef ARCH_MIPS64 +#define zero $0 /* wired zero */ +#define AT $1 /* assembler temp - uppercase because of ".set at" */ +#define v0 $2 /* return value */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 /* caller saved */ +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define ta0 $12 +#define t5 $13 +#define ta1 $13 +#define t6 $14 +#define ta2 $14 +#define t7 $15 +#define ta3 $15 +#define s0 $16 /* callee saved */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* caller saved */ +#define t9 $25 +#define jp $25 /* PIC jump register */ +#define k0 $26 /* kernel scratch */ +#define k1 $27 +#define gp $28 /* global pointer */ +#define sp $29 /* stack pointer */ +#define fp $30 /* frame pointer */ +#define s8 $30 /* same like fp! */ +#define ra $31 /* return address */ -#if !defined(__ASSEMBLY__) && !defined(ASSEMBLY) -#include <rtdef.h> - -#define MIPS_REG_NR 32 -typedef struct { - rt_uint32_t regs[MIPS_REG_NR]; /* 32 ��ͨ��Ŀ�ļĴ��� */ - rt_uint32_t CP0Status; /* CP0 Э������״̬�Ĵ��� */ - rt_uint32_t CP0DataHI; /* ������λ�Ĵ��� */ - rt_uint32_t CP0DataLO; /* ������λ�Ĵ��� */ - rt_uint32_t CP0BadVAddr; /* ������ַ�Ĵ��� */ - rt_uint32_t CP0Cause; /* �����жϻ����쳣�鿴�ļĴ���*/ - rt_uint32_t CP0EPC; /* ����������Ĵ��� */ -} mips_reg_ctx; - -#define MIPS_ARG_REG_NR 4 -typedef struct -{ - rt_uint32_t args[MIPS_ARG_REG_NR]; /* 4 �������Ĵ��� */ -} mips_arg_ctx; - -struct linkctx -{ - rt_uint32_t id; - struct linkctx *next; -}; - -struct fpctx -{ - struct linkctx link; - rt_uint32_t fcsr; - rt_uint32_t reserved; -}; - - -struct fp32ctx -{ - struct fpctx fp; - union - { - double d[16]; /* even doubles */ - float s[32]; /* even singles, padded */ - }; -}; - -struct fp64ctx -{ - struct fpctx fp; - union - { - double d[32]; /* even doubles, followed by odd doubles */ - float s[64]; /* even singles, followed by odd singles, padded */ - }; -}; - -#endif /* !defined(__ASSEMBLY__) && !defined(ASSEMBLY) */ - -#define MIPS_STK_CTX_WORD_SIZE 38 -#define SZREG 4 -/********************************************************************************************************* - MIPS �ļĴ������� -*********************************************************************************************************/ -#define REG_ZERO 0 /* wired zero */ -#define REG_AT 1 /* assembler temp */ -#define REG_V0 2 /* return reg 0 */ -#define REG_V1 3 /* return reg 1 */ -#define REG_A0 4 /* arg reg 0 */ -#define REG_A1 5 /* arg reg 1 */ -#define REG_A2 6 /* arg reg 2 */ -#define REG_A3 7 /* arg reg 3 */ -#define REG_T0 8 /* caller saved 0 */ -#define REG_T1 9 /* caller saved 1 */ -#define REG_T2 10 /* caller saved 2 */ -#define REG_T3 11 /* caller saved 3 */ -#define REG_T4 12 /* caller saved 4 */ -#define REG_T5 13 /* caller saved 5 */ -#define REG_T6 14 /* caller saved 6 */ -#define REG_T7 15 /* caller saved 7 */ -#define REG_S0 16 /* callee saved 0 */ -#define REG_S1 17 /* callee saved 1 */ -#define REG_S2 18 /* callee saved 2 */ -#define REG_S3 19 /* callee saved 3 */ -#define REG_S4 20 /* callee saved 4 */ -#define REG_S5 21 /* callee saved 5 */ -#define REG_S6 22 /* callee saved 6 */ -#define REG_S7 23 /* callee saved 7 */ -#define REG_T8 24 /* caller saved 8 */ -#define REG_T9 25 /* caller saved 9 */ -#define REG_K0 26 /* kernel temp 0 */ -#define REG_K1 27 /* kernel temp 1 */ -#define REG_GP 28 /* global pointer */ -#define REG_SP 29 /* stack pointer */ -#define REG_S8 30 /* callee saved 8 */ -#define REG_FP REG_S8 /* callee saved 8 */ -#define REG_RA 31 /* return address */ - -#define STK_CTX_SIZE (MIPS_STK_CTX_WORD_SIZE * SZREG) -#define STK_OFFSET_SR ((32 + 0) * SZREG) -#define STK_OFFSET_HI ((32 + 1) * SZREG) -#define STK_OFFSET_LO ((32 + 2) * SZREG) -#define STK_OFFSET_BADVADDR ((32 + 3) * SZREG) -#define STK_OFFSET_CAUSE ((32 + 4) * SZREG) -#define STK_OFFSET_EPC ((32 + 5) * SZREG) - -#define STK_OFFSET_LAST ((MIPS_STK_CTX_WORD_SIZE - 1) * SZREG) +#else -#define FP32CTX_CSR ((SZREG)*2) -#define FP64CTX_CSR ((SZREG)*2) +#define zero $0 /* wired zero */ +#define AT $at /* assembler temp - uppercase because of ".set at" */ +#define v0 $2 /* return value - caller saved */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */ +#define ta0 $8 +#define a5 $9 +#define ta1 $9 +#define a6 $10 +#define ta2 $10 +#define a7 $11 +#define ta3 $11 +#define t0 $12 /* caller saved */ +#define t1 $13 +#define t2 $14 +#define t3 $15 +#define s0 $16 /* callee saved */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* caller saved */ +#define t9 $25 /* callee address for PIC/temp */ +#define jp $25 /* PIC jump register */ +#define k0 $26 /* kernel temporary */ +#define k1 $27 +#define gp $28 /* global pointer - caller saved for PIC */ +#define sp $29 /* stack pointer */ +#define fp $30 /* frame pointer */ +#define s8 $30 /* callee saved */ +#define ra $31 /* return address */ -#define LINKCTX_ID ((SZREG)*0) -#define LINKCTX_NEXT ((SZREG)*1) -#define LINKCTX_TYPE_MSA 0x004D5341 -#define LINKCTX_TYPE_FP32 0x46503332 -#define LINKCTX_TYPE_FP64 0x46503634 -#define LINKCTX_TYPE_FMSA 0x463D5341 -#define LINKCTX_TYPE_DSP 0x00445350 -#define LINKCTX_TYPE_STKSWP 0x53574150 -#define LINKCTX_TYPE_XPA 0x00585041 +#endif -#define FP32CTX_0 ((SZREG)*4) -#define FP32CTX_2 (FP32CTX_0 + (1 * 8)) -#define FP32CTX_4 (FP32CTX_0 + (2 * 8)) -#define FP32CTX_6 (FP32CTX_0 + (3 * 8)) -#define FP32CTX_8 (FP32CTX_0 + (4 * 8)) -#define FP32CTX_10 (FP32CTX_0 + (5 * 8)) -#define FP32CTX_12 (FP32CTX_0 + (6 * 8)) -#define FP32CTX_14 (FP32CTX_0 + (7 * 8)) -#define FP32CTX_16 (FP32CTX_0 + (8 * 8)) -#define FP32CTX_18 (FP32CTX_0 + (9 * 8)) -#define FP32CTX_20 (FP32CTX_0 + (10 * 8)) -#define FP32CTX_22 (FP32CTX_0 + (11 * 8)) -#define FP32CTX_24 (FP32CTX_0 + (12 * 8)) -#define FP32CTX_26 (FP32CTX_0 + (13 * 8)) -#define FP32CTX_28 (FP32CTX_0 + (14 * 8)) -#define FP32CTX_30 (FP32CTX_0 + (15 * 8)) -#define FP32CTX_SIZE (FP32CTX_30 + (17 * 8)) +#define fv0 $f0 /* return value */ +#define fv0f $f1 +#define fv1 $f2 +#define fv1f $f3 +#define fa0 $f12 /* argument registers */ +#define fa0f $f13 +#define fa1 $f14 +#define fa1f $f15 +#define ft0 $f4 /* caller saved */ +#define ft0f $f5 +#define ft1 $f6 +#define ft1f $f7 +#define ft2 $f8 +#define ft2f $f9 +#define ft3 $f10 +#define ft3f $f11 +#define ft4 $f16 +#define ft4f $f17 +#define ft5 $f18 +#define ft5f $f19 +#define fs0 $f20 /* callee saved */ +#define fs0f $f21 +#define fs1 $f22 +#define fs1f $f23 +#define fs2 $f24 +#define fs2f $f25 +#define fs3 $f26 +#define fs3f $f27 +#define fs4 $f28 +#define fs4f $f29 +#define fs5 $f30 +#define fs5f $f31 -#define FP64CTX_0 ((SZREG)*4) -#define FP64CTX_2 (FP64CTX_0 + (1 * 8)) -#define FP64CTX_4 (FP64CTX_0 + (2 * 8)) -#define FP64CTX_6 (FP64CTX_0 + (3 * 8)) -#define FP64CTX_8 (FP64CTX_0 + (4 * 8)) -#define FP64CTX_10 (FP64CTX_0 + (5 * 8)) -#define FP64CTX_12 (FP64CTX_0 + (6 * 8)) -#define FP64CTX_14 (FP64CTX_0 + (7 * 8)) -#define FP64CTX_16 (FP64CTX_0 + (8 * 8)) -#define FP64CTX_18 (FP64CTX_0 + (9 * 8)) -#define FP64CTX_20 (FP64CTX_0 + (10 * 8)) -#define FP64CTX_22 (FP64CTX_0 + (11 * 8)) -#define FP64CTX_24 (FP64CTX_0 + (12 * 8)) -#define FP64CTX_26 (FP64CTX_0 + (13 * 8)) -#define FP64CTX_28 (FP64CTX_0 + (14 * 8)) -#define FP64CTX_30 (FP64CTX_0 + (15 * 8)) -#define FP64CTX_1 (FP64CTX_30 + (1 * 8)) -#define FP64CTX_3 (FP64CTX_30 + (2 * 8)) -#define FP64CTX_5 (FP64CTX_30 + (3 * 8)) -#define FP64CTX_7 (FP64CTX_30 + (4 * 8)) -#define FP64CTX_9 (FP64CTX_30 + (5 * 8)) -#define FP64CTX_11 (FP64CTX_30 + (6 * 8)) -#define FP64CTX_13 (FP64CTX_30 + (7 * 8)) -#define FP64CTX_15 (FP64CTX_30 + (8 * 8)) -#define FP64CTX_17 (FP64CTX_30 + (9 * 8)) -#define FP64CTX_19 (FP64CTX_30 + (10 * 8)) -#define FP64CTX_21 (FP64CTX_30 + (11 * 8)) -#define FP64CTX_23 (FP64CTX_30 + (12 * 8)) -#define FP64CTX_25 (FP64CTX_30 + (13 * 8)) -#define FP64CTX_27 (FP64CTX_30 + (14 * 8)) -#define FP64CTX_29 (FP64CTX_30 + (15 * 8)) -#define FP64CTX_31 (FP64CTX_30 + (16 * 8)) -#define FP64CTX_SIZE (FP64CTX_31 + (17 * 8)) +#define fcr31 $31 /* FPU status register */ -#define FPCTX_SIZE() (mips_getsr() & ST0_FR ? FP64CTX_SIZE : FP32CTX_SIZE) /* * The following macros are especially useful for __asm__ @@ -284,75 +222,128 @@ struct fp64ctx /* * Coprocessor 1 (FPU) register names */ -#define CP1_REVISION $0 -#define CP1_STATUS $31 +#define CP1_REVISION $0 +#define CP1_UFR $1 +#define CP1_UNFR $4 +#define CP1_FCCR $25 +#define CP1_FEXR $26 +#define CP1_FENR $28 +#define CP1_STATUS $31 + /* - * FPU Status Register Values + * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. */ +#define MIPS_FPIR_S (_ULCAST_(1) << 16) +#define MIPS_FPIR_D (_ULCAST_(1) << 17) +#define MIPS_FPIR_PS (_ULCAST_(1) << 18) +#define MIPS_FPIR_3D (_ULCAST_(1) << 19) +#define MIPS_FPIR_W (_ULCAST_(1) << 20) +#define MIPS_FPIR_L (_ULCAST_(1) << 21) +#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) +#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23) +#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28) +#define MIPS_FPIR_FREP (_ULCAST_(1) << 29) + /* - * Status Register Values + * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register. */ - -#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ -#define FPU_CSR_COND 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ -#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ -#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ -#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ -#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ -#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ -#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ +#define MIPS_FCCR_CONDX_S 0 +#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S) +#define MIPS_FCCR_COND0_S 0 +#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S) +#define MIPS_FCCR_COND1_S 1 +#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S) +#define MIPS_FCCR_COND2_S 2 +#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S) +#define MIPS_FCCR_COND3_S 3 +#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S) +#define MIPS_FCCR_COND4_S 4 +#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S) +#define MIPS_FCCR_COND5_S 5 +#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S) +#define MIPS_FCCR_COND6_S 6 +#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S) +#define MIPS_FCCR_COND7_S 7 +#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S) /* - * X the exception cause indicator - * E the exception enable - * S the sticky/flag bit -*/ -#define FPU_CSR_ALL_X 0x0003f000 -#define FPU_CSR_UNI_X 0x00020000 -#define FPU_CSR_INV_X 0x00010000 -#define FPU_CSR_DIV_X 0x00008000 -#define FPU_CSR_OVF_X 0x00004000 -#define FPU_CSR_UDF_X 0x00002000 -#define FPU_CSR_INE_X 0x00001000 + * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register. + */ +#define MIPS_FENR_FS_S 2 +#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S) -#define FPU_CSR_ALL_E 0x00000f80 -#define FPU_CSR_INV_E 0x00000800 -#define FPU_CSR_DIV_E 0x00000400 -#define FPU_CSR_OVF_E 0x00000200 -#define FPU_CSR_UDF_E 0x00000100 -#define FPU_CSR_INE_E 0x00000080 +/* + * FPU Status Register Values + */ +#define FPU_CSR_COND_S 23 /* $fcc0 */ +#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S) -#define FPU_CSR_ALL_S 0x0000007c -#define FPU_CSR_INV_S 0x00000040 -#define FPU_CSR_DIV_S 0x00000020 -#define FPU_CSR_OVF_S 0x00000010 -#define FPU_CSR_UDF_S 0x00000008 -#define FPU_CSR_INE_S 0x00000004 +#define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */ +#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S) -/* rounding mode */ -#define FPU_CSR_RN 0x0 /* nearest */ -#define FPU_CSR_RZ 0x1 /* towards zero */ -#define FPU_CSR_RU 0x2 /* towards +Infinity */ -#define FPU_CSR_RD 0x3 /* towards -Infinity */ +#define FPU_CSR_FO 0x00400000 +#define FPU_CSR_FN 0x00200000 +#define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */ +#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S) +#define FPU_CSR_COND1_S 25 /* $fcc1 */ +#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S) +#define FPU_CSR_COND2_S 26 /* $fcc2 */ +#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S) +#define FPU_CSR_COND3_S 27 /* $fcc3 */ +#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S) +#define FPU_CSR_COND4_S 28 /* $fcc4 */ +#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S) +#define FPU_CSR_COND5_S 29 /* $fcc5 */ +#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S) +#define FPU_CSR_COND6_S 30 /* $fcc6 */ +#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S) +#define FPU_CSR_COND7_S 31 /* $fcc7 */ +#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S) /* - * Values for PageMask register + * Bits 22:20 of the FPU Status Register will be read as 0, + * and should be written as zero. */ -#ifdef CONFIG_CPU_VR41XX +#define FPU_CSR_RSVD (_ULCAST_(7) << 20) -/* Why doesn't stupidity hurt ... */ +#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19) +#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18) -#define PM_1K 0x00000000 -#define PM_4K 0x00001800 -#define PM_16K 0x00007800 -#define PM_64K 0x0001f800 -#define PM_256K 0x0007f800 +/* + * X the exception cause indicator + * E the exception enable + * S the sticky/flag bit +*/ +#define FPU_CSR_ALL_X 0x0003f000 +#define FPU_CSR_UNI_X 0x00020000 +#define FPU_CSR_INV_X 0x00010000 +#define FPU_CSR_DIV_X 0x00008000 +#define FPU_CSR_OVF_X 0x00004000 +#define FPU_CSR_UDF_X 0x00002000 +#define FPU_CSR_INE_X 0x00001000 -#else +#define FPU_CSR_ALL_E 0x00000f80 +#define FPU_CSR_INV_E 0x00000800 +#define FPU_CSR_DIV_E 0x00000400 +#define FPU_CSR_OVF_E 0x00000200 +#define FPU_CSR_UDF_E 0x00000100 +#define FPU_CSR_INE_E 0x00000080 + +#define FPU_CSR_ALL_S 0x0000007c +#define FPU_CSR_INV_S 0x00000040 +#define FPU_CSR_DIV_S 0x00000020 +#define FPU_CSR_OVF_S 0x00000010 +#define FPU_CSR_UDF_S 0x00000008 +#define FPU_CSR_INE_S 0x00000004 + +/* Bits 0 and 1 of FPU Status Register specify the rounding mode */ +#define FPU_CSR_RM 0x00000003 +#define FPU_CSR_RN 0x0 /* nearest */ +#define FPU_CSR_RZ 0x1 /* towards zero */ +#define FPU_CSR_RU 0x2 /* towards +Infinity */ +#define FPU_CSR_RD 0x3 /* towards -Infinity */ #define PM_4K 0x00000000 #define PM_16K 0x00006000 @@ -364,7 +355,6 @@ struct fp64ctx #define PM_64M 0x07ffe000 #define PM_256M 0x1fffe000 -#endif /* * Values used for computation of new tlb entries @@ -440,38 +430,6 @@ struct fp64ctx #define ST0_IL (_ULCAST_(1) << 23) #define ST0_DL (_ULCAST_(1) << 24) -/* - * Bitfields in the TX39 family CP0 Configuration Register 3 - */ -#define TX39_CONF_ICS_SHIFT 19 -#define TX39_CONF_ICS_MASK 0x00380000 -#define TX39_CONF_ICS_1KB 0x00000000 -#define TX39_CONF_ICS_2KB 0x00080000 -#define TX39_CONF_ICS_4KB 0x00100000 -#define TX39_CONF_ICS_8KB 0x00180000 -#define TX39_CONF_ICS_16KB 0x00200000 - -#define TX39_CONF_DCS_SHIFT 16 -#define TX39_CONF_DCS_MASK 0x00070000 -#define TX39_CONF_DCS_1KB 0x00000000 -#define TX39_CONF_DCS_2KB 0x00010000 -#define TX39_CONF_DCS_4KB 0x00020000 -#define TX39_CONF_DCS_8KB 0x00030000 -#define TX39_CONF_DCS_16KB 0x00040000 - -#define TX39_CONF_CWFON 0x00004000 -#define TX39_CONF_WBON 0x00002000 -#define TX39_CONF_RF_SHIFT 10 -#define TX39_CONF_RF_MASK 0x00000c00 -#define TX39_CONF_DOZE 0x00000200 -#define TX39_CONF_HALT 0x00000100 -#define TX39_CONF_LOCK 0x00000080 -#define TX39_CONF_ICE 0x00000020 -#define TX39_CONF_DCE 0x00000010 -#define TX39_CONF_IRSIZE_SHIFT 2 -#define TX39_CONF_IRSIZE_MASK 0x0000000c -#define TX39_CONF_DRSIZE_SHIFT 0 -#define TX39_CONF_DRSIZE_MASK 0x00000003 /* * Status register bits available in all MIPS CPUs. @@ -729,77 +687,77 @@ struct fp64ctx #define __read_32bit_c0_register(source, sel) \ ({ int __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mfc0\t%0, " #source "\n\t" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__res)); \ - __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mfc0\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0\n\t" \ + : "=r" (__res)); \ + __res; \ }) #define __read_64bit_c0_register(source, sel) \ ({ unsigned long __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmfc0\t%0, " #source "\n\t" \ - ".set\tmips0" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0" \ - : "=r" (__res)); \ - __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmfc0\t%0, " #source "\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + __res; \ }) #define __write_32bit_c0_register(register, sel, value) \ do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mtc0\t%z0, " #register "\n\t" \ - : : "Jr" (value)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mtc0\t%z0, " #register "\n\t" \ + : : "Jr" (value)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ } while (0) #define __write_64bit_c0_register(register, sel, value) \ do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmtc0\t%z0, " #register "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmtc0\t%z0, " #register "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ } while (0) #define __read_ulong_c0_register(reg, sel) \ - ((sizeof(unsigned long) == 4) ? \ - __read_32bit_c0_register(reg, sel) : \ - __read_64bit_c0_register(reg, sel)) + ((sizeof(unsigned long) == 4) ? \ + __read_32bit_c0_register(reg, sel) : \ + __read_64bit_c0_register(reg, sel)) #define __write_ulong_c0_register(reg, sel, val) \ do { \ - if (sizeof(unsigned long) == 4) \ - __write_32bit_c0_register(reg, sel, val); \ - else \ - __write_64bit_c0_register(reg, sel, val); \ + if (sizeof(unsigned long) == 4) \ + __write_32bit_c0_register(reg, sel, val); \ + else \ + __write_64bit_c0_register(reg, sel, val); \ } while (0) /* @@ -808,59 +766,59 @@ do { \ */ #define __read_64bit_c0_split(source, sel) \ ({ \ - unsigned long long val; \ - unsigned long flags; \ - \ - local_irq_save(flags); \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - ".set\tmips0" \ - : "=r" (val)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source ", " #sel "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - ".set\tmips0" \ - : "=r" (val)); \ - local_irq_restore(flags); \ - \ - val; \ + unsigned long long val; \ + unsigned long flags; \ + \ + local_irq_save(flags); \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%M0, " #source "\n\t" \ + "dsll\t%L0, %M0, 32\n\t" \ + "dsrl\t%M0, %M0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + ".set\tmips0" \ + : "=r" (val)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%M0, " #source ", " #sel "\n\t" \ + "dsll\t%L0, %M0, 32\n\t" \ + "dsrl\t%M0, %M0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + ".set\tmips0" \ + : "=r" (val)); \ + local_irq_restore(flags); \ + \ + val; \ }) #define __write_64bit_c0_split(source, sel, val) \ do { \ - unsigned long flags; \ - \ - local_irq_save(flags); \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dsll\t%L0, %L0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - "dsll\t%M0, %M0, 32\n\t" \ - "or\t%L0, %L0, %M0\n\t" \ - "dmtc0\t%L0, " #source "\n\t" \ - ".set\tmips0" \ - : : "r" (val)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dsll\t%L0, %L0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - "dsll\t%M0, %M0, 32\n\t" \ - "or\t%L0, %L0, %M0\n\t" \ - "dmtc0\t%L0, " #source ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "r" (val)); \ - local_irq_restore(flags); \ + unsigned long flags; \ + \ + local_irq_save(flags); \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, " #source "\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, " #source ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + local_irq_restore(flags); \ } while (0) #define read_c0_index() __read_32bit_c0_register($0, 0) @@ -906,6 +864,9 @@ do { \ #define read_c0_prid() __read_32bit_c0_register($15, 0) +#define read_c0_ebase() __read_32bit_c0_register($15, 1) +#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) + #define read_c0_config() __read_32bit_c0_register($16, 0) #define read_c0_config1() __read_32bit_c0_register($16, 1) #define read_c0_config2() __read_32bit_c0_register($16, 2) @@ -1001,20 +962,20 @@ do { \ #define read_32bit_cp0_register(source) \ ({ int __res; \ __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ "mfc0\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ + ".set\tpop" \ : "=r" (__res)); \ __res;}) #define read_32bit_cp0_set1_register(source) \ ({ int __res; \ __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ "cfc0\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ + ".set\tpop" \ : "=r" (__res)); \ __res;}) @@ -1033,13 +994,13 @@ do { \ #define write_32bit_cp0_register(register,value) \ __asm__ __volatile__( \ "mtc0\t%0,"STR(register)"\n\t" \ - "nop" \ + "nop" \ : : "r" (value)); #define write_32bit_cp0_set1_register(register,value) \ __asm__ __volatile__( \ - "ctc0\t%0,"STR(register)"\n\t" \ - "nop" \ + "ctc0\t%0,$"STR(register)"\n\t" \ + "nop" \ : : "r" (value)); #define write_64bit_cp0_register(register,value) \ @@ -1055,16 +1016,16 @@ do { \ #define read_mips32_cp0_config1() \ ({ int __res; \ __asm__ __volatile__( \ - ".set\tnoreorder\n\t" \ - ".set\tnoat\n\t" \ - "#.set\tmips64\n\t" \ - "#mfc0\t$1, $16, 1\n\t" \ - "#.set\tmips0\n\t" \ - ".word\t0x40018001\n\t" \ - "move\t%0,$1\n\t" \ - ".set\tat\n\t" \ - ".set\treorder" \ - :"=r" (__res)); \ + ".set\tnoreorder\n\t" \ + ".set\tnoat\n\t" \ + "#.set\tmips64\n\t" \ + "#mfc0\t$1, $16, 1\n\t" \ + "#.set\tmips0\n\t" \ + ".word\t0x40018001\n\t" \ + "move\t%0,$1\n\t" \ + ".set\tat\n\t" \ + ".set\treorder" \ + :"=r" (__res)); \ __res;}) #endif @@ -1073,45 +1034,51 @@ do { \ */ #define read_32bit_cp1_register(source) \ ({ int __res; \ - __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ - "cfc1\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + "cfc1\t%0,$"STR(source)"\n\t" \ + ".set\tpop" \ : "=r" (__res)); \ __res;}) +#define write_32bit_cp1_register(register,value) \ + __asm__ __volatile__( \ + "ctc1\t%0,$"STR(register)"\n\t" \ + "nop" \ + : : "r" (value)); + /* TLB operations. */ static inline void tlb_probe(void) { - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbp\n\t" - ".set reorder"); + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbp\n\t" + ".set reorder"); } static inline void tlb_read(void) { - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbr\n\t" - ".set reorder"); + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbr\n\t" + ".set reorder"); } static inline void tlb_write_indexed(void) { - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbwi\n\t" - ".set reorder"); + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbwi\n\t" + ".set reorder"); } static inline void tlb_write_random(void) { - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbwr\n\t" - ".set reorder"); + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbwr\n\t" + ".set reorder"); } /* @@ -1121,38 +1088,38 @@ static inline void tlb_write_random(void) static inline unsigned int \ set_c0_##name(unsigned int set) \ { \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res |= set; \ - write_c0_##name(res); \ - \ - return res; \ + unsigned int res; \ + \ + res = read_c0_##name(); \ + res |= set; \ + write_c0_##name(res); \ + \ + return res; \ } \ - \ + \ static inline unsigned int \ clear_c0_##name(unsigned int clear) \ { \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res &= ~clear; \ - write_c0_##name(res); \ - \ - return res; \ + unsigned int res; \ + \ + res = read_c0_##name(); \ + res &= ~clear; \ + write_c0_##name(res); \ + \ + return res; \ } \ - \ + \ static inline unsigned int \ change_c0_##name(unsigned int change, unsigned int new) \ { \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res &= ~change; \ - res |= (new & change); \ - write_c0_##name(res); \ - \ - return res; \ + unsigned int res; \ + \ + res = read_c0_##name(); \ + res &= ~change; \ + res |= (new & change); \ + write_c0_##name(res); \ + \ + return res; \ } __BUILD_SET_C0(status,CP0_STATUS) @@ -1163,6 +1130,17 @@ __BUILD_SET_C0(config,CP0_CONFIG) #define set_cp0_cause(x) set_c0_cause(x) #define set_cp0_config(x) set_c0_config(x) +#define read_c1_status() read_32bit_cp1_register(31) +#define write_c1_status(x) write_32bit_cp1_register(31, x) + +#define readb(reg) (*((volatile unsigned char *) (reg))) +#define readw(reg) (*((volatile unsigned short *) (reg))) +#define readl(reg) (*((volatile unsigned int *) (reg))) + +#define writeb(data, reg) ((*((volatile unsigned char *)(reg))) = (unsigned char)(data)) +#define writew(data, reg) ((*((volatile unsigned short *)(reg))) = (unsigned short)(data)) +#define writel(data, reg) ((*((volatile unsigned int *)(reg))) = (unsigned int)(data)) + #endif /* !__ASSEMBLY__ */ #endif /* _MIPS_REGS_H_ */ diff --git a/libcpu/mips/common/mips_types.h b/libcpu/mips/common/mips_types.h index 7f0b8a6855..cc12d44391 100644 --- a/libcpu/mips/common/mips_types.h +++ b/libcpu/mips/common/mips_types.h @@ -19,7 +19,7 @@ * * Change Logs: * Date Author Notes - * 2016��9��7�� Urey the first version + * 2016-09-07 Urey the first version */ #ifndef _MIPS_TYPES_H_ @@ -87,30 +87,17 @@ typedef unsigned long long u64; #endif -#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \ - || defined(CONFIG_64BIT) -typedef u64 dma_addr_t; - -typedef u64 phys_addr_t; -typedef u64 phys_size_t; - -#else typedef u32 dma_addr_t; typedef u32 phys_addr_t; typedef u32 phys_size_t; -#endif -typedef u64 dma64_addr_t; /* * Don't use phys_t. You've been warned. */ -#ifdef CONFIG_64BIT_PHYS_ADDR -typedef unsigned long long phys_t; -#else + typedef unsigned long phys_t; -#endif #endif /* __ASSEMBLY__ */ diff --git a/libcpu/mips/common/mipscfg.h b/libcpu/mips/common/mipscfg.h deleted file mode 100644 index b4f30615f8..0000000000 --- a/libcpu/mips/common/mipscfg.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * File : mipscfg.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-27 swkyer first version - */ -#ifndef __MIPSCFG_H__ -#define __MIPSCFG_H__ - - -typedef struct mips32_core_cfg -{ - rt_uint16_t icache_line_size; - rt_uint16_t icache_lines_per_way; - rt_uint16_t icache_ways; - rt_uint16_t dcache_line_size; - rt_uint16_t dcache_lines_per_way; - rt_uint16_t dcache_ways; - - rt_uint16_t max_tlb_entries; /* number of tlb entry */ -} mips32_core_cfg_t; - -extern mips32_core_cfg_t g_mips_core; - -#endif /* end of __MIPSCFG_H__ */ diff --git a/libcpu/mips/common/mipsregs.h b/libcpu/mips/common/mipsregs.h deleted file mode 100644 index 22e5754b8b..0000000000 --- a/libcpu/mips/common/mipsregs.h +++ /dev/null @@ -1,706 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle - * Copyright (C) 2000 Silicon Graphics, Inc. - * Modified for further R[236]000 support by Paul M. Antoine, 1996. - * Kevin D. Kissell, [email protected] and Carsten Langgaard, [email protected] - * Copyright (C) 2000, 07 MIPS Technologies, Inc. - * Copyright (C) 2003, 2004 Maciej W. Rozycki - * - * Change Logs: - * Date Author Notes - * - */ -#ifndef __MIPSREGS_H__ -#define __MIPSREGS_H__ - -/* - * The following macros are especially useful for __asm__ - * inline assembler. - */ -#ifndef __STR -#define __STR(x) #x -#endif -#ifndef STR -#define STR(x) __STR(x) -#endif - -/* - * Configure language - */ -#ifdef __ASSEMBLY__ -#define _ULCAST_ -#else -#define _ULCAST_ (unsigned long) -#endif - -/* - * Coprocessor 0 register names - */ -#define CP0_INDEX $0 -#define CP0_RANDOM $1 -#define CP0_ENTRYLO0 $2 -#define CP0_ENTRYLO1 $3 -#define CP0_CONF $3 -#define CP0_CONTEXT $4 -#define CP0_PAGEMASK $5 -#define CP0_WIRED $6 -#define CP0_INFO $7 -#define CP0_BADVADDR $8 -#define CP0_COUNT $9 -#define CP0_ENTRYHI $10 -#define CP0_COMPARE $11 -#define CP0_STATUS $12 -#define CP0_CAUSE $13 -#define CP0_EPC $14 -#define CP0_PRID $15 -#define CP0_CONFIG $16 -#define CP0_LLADDR $17 -#define CP0_WATCHLO $18 -#define CP0_WATCHHI $19 -#define CP0_XCONTEXT $20 -#define CP0_FRAMEMASK $21 -#define CP0_DIAGNOSTIC $22 -#define CP0_DEBUG $23 -#define CP0_DEPC $24 -#define CP0_PERFORMANCE $25 -#define CP0_ECC $26 -#define CP0_CACHEERR $27 -#define CP0_TAGLO $28 -#define CP0_TAGHI $29 -#define CP0_ERROREPC $30 -#define CP0_DESAVE $31 - -/* - * R4640/R4650 cp0 register names. These registers are listed - * here only for completeness; without MMU these CPUs are not useable - * by Linux. A future ELKS port might take make Linux run on them - * though ... - */ -#define CP0_IBASE $0 -#define CP0_IBOUND $1 -#define CP0_DBASE $2 -#define CP0_DBOUND $3 -#define CP0_CALG $17 -#define CP0_IWATCH $18 -#define CP0_DWATCH $19 - -/* - * Coprocessor 0 Set 1 register names - */ -#define CP0_S1_DERRADDR0 $26 -#define CP0_S1_DERRADDR1 $27 -#define CP0_S1_INTCONTROL $20 - -/* - * Coprocessor 0 Set 2 register names - */ -#define CP0_S2_SRSCTL $12 /* MIPSR2 */ - -/* - * Coprocessor 0 Set 3 register names - */ -#define CP0_S3_SRSMAP $12 /* MIPSR2 */ - -/* - * TX39 Series - */ -#define CP0_TX39_CACHE $7 - -/* - * Coprocessor 1 (FPU) register names - */ -#define CP1_REVISION $0 -#define CP1_STATUS $31 - -/* - * FPU Status Register Values - */ -/* - * Status Register Values - */ - -#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ -#define FPU_CSR_COND 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ -#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ -#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ -#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ -#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ -#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ -#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ - - -/* FS/FO/FN */ -#define FPU_CSR_FS 0x01000000 -#define FPU_CSR_FO 0x00400000 -#define FPU_CSR_FN 0x00200000 - -/* - * Bits 18 - 20 of the FPU Status Register will be read as 0, - * and should be written as zero. - */ -#define FPU_CSR_RSVD 0x001c0000 - -/* - * X the exception cause indicator - * E the exception enable - * S the sticky/flag bit -*/ -#define FPU_CSR_ALL_X 0x0003f000 -#define FPU_CSR_UNI_X 0x00020000 -#define FPU_CSR_INV_X 0x00010000 -#define FPU_CSR_DIV_X 0x00008000 -#define FPU_CSR_OVF_X 0x00004000 -#define FPU_CSR_UDF_X 0x00002000 -#define FPU_CSR_INE_X 0x00001000 - -#define FPU_CSR_ALL_E 0x00000f80 -#define FPU_CSR_INV_E 0x00000800 -#define FPU_CSR_DIV_E 0x00000400 -#define FPU_CSR_OVF_E 0x00000200 -#define FPU_CSR_UDF_E 0x00000100 -#define FPU_CSR_INE_E 0x00000080 - -#define FPU_CSR_ALL_S 0x0000007c -#define FPU_CSR_INV_S 0x00000040 -#define FPU_CSR_DIV_S 0x00000020 -#define FPU_CSR_OVF_S 0x00000010 -#define FPU_CSR_UDF_S 0x00000008 -#define FPU_CSR_INE_S 0x00000004 - -/* Bits 0 and 1 of FPU Status Register specify the rounding mode */ -#define FPU_CSR_RM 0x00000003 -#define FPU_CSR_RN 0x0 /* nearest */ -#define FPU_CSR_RZ 0x1 /* towards zero */ -#define FPU_CSR_RU 0x2 /* towards +Infinity */ -#define FPU_CSR_RD 0x3 /* towards -Infinity */ - - -/* - * R4x00 interrupt enable / cause bits - */ -#define IE_SW0 (_ULCAST_(1) << 8) -#define IE_SW1 (_ULCAST_(1) << 9) -#define IE_IRQ0 (_ULCAST_(1) << 10) -#define IE_IRQ1 (_ULCAST_(1) << 11) -#define IE_IRQ2 (_ULCAST_(1) << 12) -#define IE_IRQ3 (_ULCAST_(1) << 13) -#define IE_IRQ4 (_ULCAST_(1) << 14) -#define IE_IRQ5 (_ULCAST_(1) << 15) - -/* - * R4x00 interrupt cause bits - */ -#define C_SW0 (_ULCAST_(1) << 8) -#define C_SW1 (_ULCAST_(1) << 9) -#define C_IRQ0 (_ULCAST_(1) << 10) -#define C_IRQ1 (_ULCAST_(1) << 11) -#define C_IRQ2 (_ULCAST_(1) << 12) -#define C_IRQ3 (_ULCAST_(1) << 13) -#define C_IRQ4 (_ULCAST_(1) << 14) -#define C_IRQ5 (_ULCAST_(1) << 15) - -/* - * Bitfields in the R4xx0 cp0 status register - */ -#define ST0_IE 0x00000001 -#define ST0_EXL 0x00000002 -#define ST0_ERL 0x00000004 -#define ST0_KSU 0x00000018 -# define KSU_USER 0x00000010 -# define KSU_SUPERVISOR 0x00000008 -# define KSU_KERNEL 0x00000000 -#define ST0_UX 0x00000020 -#define ST0_SX 0x00000040 -#define ST0_KX 0x00000080 -#define ST0_DE 0x00010000 -#define ST0_CE 0x00020000 - -/* - * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate - * cacheops in userspace. This bit exists only on RM7000 and RM9000 - * processors. - */ -#define ST0_CO 0x08000000 - -/* - * Bitfields in the R[23]000 cp0 status register. - */ -#define ST0_IEC 0x00000001 -#define ST0_KUC 0x00000002 -#define ST0_IEP 0x00000004 -#define ST0_KUP 0x00000008 -#define ST0_IEO 0x00000010 -#define ST0_KUO 0x00000020 -/* bits 6 & 7 are reserved on R[23]000 */ -#define ST0_ISC 0x00010000 -#define ST0_SWC 0x00020000 -#define ST0_CM 0x00080000 - -/* - * Bits specific to the R4640/R4650 - */ -#define ST0_UM (_ULCAST_(1) << 4) -#define ST0_IL (_ULCAST_(1) << 23) -#define ST0_DL (_ULCAST_(1) << 24) - -/* - * Enable the MIPS DSP ASE - */ -#define ST0_MX 0x01000000 - -/* - * Bitfields in the TX39 family CP0 Configuration Register 3 - */ -#define TX39_CONF_ICS_SHIFT 19 -#define TX39_CONF_ICS_MASK 0x00380000 -#define TX39_CONF_ICS_1KB 0x00000000 -#define TX39_CONF_ICS_2KB 0x00080000 -#define TX39_CONF_ICS_4KB 0x00100000 -#define TX39_CONF_ICS_8KB 0x00180000 -#define TX39_CONF_ICS_16KB 0x00200000 - -#define TX39_CONF_DCS_SHIFT 16 -#define TX39_CONF_DCS_MASK 0x00070000 -#define TX39_CONF_DCS_1KB 0x00000000 -#define TX39_CONF_DCS_2KB 0x00010000 -#define TX39_CONF_DCS_4KB 0x00020000 -#define TX39_CONF_DCS_8KB 0x00030000 -#define TX39_CONF_DCS_16KB 0x00040000 - -#define TX39_CONF_CWFON 0x00004000 -#define TX39_CONF_WBON 0x00002000 -#define TX39_CONF_RF_SHIFT 10 -#define TX39_CONF_RF_MASK 0x00000c00 -#define TX39_CONF_DOZE 0x00000200 -#define TX39_CONF_HALT 0x00000100 -#define TX39_CONF_LOCK 0x00000080 -#define TX39_CONF_ICE 0x00000020 -#define TX39_CONF_DCE 0x00000010 -#define TX39_CONF_IRSIZE_SHIFT 2 -#define TX39_CONF_IRSIZE_MASK 0x0000000c -#define TX39_CONF_DRSIZE_SHIFT 0 -#define TX39_CONF_DRSIZE_MASK 0x00000003 - -/* - * Status register bits available in all MIPS CPUs. - */ -#define ST0_IM 0x0000ff00 -#define STATUSB_IP0 8 -#define STATUSF_IP0 (_ULCAST_(1) << 8) -#define STATUSB_IP1 9 -#define STATUSF_IP1 (_ULCAST_(1) << 9) -#define STATUSB_IP2 10 -#define STATUSF_IP2 (_ULCAST_(1) << 10) -#define STATUSB_IP3 11 -#define STATUSF_IP3 (_ULCAST_(1) << 11) -#define STATUSB_IP4 12 -#define STATUSF_IP4 (_ULCAST_(1) << 12) -#define STATUSB_IP5 13 -#define STATUSF_IP5 (_ULCAST_(1) << 13) -#define STATUSB_IP6 14 -#define STATUSF_IP6 (_ULCAST_(1) << 14) -#define STATUSB_IP7 15 -#define STATUSF_IP7 (_ULCAST_(1) << 15) -#define STATUSB_IP8 0 -#define STATUSF_IP8 (_ULCAST_(1) << 0) -#define STATUSB_IP9 1 -#define STATUSF_IP9 (_ULCAST_(1) << 1) -#define STATUSB_IP10 2 -#define STATUSF_IP10 (_ULCAST_(1) << 2) -#define STATUSB_IP11 3 -#define STATUSF_IP11 (_ULCAST_(1) << 3) -#define STATUSB_IP12 4 -#define STATUSF_IP12 (_ULCAST_(1) << 4) -#define STATUSB_IP13 5 -#define STATUSF_IP13 (_ULCAST_(1) << 5) -#define STATUSB_IP14 6 -#define STATUSF_IP14 (_ULCAST_(1) << 6) -#define STATUSB_IP15 7 -#define STATUSF_IP15 (_ULCAST_(1) << 7) -#define ST0_CH 0x00040000 -#define ST0_SR 0x00100000 -#define ST0_TS 0x00200000 -#define ST0_BEV 0x00400000 -#define ST0_RE 0x02000000 -#define ST0_FR 0x04000000 -#define ST0_CU 0xf0000000 -#define ST0_CU0 0x10000000 -#define ST0_CU1 0x20000000 -#define ST0_CU2 0x40000000 -#define ST0_CU3 0x80000000 -#define ST0_XX 0x80000000 /* MIPS IV naming */ - -/* - * Bitfields and bit numbers in the coprocessor 0 cause register. - * - * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. - */ -#define CAUSEB_EXCCODE 2 -#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) -#define CAUSEB_IP 8 -#define CAUSEF_IP (_ULCAST_(255) << 8) -#define CAUSEB_IP0 8 -#define CAUSEF_IP0 (_ULCAST_(1) << 8) -#define CAUSEB_IP1 9 -#define CAUSEF_IP1 (_ULCAST_(1) << 9) -#define CAUSEB_IP2 10 -#define CAUSEF_IP2 (_ULCAST_(1) << 10) -#define CAUSEB_IP3 11 -#define CAUSEF_IP3 (_ULCAST_(1) << 11) -#define CAUSEB_IP4 12 -#define CAUSEF_IP4 (_ULCAST_(1) << 12) -#define CAUSEB_IP5 13 -#define CAUSEF_IP5 (_ULCAST_(1) << 13) -#define CAUSEB_IP6 14 -#define CAUSEF_IP6 (_ULCAST_(1) << 14) -#define CAUSEB_IP7 15 -#define CAUSEF_IP7 (_ULCAST_(1) << 15) -#define CAUSEB_IV 23 -#define CAUSEF_IV (_ULCAST_(1) << 23) -#define CAUSEB_CE 28 -#define CAUSEF_CE (_ULCAST_(3) << 28) -#define CAUSEB_BD 31 -#define CAUSEF_BD (_ULCAST_(1) << 31) - -/* - * Bits in the coprocessor 0 config register. - */ -/* Generic bits. */ -#define CONF_CM_CACHABLE_NO_WA 0 -#define CONF_CM_CACHABLE_WA 1 -#define CONF_CM_UNCACHED 2 -#define CONF_CM_CACHABLE_NONCOHERENT 3 -#define CONF_CM_CACHABLE_CE 4 -#define CONF_CM_CACHABLE_COW 5 -#define CONF_CM_CACHABLE_CUW 6 -#define CONF_CM_CACHABLE_ACCELERATED 7 -#define CONF_CM_CMASK 7 -#define CONF_BE (_ULCAST_(1) << 15) - -/* Bits common to various processors. */ -#define CONF_CU (_ULCAST_(1) << 3) -#define CONF_DB (_ULCAST_(1) << 4) -#define CONF_IB (_ULCAST_(1) << 5) -#define CONF_DC (_ULCAST_(7) << 6) -#define CONF_IC (_ULCAST_(7) << 9) -#define CONF_EB (_ULCAST_(1) << 13) -#define CONF_EM (_ULCAST_(1) << 14) -#define CONF_SM (_ULCAST_(1) << 16) -#define CONF_SC (_ULCAST_(1) << 17) -#define CONF_EW (_ULCAST_(3) << 18) -#define CONF_EP (_ULCAST_(15)<< 24) -#define CONF_EC (_ULCAST_(7) << 28) -#define CONF_CM (_ULCAST_(1) << 31) - -/* Bits specific to the R4xx0. */ -#define R4K_CONF_SW (_ULCAST_(1) << 20) -#define R4K_CONF_SS (_ULCAST_(1) << 21) -#define R4K_CONF_SB (_ULCAST_(3) << 22) - -/* Bits specific to the R5000. */ -#define R5K_CONF_SE (_ULCAST_(1) << 12) -#define R5K_CONF_SS (_ULCAST_(3) << 20) - -/* Bits specific to the RM7000. */ -#define RM7K_CONF_SE (_ULCAST_(1) << 3) -#define RM7K_CONF_TE (_ULCAST_(1) << 12) -#define RM7K_CONF_CLK (_ULCAST_(1) << 16) -#define RM7K_CONF_TC (_ULCAST_(1) << 17) -#define RM7K_CONF_SI (_ULCAST_(3) << 20) -#define RM7K_CONF_SC (_ULCAST_(1) << 31) - -/* Bits specific to the R10000. */ -#define R10K_CONF_DN (_ULCAST_(3) << 3) -#define R10K_CONF_CT (_ULCAST_(1) << 5) -#define R10K_CONF_PE (_ULCAST_(1) << 6) -#define R10K_CONF_PM (_ULCAST_(3) << 7) -#define R10K_CONF_EC (_ULCAST_(15)<< 9) -#define R10K_CONF_SB (_ULCAST_(1) << 13) -#define R10K_CONF_SK (_ULCAST_(1) << 14) -#define R10K_CONF_SS (_ULCAST_(7) << 16) -#define R10K_CONF_SC (_ULCAST_(7) << 19) -#define R10K_CONF_DC (_ULCAST_(7) << 26) -#define R10K_CONF_IC (_ULCAST_(7) << 29) - -/* Bits specific to the VR41xx. */ -#define VR41_CONF_CS (_ULCAST_(1) << 12) -#define VR41_CONF_M16 (_ULCAST_(1) << 20) -#define VR41_CONF_AD (_ULCAST_(1) << 23) - -/* Bits specific to the R30xx. */ -#define R30XX_CONF_FDM (_ULCAST_(1) << 19) -#define R30XX_CONF_REV (_ULCAST_(1) << 22) -#define R30XX_CONF_AC (_ULCAST_(1) << 23) -#define R30XX_CONF_RF (_ULCAST_(1) << 24) -#define R30XX_CONF_HALT (_ULCAST_(1) << 25) -#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) -#define R30XX_CONF_DBR (_ULCAST_(1) << 29) -#define R30XX_CONF_SB (_ULCAST_(1) << 30) -#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) - -/* Bits specific to the TX49. */ -#define TX49_CONF_DC (_ULCAST_(1) << 16) -#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ -#define TX49_CONF_HALT (_ULCAST_(1) << 18) -#define TX49_CONF_CWFON (_ULCAST_(1) << 27) - -/* Bits specific to the MIPS32/64 PRA. */ -#define MIPS_CONF_MT (_ULCAST_(7) << 7) -#define MIPS_CONF_AR (_ULCAST_(7) << 10) -#define MIPS_CONF_AT (_ULCAST_(3) << 13) -#define MIPS_CONF_M (_ULCAST_(1) << 31) - -/* - * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. - */ -#define MIPS_CONF1_FP (_ULCAST_(1) << 0) -#define MIPS_CONF1_EP (_ULCAST_(1) << 1) -#define MIPS_CONF1_CA (_ULCAST_(1) << 2) -#define MIPS_CONF1_WR (_ULCAST_(1) << 3) -#define MIPS_CONF1_PC (_ULCAST_(1) << 4) -#define MIPS_CONF1_MD (_ULCAST_(1) << 5) -#define MIPS_CONF1_C2 (_ULCAST_(1) << 6) -#define MIPS_CONF1_DA (_ULCAST_(7) << 7) -#define MIPS_CONF1_DL (_ULCAST_(7) << 10) -#define MIPS_CONF1_DS (_ULCAST_(7) << 13) -#define MIPS_CONF1_IA (_ULCAST_(7) << 16) -#define MIPS_CONF1_IL (_ULCAST_(7) << 19) -#define MIPS_CONF1_IS (_ULCAST_(7) << 22) -#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) - -#define MIPS_CONF2_SA (_ULCAST_(15)<< 0) -#define MIPS_CONF2_SL (_ULCAST_(15)<< 4) -#define MIPS_CONF2_SS (_ULCAST_(15)<< 8) -#define MIPS_CONF2_SU (_ULCAST_(15)<< 12) -#define MIPS_CONF2_TA (_ULCAST_(15)<< 16) -#define MIPS_CONF2_TL (_ULCAST_(15)<< 20) -#define MIPS_CONF2_TS (_ULCAST_(15)<< 24) -#define MIPS_CONF2_TU (_ULCAST_(7) << 28) - -#define MIPS_CONF3_TL (_ULCAST_(1) << 0) -#define MIPS_CONF3_SM (_ULCAST_(1) << 1) -#define MIPS_CONF3_MT (_ULCAST_(1) << 2) -#define MIPS_CONF3_SP (_ULCAST_(1) << 4) -#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) -#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) -#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) -#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) - -/* - * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. - */ -#define MIPS_FPIR_S (_ULCAST_(1) << 16) -#define MIPS_FPIR_D (_ULCAST_(1) << 17) -#define MIPS_FPIR_PS (_ULCAST_(1) << 18) -#define MIPS_FPIR_3D (_ULCAST_(1) << 19) -#define MIPS_FPIR_W (_ULCAST_(1) << 20) -#define MIPS_FPIR_L (_ULCAST_(1) << 21) -#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) - -/* - * R10000 performance counter definitions. - * - * FIXME: The R10000 performance counter opens a nice way to implement CPU - * time accounting with a precission of one cycle. I don't have - * R10000 silicon but just a manual, so ... - */ - -/* - * Events counted by counter #0 - */ -#define CE0_CYCLES 0 -#define CE0_INSN_ISSUED 1 -#define CE0_LPSC_ISSUED 2 -#define CE0_S_ISSUED 3 -#define CE0_SC_ISSUED 4 -#define CE0_SC_FAILED 5 -#define CE0_BRANCH_DECODED 6 -#define CE0_QW_WB_SECONDARY 7 -#define CE0_CORRECTED_ECC_ERRORS 8 -#define CE0_ICACHE_MISSES 9 -#define CE0_SCACHE_I_MISSES 10 -#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 -#define CE0_EXT_INTERVENTIONS_REQ 12 -#define CE0_EXT_INVALIDATE_REQ 13 -#define CE0_VIRTUAL_COHERENCY_COND 14 -#define CE0_INSN_GRADUATED 15 - -/* - * Events counted by counter #1 - */ -#define CE1_CYCLES 0 -#define CE1_INSN_GRADUATED 1 -#define CE1_LPSC_GRADUATED 2 -#define CE1_S_GRADUATED 3 -#define CE1_SC_GRADUATED 4 -#define CE1_FP_INSN_GRADUATED 5 -#define CE1_QW_WB_PRIMARY 6 -#define CE1_TLB_REFILL 7 -#define CE1_BRANCH_MISSPREDICTED 8 -#define CE1_DCACHE_MISS 9 -#define CE1_SCACHE_D_MISSES 10 -#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 -#define CE1_EXT_INTERVENTION_HITS 12 -#define CE1_EXT_INVALIDATE_REQ 13 -#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 -#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 - -/* - * These flags define in which privilege mode the counters count events - */ -#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ -#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ -#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ -#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ - - -#ifndef __ASSEMBLY__ - -/* - * Macros to access the system control coprocessor - */ -#define __read_32bit_c0_register(source, sel) \ -({ int __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mfc0\t%0, " #source "\n\t" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__res)); \ - __res; \ -}) - -#define __write_32bit_c0_register(register, sel, value) \ -do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mtc0\t%z0, " #register "\n\t" \ - : : "Jr" ((unsigned int)(value))); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" ((unsigned int)(value))); \ -} while (0) - -#define read_c0_index() __read_32bit_c0_register($0, 0) -#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) - -#define read_c0_random() __read_32bit_c0_register($1, 0) -#define write_c0_random(val) __write_32bit_c0_register($1, 0, val) - -#define read_c0_entrylo0() __read_32bit_c0_register($2, 0) -#define write_c0_entrylo0(val) __write_32bit_c0_register($2, 0, val) - -#define read_c0_entrylo1() __read_32bit_c0_register($3, 0) -#define write_c0_entrylo1(val) __write_32bit_c0_register($3, 0, val) - -#define read_c0_conf() __read_32bit_c0_register($3, 0) -#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) - -#define read_c0_context() __read_32bit_c0_register($4, 0) -#define write_c0_context(val) __write_32bit_c0_register($4, 0, val) - -#define read_c0_userlocal() __read_32bit_c0_register($4, 2) -#define write_c0_userlocal(val) __write_32bit_c0_register($4, 2, val) - -#define read_c0_pagemask() __read_32bit_c0_register($5, 0) -#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) - -#define read_c0_wired() __read_32bit_c0_register($6, 0) -#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) - -#define read_c0_info() __read_32bit_c0_register($7, 0) - -#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ -#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) - -#define read_c0_badvaddr() __read_32bit_c0_register($8, 0) -#define write_c0_badvaddr(val) __write_32bit_c0_register($8, 0, val) - -#define read_c0_count() __read_32bit_c0_register($9, 0) -#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) - -#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ -#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) - -#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ -#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) - -#define read_c0_entryhi() __read_32bit_c0_register($10, 0) -#define write_c0_entryhi(val) __write_32bit_c0_register($10, 0, val) - -#define read_c0_compare() __read_32bit_c0_register($11, 0) -#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) - -#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ -#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) - -#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ -#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) - -#define read_c0_status() __read_32bit_c0_register($12, 0) -#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) - -#define read_c0_cause() __read_32bit_c0_register($13, 0) -#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) - -#define read_c0_epc() __read_32bit_c0_register($14, 0) -#define write_c0_epc(val) __write_32bit_c0_register($14, 0, val) - -#define read_c0_prid() __read_32bit_c0_register($15, 0) - -#define read_c0_ebase() __read_32bit_c0_register($15, 1) -#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) - -#define read_c0_config() __read_32bit_c0_register($16, 0) -#define read_c0_config1() __read_32bit_c0_register($16, 1) -#define read_c0_config2() __read_32bit_c0_register($16, 2) -#define read_c0_config3() __read_32bit_c0_register($16, 3) -#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) -#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) -#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) -#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) - - -/* - * Macros to access the floating point coprocessor control registers - */ -#define read_32bit_cp1_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ - /* gas fails to assemble cfc1 for some archs (octeon).*/ \ - ".set\tmips1\n\t" \ - "cfc1\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ - : "=r" (__res)); \ - __res;}) -#define write_32bit_cp1_register(register, value) \ -do { \ - __asm__ __volatile__( \ - "ctc1\t%z0, "STR(register)"\n\t" \ - : : "Jr" ((unsigned int)(value))); \ -} while (0) - -#define read_c1_status() read_32bit_cp1_register(CP1_STATUS) -#define read_c1_revision() read_32bit_cp1_register(CP1_REVISION); -#define write_c1_status(val) write_32bit_cp1_register(CP1_STATUS, val) - - -#endif /* end of __ASSEMBLY__ */ - -#endif /* end of __MIPSREGS_H__ */ - diff --git a/libcpu/mips/common/ptrace.h b/libcpu/mips/common/ptrace.h new file mode 100644 index 0000000000..00ce58a085 --- /dev/null +++ b/libcpu/mips/common/ptrace.h @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + */ + +#ifndef _MIPS_PTRACE_H +#define _MIPS_PTRACE_H + +#include "asm.h" +#include "mips_regs.h" + +#define HI_LO_SIZE 4 + +#define FP_REG_SIZE 8 +#define NUM_FPU_REGS 16 + +#ifndef __ASSEMBLY__ +#include <rtthread.h> + +struct mips_fpu_struct { + rt_uint64_t fpr[NUM_FPU_REGS]; + rt_uint32_t fcr31; + rt_uint32_t pad; +}; + +struct pt_regs { +#ifndef ARCH_MIPS64 + /* Only O32 Need This! */ + /* Pad bytes for argument save space on the stack. */ + rt_uint32_t pad0[8]; + + /* Saved main processor registers. */ + rt_uint32_t regs[32]; + + /* Saved special registers. */ + rt_uint32_t cp0_status; + rt_uint32_t hi; + rt_uint32_t lo; + rt_uint32_t cp0_badvaddr; + rt_uint32_t cp0_cause; + rt_uint32_t cp0_epc; +#else + /* Saved main processor registers. */ + unsigned long regs[32]; + + /* Saved special registers. */ + rt_uint32_t cp0_status; + rt_uint32_t hi; + rt_uint32_t lo; + unsigned long cp0_badvaddr; + rt_uint32_t cp0_cause; + unsigned long cp0_epc; +#endif + +#ifdef RT_USING_FPU + /* FPU Registers */ + /* Unlike Linux Kernel, we save these registers unconditionally, + * so it should be a part of pt_regs */ + struct mips_fpu_struct fpu; +#endif +} __aligned(8); +#endif + +/* Note: For call stack o32 ABI has 0x8 shadowsoace Here */ +#ifdef ARCH_MIPS64 +#define PT_R0 (0x0 * LONGSIZE) /* 0 */ +#else +#define PT_R0 (0x8 * LONGSIZE) /* 0 */ +#endif +#define PT_R1 ((PT_R0) + LONGSIZE) /* 1 */ +#define PT_R2 ((PT_R1) + LONGSIZE) /* 2 */ +#define PT_R3 ((PT_R2) + LONGSIZE) /* 3 */ +#define PT_R4 ((PT_R3) + LONGSIZE) /* 4 */ +#define PT_R5 ((PT_R4) + LONGSIZE) /* 5 */ +#define PT_R6 ((PT_R5) + LONGSIZE) /* 6 */ +#define PT_R7 ((PT_R6) + LONGSIZE) /* 7 */ +#define PT_R8 ((PT_R7) + LONGSIZE) /* 8 */ +#define PT_R9 ((PT_R8) + LONGSIZE) /* 9 */ +#define PT_R10 ((PT_R9) + LONGSIZE) /* 10 */ +#define PT_R11 ((PT_R10) + LONGSIZE) /* 11 */ +#define PT_R12 ((PT_R11) + LONGSIZE) /* 12 */ +#define PT_R13 ((PT_R12) + LONGSIZE) /* 13 */ +#define PT_R14 ((PT_R13) + LONGSIZE) /* 14 */ +#define PT_R15 ((PT_R14) + LONGSIZE) /* 15 */ +#define PT_R16 ((PT_R15) + LONGSIZE) /* 16 */ +#define PT_R17 ((PT_R16) + LONGSIZE) /* 17 */ +#define PT_R18 ((PT_R17) + LONGSIZE) /* 18 */ +#define PT_R19 ((PT_R18) + LONGSIZE) /* 19 */ +#define PT_R20 ((PT_R19) + LONGSIZE) /* 20 */ +#define PT_R21 ((PT_R20) + LONGSIZE) /* 21 */ +#define PT_R22 ((PT_R21) + LONGSIZE) /* 22 */ +#define PT_R23 ((PT_R22) + LONGSIZE) /* 23 */ +#define PT_R24 ((PT_R23) + LONGSIZE) /* 24 */ +#define PT_R25 ((PT_R24) + LONGSIZE) /* 25 */ +#define PT_R26 ((PT_R25) + LONGSIZE) /* 26 */ +#define PT_R27 ((PT_R26) + LONGSIZE) /* 27 */ +#define PT_R28 ((PT_R27) + LONGSIZE) /* 28 */ +#define PT_R29 ((PT_R28) + LONGSIZE) /* 29 */ +#define PT_R30 ((PT_R29) + LONGSIZE) /* 30 */ +#define PT_R31 ((PT_R30) + LONGSIZE) /* 31 */ + +/* + * Saved special registers + */ +#define PT_STATUS ((PT_R31) + LONGSIZE) /* 32 */ +#define PT_HI ((PT_STATUS) + HI_LO_SIZE) /* 33 */ +#define PT_LO ((PT_HI) + HI_LO_SIZE) /* 34 */ +#define PT_BADVADDR ((PT_LO) + LONGSIZE) /* 35 */ +#define PT_CAUSE ((PT_BADVADDR) + LONGSIZE) /* 36 */ +#define PT_EPC ((PT_CAUSE) + LONGSIZE) /* 37 */ + +#define PT_REG_END ((PT_EPC) + LONGSIZE) /* Align already ensured manually */ + +#ifdef RT_USING_FPU +#define PT_FPU_R0 (PT_REG_END) +#define PT_FPU_R2 ((PT_FPU_R0) + FP_REG_SIZE) +#define PT_FPU_R4 ((PT_FPU_R2) + FP_REG_SIZE) +#define PT_FPU_R6 ((PT_FPU_R4) + FP_REG_SIZE) +#define PT_FPU_R8 ((PT_FPU_R6) + FP_REG_SIZE) +#define PT_FPU_R10 ((PT_FPU_R8) + FP_REG_SIZE) +#define PT_FPU_R12 ((PT_FPU_R10) + FP_REG_SIZE) +#define PT_FPU_R14 ((PT_FPU_R12) + FP_REG_SIZE) +#define PT_FPU_R16 ((PT_FPU_R14) + FP_REG_SIZE) +#define PT_FPU_R18 ((PT_FPU_R16) + FP_REG_SIZE) +#define PT_FPU_R20 ((PT_FPU_R18) + FP_REG_SIZE) +#define PT_FPU_R22 ((PT_FPU_R20) + FP_REG_SIZE) +#define PT_FPU_R24 ((PT_FPU_R22) + FP_REG_SIZE) +#define PT_FPU_R26 ((PT_FPU_R24) + FP_REG_SIZE) +#define PT_FPU_R28 ((PT_FPU_R26) + FP_REG_SIZE) +#define PT_FPU_R30 ((PT_FPU_R28) + FP_REG_SIZE) +#define PT_FPU_FCSR31 ((PT_FPU_R30) + FP_REG_SIZE) +#define PT_FPU_PAD0 ((PT_FPU_FCSR31) + 4) + +#define PT_FPU_END ((PT_FPU_PAD0) + 4) +#define PT_SIZE PT_FPU_END +#else +#define PT_SIZE PT_REG_END +#endif + +#endif
\ No newline at end of file diff --git a/libcpu/mips/common/stack.c b/libcpu/mips/common/stack.c new file mode 100644 index 0000000000..b933b184e7 --- /dev/null +++ b/libcpu/mips/common/stack.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + */ + +#include <rtthread.h> + +#include "mips.h" + +register rt_uint32_t $GP __asm__ ("$28"); + +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) +{ + static rt_ubase_t wSR=0; + static rt_ubase_t wGP; + rt_uint8_t *stk; + + struct pt_regs *pt; + + rt_uint32_t i; + + /* Get stack aligned */ + stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stack_addr, 8); + stk -= sizeof(struct pt_regs); + pt = (struct pt_regs*)stk; + +#ifndef ARCH_MIPS64 + for (i = 0; i < 8; ++i) + { + pt->pad0[i] = 0xdeadbeef; + } +#endif + /* Fill Stack register numbers */ + for (i = 0; i < 32; ++i) + { + pt->regs[i] = 0xdeadbeef; + } + + pt->regs[REG_SP] = (rt_ubase_t)stk; + pt->regs[REG_A0] = (rt_ubase_t)parameter; + pt->regs[REG_GP] = (rt_ubase_t)$GP; + pt->regs[REG_FP] = (rt_ubase_t)0x0; + pt->regs[REG_RA] = (rt_ubase_t)texit; + + pt->hi = 0x0; + pt->lo = 0x0; + pt->cp0_status = (ST0_IE | ST0_CU0 | ST0_IM); +#ifdef RT_USING_FPU + pt->cp0_status |= (ST0_CU1 | ST0_FR); +#endif + pt->cp0_cause = read_c0_cause(); + pt->cp0_epc = (rt_ubase_t)tentry; + pt->cp0_badvaddr = 0x0; + + return stk; +} diff --git a/libcpu/mips/common/stackframe.h b/libcpu/mips/common/stackframe.h index 96b69ab14f..bb92a18c9c 100644 --- a/libcpu/mips/common/stackframe.h +++ b/libcpu/mips/common/stackframe.h @@ -1,228 +1,256 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. + * Copyright (c) 2006-2019, RT-Thread Development Team * - * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle - * Copyright (C) 1994, 1995, 1996 Paul M. Antoine. - * Copyright (C) 1999 Silicon Graphics, Inc. - * Copyright (C) 2007 Maciej W. Rozycki + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version */ + #ifndef __STACKFRAME_H__ #define __STACKFRAME_H__ #include "asm.h" -#include "mipsregs.h" - -/* - * Stack layout for the INT exception handler - * Derived from the stack layout described in asm-mips/stackframe.h - * - * The first PTRSIZE*6 bytes are argument save space for C subroutines. - */ - -//#define PT_R0 (PTRSIZE*6) /* 0 */ -#define PT_R0 (0) /* 0 */ -#define PT_R1 ((PT_R0) + LONGSIZE) /* 1 */ -#define PT_R2 ((PT_R1) + LONGSIZE) /* 2 */ -#define PT_R3 ((PT_R2) + LONGSIZE) /* 3 */ -#define PT_R4 ((PT_R3) + LONGSIZE) /* 4 */ -#define PT_R5 ((PT_R4) + LONGSIZE) /* 5 */ -#define PT_R6 ((PT_R5) + LONGSIZE) /* 6 */ -#define PT_R7 ((PT_R6) + LONGSIZE) /* 7 */ -#define PT_R8 ((PT_R7) + LONGSIZE) /* 8 */ -#define PT_R9 ((PT_R8) + LONGSIZE) /* 9 */ -#define PT_R10 ((PT_R9) + LONGSIZE) /* 10 */ -#define PT_R11 ((PT_R10) + LONGSIZE) /* 11 */ -#define PT_R12 ((PT_R11) + LONGSIZE) /* 12 */ -#define PT_R13 ((PT_R12) + LONGSIZE) /* 13 */ -#define PT_R14 ((PT_R13) + LONGSIZE) /* 14 */ -#define PT_R15 ((PT_R14) + LONGSIZE) /* 15 */ -#define PT_R16 ((PT_R15) + LONGSIZE) /* 16 */ -#define PT_R17 ((PT_R16) + LONGSIZE) /* 17 */ -#define PT_R18 ((PT_R17) + LONGSIZE) /* 18 */ -#define PT_R19 ((PT_R18) + LONGSIZE) /* 19 */ -#define PT_R20 ((PT_R19) + LONGSIZE) /* 20 */ -#define PT_R21 ((PT_R20) + LONGSIZE) /* 21 */ -#define PT_R22 ((PT_R21) + LONGSIZE) /* 22 */ -#define PT_R23 ((PT_R22) + LONGSIZE) /* 23 */ -#define PT_R24 ((PT_R23) + LONGSIZE) /* 24 */ -#define PT_R25 ((PT_R24) + LONGSIZE) /* 25 */ -#define PT_R26 ((PT_R25) + LONGSIZE) /* 26 */ -#define PT_R27 ((PT_R26) + LONGSIZE) /* 27 */ -#define PT_R28 ((PT_R27) + LONGSIZE) /* 28 */ -#define PT_R29 ((PT_R28) + LONGSIZE) /* 29 */ -#define PT_R30 ((PT_R29) + LONGSIZE) /* 30 */ -#define PT_R31 ((PT_R30) + LONGSIZE) /* 31 */ - -/* - * Saved special registers - */ -#define PT_STATUS ((PT_R31) + LONGSIZE) /* 32 */ -#define PT_HI ((PT_STATUS) + LONGSIZE) /* 33 */ -#define PT_LO ((PT_HI) + LONGSIZE) /* 34 */ -#define PT_BADVADDR ((PT_LO) + LONGSIZE) /* 35 */ -#define PT_CAUSE ((PT_BADVADDR) + LONGSIZE) /* 36 */ -#define PT_EPC ((PT_CAUSE) + LONGSIZE) /* 37 */ +#include "mips_regs.h" +#include "ptrace.h" -#define PT_SIZE ((((PT_EPC) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1)) +/* You MUST ensure FP is enabled before SAVE_FPU! */ + .macro SAVE_FPU + .set push + .set noreorder +#ifdef RT_USING_FPU + /* Ensure CU1 (FPU) is enabled */ + MFC0 v1, CP0_STATUS + lui t1, %hi(ST0_CU1) + addiu t1, t1, %lo(ST0_CU1) + or v1, v1, t1 + MTC0 v1, CP0_STATUS + SSNOP + cfc1 v1, fcr31 + /* Store as delay slot */ + s.d $f0, PT_FPU_R0(sp) + s.d $f2, PT_FPU_R2(sp) + s.d $f4, PT_FPU_R4(sp) + s.d $f6, PT_FPU_R6(sp) + s.d $f8, PT_FPU_R8(sp) + s.d $f10, PT_FPU_R10(sp) + s.d $f12, PT_FPU_R12(sp) + s.d $f14, PT_FPU_R14(sp) + s.d $f16, PT_FPU_R16(sp) + s.d $f18, PT_FPU_R18(sp) + s.d $f20, PT_FPU_R20(sp) + s.d $f22, PT_FPU_R22(sp) + s.d $f24, PT_FPU_R24(sp) + s.d $f26, PT_FPU_R26(sp) + s.d $f28, PT_FPU_R28(sp) + s.d $f30, PT_FPU_R30(sp) + LONG_S v1, PT_FPU_FCSR31(sp) +#endif + .set reorder + .set pop + .endm + .macro SAVE_AT + .set push + .set noat + LONG_S $1, PT_R1(sp) + .set pop + .endm - .macro SAVE_AT - .set push - .set noat - LONG_S $1, PT_R1(sp) - .set pop - .endm + .macro SAVE_TEMP + mfhi v1 + LONG_S $8, PT_R8(sp) + LONG_S $9, PT_R9(sp) + sw v1, PT_HI(sp) + mflo v1 + LONG_S $10, PT_R10(sp) + LONG_S $11, PT_R11(sp) + sw v1, PT_LO(sp) + LONG_S $12, PT_R12(sp) + LONG_S $13, PT_R13(sp) + LONG_S $14, PT_R14(sp) + LONG_S $15, PT_R15(sp) + LONG_S $24, PT_R24(sp) + .endm - .macro SAVE_TEMP - mfhi v1 - LONG_S $8, PT_R8(sp) - LONG_S $9, PT_R9(sp) - LONG_S v1, PT_HI(sp) - mflo v1 - LONG_S $10, PT_R10(sp) - LONG_S $11, PT_R11(sp) - LONG_S v1, PT_LO(sp) - LONG_S $12, PT_R12(sp) - LONG_S $13, PT_R13(sp) - LONG_S $14, PT_R14(sp) - LONG_S $15, PT_R15(sp) - LONG_S $24, PT_R24(sp) - .endm + .macro SAVE_STATIC + LONG_S $16, PT_R16(sp) + LONG_S $17, PT_R17(sp) + LONG_S $18, PT_R18(sp) + LONG_S $19, PT_R19(sp) + LONG_S $20, PT_R20(sp) + LONG_S $21, PT_R21(sp) + LONG_S $22, PT_R22(sp) + LONG_S $23, PT_R23(sp) + LONG_S $30, PT_R30(sp) + .endm - .macro SAVE_STATIC - LONG_S $16, PT_R16(sp) - LONG_S $17, PT_R17(sp) - LONG_S $18, PT_R18(sp) - LONG_S $19, PT_R19(sp) - LONG_S $20, PT_R20(sp) - LONG_S $21, PT_R21(sp) - LONG_S $22, PT_R22(sp) - LONG_S $23, PT_R23(sp) - LONG_S $30, PT_R30(sp) - .endm + .macro SAVE_SOME + .set push + .set noat + .set reorder + move k1, sp + move k0, sp + PTR_SUBU sp, k1, PT_SIZE + LONG_S k0, PT_R29(sp) + LONG_S $3, PT_R3(sp) + LONG_S $0, PT_R0(sp) + MFC0 v1, CP0_STATUS + LONG_S $2, PT_R2(sp) + LONG_S v1, PT_STATUS(sp) + LONG_S $4, PT_R4(sp) + MFC0 v1, CP0_CAUSE + LONG_S $5, PT_R5(sp) + LONG_S v1, PT_CAUSE(sp) + LONG_S $6, PT_R6(sp) + MFC0 v1, CP0_EPC + LONG_S $7, PT_R7(sp) + LONG_S v1, PT_EPC(sp) + LONG_S $25, PT_R25(sp) + LONG_S $28, PT_R28(sp) + LONG_S $31, PT_R31(sp) + .set pop + .endm - .macro get_saved_sp - nop - .endm + .macro SAVE_ALL + SAVE_SOME + SAVE_AT + SAVE_TEMP + SAVE_FPU + SAVE_STATIC + .endm - .macro SAVE_SOME - .set push - .set noat - .set reorder - move k1, sp -8: move k0, sp - PTR_SUBU sp, k1, PT_SIZE - LONG_S k0, PT_R29(sp) - LONG_S $3, PT_R3(sp) - LONG_S $0, PT_R0(sp) - mfc0 v1, CP0_STATUS - LONG_S $2, PT_R2(sp) - LONG_S v1, PT_STATUS(sp) - LONG_S $4, PT_R4(sp) - mfc0 v1, CP0_CAUSE - LONG_S $5, PT_R5(sp) - LONG_S v1, PT_CAUSE(sp) - LONG_S $6, PT_R6(sp) - MFC0 v1, CP0_EPC - LONG_S $7, PT_R7(sp) - LONG_S v1, PT_EPC(sp) - LONG_S $25, PT_R25(sp) - LONG_S $28, PT_R28(sp) - LONG_S $31, PT_R31(sp) - .set pop - .endm + .macro RESTORE_FPU + .set push + .set noreorder +#ifdef RT_USING_FPU + /* Ensure CU1 (FPU) is enabled */ + MFC0 v1, CP0_STATUS + lui t1, %hi(ST0_CU1) + addiu t1, t1, %lo(ST0_CU1) + or v1, v1, t1 + MTC0 v1, CP0_STATUS + SSNOP + LONG_L v1, PT_FPU_FCSR31(sp) + ctc1 v1, fcr31 + l.d $f0, PT_FPU_R0(sp) + l.d $f2, PT_FPU_R2(sp) + l.d $f4, PT_FPU_R4(sp) + l.d $f6, PT_FPU_R6(sp) + l.d $f8, PT_FPU_R8(sp) + l.d $f10, PT_FPU_R10(sp) + l.d $f12, PT_FPU_R12(sp) + l.d $f14, PT_FPU_R14(sp) + l.d $f16, PT_FPU_R16(sp) + l.d $f18, PT_FPU_R18(sp) + l.d $f20, PT_FPU_R20(sp) + l.d $f22, PT_FPU_R22(sp) + l.d $f24, PT_FPU_R24(sp) + l.d $f26, PT_FPU_R26(sp) + l.d $f28, PT_FPU_R28(sp) + l.d $f30, PT_FPU_R30(sp) +#endif + .set reorder + .set pop + .endm - .macro SAVE_ALL - SAVE_SOME - SAVE_AT - SAVE_TEMP - SAVE_STATIC - .endm + .macro RESTORE_AT + .set push + .set noat + LONG_L $1, PT_R1(sp) + .set pop + .endm - .macro RESTORE_AT - .set push - .set noat - LONG_L $1, PT_R1(sp) - .set pop - .endm + .macro RESTORE_TEMP + lw $24, PT_LO(sp) + LONG_L $8, PT_R8(sp) + LONG_L $9, PT_R9(sp) + mtlo $24 + lw $24, PT_HI(sp) + LONG_L $10, PT_R10(sp) + LONG_L $11, PT_R11(sp) + mthi $24 + LONG_L $12, PT_R12(sp) + LONG_L $13, PT_R13(sp) + LONG_L $14, PT_R14(sp) + LONG_L $15, PT_R15(sp) + LONG_L $24, PT_R24(sp) + .endm - .macro RESTORE_TEMP - LONG_L $24, PT_LO(sp) - LONG_L $8, PT_R8(sp) - LONG_L $9, PT_R9(sp) - mtlo $24 - LONG_L $24, PT_HI(sp) - LONG_L $10, PT_R10(sp) - LONG_L $11, PT_R11(sp) - mthi $24 - LONG_L $12, PT_R12(sp) - LONG_L $13, PT_R13(sp) - LONG_L $14, PT_R14(sp) - LONG_L $15, PT_R15(sp) - LONG_L $24, PT_R24(sp) - .endm + .macro RESTORE_STATIC + LONG_L $16, PT_R16(sp) + LONG_L $17, PT_R17(sp) + LONG_L $18, PT_R18(sp) + LONG_L $19, PT_R19(sp) + LONG_L $20, PT_R20(sp) + LONG_L $21, PT_R21(sp) + LONG_L $22, PT_R22(sp) + LONG_L $23, PT_R23(sp) + LONG_L $30, PT_R30(sp) + .endm - .macro RESTORE_STATIC - LONG_L $16, PT_R16(sp) - LONG_L $17, PT_R17(sp) - LONG_L $18, PT_R18(sp) - LONG_L $19, PT_R19(sp) - LONG_L $20, PT_R20(sp) - LONG_L $21, PT_R21(sp) - LONG_L $22, PT_R22(sp) - LONG_L $23, PT_R23(sp) - LONG_L $30, PT_R30(sp) - .endm +#define STATMASK 0x1f - .macro RESTORE_SOME - .set push - .set reorder - .set noat - LONG_L v0, PT_STATUS(sp) - mtc0 v0, CP0_STATUS - LONG_L v1, PT_EPC(sp) - MTC0 v1, CP0_EPC - LONG_L $31, PT_R31(sp) - LONG_L $28, PT_R28(sp) - LONG_L $25, PT_R25(sp) - LONG_L $7, PT_R7(sp) - LONG_L $6, PT_R6(sp) - LONG_L $5, PT_R5(sp) - LONG_L $4, PT_R4(sp) - LONG_L $3, PT_R3(sp) - LONG_L $2, PT_R2(sp) - .set pop - .endm + .macro RESTORE_SOME + .set push + .set reorder + .set noat + mfc0 a0, CP0_STATUS + ori a0, STATMASK + xori a0, STATMASK + mtc0 a0, CP0_STATUS + li v1, (ST0_CU1 | ST0_FR | ST0_IM) + and a0, v1, a0 + LONG_L v0, PT_STATUS(sp) + li v1, ~(ST0_CU1 | ST0_FR | ST0_IM) + and v0, v1 + or v0, a0 + li v1, (ST0_KX | ST0_SX | ST0_UX) + or v0, v1 + mtc0 v0, CP0_STATUS + LONG_L v1, PT_EPC(sp) + MTC0 v1, CP0_EPC + LONG_L $31, PT_R31(sp) + LONG_L $28, PT_R28(sp) + LONG_L $25, PT_R25(sp) + LONG_L $7, PT_R7(sp) + LONG_L $6, PT_R6(sp) + LONG_L $5, PT_R5(sp) + LONG_L $4, PT_R4(sp) + LONG_L $3, PT_R3(sp) + LONG_L $2, PT_R2(sp) + .set pop + .endm - .macro RESTORE_SP_AND_RET - LONG_L sp, PT_R29(sp) - .set mips3 - eret - .set mips0 - .endm + .macro RESTORE_SP_AND_RET + LONG_L sp, PT_R29(sp) + eret + nop + .endm - .macro RESTORE_SP - LONG_L sp, PT_R29(sp) - .endm + .macro RESTORE_SP + LONG_L sp, PT_R29(sp) + .endm - .macro RESTORE_ALL - RESTORE_TEMP - RESTORE_STATIC - RESTORE_AT - RESTORE_SOME - RESTORE_SP - .endm + .macro RESTORE_ALL + RESTORE_TEMP + RESTORE_FPU + RESTORE_STATIC + RESTORE_AT + RESTORE_SOME + RESTORE_SP + .endm - .macro RESTORE_ALL_AND_RET - RESTORE_TEMP - RESTORE_STATIC - RESTORE_AT - RESTORE_SOME - RESTORE_SP_AND_RET - .endm + .macro RESTORE_ALL_AND_RET + RESTORE_TEMP + RESTORE_FPU + RESTORE_STATIC + RESTORE_AT + RESTORE_SOME + RESTORE_SP_AND_RET + .endm #endif /* end of __STACKFRAME_H__ */ diff --git a/libcpu/mips/gs232/SConscript b/libcpu/mips/gs232/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/mips/gs232/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/mips/gs232/cache.c b/libcpu/mips/gs232/cache.c new file mode 100644 index 0000000000..484d3816f4 --- /dev/null +++ b/libcpu/mips/gs232/cache.c @@ -0,0 +1,231 @@ +/* + * Cache Ops For Loongson GS232 + * + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2010-07-09 Bernard first version + * 2011-08-08 lgnq modified for LS1B + * 2015-07-08 chinesebear modified for loongson 1c + */ + +#include <rtthread.h> +#include <mips.h> + +#define K0BASE 0x80000000 +#define PRID_LS1C 0x4220 + +extern void Clear_TagLo (void); +extern void Invalidate_Icache_Ls1c(unsigned int); +extern void Invalidate_Dcache_ClearTag_Ls1c(unsigned int); +extern void Invalidate_Dcache_Fill_Ls1c(unsigned int); +extern void Writeback_Invalidate_Dcache(unsigned int); +extern void enable_cpu_cache(void); + +typedef struct cacheinfo_t +{ + unsigned int icache_size; + unsigned int dcache_size; + unsigned int icacheline_size; + unsigned int dcacheline_size; +} cacheinfo_t ; + +typedef struct cacheop_t +{ + void (*Clear_TagLo) (void); + void (*Invalidate_Icache) (unsigned int); + void (*Invalidate_Dcache_Fill) (unsigned int); + void (*Invalidate_Dcache_ClearTag) (unsigned int); + void (*Init_Cache)(void); +} cacheop_t ; + +static cacheop_t cacheop, *pcacheop; +static cacheinfo_t cacheinfo, *pcacheinfo; + +int identify_cpu(void) +{ + unsigned int cpu_id; + + pcacheop = &cacheop; + pcacheinfo = &cacheinfo; + + rt_kprintf("CPU configure: 0x%08x\n", read_c0_config()); + cpu_id = read_c0_prid(); + switch (cpu_id) + { + case PRID_LS1C: + rt_kprintf("CPU:Loongson 1C\n"); + pcacheop->Clear_TagLo = Clear_TagLo; + pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1c; + pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1c; + pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1c; + break; + default: + rt_kprintf("Unknown CPU type, system halted!\n"); + while (1) + { + ; + } + break; + } + + return 0; +} + +void probe_cache(void) +{ + unsigned int config1 = read_c0_config1(); + unsigned int icache_size, icache_line_size, icache_sets, icache_ways; + unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways; + + if ((icache_line_size = ((config1 >> 19) & 7))) + icache_line_size = 2 << icache_line_size; + else + icache_line_size = icache_line_size; + icache_sets = 64 << ((config1 >> 22) & 7); + icache_ways = 1 + ((config1 >> 16) & 7); + icache_size = icache_sets * icache_ways * icache_line_size; + + if ((dcache_line_size = ((config1 >> 10) & 7))) + dcache_line_size = 2 << dcache_line_size; + else + dcache_line_size = dcache_line_size; + dcache_sets = 64 << ((config1 >> 13) & 7); + dcache_ways = 1 + ((config1 >> 7) & 7); + dcache_size = dcache_sets * dcache_ways * dcache_line_size; + + rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size); + rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size); + + pcacheinfo->icache_size = icache_size; + pcacheinfo->dcache_size = dcache_size; + pcacheinfo->icacheline_size = icache_line_size; + pcacheinfo->dcacheline_size = dcache_line_size; + + return ; +} + +void invalidate_writeback_dcache_all(void) +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + + while (start < end) + { + Writeback_Invalidate_Dcache(start); //hit writeback invalidate + start += pcacheinfo->dcacheline_size; + } +} + +void invalidate_writeback_dcache(unsigned long addr, int size) +{ + unsigned long start, end; + + start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size); + end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size); + + while (start <end) + { + Writeback_Invalidate_Dcache(start); + start += pcacheinfo->dcacheline_size; + } +} + +void invalidate_icache_all(void) +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->icache_size); + + while (start < end) + { + pcacheop->Invalidate_Icache(start); + start += pcacheinfo->icacheline_size; + } +} + +void invalidate_dcache_all(void) +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + while (start <end) + { + Invalidate_Dcache_Fill_Ls1c(start); + start += pcacheinfo->icacheline_size; + } +} + +//with cache disabled +void init_dcache(void) +{ + unsigned int start = K0BASE; + unsigned int end = (start + pcacheinfo->dcache_size); + + while (start < end) + { + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; + } + +} + +void rt_hw_cache_init(void) +{ + unsigned int start, end; + + /* 1. identify cpu and probe cache */ + identify_cpu(); + probe_cache(); + + start = K0BASE; + end = (start + pcacheinfo->icache_size); + + /* + * 2. clear CP0 taglo/taghi register; + */ + pcacheop->Clear_TagLo(); + + /* + * 3. invalidate instruction cache; + */ + while (start < end) + { + pcacheop->Invalidate_Icache(start); //index invalidate icache + start += pcacheinfo->icacheline_size; + } + + /* + * 4. invalidate data cache; + */ + start = K0BASE; + end = (start + pcacheinfo->dcache_size); + while(start < end) + { + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; + } + + start = K0BASE; + while(start < end) + { + pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache + start += pcacheinfo->dcacheline_size; + } + + start = K0BASE; + while(start < end) + { + pcacheop->Invalidate_Dcache_ClearTag(start); + start += pcacheinfo->dcacheline_size; + } + + /* enable cache */ + enable_cpu_cache(); + rt_kprintf("enable cpu cache done\n"); + + return ; +} + + diff --git a/libcpu/mips/loongson_1c/cache.h b/libcpu/mips/gs232/cache.h index b5c2d4501e..381298e4df 100644 --- a/libcpu/mips/loongson_1c/cache.h +++ b/libcpu/mips/gs232/cache.h @@ -1,20 +1,19 @@ /* - * File : cache.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * Cache Ops For Loongson GS232 + * + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2010-07-09 Bernard first version - * 2011-08-08 lgnq modified for LS1B + * 2010-07-09 Bernard first version + * 2011-08-08 lgnq modified for LS1B + * 2015-07-08 chinesebear modified for loongson 1c */ + #ifndef __CACHE_H__ #define __CACHE_H__ - /* * Cache Operations */ diff --git a/libcpu/mips/loongson_1c/cache_gcc.S b/libcpu/mips/gs232/cache_gcc.S index af25c31ded..10a41652a3 100644 --- a/libcpu/mips/loongson_1c/cache_gcc.S +++ b/libcpu/mips/gs232/cache_gcc.S @@ -1,11 +1,7 @@ /* - * File : cache_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team + * Copyright (c) 2006-2019, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -13,13 +9,17 @@ * 2010-09-11 bernard port to Loongson SoC3210 * 2011-08-08 lgnq port to Loongson LS1B * 2015-07-08 chinesebear port to Loongson LS1C + * 2019-07-19 Zhou Yanjie clean up code */ -#include "../common/mipsregs.h" -#include "../common/mips.inc" -#include "../common/asm.h" + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ +#endif + +#include <mips.h> #include "cache.h" - .ent cache_init + .ent cache_init .global cache_init .set noreorder cache_init: @@ -69,84 +69,84 @@ cache_i4way: sllv t5, t4, t5 #if 0 la t0, memvar - sw t7, 0x0(t0) #ways - sw t5, 0x4(t0) #icache size - sw t6, 0x8(t0) #dcache size + sw t7, 0x0(t0) #ways + sw t5, 0x4(t0) #icache size + sw t6, 0x8(t0) #dcache size #endif ####part 3#### - .set mips3 - lui a0, 0x8000 - addu a1, $0, t5 - addu a2, $0, t6 + .set mips3 + lui a0, 0x8000 + addu a1, $0, t5 + addu a2, $0, t6 cache_init_d2way: #a0=0x80000000, a1=icache_size, a2=dcache_size #a3, v0 and v1 used as local registers - mtc0 $0, CP0_TAGHI - addu v0, $0, a0 - addu v1, a0, a2 + mtc0 $0, CP0_TAGHI + addu v0, $0, a0 + addu v1, a0, a2 1: slt a3, v0, v1 - beq a3, $0, 1f - nop - mtc0 $0, CP0_TAGLO - beq t7, 1, 4f - cache Index_Store_Tag_D, 0x0(v0) # 1 way - beq t7, 2 ,4f - cache Index_Store_Tag_D, 0x1(v0) # 2 way - cache Index_Store_Tag_D, 0x2(v0) # 4 way - cache Index_Store_Tag_D, 0x3(v0) + beq a3, $0, 1f + nop + mtc0 $0, CP0_TAGLO + beq t7, 1, 4f + cache Index_Store_Tag_D, 0x0(v0) # 1 way + beq t7, 2 ,4f + cache Index_Store_Tag_D, 0x1(v0) # 2 way + cache Index_Store_Tag_D, 0x2(v0) # 4 way + cache Index_Store_Tag_D, 0x3(v0) 4: beq $0, $0, 1b - addiu v0, v0, 0x20 + addiu v0, v0, 0x20 1: cache_flush_i2way: - addu v0, $0, a0 - addu v1, a0, a1 + addu v0, $0, a0 + addu v1, a0, a1 1: slt a3, v0, v1 - beq a3, $0, 1f - nop - beq t3, 1, 4f - cache Index_Invalidate_I, 0x0(v0) # 1 way - beq t3, 2, 4f - cache Index_Invalidate_I, 0x1(v0) # 2 way - cache Index_Invalidate_I, 0x2(v0) - cache Index_Invalidate_I, 0x3(v0) # 4 way + beq a3, $0, 1f + nop + beq t3, 1, 4f + cache Index_Invalidate_I, 0x0(v0) # 1 way + beq t3, 2, 4f + cache Index_Invalidate_I, 0x1(v0) # 2 way + cache Index_Invalidate_I, 0x2(v0) + cache Index_Invalidate_I, 0x3(v0) # 4 way 4: beq $0, $0, 1b - addiu v0, v0, 0x20 + addiu v0, v0, 0x20 1: cache_flush_d2way: - addu v0, $0, a0 - addu v1, a0, a2 + addu v0, $0, a0 + addu v1, a0, a2 1: slt a3, v0, v1 - beq a3, $0, 1f - nop - beq t7, 1, 4f - cache Index_Writeback_Inv_D, 0x0(v0) #1 way - beq t7, 2, 4f - cache Index_Writeback_Inv_D, 0x1(v0) # 2 way - cache Index_Writeback_Inv_D, 0x2(v0) - cache Index_Writeback_Inv_D, 0x3(v0) # 4 way + beq a3, $0, 1f + nop + beq t7, 1, 4f + cache Index_Writeback_Inv_D, 0x0(v0) #1 way + beq t7, 2, 4f + cache Index_Writeback_Inv_D, 0x1(v0) # 2 way + cache Index_Writeback_Inv_D, 0x2(v0) + cache Index_Writeback_Inv_D, 0x3(v0) # 4 way 4: beq $0, $0, 1b - addiu v0, v0, 0x20 + addiu v0, v0, 0x20 1: cache_init_finish: - jr t1 + jr t1 nop .set reorder - .end cache_init + .end cache_init ########################### # Enable CPU cache # ########################### LEAF(enable_cpu_cache) - .set noreorder - mfc0 t0, CP0_CONFIG - nop - and t0, ~0x03 - or t0, 0x03 - mtc0 t0, CP0_CONFIG - nop - .set reorder - j ra + .set noreorder + mfc0 t0, CP0_CONFIG + nop + and t0, ~0x03 + or t0, 0x03 + mtc0 t0, CP0_CONFIG + nop + .set reorder + j ra END (enable_cpu_cache) ########################### @@ -154,26 +154,26 @@ END (enable_cpu_cache) ########################### LEAF(disable_cpu_cache) - .set noreorder - mfc0 t0, CP0_CONFIG - nop - and t0, ~0x03 - or t0, 0x2 - mtc0 t0, CP0_CONFIG - nop - .set reorder - j ra + .set noreorder + mfc0 t0, CP0_CONFIG + nop + and t0, ~0x03 + or t0, 0x2 + mtc0 t0, CP0_CONFIG + nop + .set reorder + j ra END (disable_cpu_cache) /**********************************/ /* Invalidate Instruction Cache */ /**********************************/ LEAF(Clear_TagLo) - .set noreorder - mtc0 zero, CP0_TAGLO - nop - .set reorder - j ra + .set noreorder + mtc0 zero, CP0_TAGLO + nop + .set reorder + j ra END(Clear_TagLo) .set mips3 @@ -181,38 +181,38 @@ END(Clear_TagLo) /* Invalidate Instruction Cache */ /**********************************/ LEAF(Invalidate_Icache_Ls1c) - .set noreorder - cache Index_Invalidate_I,0(a0) - cache Index_Invalidate_I,1(a0) - cache Index_Invalidate_I,2(a0) - cache Index_Invalidate_I,3(a0) - .set reorder - j ra + .set noreorder + cache Index_Invalidate_I,0(a0) + cache Index_Invalidate_I,1(a0) + cache Index_Invalidate_I,2(a0) + cache Index_Invalidate_I,3(a0) + .set reorder + j ra END(Invalidate_Icache_Ls1c) /**********************************/ /* Invalidate Data Cache */ /**********************************/ LEAF(Invalidate_Dcache_ClearTag_Ls1c) - .set noreorder - cache Index_Store_Tag_D, 0(a0) # BDSLOT: clear tag - cache Index_Store_Tag_D, 1(a0) # BDSLOT: clear tag - .set reorder - j ra + .set noreorder + cache Index_Store_Tag_D, 0(a0) # BDSLOT: clear tag + cache Index_Store_Tag_D, 1(a0) # BDSLOT: clear tag + .set reorder + j ra END(Invalidate_Dcache_ClearTag_Ls1c) LEAF(Invalidate_Dcache_Fill_Ls1c) - .set noreorder - cache Index_Writeback_Inv_D, 0(a0) # BDSLOT: clear tag - cache Index_Writeback_Inv_D, 1(a0) # BDSLOT: clear tag - .set reorder - j ra + .set noreorder + cache Index_Writeback_Inv_D, 0(a0) # BDSLOT: clear tag + cache Index_Writeback_Inv_D, 1(a0) # BDSLOT: clear tag + .set reorder + j ra END(Invalidate_Dcache_Fill_Ls1c) LEAF(Writeback_Invalidate_Dcache) - .set noreorder - cache Hit_Writeback_Inv_D, (a0) - .set reorder - j ra + .set noreorder + cache Hit_Writeback_Inv_D, (a0) + .set reorder + j ra END(Writeback_Invalidate_Dcache) .set mips0 diff --git a/libcpu/mips/gs232/cpuinit_gcc.S b/libcpu/mips/gs232/cpuinit_gcc.S new file mode 100644 index 0000000000..3379d7dae4 --- /dev/null +++ b/libcpu/mips/gs232/cpuinit_gcc.S @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + */ + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ +#endif + +#include <mips.h> + + .section ".start", "ax" + .set noreorder + + .globl rt_cpu_early_init +rt_cpu_early_init: + jr ra + nop
\ No newline at end of file diff --git a/libcpu/mips/gs232/cpuport.c b/libcpu/mips/gs232/cpuport.c new file mode 100644 index 0000000000..1b13719449 --- /dev/null +++ b/libcpu/mips/gs232/cpuport.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2010-07-09 Bernard first version + * 2010-09-11 Bernard add CPU reset implementation + * 2015-07-06 chinesebear modified for loongson 1c + */ + +#include <rtthread.h> +#include "gs232.h" + +/** + * @addtogroup Loongson GS232 + */ + +/*@{*/ + +/** + * this function will reset CPU + * + */ +void rt_hw_cpu_reset(void) +{ + /* open the watch-dog */ + WDT_EN = 0x01; /* watch dog enable */ + WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ + WDT_SET = 0x01; /* watch dog start */ + + rt_kprintf("reboot system...\n"); + while (1); +} + +/** + * this function will shutdown CPU + * + */ +void rt_hw_cpu_shutdown(void) +{ + rt_kprintf("shutdown...\n"); + + while (1); +} + + +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define Hit_Writeback_Inv_D 0x15 + + +void flush_cache(unsigned long start_addr, unsigned long size) +{ + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); + + while (1) { + cache_op(Hit_Writeback_Inv_D, addr); + cache_op(Hit_Invalidate_I, addr); + if (addr == aend) + break; + addr += lsize; + } +} + + +/*@}*/ + diff --git a/libcpu/mips/gs232/gs232.h b/libcpu/mips/gs232/gs232.h new file mode 100644 index 0000000000..6e90f7ba66 --- /dev/null +++ b/libcpu/mips/gs232/gs232.h @@ -0,0 +1,67 @@ +/* + * Misc define for GS232 + * + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + */ + +#ifndef __GS232_H__ +#define __GS232_H__ + +#include <mips.h> + +#define INTC_BASE 0xBFD01040 + +#define GS232_INTC_CELLS 5 +#define GS232_NR_IRQS (32 * GS232_INTC_CELLS) + +#define GMAC0_BASE 0xBFE10000 +#define GMAC0_DMA_BASE 0xBFE11000 +#define GMAC1_BASE 0xBFE20000 +#define GMAC1_DMA_BASE 0xBFE21000 +#define I2C0_BASE 0xBFE58000 +#define PWM0_BASE 0xBFE5C000 +#define PWM1_BASE 0xBFE5C010 +#define PWM2_BASE 0xBFE5C020 +#define PWM3_BASE 0xBFE5C030 +#define WDT_BASE 0xBFE5C060 +#define RTC_BASE 0xBFE64000 +#define I2C1_BASE 0xBFE68000 +#define I2C2_BASE 0xBFE70000 +#define AC97_BASE 0xBFE74000 +#define NAND_BASE 0xBFE78000 +#define SPI_BASE 0xBFE80000 +#define CAN1_BASE 0xBF004300 +#define CAN0_BASE 0xBF004400 + +#ifndef __ASSEMBLY__ +#include <rthw.h> + +/* Watch Dog registers */ +#define WDT_EN HWREG32(WDT_BASE + 0x00) +#define WDT_SET HWREG32(WDT_BASE + 0x04) +#define WDT_TIMER HWREG32(WDT_BASE + 0x08) + +#define PLL_FREQ HWREG32(0xbfe78030) +#define PLL_DIV_PARAM HWREG32(0xbfe78034) + +struct gs232_intc_regs +{ + volatile unsigned int int_isr; + volatile unsigned int int_en; + volatile unsigned int int_set; + volatile unsigned int int_clr; /* offset 0x10*/ + volatile unsigned int int_pol; + volatile unsigned int int_edge; /* offset 0 */ +}; + +extern void rt_hw_timer_init(void); + +#endif + +#endif
\ No newline at end of file diff --git a/libcpu/mips/gs232/interrupt.c b/libcpu/mips/gs232/interrupt.c new file mode 100644 index 0000000000..f3e0f80763 --- /dev/null +++ b/libcpu/mips/gs232/interrupt.c @@ -0,0 +1,162 @@ +/* + * Interrupt handle for GS232 + * + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2010-10-15 Bernard first version + * 2010-10-15 lgnq modified for LS1B + * 2013-03-29 aozima Modify the interrupt interface implementations. + * 2015-07-06 chinesebear modified for loongson 1c + * 2019-12-04 Jiaxun Yang Generialize + */ + +#include <rtthread.h> +#include <rthw.h> +#include "gs232.h" + + +#define MAX_INTR (GS232_NR_IRQS) + +static struct rt_irq_desc irq_handle_table[MAX_INTR]; +void rt_interrupt_dispatch(void *ptreg); +void rt_hw_timer_handler(); + +static struct gs232_intc_regs volatile *gs232_hw0_icregs += (struct gs232_intc_regs volatile *)(INTC_BASE); + +/** + * @addtogroup Loongson GS232 + */ + +/*@{*/ + +static void rt_hw_interrupt_handler(int vector, void *param) +{ + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + rt_int32_t idx; + rt_int32_t i; + rt_uint32_t c0_status = 0; + + for (i=0; i < GS232_INTC_CELLS; i++) + { + /* Disable */ + (gs232_hw0_icregs+i)->int_en = 0x0; + /* Trigger active low */ + (gs232_hw0_icregs+i)->int_pol = -1; /* Must be done here */ + /* Make all interrupts level triggered */ + (gs232_hw0_icregs+i)->int_edge = 0x00000000; + /* Mask all interrupts */ + (gs232_hw0_icregs+i)->int_clr = 0xffffffff; + mips_unmask_cpu_irq(i + 2); + } + + rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table)); + for (idx = 0; idx < MAX_INTR; idx ++) + { + irq_handle_table[idx].handler = rt_hw_interrupt_handler; + } +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + /* mask interrupt */ + (gs232_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f)); +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + (gs232_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f)); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if (vector >= 0 && vector < MAX_INTR) + { + old_handler = irq_handle_table[vector].handler; + +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX); +#endif /* RT_USING_INTERRUPT_INFO */ + irq_handle_table[vector].handler = handler; + irq_handle_table[vector].param = param; + } + + return old_handler; +} + + +/** + * ִ Call ISR + * @IRQn ID of IRQ + */ +void gs232_do_IRQ(int IRQn) +{ + rt_isr_handler_t irq_func; + void *param; + + irq_func = irq_handle_table[IRQn].handler; + param = irq_handle_table[IRQn].param; + + irq_func(IRQn, param); + +#ifdef RT_USING_INTERRUPT_INFO + irq_handle_table[IRQn].counter++; +#endif + + return ; +} + + +void rt_do_mips_cpu_irq(rt_uint32_t ip) +{ + rt_uint32_t intstatus, irq, n; + + if (ip == 7) { + rt_hw_timer_handler(); + } else { + n = ip - 2; + /* Receive interrupt signal, compute the irq */ + intstatus = (gs232_hw0_icregs+n)->int_isr & (gs232_hw0_icregs+n)->int_en; + if (0 == intstatus) + return ; + + irq = __rt_ffs(intstatus) - 1; + gs232_do_IRQ((n<<5) + irq); + + /* ack interrupt */ + (gs232_hw0_icregs+n)->int_clr |= (1 << irq); + } +} + + +/*@}*/ + + diff --git a/libcpu/mips/gs232/ls1b.h b/libcpu/mips/gs232/ls1b.h new file mode 100644 index 0000000000..071a4aeb82 --- /dev/null +++ b/libcpu/mips/gs232/ls1b.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-08-08 lgnq first version + */ + +#ifndef __LS1B_H__ +#define __LS1B_H__ + +#include <gs232.h> + +#define LS1B_ACPI_IRQ 0 +#define LS1B_HPET_IRQ 1 +#define LS1B_UART0_IRQ 2 +#define LS1B_UART1_IRQ 3 +#define LS1B_UART2_IRQ 4 +#define LS1B_UART3_IRQ 5 +#define LS1B_CAN0_IRQ 6 +#define LS1B_CAN1_IRQ 7 +#define LS1B_SPI0_IRQ 8 +#define LS1B_SPI1_IRQ 9 +#define LS1B_AC97_IRQ 10 +#define LS1B_MS_IRQ 11 +#define LS1B_KB_IRQ 12 +#define LS1B_DMA0_IRQ 13 +#define LS1B_DMA1_IRQ 14 +#define LS1B_NAND_IRQ 15 +#define LS1B_I2C0_IRQ 16 +#define LS1B_I2C1_IRQ 17 +#define LS1B_PWM0_IRQ 18 +#define LS1B_PWM1_IRQ 19 +#define LS1B_PWM2_IRQ 20 +#define LS1B_PWM3_IRQ 21 +#define LS1B_LPC_IRQ 22 +#define LS1B_EHCI_IRQ 32 +#define LS1B_OHCI_IRQ 33 +#define LS1B_GMAC1_IRQ 34 +#define LS1B_GMAC2_IRQ 35 +#define LS1B_SATA_IRQ 36 +#define LS1B_GPU_IRQ 37 +#define LS1B_PCI_INTA_IRQ 38 +#define LS1B_PCI_INTB_IRQ 39 +#define LS1B_PCI_INTC_IRQ 40 +#define LS1B_PCI_INTD_IRQ 41 + +#define LS1B_GPIO_IRQ 64 +#define LS1B_GPIO_FIRST_IRQ 64 +#define LS1B_GPIO_IRQ_COUNT 96 +#define LS1B_GPIO_LAST_IRQ (LS1B_GPIO_FIRST_IRQ + LS1B_GPIO_IRQ_COUNT-1) + +#define INT_PCI_INTA (1<<6) +#define INT_PCI_INTB (1<<7) +#define INT_PCI_INTC (1<<8) +#define INT_PCI_INTD (1<<9) + +#define LS1B_LAST_IRQ 159 +#define MIPS_CPU_TIMER_IRQ 167 +#define LS1B_INTREG_BASE 0xbfd01040 + +#define LS1B_DMA_IRQ_BASE 168 +#define LS1B_DMA_IRQ_COUNT 16 + +#endif diff --git a/libcpu/mips/gs232/ls1c.h b/libcpu/mips/gs232/ls1c.h new file mode 100644 index 0000000000..54c7e36e99 --- /dev/null +++ b/libcpu/mips/gs232/ls1c.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-08-08 lgnq first version + * 2015-07-06 chinesebear modified for loongson 1c + */ + +#ifndef __LS1C_H__ +#define __LS1C_H__ + +#include <gs232.h> + +#define LS1C_ACPI_IRQ 0 +#define LS1C_HPET_IRQ 1 +//#define LS1C_UART0_IRQ 3 // linux����3��v1.4�汾��1c�ֲ�����2�������Σ���ȷ�� +#define LS1C_UART1_IRQ 4 +#define LS1C_UART2_IRQ 5 +#define LS1C_CAN0_IRQ 6 +#define LS1C_CAN1_IRQ 7 +#define LS1C_SPI0_IRQ 8 +#define LS1C_SPI1_IRQ 9 +#define LS1C_AC97_IRQ 10 +#define LS1C_MS_IRQ 11 +#define LS1C_KB_IRQ 12 +#define LS1C_DMA0_IRQ 13 +#define LS1C_DMA1_IRQ 14 +#define LS1C_DMA2_IRQ 15 +#define LS1C_NAND_IRQ 16 +#define LS1C_PWM0_IRQ 17 +#define LS1C_PWM1_IRQ 18 +#define LS1C_PWM2_IRQ 19 +#define LS1C_PWM3_IRQ 20 +#define LS1C_RTC_INT0_IRQ 21 +#define LS1C_RTC_INT1_IRQ 22 +#define LS1C_RTC_INT2_IRQ 23 +#define LS1C_UART3_IRQ 29 +#define LS1C_ADC_IRQ 30 +#define LS1C_SDIO_IRQ 31 + + +#define LS1C_EHCI_IRQ (32+0) +#define LS1C_OHCI_IRQ (32+1) +#define LS1C_OTG_IRQ (32+2) +#define LS1C_MAC_IRQ (32+3) +#define LS1C_CAM_IRQ (32+4) +#define LS1C_UART4_IRQ (32+5) +#define LS1C_UART5_IRQ (32+6) +#define LS1C_UART6_IRQ (32+7) +#define LS1C_UART7_IRQ (32+8) +#define LS1C_UART8_IRQ (32+9) +#define LS1C_UART9_IRQ (32+13) +#define LS1C_UART10_IRQ (32+14) +#define LS1C_UART11_IRQ (32+15) +#define LS1C_I2C2_IRQ (32+17) +#define LS1C_I2C1_IRQ (32+18) +#define LS1C_I2C0_IRQ (32+19) + + +#define LS1C_GPIO_IRQ 64 +#define LS1C_GPIO_FIRST_IRQ 64 +#define LS1C_GPIO_IRQ_COUNT 96 +#define LS1C_GPIO_LAST_IRQ (LS1C_GPIO_FIRST_IRQ + LS1C_GPIO_IRQ_COUNT-1) + + +#define LS1C_LAST_IRQ 159 +#define LS1C_INTREG_BASE 0xbfd01040 + +// ��о1c���жϷ�Ϊ���飬ÿ��32�� +#define LS1C_NR_IRQS (32*5) + + +// GPIO��ź��жϺ�֮��Ļ���ת�� +#define LS1C_GPIO_TO_IRQ(GPIOn) (LS1C_GPIO_FIRST_IRQ + (GPIOn)) +#define LS1C_IRQ_TO_GPIO(IRQn) ((IRQn) - LS1C_GPIO_FIRST_IRQ) + +#endif + diff --git a/libcpu/mips/gs232/mipscfg.c b/libcpu/mips/gs232/mipscfg.c new file mode 100644 index 0000000000..85e0e633ea --- /dev/null +++ b/libcpu/mips/gs232/mipscfg.c @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2010-05-27 swkyer first version + */ +#include <rtthread.h> +#include <mips.h> + +mips32_core_cfg_t g_mips_core = +{ + 16, /* icache_line_size */ + 256, /* icache_lines_per_way */ + 4, /* icache_ways */ + 16, /* dcache_line_size */ + 256, /* dcache_lines_per_way */ + 4, /* dcache_ways */ + 16, /* max_tlb_entries */ +}; + +static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) +{ + rt_uint16_t rets = 1; + + while (n--) + rets *= b; + + return rets; +} + +static rt_uint16_t m_log2(rt_uint16_t b) +{ + rt_uint16_t rets = 0; + + while (b != 1) + { + b /= 2; + rets++; + } + + return rets; +} + +/** + * read core attribute + */ +void mips32_cfg_init(void) +{ + rt_uint16_t val; + rt_uint32_t cp0_config1; + + cp0_config1 = read_c0_config(); + if (cp0_config1 & 0x80000000) + { + cp0_config1 = read_c0_config1(); + + val = (cp0_config1 & (7<<22))>>22; + g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<19))>>19; + g_mips_core.icache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<16))>>16; + g_mips_core.icache_ways = val + 1; + + val = (cp0_config1 & (7<<13))>>13; + g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<10))>>10; + g_mips_core.dcache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<7))>>7; + g_mips_core.dcache_ways = val + 1; + + val = (cp0_config1 & (0x3F<<25))>>25; + g_mips_core.max_tlb_entries = val + 1; + } +} diff --git a/libcpu/mips/gs232/timer.c b/libcpu/mips/gs232/timer.c new file mode 100644 index 0000000000..8879b82ccf --- /dev/null +++ b/libcpu/mips/gs232/timer.c @@ -0,0 +1,41 @@ +/* + * Assembly Macros For MIPS + * + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version + */ + +#include <rtthread.h> +#include <rthw.h> +#include <mips.h> +#include <board.h> + +/** + * This is the timer interrupt service routine. + */ +void rt_hw_timer_handler(void) +{ + unsigned int count; + + count = read_c0_compare(); + write_c0_compare(count); + write_c0_count(0); + + /* increase a OS tick */ + rt_tick_increase(); +} + +/** + * This function will initial OS timer + */ +void rt_hw_timer_init(void) +{ + write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND); + write_c0_count(0); + mips_unmask_cpu_irq(7); +}
\ No newline at end of file diff --git a/libcpu/mips/gs264/SConscript b/libcpu/mips/gs264/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/mips/gs264/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/mips/gs264/cache.c b/libcpu/mips/gs264/cache.c new file mode 100644 index 0000000000..54d38d0d3f --- /dev/null +++ b/libcpu/mips/gs264/cache.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-29 quanzhao the first version + * 2020-07-26 lizhirui porting to ls2k + */ + +#include <rthw.h> +#include <rtdef.h> + +rt_inline rt_uint64_t rt_cpu_icache_line_size(void) +{ + rt_uint64_t ctr; + return 4 << (ctr & 0xF); +} + +rt_inline rt_uint64_t rt_cpu_dcache_line_size(void) +{ + rt_uint64_t ctr; + return 4 << ((ctr >> 16) & 0xF); +} + +void rt_hw_cpu_icache_invalidate(void *addr, int size) +{ + rt_uint64_t line_size = rt_cpu_icache_line_size(); + rt_uint64_t start_addr = (rt_uint64_t)addr; + rt_uint64_t end_addr = (rt_uint64_t) addr + size + line_size - 1; +} + +void rt_hw_cpu_dcache_invalidate(void *addr, int size) +{ + rt_uint64_t line_size = rt_cpu_dcache_line_size(); + rt_uint64_t start_addr = (rt_uint64_t)addr; + rt_uint64_t end_addr = (rt_uint64_t) addr + size + line_size - 1; +} + +void rt_hw_cpu_dcache_clean(void *addr, int size) +{ + rt_uint64_t line_size = rt_cpu_dcache_line_size(); + rt_uint64_t start_addr = (rt_uint64_t)addr; + rt_uint64_t end_addr = (rt_uint64_t) addr + size + line_size - 1; +} + +void rt_hw_cpu_icache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_INVALIDATE) + rt_hw_cpu_icache_invalidate(addr, size); +} + +void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_FLUSH) + rt_hw_cpu_dcache_clean(addr, size); + else if (ops == RT_HW_CACHE_INVALIDATE) + rt_hw_cpu_dcache_invalidate(addr, size); +} + +rt_base_t rt_hw_cpu_icache_status(void) +{ + return 0; +} + +rt_base_t rt_hw_cpu_dcache_status(void) +{ + return 0; +} diff --git a/libcpu/mips/gs264/cache.h b/libcpu/mips/gs264/cache.h new file mode 100644 index 0000000000..10a4afd899 --- /dev/null +++ b/libcpu/mips/gs264/cache.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-03-25 quanzhao the first version + */ +#ifndef __CACHE_H__ +#define __CACHE_H__ + +unsigned long rt_cpu_get_smp_id(void); + +void rt_cpu_mmu_disable(void); +void rt_cpu_mmu_enable(void); +void rt_cpu_tlb_set(volatile unsigned long*); + +void rt_cpu_dcache_clean_flush(void); +void rt_cpu_icache_flush(void); + +void rt_cpu_vector_set_base(unsigned int addr); + +#endif diff --git a/libcpu/mips/gs264/cpuinit_gcc.S b/libcpu/mips/gs264/cpuinit_gcc.S new file mode 100644 index 0000000000..592fedd88a --- /dev/null +++ b/libcpu/mips/gs264/cpuinit_gcc.S @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-05 bigmagic Initial version + */ + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ +#endif + +#include <mips.h> + + .section ".text", "ax" + .set noreorder + + .globl rt_cpu_early_init +rt_cpu_early_init: + mfc0 t0, CP0_CONFIG + ori t0, 3 + mtc0 t0, CP0_CONFIG + ehb + jr ra diff --git a/libcpu/mips/gs264/mips_mmu.c b/libcpu/mips/gs264/mips_mmu.c new file mode 100644 index 0000000000..7bed69596a --- /dev/null +++ b/libcpu/mips/gs264/mips_mmu.c @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-26 lizhirui the first version + */ + +#include <string.h> +#include <stdlib.h> + +#include "mips.h" +#include "mips_mmu.h" + +void mmu_init() +{ + uint32_t status = read_c0_status(); + status |= 0x07 << 5;//ux = 1,sx = 1,kx = 1 + write_c0_status(status); + + mmu_clear_tlb(); + mmu_clear_itlb(); +} + +void mmu_set_cpu_mode(cpu_mode_t cpu_mode) +{ + uint32_t status = read_c0_status(); + status &= ~(0x03 << 3); + status |= ((uint32_t)cpu_mode & 0x03) << 3; + write_c0_status(status); +} + +cpu_mode_t mmu_get_cpu_mode() +{ + uint32_t status = read_c0_status(); + return (cpu_mode_t)((status >> 3) & 0x03); +} + +void mmu_clear_tlb() +{ + uint32_t max_tlb_index = mmu_get_max_tlb_index(); + uint64_t va = KSEG0BASE; + uint32_t entry; + tlb_item_t tlb_item; + + for(entry = 0;entry <= max_tlb_index;entry++) + { + mmu_tlb_item_init(&tlb_item); + mmu_tlb_write_indexed(entry,&tlb_item); + } +} + +void mmu_clear_itlb() +{ + uint32_t diag = read_c0_diag(); + write_c0_diag(diag | (0x01 << 2));//write ITLB bit + read_c0_entrylo0(); +} + +uint32_t mmu_get_max_tlb_index() +{ + uint32_t config1 = read_c0_config1(); + return ((config1 >> 25) & 0x3F); +} + +void mmu_tlb_write_indexed(uint32_t index,tlb_item_t *tlb_item) +{ + tlb_item -> entry_lo[0].g |= tlb_item -> entry_lo[1].g; + tlb_item -> entry_lo[1].g |= tlb_item -> entry_lo[0].g; + mmu_tlb_set_index(index); + write_c0_entrylo0(reg_type_convert(tlb_item -> entry_lo[0],uint64_t)); + write_c0_entrylo1(reg_type_convert(tlb_item -> entry_lo[1],uint64_t)); + write_c0_entryhi(reg_type_convert(tlb_item -> entry_hi,uint64_t)); + write_c0_pagemask(reg_type_convert(tlb_item -> page_mask,uint64_t)); + tlb_write_indexed(); + read_c0_entrylo0(); +} + +void mmu_tlb_write_random(tlb_item_t *tlb_item) +{ + tlb_item -> entry_lo[0].g |= tlb_item -> entry_lo[1].g; + tlb_item -> entry_lo[1].g |= tlb_item -> entry_lo[0].g; + write_c0_entrylo0(reg_type_convert(tlb_item -> entry_lo[0],uint64_t)); + write_c0_entrylo1(reg_type_convert(tlb_item -> entry_lo[1],uint64_t)); + write_c0_entryhi(reg_type_convert(tlb_item -> entry_hi,uint64_t)); + write_c0_pagemask(reg_type_convert(tlb_item -> page_mask,uint64_t)); + tlb_write_random(); + read_c0_entrylo0(); +} + +void mmu_tlb_read(uint32_t index,tlb_item_t *tlb_item) +{ + mmu_tlb_set_index(index); + tlb_read(); + uint64_t entrylo[2]; + uint64_t entryhi; + uint64_t page_mask; + entrylo[0] = read_c0_entrylo0(); + entrylo[1] = read_c0_entrylo1(); + entryhi = read_c0_entryhi(); + page_mask = read_c0_pagemask(); + tlb_item -> entry_lo[0] = reg_type_convert(entrylo[0],entry_lo_t); + tlb_item -> entry_lo[1] = reg_type_convert(entrylo[1],entry_lo_t); + tlb_item -> entry_hi = reg_type_convert(entryhi,entry_hi_t); + tlb_item -> page_mask = reg_type_convert(page_mask,page_mask_t); +} + +uint32_t mmu_tlb_find(uint64_t vpn,uint32_t asid,uint32_t *index) +{ + entry_hi_t entry_hi; + entry_hi.r = (vpn >> 62) & 0x03; + entry_hi.vpn2 = (vpn >> 13) & 0x7FFFFFFU; + entry_hi.asid = asid & 0xFFU; + tlb_item_t tlb_item; + //mmu_tlb_read(6,&tlb_item); + //tlb_dump(); + mmu_tlb_item_init(&tlb_item); + tlb_item.entry_lo[0].g = tlb_item.entry_lo[1].g = 1; + read_c0_entrylo0();//i don't know why,but if i don't read any register of mmu,tplb will be failed in qemu. + write_c0_entrylo0(reg_type_convert(tlb_item.entry_lo[0],uint64_t)); + write_c0_entrylo1(reg_type_convert(tlb_item.entry_lo[1],uint64_t)); + write_c0_entryhi(reg_type_convert(entry_hi,uint64_t)); + //__asm__ __volatile__("ehb"); + //read_c0_entryhi(); + //rt_kprintf("entry_hi = %p\n",read_c0_entryhi()); + tlb_probe(); + *index = mmu_tlb_get_index(); + return mmu_tlb_is_matched(); +} + +void mmu_tlb_item_init(tlb_item_t *tlb_item) +{ + memset(tlb_item,0,sizeof(tlb_item_t)); + tlb_item -> entry_lo[0].c = 0x03; + tlb_item -> entry_lo[1].c = 0x03; +} + +void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t asid,uint32_t global) +{ + uint64_t page_mask_v = (uint64_t)page_mask; + + /*if(page_mask_v & (1 << 13)) + { + page_mask_v |= (1 << 12); + }*/ + + uint64_t lb = lowbit((~(page_mask_v)) << 12); + uint64_t pn_remained = ((~(page_mask_v)) << 12) | lb; + vpn &= pn_remained; + ppn &= pn_remained; + uint64_t odd_vpn = vpn | lb; + uint64_t even_vpn = vpn & (~lb); + uint32_t index; + tlb_item_t tlb_item,tlb2_item; + + mmu_tlb_item_init(&tlb_item); + mmu_tlb_item_init(&tlb2_item); + tlb_item.page_mask.mask = page_mask; + + if(mmu_tlb_find(vpn & (~lb),asid,&index)) + { + mmu_tlb_read(index,&tlb_item); + mmu_tlb_write_indexed(index,&tlb2_item); + } + + entry_lo_t *entry_lo = &tlb_item.entry_lo[vpn == even_vpn ? 0 : 1]; + tlb_item.entry_lo[0].g = tlb_item.entry_lo[1].g = global; + entry_lo -> d = 1; + entry_lo -> ri = 0; + entry_lo -> xi = 0; + entry_lo -> v = 1; + entry_lo -> pfn = ppn >> 12; + tlb_item.entry_hi.r = (vpn >> 62) & 0x03; + tlb_item.entry_hi.vpn2 = (vpn >> 13) & 0x7FFFFFFU; + tlb_item.entry_hi.asid = asid & 0xFFU; + mmu_tlb_write_random(&tlb_item); +} + +uint32_t mmu_tlb_get_random() +{ + return read_c0_random(); +} + +uint32_t mmu_tlb_get_index() +{ + return read_c0_index() & 0x3F; +} + +void mmu_tlb_set_index(uint32_t index) +{ + write_c0_index(index & 0x3F); +} + +uint32_t mmu_tlb_is_matched() +{ + return (read_c0_index() & 0x80000000) == 0; +} + +uint64_t mmu_tlb_get_bad_vaddr() +{ + return read_c0_badvaddr(); +} + +void tlb_dump() +{ + uint32_t max_index = mmu_get_max_tlb_index(); + //uint32_t max_index = 10; + uint32_t entry; + tlb_item_t tlb_item; + + for(entry = 0;entry <= max_index;entry++) + { + mmu_tlb_read(entry,&tlb_item); + //mmu_tlb_write_indexed(entry,&tlb_item); + //mmu_tlb_read(entry,&tlb_item); + rt_kprintf("vpn = 0x%p,ppn0 = 0x%p,ppn1 = 0x%p\n",(uint64_t)tlb_item.entry_hi.vpn2 << 13 | (uint64_t)tlb_item.entry_hi.asid << 62,(uint64_t)tlb_item.entry_lo[0].pfn << 12,(uint64_t)tlb_item.entry_lo[1].pfn << 12); + rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[0].v,tlb_item.entry_lo[0].d,tlb_item.entry_lo[0].g,tlb_item.entry_lo[0].ri,tlb_item.entry_lo[0].xi,tlb_item.entry_lo[0].c); + rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[1].v,tlb_item.entry_lo[1].d,tlb_item.entry_lo[1].g,tlb_item.entry_lo[1].ri,tlb_item.entry_lo[1].xi,tlb_item.entry_lo[1].c); + } +} diff --git a/libcpu/mips/gs264/mips_mmu.h b/libcpu/mips/gs264/mips_mmu.h new file mode 100644 index 0000000000..fcbcef3621 --- /dev/null +++ b/libcpu/mips/gs264/mips_mmu.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-26 lizhirui the first version + */ +#ifndef __MIPS_MMU_H__ +#define __MIPS_MMU_H__ + +typedef enum cpu_mode_t +{ + CPU_MODE_KERNEL = 0x00, + CPU_MODE_SUPERVISOR = 0x01, + CPU_MODE_USER = 0x02 +}cpu_mode_t; + +typedef enum page_mask_enum_t +{ + PAGE_MASK_4KB = 0x00, + PAGE_MASK_16KB = 0x03, + PAGE_MASK_64KB = 0x0F, + PAGE_MASK_256KB = 0x3F, + PAGE_MASK_1MB = 0xFF, + PAGE_MASK_4MB = 0x3FF, + PAGE_MASK_16MB = 0xFFF, + PAGE_MASK_64MB = 0x3FFF, + PAGE_MASK_256MB = 0xFFFF, + PAGE_MASK_1GB = 0x3FFFF +}page_mask_enum_t; + +typedef struct page_mask_t +{ + uint64_t : 11; + uint64_t : 2; + uint64_t mask : 18; + uint64_t : 33; +}page_mask_t; + +typedef struct entry_lo_t +{ + uint64_t g : 1; + uint64_t v : 1; + uint64_t d : 1; + uint64_t c : 3; + uint64_t pfn : 24; + uint64_t pfnx : 3; + uint64_t : 29; + uint64_t xi : 1; + uint64_t ri : 1; +}entry_lo_t; + +typedef struct entry_hi_t +{ + uint64_t asid : 8; + uint64_t : 5; + uint64_t vpn2 : 27; + uint64_t : 22; + uint64_t r : 2; +}entry_hi_t; + +typedef struct tlb_item_t +{ + entry_lo_t entry_lo[2]; + entry_hi_t entry_hi; + page_mask_t page_mask; +}tlb_item_t; + +#define read_c0_diag() __read_32bit_c0_register($22, 0) +#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) +#define read_c0_badvaddr() __read_64bit_c0_register($8, 0) +#define read_c0_random() __read_32bit_c0_register($1, 0) + +#define reg_type_convert(variable,new_type) *((new_type *)(&variable)) +#define lowbit(x) ((x) & (-(x))) + +void mmu_init(); +void mmu_set_cpu_mode(cpu_mode_t cpu_mode); +cpu_mode_t mmu_get_cpu_mode(); +void mmu_clear_tlb(); +void mmu_clear_itlb(); +uint32_t mmu_get_max_tlb_index(); +void mmu_tlb_write_indexed(uint32_t index,tlb_item_t *tlb_item); +void mmu_tlb_write_random(tlb_item_t *tlb_item); +void mmu_tlb_read(uint32_t index,tlb_item_t *tlb_item); +uint32_t mmu_tlb_find(uint64_t vpn,uint32_t asid,uint32_t *index); +void mmu_tlb_item_init(tlb_item_t *tlb_item); +void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t asid,uint32_t global); +uint32_t mmu_tlb_get_random(); +uint32_t mmu_tlb_get_index(); +void mmu_tlb_set_index(uint32_t index); +uint32_t mmu_tlb_is_matched(); +uint64_t mmu_tlb_get_bad_vaddr(); + +void tlb_dump(); + +#endif
\ No newline at end of file diff --git a/libcpu/mips/gs264/mipscfg.c b/libcpu/mips/gs264/mipscfg.c new file mode 100644 index 0000000000..b2aed120ae --- /dev/null +++ b/libcpu/mips/gs264/mipscfg.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-07-28 lizhirui first version + */ +#include <rtthread.h> +#include <mips.h> + +mips32_core_cfg_t g_mips_core = +{ + 64, /* icache_line_size */ + 128, /* icache_lines_per_way */ + 4, /* icache_ways */ + 32768, + 64, /* dcache_line_size */ + 128, /* dcache_lines_per_way */ + 4, /* dcache_ways */ + 32768, + 64, /* max_tlb_entries */ +}; + +static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) +{ + rt_uint16_t rets = 1; + + while (n--) + rets *= b; + + return rets; +} + +static rt_uint16_t m_log2(rt_uint16_t b) +{ + rt_uint16_t rets = 0; + + while (b != 1) + { + b /= 2; + rets++; + } + + return rets; +} + +/** + * read core attribute + */ +void mips32_cfg_init(void) +{ + rt_uint16_t val; + rt_uint32_t cp0_config1; + + cp0_config1 = read_c0_config(); + if (cp0_config1 & 0x80000000) + { + cp0_config1 = read_c0_config1(); + + val = (cp0_config1 & (7<<22))>>22; + g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<19))>>19; + g_mips_core.icache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<16))>>16; + g_mips_core.icache_ways = val + 1; + + val = (cp0_config1 & (7<<13))>>13; + g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); + val = (cp0_config1 & (7<<10))>>10; + g_mips_core.dcache_line_size = 2 * m_pow(2, val); + val = (cp0_config1 & (7<<7))>>7; + g_mips_core.dcache_ways = val + 1; + + val = (cp0_config1 & (0x3F<<25))>>25; + g_mips_core.max_tlb_entries = val + 1; + } +} diff --git a/libcpu/mips/gs264/mmu.c b/libcpu/mips/gs264/mmu.c new file mode 100644 index 0000000000..b5bedace50 --- /dev/null +++ b/libcpu/mips/gs264/mmu.c @@ -0,0 +1,819 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2012-01-10 bernard porting to AM1808 + * 2020-07-26 lizhirui porting to ls2k + */ + +#include <rtthread.h> +#include <rthw.h> +#include <board.h> + +#include "cache.h" +#include "mips_mmu.h" +#include "mmu.h" + +void *current_mmu_table = RT_NULL; + +void *mmu_table_get() +{ + return current_mmu_table; +} + +void switch_mmu(void *mmu_table) +{ + current_mmu_table = mmu_table; + + mmu_clear_tlb(); + mmu_clear_itlb(); +} + +/* dump 2nd level page table */ +void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb) +{ + int i; + int fcnt = 0; + + for (i = 0; i < 256; i++) + { + rt_uint32_t pte2 = ptb[i]; + if ((pte2 & 0x3) == 0) + { + if (fcnt == 0) + rt_kprintf(" "); + rt_kprintf("%04x: ", i); + fcnt++; + if (fcnt == 16) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + continue; + } + if (fcnt != 0) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + + rt_kprintf(" %04x: %x: ", i, pte2); + if ((pte2 & 0x3) == 0x1) + { + rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n", + ((pte2 >> 7) | (pte2 >> 4))& 0xf, + (pte2 >> 15) & 0x1, + ((pte2 >> 10) | (pte2 >> 2)) & 0x1f); + } + else + { + rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n", + ((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1, + ((pte2 >> 4) | (pte2 >> 2)) & 0x1f); + } + } +} + +void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb) +{ + int i; + int fcnt = 0; + + rt_kprintf("page table@%p\n", ptb); + for (i = 0; i < 1024*4; i++) + { + rt_uint32_t pte1 = ptb[i]; + if ((pte1 & 0x3) == 0) + { + rt_kprintf("%03x: ", i); + fcnt++; + if (fcnt == 16) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + continue; + } + if (fcnt != 0) + { + rt_kprintf("fault\n"); + fcnt = 0; + } + + rt_kprintf("%03x: %08x: ", i, pte1); + if ((pte1 & 0x3) == 0x3) + { + rt_kprintf("LPAE\n"); + } + else if ((pte1 & 0x3) == 0x1) + { + rt_kprintf("pte,ns:%d,domain:%d\n", + (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf); + /* + *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000) + * - 0x80000000 + 0xC0000000)); + */ + } + else if (pte1 & (1 << 18)) + { + rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10))& 0xf, + (pte1 >> 4) & 0x1, + ((pte1 >> 10) | (pte1 >> 2)) & 0x1f); + } + else + { + rt_kprintf("section,ns:%d,ap:%x," + "xn:%d,texcb:%02x,domain:%d\n", + (pte1 >> 19) & 0x1, + ((pte1 >> 13) | (pte1 >> 10))& 0xf, + (pte1 >> 4) & 0x1, + (((pte1 & (0x7 << 12)) >> 10) | + ((pte1 & 0x0c) >> 2)) & 0x1f, + (pte1 >> 5) & 0xf); + } + } +} + +/* level1 page table, each entry for 1MB memory. */ +volatile unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024))); +void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart, + rt_uint32_t vaddrEnd, + rt_uint32_t paddrStart, + rt_uint32_t attr) +{ + volatile rt_uint32_t *pTT; + volatile int i, nSec; + pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20); + nSec = (vaddrEnd >> 20) - (vaddrStart >> 20); + for(i = 0; i <= nSec; i++) + { + *pTT = attr | (((paddrStart >> 20) + i) << 20); + pTT++; + } +} + +unsigned long rt_hw_set_domain_register(unsigned long domain_val) +{ + unsigned long old_domain; + + //asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain)); + //asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory"); + + return old_domain; +} + +void rt_hw_cpu_dcache_clean(void *addr, int size); +void rt_hw_init_mmu_table(struct mem_desc *mdesc, rt_uint32_t size) +{ + /* set page table */ + for(; size > 0; size--) + { + rt_hw_mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end, + mdesc->paddr_start, mdesc->attr); + mdesc++; + } + rt_hw_cpu_dcache_clean((void*)MMUTable, sizeof MMUTable); +} + +void rt_hw_mmu_init(void) +{ + rt_cpu_dcache_clean_flush(); + rt_cpu_icache_flush(); + rt_hw_cpu_dcache_disable(); + rt_hw_cpu_icache_disable(); + rt_cpu_mmu_disable(); + + /*rt_hw_cpu_dump_page_table(MMUTable);*/ + rt_hw_set_domain_register(0x55555555); + + rt_cpu_tlb_set(MMUTable); + + rt_cpu_mmu_enable(); + + rt_hw_cpu_icache_enable(); + rt_hw_cpu_dcache_enable(); +} + +/* + mem map +*/ + +void rt_hw_cpu_dcache_clean(void *addr, int size); + +int rt_hw_mmu_map_init(rt_mmu_info *mmu_info, void* v_address, size_t size, size_t *vtable, size_t pv_off) +{ + size_t l1_off, va_s, va_e; + rt_base_t level; + + if (!mmu_info || !vtable) + { + return -1; + } + + va_s = (size_t)v_address; + va_e = (size_t)v_address + size - 1; + + if ( va_e < va_s) + { + return -1; + } + + va_s >>= ARCH_SECTION_SHIFT; + va_e >>= ARCH_SECTION_SHIFT; + + if (va_s == 0) + { + return -1; + } + + level = rt_hw_interrupt_disable(); + + for (l1_off = va_s; l1_off <= va_e; l1_off++) + { + size_t v = vtable[l1_off]; + + if (v & ARCH_MMU_USED_MASK) + { + rt_kprintf("Error:vtable[%d] = 0x%p(is not zero),va_s = 0x%p,va_e = 0x%p!\n",l1_off,v,va_s,va_e); + rt_hw_interrupt_enable(level); + return -1; + } + } + + mmu_info->vtable = vtable; + mmu_info->vstart = va_s; + mmu_info->vend = va_e; + mmu_info->pv_off = pv_off; + + rt_hw_interrupt_enable(level); + + return 0; +} + +static size_t find_vaddr(rt_mmu_info *mmu_info, int pages) +{ + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; + size_t find_off = 0; + size_t find_va = 0; + int n = 0; + + if (!pages) + { + return 0; + } + + if (!mmu_info) + { + return 0; + } + + for (l1_off = mmu_info->vstart; l1_off <= mmu_info->vend; l1_off++) + { + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + if (*mmu_l1 & ARCH_MMU_USED_MASK) + { + mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); + for (l2_off = 0; l2_off < (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE); l2_off++) + { + if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK) + { + /* in use */ + n = 0; + } + else + { + if (!n) + { + find_va = l1_off; + find_off = l2_off; + } + n++; + if (n >= pages) + { + return (find_va << ARCH_SECTION_SHIFT) + (find_off << ARCH_PAGE_SHIFT); + } + } + } + } + else + { + if (!n) + { + find_va = l1_off; + find_off = 0; + } + n += (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE); + if (n >= pages) + { + return (find_va << ARCH_SECTION_SHIFT) + (find_off << ARCH_PAGE_SHIFT); + } + } + } + return 0; +} + +#ifdef RT_USING_USERSPACE +static int check_vaddr(rt_mmu_info *mmu_info, void *va, int pages) +{ + size_t loop_va = (size_t)va & ~ARCH_PAGE_MASK; + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; + + if (!pages) + { + return -1; + } + + if (!mmu_info) + { + return -1; + } + + while (pages--) + { + l1_off = (loop_va >> ARCH_SECTION_SHIFT); + l2_off = ((loop_va & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT); + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + + if (*mmu_l1 & ARCH_MMU_USED_MASK) + { + mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); + if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK) + { + return -1; + } + } + loop_va += ARCH_PAGE_SIZE; + } + return 0; +} +#endif + +static void __rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t npages) +{ + size_t loop_va = (size_t)v_addr & ~ARCH_PAGE_MASK; + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; + size_t *ref_cnt; + + if (!mmu_info) + { + return; + } + + while (npages--) + { + l1_off = (loop_va >> ARCH_SECTION_SHIFT); + if (l1_off < mmu_info->vstart || l1_off > mmu_info->vend) + { + return; + } + + l2_off = ((loop_va & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT); + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + + if (*mmu_l1 & ARCH_MMU_USED_MASK) + { + mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); + } + else + { + return; + } + + if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK) + { + *(mmu_l2 + l2_off) = 0; + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l2 + l2_off, 4); + + ref_cnt = mmu_l2 + (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE); + (*ref_cnt)--; + if (!*ref_cnt) + { +#ifdef RT_USING_USERSPACE + rt_pages_free(mmu_l2, 0); +#else + rt_free_align(mmu_l2); +#endif + *mmu_l1 = 0; + + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l1, 4); + } + } + loop_va += ARCH_PAGE_SIZE; + } +} + +static int __rt_hw_mmu_map(rt_mmu_info *mmu_info, void* v_addr, void* p_addr, size_t npages, size_t attr) +{ + size_t loop_va = (size_t)v_addr & ~ARCH_PAGE_MASK; + size_t loop_pa = (size_t)p_addr & ~ARCH_PAGE_MASK; + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; + size_t *ref_cnt; + + if (!mmu_info) + { + return -1; + } + + while (npages--) + { + l1_off = (loop_va >> ARCH_SECTION_SHIFT); + l2_off = ((loop_va & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT); + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + + if (*mmu_l1 & ARCH_MMU_USED_MASK) + { + mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); + } + else + { +#ifdef RT_USING_USERSPACE + mmu_l2 = (size_t*)rt_pages_alloc(0); +#else + mmu_l2 = (size_t*)rt_malloc_align(ARCH_PAGE_TBL_SIZE * 2, ARCH_PAGE_TBL_SIZE); +#endif + if (mmu_l2) + { + rt_memset(mmu_l2, 0, ARCH_PAGE_TBL_SIZE * 2); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l2, ARCH_PAGE_TBL_SIZE); + + *mmu_l1 = (((size_t)mmu_l2 + mmu_info->pv_off) | 0x1); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l1, 4); + } + else + { + /* error, unmap and quit */ + __rt_hw_mmu_unmap(mmu_info, v_addr, npages); + return -1; + } + } + + ref_cnt = mmu_l2 + (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE); + (*ref_cnt)++; + + *(mmu_l2 + l2_off) = (loop_pa | attr); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l2 + l2_off, 4); + + loop_va += ARCH_PAGE_SIZE; + loop_pa += ARCH_PAGE_SIZE; + } + return 0; +} + +static void rt_hw_cpu_tlb_invalidate(void) +{ + mmu_clear_tlb(); + mmu_clear_itlb(); +} + +#ifdef RT_USING_USERSPACE +void *_rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void* p_addr, size_t size, size_t attr) +{ + size_t pa_s, pa_e; + size_t vaddr; + int pages; + int ret; + + if (!size) + { + return 0; + } + pa_s = (size_t)p_addr; + pa_e = (size_t)p_addr + size - 1; + pa_s >>= ARCH_PAGE_SHIFT; + pa_e >>= ARCH_PAGE_SHIFT; + pages = pa_e - pa_s + 1; + if (v_addr) + { + vaddr = (size_t)v_addr; + pa_s = (size_t)p_addr; + if ((vaddr & ARCH_PAGE_MASK) != (pa_s & ARCH_PAGE_MASK)) + { + return 0; + } + vaddr &= ~ARCH_PAGE_MASK; + if (check_vaddr(mmu_info, (void*)vaddr, pages) != 0) + { + return 0; + } + } + else + { + vaddr = find_vaddr(mmu_info, pages); + } + if (vaddr) { + ret = __rt_hw_mmu_map(mmu_info, (void*)vaddr, p_addr, pages, attr); + if (ret == 0) + { + rt_hw_cpu_tlb_invalidate(); + return (void*)(vaddr + ((size_t)p_addr & ARCH_PAGE_MASK)); + } + } + return 0; +} +#else +void *_rt_hw_mmu_map(rt_mmu_info *mmu_info, void* p_addr, size_t size, size_t attr) +{ + size_t pa_s, pa_e; + size_t vaddr; + int pages; + int ret; + + pa_s = (size_t)p_addr; + pa_e = (size_t)p_addr + size - 1; + pa_s >>= ARCH_PAGE_SHIFT; + pa_e >>= ARCH_PAGE_SHIFT; + pages = pa_e - pa_s + 1; + vaddr = find_vaddr(mmu_info, pages); + if (vaddr) { + ret = __rt_hw_mmu_map(mmu_info, (void*)vaddr, p_addr, pages, attr); + if (ret == 0) + { + rt_hw_cpu_tlb_invalidate(); + return (void*)(vaddr + ((size_t)p_addr & ARCH_PAGE_MASK)); + } + } + return 0; +} +#endif + +#ifdef RT_USING_USERSPACE +static int __rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void* v_addr, size_t npages, size_t attr) +{ + size_t loop_va = (size_t)v_addr & ~ARCH_PAGE_MASK; + size_t loop_pa; + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; + size_t *ref_cnt; + + if (!mmu_info) + { + return -1; + } + + while (npages--) + { + loop_pa = (size_t)rt_pages_alloc(0) + mmu_info->pv_off; + if (!loop_pa) + goto err; + + //rt_kprintf("vaddr = %08x is mapped to paddr = %08x\n",v_addr,loop_pa); + l1_off = (loop_va >> ARCH_SECTION_SHIFT); + l2_off = ((loop_va & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT); + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + + if (*mmu_l1 & ARCH_MMU_USED_MASK) + { + mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); + } + else + { + //mmu_l2 = (size_t*)rt_malloc_align(ARCH_PAGE_TBL_SIZE * 2, ARCH_PAGE_TBL_SIZE); + mmu_l2 = (size_t*)rt_pages_alloc(0); + if (mmu_l2) + { + rt_memset(mmu_l2, 0, ARCH_PAGE_TBL_SIZE * 2); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l2, ARCH_PAGE_TBL_SIZE); + + *mmu_l1 = (((size_t)mmu_l2 + mmu_info->pv_off) | 0x1); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l1, 4); + } + else + goto err; + } + + ref_cnt = mmu_l2 + (ARCH_SECTION_SIZE/ARCH_PAGE_SIZE); + (*ref_cnt)++; + + //loop_pa += mmu_info->pv_off; + *(mmu_l2 + l2_off) = (loop_pa | attr); + /* cache maintain */ + rt_hw_cpu_dcache_clean(mmu_l2 + l2_off, 4); + + loop_va += ARCH_PAGE_SIZE; + } + return 0; +err: + { + /* error, unmap and quit */ + int i; + void *va, *pa; + + va = (void*)((size_t)v_addr & ~ARCH_PAGE_MASK); + for (i = 0; i < npages; i++) + { + pa = rt_hw_mmu_v2p(mmu_info, va); + pa -= mmu_info->pv_off; + rt_pages_free(pa, 0); + va += ARCH_PAGE_SIZE; + } + + __rt_hw_mmu_unmap(mmu_info, v_addr, npages); + return -1; + } +} + +void *_rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void *v_addr, size_t size, size_t attr) +{ + size_t vaddr; + size_t offset; + int pages; + int ret; + + if (!size) + { + return 0; + } + offset = (size_t)v_addr & ARCH_PAGE_MASK; + size += (offset + ARCH_PAGE_SIZE - 1); + pages = (size >> ARCH_PAGE_SHIFT); + if (v_addr) + { + vaddr = (size_t)v_addr; + vaddr &= ~ARCH_PAGE_MASK; + if (check_vaddr(mmu_info, (void*)vaddr, pages) != 0) + { + return 0; + } + } + else + { + vaddr = find_vaddr(mmu_info, pages); + } + if (vaddr) { + ret = __rt_hw_mmu_map_auto(mmu_info, (void*)vaddr, pages, attr); + if (ret == 0) + { + rt_hw_cpu_tlb_invalidate(); + return (void*)vaddr + offset; + } + } + return 0; +} +#endif + +void _rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t size) +{ + size_t va_s, va_e; + int pages; + + va_s = (size_t)v_addr; + va_e = (size_t)v_addr + size - 1; + va_s >>= ARCH_PAGE_SHIFT; + va_e >>= ARCH_PAGE_SHIFT; + pages = va_e - va_s + 1; + __rt_hw_mmu_unmap(mmu_info, v_addr, pages); + rt_hw_cpu_tlb_invalidate(); +} + +//va --> pa +void *rt_hw_kernel_virt_to_phys(void *v_addr, size_t size) +{ + void *p_addr = 0; + + return p_addr; +} + +//pa --> va +void *rt_hw_kernel_phys_to_virt(void *p_addr, size_t size) +{ + void *v_addr = 0; + + #ifdef RT_USING_USERSPACE + extern rt_mmu_info mmu_info; + v_addr = rt_hw_mmu_map(&mmu_info, 0, p_addr, size, MMU_MAP_K_RW); + #else + v_addr = p_addr; + #endif + + return v_addr; +} + +#ifdef RT_USING_USERSPACE +void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void* p_addr, size_t size, size_t attr) +{ + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_map(mmu_info, v_addr, p_addr, size, attr); + rt_hw_interrupt_enable(level); + return ret; +} + +void *rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void *v_addr, size_t size, size_t attr) +{ + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_map_auto(mmu_info, v_addr, size, attr); + rt_hw_interrupt_enable(level); + return ret; +} +#endif + +void rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t size) +{ + rt_base_t level; + + level = rt_hw_interrupt_disable(); + _rt_hw_mmu_unmap(mmu_info, v_addr, size); + rt_hw_interrupt_enable(level); +} + +void *_rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void* v_addr) +{ + size_t l1_off, l2_off; + size_t *mmu_l1, *mmu_l2; + size_t tmp; + size_t pa; + + l1_off = (size_t)v_addr >> ARCH_SECTION_SHIFT; + + if (!mmu_info) + { + return (void*)0; + } + + mmu_l1 = (size_t*)mmu_info->vtable + l1_off; + + tmp = *mmu_l1; + + switch (tmp & ARCH_MMU_USED_MASK) + { + case 0: /* not used */ + break; + case 1: /* page table */ + mmu_l2 = (size_t *)((tmp & ~ARCH_PAGE_TBL_MASK) - mmu_info->pv_off); + l2_off = (((size_t)v_addr & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT); + pa = *(mmu_l2 + l2_off); + if (pa & ARCH_MMU_USED_MASK) + { + if ((pa & ARCH_MMU_USED_MASK) == 1) + { + /* lage page, not support */ + break; + } + pa &= ~(ARCH_PAGE_MASK); + pa += ((size_t)v_addr & ARCH_PAGE_MASK); + return (void*)pa; + } + break; + case 2: + case 3: + /* section */ + if (tmp & ARCH_TYPE_SUPERSECTION) + { + /* super section, not support */ + break; + } + pa = (tmp & ~ARCH_SECTION_MASK); + pa += ((size_t)v_addr & ARCH_SECTION_MASK); + return (void*)pa; + } + return (void*)0; +} + +void *rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void* v_addr) +{ + void *ret; + rt_base_t level; + + level = rt_hw_interrupt_disable(); + ret = _rt_hw_mmu_v2p(mmu_info, v_addr); + rt_hw_interrupt_enable(level); + return ret; +} + +#ifdef RT_USING_USERSPACE +void init_mm_setup(unsigned int *mtbl, unsigned int size, unsigned int pv_off) { + unsigned int va; + + for (va = 0; va < 0x1000; va++) { + unsigned int vaddr = (va << 20); + if (vaddr >= KERNEL_VADDR_START && vaddr - KERNEL_VADDR_START < size) { + mtbl[va] = ((va << 20) + pv_off) | NORMAL_MEM; + } else if (vaddr >= (KERNEL_VADDR_START + pv_off) && vaddr - (KERNEL_VADDR_START + pv_off) < size) { + mtbl[va] = (va << 20) | NORMAL_MEM; + } else { + mtbl[va] = 0; + } + } +} +#endif diff --git a/libcpu/mips/gs264/mmu.h b/libcpu/mips/gs264/mmu.h new file mode 100644 index 0000000000..2472bf975f --- /dev/null +++ b/libcpu/mips/gs264/mmu.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-25 quanzhao the first version + * 2020-07-26 lizhirui porting to ls2k + */ +#ifndef __MMU_H_ +#define __MMU_H_ + +#include <rtthread.h> + +#define DESC_SEC (0x2) +#define MEMWBWA ((1<<12)|(3<<2)) /* write back, write allocate */ +#define MEMWB (3<<2) /* write back, no write allocate */ +#define MEMWT (2<<2) /* write through, no write allocate */ +#define SHAREDEVICE (1<<2) /* shared device */ +#define STRONGORDER (0<<2) /* strong ordered */ +#define XN (1<<4) /* execute Never */ +#ifdef RT_USING_USERSPACE +#define AP_RW (1<<10) /* supervisor=RW, user=No */ +#define AP_RO ((1<<10) |(1 << 15)) /* supervisor=RW, user=No */ +#else +#define AP_RW (3<<10) /* supervisor=RW, user=RW */ +#define AP_RO ((2<<10) /* supervisor=RW, user=RO */ +#endif + +#define SHARED (1<<16) /* shareable */ + +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) + +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) + +/* device mapping type */ +#define DEVICE_MEM (SHARED|AP_RW|DOMAIN0|SHAREDEVICE|DESC_SEC|XN) +/* normal memory mapping type */ +#define NORMAL_MEM (SHARED|AP_RW|DOMAIN0|MEMWBWA|DESC_SEC) + +#define STRONG_ORDER_MEM (SHARED|AP_RO|XN|DESC_SEC) + +struct mem_desc +{ + rt_uint32_t vaddr_start; + rt_uint32_t vaddr_end; + rt_uint32_t paddr_start; + rt_uint32_t attr; +}; + +#define MMU_MAP_MTBL_XN (1<<0) +#define MMU_MAP_MTBL_A (1<<1) +#define MMU_MAP_MTBL_B (1<<2) +#define MMU_MAP_MTBL_C (1<<3) +#define MMU_MAP_MTBL_AP01(x) (x<<4) +#define MMU_MAP_MTBL_TEX(x) (x<<6) +#define MMU_MAP_MTBL_AP2(x) (x<<9) +#define MMU_MAP_MTBL_SHARE (1<<10) + +#define MMU_MAP_K_RO (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(1)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_K_RWCB (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_K_RW (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_K_DEVICE (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_U_RO (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(1)|MMU_MAP_MTBL_AP01(2)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_U_RWCB (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_U_RW (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_SHARE) +#define MMU_MAP_U_DEVICE (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_SHARE) + +#define ARCH_SECTION_SHIFT 20 +#define ARCH_SECTION_SIZE (1 << ARCH_SECTION_SHIFT) +#define ARCH_SECTION_MASK (ARCH_SECTION_SIZE - 1) +#define ARCH_PAGE_SHIFT 14 +#define ARCH_PAGE_SIZE (1 << ARCH_PAGE_SHIFT) +#define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1) +#define ARCH_PAGE_TBL_SHIFT 10 +#define ARCH_PAGE_TBL_SIZE (1 << ARCH_PAGE_TBL_SHIFT) +#define ARCH_PAGE_TBL_MASK (ARCH_PAGE_TBL_SIZE - 1) + +#define ARCH_MMU_USED_MASK 3 + +#define ARCH_TYPE_SUPERSECTION (1 << 18) + +typedef struct +{ + size_t *vtable; + size_t vstart; + size_t vend; + size_t pv_off; +} rt_mmu_info; + +void *mmu_table_get(); +void switch_mmu(void *mmu_table); + +int rt_hw_mmu_map_init(rt_mmu_info *mmu_info, void* v_address, size_t size, size_t *vtable, size_t pv_off); +#ifdef RT_USING_USERSPACE +void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void* p_addr, size_t size, size_t attr); +void *rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void *v_addr, size_t size, size_t attr); +#else +void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void* p_addr, size_t size, size_t attr); +#endif +void rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t size); +void *rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void* v_addr); + +void *rt_hw_kernel_phys_to_virt(void *p_addr, size_t size); +void *rt_hw_kernel_virt_to_phys(void *v_addr, size_t size); + +#endif diff --git a/libcpu/mips/loongson_1b/cache.c b/libcpu/mips/loongson_1b/cache.c deleted file mode 100644 index 842f392cb7..0000000000 --- a/libcpu/mips/loongson_1b/cache.c +++ /dev/null @@ -1,230 +0,0 @@ -/* - * File : cache.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-07-09 Bernard first version - * 2011-08-08 lgnq modified for LS1B - */ - -#include <rtthread.h> -#include "../common/mipsregs.h" - -#define K0BASE 0x80000000 -#define PRID_LS1B 0x4220 - -extern void Clear_TagLo (void); -extern void Invalidate_Icache_Ls1b(unsigned int); -extern void Invalidate_Dcache_ClearTag_Ls1b(unsigned int); -extern void Invalidate_Dcache_Fill_Ls1b(unsigned int); -extern void Writeback_Invalidate_Dcache(unsigned int); -extern void enable_cpu_cache(void); - -typedef struct cacheinfo_t -{ - unsigned int icache_size; - unsigned int dcache_size; - unsigned int icacheline_size; - unsigned int dcacheline_size; -} cacheinfo_t ; - -typedef struct cacheop_t -{ - void (*Clear_TagLo) (void); - void (*Invalidate_Icache) (unsigned int); - void (*Invalidate_Dcache_Fill) (unsigned int); - void (*Invalidate_Dcache_ClearTag) (unsigned int); - void (*Init_Cache)(void); -} cacheop_t ; - -static cacheop_t cacheop, *pcacheop; -static cacheinfo_t cacheinfo, *pcacheinfo; - -int identify_cpu(void) -{ - unsigned int cpu_id; - - pcacheop = &cacheop; - pcacheinfo = &cacheinfo; - - rt_kprintf("CPU configure: 0x%08x\n", read_c0_config()); - cpu_id = read_c0_prid(); - switch (cpu_id) - { - case PRID_LS1B: - rt_kprintf("CPU:LS1B\n"); - pcacheop->Clear_TagLo = Clear_TagLo; - pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1b; - pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1b; - pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1b; - break; - default: - rt_kprintf("Unknown CPU type, system halted!\n"); - while (1) - { - ; - } - break; - } - - return 0; -} - -void probe_cache(void) -{ - unsigned int config1 = read_c0_config1(); - unsigned int icache_size, icache_line_size, icache_sets, icache_ways; - unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways; - - if ((icache_line_size = ((config1 >> 19) & 7))) - icache_line_size = 2 << icache_line_size; - else - icache_line_size = icache_line_size; - icache_sets = 64 << ((config1 >> 22) & 7); - icache_ways = 1 + ((config1 >> 16) & 7); - icache_size = icache_sets * icache_ways * icache_line_size; - - if ((dcache_line_size = ((config1 >> 10) & 7))) - dcache_line_size = 2 << dcache_line_size; - else - dcache_line_size = dcache_line_size; - dcache_sets = 64 << ((config1 >> 13) & 7); - dcache_ways = 1 + ((config1 >> 7) & 7); - dcache_size = dcache_sets * dcache_ways * dcache_line_size; - - rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size); - rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size); - - pcacheinfo->icache_size = icache_size; - pcacheinfo->dcache_size = dcache_size; - pcacheinfo->icacheline_size = icache_line_size; - pcacheinfo->dcacheline_size = dcache_line_size; - - return ; -} - -void invalidate_writeback_dcache_all(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - - while (start < end) - { - Writeback_Invalidate_Dcache(start); //hit writeback invalidate - start += pcacheinfo->dcacheline_size; - } -} - -void invalidate_writeback_dcache(unsigned long addr, int size) -{ - unsigned long start, end; - - start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size); - end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size); - - while (start <end) - { - Writeback_Invalidate_Dcache(start); - start += pcacheinfo->dcacheline_size; - } -} - -void invalidate_icache_all(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->icache_size); - - while (start < end) - { - pcacheop->Invalidate_Icache(start); - start += pcacheinfo->icacheline_size; - } -} - -void invalidate_dcache_all(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - while (start <end) - { - Invalidate_Dcache_Fill_Ls1b(start); - start += pcacheinfo->icacheline_size; - } -} - -//with cache disabled -void init_dcache(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - - while (start < end) - { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; - } - -} - -void rt_hw_cache_init(void) -{ - unsigned int start, end; - - /* 1. identify cpu and probe cache */ - identify_cpu(); - probe_cache(); - - start = K0BASE; - end = (start + pcacheinfo->icache_size); - - /* - * 2. clear CP0 taglo/taghi register; - */ - pcacheop->Clear_TagLo(); - - /* - * 3. invalidate instruction cache; - */ - while (start < end) - { - pcacheop->Invalidate_Icache(start); //index invalidate icache - start += pcacheinfo->icacheline_size; - } - - /* - * 4. invalidate data cache; - */ - start = K0BASE; - end = (start + pcacheinfo->dcache_size); - while(start < end) - { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; - } - - start = K0BASE; - while(start < end) - { - pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache - start += pcacheinfo->dcacheline_size; - } - - start = K0BASE; - while(start < end) - { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; - } - - /* enable cache */ - enable_cpu_cache(); - rt_kprintf("enable cpu cache done\n"); - - return ; -} diff --git a/libcpu/mips/loongson_1b/cache.h b/libcpu/mips/loongson_1b/cache.h deleted file mode 100644 index b5c2d4501e..0000000000 --- a/libcpu/mips/loongson_1b/cache.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * File : cache.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-07-09 Bernard first version - * 2011-08-08 lgnq modified for LS1B - */ -#ifndef __CACHE_H__ -#define __CACHE_H__ - -/* - * Cache Operations - */ -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 -#define Index_Invalidate_SI 0x02 -#define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_D 0x0d -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_I 0x10 -#define Hit_Invalidate_D 0x11 -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Fill 0x14 -#define Hit_Writeback_Inv_D 0x15 -/* 0x16 is unused */ -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 -/* 0x1a is unused */ -#define Hit_Writeback_SD 0x1b -/* 0x1c is unused */ -/* 0x1e is unused */ -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f - -#endif diff --git a/libcpu/mips/loongson_1b/cache_gcc.S b/libcpu/mips/loongson_1b/cache_gcc.S deleted file mode 100644 index bb6f46de4c..0000000000 --- a/libcpu/mips/loongson_1b/cache_gcc.S +++ /dev/null @@ -1,217 +0,0 @@ -/* - * File : cache_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-09-11 bernard port to Loongson SoC3210 - * 2011-08-08 lgnq port to Loongson LS1B - */ -#include "../common/mipsregs.h" -#include "../common/mips.inc" -#include "../common/asm.h" -#include "cache.h" - - .ent cache_init - .global cache_init - .set noreorder -cache_init: - move t1,ra -####part 2#### -cache_detect_4way: - mfc0 t4, CP0_CONFIG - andi t5, t4, 0x0e00 - srl t5, t5, 9 #ic - andi t6, t4, 0x01c0 - srl t6, t6, 6 #dc - addiu t8, $0, 1 - addiu t9, $0, 2 - #set dcache way - beq t6, $0, cache_d1way - addiu t7, $0, 1 #1 way - beq t6, t8, cache_d2way - addiu t7, $0, 2 #2 way - beq $0, $0, cache_d4way - addiu t7, $0, 4 #4 way -cache_d1way: - beq $0, $0, 1f - addiu t6, t6, 12 #1 way -cache_d2way: - beq $0, $0, 1f - addiu t6, t6, 11 #2 way -cache_d4way: - addiu t6, t6, 10 #4 way (10), 2 way(11), 1 way(12) -1: #set icache way - beq t5, $0, cache_i1way - addiu t3, $0, 1 #1 way - beq t5, t8, cache_i2way - addiu t3, $0, 2 #2 way - beq $0, $0, cache_i4way - addiu t3, $0, 4 #4 way -cache_i1way: - beq $0, $0, 1f - addiu t5, t5, 12 -cache_i2way: - beq $0, $0, 1f - addiu t5, t5, 11 -cache_i4way: - addiu t5, t5, 10 #4 way (10), 2 way(11), 1 way(12) - -1: addiu t4, $0, 1 - sllv t6, t4, t6 - sllv t5, t4, t5 -#if 0 - la t0, memvar - sw t7, 0x0(t0) #ways - sw t5, 0x4(t0) #icache size - sw t6, 0x8(t0) #dcache size -#endif -####part 3#### - .set mips3 - lui a0, 0x8000 - addu a1, $0, t5 - addu a2, $0, t6 -cache_init_d2way: -#a0=0x80000000, a1=icache_size, a2=dcache_size -#a3, v0 and v1 used as local registers - mtc0 $0, CP0_TAGHI - addu v0, $0, a0 - addu v1, a0, a2 -1: slt a3, v0, v1 - beq a3, $0, 1f - nop - mtc0 $0, CP0_TAGLO - beq t7, 1, 4f - cache Index_Store_Tag_D, 0x0(v0) # 1 way - beq t7, 2 ,4f - cache Index_Store_Tag_D, 0x1(v0) # 2 way - cache Index_Store_Tag_D, 0x2(v0) # 4 way - cache Index_Store_Tag_D, 0x3(v0) -4: beq $0, $0, 1b - addiu v0, v0, 0x20 -1: -cache_flush_i2way: - addu v0, $0, a0 - addu v1, a0, a1 -1: slt a3, v0, v1 - beq a3, $0, 1f - nop - beq t3, 1, 4f - cache Index_Invalidate_I, 0x0(v0) # 1 way - beq t3, 2, 4f - cache Index_Invalidate_I, 0x1(v0) # 2 way - cache Index_Invalidate_I, 0x2(v0) - cache Index_Invalidate_I, 0x3(v0) # 4 way -4: beq $0, $0, 1b - addiu v0, v0, 0x20 -1: -cache_flush_d2way: - addu v0, $0, a0 - addu v1, a0, a2 -1: slt a3, v0, v1 - beq a3, $0, 1f - nop - beq t7, 1, 4f - cache Index_Writeback_Inv_D, 0x0(v0) #1 way - beq t7, 2, 4f - cache Index_Writeback_Inv_D, 0x1(v0) # 2 way - cache Index_Writeback_Inv_D, 0x2(v0) - cache Index_Writeback_Inv_D, 0x3(v0) # 4 way -4: beq $0, $0, 1b - addiu v0, v0, 0x20 -1: -cache_init_finish: - jr t1 - nop - .set reorder - .end cache_init - -########################### -# Enable CPU cache # -########################### - -LEAF(enable_cpu_cache) - .set noreorder - mfc0 t0, CP0_CONFIG - nop - and t0, ~0x03 - or t0, 0x03 - mtc0 t0, CP0_CONFIG - nop - .set reorder - j ra -END (enable_cpu_cache) - -########################### -# disable CPU cache # -########################### - -LEAF(disable_cpu_cache) - .set noreorder - mfc0 t0, CP0_CONFIG - nop - and t0, ~0x03 - or t0, 0x2 - mtc0 t0, CP0_CONFIG - nop - .set reorder - j ra -END (disable_cpu_cache) - -/**********************************/ -/* Invalidate Instruction Cache */ -/**********************************/ -LEAF(Clear_TagLo) - .set noreorder - mtc0 zero, CP0_TAGLO - nop - .set reorder - j ra -END(Clear_TagLo) - - .set mips3 -/**********************************/ -/* Invalidate Instruction Cache */ -/**********************************/ -LEAF(Invalidate_Icache_Ls1b) - .set noreorder - cache Index_Invalidate_I,0(a0) - cache Index_Invalidate_I,1(a0) - cache Index_Invalidate_I,2(a0) - cache Index_Invalidate_I,3(a0) - .set reorder - j ra -END(Invalidate_Icache_Ls1b) - -/**********************************/ -/* Invalidate Data Cache */ -/**********************************/ -LEAF(Invalidate_Dcache_ClearTag_Ls1b) - .set noreorder - cache Index_Store_Tag_D, 0(a0) # BDSLOT: clear tag - cache Index_Store_Tag_D, 1(a0) # BDSLOT: clear tag - .set reorder - j ra -END(Invalidate_Dcache_ClearTag_Ls1b) - -LEAF(Invalidate_Dcache_Fill_Ls1b) - .set noreorder - cache Index_Writeback_Inv_D, 0(a0) # BDSLOT: clear tag - cache Index_Writeback_Inv_D, 1(a0) # BDSLOT: clear tag - .set reorder - j ra -END(Invalidate_Dcache_Fill_Ls1b) - -LEAF(Writeback_Invalidate_Dcache) - .set noreorder - cache Hit_Writeback_Inv_D, (a0) - .set reorder - j ra -END(Writeback_Invalidate_Dcache) - .set mips0 diff --git a/libcpu/mips/loongson_1b/context_gcc.S b/libcpu/mips/loongson_1b/context_gcc.S deleted file mode 100644 index ce004dc716..0000000000 --- a/libcpu/mips/loongson_1b/context_gcc.S +++ /dev/null @@ -1,149 +0,0 @@ -/* - * File : context_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-09-11 bernard port to Loongson SoC3210 - * 2011-08-08 lgnq port to Loongson LS1B - */ - -#include "../common/mips.inc" -#include "../common/stackframe.h" - - .section ".text", "ax" - .set noreorder - -/* - * rt_base_t rt_hw_interrupt_disable() - */ - .globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mfc0 v0, CP0_STATUS - and v1, v0, 0xfffffffe - mtc0 v1, CP0_STATUS - jr ra - nop - -/* - * void rt_hw_interrupt_enable(rt_base_t level) - */ - .globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - mtc0 a0, CP0_STATUS - jr ra - nop - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) - * a0 --> from - * a1 --> to - */ - .globl rt_hw_context_switch -rt_hw_context_switch: - mtc0 ra, CP0_EPC - SAVE_ALL - - sw sp, 0(a0) /* store sp in preempted tasks TCB */ - lw sp, 0(a1) /* get new task stack pointer */ - - RESTORE_ALL_AND_RET - -/* - * void rt_hw_context_switch_to(rt_uint32 to)/* - * a0 --> to - */ - .globl rt_hw_context_switch_to -rt_hw_context_switch_to: - lw sp, 0(a0) /* get new task stack pointer */ - - RESTORE_ALL_AND_RET - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* - */ - .globl rt_thread_switch_interrupt_flag - .globl rt_interrupt_from_thread - .globl rt_interrupt_to_thread - .globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - la t0, rt_thread_switch_interrupt_flag - lw t1, 0(t0) - nop - bnez t1, _reswitch - nop - li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ - sw t1, 0(t0) - la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ - sw a0, 0(t0) -_reswitch: - la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ - sw a1, 0(t0) - jr ra - nop - -/* - * void rt_hw_context_switch_interrupt_do(rt_base_t flag) - */ - .globl rt_interrupt_enter - .globl rt_interrupt_leave - .globl mips_irq_handle -mips_irq_handle: - SAVE_ALL - - mfc0 t0, CP0_CAUSE - and t1, t0, 0xff - bnez t1, spurious_interrupt /* check exception */ - nop - - /* let k0 keep the current context sp */ - move k0, sp - /* switch to kernel stack */ - li sp, SYSTEM_STACK - - jal rt_interrupt_enter - nop - jal rt_interrupt_dispatch - nop - jal rt_interrupt_leave - nop - - /* switch sp back to thread's context */ - move sp, k0 - - /* - * if rt_thread_switch_interrupt_flag set, jump to - * rt_hw_context_switch_interrupt_do and don't return - */ - la k0, rt_thread_switch_interrupt_flag - lw k1, 0(k0) - beqz k1, spurious_interrupt - nop - sw zero, 0(k0) /* clear flag */ - nop - - /* - * switch to the new thread - */ - la k0, rt_interrupt_from_thread - lw k1, 0(k0) - nop - sw sp, 0(k1) /* store sp in preempted tasks's TCB */ - - la k0, rt_interrupt_to_thread - lw k1, 0(k0) - nop - lw sp, 0(k1) /* get new task's stack pointer */ - j spurious_interrupt - nop - -spurious_interrupt: - RESTORE_ALL_AND_RET - - .set reorder diff --git a/libcpu/mips/loongson_1b/cpuport.c b/libcpu/mips/loongson_1b/cpuport.c deleted file mode 100644 index c095c04814..0000000000 --- a/libcpu/mips/loongson_1b/cpuport.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * File : cpuport.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-07-09 Bernard first version - * 2010-09-11 Bernard add CPU reset implementation - */ - -#include <rtthread.h> -#include "ls1b.h" - -/** - * @addtogroup Loongson LS1B - */ - -/*@{*/ - -/** - * this function will reset CPU - * - */ -void rt_hw_cpu_reset(void) -{ - /* open the watch-dog */ - WDT_EN = 0x01; /* watch dog enable */ - WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ - WDT_SET = 0x01; /* watch dog start */ - - rt_kprintf("reboot system...\n"); - while (1); -} - -/** - * this function will shutdown CPU - * - */ -void rt_hw_cpu_shutdown(void) -{ - rt_kprintf("shutdown...\n"); - - while (1); -} - -extern rt_uint32_t cp0_get_cause(void); -extern rt_uint32_t cp0_get_status(void); -extern rt_uint32_t cp0_get_hi(void); -extern rt_uint32_t cp0_get_lo(void); - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - static rt_uint32_t g_sr = 0; - - if (g_sr == 0) - { - g_sr = cp0_get_status(); - g_sr &= 0xfffffffe; - g_sr |= 0x8401; - } - - /** Start at stack top */ - stk = (rt_uint32_t *)stack_addr; - *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ - *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ - *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ - *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ - *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ - *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ - *(--stk) = (rt_uint32_t) texit; /* ra */ - *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ - *(--stk) = (rt_uint32_t) stack_addr; /* sp */ - *(--stk) = (rt_uint32_t) 0x0000001c; /* gp */ - *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ - *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ - *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ - *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ - *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ - *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ - *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ - *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ - *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ - *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ - *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ - *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ - *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ - *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ - *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ - *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ - *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ - *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ - *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ - *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ - *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ - *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ - *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ - *(--stk) = (rt_uint32_t) parameter; /* a0 */ - *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ - *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ - *(--stk) = (rt_uint32_t) 0x00000001; /* at */ - *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - -/*@}*/ - diff --git a/libcpu/mips/loongson_1b/exception.c b/libcpu/mips/loongson_1b/exception.c deleted file mode 100644 index 4a3745cbc5..0000000000 --- a/libcpu/mips/loongson_1b/exception.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * File : cpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - */ -#include <rtthread.h> -#include <rthw.h> -#include "../common/exception.h" -#include "../common/mipsregs.h" - -/** - * @addtogroup Loongson - */ - -/*@{*/ - -/** - * exception handle table - */ -#define RT_EXCEPTION_MAX 8 -exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX]; - -/** - * setup the exception handle - */ -exception_func_t rt_set_except_vector(int n, exception_func_t func) -{ - exception_func_t old_handler = sys_exception_handlers[n]; - - if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func)) - { - return 0; - } - - sys_exception_handlers[n] = func; - - return old_handler; -} - -void tlb_refill_handler(void) -{ - rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); -} - -void cache_error_handler(void) -{ - rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); -} - -static void unhandled_exception_handle(pt_regs_t *regs) -{ - rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause()); -} - -void install_default_execpt_handle(void) -{ - rt_int32_t i; - - for (i=0; i<RT_EXCEPTION_MAX; i++) - sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle; -} - -void exception_handler(pt_regs_t *regs) -{ - rt_uint32_t cause; - rt_uint32_t index; - - cause = (read_c0_cause() & read_c0_config()); - cause = (cause & 0xfc00) >> 8; - - for (index = RT_EXCEPTION_MAX; index > 0; index --) - { - if (cause & (1 << index)) - { - sys_exception_handlers[index](regs); - cause &= ~(1 << index); - } - } -} - -/*@}*/ diff --git a/libcpu/mips/loongson_1b/interrupt.c b/libcpu/mips/loongson_1b/interrupt.c deleted file mode 100644 index 998d1e4918..0000000000 --- a/libcpu/mips/loongson_1b/interrupt.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-10-15 Bernard first version - * 2010-10-15 lgnq modified for LS1B - * 2013-03-29 aozima Modify the interrupt interface implementations. - */ - -#include <rtthread.h> -#include <rthw.h> -#include "ls1b.h" - -#define MAX_INTR 32 - -extern rt_uint32_t rt_interrupt_nest; -rt_uint32_t rt_interrupt_from_thread; -rt_uint32_t rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -static struct rt_irq_desc irq_handle_table[MAX_INTR]; -void rt_interrupt_dispatch(void *ptreg); -void rt_hw_timer_handler(); - -static struct ls1b_intc_regs volatile *ls1b_hw0_icregs -= (struct ls1b_intc_regs volatile *)(LS1B_INTREG_BASE); - -/** - * @addtogroup Loongson LS1B - */ - -/*@{*/ - -static void rt_hw_interrupt_handler(int vector, void *param) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} - -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init(void) -{ - rt_int32_t idx; - - /* pci active low */ - ls1b_hw0_icregs->int_pol = -1; //must be done here 20110802 lgnq - /* make all interrupts level triggered */ - (ls1b_hw0_icregs+0)->int_edge = 0x0000e000; - /* mask all interrupts */ - (ls1b_hw0_icregs+0)->int_clr = 0xffffffff; - - rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table)); - for (idx = 0; idx < MAX_INTR; idx ++) - { - irq_handle_table[idx].handler = rt_hw_interrupt_handler; - } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -/** - * This function will mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_mask(int vector) -{ - /* mask interrupt */ - (ls1b_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f)); -} - -/** - * This function will un-mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_umask(int vector) -{ - (ls1b_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f)); -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param new_handler the interrupt service routine to be installed - * @param old_handler the old interrupt service routine - */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) -{ - rt_isr_handler_t old_handler = RT_NULL; - - if (vector >= 0 && vector < MAX_INTR) - { - old_handler = irq_handle_table[vector].handler; - -#ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX); -#endif /* RT_USING_INTERRUPT_INFO */ - irq_handle_table[vector].handler = handler; - irq_handle_table[vector].param = param; - } - - return old_handler; -} - -void rt_interrupt_dispatch(void *ptreg) -{ - int irq; - void *param; - rt_isr_handler_t irq_func; - static rt_uint32_t status = 0; - rt_uint32_t c0_status; - rt_uint32_t c0_cause; - volatile rt_uint32_t cause_im; - volatile rt_uint32_t status_im; - rt_uint32_t pending_im; - - /* check os timer */ - c0_status = read_c0_status(); - c0_cause = read_c0_cause(); - - cause_im = c0_cause & ST0_IM; - status_im = c0_status & ST0_IM; - pending_im = cause_im & status_im; - - if (pending_im & CAUSEF_IP7) - { - rt_hw_timer_handler(); - } - - if (pending_im & CAUSEF_IP2) - { - /* the hardware interrupt */ - status = ls1b_hw0_icregs->int_isr; - if (!status) - return; - - for (irq = MAX_INTR; irq > 0; --irq) - { - if ((status & (1 << irq))) - { - status &= ~(1 << irq); - - irq_func = irq_handle_table[irq].handler; - param = irq_handle_table[irq].param; - - /* do interrupt */ - irq_func(irq, param); - -#ifdef RT_USING_INTERRUPT_INFO - irq_handle_table[irq].counter++; -#endif /* RT_USING_INTERRUPT_INFO */ - - /* ack interrupt */ - ls1b_hw0_icregs->int_clr |= (1 << irq); - } - } - } - else if (pending_im & CAUSEF_IP3) - { - rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); - } - else if (pending_im & CAUSEF_IP4) - { - rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); - } - else if (pending_im & CAUSEF_IP5) - { - rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); - } - else if (pending_im & CAUSEF_IP6) - { - rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__); - } -} - -/*@}*/ diff --git a/libcpu/mips/loongson_1b/ls1b.h b/libcpu/mips/loongson_1b/ls1b.h deleted file mode 100644 index 34393a3448..0000000000 --- a/libcpu/mips/loongson_1b/ls1b.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * File : ls1b.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2011, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-08-08 lgnq first version - */ - -#ifndef __LS1B_H__ -#define __LS1B_H__ - -#include "../common/mipsregs.h" - -#define LS1B_ACPI_IRQ 0 -#define LS1B_HPET_IRQ 1 -#define LS1B_UART0_IRQ 2 -#define LS1B_UART1_IRQ 3 -#define LS1B_UART2_IRQ 4 -#define LS1B_UART3_IRQ 5 -#define LS1B_CAN0_IRQ 6 -#define LS1B_CAN1_IRQ 7 -#define LS1B_SPI0_IRQ 8 -#define LS1B_SPI1_IRQ 9 -#define LS1B_AC97_IRQ 10 -#define LS1B_MS_IRQ 11 -#define LS1B_KB_IRQ 12 -#define LS1B_DMA0_IRQ 13 -#define LS1B_DMA1_IRQ 14 -#define LS1B_NAND_IRQ 15 -#define LS1B_I2C0_IRQ 16 -#define LS1B_I2C1_IRQ 17 -#define LS1B_PWM0_IRQ 18 -#define LS1B_PWM1_IRQ 19 -#define LS1B_PWM2_IRQ 20 -#define LS1B_PWM3_IRQ 21 -#define LS1B_LPC_IRQ 22 -#define LS1B_EHCI_IRQ 32 -#define LS1B_OHCI_IRQ 33 -#define LS1B_GMAC1_IRQ 34 -#define LS1B_GMAC2_IRQ 35 -#define LS1B_SATA_IRQ 36 -#define LS1B_GPU_IRQ 37 -#define LS1B_PCI_INTA_IRQ 38 -#define LS1B_PCI_INTB_IRQ 39 -#define LS1B_PCI_INTC_IRQ 40 -#define LS1B_PCI_INTD_IRQ 41 - -#define LS1B_GPIO_IRQ 64 -#define LS1B_GPIO_FIRST_IRQ 64 -#define LS1B_GPIO_IRQ_COUNT 96 -#define LS1B_GPIO_LAST_IRQ (LS1B_GPIO_FIRST_IRQ + LS1B_GPIO_IRQ_COUNT-1) - -#define INT_PCI_INTA (1<<6) -#define INT_PCI_INTB (1<<7) -#define INT_PCI_INTC (1<<8) -#define INT_PCI_INTD (1<<9) - -#define LS1B_LAST_IRQ 159 -#define MIPS_CPU_TIMER_IRQ 167 -#define LS1B_INTREG_BASE 0xbfd01040 - -#define LS1B_DMA_IRQ_BASE 168 -#define LS1B_DMA_IRQ_COUNT 16 - -struct ls1b_intc_regs -{ - volatile unsigned int int_isr; - volatile unsigned int int_en; - volatile unsigned int int_set; - volatile unsigned int int_clr; /* offset 0x10*/ - volatile unsigned int int_pol; - volatile unsigned int int_edge; /* offset 0 */ -}; - -struct ls1b_cop_global_regs -{ - volatile unsigned int control; - volatile unsigned int rd_inten; - volatile unsigned int wr_inten; - volatile unsigned int rd_intisr; /* offset 0x10*/ - volatile unsigned int wr_intisr; - unsigned int unused[11]; -} ; - -struct ls1b_cop_channel_regs -{ - volatile unsigned int rd_control; - volatile unsigned int rd_src; - volatile unsigned int rd_cnt; - volatile unsigned int rd_status; /* offset 0x10*/ - volatile unsigned int wr_control; - volatile unsigned int wr_src; - volatile unsigned int wr_cnt; - volatile unsigned int wr_status; /* offset 0x10*/ -} ; - -struct ls1b_cop_regs -{ - struct ls1b_cop_global_regs global; - struct ls1b_cop_channel_regs chan[8][2]; -} ; - -#define __REG8(addr) *((volatile unsigned char *)(addr)) -#define __REG16(addr) *((volatile unsigned short *)(addr)) -#define __REG32(addr) *((volatile unsigned int *)(addr)) - -#define GMAC0_BASE 0xBFE10000 -#define GMAC0_DMA_BASE 0xBFE11000 -#define GMAC1_BASE 0xBFE20000 -#define GMAC1_DMA_BASE 0xBFE21000 -#define I2C0_BASE 0xBFE58000 -#define PWM0_BASE 0xBFE5C000 -#define PWM1_BASE 0xBFE5C010 -#define PWM2_BASE 0xBFE5C020 -#define PWM3_BASE 0xBFE5C030 -#define WDT_BASE 0xBFE5C060 -#define RTC_BASE 0xBFE64000 -#define I2C1_BASE 0xBFE68000 -#define I2C2_BASE 0xBFE70000 -#define AC97_BASE 0xBFE74000 -#define NAND_BASE 0xBFE78000 -#define SPI_BASE 0xBFE80000 -#define CAN1_BASE 0xBF004300 -#define CAN0_BASE 0xBF004400 - -/* Watch Dog registers */ -#define WDT_EN __REG32(WDT_BASE + 0x00) -#define WDT_SET __REG32(WDT_BASE + 0x04) -#define WDT_TIMER __REG32(WDT_BASE + 0x08) - -#define PLL_FREQ __REG32(0xbfe78030) -#define PLL_DIV_PARAM __REG32(0xbfe78034) - -#endif diff --git a/libcpu/mips/loongson_1b/mipscfg.c b/libcpu/mips/loongson_1b/mipscfg.c deleted file mode 100644 index 10dd3fee9e..0000000000 --- a/libcpu/mips/loongson_1b/mipscfg.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * File : mipscfg.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-27 swkyer first version - */ -#include <rtthread.h> -#include "../common/mipsregs.h" -#include "../common/mipscfg.h" - -mips32_core_cfg_t g_mips_core = -{ - 16, /* icache_line_size */ - 256, /* icache_lines_per_way */ - 4, /* icache_ways */ - 16, /* dcache_line_size */ - 256, /* dcache_lines_per_way */ - 4, /* dcache_ways */ - 16, /* max_tlb_entries */ -}; - -static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) -{ - rt_uint16_t rets = 1; - - while (n--) - rets *= b; - - return rets; -} - -static rt_uint16_t m_log2(rt_uint16_t b) -{ - rt_uint16_t rets = 0; - - while (b != 1) - { - b /= 2; - rets++; - } - - return rets; -} - -/** - * read core attribute - */ -void mips32_cfg_init(void) -{ - rt_uint16_t val; - rt_uint32_t cp0_config1; - - cp0_config1 = read_c0_config(); - if (cp0_config1 & 0x80000000) - { - cp0_config1 = read_c0_config1(); - - val = (cp0_config1 & (7<<22))>>22; - g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<19))>>19; - g_mips_core.icache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<16))>>16; - g_mips_core.icache_ways = val + 1; - - val = (cp0_config1 & (7<<13))>>13; - g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<10))>>10; - g_mips_core.dcache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<7))>>7; - g_mips_core.dcache_ways = val + 1; - - val = (cp0_config1 & (0x3F<<25))>>25; - g_mips_core.max_tlb_entries = val + 1; - } -} diff --git a/libcpu/mips/loongson_1b/start_gcc.S b/libcpu/mips/loongson_1b/start_gcc.S deleted file mode 100644 index fd98335671..0000000000 --- a/libcpu/mips/loongson_1b/start_gcc.S +++ /dev/null @@ -1,137 +0,0 @@ -/* - * File : start_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-09-04 bernard porting to Jz47xx - */ - -#include "../common/mips.inc" -#include "../common/stackframe.h" - - .section ".start", "ax" - .set noreorder - - /* the program entry */ - .globl _start -_start: - .set noreorder - la ra, _start - - /* disable interrupt */ - mfc0 t0, CP0_STATUS - and t0, 0xfffffffe # By default it will be disabled. - mtc0 t0, CP0_STATUS # Set CPU to disable interrupt. - nop - - /* disable cache */ - mfc0 t0, CP0_CONFIG - and t0, 0xfffffff8 - or t0, 0x2 # disable,!default value is not it! - mtc0 t0, CP0_CONFIG # Set CPU to disable cache. - nop - - /* setup stack pointer */ - li sp, SYSTEM_STACK - la gp, _gp - - /* clear bss */ - la t0, __bss_start - la t1, __bss_end -_clr_bss_loop: - sw zero, 0(t0) - bne t0, t1, _clr_bss_loop - addiu t0, t0, 4 - - /* jump to RT-Thread RTOS */ - jal rtthread_startup - nop - - /* restart, never die */ - j _start - nop - .set reorder - - .globl cp0_get_cause -cp0_get_cause: - mfc0 v0, CP0_CAUSE - jr ra - nop - - .globl cp0_get_status -cp0_get_status: - mfc0 v0, CP0_STATUS - jr ra - nop - - .globl cp0_get_hi -cp0_get_hi: - mfhi v0 - jr ra - nop - - .globl cp0_get_lo -cp0_get_lo: - mflo v0 - jr ra - nop - - .extern tlb_refill_handler - .extern cache_error_handler - - /* Exception Handler */ - - /* 0x0 - TLB refill handler */ - .section .vectors.1, "ax", %progbits - .global tlb_refill_exception - .type tlb_refill_exception,@function -tlb_refill_exception: - j tlb_refill_handler - nop - - /* 0x100 - Cache error handler */ - .section .vectors.2, "ax", %progbits - j cache_error_handler - nop - - /* 0x180 - Exception/Interrupt handler */ - .section .vectors.3, "ax", %progbits - .global general_exception - .type general_exception,@function -general_exception: - j _general_exception_handler - nop - - /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */ - .section .vectors.4, "ax", %progbits - .global irq_exception - .type irq_exception,@function -irq_exception: - j _irq_handler - nop - - .section .vectors, "ax", %progbits - .extern mips_irq_handle - - /* general exception handler */ -_general_exception_handler: - .set noreorder - la k0, mips_irq_handle - jr k0 - nop - .set reorder - - /* interrupt handler */ -_irq_handler: - .set noreorder - la k0, mips_irq_handle - jr k0 - nop - .set reorder diff --git a/libcpu/mips/loongson_1c/cache.c b/libcpu/mips/loongson_1c/cache.c deleted file mode 100644 index bf97db9b4e..0000000000 --- a/libcpu/mips/loongson_1c/cache.c +++ /dev/null @@ -1,233 +0,0 @@ -/* - * File : cache.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-07-09 Bernard first version - * 2011-08-08 lgnq modified for LS1B - * 2015-07-08 chinesebear modified for loongson 1c - */ - -#include <rtthread.h> -#include "../common/mipsregs.h" - -#define K0BASE 0x80000000 -#define PRID_LS1C 0x4220 - -extern void Clear_TagLo (void); -extern void Invalidate_Icache_Ls1c(unsigned int); -extern void Invalidate_Dcache_ClearTag_Ls1c(unsigned int); -extern void Invalidate_Dcache_Fill_Ls1c(unsigned int); -extern void Writeback_Invalidate_Dcache(unsigned int); -extern void enable_cpu_cache(void); - -typedef struct cacheinfo_t -{ - unsigned int icache_size; - unsigned int dcache_size; - unsigned int icacheline_size; - unsigned int dcacheline_size; -} cacheinfo_t ; - -typedef struct cacheop_t -{ - void (*Clear_TagLo) (void); - void (*Invalidate_Icache) (unsigned int); - void (*Invalidate_Dcache_Fill) (unsigned int); - void (*Invalidate_Dcache_ClearTag) (unsigned int); - void (*Init_Cache)(void); -} cacheop_t ; - -static cacheop_t cacheop, *pcacheop; -static cacheinfo_t cacheinfo, *pcacheinfo; - -int identify_cpu(void) -{ - unsigned int cpu_id; - - pcacheop = &cacheop; - pcacheinfo = &cacheinfo; - - rt_kprintf("CPU configure: 0x%08x\n", read_c0_config()); - cpu_id = read_c0_prid(); - switch (cpu_id) - { - case PRID_LS1C: - rt_kprintf("CPU:Loongson 1C\n"); - pcacheop->Clear_TagLo = Clear_TagLo; - pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1c; - pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1c; - pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1c; - break; - default: - rt_kprintf("Unknown CPU type, system halted!\n"); - while (1) - { - ; - } - break; - } - - return 0; -} - -void probe_cache(void) -{ - unsigned int config1 = read_c0_config1(); - unsigned int icache_size, icache_line_size, icache_sets, icache_ways; - unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways; - - if ((icache_line_size = ((config1 >> 19) & 7))) - icache_line_size = 2 << icache_line_size; - else - icache_line_size = icache_line_size; - icache_sets = 64 << ((config1 >> 22) & 7); - icache_ways = 1 + ((config1 >> 16) & 7); - icache_size = icache_sets * icache_ways * icache_line_size; - - if ((dcache_line_size = ((config1 >> 10) & 7))) - dcache_line_size = 2 << dcache_line_size; - else - dcache_line_size = dcache_line_size; - dcache_sets = 64 << ((config1 >> 13) & 7); - dcache_ways = 1 + ((config1 >> 7) & 7); - dcache_size = dcache_sets * dcache_ways * dcache_line_size; - - rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size); - rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size); - - pcacheinfo->icache_size = icache_size; - pcacheinfo->dcache_size = dcache_size; - pcacheinfo->icacheline_size = icache_line_size; - pcacheinfo->dcacheline_size = dcache_line_size; - - return ; -} - -void invalidate_writeback_dcache_all(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - - while (start < end) - { - Writeback_Invalidate_Dcache(start); //hit writeback invalidate - start += pcacheinfo->dcacheline_size; - } -} - -void invalidate_writeback_dcache(unsigned long addr, int size) -{ - unsigned long start, end; - - start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size); - end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size); - - while (start <end) - { - Writeback_Invalidate_Dcache(start); - start += pcacheinfo->dcacheline_size; - } -} - -void invalidate_icache_all(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->icache_size); - - while (start < end) - { - pcacheop->Invalidate_Icache(start); - start += pcacheinfo->icacheline_size; - } -} - -void invalidate_dcache_all(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - while (start <end) - { - Invalidate_Dcache_Fill_Ls1c(start); - start += pcacheinfo->icacheline_size; - } -} - -//with cache disabled -void init_dcache(void) -{ - unsigned int start = K0BASE; - unsigned int end = (start + pcacheinfo->dcache_size); - - while (start < end) - { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; - } - -} - -void rt_hw_cache_init(void) -{ - unsigned int start, end; - - /* 1. identify cpu and probe cache */ - identify_cpu(); - probe_cache(); - - start = K0BASE; - end = (start + pcacheinfo->icache_size); - - /* - * 2. clear CP0 taglo/taghi register; - */ - pcacheop->Clear_TagLo(); - - /* - * 3. invalidate instruction cache; - */ - while (start < end) - { - pcacheop->Invalidate_Icache(start); //index invalidate icache - start += pcacheinfo->icacheline_size; - } - - /* - * 4. invalidate data cache; - */ - start = K0BASE; - end = (start + pcacheinfo->dcache_size); - while(start < end) - { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; - } - - start = K0BASE; - while(start < end) - { - pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache - start += pcacheinfo->dcacheline_size; - } - - start = K0BASE; - while(start < end) - { - pcacheop->Invalidate_Dcache_ClearTag(start); - start += pcacheinfo->dcacheline_size; - } - - /* enable cache */ - enable_cpu_cache(); - rt_kprintf("enable cpu cache done\n"); - - return ; -} - - diff --git a/libcpu/mips/loongson_1c/context_gcc.S b/libcpu/mips/loongson_1c/context_gcc.S deleted file mode 100644 index fbffd34866..0000000000 --- a/libcpu/mips/loongson_1c/context_gcc.S +++ /dev/null @@ -1,162 +0,0 @@ -/* - * File : context_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-09-11 bernard port to Loongson SoC3210 - * 2011-08-08 lgnq port to Loongson LS1B - */ - -#include "../common/mips.inc" -#include "../common/stackframe.h" -#include "stackframe_fpu.h" - - .section ".text", "ax" - .set noreorder - -/* - * rt_base_t rt_hw_interrupt_disable() - */ - .globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mfc0 v0, CP0_STATUS - and v1, v0, 0xfffffffe - mtc0 v1, CP0_STATUS - jr ra - nop - -/* - * void rt_hw_interrupt_enable(rt_base_t level) - */ - .globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - ori a0, 0x00000800 - mtc0 a0, CP0_STATUS - ehb - mfc0 v0, CP0_CAUSE - ehb - or v1, v0, 0x800000 //EBASE + 0x200 - mtc0 v1, CP0_CAUSE - ehb - jr ra - nop - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) - * a0 --> from - * a1 --> to - */ - .globl rt_hw_context_switch -rt_hw_context_switch: - mtc0 ra, CP0_EPC - SAVE_ALL - SAVE_FPU - - sw sp, 0(a0) /* store sp in preempted tasks TCB */ - lw sp, 0(a1) /* get new task stack pointer */ - - RESTORE_FPU - RESTORE_ALL_AND_RET - -/* - * void rt_hw_context_switch_to(rt_uint32 to)/* - * a0 --> to - */ - .globl rt_hw_context_switch_to -rt_hw_context_switch_to: - lw sp, 0(a0) /* get new task stack pointer */ - - RESTORE_FPU - RESTORE_ALL_AND_RET - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* - */ - .globl rt_thread_switch_interrupt_flag - .globl rt_interrupt_from_thread - .globl rt_interrupt_to_thread - .globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - la t0, rt_thread_switch_interrupt_flag - lw t1, 0(t0) - nop - bnez t1, _reswitch - nop - li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ - sw t1, 0(t0) - la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ - sw a0, 0(t0) -_reswitch: - la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ - sw a1, 0(t0) - jr ra - nop - -/* - * void rt_hw_context_switch_interrupt_do(rt_base_t flag) - */ - .globl rt_interrupt_enter - .globl rt_interrupt_leave - .globl mips_irq_handle -mips_irq_handle: - SAVE_ALL - SAVE_FPU - - mfc0 t0, CP0_CAUSE - and t1, t0, 0xff - bnez t1, spurious_interrupt /* check exception */ - nop - - /* let k0 keep the current context sp */ - move k0, sp - /* switch to kernel stack */ - li sp, SYSTEM_STACK - - jal rt_interrupt_enter - nop - jal rt_interrupt_dispatch - nop - jal rt_interrupt_leave - nop - - /* switch sp back to thread's context */ - move sp, k0 - - /* - * if rt_thread_switch_interrupt_flag set, jump to - * rt_hw_context_switch_interrupt_do and don't return - */ - la k0, rt_thread_switch_interrupt_flag - lw k1, 0(k0) - beqz k1, spurious_interrupt - nop - sw zero, 0(k0) /* clear flag */ - nop - - /* - * switch to the new thread - */ - la k0, rt_interrupt_from_thread - lw k1, 0(k0) - nop - sw sp, 0(k1) /* store sp in preempted tasks's TCB */ - - la k0, rt_interrupt_to_thread - lw k1, 0(k0) - nop - lw sp, 0(k1) /* get new task's stack pointer */ - j spurious_interrupt - nop - -spurious_interrupt: - RESTORE_FPU - RESTORE_ALL_AND_RET - - .set reorder diff --git a/libcpu/mips/loongson_1c/cpuport.c b/libcpu/mips/loongson_1c/cpuport.c deleted file mode 100644 index 03fdc2a514..0000000000 --- a/libcpu/mips/loongson_1c/cpuport.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * File : cpuport.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-07-09 Bernard first version - * 2010-09-11 Bernard add CPU reset implementation - * 2015-07-06 chinesebear modified for loongson 1c - */ - -#include <rtthread.h> -#include "ls1c.h" - -register rt_uint32_t $GP __asm__ ("$28"); - -/** - * @addtogroup Loongson LS1B - */ - -/*@{*/ - -/** - * this function will reset CPU - * - */ -void rt_hw_cpu_reset(void) -{ - /* open the watch-dog */ - WDT_EN = 0x01; /* watch dog enable */ - WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ - WDT_SET = 0x01; /* watch dog start */ - - rt_kprintf("reboot system...\n"); - while (1); -} - -/** - * this function will shutdown CPU - * - */ -void rt_hw_cpu_shutdown(void) -{ - rt_kprintf("shutdown...\n"); - - while (1); -} - -extern rt_uint32_t cp0_get_cause(void); -extern rt_uint32_t cp0_get_status(void); -extern rt_uint32_t cp0_get_hi(void); -extern rt_uint32_t cp0_get_lo(void); - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - static rt_uint32_t g_sr = 0; - static rt_uint32_t g_gp = 0; - - if (g_sr == 0) - { - g_sr = cp0_get_status(); - g_sr &= 0xfffffffe; - g_sr |= 0x8401; - - g_gp = $GP; - } - - /** Start at stack top */ - stk = (rt_uint32_t *)stack_addr; - *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ - *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ - *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ - *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ - *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ - *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ - *(--stk) = (rt_uint32_t) texit; /* ra */ - *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ - *(--stk) = (rt_uint32_t) stack_addr; /* sp */ - *(--stk) = (rt_uint32_t) g_gp; /* gp */ - *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ - *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ - *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ - *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ - *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ - *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ - *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ - *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ - *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ - *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ - *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ - *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ - *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ - *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ - *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ - *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ - *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ - *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ - *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ - *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ - *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ - *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ - *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ - *(--stk) = (rt_uint32_t) parameter; /* a0 */ - *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ - *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ - *(--stk) = (rt_uint32_t) 0x00000001; /* at */ - *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - -#define cache_op(op,addr) \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noreorder \n" \ - " .set mips3\n\t \n" \ - " cache %0, %1 \n" \ - " .set pop \n" \ - : \ - : "i" (op), "R" (*(unsigned char *)(addr))) - -#if defined(CONFIG_CPU_LOONGSON2) -#define Hit_Invalidate_I 0x00 -#else -#define Hit_Invalidate_I 0x10 -#endif -#define Hit_Invalidate_D 0x11 -#define CONFIG_SYS_CACHELINE_SIZE 32 -#define Hit_Writeback_Inv_D 0x15 - - -void flush_cache(unsigned long start_addr, unsigned long size) -{ - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; - unsigned long addr = start_addr & ~(lsize - 1); - unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); - - while (1) { - cache_op(Hit_Writeback_Inv_D, addr); - cache_op(Hit_Invalidate_I, addr); - if (addr == aend) - break; - addr += lsize; - } -} - - -/*@}*/ - diff --git a/libcpu/mips/loongson_1c/exception.c b/libcpu/mips/loongson_1c/exception.c deleted file mode 100644 index 4a3745cbc5..0000000000 --- a/libcpu/mips/loongson_1c/exception.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * File : cpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - */ -#include <rtthread.h> -#include <rthw.h> -#include "../common/exception.h" -#include "../common/mipsregs.h" - -/** - * @addtogroup Loongson - */ - -/*@{*/ - -/** - * exception handle table - */ -#define RT_EXCEPTION_MAX 8 -exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX]; - -/** - * setup the exception handle - */ -exception_func_t rt_set_except_vector(int n, exception_func_t func) -{ - exception_func_t old_handler = sys_exception_handlers[n]; - - if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func)) - { - return 0; - } - - sys_exception_handlers[n] = func; - - return old_handler; -} - -void tlb_refill_handler(void) -{ - rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); -} - -void cache_error_handler(void) -{ - rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); -} - -static void unhandled_exception_handle(pt_regs_t *regs) -{ - rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause()); -} - -void install_default_execpt_handle(void) -{ - rt_int32_t i; - - for (i=0; i<RT_EXCEPTION_MAX; i++) - sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle; -} - -void exception_handler(pt_regs_t *regs) -{ - rt_uint32_t cause; - rt_uint32_t index; - - cause = (read_c0_cause() & read_c0_config()); - cause = (cause & 0xfc00) >> 8; - - for (index = RT_EXCEPTION_MAX; index > 0; index --) - { - if (cause & (1 << index)) - { - sys_exception_handlers[index](regs); - cause &= ~(1 << index); - } - } -} - -/*@}*/ diff --git a/libcpu/mips/loongson_1c/interrupt.c b/libcpu/mips/loongson_1c/interrupt.c deleted file mode 100644 index 407580d89e..0000000000 --- a/libcpu/mips/loongson_1c/interrupt.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-10-15 Bernard first version - * 2010-10-15 lgnq modified for LS1B - * 2013-03-29 aozima Modify the interrupt interface implementations. - * 2015-07-06 chinesebear modified for loongson 1c - */ - -#include <rtthread.h> -#include <rthw.h> -#include "ls1c.h" -#include "ls1c_public.h" - - -#define MAX_INTR (LS1C_NR_IRQS) - -extern rt_uint32_t rt_interrupt_nest; -rt_uint32_t rt_interrupt_from_thread; -rt_uint32_t rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -static struct rt_irq_desc irq_handle_table[MAX_INTR]; -void rt_interrupt_dispatch(void *ptreg); -void rt_hw_timer_handler(); - -static struct ls1c_intc_regs volatile *ls1c_hw0_icregs -= (struct ls1c_intc_regs volatile *)(LS1C_INTREG_BASE); - -/** - * @addtogroup Loongson LS1B - */ - -/*@{*/ - -static void rt_hw_interrupt_handler(int vector, void *param) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} - -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init(void) -{ - rt_int32_t idx; - rt_int32_t i; - rt_uint32_t c0_status = 0; - - // ����Э������0��״̬�Ĵ���SR��IM7-2�������ж� - c0_status = read_c0_status(); - c0_status |= 0xFC00; - write_c0_status(c0_status); - - // ��о1c���жϷ�Ϊ���� - for (i=0; i<5; i++) - { - /* disable */ - (ls1c_hw0_icregs+i)->int_en = 0x0; - /* pci active low */ - (ls1c_hw0_icregs+i)->int_pol = -1; //must be done here 20110802 lgnq - /* make all interrupts level triggered */ - (ls1c_hw0_icregs+i)->int_edge = 0x00000000; - /* mask all interrupts */ - (ls1c_hw0_icregs+i)->int_clr = 0xffffffff; - } - - rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table)); - for (idx = 0; idx < MAX_INTR; idx ++) - { - irq_handle_table[idx].handler = rt_hw_interrupt_handler; - } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -/** - * This function will mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_mask(int vector) -{ - /* mask interrupt */ - (ls1c_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f)); -} - -/** - * This function will un-mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_umask(int vector) -{ - (ls1c_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f)); -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param new_handler the interrupt service routine to be installed - * @param old_handler the old interrupt service routine - */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) -{ - rt_isr_handler_t old_handler = RT_NULL; - - if (vector >= 0 && vector < MAX_INTR) - { - old_handler = irq_handle_table[vector].handler; - -#ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX); -#endif /* RT_USING_INTERRUPT_INFO */ - irq_handle_table[vector].handler = handler; - irq_handle_table[vector].param = param; - } - - return old_handler; -} - - -/** - * ִ���жϴ������� - * @IRQn �жϺ� - */ -void ls1c_do_IRQ(int IRQn) -{ - rt_isr_handler_t irq_func; - void *param; - - // �ҵ��жϴ������� - irq_func = irq_handle_table[IRQn].handler; - param = irq_handle_table[IRQn].param; - - // ִ���жϴ������� - irq_func(IRQn, param); - -#ifdef RT_USING_INTERRUPT_INFO - irq_handle_table[IRQn].counter++; -#endif - - return ; -} - - -void ls1c_irq_dispatch(int n) -{ - rt_uint32_t intstatus, irq; - - /* Receive interrupt signal, compute the irq */ - intstatus = (ls1c_hw0_icregs+n)->int_isr & (ls1c_hw0_icregs+n)->int_en; - if (0 == intstatus) - return ; - - // ִ���жϴ������� - irq = ls1c_ffs(intstatus) - 1; - ls1c_do_IRQ((n<<5) + irq); - - /* ack interrupt */ - (ls1c_hw0_icregs+n)->int_clr |= (1 << irq); - - return ; -} - - -void rt_interrupt_dispatch(void *ptreg) -{ - int irq; - void *param; - rt_isr_handler_t irq_func; - static rt_uint32_t status = 0; - rt_uint32_t c0_status; - rt_uint32_t c0_cause; - volatile rt_uint32_t cause_im; - volatile rt_uint32_t status_im; - rt_uint32_t pending_im; - - /* check os timer */ - c0_status = read_c0_status(); - c0_cause = read_c0_cause(); - - cause_im = c0_cause & ST0_IM; - status_im = c0_status & ST0_IM; - pending_im = cause_im & status_im; - - if (pending_im & CAUSEF_IP7) - { - rt_hw_timer_handler(); - } - else if (pending_im & CAUSEF_IP2) - { - ls1c_irq_dispatch(0); - } - else if (pending_im & CAUSEF_IP3) - { - ls1c_irq_dispatch(1); - } - else if (pending_im & CAUSEF_IP4) - { - ls1c_irq_dispatch(2); - } - else if (pending_im & CAUSEF_IP5) - { - ls1c_irq_dispatch(3); - } - else if (pending_im & CAUSEF_IP6) - { - ls1c_irq_dispatch(4); - } -} - -/*@}*/ - - diff --git a/libcpu/mips/loongson_1c/ls1c.h b/libcpu/mips/loongson_1c/ls1c.h deleted file mode 100644 index a203810c37..0000000000 --- a/libcpu/mips/loongson_1c/ls1c.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * File : ls1c.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2011, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-08-08 lgnq first version - * 2015-07-06 chinesebear modified for loongson 1c - */ - -#ifndef __LS1C_H__ -#define __LS1C_H__ - -#include "../common/mipsregs.h" - -#define LS1C_ACPI_IRQ 0 -#define LS1C_HPET_IRQ 1 -//#define LS1C_UART0_IRQ 3 // linux����3��v1.4�汾��1c�ֲ�����2�������Σ���ȷ�� -#define LS1C_UART1_IRQ 4 -#define LS1C_UART2_IRQ 5 -#define LS1C_CAN0_IRQ 6 -#define LS1C_CAN1_IRQ 7 -#define LS1C_SPI0_IRQ 8 -#define LS1C_SPI1_IRQ 9 -#define LS1C_AC97_IRQ 10 -#define LS1C_MS_IRQ 11 -#define LS1C_KB_IRQ 12 -#define LS1C_DMA0_IRQ 13 -#define LS1C_DMA1_IRQ 14 -#define LS1C_DMA2_IRQ 15 -#define LS1C_NAND_IRQ 16 -#define LS1C_PWM0_IRQ 17 -#define LS1C_PWM1_IRQ 18 -#define LS1C_PWM2_IRQ 19 -#define LS1C_PWM3_IRQ 20 -#define LS1C_RTC_INT0_IRQ 21 -#define LS1C_RTC_INT1_IRQ 22 -#define LS1C_RTC_INT2_IRQ 23 -#define LS1C_UART3_IRQ 29 -#define LS1C_ADC_IRQ 30 -#define LS1C_SDIO_IRQ 31 - - -#define LS1C_EHCI_IRQ (32+0) -#define LS1C_OHCI_IRQ (32+1) -#define LS1C_OTG_IRQ (32+2) -#define LS1C_MAC_IRQ (32+3) -#define LS1C_CAM_IRQ (32+4) -#define LS1C_UART4_IRQ (32+5) -#define LS1C_UART5_IRQ (32+6) -#define LS1C_UART6_IRQ (32+7) -#define LS1C_UART7_IRQ (32+8) -#define LS1C_UART8_IRQ (32+9) -#define LS1C_UART9_IRQ (32+13) -#define LS1C_UART10_IRQ (32+14) -#define LS1C_UART11_IRQ (32+15) -#define LS1C_I2C2_IRQ (32+17) -#define LS1C_I2C1_IRQ (32+18) -#define LS1C_I2C0_IRQ (32+19) - - -#define LS1C_GPIO_IRQ 64 -#define LS1C_GPIO_FIRST_IRQ 64 -#define LS1C_GPIO_IRQ_COUNT 96 -#define LS1C_GPIO_LAST_IRQ (LS1C_GPIO_FIRST_IRQ + LS1C_GPIO_IRQ_COUNT-1) - - -#define LS1C_LAST_IRQ 159 -#define LS1C_INTREG_BASE 0xbfd01040 - -// ��о1c���жϷ�Ϊ���飬ÿ��32�� -#define LS1C_NR_IRQS (32*5) - - -// GPIO��ź��жϺ�֮��Ļ���ת�� -#define LS1C_GPIO_TO_IRQ(GPIOn) (LS1C_GPIO_FIRST_IRQ + (GPIOn)) -#define LS1C_IRQ_TO_GPIO(IRQn) ((IRQn) - LS1C_GPIO_FIRST_IRQ) - - -struct ls1c_intc_regs -{ - volatile unsigned int int_isr; - volatile unsigned int int_en; - volatile unsigned int int_set; - volatile unsigned int int_clr; /* offset 0x10*/ - volatile unsigned int int_pol; - volatile unsigned int int_edge; /* offset 0 */ -}; - -struct ls1c_cop_global_regs -{ - volatile unsigned int control; - volatile unsigned int rd_inten; - volatile unsigned int wr_inten; - volatile unsigned int rd_intisr; /* offset 0x10*/ - volatile unsigned int wr_intisr; - unsigned int unused[11]; -} ; - -struct ls1c_cop_channel_regs -{ - volatile unsigned int rd_control; - volatile unsigned int rd_src; - volatile unsigned int rd_cnt; - volatile unsigned int rd_status; /* offset 0x10*/ - volatile unsigned int wr_control; - volatile unsigned int wr_src; - volatile unsigned int wr_cnt; - volatile unsigned int wr_status; /* offset 0x10*/ -} ; - -struct ls1c_cop_regs -{ - struct ls1c_cop_global_regs global; - struct ls1c_cop_channel_regs chan[8][2]; -} ; - -#define __REG8(addr) *((volatile unsigned char *)(addr)) -#define __REG16(addr) *((volatile unsigned short *)(addr)) -#define __REG32(addr) *((volatile unsigned int *)(addr)) - -#define GMAC0_BASE 0xBFE10000 -#define GMAC0_DMA_BASE 0xBFE11000 -#define GMAC1_BASE 0xBFE20000 -#define GMAC1_DMA_BASE 0xBFE21000 -#define I2C0_BASE 0xBFE58000 -#define PWM0_BASE 0xBFE5C000 -#define PWM1_BASE 0xBFE5C010 -#define PWM2_BASE 0xBFE5C020 -#define PWM3_BASE 0xBFE5C030 -#define WDT_BASE 0xBFE5C060 -#define RTC_BASE 0xBFE64000 -#define I2C1_BASE 0xBFE68000 -#define I2C2_BASE 0xBFE70000 -#define AC97_BASE 0xBFE74000 -#define NAND_BASE 0xBFE78000 -#define SPI_BASE 0xBFE80000 -#define CAN1_BASE 0xBF004300 -#define CAN0_BASE 0xBF004400 - -/* Watch Dog registers */ -#define WDT_EN __REG32(WDT_BASE + 0x00) -#define WDT_SET __REG32(WDT_BASE + 0x04) -#define WDT_TIMER __REG32(WDT_BASE + 0x08) - -#define PLL_FREQ __REG32(0xbfe78030) -#define PLL_DIV_PARAM __REG32(0xbfe78034) - -#endif - diff --git a/libcpu/mips/loongson_1c/mipscfg.c b/libcpu/mips/loongson_1c/mipscfg.c deleted file mode 100644 index 10dd3fee9e..0000000000 --- a/libcpu/mips/loongson_1c/mipscfg.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * File : mipscfg.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-27 swkyer first version - */ -#include <rtthread.h> -#include "../common/mipsregs.h" -#include "../common/mipscfg.h" - -mips32_core_cfg_t g_mips_core = -{ - 16, /* icache_line_size */ - 256, /* icache_lines_per_way */ - 4, /* icache_ways */ - 16, /* dcache_line_size */ - 256, /* dcache_lines_per_way */ - 4, /* dcache_ways */ - 16, /* max_tlb_entries */ -}; - -static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) -{ - rt_uint16_t rets = 1; - - while (n--) - rets *= b; - - return rets; -} - -static rt_uint16_t m_log2(rt_uint16_t b) -{ - rt_uint16_t rets = 0; - - while (b != 1) - { - b /= 2; - rets++; - } - - return rets; -} - -/** - * read core attribute - */ -void mips32_cfg_init(void) -{ - rt_uint16_t val; - rt_uint32_t cp0_config1; - - cp0_config1 = read_c0_config(); - if (cp0_config1 & 0x80000000) - { - cp0_config1 = read_c0_config1(); - - val = (cp0_config1 & (7<<22))>>22; - g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<19))>>19; - g_mips_core.icache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<16))>>16; - g_mips_core.icache_ways = val + 1; - - val = (cp0_config1 & (7<<13))>>13; - g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<10))>>10; - g_mips_core.dcache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<7))>>7; - g_mips_core.dcache_ways = val + 1; - - val = (cp0_config1 & (0x3F<<25))>>25; - g_mips_core.max_tlb_entries = val + 1; - } -} diff --git a/libcpu/mips/loongson_1c/sdram_cfg.h b/libcpu/mips/loongson_1c/sdram_cfg.h deleted file mode 100644 index 3f88f26623..0000000000 --- a/libcpu/mips/loongson_1c/sdram_cfg.h +++ /dev/null @@ -1,85 +0,0 @@ - -#ifndef __OPENLOONGSON_SDRAM_CFG_H -#define __OPENLOONGSON_SDRAM_CFG_H - - -//#define SD_FREQ (6 * PLL_M) / (2 * SDRAM_PARAM_DIV_NUM) -#define SD_FREQ (((APB_CLK / 4) * (PLL_MULT / CPU_DIV)) / SDRAM_PARAM_DIV_NUM) - - -/* 颗粒行数 */ -#define ROW_1K 0x7 -#define ROW_2K 0x0 -#define ROW_4K 0x1 -#define ROW_8K 0x2 -#define ROW_16K 0x3 -/* 颗粒列数 */ -#define COL_256 0x7 -#define COL_512 0x0 -#define COL_1K 0x1 -#define COL_2K 0x2 -#define COL_4K 0x3 -/* 颗粒位宽 */ -#define WIDTH_8 0x0 -#define WIDTH_16 0x1 -#define WIDTH_32 0x2 - -#define TRCD 3 -#define TCL 3 -#define TRP 3 -#define TRFC 8 -#define TRAS 6 -#define TREF 0x818 -#define TWR 2 - -#define DEF_SEL 0x1 -#define DEF_SEL_N 0x0 -#define HANG_UP 0x1 -#define HANG_UP_N 0x0 -#define CFG_VALID 0x1 - - -#if 0 -// 白菜板8MB -/* - 以型号为IS42S16400的SDRAM为例， - 物理参数为， - 容量：8MB - 位宽：16位 - 列宽：8位，即2的8次方，即256 - 行宽：12位，即2的12次方，即4K - - 所以， - 颗粒的位宽=WIDTH_16 - 颗粒的列数=COL_256 - 颗粒的行数=ROW_4K - - 再结合宏SD_PARA0和芯片手册中寄存器SD_CONFIG，相信一看就能明白 - 替换宏SD_PARA0中的行宽、列宽和位宽 -*/ -#define SDRAM_WIDTH (WIDTH_16) -#define SDRAM_COL (COL_256) -#define SDRAM_ROW (ROW_4K) - -#else - -// 智龙32MByte -#define SDRAM_WIDTH (WIDTH_16) -#define SDRAM_COL (COL_512) -#define SDRAM_ROW (ROW_8K) - -#endif - -#define SD_PARA0 (0x7f<<25 | \ - (TRAS << 21) | \ - (TRFC << 17) | (TRP << 14) | (TCL << 11) | \ - (TRCD << 8) | (SDRAM_WIDTH << 6) | (SDRAM_COL << 3) | \ - SDRAM_ROW) - -#define SD_PARA1 ((HANG_UP_N << 8) | (DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7)) - -#define SD_PARA1_EN ((CFG_VALID << 9) | (HANG_UP_N << 8) | \ - (DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7)) - - -#endif diff --git a/libcpu/mips/loongson_1c/stackframe_fpu.h b/libcpu/mips/loongson_1c/stackframe_fpu.h deleted file mode 100644 index 93b8ef10c3..0000000000 --- a/libcpu/mips/loongson_1c/stackframe_fpu.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * ls1c FPU's stackframe - * �ʼ���룬��������뵽stackframe.h�е�SAVE_ALL, RESTORE_ALL��RESTORE_ALL_AND_RET�У� - * �����ǵ�Դ�ļ�"stackframe.h"λ��Ŀ¼"libcpu\mips\common"�ڣ���Ӱ�쵽����mips cpu - * ���ԣ������½���Դ�ļ� - */ -#ifndef __OPENLOONGSON_STACKFRAME_FPU_H -#define __OPENLOONGSON_STACKFRAME_FPU_H - - -#include "../common/asm.h" -#include "../common/mipsregs.h" -#include "../common/stackframe.h" - - - -#define PT_FPU_R0 (0) -#define PT_FPU_R2 ((PT_FPU_R0) + 2*LONGSIZE) -#define PT_FPU_R4 ((PT_FPU_R2) + 2*LONGSIZE) -#define PT_FPU_R6 ((PT_FPU_R4) + 2*LONGSIZE) -#define PT_FPU_R8 ((PT_FPU_R6) + 2*LONGSIZE) -#define PT_FPU_R10 ((PT_FPU_R8) + 2*LONGSIZE) -#define PT_FPU_R12 ((PT_FPU_R10) + 2*LONGSIZE) -#define PT_FPU_R14 ((PT_FPU_R12) + 2*LONGSIZE) -#define PT_FPU_R16 ((PT_FPU_R14) + 2*LONGSIZE) -#define PT_FPU_R18 ((PT_FPU_R16) + 2*LONGSIZE) -#define PT_FPU_R20 ((PT_FPU_R18) + 2*LONGSIZE) -#define PT_FPU_R22 ((PT_FPU_R20) + 2*LONGSIZE) -#define PT_FPU_R24 ((PT_FPU_R22) + 2*LONGSIZE) -#define PT_FPU_R26 ((PT_FPU_R24) + 2*LONGSIZE) -#define PT_FPU_R28 ((PT_FPU_R26) + 2*LONGSIZE) -#define PT_FPU_R30 ((PT_FPU_R28) + 2*LONGSIZE) - -#define PT_FPU_SIZE ((((PT_FPU_R30) + 2*LONGSIZE) + (2*PTRSIZE-1)) & ~(2*PTRSIZE-1)) - - - .macro SAVE_FPU - .set push - .set noreorder -#ifdef RT_USING_FPU - move k1, sp /* �����ֳ� */ - and k0, k1, 0xFFFFFFF8 /* 8�ֽڶ��� */ - PTR_SUBU sp, k0, PT_FPU_SIZE /* ����ջ�� */ - s.d $f0, PT_FPU_R0(sp) - s.d $f2, PT_FPU_R2(sp) - s.d $f4, PT_FPU_R4(sp) - s.d $f6, PT_FPU_R6(sp) - s.d $f8, PT_FPU_R8(sp) - s.d $f10, PT_FPU_R10(sp) - s.d $f12, PT_FPU_R12(sp) - s.d $f14, PT_FPU_R14(sp) - s.d $f16, PT_FPU_R16(sp) - s.d $f18, PT_FPU_R18(sp) - s.d $f20, PT_FPU_R20(sp) - s.d $f22, PT_FPU_R22(sp) - s.d $f24, PT_FPU_R24(sp) - s.d $f26, PT_FPU_R26(sp) - s.d $f28, PT_FPU_R28(sp) - s.d $f30, PT_FPU_R30(sp) - move sp, k1 /* �ָ��ֳ� */ -#endif - .set reorder - .set pop - .endm - - - .macro RESTORE_FPU - .set push - .set noreorder -#ifdef RT_USING_FPU - move k1, sp /* �����ֳ� */ - and k0, k1, 0xFFFFFFF8 /* 8�ֽڶ��� */ - PTR_SUBU sp, k0, PT_FPU_SIZE /* ����ջ��*/ - l.d $f0, PT_FPU_R0(sp) - l.d $f2, PT_FPU_R2(sp) - l.d $f4, PT_FPU_R4(sp) - l.d $f6, PT_FPU_R6(sp) - l.d $f8, PT_FPU_R8(sp) - l.d $f10, PT_FPU_R10(sp) - l.d $f12, PT_FPU_R12(sp) - l.d $f14, PT_FPU_R14(sp) - l.d $f16, PT_FPU_R16(sp) - l.d $f18, PT_FPU_R18(sp) - l.d $f20, PT_FPU_R20(sp) - l.d $f22, PT_FPU_R22(sp) - l.d $f24, PT_FPU_R24(sp) - l.d $f26, PT_FPU_R26(sp) - l.d $f28, PT_FPU_R28(sp) - l.d $f30, PT_FPU_R30(sp) - move sp, k1 /* �ָ��ֳ� */ -#endif - .set reorder - .set pop - .endm - - -#endif - diff --git a/libcpu/mips/loongson_1c/start_gcc.S b/libcpu/mips/loongson_1c/start_gcc.S deleted file mode 100644 index 4e71bc0524..0000000000 --- a/libcpu/mips/loongson_1c/start_gcc.S +++ /dev/null @@ -1,529 +0,0 @@ -/* - * File : start_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-09-04 bernard porting to Jz47xx - */ - -#include "../common/mips.inc" -#include "../common/stackframe.h" -#include "sdram_cfg.h" -#include "cache.h" -#include "rtconfig.h" - -#define SR_BOOT_EXC_VEC 0x00400000 - - -/* config pll div for cpu and sdram */ -#define PLL_MULT (0x54) // 晶振为24Mhz时，PLL=504Mhz -#define SDRAM_DIV (0) // SDRAM为CPU的2分频 -#define CPU_DIV (2) // CPU为PLL的2分频 - - // 配置内存大小 -#define MEM_SIZE (0x02000000) // 32MByte - - /* Delay macro */ -#define DELAY(count) \ - li v0, count; \ - 99: \ - bnez v0, 99b;\ - addiu v0, -1 - - -#define msize s2 -#define output_en s3 - - - - - .section ".start", "ax" - .set noreorder - - /* the program entry */ - .globl _start -_start: - .set noreorder - la ra, _start - -#if !defined(RT_USING_SELF_BOOT) - - /* disable interrupt */ - mfc0 t0, CP0_STATUS - and t0, 0xfffffffe # By default it will be disabled. - mtc0 t0, CP0_STATUS # Set CPU to disable interrupt. - nop - - /* disable cache */ - mfc0 t0, CP0_CONFIG - and t0, 0xfffffff8 - or t0, 0x2 # disable,!default value is not it! - mtc0 t0, CP0_CONFIG # Set CPU to disable cache. - nop - - /* setup stack pointer */ - li sp, SYSTEM_STACK - la gp, _gp - - /* clear bss */ - la t0, __bss_start - la t1, __bss_end -_clr_bss_loop: - sw zero, 0(t0) - bne t0, t1, _clr_bss_loop - addiu t0, t0, 4 - - /* jump to RT-Thread RTOS */ - jal rtthread_startup - nop - - /* restart, never die */ - j _start - nop - -#else - - mtc0 zero, CP0_STATUS // 清零cp0 status寄存器 - mtc0 zero, CP0_CAUSE // 清零cp0 cause寄存器 - - /* - 设置启动异常向量入口地址为ROM地址(0xbfc00000) - 将寄存器cp0 status的BEV置1，使CPU采用ROM(kseg1)空间的异常入口点 - */ - li t0, SR_BOOT_EXC_VEC /* Exception to Boostrap Location */ - mtc0 t0, CP0_STATUS - - /* setup stack pointer */ - li sp, SYSTEM_STACK - la gp, _gp - - /* initialize spi */ - li t0, 0xbfe80000 //地址0xbfe80000为SPI0的寄存器基地址 - li t1, 0x17 // div 4, fast_read + burst_en + memory_en double I/O 模式 部分SPI flash可能不支持 - sb t1, 0x4(t0) // 设置寄存器sfc_param - li t1, 0x05 - sb t1, 0x6(t0) // 设置寄存器sfc_timing - - /* 设置sdram cs1复用关系，开发板使用ejtag_sel gpio_0引脚(第五复用)作为第二片sdram的片选 - 注意sw2拨码开关的设置，使用ejtag烧录pmon时需要调整拨码开关，烧录完再调整回来 */ - li a0, 0xbfd011c0 - lw a1, 0x40(a0) - ori a1, 0x01 - sw a1, 0x40(a0) - - - bal locate - nop - - /* restart, never die */ - j _start - nop -#endif - - .set reorder - - .globl cp0_get_cause -cp0_get_cause: - mfc0 v0, CP0_CAUSE - jr ra - nop - - .globl cp0_get_status -cp0_get_status: - mfc0 v0, CP0_STATUS - jr ra - nop - - .globl cp0_get_hi -cp0_get_hi: - mfhi v0 - jr ra - nop - - .globl cp0_get_lo -cp0_get_lo: - mflo v0 - jr ra - nop - -#if defined(RT_USING_SELF_BOOT) - -/****************************************LOCATE*********************************/ - -/* - * We get here from executing a bal to get the PC value of the current execute - * location into ra. Check to see if we run from ROM or if this is ramloaded. - * 寄存器ra内保持着函数的返回地址，根据ra的值来判断当前是从ROM冷启动，还是从RAM热复位的 - * ROM冷启动由通电引起，RAM热复位为各种异常引起，比如看门狗引起的复位等， - * 也就是RAM热复位之前CPU已经开始运行了 - * 如果是从ROM冷启动，则寄存器ra的值为指令"bal locate"所在位置加8字节，大概在0xBFC00000附近 - * 如果是从RAM热复位，则集成器ra的值为0x80xxxxxx - */ -locate: -// la s0, uncached -// subu s0, ra, s0 - /* - * start.s的这段汇编程序在ROM（入口点为0xBFC00000）中运行 - * 而编译链接时指定的起始地址是0x80100000，所以需要修正一下地址 - * s0中保存着ra与start的差值，在后续的代码中可以起到修正地址的作用 - * 在看看文件开始的时候，对寄存器s0用途的描述是“ link versus load offset, used to relocate absolute adresses” - * 除了修正地址外，还通过s0的值来判断是从ROM冷启动，还是从RAM热启动 - */ - - la s0, _start // s0 = _start， 其中start的地址为编译链接时，指定的0x80010000 - subu s0, ra, s0 // s0 = ra - s0，其中ra的值在ROM入口地址0xBFC00000附近 - and s0, 0xffff0000 // s0 = s0 & 0xffff0000 - - /* - * 初始化cp0的status寄存器和cause寄存器 - * 在异常引起的(从RAM)热复位后，需要重新初始化cp0的status和cause， - * 如果是从ROM冷启动的，那么前面已经初始化了，这里是再次重复初始化，没有影响的 - */ - li t0, SR_BOOT_EXC_VEC - mtc0 t0, CP0_CONFIG // 重新初始化cp0的status寄存器 - mtc0 zero, CP0_CAUSE // 重新清零cp0的cause寄存器 - .set noreorder - - li t0, 0xbfe78030 // 地址0xbfe78030为PLL/SDRAM频率配置寄存器的地址 - /* 设置PLL倍频 及SDRAM分频 */ - li t2, (0x80000008 | (PLL_MULT << 8) | (0x3 << 2) | SDRAM_DIV) - /* 设置CPU分频 */ - li t3, (0x00008003 | (CPU_DIV << 8)) - /* 注意：首先需要把分频使能位清零 */ - li t1, 0x2 - sw t1, 0x4(t0) // 清零CPU_DIV_VALID，即disable - sw t2, 0x0(t0) // 写寄存器START_FREQ - sw t3, 0x4(t0) // 写寄存器CLK_DIV_PARAM - DELAY(2000) - - /* 芯片上电默认使用gpio(输入模式）但大多时候是使用模块的功能，如lcd i2c spi ac97等 - 所以这里把gpio都关闭，方便使用模块功能。如果上电后需要gpio输出一个确定电平， - 如继电器、LDE等，可以修改这里的代码。*/ - /* disable all gpio */ - li a0,0xbfd00000 - sw zero,0x10c0(a0) /* disable gpio 0-31 */ - sw zero,0x10c4(a0) /* disable gpio 32-63 */ - sw zero,0x10c8(a0) /* disable gpio 64-95 */ - sw zero,0x10cc(a0) - - li t0, 0xffffffff - sw t0, 0x10d0(a0) - sw t0, 0x10d4(a0) - sw t0, 0x10d8(a0) - sw t0, 0x10dc(a0) - - sw t0, 0x10f0(a0) - sw t0, 0x10f4(a0) - sw t0, 0x10f8(a0) - sw t0, 0x10fc(a0) - - - /* lcd soft_reset and panel config & timing */ -#ifdef DC_FB0 -/* li a0, 0xbc301240 - li a1, 0x00100103 - sw a1, 0x0(a0) - li a1, 0x00000103 - sw a1, 0x0(a0) //soft_reset - li a1, 0x00100103 - sw a1, 0x0(a0) - - li a1, 0x80001111 - sw a1, 0x180(a0) //panel config - li a1, 0x33333333 - sw a1, 0x1a0(a0)*/ -#endif - - li output_en, 0x1 -#ifdef FAST_STARTUP - li a1, 0x03000000 - sw a1, 0x10c4(a0) - sw a1, 0x10d4(a0) - lw a2, 0x10e4(a0) - and a2, a1 - beq a2, a1, get_pin_val_finish - nop - li output_en, 0x1 - -get_pin_val_finish: - -#endif - - /* Initializing. Standby... */ - /* - * 根据s0的值判断是否为ROM冷启动 - * 如果s0不等于0，则是ROM冷启动；如果等于0，则是RAM热复位 - * 冷启动，则需要初始化内存，cache，加载代码到内存等 - */ - bnez s0, 1f // 如果寄存器s0不等于0，则说明是ROM冷启动，则跳转到下一个标号1处进行彻底初始化 - nop - li a0, 128 - - jal rtthread_startup // 热复位，则直接跳转到函数main - nop -1: - -/* use only 8wins */ -#define CPU_WIN_BASE 0xbfd00000 -#define CPU_WIN_MASK 0xbfd00040 -#define CPU_WIN_MMAP 0xbfd00080 - -#define set_cpu_window(id, base, mask, mmap) \ - li t0, CPU_WIN_BASE ; \ - sw $0, 0x80+id*8(t0) ; \ - li t1, base ; \ - sw t1, 0x00+id*8(t0) ; \ - sw $0, 0x04+id*8(t0) ; \ - li t1, mask ; \ - sw t1, 0x40+id*8(t0) ; \ - sw $0, 0x44+id*8(t0) ; \ - li t1, mmap ; \ - sw t1, 0x80+id*8(t0) ; \ - sw $0, 0x84+id*8(t0) - -/* fixup cpu window */ -cpu_win_fixup: - // - // hit = (paddr & mask) == (mmap & mask) - // mapped_addr = paddr &~mask | mmap & mask - // - // mmap[7] -> enable - // mmap[5] -> block trans enable - // mmap[4] -> cachable - // mmap[1:0] -> destination - // - // NOTE: the address windows has priority, win0 > win1 > ... > win7 - -/* set_cpu_window(0, 0x1c280000, 0xfff80000, 0x1c280083) // camera 512K - set_cpu_window(1, 0x1c300000, 0xfff00000, 0x1c300081) // dc 1M - set_cpu_window(2, 0x1fe10000, 0xffffe000, 0x1fe10082) // gmac0 8K - set_cpu_window(3, 0x1fe10000, 0xffff0000, 0x1fe100d0) // gmac0 64K - set_cpu_window(4, 0x1f000000, 0xff000000, 0x1f000082) // AXIMUX 16M - set_cpu_window(5, 0x00000000, 0x00000000, 0x000000f0) // ddr 0 - set_cpu_window(6, 0x00000000, 0x00000000, 0x000000f0) // ddr 0 - set_cpu_window(7, 0x00000000, 0x00000000, 0x000000f0) // ddr 0*/ - -/* set_cpu_window(0, 0x1c280000, 0xfff80000, 0x1c2800d3) // camera -// set_cpu_window(1, 0x1fc00000, 0xfff00000, 0x1fc000f2) // - set_cpu_window(2, 0x1c300000, 0xfff00000, 0x1c3000d1) // dc 1M -// set_cpu_window(3, 0x1f000000, 0xff000000, 0x1f0000d2) // - set_cpu_window(4, 0x00000000, 0x00000000, 0x000000f0) - set_cpu_window(5, 0x00000000, 0x00000000, 0x000000f0) - set_cpu_window(6, 0x00000000, 0x00000000, 0x000000f0) // ddr 0 - set_cpu_window(7, 0x00000000, 0x00000000, 0x000000f0) // ddr 0*/ - - // after this fixup, the kernel code should be compiled with - // uncached instruction fetch patch - - /* 配置内存 */ - li msize, MEM_SIZE -#if !defined(NAND_BOOT_EN) - - /* - 手册建议，先写寄存器SD_CONFIG[31:0]，然后再写寄存器的SD_CONFIG[63:32]， - 即先写低32位，再写高32位。 - 写三次寄存器，最后一次将最高位置一，即使能 - */ - - // 写第一次 - li t1, 0xbfd00410 // 寄存器SD_CONFIG[31:0]的地址为0xbfd00410 - li a1, SD_PARA0 // 宏SD_PARA0在sdram_cfg.S中定义的 - sw a1, 0x0(t1) // 将宏SD_PARA0的值写入寄存器SD_CONFIG[31:0] - li a1, SD_PARA1 - sw a1, 0x4(t1) // 同理，将宏SD_PARA1的值写入寄存器SD_CONFIG[63:32] - - // 写第二次 - li a1, SD_PARA0 - sw a1, 0x0(t1) - li a1, SD_PARA1 - sw a1, 0x4(t1) - - // 写第三次 - li a1, SD_PARA0 - sw a1, 0x0(t1) - li a1, SD_PARA1_EN // 使能 - sw a1, 0x4(t1) -// DELAY(100) -#endif - - /**************************************CACHE*****************************/ - -#define CF_7_SE (1 << 3) /* Secondary cache enable */ -#define CF_7_SC (1 << 31) /* Secondary cache not present */ -#define CF_7_TE (1 << 12) /* Tertiary cache enable */ -#define CF_7_TC (1 << 17) /* Tertiary cache not present */ -#define CF_7_TS (3 << 20) /* Tertiary cache size */ -#define CF_7_TS_AL 20 /* Shift to align */ -#define NOP8 nop;nop;nop;nop;nop;nop;nop;nop - -do_caches: - /* Init caches... */ - li s7, 0 /* no L2 cache */ - li s8, 0 /* no L3 cache */ - - bal cache_init // 调用汇编函数cache_init - nop - - mfc0 a0, CP0_CONFIG // 将协处理器0的config寄存器的值加载到寄存器a0 - and a0, a0, ~((1<<12) | 7) // a0 = a0 & ~((1<<12) | 7) - or a0, a0, 2 // a0 |= 2 - mtc0 a0, CP0_CONFIG // 将寄存器a0的值写入协处理器0的config寄存器 - -/***********************MEMORY DEBUGGING AND COPY SELF TO RAM***********************/ -//#include "newtest.32/mydebug.S" -bootnow: - /* copy program to sdram to make copy fast */ - /* 先将执行拷贝pmon到内存任务的代码，拷贝到内存0xa0000000 */ - - /* 先确定需要拷贝的代码段为标号121到标号122之间的代码 - * 由于链接时指定的起始地址是0x80010000， - * 而目前正在ROM（SPI NOR FLASH，起始地址为0xBFC00000）运行 - * 所以需要用寄存器s0来修正一下地址 - */ - la t0, 121f // 将下一个标号121所在地址，加载到寄存器t0 - addu t0, s0 // 使用寄存器s0修正t0中的(标号121的)地址 - la t1, 122f // 将下一个标号122所在地址，加载到寄存器t1 - addu t1, s0 // 使用寄存器s0修正t1中的(标号122的)地址 - - li t2, 0xa0000000 // 将立即数0xa0000000（起始地址）加载到寄存器t2 -1: - lw v0, (t0) // 将寄存器t0所指的内存地址开始4字节的数据加载到寄存器v0 - sw v0, (t2) // 将寄存器v0的内容保存到寄存器t2所指的内存中 - addu t0, 4 // 寄存器t0向后移4字节 - addu t2, 4 // 寄存器t2向后移4字节 - ble t0, t1, 1b // 如果t0 <= t1，则跳转到上一个标号1处，继续拷贝后面的4字节 - nop - - li t0, 0xa0000000 // 将立即数0xa0000000加载到寄存器t0 - jr t0 // 跳转到起始地址0xa0000000处开始执行（拷贝任务） - nop - -121: - /* Copy PMON to execute location... */ - /* 将固件拷贝到起始地址为0xa0010000的内存空间 - 由于kseg0(0x8000 0000 - 0x9FFF FFFF)和kseg1(0xA000 0000 - 0xBFFF FFFF)是映射到物理内存的相同区域 - 即拷贝到0xA000 0000开始的kseg1，就相当于拷贝到0x8000 0000开始的kseg0 - 这就是为什么链接时，指定的地址是0x8001 0000，而拷贝的目标起始地址是0xA001 0000 - */ - la a0, _start // 加载符号start所在地址0x80010000加载到寄存器a0中 - addu a1, a0, s0 // 使用寄存器s0修正寄存器a0中的地址，a1=0xBFC00000 - la a2, __bss_start // 加载_edata（链接脚本中的一个符号）到寄存器a2 - or a0, 0xa0000000 // a0 = a0 | 0xa0000000 = 0xa0010000 - or a2, 0xa0000000 // a2 = a2 | 0xa0000000，修正地址_edata - subu t1, a2, a0 // t1 = a2 - a0，即计算从start到_edata之间的长度（字节数） - srl t1, t1, 2 // t1 >>= 2，即t1除以4。(和前面类似，每次拷贝4字节，所以除以4) - // 似乎t1计算结果没有被使用，马上就被后面的覆盖了 - - move t0, a0 // t0 = a0 = 0xa0010000 (目标起始地址) - move t1, a1 // t1 = a1 = 0xBFC00000 (start在ROM中的地址，源起始地址) - move t2, a2 // t2 = a2 (_edata在ROM中的地址，源结束地址) - - /* copy text section */ -1: and t3, t0, 0x0000ffff // t3 = t0 & 0x0000ffff，取低16位 - bnez t3, 2f // 如果t3不等于0，则跳转到下一个标号2处继续执行，t3的计算结果似乎没被使用，就被后面的覆盖了 - nop -2: lw t3, 0(t1) // 从源地址t1处加载4字节到寄存器t3中 - nop - sw t3, 0(t0) // 将寄存器t3中的4字节数据保存到目标地址t0处 - addu t0, 4 // 目标地址t0后移4字节 - addu t1, 4 // 源地址t1 后移4字节 - bne t2, t0, 1b // 如果t2不等于t0，则跳到上一个标号1处继续拷贝，总的来说就是判断拷贝是否结束 - nop - /* copy text section done. */ - - /* clear bss */ - la t0, __bss_start - la t1, __bss_end -_clr_bss_loop: - sw zero, 0(t0) - bne t0, t1, _clr_bss_loop - addiu t0, t0, 4 - - /* disable interrupt */ - mfc0 t0, CP0_STATUS - and t0, 0xfffffffe # By default it will be disabled. - mtc0 t0, CP0_STATUS # Set CPU to disable interrupt. - nop - - /* disable cache */ - mfc0 t0, CP0_CONFIG - and t0, 0xfffffff8 - or t0, 0x2 # disable,!default value is not it! - mtc0 t0, CP0_CONFIG # Set CPU to disable cache. - nop - - /* jump to RT-Thread RTOS */ - jal rtthread_startup - nop - - /* restart, never die */ - j _start - nop - - -122: - -stuck: - b stuck - nop -#endif - - .extern tlb_refill_handler - .extern cache_error_handler - - /* Exception Handler */ - - /* 0x0 - TLB refill handler */ - .section .vectors.1, "ax", %progbits - .global tlb_refill_exception - .type tlb_refill_exception,@function -tlb_refill_exception: - j tlb_refill_handler - nop - - /* 0x100 - Cache error handler */ - .section .vectors.2, "ax", %progbits - j cache_error_handler - nop - - /* 0x180 - Exception/Interrupt handler */ - .section .vectors.3, "ax", %progbits - .global general_exception - .type general_exception,@function -general_exception: - j _general_exception_handler - nop - - /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */ - .section .vectors.4, "ax", %progbits - .global irq_exception - .type irq_exception,@function -irq_exception: - j _irq_handler - nop - - .section .vectors, "ax", %progbits - .extern mips_irq_handle - - /* general exception handler */ -_general_exception_handler: - .set noreorder - la k0, mips_irq_handle - jr k0 - nop - .set reorder - - /* interrupt handler */ -_irq_handler: - .set noreorder - la k0, mips_irq_handle - jr k0 - nop - .set reorder diff --git a/libcpu/mips/pic32/SConscript b/libcpu/mips/pic32/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/mips/pic32/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/mips/pic32/context_gcc.S b/libcpu/mips/pic32/context_gcc.S index 3e820fb9d8..bd46dffdc7 100644 --- a/libcpu/mips/pic32/context_gcc.S +++ b/libcpu/mips/pic32/context_gcc.S @@ -1,5 +1,20 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2011-05-24 aozima first version + * 2019-07-19 Zhou Yanjie clean up code + */ + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ +#endif + #include <p32xxxx.h> -#include "../common/mips.inc" +#include "../common/mips_def.h" #include "../common/stackframe.h" .section ".text", "ax" diff --git a/libcpu/mips/x1000/cache.c b/libcpu/mips/x1000/cache.c deleted file mode 100644 index 5fc9682810..0000000000 --- a/libcpu/mips/x1000/cache.c +++ /dev/null @@ -1,217 +0,0 @@ -/* - * File : cache.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016/11/02 Urey the first version - */ - -#include <rtthread.h> -#include <board.h> -#include <rthw.h> - -#include "../common/mips.h" - - -#define CONFIG_SYS_DCACHE_SIZE 16384 -#define CONFIG_SYS_ICACHE_SIZE 16384 -#define CONFIG_SYS_CACHELINE_SIZE 32 - -#define K0_TO_K1() \ -do { \ - unsigned long __k0_addr; \ - \ - __asm__ __volatile__( \ - "la %0, 1f\n\t" \ - "or %0, %0, %1\n\t" \ - "jr %0\n\t" \ - "nop\n\t" \ - "1: nop\n" \ - : "=&r"(__k0_addr) \ - : "r" (0x20000000) ); \ -} while(0) - -#define K1_TO_K0() \ -do { \ - unsigned long __k0_addr; \ - __asm__ __volatile__( \ - "nop;nop;nop;nop;nop;nop;nop\n\t" \ - "la %0, 1f\n\t" \ - "jr %0\n\t" \ - "nop\n\t" \ - "1: nop\n" \ - : "=&r" (__k0_addr)); \ -} while (0) - -#define INVALIDATE_BTB() \ -do { \ - unsigned long tmp; \ - __asm__ __volatile__( \ - ".set mips32\n\t" \ - "mfc0 %0, $16, 7\n\t" \ - "nop\n\t" \ - "ori %0, 2\n\t" \ - "mtc0 %0, $16, 7\n\t" \ - "nop\n\t" \ - ".set mips2\n\t" \ - : "=&r" (tmp)); \ -} while (0) - -#define __sync() \ - __asm__ __volatile__( \ - ".set push\n\t" \ - ".set noreorder\n\t" \ - ".set mips2\n\t" \ - "sync\n\t" \ - ".set pop" \ - : /* no output */ \ - : /* no input */ \ - : "memory") - -#if defined(JZ4775) || defined(X1000) -#define SYNC_WB() \ -do { \ - __asm__ __volatile__ ( \ - "sync\n\t" \ - "lw $0, %0\n\t" \ - : \ - :"m"(*(int *)0xa0000000) \ - :"memory"); \ -} while (0) -#else -#error "not define sync wb" -#define SYNC_WB() __asm__ __volatile__ ("sync") -#endif - - -#undef cache_op -#define cache_op(op, addr) \ - __asm__ __volatile__( \ - ".set push\n" \ - ".set noreorder\n" \ - ".set mips3\n" \ - "cache %0, %1\n" \ - ".set pop\n" \ - : \ - : "i" (op), "R" (*(unsigned char *)(addr))) - - -void rt_hw_dcache_flush_line(rt_uint32_t addr) -{ - cache_op(HIT_WRITEBACK_INV_D, addr); - SYNC_WB(); -} - -void rt_hw_dcache_flush_range(rt_uint32_t start_addr, rt_uint32_t size) -{ - rt_uint32_t lsize = CONFIG_SYS_CACHELINE_SIZE; - rt_uint32_t addr = start_addr & ~(lsize - 1); - rt_uint32_t aend = (start_addr + size - 1) & ~(lsize - 1); - rt_uint32_t writebuffer; - - for (; addr <= aend; addr += lsize) - { - cache_op(HIT_WRITEBACK_INV_D, addr); - } - SYNC_WB(); -} - -void rt_hw_dcache_flush_all(void) -{ - rt_uint32_t addr; - - for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE) - { - cache_op(INDEX_WRITEBACK_INV_D, addr); - } - - SYNC_WB(); -} - -void rt_hw_dcache_invalidate_range(rt_uint32_t start_addr,rt_uint32_t size) -{ - rt_uint32_t lsize = CONFIG_SYS_CACHELINE_SIZE; - rt_uint32_t addr = start_addr & ~(lsize - 1); - rt_uint32_t aend = (start_addr + size - 1) & ~(lsize - 1); - - for (; addr <= aend; addr += lsize) - cache_op(HIT_INVALIDATE_D, addr); -} - -void rt_hw_dcache_invalidate_all(void) -{ - rt_uint32_t addr; - - for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE) - { - cache_op(INDEX_STORE_TAG_D, addr); - } - - SYNC_WB(); -} - -void rt_hw_icache_flush_line(rt_uint32_t addr) -{ - cache_op(HIT_INVALIDATE_I, addr); -} - -void rt_hw_icache_flush_all(void) -{ - rt_uint32_t addr; - - asm volatile ("mtc0 $0, $28"); /* Clear Taglo */ - asm volatile ("mtc0 $0, $29"); /* Clear TagHi */ - - for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; addr += CONFIG_SYS_CACHELINE_SIZE) - { - cache_op(INDEX_STORE_TAG_I, addr); - } - - INVALIDATE_BTB(); -} - -void rt_hw_icache_invalidate_all(void) -{ - rt_uint32_t i; - - K0_TO_K1(); - - asm volatile (".set noreorder\n" - ".set mips32\n\t" - "mtc0\t$0,$28\n\t" - "mtc0\t$0,$29\n" - ".set mips0\n" - ".set reorder\n"); - for (i = CKSEG0; i < CKSEG0 + CONFIG_SYS_ICACHE_SIZE; i += CONFIG_SYS_CACHELINE_SIZE) - cache_op(INDEX_STORE_TAG_I, i); - - K1_TO_K0(); - - INVALIDATE_BTB(); -} - - -void rt_hw_flush_cache_all(void) -{ - rt_hw_dcache_flush_all(); - rt_hw_icache_flush_all(); -} - - - diff --git a/libcpu/mips/x1000/cache.h b/libcpu/mips/x1000/cache.h deleted file mode 100644 index 0454527d91..0000000000 --- a/libcpu/mips/x1000/cache.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * File : cache.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��19�� Urey the first version - */ - -#ifndef _X1000_CACHE_H_ -#define _X1000_CACHE_H_ - -#include "../common/mips.h" -#include "../common/mips_cache.h" - - -void rt_hw_icache_invalidate_all(void); -void rt_hw_icache_flush_all(void); - -void rt_hw_dcache_flush_all(void); -void rt_hw_dcache_flush_range(rt_uint32_t addr, rt_uint32_t size); -void rt_hw_dcache_invalidate_all(void); -void rt_hw_dcache_invalidate_range(rt_uint32_t addr,rt_uint32_t size); - -void rt_hw_flush_cache_all(void); -#endif /* _X1000_CACHE_H_ */ diff --git a/libcpu/mips/x1000/cpu.c b/libcpu/mips/x1000/cpu.c deleted file mode 100644 index e1a51b9fe7..0000000000 --- a/libcpu/mips/x1000/cpu.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - * File : cpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��8�� Urey the first version - */ - - -#include <rtthread.h> -#include <board.h> -#include <rthw.h> - -#include "../common/mips.h" - -mips32_core_cfg_t g_mips_core = -{ - .icache_line_size = 32, - .icache_size = 16384, - - .dcache_line_size = 32, - .dcache_size = 16384, - - .max_tlb_entries = 16, /* max_tlb_entries */ -}; - -void rt_hw_tlb_init(void) -{ -//---------------------------------------------------------------------------------- -//cchappy tlb 0x30000000 to 0xC0000000 -//---------------------------------------------------------------------------------- - unsigned int pagemask = 0x007fe000;//0x01ffe000; /* 4MB */ - /* cached D:allow-W V:valid G */ - unsigned int entrylo0 = (0x30000000 >> 6) | (3 << 3) + (1 << 2) + (1 << 1) + 1; - unsigned int entrylo1 = (0x30400000 >> 6) | (3 << 3) + (1 << 2) + (1 << 1) + 1; - unsigned int entryhi = 0xc0000000; /* kseg2 base */ - int i; - __write_32bit_c0_register($5, 4, 0xa9000000); - write_c0_pagemask(pagemask); - write_c0_wired(0); -/* indexed write 32 tlb entry */ - for(i = 0; i < 32; i++) - { - asm ( - ".macro _ssnop; sll $0, $0, 1; .endm\n\t" - ".macro _ehb; sll $0, $0, 3; .endm\n\t" - ".macro mtc0_tlbw_hazard; _ssnop; _ssnop; _ehb; .endm\n\t" - ".macro tlbw_use_hazard; _ssnop; _ssnop; _ssnop; _ehb; .endm\n\t" - "\n\t" - "mtc0 %0, $0\n\t" /* write Index */ - "tlbw_use_hazard\n\t" - "mtc0 %1, $5\n\t" /* write PageMask */ - "mtc0 %2, $10\n\t" /* write EntryHi */ - "mtc0 %3, $2\n\t" /* write EntryLo0 */ - "mtc0 %4, $3\n\t" /* write EntryLo1 */ - "mtc0_tlbw_hazard\n\t" - "tlbwi \n\t" /* TLB indexed write */ - "tlbw_use_hazard\n\t" - : : "Jr" (i), "r" (pagemask), "r" (entryhi), - "r" (entrylo0), "r" (entrylo1) - ); - entryhi += 0x0800000; /* 32MB */ - entrylo0 += (0x0800000 >> 6); - entrylo1 += (0x0800000 >> 6); - } -} - -void rt_hw_cache_init(void) -{ - r4k_cache_flush_all(); -} - -/** - * this function will reset CPU - * - */ -RT_WEAK void rt_hw_cpu_reset() -{ - /* open the watch-dog */ - REG_WDT_TCSR = WDT_TCSR_EXT_EN; - REG_WDT_TCSR |= WDT_TCSR_PRESCALE_1024; - REG_WDT_TDR = 0x03; - REG_WDT_TCNT = 0x00; - REG_WDT_TCER |= WDT_TCER_TCEN; - - rt_kprintf("reboot system...\n"); - rt_hw_interrupt_disable(); - while (1); -} - -/** - * this function will shutdown CPU - * - */ -RT_WEAK void rt_hw_cpu_shutdown() -{ - rt_kprintf("shutdown...\n"); - rt_hw_interrupt_disable(); - while (1); -} - -/** - * This function finds the first bit set (beginning with the least significant bit) - * in value and return the index of that bit. - * - * Bits are numbered starting at 1 (the least significant bit). A return value of - * zero from any of these functions means that the argument was zero. - * - * @return return the index of the first bit set. If value is 0, then this function - * shall return 0. - */ -RT_WEAK int __rt_ffs(int value) -{ - return __builtin_ffs(value); -} diff --git a/libcpu/mips/x1000/interrupt.c b/libcpu/mips/x1000/interrupt.c deleted file mode 100644 index 2a7a42e792..0000000000 --- a/libcpu/mips/x1000/interrupt.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - * File : cpu_intc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016/09/07 Urey the first version - */ - -#include <stdio.h> -#include <stdlib.h> - -#include <rtthread.h> -#include <rthw.h> -#include <board.h> - -#include "../common/mips.h" - -#define INTERRUPTS_MAX 64 - -extern rt_uint32_t rt_interrupt_nest; -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -static struct rt_irq_desc isr_table[INTERRUPTS_MAX]; - -static void rt_hw_interrupt_handler(int vector, void *param) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} - -void rt_hw_interrupt_init(void) -{ - rt_int32_t idx; - - clear_c0_status(0xff04); /* clear ERL */ - set_c0_status(0x0400); /* set IP2 */ - - - rt_memset(isr_table, 0x00, sizeof(isr_table)); - for (idx = 0; idx < INTERRUPTS_MAX; idx ++) - { - isr_table[idx].handler = rt_hw_interrupt_handler; - } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; - - /* enable cpu interrupt mask */ - set_c0_status(IE_IRQ0 | IE_IRQ1); -} - -void rt_hw_interrupt_mask(int vector) -{ - /* mask interrupt */ - __intc_mask_irq(vector); -} - -void rt_hw_interrupt_umask(int vector) -{ - __intc_unmask_irq(vector); -} - -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) -{ - rt_isr_handler_t old_handler = RT_NULL; - - if(vector < INTERRUPTS_MAX) - { - old_handler = isr_table[vector].handler; - -#ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); -#endif /* RT_USING_INTERRUPT_INFO */ - isr_table[vector].handler = handler; - isr_table[vector].param = param; - } - - return old_handler; -} - -rt_inline int fls(int x) -{ - __asm__("clz %0, %1" : "=r" (x) : "r" (x)); - - return 32 - x; -} - -void rt_interrupt_dispatch(void *ptreg) -{ - void *param; - rt_isr_handler_t irq_func; - - int irq = 0, group; - rt_uint32_t intc_ipr0 = 0, intc_ipr1 = 0, vpu_pending = 0; - - rt_uint32_t c0_status, c0_cause; - rt_uint32_t pending_im; - - /* check os timer */ - c0_status = read_c0_status(); - c0_cause = read_c0_cause(); - - pending_im = (c0_cause & ST0_IM) & (c0_status & ST0_IM); - - if (pending_im & CAUSEF_IP3) - { - extern void rt_hw_ost_handler(void); - rt_hw_ost_handler(); - return; - } - if (pending_im & CAUSEF_IP2) - { - intc_ipr0 = REG_INTC_IPR(0); - intc_ipr1 = REG_INTC_IPR(1); - - if (intc_ipr0) - { - irq = fls(intc_ipr0) - 1; - intc_ipr0 &= ~(1<<irq); - } - else if(intc_ipr1) - { - irq = fls(intc_ipr1) - 1; - intc_ipr1 &= ~(1<<irq); - irq += 32; - } - else - { - //VPU - } - - if (irq >= INTERRUPTS_MAX) - rt_kprintf("max interrupt, irq=%d\n", irq); - - /* do interrupt */ - irq_func = isr_table[irq].handler; - param = isr_table[irq].param; - (*irq_func)(irq, param); - -#ifdef RT_USING_INTERRUPT_INFO - isr_table[irq].counter++; -#endif /* RT_USING_INTERRUPT_INFO */ - - /* ack interrupt */ - __intc_ack_irq(irq); - } - - if (pending_im & CAUSEF_IP0) - rt_kprintf("CAUSEF_IP0\n"); - if (pending_im & CAUSEF_IP1) - rt_kprintf("CAUSEF_IP1\n"); - if (pending_im & CAUSEF_IP4) - rt_kprintf("CAUSEF_IP4\n"); - if (pending_im & CAUSEF_IP5) - rt_kprintf("CAUSEF_IP5\n"); - if (pending_im & CAUSEF_IP6) - rt_kprintf("CAUSEF_IP6\n"); - if (pending_im & CAUSEF_IP7) - rt_kprintf("CAUSEF_IP7\n"); -} - -#ifdef RT_USING_INTERRUPT_INFO -#include <finsh.h> -int list_irqs(void) -{ - int index; - - rt_kprintf("interrupt list:\n"); - rt_kprintf("----------------\n"); - rt_kprintf("name counter\n"); - for (index = 0; index < INTERRUPTS_MAX; index ++) - { - if (isr_table[index].handler != rt_hw_interrupt_handler) - { - rt_kprintf("%-*.*s %d\n", RT_NAME_MAX, RT_NAME_MAX, isr_table[index].name, isr_table[index].counter); - } - } - - return 0; -} -MSH_CMD_EXPORT(list_irqs, list interrupt counter); -#endif - -unsigned int spin_lock_irqsave(void) -{ - register unsigned int t; - t = read_c0_status(); - write_c0_status((t & (~1))); - return (t); -} - -void spin_unlock_irqrestore(unsigned int val) -{ - write_c0_status(val); -} diff --git a/libcpu/mips/x1000/mips_backtrace.c b/libcpu/mips/x1000/mips_backtrace.c deleted file mode 100644 index b8a861bad5..0000000000 --- a/libcpu/mips/x1000/mips_backtrace.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * File : mips_backtrace.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��11�� Urey the first version - */ - -#include <rtthread.h> -#include <stdlib.h> -#include <stdio.h> -#include <stdint.h> - -#include "mips.h" - -/********************************************************************************************************* - ָ��� -*********************************************************************************************************/ -#define ADDUI_SP_INST 0x27bd0000 -#define SW_RA_INST 0xafbf0000 -#define JR_RA_INST 0x03e00008 - -#define INST_OP_MASK 0xffff0000 -#define INST_OFFSET_MASK 0x0000ffff - -#define abs(s) ((s) < 0 ? -(s):(s)) - -int backtrace_ctx(mips_reg_ctx *ctx) -{ - unsigned long *addr; - unsigned long *pc, *ra, *sp; - size_t ra_offset; - size_t stack_size; - int depth; - int size = 8; - - pc = (unsigned long *)(unsigned long)ctx->CP0EPC; - ra = (unsigned long *)(unsigned long)ctx->regs[REG_RA]; - sp = (unsigned long *)(unsigned long)ctx->regs[REG_SP]; - - rt_kprintf("[0x%08x]\n", pc); - - if (size == 1) return 1; - - ra_offset = stack_size = 0; - - for (addr = ra; !ra_offset || !stack_size; --addr) - { - switch (*addr & INST_OP_MASK) { - case ADDUI_SP_INST: - stack_size = abs((short)(*addr&INST_OFFSET_MASK)); - break; - - case SW_RA_INST: - ra_offset = (short)(*addr&INST_OFFSET_MASK); - break; - - case 0x3c1c0000: - goto out_of_loop; - - default: - break; - } - } - -out_of_loop: - if (ra_offset) ra = *(unsigned long **)((unsigned long)sp + ra_offset); - if (stack_size) sp = (unsigned long *)((unsigned long)sp + stack_size); - - // repeat backwar scanning - for (depth = 1; depth < size && ra && ra != (unsigned long *)0xffffffff; ++depth) - { - rt_kprintf("RA[%2d] : [0x%08x]\n", depth ,ra); - - ra_offset = 0; - stack_size = 0; - - for ( addr = ra; !ra_offset || !stack_size; -- addr ) - { - switch( *addr & INST_OP_MASK) - { - case ADDUI_SP_INST: - stack_size = abs((short)(*addr&INST_OFFSET_MASK)); - break; - - case SW_RA_INST: - ra_offset = abs((short)(*addr&INST_OFFSET_MASK)); - break; - - case 0x3c1c0000: - return depth +1; - - default: - break; - } - } - - ra = *(unsigned long **)((unsigned long)sp + ra_offset); - sp = (unsigned long *)((unsigned long)sp + stack_size); - } - - return depth; -} - -int backtrace(void) -{ - unsigned long *addr; - unsigned long *ra; - unsigned long *sp; - int size = 8, depth; - - size_t ra_offset; - size_t stack_size; - - // get current $a and $sp - __asm__ __volatile__ ( - " move %0, $ra\n" - " move %1, $sp\n" - : "=r"(ra), "=r"(sp) - ); - - // scanning to find the size of hte current stack frame - stack_size = 0; - - for ( addr = (unsigned long *)backtrace; !stack_size; ++addr) - { - if ((*addr & INST_OP_MASK ) == ADDUI_SP_INST ) - stack_size = abs((short)(*addr&INST_OFFSET_MASK)); - else if ( *addr == JR_RA_INST ) - break; - } - - sp = (unsigned long *) (( unsigned long )sp + stack_size); - - // repeat backwar scanning - for ( depth = 0; depth < size && ((( unsigned long )ra > KSEG0BASE) && (( unsigned long )ra < KSEG1BASE)); ++ depth ) - { - rt_kprintf("RA[%2d] : [0x%08x]\n", depth, ra); - { - extern void rt_thread_exit(void); - if ((uint32_t)ra == (uint32_t)(rt_thread_exit)) - return depth; - } - - ra_offset = 0; - stack_size = 0; - - for ( addr = ra; !ra_offset || !stack_size; -- addr ) - { - switch( *addr & INST_OP_MASK) - { - case ADDUI_SP_INST: - stack_size = abs((short)(*addr&INST_OFFSET_MASK)); - break; - - case SW_RA_INST: - ra_offset = (short)(*addr&INST_OFFSET_MASK); - break; - - case 0x3c1c0000: - return depth +1; - - default: - break; - } - } - - ra = *(unsigned long **)((unsigned long)sp + ra_offset); - sp = (unsigned long*) ((unsigned long)sp+stack_size ); - } - - return depth; -} - -#include <rtthread.h> -extern long list_thread(void); -void assert_hook(const char* ex, const char* func, rt_size_t line) -{ - backtrace(); - - list_thread(); - rt_kprintf("(%s) assertion failed at function:%s, line number:%d \n", ex, func, line); -} - -int backtrace_init(void) -{ -#ifdef RT_DEBUG - rt_assert_set_hook(assert_hook); -#endif - return 0; -} -INIT_DEVICE_EXPORT(backtrace_init); diff --git a/libcpu/mips/x1000/mips_cache_gcc.S b/libcpu/mips/x1000/mips_cache_gcc.S deleted file mode 100644 index 671f193af0..0000000000 --- a/libcpu/mips/x1000/mips_cache_gcc.S +++ /dev/null @@ -1,62 +0,0 @@ -/* - * File : mips_cache_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��19�� Urey the first version - */ - -#ifndef __ASSEMBLY__ -# define __ASSEMBLY__ -#endif - -#include "../common/mips.h" - - .text - .set noreorder - - .globl cache_init - .ent cache_init -cache_init: - .set noreorder - mtc0 zero, CP0_TAGLO - move t0, a0 // cache total size - move t1, a1 // cache line size - li t2, 0x80000000 - addu t3, t0, t2 - -_cache_init_loop: - cache 8, 0(t2) // icache_index_store_tag - cache 9, 0(t2) // dcache_index_store_tag - addu t2, t1 - bne t2, t3, _cache_init_loop - nop - - mfc0 t0, CP0_CONFIG - li t1, 0x7 - not t1 - and t0, t0, t1 - or t0, 0x3 // cacheable, noncoherent, write-back, write allocate - mtc0 t0, CP0_CONFIG - - jr ra - nop - - .set reorder - .end cache_init diff --git a/libcpu/mips/x1000/mips_context_gcc.S b/libcpu/mips/x1000/mips_context_gcc.S deleted file mode 100644 index d4c314ab65..0000000000 --- a/libcpu/mips/x1000/mips_context_gcc.S +++ /dev/null @@ -1,95 +0,0 @@ -/* - * File : mips_context_asm.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��7�� Urey the first version - */ - -#ifndef __ASSEMBLY__ -# define __ASSEMBLY__ -#endif - -#include "../common/mips.h" - - .global rt_thread_switch_interrupt_flag - .global rt_interrupt_from_thread - .global rt_interrupt_to_thread - - .section .text,"ax",@progbits - .set noreorder - .set noat - - .globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mfc0 v0,CP0_STATUS - srl v1,v0,1 - sll v1,v1,1 -# and v1,v0,0xfffffffe - mtc0 v1,CP0_STATUS - jr ra - nop - -LEAF(rt_hw_interrupt_enable) - mtc0 a0,CP0_STATUS - jr ra - nop -END(rt_hw_interrupt_enable) - -/* - * void rt_hw_context_switch_to(rt_uint32 to)/* - * a0 --> to - */ -LEAF(rt_hw_context_switch_to) - lw sp , 0(a0) /* switch to the new stack */ - RESTORE_CONTEXT -END(rt_hw_context_switch_to) - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) - * a0 --> from - * a1 --> to - */ -LEAF(rt_hw_context_switch) - mtc0 ra, CP0_EPC - SAVE_CONTEXT - - sw sp, 0(a0) /* store sp in preempted tasks TCB */ - lw sp, 0(a1) /* get new task stack pointer */ - - RESTORE_CONTEXT -END(rt_hw_context_switch) - -LEAF(rt_hw_context_switch_interrupt) - la t0, rt_thread_switch_interrupt_flag - lw t1, 0(t0) - nop - bnez t1, _reswitch - nop - li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ - sw t1, 0(t0) - la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ - sw a0, 0(t0) -_reswitch: - la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ - sw a1, 0(t0) - jr ra - nop -END(rt_hw_context_switch_interrupt) - diff --git a/libcpu/mips/x1000/mips_excpt.c b/libcpu/mips/x1000/mips_excpt.c deleted file mode 100644 index 5d2a3dce6d..0000000000 --- a/libcpu/mips/x1000/mips_excpt.c +++ /dev/null @@ -1,382 +0,0 @@ -/* - * File : mips_excpt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��7�� Urey the first version - */ - -#include <rtthread.h> -#include <rthw.h> -#include <stdio.h> - -#include "mips.h" -#include "mips_excpt.h" - -extern int backtrace(void); -int backtrace_ctx(mips_reg_ctx *ctx); - -extern long list_thread(void); - -const static char *regstr[] = { - "$0 zero", "$1 at", "$2 v0", "$3 v1", "$4 a0", "$5 a1", "$6 a2", "$7 a3", - "$8 t0", "$9 t1", "$10 t2", "$11 t3", "$12 t4", "$13 t5", "$14 t6", "$15 t7", - "$16 s0", "$17 s1", "$18 s2", "$19 s3", "$20 s4", "$21 s5", "$22 s6", "$23 s7", - "$24 t8", "$25 t9", "$26 k0", "$27 k1", "$28 gp", "$29 sp", "$30 fp", "$31 ra" -}; - -static const char *cause_strings[32] = -{ - /* 0 */ "Int", - /* 1 */ "TLB Mods", - /* 2 */ "TLB Load", - /* 3 */ "TLB Store", - /* 4 */ "Address Load", - /* 5 */ "Address Store", - /* 6 */ "Instruction Bus Error", - /* 7 */ "Data Bus Error", - /* 8 */ "Syscall", - /* 9 */ "Breakpoint", - /* 10 */ "Reserved Instruction", - /* 11 */ "Coprocessor Unuseable", - /* 12 */ "Overflow", - /* 13 */ "Trap", - /* 14 */ "Instruction Virtual Coherency Error", - /* 15 */ "FP Exception", - /* 16 */ "Reserved 16", - /* 17 */ "Reserved 17", - /* 18 */ "Reserved 18", - /* 19 */ "Reserved 19", - /* 20 */ "Reserved 20", - /* 21 */ "Reserved 21", - /* 22 */ "Reserved 22", - /* 23 */ "Watch", - /* 24 */ "Reserved 24", - /* 25 */ "Reserved 25", - /* 26 */ "Reserved 26", - /* 27 */ "Reserved 27", - /* 28 */ "Reserved 28", - /* 29 */ "Reserved 29", - /* 30 */ "Reserved 30", - /* 31 */ "Data Virtual Coherency Error" -}; - - -/** - * exception handle table - */ -exception_func_t sys_exception_handlers[32]; - -static void mod_handler(mips_reg_ctx *regs) -{ - rt_kprintf("tlb modification exception\n"); - rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_kprintf(" cause: 0x%08x\n", read_c0_cause()); - - list_thread(); - - printf("-----------------------------------------------------\n"); - printf("BACKTRACE:\n"); - backtrace(); - printf("-----------------------------------------------------\n"); - - rt_hw_cpu_shutdown(); -} - -static void tlbl_handler(mips_reg_ctx *regs) -{ - rt_kprintf("tlb exception: load\n"); - rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_kprintf(" cause: 0x%08x\n", read_c0_cause()); - - list_thread(); - - printf("-----------------------------------------------------\n"); - printf("BACKTRACE:\n"); - backtrace(); - printf("-----------------------------------------------------\n"); - - rt_hw_cpu_shutdown(); -} - -static void tlbs_handler(mips_reg_ctx *regs) -{ - rt_kprintf("tlb exception: store\n"); - rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_kprintf(" cause: 0x%08x\n", read_c0_cause()); - - list_thread(); - - printf("-----------------------------------------------------\n"); - printf("BACKTRACE:\n"); - backtrace(); - printf("-----------------------------------------------------\n"); - - rt_hw_cpu_shutdown(); -} - -static void adel_handler(mips_reg_ctx *regs) -{ - rt_kprintf("address error exception: load\n"); - rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_kprintf(" cause: 0x%08x\n", read_c0_cause()); - - list_thread(); - rt_kprintf("current thread: %.*s\n", RT_NAME_MAX, rt_thread_self()->name); - - printf("-----------------------------------------------------\n"); - printf("BACKTRACE:\n"); - backtrace(); - printf("-----------------------------------------------------\n"); - - rt_hw_cpu_shutdown(); -} - -static void ades_handler(mips_reg_ctx *regs) -{ - rt_kprintf("address error exception: store\n"); - rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_kprintf(" cause: 0x%08x\n", read_c0_cause()); - - list_thread(); - - printf("-----------------------------------------------------\n"); - printf("BACKTRACE:\n"); - backtrace(); - printf("-----------------------------------------------------\n"); - - rt_hw_cpu_shutdown(); -} - -static void fpe_handler(mips_reg_ctx *regs) -{ - rt_kprintf("floating point exception\n"); - rt_kprintf("exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_kprintf(" cause: 0x%08x\n", read_c0_cause()); - - list_thread(); - - printf("-----------------------------------------------------\n"); - printf("BACKTRACE:\n"); - backtrace(); - printf("-----------------------------------------------------\n"); - - rt_hw_cpu_shutdown(); -} - - -static void unhandled_exception_handle(mips_reg_ctx *regs) -{ - int i; - unsigned int cause = read_c0_cause(); - unsigned int exc = (cause >> 2) & 0x1f; - - rt_kprintf("exception happens, epc: 0x%08x\n", regs->CP0EPC); - rt_kprintf(" cause: 0x%08x\n", regs->CP0Cause); - - for (i = 0; i < 32; i++) - { - if (i % 4 == 0) - printf("\n"); - printf("%8s %08x ", regstr[i], regs->regs[i]); - } - printf("\n"); - - list_thread(); - rt_hw_cpu_shutdown(); -} - -static void install_default_exception_handler(void) -{ - int i; - - for (i=0; i<sizeof(sys_exception_handlers)/sizeof(sys_exception_handlers[0]); i++) - sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle; - - sys_exception_handlers[EX_MOD] = mod_handler; - sys_exception_handlers[EX_TLBL] = tlbl_handler; - sys_exception_handlers[EX_TLBS] = tlbs_handler; - sys_exception_handlers[EX_ADEL] = adel_handler; - sys_exception_handlers[EX_ADES] = ades_handler; - sys_exception_handlers[EX_FPE] = fpe_handler; -} - -int rt_hw_exception_init(void) -{ - /* install the default exception handler */ - install_default_exception_handler(); - - return RT_EOK; -} - -/** - * setup the exception handle - */ -exception_func_t rt_set_except_vector(int n, exception_func_t func) -{ - exception_func_t old_handler = sys_exception_handlers[n]; - - if ((n == 0) || (n > 32) || (!func)) - { - return 0; - } - - sys_exception_handlers[n] = func; - - return old_handler; -} - -void mips_exception_handler(mips_reg_ctx *ctx) -{ - static int read_epc_count = 0; - static int epc_save = 0; - int i; - unsigned int epc; - - //��� read_epc_count>0 ˵�� c_except_handler �ڶ� epc ʱ�����ˣ����� epc ������һ���µ��쳣 - if (read_epc_count > 0) - { - printf("ERROR: read epc fail when except handle\n"); - epc = epc_save; - read_epc_count = 0; - } - else - { - read_epc_count++; - epc_save = 0; - epc = read_c0_epc(); - epc_save = epc; - - if (epc != 0) - { - printf("-----------------------------------------------------\n"); - for (i = 0; i < 4; i++) - { - printf("%08x:\t%08x\n", - (epc - 4 * 4 + i * 4), - *(unsigned int *) ((epc - 4 * 4 + i * 4) | 0xa0000000)); - } - for (i = 0; i < 4; i++) - { - printf("%08x:\t%08x\n", - (epc + i * 4), - *(unsigned int *) ((epc + i * 4) | 0xa0000000)); - } - printf("-----------------------------------------------------\n"); - } - - read_epc_count--; - } - - printf("-----------------------------------------------------\n"); - unsigned int cause = read_c0_cause(); - unsigned int exc = (cause >> 2) & 0x1f; - printf("CAUSE=%08x --> %s\n", cause, cause_strings[exc]); - printf("EPC=%08x\n", epc); - - for (i = 0; i < 32; i++) - { - if ((i != 0) && (i % 4 == 0)) - printf("\n"); - printf("%8s %08x ", regstr[i], ctx->regs[i]); - } - printf("\n-----------------------------------------------------\n"); - printf("%s: \t %8x\n","CP0Status ", ctx->CP0Status); - printf("%s: \t %8x\n","CP0DataHI ", ctx->CP0DataHI); - printf("%s: \t %8x\n","CP0DataLO ", ctx->CP0DataLO); - printf("%s: \t %8x\n","CP0BadVAddr", ctx->CP0BadVAddr); - printf("%s: \t %8x\n","CP0Cause ", ctx->CP0Cause); - printf("%s: \t %8x\n","CP0EPC ", ctx->CP0EPC); - printf("-----------------------------------------------------\n"); - -#if 0 - switch (exc) - { - case EX_MOD: - /* TLB modified */ - break; - - case EX_TLBL: /* TLB exc(load or ifetch) */ - case EX_TLBS: /* TLB exception (store) */ - - break; - - case EX_ADEL: /* Address err(load or ifetch) */ - case EX_ADES: /* Address error (store) */ - - break; - - case EX_IBE: /* Instruction Bus Error */ - case EX_DBE: /* Data Bus Error */ - - break; - - case EX_SYS: /* Syscall */ - - break; - - case EX_BP: /* Breakpoint */ - case EX_TR: /* Trap instruction */ - - break; - case EX_RI: /* Reserved instruction */ - - break; - case EX_FPE: /* floating point exception */ - break; - - case EX_CPU: /* CoProcessor Unusable */ - - break; - case EX_OV: /* OVerflow */ - case EX_C2E: /* COP2 exception */ - case EX_MDMX: /* MDMX exception */ - case EX_WATCH: /* Watch exception */ - case EX_MCHECK: /* Machine check exception */ - case EX_CacheErr: /* Cache error caused re-entry */ - /* to Debug Mode */ - - break; - default: - rt_kprintf("Unknow exception: %d\r\n", exc); - break; - } -#else - sys_exception_handlers[exc](ctx); -#endif - - rt_hw_cpu_shutdown(); -} - - -void mips_cache_error_handler (unsigned int Addr) -{ - rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); - list_thread(); - rt_hw_cpu_shutdown(); -} - -void mips_tlb_refill_handler(void) -{ - rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); - rt_kprintf(" cause: 0x%08x\n", read_c0_cause()); - list_thread(); - rt_kprintf("current thread: %s\n", rt_thread_self()->name); - rt_hw_cpu_shutdown(); -} diff --git a/libcpu/mips/x1000/mips_excpt_gcc.S b/libcpu/mips/x1000/mips_excpt_gcc.S deleted file mode 100644 index c403adf93b..0000000000 --- a/libcpu/mips/x1000/mips_excpt_gcc.S +++ /dev/null @@ -1,102 +0,0 @@ -/* - * File : mips_excpt_asm.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��7�� Urey the first version - */ - -#ifndef __ASSEMBLY__ -# define __ASSEMBLY__ -#endif - -#include "../common/mips.h" - -#define _EXC_STKSIZE 20*1024 - -;/********************************************************************************************************* -; PTE BASE ��ض��� -;*********************************************************************************************************/ - -#define PTE_BASE_OFFSET 23 -#define PTE_BASE_SIZE 9 -#define MIPS32_BADVPN2_SHIFT 2 - - - .section ".text", "ax" - .set noreorder - -LEAF(mips_tlb_refill_handlerx) - .set push - .set noat - .set noreorder - .set volatile - - ;/* - ; * K1 = CP0_CTXT - ; * K0 = K1 - ; */ - mfc0 k1 , CP0_CONTEXT ;/* K1 ���� Context �Ĵ��� */ - ehb - move k0 , k1 ;/* K0 ���� Context �Ĵ��� */ - - ;/* - ; * K1 <<= PTE_BASE_SIZE - ; * K1 >>= PTE_BASE_SIZE - ; * K1 >>= 4 - ; * K1 >>= MIPS32_BADVPN2_SHIFT - ; * K1 <<= 3 - ; */ - sll k1 , PTE_BASE_SIZE - srl k1 , (PTE_BASE_SIZE + 4 + MIPS32_BADVPN2_SHIFT) ;/* K1 Ϊ BAD VPN2 */ - sll k1 , (4 - 1) - - ;/* - ; * K0 >>= PTE_BASE_OFFSET - ; * K0 <<= PTE_BASE_OFFSET - ; */ - srl k0 , PTE_BASE_OFFSET - sll k0 , PTE_BASE_OFFSET ;/* K0 Ϊ PTE BASE */ - - ;/* - ; * K1 = K1 | K0 - ; */ - or k1 , k1 , k0 ;/* �ϳ� */ - - ;/* - ; * K0 = *K1 - ; * K1 = *(K1 + 4) - ; */ - lw k0 , 0(k1) - lw k1 , 4(k1) - - ;/* - ; * CP0_TLBLO0 = K0 - ; * CP0_TLBLO1 = K1 - ; */ - mtc0 k0 , CP0_ENTRYLO0 ;/* EntryLo0 */ - mtc0 k1 , CP0_ENTRYLO1 ;/* EntryLo1 */ - ehb - - tlbwr ;/* TLB ����滻 */ - - eret ;/* �쳣���� */ - - .set pop -END(mips_tlb_refill_handlerx) diff --git a/libcpu/mips/x1000/mips_fp_gcc.S b/libcpu/mips/x1000/mips_fp_gcc.S deleted file mode 100644 index b219084065..0000000000 --- a/libcpu/mips/x1000/mips_fp_gcc.S +++ /dev/null @@ -1,197 +0,0 @@ -/* - * File : mips_vfp32_asm.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��9�� Urey the first version - */ - -#ifndef __ASSEMBLY__ -# define __ASSEMBLY__ -#endif - -#ifdef __mips_hard_float - -.module hardfloat -.module doublefloat -.set nomips16 - -#include "../common/mips.h" -#undef fp - - .global mips_vfp32_init -LEAF(mips_vfp32_init) - mfc0 t0, CP0_STATUS - or t0 , M_StatusCU1 - mtc0 t0, CP0_STATUS - jr ra - nop -END(mips_vfp32_init) - -# -# FUNCTION: _fpctx_save -# -# DESCRIPTION: save floating point registers to memory starting at a0 -# -# RETURNS: int -# 0: No context saved -# CTX_*: Type of context stored -# - .global _fpctx_save -LEAF(_fpctx_save) - sw zero, LINKCTX_NEXT(a0) - mfc0 t0, CP0_STATUS - li t1, M_StatusCU1 - and t1, t0, t1 - bnez t1, 1f - # FP not enabled, bail out - move v0, zero - jr ra - -1: # Save FP32 base - li t1, ST0_FR - and t0, t0, t1 - cfc1 t2, $31 - sw t2, FP32CTX_CSR(a0) - sdc1 $f0, FP32CTX_0(a0) - sdc1 $f2, FP32CTX_2(a0) - sdc1 $f4, FP32CTX_4(a0) - sdc1 $f6, FP32CTX_6(a0) - sdc1 $f8, FP32CTX_8(a0) - sdc1 $f10, FP32CTX_10(a0) - sdc1 $f12, FP32CTX_12(a0) - sdc1 $f14, FP32CTX_14(a0) - sdc1 $f16, FP32CTX_16(a0) - sdc1 $f18, FP32CTX_18(a0) - sdc1 $f20, FP32CTX_20(a0) - sdc1 $f22, FP32CTX_22(a0) - sdc1 $f24, FP32CTX_24(a0) - sdc1 $f26, FP32CTX_26(a0) - sdc1 $f28, FP32CTX_28(a0) - sdc1 $f30, FP32CTX_30(a0) - bnez t0, 2f - li v0, LINKCTX_TYPE_FP32 - sw v0, LINKCTX_ID(a0) - jr ra - -2: # Save FP64 extra -.set push -.set fp=64 - sdc1 $f1, FP64CTX_1(a0) - sdc1 $f3, FP64CTX_3(a0) - sdc1 $f5, FP64CTX_5(a0) - sdc1 $f7, FP64CTX_7(a0) - sdc1 $f9, FP64CTX_9(a0) - sdc1 $f11, FP64CTX_11(a0) - sdc1 $f13, FP64CTX_13(a0) - sdc1 $f15, FP64CTX_15(a0) - sdc1 $f17, FP64CTX_17(a0) - sdc1 $f19, FP64CTX_19(a0) - sdc1 $f21, FP64CTX_21(a0) - sdc1 $f23, FP64CTX_23(a0) - sdc1 $f25, FP64CTX_25(a0) - sdc1 $f27, FP64CTX_27(a0) - sdc1 $f29, FP64CTX_29(a0) - sdc1 $f31, FP64CTX_31(a0) -.set pop - li v0, LINKCTX_TYPE_FP64 - sw v0, LINKCTX_ID(a0) - jr ra -END(_fpctx_save) - -# -# FUNCTION: _fpctx_load -# -# DESCRIPTION: load floating point registers from context chain starting at a0 -# -# RETURNS: int -# 0: Unrecognised context -# CTX_*: Type of context restored -# - .global _fpctx_load -LEAF(_fpctx_load) - lw v0, LINKCTX_ID(a0) - # Detect type - li t0, LINKCTX_TYPE_FP64 - li t1, LINKCTX_TYPE_FP32 - li t2, M_StatusCU1 - beq v0, t0, 0f - beq v0, t1, 1f - # Don't recognise this context, fail - move v0, zero - jr ra - -0: # FP64 context - # Enable CU1 - di t3 - ehb - or t3, t3, t2 - mtc0 t3, CP0_STATUS - ehb - # Load FP64 extra -.set push -.set fp=64 - ldc1 $f1, FP64CTX_1(a0) - ldc1 $f3, FP64CTX_3(a0) - ldc1 $f5, FP64CTX_5(a0) - ldc1 $f7, FP64CTX_7(a0) - ldc1 $f9, FP64CTX_9(a0) - ldc1 $f11, FP64CTX_11(a0) - ldc1 $f13, FP64CTX_13(a0) - ldc1 $f15, FP64CTX_15(a0) - ldc1 $f17, FP64CTX_17(a0) - ldc1 $f19, FP64CTX_19(a0) - ldc1 $f21, FP64CTX_21(a0) - ldc1 $f23, FP64CTX_23(a0) - ldc1 $f25, FP64CTX_25(a0) - ldc1 $f27, FP64CTX_27(a0) - ldc1 $f29, FP64CTX_29(a0) - ldc1 $f31, FP64CTX_31(a0) -.set pop -1: # FP32 context - # Enable CU1 - di t3 - ehb - or t3, t3, t2 - mtc0 t3, CP0_STATUS - ehb - # Load FP32 base - lw t1, FP32CTX_CSR(a0) - ctc1 t1, $31 - ldc1 $f0, FP32CTX_0(a0) - ldc1 $f2, FP32CTX_2(a0) - ldc1 $f4, FP32CTX_4(a0) - ldc1 $f6, FP32CTX_6(a0) - ldc1 $f8, FP32CTX_8(a0) - ldc1 $f10, FP32CTX_10(a0) - ldc1 $f12, FP32CTX_12(a0) - ldc1 $f14, FP32CTX_14(a0) - ldc1 $f16, FP32CTX_16(a0) - ldc1 $f18, FP32CTX_18(a0) - ldc1 $f20, FP32CTX_20(a0) - ldc1 $f22, FP32CTX_22(a0) - ldc1 $f24, FP32CTX_24(a0) - ldc1 $f26, FP32CTX_26(a0) - ldc1 $f28, FP32CTX_28(a0) - ldc1 $f30, FP32CTX_30(a0) - # Return CTX_FP32/64 - jr ra -END(_fpctx_load) - -#endif diff --git a/libcpu/mips/x1000/stack.c b/libcpu/mips/x1000/stack.c deleted file mode 100644 index 0043ea2a21..0000000000 --- a/libcpu/mips/x1000/stack.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * File : stack.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��8�� Urey the first version - */ - -#include <rtthread.h> - -#include "../common/mips.h" - -register U32 $GP __asm__ ("$28"); - -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) -{ - static rt_uint32_t wSR=0; - static rt_uint32_t wGP; - - mips_reg_ctx *regCtx; - mips_arg_ctx *argCtx; - rt_uint32_t i; - - if (wSR == 0) - { - wSR = read_c0_status(); - wSR &= 0xfffffffe; - wSR |= 0x0403; - - wGP = $GP; - } - - if ((rt_uint32_t) stack_addr & 0x7) - { - stack_addr = (rt_uint8_t *)((rt_uint32_t)stack_addr - 4); - } - - argCtx = (mips_arg_ctx *)((rt_uint32_t)stack_addr - sizeof(mips_arg_ctx)); - regCtx = (mips_reg_ctx *)((rt_uint32_t)stack_addr - sizeof(mips_arg_ctx) - sizeof(mips_reg_ctx)); - - for (i = 0; i < 4; ++i) - { - argCtx->args[i] = i; - } - - //����ͨ�üĴ��� - for (i = 0; i < 32; ++i) - { - regCtx->regs[i] = i; - } - - regCtx->regs[REG_SP] = (rt_uint32_t)stack_addr; - regCtx->regs[REG_A0] = (rt_uint32_t)parameter; - regCtx->regs[REG_GP] = (rt_uint32_t)wGP; - regCtx->regs[REG_FP] = (rt_uint32_t)0x0; - regCtx->regs[REG_RA] = (rt_uint32_t)texit; - - regCtx->CP0DataLO = 0x00; - regCtx->CP0DataHI = 0x00; - regCtx->CP0Cause = read_c0_cause(); - regCtx->CP0Status = wSR; - regCtx->CP0EPC = (rt_uint32_t)tentry; - regCtx->CP0BadVAddr= 0x00; - - return (rt_uint8_t *)(regCtx); -} diff --git a/libcpu/mips/x1000/startup_gcc.S b/libcpu/mips/x1000/startup_gcc.S deleted file mode 100644 index 1376cb7dd4..0000000000 --- a/libcpu/mips/x1000/startup_gcc.S +++ /dev/null @@ -1,328 +0,0 @@ -/* - * File : startup.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2016��9��7�� Urey the first version - */ - -#ifndef __ASSEMBLY__ -# define __ASSEMBLY__ -#endif - -#include "../common/mips.h" - -#define IRQ_STACK_SIZE 0x2000 -#define EXC_STACK_SIZE 0x2000 - - - .section ".bss" - ALIGN(4) -irq_stack_low: - .space IRQ_STACK_SIZE -irq_stack_top: - .space 8 - - ALIGN(4) -exc_stack_low: - .space EXC_STACK_SIZE -exc_stack_top: - .space 8 - -#define SYSTEM_STACK 0x80003fe8 - -;/********************************************************************************************************* -; ��� -;*********************************************************************************************************/ - .global rtthread_startup - .global mips_vfp32_init - - .global _start - .section ".start", "ax" - .set noreorder -_start: - .set noreorder - la ra, _start - - li t1, 0x00800000 - mtc0 t1, CP0_CAUSE - - /* init cp0 registers. */ - li t0, 0x1000FC00 /* BEV = 0 and mask all interrupt */ - mtc0 t0, CP0_STATUS - -#ifdef __mips_hard_float - jal mips_vfp32_init - nop -#endif - - /* setup stack pointer */ - li sp, SYSTEM_STACK - la gp, _gp - -_cache_init: - /* init caches, assumes a 4way * 128set * 32byte I/D cache */ - mtc0 zero, CP0_TAGLO /* TAGLO reg */ - mtc0 zero, CP0_TAGHI /* TAGHI reg */ - li t0, 3 /* enable cache for kseg0 accesses */ - mtc0 t0, CP0_CONFIG /* CONFIG reg */ - la t0, 0x80000000 /* an idx op should use an unmappable address */ - ori t1, t0, 0x4000 /* 16kB cache */ - -_cache_loop: - cache 0x8, 0(t0) /* index store icache tag */ - cache 0x9, 0(t0) /* index store dcache tag */ - bne t0, t1, _cache_loop - addiu t0, t0, 0x20 /* 32 bytes per cache line */ - nop - - /* invalidate BTB */ - mfc0 t0, CP0_CONFIG - nop - ori t0, 2 - mtc0 t0, CP0_CONFIG - nop - - - /* jump to RT-Thread RTOS */ - jal rtthread_startup - nop - - /* restart, never die */ - j _start - nop - .set reorder - - -;/********************************************************************************************************* -; �쳣������ -;*********************************************************************************************************/ - /* 0x0 - TLB refill handler */ - .section .vectors.1, "ax", %progbits - j mips_tlb_refill_entry - nop - - /* 0x100 - Cache error handler */ - .section .vectors.2, "ax", %progbits - j mips_cache_error_entry - nop - - /* 0x180 - Exception/Interrupt handler */ - .section .vectors.3, "ax", %progbits - j mips_exception_entry - nop - - /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */ - .section .vectors.4, "ax", %progbits - j mips_interrupt_entry - nop - .section .vectors, "ax", %progbits - - .global mips_exception_handler -// .global mips_syscall -LEAF(mips_exception_entry) - .set push - .set noat - .set noreorder - .set volatile - - mfc0 k0, C0_CAUSE - andi k0, k0, 0x7c - beq zero, k0, except_do_intr - nop - - andi k0,(0x08 << 2) - beq zero,k0,except_do - nop -except_do_intr: - la k0,mips_interrupt_entry - jr k0 - nop -except_do_syscall: -// la k0,mips_syscall -// jr k0 - nop -except_do: - //save sp - move k0,sp - //la sp, exc_stack_top - subu sp, sp, CONTEXT_SIZE - //save context - sw $0, (4*0)(sp); - sw $1, (4*1)(sp); - sw $2, (4*2)(sp); - sw $3, (4*3)(sp); - sw $4, (4*4)(sp); - sw $5, (4*5)(sp); - sw $6, (4*6)(sp); - sw $7, (4*7)(sp); - sw $8, (4*8)(sp); - sw $9, (4*9)(sp); - sw $10, (4*10)(sp); - sw $11, (4*11)(sp); - sw $12, (4*12)(sp); - sw $13, (4*13)(sp); - sw $14, (4*14)(sp); - sw $15, (4*15)(sp); - sw $16, (4*16)(sp); - sw $17, (4*17)(sp); - sw $18, (4*18)(sp); - sw $19, (4*19)(sp); - sw $20, (4*20)(sp); - sw $21, (4*21)(sp); - sw $22, (4*22)(sp); - sw $23, (4*23)(sp); - sw $24, (4*24)(sp); - sw $25, (4*25)(sp); - sw $26, (4*26)(sp); - sw $27, (4*27)(sp); - sw $28, (4*28)(sp); - sw k0, (4*29)(sp); //old sp - sw $30, (4*30)(sp); - sw $31, (4*31)(sp); - - /* STATUS CAUSE EPC.... */ - mfc0 $2, CP0_STATUS - sw $2, STK_OFFSET_SR(sp) - - mfc0 $2, CP0_CAUSE - sw $2, STK_OFFSET_CAUSE(sp) - - mfc0 $2, CP0_BADVADDR - sw $2, STK_OFFSET_BADVADDR(sp) - - MFC0 $2, CP0_EPC - sw $2, STK_OFFSET_EPC(sp) - - mfhi $2 - sw $2, STK_OFFSET_HI(sp) - - mflo $2 - sw $2, STK_OFFSET_LO(sp) - - move a0, sp - la k0, mips_exception_handler - j k0 - nop - - // - - .set pop -END(mips_exception_entry) - - .global mips_tlb_refill_handler -LEAF(mips_tlb_refill_entry) - .set push - .set noat - .set noreorder - .set volatile - - la k0,mips_tlb_refill_handler - jr k0 - - nop - eret - nop - - .set pop -END(mips_tlb_refill_entry) - - .global mips_cache_error_handler -LEAF(mips_cache_error_entry) - .set push - .set noat - .set noreorder - .set volatile - - la k0,mips_cache_error_handler - jr k0 - nop - eret - nop - - .set pop -END(mips_cache_error_entry) - - - -.global rt_interrupt_dispatch -.global rt_interrupt_enter -.global rt_interrupt_leave -LEAF(mips_interrupt_entry) - .set push - .set noat - .set noreorder - .set volatile - - //mfc0 k0,CP0_EPC - SAVE_CONTEXT - - mfc0 t0, CP0_CAUSE - mfc0 t1, CP0_STATUS - and t0, t1 - - andi t0, 0xff00 - beqz t0, spurious_interrupt - nop - - /* let k0 keep the current context sp */ - move k0, sp - - /* switch to kernel stack */ - la sp, irq_stack_top - jal rt_interrupt_enter - nop - jal rt_interrupt_dispatch - nop - jal rt_interrupt_leave - nop - - /* switch sp back to thread's context */ - move sp, k0 - - /* - * if rt_thread_switch_interrupt_flag set, jump to - * rt_hw_context_switch_interrupt_do and don't return - */ - la k0, rt_thread_switch_interrupt_flag - lw k1, 0(k0) - beqz k1, spurious_interrupt - nop - sw zero, 0(k0) /* clear flag */ - nop - - /* - * switch to the new thread - */ - la k0, rt_interrupt_from_thread - lw k1, 0(k0) - nop - sw sp, 0(k1) /* store sp in preempted tasks's TCB */ - - la k0, rt_interrupt_to_thread - lw k1, 0(k0) - nop - lw sp, 0(k1) /* get new task's stack pointer */ - j spurious_interrupt - nop -spurious_interrupt: - RESTORE_CONTEXT - - .set pop -END(mips_interrupt_entry) diff --git a/libcpu/mips/x1000/x1000.h b/libcpu/mips/x1000/x1000.h deleted file mode 100644 index aa18297395..0000000000 --- a/libcpu/mips/x1000/x1000.h +++ /dev/null @@ -1,284 +0,0 @@ -/* - * File : x1000.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2015-11-19 Urey the first version - */ - -#ifndef __X1000_H__ -#define __X1000_H__ - -#include "../common/mips.h" - -#ifndef __ASSEMBLY__ - -#define cache_unroll(base,op) \ - __asm__ __volatile__(" \ - .set noreorder; \ - .set mips3; \ - cache %1, (%0); \ - .set mips0; \ - .set reorder" \ - : \ - : "r" (base), \ - "i" (op)); - -/* cpu pipeline flush */ -static inline void jz_sync(void) -{ - __asm__ volatile ("sync"); -} - -static inline void writeb(u8 value, u32 address) -{ - *((volatile u8 *) address) = value; -} -static inline void writew( u16 value, u32 address) -{ - *((volatile u16 *) address) = value; -} -static inline void writel(u32 value, u32 address) -{ - *((volatile u32 *) address) = value; -} - -static inline u8 readb(u32 address) -{ - return *((volatile u8 *)address); -} - -static inline u16 readw(u32 address) -{ - return *((volatile u16 *)address); -} - -static inline u32 readl(u32 address) -{ - return *((volatile u32 *)address); -} - -static inline void jz_writeb(u32 address, u8 value) -{ - *((volatile u8 *)address) = value; -} - -static inline void jz_writew(u32 address, u16 value) -{ - *((volatile u16 *)address) = value; -} - -static inline void jz_writel(u32 address, u32 value) -{ - *((volatile u32 *)address) = value; -} - -static inline u8 jz_readb(u32 address) -{ - return *((volatile u8 *)address); -} - -static inline u16 jz_readw(u32 address) -{ - return *((volatile u16 *)address); -} - -static inline u32 jz_readl(u32 address) -{ - return *((volatile u32 *)address); -} - -#define BIT(n) (0x01u << (n)) -#define BIT0 (0x01u << 0) -#define BIT1 (0x01u << 1) -#define BIT2 (0x01u << 2) -#define BIT3 (0x01u << 3) -#define BIT4 (0x01u << 4) -#define BIT5 (0x01u << 5) -#define BIT6 (0x01u << 6) -#define BIT7 (0x01u << 7) -#define BIT8 (0x01u << 8) -#define BIT9 (0x01u << 9) -#define BIT10 (0x01u << 10) -#define BIT11 (0x01u << 11) -#define BIT12 (0x01u << 12) -#define BIT13 (0x01u << 13) -#define BIT14 (0x01u << 14) -#define BIT15 (0x01u << 15) -#define BIT16 (0x01u << 16) -#define BIT17 (0x01u << 17) -#define BIT18 (0x01u << 18) -#define BIT19 (0x01u << 19) -#define BIT20 (0x01u << 20) -#define BIT21 (0x01u << 21) -#define BIT22 (0x01u << 22) -#define BIT23 (0x01u << 23) -#define BIT24 (0x01u << 24) -#define BIT25 (0x01u << 25) -#define BIT26 (0x01u << 26) -#define BIT27 (0x01u << 27) -#define BIT28 (0x01u << 28) -#define BIT29 (0x01u << 29) -#define BIT30 (0x01u << 30) -#define BIT31 (0x01u << 31) - -/* Generate the bit field mask from msb to lsb */ -#define BITS_H2L(msb, lsb) ((0xFFFFFFFF >> (32-((msb)-(lsb)+1))) << (lsb)) - - -/* Get the bit field value from the data which is read from the register */ -#define get_bf_value(data, lsb, mask) (((data) & (mask)) >> (lsb)) - -#endif /* !ASSEMBLY */ - - -//---------------------------------------------------------------------- -// Register Definitions -// -/* AHB0 BUS Devices Base */ -#define HARB0_BASE 0xB3000000 -#define EMC_BASE 0xB3010000 -#define DDRC_BASE 0xB3020000 -#define MDMAC_BASE 0xB3030000 -#define LCD_BASE 0xB3050000 -#define TVE_BASE 0xB3050000 -#define SLCD_BASE 0xB3050000 -#define CIM_BASE 0xB3060000 -#define IPU_BASE 0xB3080000 -/* AHB1 BUS Devices Base */ -#define HARB1_BASE 0xB3200000 -#define DMAGP0_BASE 0xB3210000 -#define DMAGP1_BASE 0xB3220000 -#define DMAGP2_BASE 0xB3230000 -#define MC_BASE 0xB3250000 -#define ME_BASE 0xB3260000 -#define DEBLK_BASE 0xB3270000 -#define IDCT_BASE 0xB3280000 -#define CABAC_BASE 0xB3290000 -#define TCSM0_BASE 0xB32B0000 -#define TCSM1_BASE 0xB32C0000 -#define SRAM_BASE 0xB32D0000 -/* AHB2 BUS Devices Base */ -#define HARB2_BASE 0xB3400000 -#define NEMC_BASE 0xB3410000 -#define DMAC_BASE 0xB3420000 -#define UHC_BASE 0xB3430000 -//#define UDC_BASE 0xB3440000 -#define SFC_BASE 0xB3440000 -#define GPS_BASE 0xB3480000 -#define ETHC_BASE 0xB34B0000 -#define BCH_BASE 0xB34D0000 -#define MSC0_BASE 0xB3450000 -#define MSC1_BASE 0xB3460000 -#define MSC2_BASE 0xB3470000 -#define OTG_BASE 0xb3500000 - -/* APB BUS Devices Base */ -#define CPM_BASE 0xB0000000 -#define INTC_BASE 0xB0001000 -#define TCU_BASE 0xB0002000 -#define WDT_BASE 0xB0002000 -#define OST_BASE 0xB2000000 /* OS Timer */ -#define RTC_BASE 0xB0003000 -#define GPIO_BASE 0xB0010000 -#define AIC_BASE 0xB0020000 -#define DMIC_BASE 0xB0021000 -#define ICDC_BASE 0xB0020000 -#define UART0_BASE 0xB0030000 -#define UART1_BASE 0xB0031000 -#define UART2_BASE 0xB0032000 -#define SCC_BASE 0xB0040000 -#define SSI0_BASE 0xB0043000 -#define SSI1_BASE 0xB0044000 -#define SSI2_BASE 0xB0045000 -#define I2C0_BASE 0xB0050000 -#define I2C1_BASE 0xB0051000 -#define I2C2_BASE 0xB0052000 -#define PS2_BASE 0xB0060000 -#define SADC_BASE 0xB0070000 -#define OWI_BASE 0xB0072000 -#define TSSI_BASE 0xB0073000 - -/* NAND CHIP Base Address*/ -#define NEMC_CS1_IOBASE 0Xbb000000 -#define NEMC_CS2_IOBASE 0Xba000000 -#define NEMC_CS3_IOBASE 0Xb9000000 -#define NEMC_CS4_IOBASE 0Xb8000000 -#define NEMC_CS5_IOBASE 0Xb7000000 -#define NEMC_CS6_IOBASE 0Xb6000000 - -/********************************************************************************************************* -** WDT -*********************************************************************************************************/ -#define WDT_TDR (0x00) -#define WDT_TCER (0x04) -#define WDT_TCNT (0x08) -#define WDT_TCSR (0x0C) - -#define REG_WDT_TDR REG16(WDT_BASE + WDT_TDR) -#define REG_WDT_TCER REG8(WDT_BASE + WDT_TCER) -#define REG_WDT_TCNT REG16(WDT_BASE + WDT_TCNT) -#define REG_WDT_TCSR REG16(WDT_BASE + WDT_TCSR) - -#define WDT_TSCR_WDTSC (1 << 16) - -#define WDT_TCSR_PRESCALE_1 (0 << 3) -#define WDT_TCSR_PRESCALE_4 (1 << 3) -#define WDT_TCSR_PRESCALE_16 (2 << 3) -#define WDT_TCSR_PRESCALE_64 (3 << 3) -#define WDT_TCSR_PRESCALE_256 (4 << 3) -#define WDT_TCSR_PRESCALE_1024 (5 << 3) - -#define WDT_TCSR_EXT_EN (1 << 2) -#define WDT_TCSR_RTC_EN (1 << 1) -#define WDT_TCSR_PCK_EN (1 << 0) - -#define WDT_TCER_TCEN (1 << 0) - -/* RTC Reg */ -#define RTC_RTCCR (0x00) /* rw, 32, 0x00000081 */ -#define RTC_RTCSR (0x04) /* rw, 32, 0x???????? */ -#define RTC_RTCSAR (0x08) /* rw, 32, 0x???????? */ -#define RTC_RTCGR (0x0c) /* rw, 32, 0x0??????? */ -#define RTC_HCR (0x20) /* rw, 32, 0x00000000 */ -#define RTC_HWFCR (0x24) /* rw, 32, 0x0000???0 */ -#define RTC_HRCR (0x28) /* rw, 32, 0x00000??0 */ -#define RTC_HWCR (0x2c) /* rw, 32, 0x00000008 */ -#define RTC_HWRSR (0x30) /* rw, 32, 0x00000000 */ -#define RTC_HSPR (0x34) /* rw, 32, 0x???????? */ -#define RTC_WENR (0x3c) /* rw, 32, 0x00000000 */ -#define RTC_CKPCR (0x40) /* rw, 32, 0x00000010 */ -#define RTC_OWIPCR (0x44) /* rw, 32, 0x00000010 */ -#define RTC_PWRONCR (0x48) /* rw, 32, 0x???????? */ - -#define RTCCR_WRDY BIT(7) -#define WENR_WEN BIT(31) - -#define RECOVERY_SIGNATURE (0x001a1a) -#define REBOOT_SIGNATURE (0x003535) -#define UNMSAK_SIGNATURE (0x7c0000)//do not use these bits - - -#include "x1000_cpm.h" -#include "x1000_intc.h" -#include "x1000_otg_dwc.h" -#include "x1000_aic.h" -#include "x1000_slcdc.h" - -#endif /* _JZ_M150_H_ */ diff --git a/libcpu/mips/x1000/x1000_aic.h b/libcpu/mips/x1000/x1000_aic.h deleted file mode 100644 index ed2c8e6f73..0000000000 --- a/libcpu/mips/x1000/x1000_aic.h +++ /dev/null @@ -1,794 +0,0 @@ -/** - ****************************************************************************** - * @file x1000_aic.h - * @author Urey - * @version V1.0.0 - * @date 2017��2��20�� - * @brief TODO - ****************************************************************************** -**/ - - -#ifndef _X1000_AIC_H_ -#define _X1000_AIC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#define AIC_FR (AIC_BASE + 0x00) -#define AIC_CR (AIC_BASE + 0x04) -#define AIC_ACCR1 (AIC_BASE + 0x08) -#define AIC_ACCR2 (AIC_BASE + 0x0c) -#define AIC_I2SCR (AIC_BASE + 0x10) -#define AIC_SR (AIC_BASE + 0x14) -#define AIC_ACSR (AIC_BASE + 0x18) -#define AIC_I2SSR (AIC_BASE + 0x1c) -#define AIC_ACCAR (AIC_BASE + 0x20) -#define AIC_ACCDR (AIC_BASE + 0x24) -#define AIC_ACSAR (AIC_BASE + 0x28) -#define AIC_ACSDR (AIC_BASE + 0x2c) -#define AIC_I2SDIV (AIC_BASE + 0x30) -#define AIC_DR (AIC_BASE + 0x34) - -#define SPDIF_ENA (AIC_BASE + 0x80) -#define SPDIF_CTRL (AIC_BASE + 0x84) -#define SPDIF_STATE (AIC_BASE + 0x88) -#define SPDIF_CFG1 (AIC_BASE + 0x8c) -#define SPDIF_CFG2 (AIC_BASE + 0x90) -#define SPDIF_FIFO (AIC_BASE + 0x94) - -#define ICDC_CKCFG (AIC_BASE + 0xa0) -#define ICDC_RGADW (AIC_BASE + 0xa4) -#define ICDC_RGDATA (AIC_BASE + 0xa8) - - -/* AIC_FR definition */ -#define AIC_FR_RFTH_LSB 24 -#define AIC_FR_RFTH(x) ( ( (x)/2 - 1 ) << AIC_FR_RFTH_LSB) // 2, 4, ..., 32 -#define AIC_FR_RFTH_MASK BITS_H2L(27, AIC_FR_RFTH_LSB) - -#define AIC_FR_TFTH_LSB 16 -#define AIC_FR_TFTH(x) ( ( (x)/2 ) << AIC_FR_TFTH_LSB) // 2, 4, ..., 32 -#define AIC_FR_TFTH_MASK BITS_H2L(20, AIC_FR_TFTH_LSB) - -/* new@4770 */ -#define AIC_FR_IBCKD BIT10 - -/* new@4770 */ -#define AIC_FR_ISYNCD BIT9 - -/* new@4770 */ -#define IC_FR_DMODE BIT8 - -#define AIC_FR_LSMP BIT6 -#define AIC_FR_ICDC BIT5 -#define AIC_FR_AUSEL BIT4 -#define AIC_FR_RST BIT3 -#define AIC_FR_BCKD BIT2 -#define AIC_FR_SYNCD BIT1 -#define AIC_FR_ENB BIT0 - - -/* AIC_CR definition */ -#define AIC_CR_PACK16 BIT28 - -#define AIC_CR_CHANNEL_LSB 24 -#define AIC_CR_CHANNEL_MASK BITS_H2L(26, 24) -#define AIC_CR_CHANNEL_MONO (0x0 << AIC_CR_CHANNEL_LSB) -#define AIC_CR_CHANNEL_STEREO (0x1 << AIC_CR_CHANNEL_LSB) -#define AIC_CR_CHANNEL_4CHNL (0x3 << AIC_CR_CHANNEL_LSB) -#define AIC_CR_CHANNEL_6CHNL (0x5 << AIC_CR_CHANNEL_LSB) -#define AIC_CR_CHANNEL_8CHNL (0x7 << AIC_CR_CHANNEL_LSB) - -#define AIC_CR_OSS_LSB 19 -#define AIC_CR_OSS_MASK BITS_H2L(21, AIC_CR_OSS_LSB) -#define AIC_CR_OSS(n) (((n) > 18 ? (n)/6 : (n)/9) << AIC_CR_OSS_LSB) /* n = 8, 16, 18, 20, 24 */ - -#define AIC_CR_ISS_LSB 16 -#define AIC_CR_ISS_MASK BITS_H2L(18, AIC_CR_ISS_LSB) -#define AIC_CR_ISS(n) (((n) > 18 ? (n)/6 : (n)/9) << AIC_CR_ISS_LSB) /* n = 8, 16, 18, 20, 24 */ - -#define AIC_CR_RDMS BIT15 -#define AIC_CR_TDMS BIT14 -#define AIC_CR_M2S BIT11 -#define AIC_CR_ENDSW BIT10 -#define AIC_CR_AVSTSU BIT9 -#define AIC_CR_TFLUSH BIT8 -#define AIC_CR_RFLUSH BIT7 -#define AIC_CR_EROR BIT6 -#define AIC_CR_ETUR BIT5 -#define AIC_CR_ERFS BIT4 -#define AIC_CR_ETFS BIT3 -#define AIC_CR_ENLBF BIT2 -#define AIC_CR_ERPL BIT1 -#define AIC_CR_EREC BIT0 - -/* AIC controller AC-link control register 1(ACCR1) */ -#define AIC_ACCR1_RS_LSB 16 -#define AIC_ACCR1_RS_MASK BITS_H2L(25, AIC_ACCR1_RS_LSB) -#define AIC_ACCR1_RS_SLOT(n) ((1 << ((n) - 3)) << AIC_ACCR1_RS_LSB) /* n = 3 .. 12 */ - -#define AIC_ACCR1_XS_LSB 0 -#define AIC_ACCR1_XS_MASK BITS_H2L(9, AIC_ACCR1_XS_LSB) -#define AIC_ACCR1_XS_SLOT(n) ((1 << ((n) - 3)) << AIC_ACCR1_XS_LSB) /* n = 3 .. 12 */ - -/* AIC controller AC-link control register 2 (ACCR2) */ -#define AIC_ACCR2_ERSTO BIT18 -#define AIC_ACCR2_ESADR BIT17 -#define AIC_ACCR2_ECADT BIT16 -#define AIC_ACCR2_SO BIT3 -#define AIC_ACCR2_SR BIT2 -#define AIC_ACCR2_SS BIT1 -#define AIC_ACCR2_SA BIT0 - -/* AIC controller i2s/msb-justified control register (I2SCR) */ -#define AIC_I2SCR_RFIRST BIT17 -#define AIC_I2SCR_SWLH BIT16 -#define AIC_I2SCR_ISTPBK BIT13 -#define AIC_I2SCR_STPBK BIT12 -#define AIC_I2SCR_ESCLK BIT4 -#define AIC_I2SCR_AMSL BIT0 - -/* AIC controller FIFO status register (AICSR) */ -#define AIC_SR_RFL_LSB 24 -#define AIC_SR_RFL_MASK BITS_H2L(29, AIC_SR_RFL_LSB) - -#define AIC_SR_TFL_LSB 8 -#define AIC_SR_TFL_MASK BITS_H2L(13, AIC_SR_TFL_LSB) - -#define AIC_SR_ROR BIT6 -#define AIC_SR_TUR BIT5 -#define AIC_SR_RFS BIT4 -#define AIC_SR_TFS BIT3 - -/* AIC controller AC-link status register (ACSR) */ -#define AIC_ACSR_SLTERR BIT21 -#define AIC_ACSR_CRDY BIT20 -#define AIC_ACSR_CLPM BIT19 -#define AIC_ACSR_RSTO BIT18 -#define AIC_ACSR_SADR BIT17 -#define AIC_ACSR_CADT BIT16 - -/* AIC controller I2S/MSB-justified status register (I2SSR) */ -#define AIC_I2SSR_CHBSY BIT5 -#define AIC_I2SSR_TBSY BIT4 -#define AIC_I2SSR_RBSY BIT3 -#define AIC_I2SSR_BSY BIT2 - -/* AIC controller AC97 codec command address register (ACCAR) */ -#define AIC_ACCAR_CAR_LSB 0 -#define AIC_ACCAR_CAR_MASK BITS_H2L(19, AIC_ACCAR_CAR_LSB) - - -/* AIC controller AC97 codec command data register (ACCDR) */ -#define AIC_ACCDR_CDR_LSB 0 -#define AIC_ACCDR_CDR_MASK BITS_H2L(19, AIC_ACCDR_CDR_LSB) - -/* AC97 read and write macro based on ACCAR and ACCDR */ -#define AC97_READ_CMD BIT19 -#define AC97_WRITE_CMD (BIT19 & ~BIT19) - -#define AC97_INDEX_LSB 12 -#define AC97_INDEX_MASK BITS_H2L(18, AC97_INDEX_LSB) - -#define AC97_DATA_LSB 4 -#define AC97_DATA_MASK BITS_H2L(19, AC97_DATA_LSB) - -/* AIC controller AC97 codec status address register (ACSAR) */ -#define AIC_ACSAR_SAR_LSB 0 -#define AIC_ACSAR_SAR_MASK BITS_H2L(19, AIC_ACSAR_SAR_LSB) - -/* AIC controller AC97 codec status data register (ACSDR) */ -#define AIC_ACSDR_SDR_LSB 0 -#define AIC_ACSDR_SDR_MASK BITS_H2L(19, AIC_ACSDR_SDR_LSB) - -/* AIC controller I2S/MSB-justified clock divider register (I2SDIV) */ -#define AIC_I2SDIV_IDIV_LSB 16 -#define AIC_I2SDIV_IDIV_MASK BITS_H2L(24, AIC_I2SDIV_IDIV_LSB) -#define AIC_I2SDIV_DIV_LSB 0 -#define AIC_I2SDIV_DIV_MASK BITS_H2L(8, AIC_I2SDIV_DIV_LSB) - -/* SPDIF enable register (SPDIF_ENA) */ -#define SPDIF_ENA_SPEN BIT0 - -/* SPDIF control register (SPDIF_CTRL) */ -#define SPDIF_CTRL_DMAEN BIT15 -#define SPDIF_CTRL_DTYPE BIT14 -#define SPDIF_CTRL_SIGN BIT13 -#define SPDIF_CTRL_INVALID BIT12 -#define SPDIF_CTRL_RST BIT11 -#define SPDIF_CTRL_SPDIFI2S BIT10 -#define SPDIF_CTRL_MTRIG BIT1 -#define SPDIF_CTRL_MFFUR BIT0 - -/* SPDIF state register (SPDIF_STAT) */ -#define SPDIF_STAT_BUSY BIT7 -#define SPDIF_STAT_FTRIG BIT1 -#define SPDIF_STAT_FUR BIT0 - -#define SPDIF_STAT_FLVL_LSB 8 -#define SPDIF_STAT_FLVL_MASK BITS_H2L(14, SPDIF_STAT_FLVL_LSB) - -/* SPDIF configure 1 register (SPDIF_CFG1) */ -#define SPDIF_CFG1_INITLVL BIT17 -#define SPDIF_CFG1_ZROVLD BIT16 - -#define SPDIF_CFG1_TRIG_LSB 12 -#define SPDIF_CFG1_TRIG_MASK BITS_H2L(13, SPDIF_CFG1_TRIG_LSB) -#define SPDIF_CFG1_TRIG(n) (((n) > 16 ? 3 : (n)/8) << SPDIF_CFG1_TRIG_LSB) /* n = 4, 8, 16, 32 */ - -#define SPDIF_CFG1_SRCNUM_LSB 8 -#define SPDIF_CFG1_SRCNUM_MASK BITS_H2L(11, SPDIF_CFG1_SRCNUM_LSB) - -#define SPDIF_CFG1_CH1NUM_LSB 4 -#define SPDIF_CFG1_CH1NUM_MASK BITS_H2L(7, SPDIF_CFG1_CH1NUM_LSB) - -#define SPDIF_CFG1_CH2NUM_LSB 0 -#define SPDIF_CFG1_CH2NUM_MASK BITS_H2L(3, SPDIF_CFG1_CH2NUM_LSB) - -/* SPDIF configure 2 register (SPDIF_CFG2) */ -#define SPDIF_CFG2_MAXWL BIT18 -#define SPDIF_CFG2_PRE BIT3 -#define SPDIF_CFG2_COPYN BIT2 -#define SPDIF_CFG2_AUDION BIT1 -#define SPDIF_CFG2_CONPRO BIT0 - -#define SPDIF_CFG2_FS_LSB 26 -#define SPDIF_CFG2_FS_MASK BITS_H2L(29, SPDIF_CFG2_FS_LSB) - -#define SPDIF_CFG2_ORGFRQ_LSB 22 -#define SPDIF_CFG2_ORGFRQ_MASK BITS_H2L(25, SPDIF_CFG2_ORGFRQ_LSB) - -#define SPDIF_CFG2_SAMWL_LSB 19 -#define SPDIF_CFG2_SAMWL_MASK BITS_H2L(21, SPDIF_CFG2_SAMWL_LSB) - -#define SPDIF_CFG2_CLKACU_LSB 16 -#define SPDIF_CFG2_CLKACU_MASK BITS_H2L(17, SPDIF_CFG2_CLKACU_LSB) - -#define SPDIF_CFG2_CATCODE_LSB 8 -#define SPDIF_CFG2_CATCODE_MASK BITS_H2L(15, SPDIF_CFG2_CATCODE_LSB) - -#define SPDIF_CFG2_CHMD_LSB 6 -#define SPDIF_CFG2_CHMD_MASK BITS_H2L(7, SPDIF_CFG2_CHMD_LSB) - -/* ICDC internal register access control register(RGADW) */ -#define ICDC_RGADW_RGWR BIT16 - -#define ICDC_RGADW_RGADDR_LSB 8 -#define ICDC_RGADW_RGADDR_MASK BITS_H2L(14, ICDC_RGADW_RGADDR_LSB) - -#define ICDC_RGADW_RGDIN_LSB 0 -#define ICDC_RGADW_RGDIN_MASK BITS_H2L(7, ICDC_RGADW_RGDIN_LSB) - - -/* ICDC internal register data output register (RGDATA)*/ -#define ICDC_RGDATA_IRQ BIT8 - -#define ICDC_RGDATA_RGDOUT_LSB 0 -#define ICDC_RGDATA_RGDOUT_MASK BITS_H2L(7, ICDC_RGDATA_RGDOUT_LSB) - - -#ifndef __MIPS_ASSEMBLER - - -#define REG_AIC_FR REG32(AIC_FR) -#define REG_AIC0_FR REG32(AIC0_FR) -#define REG_AIC_CR REG32(AIC_CR) -#define REG_AIC_ACCR1 REG32(AIC_ACCR1) -#define REG_AIC_ACCR2 REG32(AIC_ACCR2) -#define REG_AIC_I2SCR REG32(AIC_I2SCR) -#define REG_AIC_SR REG32(AIC_SR) -#define REG_AIC_ACSR REG32(AIC_ACSR) -#define REG_AIC_I2SSR REG32(AIC_I2SSR) -#define REG_AIC_ACCAR REG32(AIC_ACCAR) -#define REG_AIC_ACCDR REG32(AIC_ACCDR) -#define REG_AIC_ACSAR REG32(AIC_ACSAR) -#define REG_AIC_ACSDR REG32(AIC_ACSDR) -#define REG_AIC_I2SDIV REG32(AIC_I2SDIV) -#define REG_AIC_DR REG32(AIC_DR) - -#define REG_SPDIF_ENA REG32(SPDIF_ENA) -#define REG_SPDIF_CTRL REG32(SPDIF_CTRL) -#define REG_SPDIF_STATE REG32(SPDIF_STATE) -#define REG_SPDIF_CFG1 REG32(SPDIF_CFG1) -#define REG_SPDIF_CFG2 REG32(SPDIF_CFG2) -#define REG_SPDIF_FIFO REG32(SPDIF_FIFO) - -#define REG_ICDC_RGADW REG32(ICDC_RGADW) -#define REG_ICDC_RGDATA REG32(ICDC_RGDATA) - -#if 0 -#define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB ) -#define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB ) - -#define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL ) -#define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL ) - -#define __aic_play_zero() ( REG_AIC_FR &= ~AIC_FR_LSMP ) -#define __aic_play_lastsample() ( REG_AIC_FR |= AIC_FR_LSMP ) - -#define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD ) -#define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) ) - -#define jz_aic_ibck_in (CLRREG32(AIC_FR, AIC_FR_IBCKD)) -#define jz_aic_ibck_out (SETREG32(AIC_FR, AIC_FR_IBCKD)) - -#define jz_aic_isync_in (CLRREG32(AIC_FR, AIC_FR_ISYNCD)) -#define jz_aic_isync_out (SETREG32(AIC_FR, AIC_FR_ISYNCD)) - -#define jz_aic_enable_dmode (SETREG32(AIC_FR, AIC_FR_DMODE)) -#define jz_aic_disable_dmode (CLRREG32(AIC_FR, AIC_FR_DMODE)) - -#define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST ) - -#define __aic_reset() \ -do { \ - REG_AIC_FR |= AIC_FR_RST; \ -} while(0) - - -#define __aic_set_transmit_trigger(n) \ -do { \ - REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \ - REG_AIC_FR |= ((n) << AIC_FR_TFTH_LSB); \ -} while(0) - -#define __aic_set_receive_trigger(n) \ -do { \ - REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \ - REG_AIC_FR |= ((n) << AIC_FR_RFTH_LSB); \ -} while(0) - -#define __aic_enable_oldstyle() -#define __aic_enable_newstyle() -#define __aic_enable_pack16() ( REG_AIC_CR |= AIC_CR_PACK16 ) -#define __aic_enable_unpack16() ( REG_AIC_CR &= ~AIC_CR_PACK16) - -#define jz_aic_set_channel(n) \ - do { \ - switch((n)) { \ - case 1: \ - case 2: \ - case 4: \ - case 6: \ - case 8: \ - CLRREG32(AIC_CR, AIC_CR_CHANNEL_MASK); \ - SETREG32(AIC_CR, ((((n) - 1) << 24) & AIC_CR_CHANNEL_MASK)); \ - break; \ - default: \ - printk("invalid aic channel, must be 1, 2, 4, 6, or 8\n"); \ - break; \ - } \ - } while(0) - -/* n = AIC_CR_CHANNEL_MONO,AIC_CR_CHANNEL_STEREO ... */ -#define __aic_out_channel_select(n) \ -do { \ - REG_AIC_CR &= ~AIC_CR_CHANNEL_MASK; \ - REG_AIC_CR |= ((n) << AIC_CR_CHANNEL_LSB ); \ -} while(0) - -#define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC ) -#define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC ) -#define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL ) -#define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL ) -#define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF ) -#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF ) - -#define __aic_flush_tfifo() ( REG_AIC_CR |= AIC_CR_TFLUSH ) -#define __aic_unflush_tfifo() ( REG_AIC_CR &= ~AIC_CR_TFLUSH ) -#define __aic_flush_rfifo() ( REG_AIC_CR |= AIC_CR_RFLUSH ) -#define __aic_unflush_rfifo() ( REG_AIC_CR &= ~AIC_CR_RFLUSH ) - -#define __aic_enable_transmit_intr() \ - ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) ) -#define __aic_disable_transmit_intr() \ - ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) ) -#define __aic_enable_receive_intr() \ - ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) ) -#define __aic_disable_receive_intr() \ - ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) ) - -#define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS ) -#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS ) -#define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS ) -#define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS ) - -#define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S ) -#define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S ) -#define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW ) -#define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW ) -#define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU ) -#define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU ) - -#define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT(3) -#define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT(4) -#define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT(6) -#define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT(7) -#define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT(8) -#define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT(9) - -#define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT(3) -#define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT(4) -#define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT(6) -#define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT(7) -#define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT(8) -#define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT(9) - -#define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK ) -#define __ac97_set_xs_mono() \ -do { \ - REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ - REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \ -} while(0) -#define __ac97_set_xs_stereo() \ -do { \ - REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ - REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \ -} while(0) - -/* In fact, only stereo is support now. */ -#define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK ) -#define __ac97_set_rs_mono() \ -do { \ - REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ - REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \ -} while(0) -#define __ac97_set_rs_stereo() \ -do { \ - REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ - REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \ -} while(0) - -#define __ac97_warm_reset_codec() \ - do { \ - REG_AIC_ACCR2 |= AIC_ACCR2_SA; \ - REG_AIC_ACCR2 |= AIC_ACCR2_SS; \ - udelay(2); \ - REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \ - REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \ - } while (0) - -#define __ac97_cold_reset_codec() \ - do { \ - REG_AIC_ACCR2 |= AIC_ACCR2_SR; \ - udelay(2); \ - REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \ - } while (0) - -/* n=8,16,18,20 */ -#define __ac97_set_iass(n) \ - ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT ) -#define __ac97_set_oass(n) \ - ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT ) - -/* This bit should only be set in 2 channels configuration */ -#define __i2s_send_rfirst() ( REG_AIC_I2SCR |= AIC_I2SCR_RFIRST ) /* RL */ -#define __i2s_send_lfirst() ( REG_AIC_I2SCR &= ~AIC_I2SCR_RFIRST ) /* LR */ - -/* This bit should only be set in 2 channels configuration and 16bit-packed mode */ -#define __i2s_switch_lr() ( REG_AIC_I2SCR |= AIC_I2SCR_SWLH ) -#define __i2s_unswitch_lr() ( REG_AIC_I2SCR &= ~AIC_I2SCR_SWLH ) - -#define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL ) -#define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL ) - -/* n=8,16,18,20,24 */ -/*#define __i2s_set_sample_size(n) \ - ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/ - -#define __i2s_out_channel_select(n) __aic_out_channel_select(n) - -#define __i2s_set_oss_sample_size(n) \ - ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS(n)) -#define __i2s_set_iss_sample_size(n) \ - ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS(n)) - -#define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK ) -#define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK ) - -#define __i2s_stop_ibitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_ISTPBK ) -#define __i2s_start_ibitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_ISTPBK ) - -#define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS ) -#define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS ) -#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR ) -#define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR ) - -#define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) ) - -#define __aic_get_transmit_resident() \ - ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_LSB ) -#define __aic_get_receive_count() \ - ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_LSB ) - -#define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT ) -#define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR ) -#define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO ) -#define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM ) -#define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY ) -#define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR ) -#define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR ) - -#define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY ) - -#define __ac97_out_rcmd_addr(reg) \ -do { \ - REG_AIC_ACCAR = AC97_READ_CMD | ((reg) << AC97_INDEX_LSB); \ -} while (0) - -#define __ac97_out_wcmd_addr(reg) \ -do { \ - REG_AIC_ACCAR = AC97_WRITE_CMD | ((reg) << AC97_INDEX_LSB); \ -} while (0) - -#define __ac97_out_data(value) \ -do { \ - REG_AIC_ACCDR = ((value) << AC97_DATA_LSB); \ -} while (0) - -#define __ac97_in_data() \ - ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> AC97_DATA_LSB ) - -#define __ac97_in_status_addr() \ - ( (REG_AIC_ACSAR & AC97_INDEX_MASK) >> AC97_INDEX_LSB ) - -#define __i2s_set_sample_rate(i2sclk, sync) \ - ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) ) - -#define __aic_write_tfifo(v) ( REG_AIC_DR = (v) ) -#define __aic_read_rfifo() ( REG_AIC_DR ) - -#define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC ) -#define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC ) -#define __aic0_internal_codec() ( REG_AIC0_FR |= AIC_FR_ICDC ) -#define __aic0_external_codec() ( REG_AIC0_FR &= ~AIC_FR_ICDC ) - -// -// Define next ops for AC97 compatible -// - -#define AC97_ACSR AIC_ACSR - -#define __ac97_enable() __aic_enable(); __aic_select_ac97() -#define __ac97_disable() __aic_disable() -#define __ac97_reset() __aic_reset() - -#define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n) -#define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n) - -#define __ac97_enable_record() __aic_enable_record() -#define __ac97_disable_record() __aic_disable_record() -#define __ac97_enable_replay() __aic_enable_replay() -#define __ac97_disable_replay() __aic_disable_replay() -#define __ac97_enable_loopback() __aic_enable_loopback() -#define __ac97_disable_loopback() __aic_disable_loopback() - -#define __ac97_enable_transmit_dma() __aic_enable_transmit_dma() -#define __ac97_disable_transmit_dma() __aic_disable_transmit_dma() -#define __ac97_enable_receive_dma() __aic_enable_receive_dma() -#define __ac97_disable_receive_dma() __aic_disable_receive_dma() - -#define __ac97_transmit_request() __aic_transmit_request() -#define __ac97_receive_request() __aic_receive_request() -#define __ac97_transmit_underrun() __aic_transmit_underrun() -#define __ac97_receive_overrun() __aic_receive_overrun() - -#define __ac97_clear_errors() __aic_clear_errors() - -#define __ac97_get_transmit_resident() __aic_get_transmit_resident() -#define __ac97_get_receive_count() __aic_get_receive_count() - -#define __ac97_enable_transmit_intr() __aic_enable_transmit_intr() -#define __ac97_disable_transmit_intr() __aic_disable_transmit_intr() -#define __ac97_enable_receive_intr() __aic_enable_receive_intr() -#define __ac97_disable_receive_intr() __aic_disable_receive_intr() - -#define __ac97_write_tfifo(v) __aic_write_tfifo(v) -#define __ac97_read_rfifo() __aic_read_rfifo() - -// -// Define next ops for I2S compatible -// - -#define I2S_ACSR AIC_I2SSR - -#define __i2s_enable() __aic_enable(); __aic_select_i2s() -#define __i2s_disable() __aic_disable() -#define __i2s_reset() __aic_reset() - -#define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n) -#define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n) - -#define __i2s_enable_record() __aic_enable_record() -#define __i2s_disable_record() __aic_disable_record() -#define __i2s_enable_replay() __aic_enable_replay() -#define __i2s_disable_replay() __aic_disable_replay() -#define __i2s_enable_loopback() __aic_enable_loopback() -#define __i2s_disable_loopback() __aic_disable_loopback() - -#define __i2s_enable_transmit_dma() __aic_enable_transmit_dma() -#define __i2s_disable_transmit_dma() __aic_disable_transmit_dma() -#define __i2s_enable_receive_dma() __aic_enable_receive_dma() -#define __i2s_disable_receive_dma() __aic_disable_receive_dma() - -#define __i2s_transmit_request() __aic_transmit_request() -#define __i2s_receive_request() __aic_receive_request() -#define __i2s_transmit_underrun() __aic_transmit_underrun() -#define __i2s_receive_overrun() __aic_receive_overrun() - -#define __i2s_clear_errors() __aic_clear_errors() - -#define __i2s_get_transmit_resident() __aic_get_transmit_resident() -#define __i2s_get_receive_count() __aic_get_receive_count() - -#define __i2s_enable_transmit_intr() __aic_enable_transmit_intr() -#define __i2s_disable_transmit_intr() __aic_disable_transmit_intr() -#define __i2s_enable_receive_intr() __aic_enable_receive_intr() -#define __i2s_disable_receive_intr() __aic_disable_receive_intr() - -#define __i2s_write_tfifo(v) __aic_write_tfifo(v) -#define __i2s_read_rfifo() __aic_read_rfifo() - -#define __i2s_reset_codec() \ - do { \ - } while (0) - - -/************************************************************************* - * SPDIF INTERFACE in AIC Controller - *************************************************************************/ - -#define __spdif_enable() ( REG_SPDIF_ENA |= SPDIF_ENA_SPEN ) -#define __spdif_disable() ( REG_SPDIF_ENA &= ~SPDIF_ENA_SPEN ) - -#define __spdif_enable_transmit_dma() ( REG_SPDIF_CTRL |= SPDIF_CTRL_DMAEN ) -#define __spdif_disable_transmit_dma() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_DMAEN ) -#define __spdif_enable_dtype() ( REG_SPDIF_CTRL |= SPDIF_CTRL_DTYPE ) -#define __spdif_disable_dtype() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_DTYPE ) -#define __spdif_enable_sign() ( REG_SPDIF_CTRL |= SPDIF_CTRL_SIGN ) -#define __spdif_disable_sign() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_SIGN ) -#define __spdif_enable_invalid() ( REG_SPDIF_CTRL |= SPDIF_CTRL_INVALID ) -#define __spdif_disable_invalid() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_INVALID ) -#define __spdif_enable_reset() ( REG_SPDIF_CTRL |= SPDIF_CTRL_RST ) -#define __spdif_select_spdif() ( REG_SPDIF_CTRL |= SPDIF_CTRL_SPDIFI2S ) -#define __spdif_select_i2s() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_SPDIFI2S ) -#define __spdif_enable_MTRIGmask() ( REG_SPDIF_CTRL |= SPDIF_CTRL_MTRIG ) -#define __spdif_disable_MTRIGmask() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_MTRIG ) -#define __spdif_enable_MFFURmask() ( REG_SPDIF_CTRL |= SPDIF_CTRL_MFFUR ) -#define __spdif_disable_MFFURmask() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_MFFUR ) - -#define __spdif_enable_initlvl_high() ( REG_SPDIF_CFG1 |= SPDIF_CFG1_INITLVL ) -#define __spdif_enable_initlvl_low() ( REG_SPDIF_CFG1 &= ~SPDIF_CFG1_INITLVL ) -#define __spdif_enable_zrovld_invald() ( REG_SPDIF_CFG1 |= SPDIF_CFG1_ZROVLD ) -#define __spdif_enable_zrovld_vald() ( REG_SPDIF_CFG1 &= ~SPDIF_CFG1_ZROVLD ) - -/* 0, 1, 2, 3 */ -#define __spdif_set_transmit_trigger(n) \ -do { \ - REG_SPDIF_CFG1 &= ~SPDIF_CFG1_TRIG_MASK; \ - REG_SPDIF_CFG1 |= SPDIF_CFG1_TRIG(n); \ -} while(0) - -/* 1 ~ 15 */ -#define __spdif_set_srcnum(n) \ -do { \ - REG_SPDIF_CFG1 &= ~SPDIF_CFG1_SRCNUM_MASK; \ - REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_SRCNUM_LSB); \ -} while(0) - -/* 1 ~ 15 */ -#define __spdif_set_ch1num(n) \ -do { \ - REG_SPDIF_CFG1 &= ~SPDIF_CFG1_CH1NUM_MASK; \ - REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH1NUM_LSB); \ -} while(0) - -/* 1 ~ 15 */ -#define __spdif_set_ch2num(n) \ -do { \ - REG_SPDIF_CFG1 &= ~SPDIF_CFG1_CH2NUM_MASK; \ - REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH2NUM_LSB); \ -} while(0) - -/* 0x0, 0x2, 0x3, 0xa, 0xe */ -#define __spdif_set_fs(n) \ -do { \ - REG_SPDIF_CFG2 &= ~SPDIF_CFG2_FS_MASK; \ - REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_FS_LSB); \ -} while(0) - -/* 0xd, 0xc, 0x5, 0x1 */ -#define __spdif_set_orgfrq(n) \ -do { \ - REG_SPDIF_CFG2 &= ~SPDIF_CFG2_ORGFRQ_MASK; \ - REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_ORGFRQ_LSB); \ -} while(0) - -/* 0x1, 0x6, 0x2, 0x4, 0x5 */ -#define __spdif_set_samwl(n) \ -do { \ - REG_SPDIF_CFG2 &= ~SPDIF_CFG2_SAMWL_MASK; \ - REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_SAMWL_LSB); \ -} while(0) - -#define __spdif_enable_samwl_24() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_MAXWL ) -#define __spdif_enable_samwl_20() ( REG_SPDIF_CFG1 &= ~SPDIF_CFG2_MAXWL ) - -/* 0x1, 0x1, 0x2, 0x3 */ -#define __spdif_set_clkacu(n) \ -do { \ - REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CLKACU_MASK; \ - REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CLKACU_LSB); \ -} while(0) - -/* see IEC60958-3 */ -#define __spdif_set_catcode(n) \ -do { \ - REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CATCODE_MASK; \ - REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CATCODE_LSB); \ -} while(0) - -/* n = 0x0, */ -#define __spdif_set_chmode(n) \ -do { \ - REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CHMD_MASK; \ - REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CHMD_LSB); \ -} while(0) - -#define __spdif_enable_pre() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_PRE ) -#define __spdif_disable_pre() ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_PRE ) -#define __spdif_enable_copyn() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_COPYN ) -#define __spdif_disable_copyn() ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_COPYN ) -/* audio sample word represents linear PCM samples */ -#define __spdif_enable_audion() ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_AUDION ) -/* udio sample word used for other purpose */ -#define __spdif_disable_audion() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_AUDION ) -#define __spdif_enable_conpro() ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CONPRO ) -#define __spdif_disable_conpro() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_CONPRO ) - -/*************************************************************************** - * ICDC - ***************************************************************************/ -#define __i2s_internal_codec() __aic_internal_codec() -#define __i2s_external_codec() __aic_external_codec() - -#define __icdc_clk_ready() ( REG_ICDC_CKCFG & ICDC_CKCFG_CKRDY ) -#define __icdc_sel_adc() ( REG_ICDC_CKCFG |= ICDC_CKCFG_SELAD ) -#define __icdc_sel_dac() ( REG_ICDC_CKCFG &= ~ICDC_CKCFG_SELAD ) - -#define __icdc_set_rgwr() ( REG_ICDC_RGADW |= ICDC_RGADW_RGWR ) -#define __icdc_clear_rgwr() ( REG_ICDC_RGADW &= ~ICDC_RGADW_RGWR ) -#define __icdc_rgwr_ready() ( REG_ICDC_RGADW & ICDC_RGADW_RGWR ) - -#define AIC_RW_CODEC_START() while (INREG32(ICDC_RGADW) & ICDC_RGADW_RGWR) -#define AIC_RW_CODEC_STOP() while (INREG32(ICDC_RGADW) & ICDC_RGADW_RGWR) - - -#define __icdc_set_addr(n) \ -do { \ - REG_ICDC_RGADW &= ~ICDC_RGADW_RGADDR_MASK; \ - REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGADDR_LSB; \ -} while(0) - -#define __icdc_set_cmd(n) \ -do { \ - REG_ICDC_RGADW &= ~ICDC_RGADW_RGDIN_MASK; \ - REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGDIN_LSB; \ -} while(0) - -#define __icdc_irq_pending() ( REG_ICDC_RGDATA & ICDC_RGDATA_IRQ ) -#define __icdc_get_value() ( REG_ICDC_RGDATA & ICDC_RGDATA_RGDOUT_MASK ) - - - -#endif /* __MIPS_ASSEMBLER */ - -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* _X1000_AIC_H_ */ diff --git a/libcpu/mips/x1000/x1000_cpm.h b/libcpu/mips/x1000/x1000_cpm.h deleted file mode 100644 index da2cc964e5..0000000000 --- a/libcpu/mips/x1000/x1000_cpm.h +++ /dev/null @@ -1,511 +0,0 @@ -/* - * File : x1000_cpm.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2017-02-03 Urey the first version - */ - -#ifndef _X1000_CPM_H_ -#define _X1000_CPM_H_ - -#define CPM_CPCCR (0x00) -#define CPM_CPCSR (0xd4) - -#define CPM_DDRCDR (0x2c) -#define CPM_I2SCDR (0x60) -#define CPM_I2SCDR1 (0x70) -#define CPM_LPCDR (0x64) -#define CPM_MSC0CDR (0x68) -#define CPM_MSC1CDR (0xa4) -#define CPM_USBCDR (0x50) -#define CPM_MACCDR (0x54) -#define CPM_UHCCDR (0x6c) -#define CPM_SFCCDR (0x74) -#define CPM_CIMCDR (0x7c) -#define CPM_PCMCDR (0x84) -#define CPM_PCMCDR1 (0xe0) -#define CPM_MPHYC (0xe8) - -#define CPM_INTR (0xb0) -#define CPM_INTRE (0xb4) -#define CPM_DRCG (0xd0) -#define CPM_CPSPPR (0x38) -#define CPM_CPPSR (0x34) - -#define CPM_USBPCR (0x3c) -#define CPM_USBRDT (0x40) -#define CPM_USBVBFIL (0x44) -#define CPM_USBPCR1 (0x48) - -#define CPM_CPAPCR (0x10) -#define CPM_CPMPCR (0x14) - -#define CPM_LCR (0x04) -#define CPM_PSWC0ST (0x90) -#define CPM_PSWC1ST (0x94) -#define CPM_PSWC2ST (0x98) -#define CPM_PSWC3ST (0x9c) -#define CPM_CLKGR (0x20) -#define CPM_CLKGR0 (0x20) -#define CPM_MESTSEL (0xec) -#define CPM_SRBC (0xc4) -#define CPM_ERNG (0xd8) -#define CPM_RNG (0xdc) -#define CPM_SLBC (0xc8) -#define CPM_SLPC (0xcc) -#define CPM_OPCR (0x24) -#define CPM_RSR (0x08) - - - - -/* - * CPM registers common define - */ - -/* Clock control register(CPCCR) */ -#define CPCCR_SEL_SRC_LSB 30 -#define CPCCR_SEL_SRC_MASK BITS_H2L(31, CPCCR_SEL_SRC_LSB) - -#define CPCCR_SEL_CPLL_LSB 28 -#define CPCCR_SEL_CPLL_MASK BITS_H2L(29, CPCCR_SEL_CPLL_LSB) - -#define CPCCR_SEL_H0PLL_LSB 26 -#define CPCCR_SEL_H0PLL_MASK BITS_H2L(27, CPCCR_SEL_H0PLL_LSB) - -#define CPCCR_SEL_H2PLL_LSB 24 -#define CPCCR_SEL_H2PLL_MASK BITS_H2L(25, CPCCR_SEL_H2PLL_LSB) - -#define CPCCR_CE_CPU BIT22 -#define CPCCR_CE_AHB0 BIT21 -#define CPCCR_CE_AHB2 BIT20 -#define CPCCR_CE (CPCCR_CE_CPU | CPCCR_CE_AHB0 | CPCCR_CE_AHB2) - -#define CPCCR_PDIV_LSB 16 -#define CPCCR_PDIV_MASK BITS_H2L(19, CPCCR_PDIV_LSB) - -#define CPCCR_H2DIV_LSB 12 -#define CPCCR_H2DIV_MASK BITS_H2L(15, CPCCR_H2DIV_LSB) - -#define CPCCR_H0DIV_LSB 8 -#define CPCCR_H0DIV_MASK BITS_H2L(11, CPCCR_H0DIV_LSB) - -#define CPCCR_L2DIV_LSB 4 -#define CPCCR_L2DIV_MASK BITS_H2L(7, CPCCR_L2DIV_LSB) - -#define CPCCR_CDIV_LSB 0 -#define CPCCR_CDIV_MASK BITS_H2L(3, CPCCR_CDIV_LSB) - -#define CPM_SRC_SEL_APLL 1 -#define CPM_PLL_SEL_SRC 1 -#define CPM_PLL_SEL_MPLL 2 - -/* Clock Status register(CPCSR) */ -#define CPCSR_SRC_MUX BIT31 -#define CPCSR_CPU_MUX BIT30 -#define CPCSR_AHB0_MUX BIT29 -#define CPCSR_AHB2_MUX BIT28 -#define CPCSR_DDR_MUX BIT27 -#define CPCSR_H2DIV_BUSY BIT2 -#define CPCSR_H0DIV_BUSY BIT1 -#define CPCSR_CDIV_BUSY BIT0 -#define CPCSR_DIV_BUSY (CPCSR_H2DIV_BUSY | CPCSR_H0DIV_BUSY | CPCSR_CDIV_BUSY) - -/* DDR clock divider register(DDCDR) */ -#define DDCDR_DCS_LSB 30 -#define DDCDR_DCS_MASK BITS_H2L(31, DDCDR_DCS_LSB) -#define DDCDR_DCS_STOP (0 << DDCDR_DCS_LSB) -#define DDCDR_DCS_APLL (1 << DDCDR_DCS_LSB) -#define DDCDR_DCS_MPLL (2 << DDCDR_DCS_LSB) -#define DDCDR_CE_DDR BIT29 -#define DDCDR_DDR_BUSY BIT28 -#define DDCDR_DDR_STOP BIT27 -#define DDCDR_GATE_EN BIT26 -#define DDCDR_DDR_CHANGE_EN BIT25 -#define DDCDR_DDR BIT24 -#define DDCDR_DDRDIV_LSB 0 -#define DDCDR_DDRDIV_MASK BITS_H2L(3, DDCDR_DDRDIV_LSB) - -/*MACPHY clock divider Register (MACCDR)*/ -#define MACCDR_MACPCS BIT31 -#define MACCDR_CE_MAC BIT29 -#define MACCDR_MAC_BUSY BIT28 -#define MACCDR_MAC_STOP BIT27 -#define MACCDR_MACCDR_LSB BIT0 -#define MACCDR_MACCDR_MASK BITS_H2L(7,MACCDR_MACCDR_LSB) - -/* I2S device clock divider register(I2SCDR) */ -#define I2SCDR_I2PCS BIT31 -#define I2SCDR_I2CS BIT30 - -#define I2SCDR_I2SDIV_M_LSB 13 -#define I2SCDR_I2SDIV_M_MASK BITS_H2L(21,I2SCDR_I2SDIV_M_LSB) -#define I2SCDR_I2SDIV_N_LSB 0 /* I2SCDR bit */ -#define I2SCDR_I2SDIV_N_MASK BITS_H2L(7, I2SCDR_I2SDIV_N_LSB) - - -/* I2S device clock divider register(I2SCDR1) */ -#define I2SCDR1_NEN BIT31 -#define I2SCDR1_DEN BIT30 -#define I2SCDR1_I2SDIV_D_LSB 0 -#define I2SCDR1_I2SDIV_D_MASK BITS_H2L(12,I2SCDR1_I2SDIV_D_LSB) - -/* LCD pix clock divider register(LPCDR) */ -#define LPCDR_LPCS_LSB 31 -#define LPCDR_LPCS_APLL (0 << LPCDR_LPCS_LSB) -#define LPCDR_LPCS_MPLL (1 << LPCDR_LPCS_LSB) -#define LPCDR_CE_LCD BIT28 -#define LPCDR_LCD_BUSY BIT27 -#define LPCDR_LCD_STOP BIT26 - -#define LPCDR_PIXDIV_LSB 0 /* LPCDR bit */ -#define LPCDR_PIXDIV_MASK BITS_H2L(7, LPCDR_PIXDIV_LSB) - -/* MSC clock divider register(MSCCDR) */ -#define MSCCDR_MPCS_LSB 31 /* MPCS bit */ -#define MSCCDR_MPCS_APLL (0 << MSCCDR_MPCS_LSB) -#define MSCCDR_MPCS_MPLL (1 << MSCCDR_MPCS_LSB) - -#define MSCCDR_CE_MSC BIT29 -#define MSCCDR_MSC_BUSY BIT28 -#define MSCCDR_MSC_STOP BIT27 -#define MSCCDR_S_CLK0_SEL BIT15 - -#define MSCCDR_MSCDIV_LSB 0 /* MSCCDR bit */ -#define MSCCDR_MSCDIV_MASK BITS_H2L(7, MSCCDR_MSCDIV_LSB) - - -/* OTG PHY clock divider register(USBCDR) */ -#define USBCDR_UCS BIT31 -#define USBCDR_UPCS BIT30 -#define USBCDR_CE_USB BIT29 -#define USBCDR_USB_BUSY BIT28 -#define USBCDR_USB_STOP BIT27 - -#define USBCDR_OTGDIV_LSB 0 /* USBCDR bit */ -#define USBCDR_OTGDIV_MASK BITS_H2L(7, USBCDR_OTGDIV_LSB) - -/* SSI clock divider register(SSICDR) */ -#define SSICDR_SPCS BIT31 -#define SSICDR_SCS BIT30 -#define SSICDR_CE_SSI BIT29 -#define SSICDR_SSI_BUSY BIT28 -#define SSICDR_SSI_STOP BIT27 -#define SSICDR_SSIDIV_LSB 0 /* SSICDR bit */ -#define SSICDR_SSIDIV_MASK BITS_H2L(7, SSICDR_SSIDIV_LSB) - -/* CIM mclk clock divider register(CIMCDR) */ -#define CIMCDR_CIMPCS_APLL (0 << 31) -#define CIMCDR_CIMPCS_MPLL BIT31 -#define CIMCDR_CE_CIM BIT29 -#define CIMCDR_CIM_BUSY BIT28 -#define CIMCDR_CIM_STOP BIT27 - -#define CIMCDR_CIMDIV_LSB 0 /* CIMCDR bit */ -#define CIMCDR_CIMDIV_MASK BITS_H2L(7, CIMCDR_CIMDIV_LSB) - - -/* PCM device clock divider register(PCMCDR) */ -#define PCMCDR_PCMPCS_LSB 30 -#define PCMCDR_PCMPCS_MASK BITS_H2L(31,PCMCDR_PCMPCS_LSB) -#define PCMCDR_PCMPCS_SCLK_A 0 << PCMCDR_PCMPCS_LSB -#define PCMCDR_PCMPCS_EXTCLK 1 << PCMCDR_PCMPCS_LSB -#define PCMCDR_PCMPCS_MPLL 2 << PCMCDR_PCMPCS_LSB -#define PCMCDR_CE_PCM BIT29 -#define PCMCDR_PCMDIV_M_LSB 13 -#define PCMCDR_PCMDIV_M_MASK BITS_H2L(21,PCMCDR_PCMDIV_M_LSB) -#define PCMCDR_PCMDIV_N_LSB 0 -#define PCMCDR_PCMDIV_N_MASK BITS_H2L(12,PCMCDR_PCMDIV_N_LSB) - -/* PCM device clock divider register(PCMCDR1) */ - -#define PCMCDR1_PCM_NEN BIT31 -#define PCMCDR1_PCM_DEN BIT30 -#define PCMCDR1_PCMDIV_D_LSB 0 -#define PCMCDR1_PCMDIV_D_MASK BITS_H2L(12,PCMCDR1_PCMDIV_D_LSB) - -/* MAC PHY Control Register (MPHYC) */ -#define MPHYC_MODE_SEL BIT31 //useless now -#define MPHYC_MAC_SPEED_LSB 29 -#define MPHYC_MAC_SPEED_MASK BITS_H2L(30,MPHYC_MAC_SPEED_LSB) -#define MPHYC_SOFT_RST BIT3 -#define MPHYC_PHY_INTF_LSB 0 -#define MPHYC_PHY_INTF_MASK BITS_H2L(2,MPHYC_PHY_INTF_MASK) //useless now - -/* CPM Interrupt Register (CPM_INTR)*/ -#define CPM_INTR_VBUS_INTR BIT1 -#define CPM_INTR_ADEV_INTR BIT0 - -/* CPM Interrupt Enable Register (CPM_INTRE)*/ -#define CPM_INTRE_VBUS_INTRE BIT1 -#define CPM_INTRE_ADEV_INTRE BIT0 - -/* CPM scratch pad protected register(CPSPPR) */ -#define CPSPPR_CPSPR_WRITABLE (0x00005a5a) - -/* OTG parameter control register(USBPCR) */ -#define USBPCR_USB_MODE BIT31 -#define USBPCR_AVLD_REG BIT30 -#define USBPCR_INCRM BIT27 /* INCR_MASK bit */ -#define USBPCR_TXRISE_TUNE BIT26 -#define USBPCR_COMMONONN BIT25 -#define USBPCR_VBUSVLDEXT BIT24 -#define USBPCR_VBUSVLDEXTSEL BIT23 -#define USBPCR_POR BIT22 -#define USBPCR_SIDDQ BIT21 -#define USBPCR_OTG_DISABLE BIT20 -#define USBPCR_TXPREEMPHTUNE BIT6 - -#define USBPCR_IDPULLUP_LSB 28 /* IDPULLUP_MASK bit */ -#define USBPCR_IDPULLUP_MASK BITS_H2L(29, USBPCR_IDPULLUP_LSB) - -#define USBPCR_COMPDISTUNE_LSB 17 -#define USBPCR_COMPDISTUNE_MASK BITS_H2L(19, USBPCR_COMPDISTUNE_LSB) - -#define USBPCR_OTGTUNE_LSB 14 -#define USBPCR_OTGTUNE_MASK BITS_H2L(16, USBPCR_OTGTUNE_LSB) - -#define USBPCR_SQRXTUNE_LSB 11 -#define USBPCR_SQRXTUNE_MASK BITS_H2L(13, USBPCR_SQRXTUNE_LSB) - -#define USBPCR_TXFSLSTUNE_LSB 7 -#define USBPCR_TXFSLSTUNE_MASK BITS_H2L(10, USBPCR_TXFSLSTUNE_LSB) - -#define USBPCR_TXRISETUNE_LSB 4 -#define USBPCR_TXRISETUNE_MASK BITS_H2L(5, USBPCR_TXRISETUNE_LSB) - -#define USBPCR_TXVREFTUNE_LSB 0 -#define USBPCR_TXVREFTUNE_MASK BITS_H2L(3, USBPCR_TXVREFTUNE_LSB) - -/* OTG reset detect timer register(USBRDT) */ -#define USBRDT_HB_MASK BIT26 -#define USBRDT_VBFIL_LD_EN BIT25 -#define USBRDT_IDDIG_EN BIT24 -#define USBRDT_IDDIG_REG BIT23 - -#define USBRDT_USBRDT_LSB 0 -#define USBRDT_USBRDT_MASK BITS_H2L(22, USBRDT_USBRDT_LSB) - -/* OTG parameter control register(USBPCR1) */ -#define USBPCR1_REG BIT31 -#define USBPCR1_USB_SEL BIT28 -#define USBPCR1_REFCLKSEL_LSB 26 -#define USBPCR1_REFCLKSEL_MASK BITS_H2L(27, USBPCR1_REFCLKSEL_LSB) - -#define USBPCR1_REFCLKDIV_LSB 24 -#define USBPCR1_REFCLKDIV_MASK BITS_H2L(25, USBPCR1_REFCLKDIV_LSB) - -#define USBPCR1_PORT_RST BIT21 - -#define USBPCR1_WORD_IF0 BIT19 -#define USBPCR1_WORD_IF1 BIT18 - - -/* APLL control register (CPXPCR) */ -#define CPAPCR_BS BIT31 -#define CPAPCR_M_LSB 24 -#define CPAPCR_M_MASK BITS_H2L(30, CPAPCR_M_LSB) - -#define CPAPCR_N_LSB 18 -#define CPAPCR_N_MASK BITS_H2L(22, CPAPCR_N_LSB) - -#define CPAPCR_OD_LSB 16 -#define CPAPCR_OD_MASK BITS_H2L(17, CPAPCR_OD_LSB) - -#define CPAPCR_LOCK BIT15 /* LOCK bit */ -#define CPAPCR_ON BIT10 -#define CPAPCR_BP BIT9 -#define CPAPCR_EN BIT8 -#define CPAPCR_PLLST_LSB 0 -#define CPAPCR_PLLST_MASK BITS_H2L(7,CPAPCR_PLLST_LSB) - -#define CPM_CPAPCR_EN CPAPCR_EN -#define CPM_CPAPCR_ON CPAPCR_ON - -/* MPLL control register (CPXPCR) */ -#define CPMPCR_BS BIT31 -#define CPMPCR_M_LSB 24 -#define CPMPCR_M_MASK BITS_H2L(30, CPAPCR_M_LSB) - -#define CPMPCR_N_LSB 18 -#define CPMPCR_N_MASK BITS_H2L(22, CPAPCR_N_LSB) - -#define CPMPCR_OD_LSB 16 -#define CPMPCR_OD_MASK BITS_H2L(17, CPAPCR_OD_LSB) - -#define CPMPCR_EN BIT7 -#define CPMPCR_BP BIT6 -#define CPMPCR_LOCK BIT1 /* LOCK bit */ -#define CPMPCR_ON BIT0 - -#define CPM_CPMPCR_EN CPMPCR_EN -#define CPM_CPMPCR_ON CPMPCR_ON - - - -/* Low power control register(LCR) */ -#define LCR_PST_LSB 8 -#define LCD_PST_MASK BITS_H2L(19,LCR_PST_LSB) -#define LCR_LPM_LSB 0 -#define LCR_LPM_MASK BITS_H2L(1,LCR_LPM_LSB) - -/* Clock gate register 0(CGR0) */ -#define CLKGR0_DDR BIT31 -#define CLKGR0_CPU BIT30 -#define CLKGR0_AHB0 BIT29 -#define CLKGR0_APB0 BIT28 -#define CLKGR0_RTC BIT27 -#define CLKGR0_PCM BIT26 -#define CLKGR0_MAC BIT25 -#define CLKGR0_AES BIT24 -#define CLKGR0_LCD BIT23 -#define CLKGR0_CIM BIT22 -#define CLKGR0_PDMA BIT21 -#define CLKGR0_OST BIT20 -#define CLKGR0_SSI BIT19 -#define CLKGR0_TCU BIT18 -#define CLKGR0_DMIC BIT17 -#define CLKGR0_UART2 BIT16 -#define CLKGR0_UART1 BIT15 -#define CLKGR0_UART0 BIT14 -#define CLKGR0_SADC BIT13 -#define CLKGR0_JPEG BIT12 -#define CLKGR0_AIC BIT11 -#define CLKGR0_I2C3 BIT10 -#define CLKGR0_I2C2 BIT9 -#define CLKGR0_I2C1 BIT8 -#define CLKGR0_I2C0 BIT7 -#define CLKGR0_SCC BIT6 -#define CLKGR0_MSC1 BIT5 -#define CLKGR0_MSC0 BIT4 -#define CLKGR0_OTG BIT3 -#define CLKGR0_SFC BIT2 -#define CLKGR0_EFUSE BIT1 -#define CLKGR0_NEMC BIT0 - -/* CPM MEST SEL Register */ - -#define MEST_SEL_TST8 BIT8 -#define MEST_SEL_TST7 BIT7 -#define MEST_SEL_TST4 BIT4 -#define MEST_SEL_TST3 BIT3 -#define MEST_SEL_TST1 BIT1 -#define MEST_SEL_TST0 BIT0 - -/*Soft Reset and Bus Control Register (SRBC)*/ - -#define SRBC_JPEG_SR BIT31 -#define SRBC_JPEG_STP BIT30 -#define SRBC_JPEG_ACK BIT29 -#define SRBC_LCD_SR BIT25 -#define SRBC_LCD_STP BIT24 -#define SRBC_LCD_ACK BIT23 -#define SRBC_CIM_STP BIT21 -#define SRBC_CIM_ACK BIT20 -#define SRBC_CPU_STP BIT15 -#define SRBC_CPU_ACK BIT14 -#define SRBC_OTG_SR BIT12 -#define SRBC_AHB2_STP BIT8 -#define SRBC_AHB2_ACK BIT7 -#define SRBC_DDR_STP BIT6 -#define SRBC_DDR_ACK BIT5 - - -/* Oscillator and power control register(OPCR) */ -#define OPCR_IDLE_DIS BIT31 -#define OPCR_MASK_INT BIT30 -#define OPCR_MASK_VPU BIT29 //ONLY FOR DEBUG -#define OPCR_GATE_SCLK_ABUS BIT28 -#define OPCR_L2C_PD BIT25 -#define OPCR_REQ_MODE BIT24 -#define OPCR_GATE_USBPHY_CLK BIT23 -#define OPCR_DIS_STOP_MUX BIT22 -#define OPCR_O1ST_LSB 8 -#define OPCR_O1ST_MASK BITS_H2L(19, OPCR_O1ST_LSB) -#define OPCR_OTGPHY0_ENABLE BIT7 /* otg */ -#define OPCR_OTGPHY1_ENABLE BIT6 /* uhc */ -#define OPCR_USBPHY_ENABLE (OPCR_OTGPHY0_ENABLE | OPCR_OTGPHY1_ENABLE) -#define OPCR_O1SE BIT4 -#define OPCR_PD BIT3 -#define OPCR_ERCS BIT2 -#define OPCR_BUSMODE BIT1 - - - -/* Reset status register(RSR) */ -#define RSR_HR BIT3 -#define RSR_P0R BIT2 -#define RSR_WR BIT1 -#define RSR_PR BIT0 - - -#ifndef __ASSEMBLY__ - -#define REG_CPM_CPCCR REG32(CPM_BASE + CPM_CPCCR) -#define REG_CPM_CPCSR REG32(CPM_BASE + CPM_CPCSR) -#define REG_CPM_DDCDR REG32(CPM_BASE + CPM_DDCDR) -#define REG_CPM_MACCDR REG32(CPM_BASE + CPM_MACCDR) -#define REG_CPM_I2SCDR REG32(CPM_BASE + CPM_I2SCDR) -#define REG_CPM_I2SCDR1 REG32(CPM_BASE + CPM_I2SCDR1) -#define REG_CPM_LPCDR REG32(CPM_BASE + CPM_LPCDR) -#define REG_CPM_MSC0CDR REG32(CPM_BASE + CPM_MSC0CDR) -#define REG_CPM_MSC1CDR REG32(CPM_BASE + CPM_MSC1CDR) -#define REG_CPM_USBCDR REG32(CPM_BASE + CPM_USBCDR) -#define REG_CPM_SSICDR REG32(CPM_BASE + CPM_SSICDR) -#define REG_CPM_CIMCDR REG32(CPM_BASE + CPM_CIMCDR) -#define REG_CPM_PCMCDR REG32(CPM_BASE + CPM_PCMCDR) -#define REG_CPM_PCMCDR1 REG32(CPM_BASE + CPM_PCMCDR1) -#define REG_CPM_MPHYC REG32(CPM_BASE + CPM_MPHYC) -#define REG_CPM_INTRCDR REG32(CPM_BASE + CPM_INTRCDR) -#define REG_CPM_INTRECDR REG32(CPM_BASE + CPM_INTRECDR) -#define REG_CPM_CPSPR REG32(CPM_BASE + CPM_CPSPR) -#define REG_CPM_CPSPPR REG32(CPM_BASE + CPM_CPSPPR) -#define REG_CPM_USBPCR REG32(CPM_BASE + CPM_USBPCR) -#define REG_CPM_USBRDT REG32(CPM_BASE + CPM_USBRDT) -#define REG_CPM_USBVBFIL REG32(CPM_BASE + CPM_USBVBFIL) -#define REG_CPM_USBPCR1 REG32(CPM_BASE + CPM_USBPCR1) -#define REG_CPM_CPAPCR REG32(CPM_BASE + CPM_CPAPCR) -#define REG_CPM_CPMPCR REG32(CPM_BASE + CPM_CPMPCR) - -#define REG_CPM_LCR REG32(CPM_BASE + CPM_LCR) -#define REG_CPM_PSWC0ST REG32(CPM_BASE + CPM_PSWC0ST) -#define REG_CPM_PSWC1ST REG32(CPM_BASE + CPM_PSWC1ST) -#define REG_CPM_PSWC2ST REG32(CPM_BASE + CPM_PSWC2ST) -#define REG_CPM_PSWC3ST REG32(CPM_BASE + CPM_PSWC3ST) -#define REG_CPM_CLKGR0 REG32(CPM_BASE + CPM_CLKGR0) -#define REG_CPM_SRBC REG32(CPM_BASE + CPM_SRBC) -#define REG_CPM_SLBC REG32(CPM_BASE + CPM_SLBC) -#define REG_CPM_SLPC REG32(CPM_BASE + CPM_SLPC) -#define REG_CPM_OPCR REG32(CPM_BASE + CPM_OPCR) -#define REG_CPM_RSR REG32(CPM_BASE + CPM_RSR) - -#define _REG_CPM_MSCCDR(n) REG_CPM_MSC##n##CDR -#define REG_CPM_MSCCDR(n) _REG_CPM_MSCCDR(n) - -/* CPM read write */ -#define cpm_inl(off) readl(CPM_BASE + off) -#define cpm_outl(val,off) writel(val, CPM_BASE + off) -#define cpm_test_bit(bit,off) (cpm_inl(off) & 0x1<<(bit)) -#define cpm_set_bit(bit,off) (cpm_outl((cpm_inl(off) | 0x1<<(bit)),off)) -#define cpm_clear_bit(bit,off) (cpm_outl(cpm_inl(off) & ~(0x1 << bit), off)) - -#endif /* __ASSEMBLY__ */ - -#endif /* _X1000_CPM_H_ */ diff --git a/libcpu/mips/x1000/x1000_intc.h b/libcpu/mips/x1000/x1000_intc.h deleted file mode 100644 index 1644b90777..0000000000 --- a/libcpu/mips/x1000/x1000_intc.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * File : x1000_intc.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2017-02-03 Urey the first version - */ - -#ifndef _X1000_INTC_H_ -#define _X1000_INTC_H_ - - -/* - * INTC (Interrupt Controller) - */ -#define INTC_ISR(n) (INTC_BASE + 0x00 + (n) * 0x20) -#define INTC_IMR(n) (INTC_BASE + 0x04 + (n) * 0x20) -#define INTC_IMSR(n) (INTC_BASE + 0x08 + (n) * 0x20) -#define INTC_IMCR(n) (INTC_BASE + 0x0c + (n) * 0x20) -#define INTC_IPR(n) (INTC_BASE + 0x10 + (n) * 0x20) - -#define REG_INTC_ISR(n) REG32(INTC_ISR((n))) -#define REG_INTC_IMR(n) REG32(INTC_IMR((n))) -#define REG_INTC_IMSR(n) REG32(INTC_IMSR((n))) -#define REG_INTC_IMCR(n) REG32(INTC_IMCR((n))) -#define REG_INTC_IPR(n) REG32(INTC_IPR((n))) - -// interrupt controller interrupts -#define IRQ_DMIC 0 -#define IRQ_AIC0 1 -#define IRQ_RESERVED2 2 -#define IRQ_RESERVED3 3 -#define IRQ_RESERVED4 4 -#define IRQ_RESERVED5 5 -#define IRQ_RESERVED6 6 -#define IRQ_SFC 7 -#define IRQ_SSI0 8 -#define IRQ_RESERVED9 9 -#define IRQ_PDMA 10 -#define IRQ_PDMAD 11 -#define IRQ_RESERVED12 12 -#define IRQ_RESERVED13 13 -#define IRQ_GPIO3 14 -#define IRQ_GPIO2 15 -#define IRQ_GPIO1 16 -#define IRQ_GPIO0 17 -#define IRQ_RESERVED18 18 -#define IRQ_RESERVED19 19 -#define IRQ_RESERVED20 20 -#define IRQ_OTG 21 -#define IRQ_RESERVED22 22 -#define IRQ_AES 23 -#define IRQ_RESERVED24 24 -#define IRQ_TCU2 25 -#define IRQ_TCU1 26 -#define IRQ_TCU0 27 -#define IRQ_RESERVED28 28 -#define IRQ_RESERVED29 29 -#define IRQ_CIM 30 -#define IRQ_LCD 31 -#define IRQ_RTC 32 -#define IRQ_RESERVED33 33 -#define IRQ_RESERVED34 34 -#define IRQ_RESERVED35 35 -#define IRQ_MSC1 36 -#define IRQ_MSC0 37 -#define IRQ_SCC 38 -#define IRQ_RESERVED39 39 -#define IRQ_PCM0 40 -#define IRQ_RESERVED41 41 -#define IRQ_RESERVED42 42 -#define IRQ_RESERVED43 43 -#define IRQ_HARB2 44 -#define IRQ_RESERVED45 45 -#define IRQ_HARB0 46 -#define IRQ_CPM 47 -#define IRQ_RESERVED48 48 -#define IRQ_UART2 49 -#define IRQ_UART1 50 -#define IRQ_UART0 51 -#define IRQ_DDR 52 -#define IRQ_RESERVED53 53 -#define IRQ_EFUSE 54 -#define IRQ_MAC 55 -#define IRQ_RESERVED56 56 -#define IRQ_RESERVED57 57 -#define IRQ_I2C2 58 -#define IRQ_I2C1 59 -#define IRQ_I2C0 60 -#define IRQ_PDMAM 61 -#define IRQ_JPEG 62 -#define IRQ_RESERVED63 63 - -#define IRQ_INTC_MAX 63 - -#ifndef __ASSEMBLY__ - -#define __intc_unmask_irq(n) (REG_INTC_IMCR((n)/32) = (1 << ((n)%32))) -#define __intc_mask_irq(n) (REG_INTC_IMSR((n)/32) = (1 << ((n)%32))) -#define __intc_ack_irq(n) (REG_INTC_IPR((n)/32) = (1 << ((n)%32))) /* A dummy ack, as the Pending Register is Read Only. Should we remove __intc_ack_irq() */ - -#endif /* !__ASSEMBLY__ */ - -#endif /* _X1000_INTC_H_ */ diff --git a/libcpu/mips/x1000/x1000_otg_dwc.h b/libcpu/mips/x1000/x1000_otg_dwc.h deleted file mode 100644 index bb77981daa..0000000000 --- a/libcpu/mips/x1000/x1000_otg_dwc.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * File : x1000_otg_dwc.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2017-02-03 Urey the first version - */ - -#ifndef _X1000_OTG_DWC_H_ -#define _X1000_OTG_DWC_H_ - -/* Globle Regs define */ -#define GOTG_CTL (OTG_BASE + 0x00) -#define GOTG_INTR (OTG_BASE + 0x04) -#define GAHB_CFG (OTG_BASE + 0x08) -#define GUSB_CFG (OTG_BASE + 0x0c) -#define GRST_CTL (OTG_BASE + 0x10) -#define GINT_STS (OTG_BASE + 0x14) -#define GINT_MASK (OTG_BASE + 0x18) -#define GRXSTS_READ (OTG_BASE + 0x1c) -#define GRXSTS_POP (OTG_BASE + 0x20) -#define GRXFIFO_SIZE (OTG_BASE + 0x24) -#define GNPTXFIFO_SIZE (OTG_BASE + 0x28) -#define GDTXFIFO_SIZE (OTG_BASE + 0x104) -#define GHW_CFG1 (OTG_BASE + 0x44) -#define GHW_CFG2 (OTG_BASE + 0x48) -#define GHW_CFG3 (OTG_BASE + 0x4c) -#define GHW_CFG4 (OTG_BASE + 0x50) -#define GDFIFO_CFG (OTG_BASE + 0x5c) -#define PCGC_CTL (OTG_BASE + 0xe00) - -/* Fifo number 1 ~ 15 */ -#define GDEIP_TXF(n) (OTG_BASE + (0x104 + ((n-1) * 0x4))) - -#define REG_GOTG_CTL REG32(GOTG_CTL) -#define REG_GOTG_INTR REG32(GOTG_INTR) -#define REG_GAHB_CFG REG32(GAHB_CFG) -#define REG_GUSB_CFG REG32(GUSB_CFG) -#define REG_GRST_CTL REG32(GRST_CTL) -#define REG_GINT_STS REG32(GINT_STS) -#define REG_GINT_MASK REG32(GINT_MASK) -#define REG_GRXSTS_READ REG32(GRXSTS_READ) -#define REG_GRXSTS_POP REG32(GRXSTS_POP) -#define REG_GRXFIFO_SIZE REG32(GRXFIFO_SIZE) -#define REG_GNPTXFIFO_SIZE REG32(GNPTXFIFO_SIZE) -#define REG_GDTXFIFO_SIZE REG32(GDTXFIFO_SIZE) -#define REG_GHW_CFG1 REG32(GHW_CFG1) -#define REG_GHW_CFG2 REG32(GHW_CFG2) -#define REG_GHW_CFG3 REG32(GHW_CFG3) -#define REG_GHW_CFG4 REG32(GHW_CFG4) -#define REG_GDFIFO_CFG REG32(GDFIFO_CFG) -#define REG_GDIEP_TXF(n) REG32(GDEIP_TXF(n)) -#define REG_PCGC_CTL REG32(PCGC_CTL) -/* Device Regs define */ -#define EP_FIFO(n) (OTG_BASE + (n+1)*0x1000) // FiX ME -#define REG_EP_FIFO(n) REG32(EP_FIFO(n)) - - -#define OTG_DCFG (OTG_BASE + 0x800) -#define OTG_DCTL (OTG_BASE + 0x804) -#define OTG_DSTS (OTG_BASE + 0x808) -#define DIEP_MASK (OTG_BASE + 0x810) -#define DOEP_MASK (OTG_BASE + 0x814) -#define OTG_DAINT (OTG_BASE + 0x818) -#define DAINT_MASK (OTG_BASE + 0x81c) - -#define DIEP_EMPMSK (OTG_BASE + 0x834) - - -/* It's used in OTG_MULT_PROC_INTRPT = 1 -#define DEACH_INT (OTG_BASE + 0x838) -#define DEACH_INTMASK (OTG_BASE + 0x83c) -#define DIEP0_INTMASK (OTG_BASE + 0x840) -#define DIEP1_INTMASK (OTG_BASE + 0x844) -#define DOEP0_INTMASK (OTG_BASE + 0x880) -#define DOEP1_INTMASK (OTG_BASE + 0x884) -*/ - -#define DIEP_CTL(n) (OTG_BASE + (0x900 + (n)*0x20)) -#define DOEP_CTL(n) (OTG_BASE + (0xb00 + (n)*0x20)) - -#define DIEP_INT(n) (OTG_BASE + (0x908 + (n)*0x20)) -#define DOEP_INT(n) (OTG_BASE + (0xb08 + (n)*0x20)) - -#define DIEP_SIZE(n) (OTG_BASE + (0x910 + (n)*0x20)) -#define DOEP_SIZE(n) (OTG_BASE + (0xb10 + (n)*0x20)) - -#define DIEP_TXFSTS(n) (OTG_BASE + (0x918 + (n)*0x20)) - -#define DIEP_DMA(n) (OTG_BASE + (0x914 + (n)*0x20)) -#define DOEP_DMA(n) (OTG_BASE + (0xb14 + (n)*0x20)) - -#define REG_OTG_DCFG REG32(OTG_DCFG) -#define REG_OTG_DCTL REG32(OTG_DCTL) -#define REG_OTG_DSTS REG32(OTG_DSTS) -#define REG_DIEP_MASK REG32(DIEP_MASK) -#define REG_DOEP_MASK REG32(DOEP_MASK) -#define REG_OTG_DAINT REG32(OTG_DAINT) -#define REG_DAINT_MASK REG32(DAINT_MASK) -#define REG_DIEP_EMPMSK REG32(DIEP_EMPMSK) - -#define REG_DIEP_CTL(n) REG32(DIEP_CTL(n)) -#define REG_DOEP_CTL(n) REG32(DOEP_CTL(n)) - -#define REG_DIEP_INT(n) REG32(DIEP_INT(n)) -#define REG_DOEP_INT(n) REG32(DOEP_INT(n)) - -#define REG_DIEP_SIZE(n) REG32(DIEP_SIZE(n)) -#define REG_DOEP_SIZE(n) REG32(DOEP_SIZE(n)) - -#define REG_DIEP_TXFSTS(n) REG32(DIEP_TXFSTS(n)) - -#define REG_DIEP_DMA(n) REG32(DIEP_DMA(n)) -#define REG_DOEP_DMA(n) REG32(DOEP_DMA(n)) - -/* Regs macro define */ -/*************************************************/ -#define AHBCFG_TXFE_LVL BIT7 -#define AHBCFG_DMA_ENA BIT5 -#define AHBCFG_GLOBLE_INTRMASK BIT0 -#define USBCFG_FORCE_DEVICE BIT30 -#define USBCFG_TRDTIME_MASK (0xf << 10) -#define USBCFG_TRDTIME_9 (9 << 10) -#define USBCFG_TRDTIME_6 (6 << 10) - -/* GRSTCTL */ -#define RSTCTL_AHB_IDLE BIT31 -#define RSTCTL_TXFNUM_ALL (0x10 << 6) -#define RSTCTL_TXFIFO_FLUSH BIT5 -#define RSTCTL_RXFIFO_FLUSH BIT4 -#define RSTCTL_INTK_FLUSH BIT3 -#define RSTCTL_FRMCNT_RST BIT2 -#define RSTCTL_CORE_RST BIT0 - -/* GINTMSK */ -#define GINTMSK_RSUME_DETE BIT31 -#define GINTMSK_CONID_STSCHG BIT28 -#define GINTMSK_RESET_DETE BIT23 -#define GINTMSK_FETCH_SUSPEND BIT22 -#define GINTMSK_OEP_INTR BIT19 -#define GINTMSK_IEP_INTR BIT18 -#define GINTMSK_EP_MISMATCH BIT17 -#define GINTMSK_ENUM_DONE BIT13 -#define GINTMSK_USB_RESET BIT12 -#define GINTMSK_USB_SUSPEND BIT11 -#define GINTMSK_USB_EARLYSUSPEND BIT10 -#define GINTMSK_I2C_INT BIT9 -#define GINTMSK_ULPK_CKINT BIT8 -#define GINTMSK_GOUTNAK_EFF BIT7 -#define GINTMSK_GINNAK_EFF BIT6 -#define GINTMSK_NPTXFIFO_EMPTY BIT5 -#define GINTMSK_RXFIFO_NEMPTY BIT4 -#define GINTMSK_START_FRAM BIT3 -#define GINTMSK_OTG_INTR BIT2 -#define GINTMSK_MODE_MISMATCH BIT1 - -/* GINTSTS */ -#define GINTSTS_RSUME_DETE BIT31 -#define GINTSTS_CONID_STSCHG BIT28 -#define GINTSTS_RESET_DETE BIT23 -#define GINTSTS_FETCH_SUSPEND BIT22 -#define GINTSTS_OEP_INTR BIT19 -#define GINTSTS_IEP_INTR BIT18 -#define GINTSTS_EP_MISMATCH BIT17 -#define GINTSTS_ENUM_DONE BIT13 -#define GINTSTS_USB_RESET BIT12 -#define GINTSTS_USB_SUSPEND BIT11 -#define GINTSTS_USB_EARLYSUSPEND BIT10 -#define GINTSTS_I2C_INT BIT9 -#define GINTSTS_ULPK_CKINT BIT8 -#define GINTSTS_GOUTNAK_EFF BIT7 -#define GINTSTS_GINNAK_EFF BIT6 -#define GINTSTS_NPTXFIFO_EMPTY BIT5 -#define GINTSTS_RXFIFO_NEMPTY BIT4 -#define GINTSTS_START_FRAM BIT3 -#define GINTSTS_OTG_INTR BIT2 -#define GINTSTS_MODE_MISMATCH BIT1 - -/* DCTL */ -#define DCTL_CGOUTNAK BIT10 -#define DCTL_CLR_GNPINNAK BIT8 -#define DCTL_SGNPINNAK BIT7 -#define DCTL_SOFT_DISCONN BIT1 -#define DCTL_SGOUTNAK BIT9 -/* DCFG */ -#define DCFG_DEV_ADDR_MASK (0x7f << 4) -#define DCFG_DEV_ADDR_BIT 4 -#define DCFG_DEV_DESC_DMA (1 << 23) -/* DSTS */ -#define DSTS_ERRATIC_ERROR BIT3 -#define DSTS_ENUM_SPEED_MASK (0x3 << 1) -#define DSTS_ENUM_SPEED_BIT BIT1 -#define DSTS_ENUM_SPEED_HIGH (0x0 << 1) -#define DSTS_ENUM_SPEED_FULL_30OR60 (0x1 << 1) -#define DSTS_ENUM_SPEED_LOW (0x2 << 1) -#define DSTS_ENUM_SPEED_FULL_48 (0x3 << 1) - -/* GRXSTSR/GRXSTSP */ -#define GRXSTSP_PKSTS_MASK (0xf << 17) -#define GRXSTSP_PKSTS_GOUT_NAK (0x1 << 17) -#define GRXSTSP_PKSTS_GOUT_RECV (0x2 << 17) -#define GRXSTSP_PKSTS_TX_COMP (0x3 << 17) -#define GRXSTSP_PKSTS_SETUP_COMP (0x4 << 17) -#define GRXSTSP_PKSTS_SETUP_RECV (0x6 << 17) -#define GRXSTSP_BYTE_CNT_MASK (0x7ff << 4) -#define GRXSTSP_BYTE_CNT_BIT 4 -#define GRXSTSP_EPNUM_MASK (0xf) -#define GRXSTSP_EPNUM_BIT BIT0 - - -/* DIOEPCTL */ -// ep0 -#define DEP_EP0_MAXPKET_SIZE 64 -#define DEP_EP0_MPS_64 (0x0) -#define DEP_EP0_MPS_32 (0x1) -#define DEP_EP0_MPS_16 (0x2) -#define DEP_EP0_MPS_8 (0x3) - -#define DEP_ENA_BIT BIT31 -#define DEP_DISENA_BIT BIT30 -#define DEP_SET_NAK BIT27 -#define DEP_CLEAR_NAK BIT26 -#define DEP_SET_STALL BIT21 -#define DEP_TYPE_MASK (0x3 << 18) -#define DEP_TYPE_CNTL (0x0 << 18) -#define DEP_TYPE_ISO (0x1 << 18) -#define DEP_TYPE_BULK (0x2 << 18) -#define DEP_TYPE_INTR (0x3 << 18) -#define USB_ACTIVE_EP BIT15 -#define DEP_PKTSIZE_MASK 0x7ff -#define DEP_FS_PKTSIZE 64 -#define DEP_HS_PKTSIZE 512 - -/* DIOEPINT */ -#define DEP_NYET_INT BIT14 -#define DEP_NAK_INT BIT13 -#define DEP_BABBLE_ERR_INT BIT12 -#define DEP_PKT_DROP_STATUS BIT11 -#define DEP_BNA_INT BIT9 -#define DEP_TXFIFO_UNDRN BIT8 // Only for INEP -#define DEP_OUTPKT_ERR BIT8 // Only for OUTEP -#define DEP_TXFIFO_EMPTY BIT7 -#define DEP_INEP_NAKEFF BIT6 // Only for INEP -#define DEP_B2B_SETUP_RECV BIT6 // Only for OUTEP0 -#define DEP_INTOKEN_EPMISATCH BIT5 // Only for INEP -#define DEP_STATUS_PHASE_RECV BIT5 // Only for OUTEP0 -#define DEP_INTOKEN_RECV_TXFIFO_EMPTY BIT4 // Only for INEP -#define DEP_OUTTOKEN_RECV_EPDIS BIT4 // Only for OUTEP -#define DEP_TIME_OUT BIT3 // Only for INEP -#define DEP_SETUP_PHASE_DONE BIT3 // Only for OUTEP0 -#define DEP_AHB_ERR BIT2 -#define DEP_EPDIS_INT BIT1 -#define DEP_XFER_COMP BIT0 // Used by INEP and OUTEP - -/* DOEPSIZ0 */ -#define DOEPSIZE0_SUPCNT_1 (0x1 << 29) -#define DOEPSIZE0_SUPCNT_2 (0x2 << 29) -#define DOEPSIZE0_SUPCNT_3 (0x3 << 29) -#define DOEPSIZE0_PKTCNT_BIT BIT19 - - -#define DEP_RXFIFO_SIZE 1064 -#define DEP_NPTXFIFO_SIZE 1024 -#define DEP_DTXFIFO_SIZE 768 - - -#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0 -#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1 -#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3 -#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5 -#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7 - -#define DWC_GAHBCFG_EXT_DMA_BURST_1word 0x0 -#define DWC_GAHBCFG_EXT_DMA_BURST_4word 0x1 -#define DWC_GAHBCFG_EXT_DMA_BURST_8word 0x2 -#define DWC_GAHBCFG_EXT_DMA_BURST_16word 0x3 -#define DWC_GAHBCFG_EXT_DMA_BURST_32word 0x4 -#define DWC_GAHBCFG_EXT_DMA_BURST_64word 0x5 -#define DWC_GAHBCFG_EXT_DMA_BURST_128word 0x6 -#define DWC_GAHBCFG_EXT_DMA_BURST_256word 0x7 - -#define DEP_NUM 2 - -#if 0 -#define UTMI_PHY_WIDTH 8 -#else -#define UTMI_PHY_WIDTH 16 -#endif - -#endif /* _X1000_OTG_DWC_H_ */ diff --git a/libcpu/mips/x1000/x1000_slcdc.h b/libcpu/mips/x1000/x1000_slcdc.h deleted file mode 100644 index fab76ffad9..0000000000 --- a/libcpu/mips/x1000/x1000_slcdc.h +++ /dev/null @@ -1,463 +0,0 @@ -/* - * File : x1000_slcdc.h - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team - * - * Change Logs: - * Date Author Notes - * 2017��3��20�� Urey the first version - */ -#ifndef _X1000_SLCDC_H_ -#define _X1000_SLCDC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/************************************************************************* - * SLCD (Smart LCD Controller) - *************************************************************************/ -#define LCDC0_BASE LCD_BASE - -#define SLCDC_CFG (LCDC0_BASE + 0xA0) /* SLCDC Configure Register */ -#define SLCDC_CTRL (LCDC0_BASE + 0xA4) /* SLCDC Control Register */ -#define SLCDC_STATE (LCDC0_BASE + 0xA8) /* SLCDC Status Register */ -#define SLCDC_DATA (LCDC0_BASE + 0xAC) /* SLCDC Data Register */ - -#define SLCDC_CFG_NEW (LCDC0_BASE + 0xB8) -#define SLCDC_WTIME (LCDC0_BASE + 0xB0) -#define SLCDC_TAS (LCDC0_BASE + 0xB4) -#define SLCDC_SLOW_TIME (LCDC0_BASE + 0xBC) - -/* SLCDC Configure Register */ -#define SLCDC_CFG_DWIDTH_BIT 10 -#define SLCDC_CFG_DWIDTH_MASK (0x7 << SLCDC_CFG_DWIDTH_BIT) -#define SLCDC_CFG_DWIDTH_18BIT (0 << SLCDC_CFG_DWIDTH_BIT) -#define SLCDC_CFG_DWIDTH_16BIT (1 << SLCDC_CFG_DWIDTH_BIT) -#define SLCDC_CFG_DWIDTH_8BIT_x3 (2 << SLCDC_CFG_DWIDTH_BIT) -#define SLCDC_CFG_DWIDTH_8BIT_x2 (3 << SLCDC_CFG_DWIDTH_BIT) -#define SLCDC_CFG_DWIDTH_8BIT_x1 (4 << SLCDC_CFG_DWIDTH_BIT) -#define SLCDC_CFG_DWIDTH_24BIT (5 << SLCDC_CFG_DWIDTH_BIT) -#define SLCDC_CFG_DWIDTH_9BIT_x2 (7 << SLCDC_CFG_DWIDTH_BIT) -#define SLCDC_CFG_CWIDTH_BIT (8) -#define SLCDC_CFG_CWIDTH_MASK (0x3 << SLCDC_CFG_CWIDTH_BIT) -#define SLCDC_CFG_CWIDTH_16BIT (0 << SLCDC_CFG_CWIDTH_BIT) -#define SLCDC_CFG_CWIDTH_8BIT (1 << SLCDC_CFG_CWIDTH_BIT) -#define SLCDC_CFG_CWIDTH_18BIT (2 << SLCDC_CFG_CWIDTH_BIT) -#define SLCDC_CFG_CWIDTH_24BIT (3 << SLCDC_CFG_CWIDTH_BIT) -#define SLCDC_CFG_CS_ACTIVE_LOW (0 << 4) -#define SLCDC_CFG_CS_ACTIVE_HIGH (1 << 4) -#define SLCDC_CFG_RS_CMD_LOW (0 << 3) -#define SLCDC_CFG_RS_CMD_HIGH (1 << 3) -#define SLCDC_CFG_CLK_ACTIVE_FALLING (0 << 1) -#define SLCDC_CFG_CLK_ACTIVE_RISING (1 << 1) -#define SLCDC_CFG_TYPE_PARALLEL (0 << 0) -#define SLCDC_CFG_TYPE_SERIAL (1 << 0) - -/* SLCD New Configure Register */ -#define SLCDC_NEW_CFG_DWIDTH_BIT 13 -#define SLCDC_NEW_CFG_DWIDTH_MASK (0x7 << SLCDC_NEW_CFG_DWIDTH_BIT) -#define SLCDC_NEW_CFG_DWIDTH_8BIT (0 << SLCDC_NEW_CFG_DWIDTH_BIT) -#define SLCDC_NEW_CFG_DWIDTH_9BIT (1 << SLCDC_NEW_CFG_DWIDTH_BIT) -#define SLCDC_NEW_CFG_DWIDTH_16BIT (2 << SLCDC_NEW_CFG_DWIDTH_BIT) -#define SLCDC_NEW_CFG_DWIDTH_18BIT (3 << SLCDC_NEW_CFG_DWIDTH_BIT) -#define SLCDC_NEW_CFG_DWIDTH_24BIT (4 << SLCDC_NEW_CFG_DWIDTH_BIT) -#define SLCDC_NEW_CFG_6800_MD (1 << 11) -#define SLCDC_NEW_CFG_CMD_9BIT (1 << 10) /* only use in old slcd */ -#define SLCDC_NEW_CFG_CMD_16BIT (0 << 10) /* only use in old slcd */ -#define SLCDC_NEW_CFG_DTIME_BIT 8 -#define SLCDC_NEW_CFG_DTIME_MASK (0x3 << SLCDC_NEW_CFG_DTIME_BIT) -#define SLCDC_NEW_CFG_DTIME_ONCE (0 << SLCDC_NEW_CFG_DTIME_BIT) -#define SLCDC_NEW_CFG_DTIME_TWICE (1 << SLCDC_NEW_CFG_DTIME_BIT) -#define SLCDC_NEW_CFG_DTIME_THREE (2 << SLCDC_NEW_CFG_DTIME_BIT) -#define SLCDC_NEW_CFG_CS_HIGH_IDLE (0 << 5) -#define SLCDC_NEW_CFG_CS_LOW_IDLE (1 << 5) -#define SLCDC_NEW_CFG_RS_CMD_LOW (0 << 4) -#define SLCDC_NEW_CFG_RS_CMD_HIGH (1 << 4) -#define SLCDC_NEW_CFG_CLK_ACTIVE_FALLING (0 << 3) -#define SLCDC_NEW_CFG_CLK_ACTIVE_RISING (1 << 3) -#define SLCDC_NEW_CFG_DTYPE_PARALLEL (0 << 2) -#define SLCDC_NEW_CFG_DTYPE_SERIAL (1 << 2) -#define SLCDC_NEW_CFG_CTYPE_PARALLEL (0 << 1) -#define SLCDC_NEW_CFG_CTYPE_SERIAL (1 << 1) -#define SLCDC_NEW_CFG_FMT_CONV_EN (1 << 0) - -/* SLCD Control Register */ -#define SLCDC_CTRL_TE_INV (1 << 9) -#define SLCDC_CTRL_NOT_USE_TE (1 << 8) -#define SLCDC_CTRL_DCSI_SEL (1 << 7) -#define SLCDC_CTRL_MIPI_MODE (1 << 6) -#define SLCDC_CTRL_NEW_MODE (1 << 5) -#define SLCDC_CTRL_FAST_MODE (1 << 4) -#define SLCDC_CTRL_GATE_MASK (1 << 3) -#define SLCDC_CTRL_DMA_MODE (1 << 2) -#define SLCDC_CTRL_DMA_START (1 << 1) -#define SLCDC_CTRL_DMA_EN (1 << 0) - -/* SLCD Status Register */ -#define SLCDC_STATE_BUSY (1 << 0) - -/* SLCD Data Register */ -#define SLCDC_DATA_RS_DATA (0 << 30) -#define SLCDC_DATA_RS_COMMAND (1 << 30) - -/************************************************************************* - * LCDC (LCD Controller) - *************************************************************************/ - -#define LCDC_CFG (LCDC0_BASE + 0x00) -#define LCDC_CTRL (LCDC0_BASE + 0x30) -#define LCDC_STATE (LCDC0_BASE + 0x34) -#define LCDC_OSDC (LCDC0_BASE + 0x100) -#define LCDC_OSDCTRL (LCDC0_BASE + 0x104) -#define LCDC_OSDS (LCDC0_BASE + 0x108) -#define LCDC_BGC0 (LCDC0_BASE + 0x10C) -#define LCDC_BGC1 (LCDC0_BASE + 0x2C4) -#define LCDC_KEY0 (LCDC0_BASE + 0x110) -#define LCDC_KEY1 (LCDC0_BASE + 0x114) -#define LCDC_ALPHA (LCDC0_BASE + 0x118) -#define LCDC_RGBC (LCDC0_BASE + 0x90) -#define LCDC_VAT (LCDC0_BASE + 0x0c) -#define LCDC_DAH (LCDC0_BASE + 0x10) -#define LCDC_DAV (LCDC0_BASE + 0x14) -#define LCDC_XYP0 (LCDC0_BASE + 0x120) -#define LCDC_XYP1 (LCDC0_BASE + 0x124) -#define LCDC_SIZE0 (LCDC0_BASE + 0x128) -#define LCDC_SIZE1 (LCDC0_BASE + 0x12C) -#define LCDC_VSYNC (LCDC0_BASE + 0x04) -#define LCDC_HSYNC (LCDC0_BASE + 0x08) -#define LCDC_PS (LCDC0_BASE + 0x18) -#define LCDC_CLS (LCDC0_BASE + 0x1c) -#define LCDC_SPL (LCDC0_BASE + 0x20) -#define LCDC_REV (LCDC0_BASE + 0x24) -#define LCDC_IID (LCDC0_BASE + 0x38) -#define LCDC_DA0 (LCDC0_BASE + 0x40) -#define LCDC_SA0 (LCDC0_BASE + 0x44) -#define LCDC_FID0 (LCDC0_BASE + 0x48) -#define LCDC_CMD0 (LCDC0_BASE + 0x4c) -#define LCDC_DA1 (LCDC0_BASE + 0x50) -#define LCDC_SA1 (LCDC0_BASE + 0x54) -#define LCDC_FID1 (LCDC0_BASE + 0x58) -#define LCDC_CMD1 (LCDC0_BASE + 0x5c) -#define LCDC_OFFS0 (LCDC0_BASE + 0x60) -#define LCDC_PW0 (LCDC0_BASE + 0x64) -#define LCDC_CNUM0 (LCDC0_BASE + 0x68) -#define LCDC_DESSIZE0 (LCDC0_BASE + 0x6C) -#define LCDC_OFFS1 (LCDC0_BASE + 0x70) -#define LCDC_PW1 (LCDC0_BASE + 0x74) -#define LCDC_CNUM1 (LCDC0_BASE + 0x78) -#define LCDC_DESSIZE1 (LCDC0_BASE + 0x7C) -#define LCDC_PCFG (LCDC0_BASE + 0x2C0) -#define LCDC_CPOS1 (0x78) -#define LCDC_DUAL_CTRL (0x2c8) -#define LCDC_ENH_CFG (0x400) -#define LCDC_ENH_CSCCFG (0x404) -#define LCDC_ENH_LUMACFG (0x408) -#define LCDC_ENH_CHROCFG0 (0x40c) -#define LCDC_ENH_CHROCFG1 (0x410) -#define LCDC_ENH_DITHERCFG (0x414) -#define LCDC_ENH_STATUS (0x418) -#define LCDC_ENH_GAMMA (0x800) -#define LCDC_ENH_VEE (0x1000) - -/* LCD Configure Register */ -#define LCDC_CFG_LCDPIN_BIT 31 -#define LCDC_CFG_LCDPIN_MASK (0x1 << LCDC_CFG_LCDPIN_BIT) -#define LCDC_CFG_LCDPIN_LCD (0x0 << LCDC_CFG_LCDPIN_BIT) -#define LCDC_CFG_LCDPIN_SLCD (0x1 << LCDC_CFG_LCDPIN_BIT) -#define LCDC_CFG_TVEPEH (1 << 30) -#define LCDC_CFG_NEWDES (1 << 28) -#define LCDC_CFG_PALBP (1 << 27) -#define LCDC_CFG_TVEN (1 << 26) -#define LCDC_CFG_RECOVER (1 << 25) -#define LCDC_CFG_PSM (1 << 23) -#define LCDC_CFG_CLSM (1 << 22) -#define LCDC_CFG_SPLM (1 << 21) -#define LCDC_CFG_REVM (1 << 20) -#define LCDC_CFG_HSYNM (1 << 19) -#define LCDC_CFG_PCLKM (1 << 18) -#define LCDC_CFG_INVDAT (1 << 17) -#define LCDC_CFG_SYNDIR_IN (1 << 16) -#define LCDC_CFG_PSP (1 << 15) -#define LCDC_CFG_CLSP (1 << 14) -#define LCDC_CFG_SPLP (1 << 13) -#define LCDC_CFG_REVP (1 << 12) -#define LCDC_CFG_HSP (1 << 11) -#define LCDC_CFG_PCP (1 << 10) -#define LCDC_CFG_DEP (1 << 9) -#define LCDC_CFG_VSP (1 << 8) -#define LCDC_CFG_MODE_TFT_18BIT (1 << 7) -#define LCDC_CFG_MODE_TFT_16BIT (0 << 7) -#define LCDC_CFG_MODE_TFT_24BIT (1 << 6) -#define LCDC_CFG_MODE_BIT 0 -#define LCDC_CFG_MODE_MASK (0x0f << LCDC_CFG_MODE_BIT) -#define LCDC_CFG_MODE_GENERIC_TFT (0 << LCDC_CFG_MODE_BIT) -#define LCDC_CFG_MODE_SPECIAL_TFT_1 (1 << LCDC_CFG_MODE_BIT) -#define LCDC_CFG_MODE_SPECIAL_TFT_2 (2 << LCDC_CFG_MODE_BIT) -#define LCDC_CFG_MODE_SPECIAL_TFT_3 (3 << LCDC_CFG_MODE_BIT) -#define LCDC_CFG_MODE_NONINTER_CCIR656 (4 << LCDC_CFG_MODE_BIT) -#define LCDC_CFG_MODE_INTER_CCIR656 (6 << LCDC_CFG_MODE_BIT) -#define LCDC_CFG_MODE_SERIAL_TFT (12 << LCDC_CFG_MODE_BIT) -#define LCDC_CFG_MODE_LCM (13 << LCDC_CFG_MODE_BIT) -/* LCD Control Register */ -#define LCDC_CTRL_PINMD (1 << 31) -#define LCDC_CTRL_BST_BIT 28 -#define LCDC_CTRL_BST_MASK (0x7 << LCDC_CTRL_BST_BIT) -#define LCDC_CTRL_BST_4 (0 << LCDC_CTRL_BST_BIT) -#define LCDC_CTRL_BST_8 (1 << LCDC_CTRL_BST_BIT) -#define LCDC_CTRL_BST_16 (2 << LCDC_CTRL_BST_BIT) -#define LCDC_CTRL_BST_32 (3 << LCDC_CTRL_BST_BIT) -#define LCDC_CTRL_BST_64 (4 << LCDC_CTRL_BST_BIT) -#define LCDC_CTRL_RGB565 (0 << 27) -#define LCDC_CTRL_RGB555 (1 << 27) -#define LCDC_CTRL_OFUP (1 << 26) -#define LCDC_CTRL_PDD_BIT 16 -#define LCDC_CTRL_PDD_MASK (0xff << LCDC_CTRL_PDD_BIT) -#define LCDC_CTRL_DACTE (1 << 14) -#define LCDC_CTRL_EOFM (1 << 13) -#define LCDC_CTRL_SOFM (1 << 12) -#define LCDC_CTRL_OFUM (1 << 11) -#define LCDC_CTRL_IFUM0 (1 << 10) -#define LCDC_CTRL_IFUM1 (1 << 9) -#define LCDC_CTRL_LDDM (1 << 8) -#define LCDC_CTRL_QDM (1 << 7) -#define LCDC_CTRL_BEDN (1 << 6) -#define LCDC_CTRL_PEDN (1 << 5) -#define LCDC_CTRL_DIS (1 << 4) -#define LCDC_CTRL_ENA (1 << 3) -#define LCDC_CTRL_BPP_BIT 0 -#define LCDC_CTRL_BPP_MASK (0x07 << LCDC_CTRL_BPP_BIT) -#define LCDC_CTRL_BPP_1 (0 << LCDC_CTRL_BPP_BIT) -#define LCDC_CTRL_BPP_2 (1 << LCDC_CTRL_BPP_BIT) -#define LCDC_CTRL_BPP_4 (2 << LCDC_CTRL_BPP_BIT) -#define LCDC_CTRL_BPP_8 (3 << LCDC_CTRL_BPP_BIT) -#define LCDC_CTRL_BPP_16 (4 << LCDC_CTRL_BPP_BIT) -#define LCDC_CTRL_BPP_18_24 (5 << LCDC_CTRL_BPP_BIT) -#define LCDC_CTRL_BPP_CMPS_24 (6 << LCDC_CTRL_BPP_BIT) -#define LCDC_CTRL_BPP_30 (7 << LCDC_CTRL_BPP_BIT) -/* LCD Status Register */ -#define LCDC_STATE_QD (1 << 7) -#define LCDC_STATE_EOF (1 << 5) -#define LCDC_STATE_SOF (1 << 4) -#define LCDC_STATE_OFU (1 << 3) -#define LCDC_STATE_IFU0 (1 << 2) -#define LCDC_STATE_IFU1 (1 << 1) -#define LCDC_STATE_LDD (1 << 0) -/* OSD Configure Register */ -#define LCDC_OSDC_PREMULTI1 (1 << 23) -#define LCDC_OSDC_COEF_SLE1_BIT 21 -#define LCDC_OSDC_COEF_SLE1_MASK (0x03 << LCDC_OSDC_COEF_SLE1_BIT) -#define LCDC_OSDC_COEF_SLE1_0 (0 << LCDC_OSDC_COEF_SLE1_BIT) -#define LCDC_OSDC_COEF_SLE1_1 (1 << LCDC_OSDC_COEF_SLE1_BIT) -#define LCDC_OSDC_COEF_SLE1_2 (2 << LCDC_OSDC_COEF_SLE1_BIT) -#define LCDC_OSDC_COEF_SLE1_3 (3 << LCDC_OSDC_COEF_SLE1_BIT) -#define LCDC_OSDC_PREMULTI0 (1 << 20) -#define LCDC_OSDC_COEF_SLE0_BIT 18 -#define LCDC_OSDC_COEF_SLE0_MASK (0x03 << LCDC_OSDC_COEF_SLE0_BIT) -#define LCDC_OSDC_COEF_SLE0_0 (0 << LCDC_OSDC_COEF_SLE0_BIT) -#define LCDC_OSDC_COEF_SLE0_1 (1 << LCDC_OSDC_COEF_SLE0_BIT) -#define LCDC_OSDC_COEF_SLE0_2 (2 << LCDC_OSDC_COEF_SLE0_BIT) -#define LCDC_OSDC_COEF_SLE0_3 (3 << LCDC_OSDC_COEF_SLE0_BIT) -#define LCDC_OSDC_ALPHAMD1 (1 << 17) -#define LCDC_OSDC_SOFM1 (1 << 15) -#define LCDC_OSDC_EOFM1 (1 << 14) -#define LCDC_OSDC_SOFM0 (1 << 11) -#define LCDC_OSDC_EOFM0 (1 << 10) -#define LCDC_OSDC_DENDM (1 << 9) -#define LCDC_OSDC_F1EN (1 << 4) -#define LCDC_OSDC_F0EN (1 << 3) -#define LCDC_OSDC_ALPHAEN (1 << 2) -#define LCDC_OSDC_ALPHAMD0 (1 << 1) -#define LCDC_OSDC_OSDEN (1 << 0) -/* OSD Controll Register */ -#define LCDC_OSDCTRL_IPU_CLKEN (1 << 15) -#define LCDC_OSDCTRL_RGB0_RGB565 (0 << 5) -#define LCDC_OSDCTRL_RGB0_RGB555 (1 << 5) -#define LCDC_OSDCTRL_RGB1_RGB565 (0 << 4) -#define LCDC_OSDCTRL_RGB1_RGB555 (1 << 4) -#define LCDC_OSDCTRL_BPP_BIT 0 -#define LCDC_OSDCTRL_BPP_MASK (0x7<<LCDC_OSDCTRL_BPP_BIT) -#define LCDC_OSDCTRL_BPP_15_16 (4 << LCDC_OSDCTRL_BPP_BIT) -#define LCDC_OSDCTRL_BPP_18_24 (5 << LCDC_OSDCTRL_BPP_BIT) -#define LCDC_OSDCTRL_BPP_CMPS_24 (6 << LCDC_OSDCTRL_BPP_BIT) -#define LCDC_OSDCTRL_BPP_30 (7 << LCDC_OSDCTRL_BPP_BIT) -/* OSD State Register */ -#define LCDC_OSDS_SOF1 (1 << 15) -#define LCDC_OSDS_EOF1 (1 << 14) -#define LCDC_OSDS_SOF0 (1 << 11) -#define LCDC_OSDS_EOF0 (1 << 10) -#define LCDC_OSDS_DEND (1 << 8) -/* Background 0 or Background 1 Color Register */ -#define LCDC_BGC_RED_OFFSET 16 -#define LCDC_BGC_RED_MASK (0xFF << LCDC_BGC_RED_OFFSET) -#define LCDC_BGC_GREEN_OFFSET 8 -#define LCDC_BGC_GREEN_MASK (0xFF << LCDC_BGC_GREEN_OFFSET) -#define LCDC_BGC_BLUE_OFFSET 0 -#define LCDC_BGC_BLUE_MASK (0xFF << LCDC_BGC_BLUE_OFFSET) -/* Foreground 0 or Foreground 1 Color Key Register */ -#define LCDC_KEY_KEYEN (1 << 31) -#define LCDC_KEY_KEYMD (1 << 30) -#define LCDC_KEY_RED_OFFSET 16 -#define LCDC_KEY_RED_MASK (0xFF << LCDC_KEY_RED_OFFSET) -#define LCDC_KEY_GREEN_OFFSET 8 -#define LCDC_KEY_GREEN_MASK (0xFF << LCDC_KEY_GREEN_OFFSET) -#define LCDC_KEY_BLUE_OFFSET 0 -#define LCDC_KEY_BLUE_MASK (0xFF << LCDC_KEY_BLUE_OFFSET) -#define LCDC_KEY_MASK (LCDC_KEY_RED_MASK | LCDC_KEY_GREEN_MASK\ -/* ALPHA Register */ -#define LCDC_ALPHA1_OFFSET 8 -#define LCDC_ALPHA1_MASK (0xFF << LCDC_ALPHA1_OFFSET) -#define LCDC_ALPHA0_OFFSET 0 -#define LCDC_ALPHA0_MASK (0xFF << LCDC_ALPHA0_OFFSET) -/* IPU Restart Register */ -#define LCDC_IPUR_IPUREN (1 << 31) -#define LCDC_IPUR_IPURMASK (0xFFFFFF) -/* RGB Control Register */ -#define LCDC_RGBC_RGBDM (1 << 15) -#define LCDC_RGBC_DMM (1 << 14) -#define LCDC_RGBC_RGBFMT (1 << 7) -#define LCDC_RGBC_ODDRGB_BIT 4 -#define LCDC_RGBC_ODDRGB_MASK (0x7 << LCDC_RGBC_ODDRGB_BIT) -#define LCDC_RGBC_ODD_RGB (0 << LCDC_RGBC_ODDRGB_BIT) -#define LCDC_RGBC_ODD_RBG (1 << LCDC_RGBC_ODDRGB_BIT) -#define LCDC_RGBC_ODD_GRB (2 << LCDC_RGBC_ODDRGB_BIT) -#define LCDC_RGBC_ODD_GBR (3 << LCDC_RGBC_ODDRGB_BIT) -#define LCDC_RGBC_ODD_BRG (4 << LCDC_RGBC_ODDRGB_BIT) -#define LCDC_RGBC_ODD_BGR (5 << LCDC_RGBC_ODDRGB_BIT) -#define LCDC_RGBC_EVENRGB_BIT 0 -#define LCDC_RGBC_EVENRGB_MASK (0x7<<LCDC_RGBC_EVENRGB_BIT) -#define LCDC_RGBC_EVEN_RGB 0 -#define LCDC_RGBC_EVEN_RBG 1 -#define LCDC_RGBC_EVEN_GRB 2 -#define LCDC_RGBC_EVEN_GBR 3 -#define LCDC_RGBC_EVEN_BRG 4 -#define LCDC_RGBC_EVEN_BGR 5 -/* Vertical Synchronize Register */ -#define LCDC_VSYNC_VPS_BIT 16 -#define LCDC_VSYNC_VPS_MASK (0xfff << LCDC_VSYNC_VPS_BIT) -#define LCDC_VSYNC_VPE_BIT 0 -#define LCDC_VSYNC_VPE_MASK (0xfff << LCDC_VSYNC_VPE_BIT) -/* Horizontal Synchronize Register */ -#define LCDC_HSYNC_HPS_BIT 16 -#define LCDC_HSYNC_HPS_MASK (0xfff << LCDC_HSYNC_HPS_BIT) -#define LCDC_HSYNC_HPE_BIT 0 -#define LCDC_HSYNC_HPE_MASK (0xfff << LCDC_HSYNC_HPE_BIT) -/* Virtual Area Setting Register */ -#define LCDC_VAT_HT_BIT 16 -#define LCDC_VAT_HT_MASK (0xfff << LCDC_VAT_HT_BIT) -#define LCDC_VAT_VT_BIT 0 -#define LCDC_VAT_VT_MASK (0xfff << LCDC_VAT_VT_BIT) -/* Display Area Horizontal Start/End Point Register */ -#define LCDC_DAH_HDS_BIT 16 -#define LCDC_DAH_HDS_MASK (0xfff << LCDC_DAH_HDS_BIT) -#define LCDC_DAH_HDE_BIT 0 -#define LCDC_DAH_HDE_MASK (0xfff << LCDC_DAH_HDE_BIT) -/* Display Area Vertical Start/End Point Register */ -#define LCDC_DAV_VDS_BIT 16 -#define LCDC_DAV_VDS_MASK (0xfff << LCDC_DAV_VDS_BIT) -#define LCDC_DAV_VDE_BIT 0 -#define LCDC_DAV_VDE_MASK (0xfff << LCDC_DAV_VDE_BIT) -/* Foreground 0 or Foreground 1 XY Position Register */ -#define LCDC_XYP_YPOS_BIT 16 -#define LCDC_XYP_YPOS_MASK (0xfff << LCDC_XYP_YPOS_BIT) -#define LCDC_XYP_XPOS_BIT 0 -#define LCDC_XYP_XPOS_MASK (0xfff << LCDC_XYP_XPOS_BIT) -/* Foreground 0 or Foreground 1 Size Register */ -#define LCDC_SIZE_HEIGHT_BIT 16 -#define LCDC_SIZE_HEIGHT_MASK (0xfff << LCDC_SIZE_HEIGHT_BIT) -#define LCDC_SIZE_WIDTH_BIT 0 -#define LCDC_SIZE_WIDTH_MASK (0xfff << LCDC_SIZE_WIDTH_BIT) -/* PS Signal Setting */ -#define LCDC_PS_PSS_BIT 16 -#define LCDC_PS_PSS_MASK (0xfff << LCDC_PS_PSS_BIT) -#define LCDC_PS_PSE_BIT 0 -#define LCDC_PS_PSE_MASK (0xfff << LCDC_PS_PSE_BIT) -/* CLS Signal Setting */ -#define LCDC_CLS_CLSS_BIT 16 -#define LCDC_CLS_CLSS_MASK (0xfff << LCDC_CLS_CLSS_BIT) -#define LCDC_CLS_CLSE_BIT 0 -#define LCDC_CLS_CLSE_MASK (0xfff << LCDC_CLS_CLSE_BIT) -/* SPL Signal Setting */ -#define LCDC_SPL_SPLS_BIT 16 -#define LCDC_SPL_SPLS_MASK (0xfff << LCDC_SPL_SPLS_BIT) -#define LCDC_SPL_SPLE_BIT 0 -#define LCDC_SPL_SPLE_MASK (0xfff << LCDC_SPL_SPLE_BIT) -/* REV Signal Setting */ -#define LCDC_REV_REVS_BIT 16 -#define LCDC_REV_REVS_MASK (0xfff << LCDC_REV_REVS_BIT) -/* DMA Command 0 or 1 Register */ -#define LCDC_CMD_SOFINT (1 << 31) -#define LCDC_CMD_EOFINT (1 << 30) -#define LCDC_CMD_CMD (1 << 29) -#define LCDC_CMD_PAL (1 << 28) -#define LCDC_CMD_COMPEN (1 << 27) -#define LCDC_CMD_FRM_EN (1 << 26) -#define LCDC_CMD_FIELD_SEL (1 << 25) -#define LCDC_CMD_16X16BLOCK (1 << 24) -#define LCDC_CMD_LEN_BIT 0 -#define LCDC_CMD_LEN_MASK (0xffffff << LCDC_CMD_LEN_BIT) -/* DMA Offsize Register 0,1 */ -#define LCDC_OFFS_BIT 0 -#define LCDC_OFFS_OFFSIZE_MASK (0xffffff << LCDC_OFFS_BIT) -/* DMA Page Width Register 0,1 */ -#define LCDC_PW_BIT 0 -#define LCDC_PW_PAGEWIDTH_MASK (0xffffff << LCDC_PW_BIT) -/* DMA Command Counter Register 0,1 */ -#define LCDC_CNUM_BIT 0 -#define LCDC_CNUM_CNUM_MASK (0xff << LCDC_CNUM_BIT) -#define LCDC_CPOS_ALPHAMD1 (1 << 31) -#define LCDC_CPOS_RGB_RGB565 (0 << 30) -#define LCDC_CPOS_RGB_RGB555 (1 << 30) -#define LCDC_CPOS_BPP_BIT 27 -#define LCDC_CPOS_BPP_MASK (0x07 << LCDC_CPOS_BPP_BIT) -#define LCDC_CPOS_BPP_16 (4 << LCDC_CPOS_BPP_BIT) -#define LCDC_CPOS_BPP_18_24 (5 << LCDC_CPOS_BPP_BIT) -#define LCDC_CPOS_BPP_CMPS_24 (6 << LCDC_CPOS_BPP_BIT) -#define LCDC_CPOS_BPP_30 (7 << LCDC_CPOS_BPP_BIT) -#define LCDC_CPOS_PREMULTI (1 << 26) -#define LCDC_CPOS_COEF_SLE_BIT 24 -#define LCDC_CPOS_COEF_SLE_MASK (0x3 << LCDC_CPOS_COEF_SLE_BIT) -#define LCDC_CPOS_COEF_SLE_0 (0 << LCDC_CPOS_COEF_SLE_BIT) -#define LCDC_CPOS_COEF_SLE_1 (1 << LCDC_CPOS_COEF_SLE_BIT) -#define LCDC_CPOS_COEF_SLE_2 (2 << LCDC_CPOS_COEF_SLE_BIT) -#define LCDC_CPOS_COEF_SLE_3 (3 << LCDC_CPOS_COEF_SLE_BIT) -#define LCDC_CPOS_YPOS_BIT 12 -#define LCDC_CPOS_YPOS_MASK (0xfff << LCDC_CPOS_YPOS_BIT) -#define LCDC_CPOS_XPOS_BIT 0 -#define LCDC_CPOS_XPOS_MASK (0xfff << LCDC_CPOS_XPOS_BIT) -/* Foreground 0,1 Size Register */ -#define LCDC_DESSIZE_ALPHA_BIT 24 -#define LCDC_DESSIZE_ALPHA_MASK (0xff << LCDC_DESSIZE_ALPHA_BIT) -#define LCDC_DESSIZE_HEIGHT_BIT 12 -#define LCDC_DESSIZE_HEIGHT_MASK (0xfff << LCDC_DESSIZE_HEIGHT_BIT) -#define LCDC_DESSIZE_WIDTH_BIT 0 -#define LCDC_DESSIZE_WIDTH_MASK (0xfff << LCDC_DESSIZE_WIDTH_BIT) -/* Priority level threshold configure Register */ -#define LCDC_PCFG_LCDC_PRI_MD (1 << 31) -#define LCDC_PCFG_HP_BST_BIT 28 -#define LCDC_PCFG_HP_BST_MASK (0x7 << LCDC_PCFG_HP_BST_BIT) -#define LCDC_PCFG_HP_BST_4 (0 << LCDC_PCFG_HP_BST_BIT) -#define LCDC_PCFG_HP_BST_8 (1 << LCDC_PCFG_HP_BST_BIT) -#define LCDC_PCFG_HP_BST_16 (2 << LCDC_PCFG_HP_BST_BIT) -#define LCDC_PCFG_HP_BST_32 (3 << LCDC_PCFG_HP_BST_BIT) -#define LCDC_PCFG_HP_BST_C16 (5 << LCDC_PCFG_HP_BST_BIT) -#define LCDC_PCFG_HP_BST_64 (4 << LCDC_PCFG_HP_BST_BIT) -#define LCDC_PCFG_HP_BST_DIS (7 << LCDC_PCFG_HP_BST_BIT) -#define LCDC_PCFG_PCFG2_BIT 18 -#define LCDC_PCFG_PCFG2_MASK (0x1ff << LCDC_PCFG_PCFG2_BIT) -#define LCDC_PCFG_PCFG1_BIT 9 -#define LCDC_PCFG_PCFG1_MASK (0x1ff << LCDC_PCFG_PCFG1_BIT) -#define LCDC_PCFG_PCFG0_BIT 0 -#define LCDC_PCFG_PCFG0_MASK (0x1ff << LCDC_PCFG_PCFG0_BIT) -/* Dual LCDC Channel Control register */ -#define LCDC_DUAL_CTRL_IPU_WR_SEL (1 << 8) -#define LCDC_DUAL_CTRL_TFT_SEL (1 << 6) -#define LCDC_DUAL_CTRL_PRI_IPU_EN (1 << 5) -#define LCDC_DUAL_CTRL_PRI_IPU_BIT 3 -#define LCDC_DUAL_CTRL_PRI_IPU_MASK (0x3 << LCDC_DUAL_CTRL_PRI_IPU_BIT) - - -#ifdef __cplusplus -} -#endif - -#endif /* _X1000_SLCDC_H_ */ diff --git a/libcpu/mips/xburst/SConscript b/libcpu/mips/xburst/SConscript deleted file mode 100644 index 0f06c299bb..0000000000 --- a/libcpu/mips/xburst/SConscript +++ /dev/null @@ -1,11 +0,0 @@ -# RT-Thread building script for component - -from building import * - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.S') -CPPPATH = [cwd] - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/libcpu/mips/xburst/cache.c b/libcpu/mips/xburst/cache.c deleted file mode 100644 index cd37f69993..0000000000 --- a/libcpu/mips/xburst/cache.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * File : cache.c - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes -*/ - -#include "../xburst/cache.h" - -#include <board.h> - -#define CACHE_SIZE 16*1024 -#define CACHE_LINE_SIZE 32 -#define KSEG0 0x80000000 - -#define K0_TO_K1() \ -do { \ - unsigned long __k0_addr; \ - \ - __asm__ __volatile__( \ - "la %0, 1f\n\t" \ - "or %0, %0, %1\n\t" \ - "jr %0\n\t" \ - "nop\n\t" \ - "1: nop\n" \ - : "=&r"(__k0_addr) \ - : "r" (0x20000000) ); \ -} while(0) - -#define K1_TO_K0() \ -do { \ - unsigned long __k0_addr; \ - __asm__ __volatile__( \ - "nop;nop;nop;nop;nop;nop;nop\n\t" \ - "la %0, 1f\n\t" \ - "jr %0\n\t" \ - "nop\n\t" \ - "1: nop\n" \ - : "=&r" (__k0_addr)); \ -} while (0) - -#define INVALIDATE_BTB() \ -do { \ - unsigned long tmp; \ - __asm__ __volatile__( \ - ".set mips32\n\t" \ - "mfc0 %0, $16, 7\n\t" \ - "nop\n\t" \ - "ori %0, 2\n\t" \ - "mtc0 %0, $16, 7\n\t" \ - "nop\n\t" \ - ".set mips2\n\t" \ - : "=&r" (tmp)); \ -} while (0) - -#define SYNC_WB() __asm__ __volatile__ ("sync") - -#define cache_op(op,addr) \ - __asm__ __volatile__( \ - " .set noreorder \n" \ - " .set mips32\n\t \n" \ - " cache %0, %1 \n" \ - " .set mips0 \n" \ - " .set reorder" \ - : \ - : "i" (op), "m" (*(unsigned char *)(addr))) - -void __icache_invalidate_all(void) -{ - unsigned int i; - - K0_TO_K1(); - - asm volatile (".set noreorder\n" - ".set mips32\n\t" - "mtc0\t$0,$28\n\t" - "mtc0\t$0,$29\n" - ".set mips0\n" - ".set reorder\n"); - for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE) - cache_op(Index_Store_Tag_I, i); - - K1_TO_K0(); - - INVALIDATE_BTB(); -} - -void __dcache_writeback_all(void) -{ - unsigned int i; - - for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE) - cache_op(Index_Writeback_Inv_D, i); - - SYNC_WB(); -} - -void rt_hw_cache_init(void) -{ - __dcache_writeback_all(); - __icache_invalidate_all(); -} - diff --git a/libcpu/mips/xburst/cache.h b/libcpu/mips/xburst/cache.h deleted file mode 100644 index c0f8a1f424..0000000000 --- a/libcpu/mips/xburst/cache.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * File : cache.h - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes -*/ - -#ifndef __CACHE_H__ -#define __CACHE_H__ - -/* - * Cache Operations - */ -#define Index_Invalidate_I 0x00 -#define Index_Writeback_Inv_D 0x01 -#define Index_Invalidate_SI 0x02 -#define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_D 0x0d -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_I 0x10 -#define Hit_Invalidate_D 0x11 -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Fill 0x14 -#define Hit_Writeback_Inv_D 0x15 -/* 0x16 is unused */ -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 -/* 0x1a is unused */ -#define Hit_Writeback_SD 0x1b -/* 0x1c is unused */ -/* 0x1e is unused */ -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f - -void rt_hw_cache_init(void); - -#endif diff --git a/libcpu/mips/xburst/cache_gcc.S b/libcpu/mips/xburst/cache_gcc.S deleted file mode 100644 index 76552698d0..0000000000 --- a/libcpu/mips/xburst/cache_gcc.S +++ /dev/null @@ -1,42 +0,0 @@ -/* - * File : cache_init.S - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - */ -#include "../common/mips.inc" -#include "../common/mipsregs.h" -#include "../common/stackframe.h" - - .text - .set noreorder - - .globl cache_init - .ent cache_init -cache_init: - .set noreorder - mtc0 zero, CP0_TAGLO - move t0, a0 // cache total size - move t1, a1 // cache line size - li t2, 0x80000000 - addu t3, t0, t2 - -_cache_init_loop: - cache 8, 0(t2) // icache_index_store_tag - cache 9, 0(t2) // dcache_index_store_tag - addu t2, t1 - bne t2, t3, _cache_init_loop - nop - - mfc0 t0, CP0_CONFIG - li t1, 0x7 - not t1 - and t0, t0, t1 - or t0, 0x3 // cacheable, noncoherent, write-back, write allocate - mtc0 t0, CP0_CONFIG - - jr ra - nop - - .set reorder - .end cache_init diff --git a/libcpu/mips/xburst/context_gcc.S b/libcpu/mips/xburst/context_gcc.S deleted file mode 100644 index d018de3da8..0000000000 --- a/libcpu/mips/xburst/context_gcc.S +++ /dev/null @@ -1,146 +0,0 @@ -/* - * File : context_gcc.S - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-09-11 bernard port to Jz4755 - */ -#include "../common/mips.inc" -#include "../common/stackframe.h" -#include "stack.h" - - .section ".text", "ax" - .set noreorder - -/* - * rt_base_t rt_hw_interrupt_disable() - */ - .globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mfc0 v0, CP0_STATUS - and v1, v0, 0xfffffffe - mtc0 v1, CP0_STATUS - jr ra - nop - -/* - * void rt_hw_interrupt_enable(rt_base_t level) - */ - .globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - mtc0 a0, CP0_STATUS - jr ra - nop - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to) - * a0 --> from - * a1 --> to - */ - .globl rt_hw_context_switch -rt_hw_context_switch: - mtc0 ra, CP0_EPC - SAVE_ALL - - sw sp, 0(a0) /* store sp in preempted tasks TCB */ - lw sp, 0(a1) /* get new task stack pointer */ - - RESTORE_ALL_AND_RET - -/* - * void rt_hw_context_switch_to(rt_uint32 to)/* - * a0 --> to - */ - .globl rt_hw_context_switch_to -rt_hw_context_switch_to: - lw sp, 0(a0) /* get new task stack pointer */ - - RESTORE_ALL_AND_RET - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/* - */ - .globl rt_thread_switch_interrupt_flag - .globl rt_interrupt_from_thread - .globl rt_interrupt_to_thread - .globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - la t0, rt_thread_switch_interrupt_flag - lw t1, 0(t0) - nop - bnez t1, _reswitch - nop - li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ - sw t1, 0(t0) - la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ - sw a0, 0(t0) -_reswitch: - la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ - sw a1, 0(t0) - jr ra - nop - - .globl system_dump - -/* - * void rt_hw_context_switch_interrupt_do(rt_base_t flag) - */ - .globl rt_interrupt_enter - .globl rt_interrupt_leave - .globl mips_irq_handle -mips_irq_handle: - SAVE_ALL - - mfc0 t0, CP0_CAUSE - mfc0 t1, CP0_STATUS - and t0, t1 - - andi t0, 0xff00 - beqz t0, spurious_interrupt - nop - - /* let k0 keep the current context sp */ - move k0, sp - /* switch to kernel stack */ - li sp, SYSTEM_STACK - - jal rt_interrupt_enter - nop - jal rt_interrupt_dispatch - nop - jal rt_interrupt_leave - nop - - /* switch sp back to thread's context */ - move sp, k0 - - /* - * if rt_thread_switch_interrupt_flag set, jump to - * rt_hw_context_switch_interrupt_do and don't return - */ - la k0, rt_thread_switch_interrupt_flag - lw k1, 0(k0) - beqz k1, spurious_interrupt - nop - sw zero, 0(k0) /* clear flag */ - nop - - /* - * switch to the new thread - */ - la k0, rt_interrupt_from_thread - lw k1, 0(k0) - nop - sw sp, 0(k1) /* store sp in preempted tasks's TCB */ - - la k0, rt_interrupt_to_thread - lw k1, 0(k0) - nop - lw sp, 0(k1) /* get new task's stack pointer */ - j spurious_interrupt - nop - -spurious_interrupt: - RESTORE_ALL_AND_RET - - .set reorder diff --git a/libcpu/mips/xburst/cpu.c b/libcpu/mips/xburst/cpu.c deleted file mode 100644 index 88137535d9..0000000000 --- a/libcpu/mips/xburst/cpu.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * File : cpu.c - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2010-07-09 Bernard first version - * 2010-09-11 Bernard add CPU reset implementation - */ -#include <rtthread.h> -#include <board.h> - -/** - * @addtogroup Ingenic - */ -/*@{*/ - -/** - * this function will reset CPU - * - */ -void rt_hw_cpu_reset() -{ - /* open the watch-dog */ - REG_WDT_TCSR = WDT_TCSR_EXT_EN; - REG_WDT_TCSR |= WDT_TCSR_PRESCALE_1024; - REG_WDT_TDR = 0x03; - REG_WDT_TCNT = 0x00; - REG_WDT_TCER |= WDT_TCER_TCEN; - - rt_kprintf("reboot system...\n"); - while (1); -} - -/** - * this function will shutdown CPU - * - */ -void rt_hw_cpu_shutdown() -{ - rt_kprintf("shutdown...\n"); - - while (1); -} - -/** - * This function finds the first bit set (beginning with the least significant bit) - * in value and return the index of that bit. - * - * Bits are numbered starting at 1 (the least significant bit). A return value of - * zero from any of these functions means that the argument was zero. - * - * @return return the index of the first bit set. If value is 0, then this function - * shall return 0. - */ -int __rt_ffs(int value) -{ - return __builtin_ffs(value); -} - -/*@}*/ diff --git a/libcpu/mips/xburst/exception.c b/libcpu/mips/xburst/exception.c deleted file mode 100644 index aebdf704ea..0000000000 --- a/libcpu/mips/xburst/exception.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * File : exception.c - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - */ -#include <rtthread.h> -#include <rthw.h> -#include "../common/exception.h" -#include "../common/mipsregs.h" - -/** - * @addtogroup Ingenic - */ -/*@{*/ - -/** - * exception handle table - */ -exception_func_t sys_exception_handlers[33]; - -/** - * setup the exception handle - */ -exception_func_t rt_set_except_vector(int n, exception_func_t func) -{ - exception_func_t old_handler = sys_exception_handlers[n]; - - if ((n == 0) || (n > 32) || (!func)) - { - return 0; - } - - sys_exception_handlers[n] = func; - - return old_handler; -} - -void tlb_refill_handler(void) -{ - rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); -} - -void cache_error_handler(void) -{ - rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc()); - rt_hw_cpu_shutdown(); -} - -static void unhandled_exception_handle(pt_regs_t *regs) -{ - rt_kprintf("exception happens, epc: 0x%08x\n", regs->cp0_epc); -} - -void install_default_execpt_handle(void) -{ - rt_int32_t i; - - for (i=0; i<33; i++) - sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle; -} - -/*@}*/ - diff --git a/libcpu/mips/xburst/interrupt.c b/libcpu/mips/xburst/interrupt.c deleted file mode 100644 index 337646c735..0000000000 --- a/libcpu/mips/xburst/interrupt.c +++ /dev/null @@ -1,249 +0,0 @@ -/* - * File : interrupt.c - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * 2010-07-09 Bernard first version - * 2013-03-29 aozima Modify the interrupt interface implementations. - */ - -#include <rtthread.h> -#include <rthw.h> -#include <board.h> - -#if defined(RT_USING_JZ4770) || defined(RT_USING_JZ4775) || defined(RT_USING_JZ_M150) || defined(RT_USING_JZ_X1000) -#define INTERRUPTS_MAX 64 -#else -#define INTERRUPTS_MAX 32 -#endif - -extern rt_uint32_t rt_interrupt_nest; -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -static struct rt_irq_desc isr_table[INTERRUPTS_MAX]; - -/** - * @addtogroup Ingenic - */ -/*@{*/ - -static void rt_hw_interrupt_handler(int vector, void *param) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} - -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init(void) -{ - rt_int32_t idx; - - rt_memset(isr_table, 0x00, sizeof(isr_table)); - for (idx = 0; idx < INTERRUPTS_MAX; idx ++) - { - isr_table[idx].handler = rt_hw_interrupt_handler; - } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -/** - * This function will mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_mask(int vector) -{ - /* mask interrupt */ - __intc_mask_irq(vector); -} - -/** - * This function will un-mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_umask(int vector) -{ - __intc_unmask_irq(vector); -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param handler the interrupt service routine to be installed - * @param param the interrupt service function parameter - * @param name the interrupt name - * @return old handler - */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) -{ - rt_isr_handler_t old_handler = RT_NULL; - - if(vector < INTERRUPTS_MAX) - { - old_handler = isr_table[vector].handler; - -#ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); -#endif /* RT_USING_INTERRUPT_INFO */ - isr_table[vector].handler = handler; - isr_table[vector].param = param; - } - - return old_handler; -} - -#if defined(RT_USING_JZ4770) || defined(RT_USING_JZ4775) || defined(RT_USING_JZ_M150) || defined(RT_USING_JZ_X1000) -/* - * fls - find last bit set. - * @word: The word to search - * - * This is defined the same way as ffs. - * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. - */ -rt_inline int fls(int x) -{ - __asm__("clz %0, %1" : "=r" (x) : "r" (x)); - - return 32 - x; -} -#endif - -#include <mipsregs.h> - -void rt_interrupt_dispatch(void *ptreg) -{ - int i; - void *param; - rt_isr_handler_t irq_func; - -#if defined(RT_USING_JZ4770) || defined(RT_USING_JZ4775) || defined(RT_USING_JZ_M150) || defined(RT_USING_JZ_X1000) - int irq = 0, group; - rt_uint32_t intc_ipr0 = 0, intc_ipr1 = 0, vpu_pending = 0; - - rt_uint32_t c0_status, c0_cause; - rt_uint32_t pending_im; - - /* check os timer */ - c0_status = read_c0_status(); - c0_cause = read_c0_cause(); - - pending_im = (c0_cause & ST0_IM) & (c0_status & ST0_IM); - - if (pending_im & CAUSEF_IP3) - { - extern void rt_hw_ost_handler(void); - rt_hw_ost_handler(); - return; - } - - if (pending_im & CAUSEF_IP2) - { - intc_ipr0 = REG_INTC_IPR(0); - intc_ipr1 = REG_INTC_IPR(1); - - if (intc_ipr0) - { - irq = fls(intc_ipr0) - 1; - intc_ipr0 &= ~(1<<irq); - } - else if(intc_ipr1) - { - irq = fls(intc_ipr1) - 1; - intc_ipr1 &= ~(1<<irq); - irq += 32; - } -#ifndef RT_USING_JZ_X1000 /* X1000 has no VPU */ - else - { - __asm__ __volatile__ ( - "mfc0 %0, $13, 0 \n\t" - "nop \n\t" - :"=r"(vpu_pending) - :); - - if(vpu_pending & 0x800) - irq = IRQ_VPU; - else - return; - } -#endif - - if (irq >= INTERRUPTS_MAX) - rt_kprintf("max interrupt, irq=%d\n", irq); - - /* do interrupt */ - irq_func = isr_table[irq].handler; - param = isr_table[irq].param; - (*irq_func)(irq, param); - -#ifdef RT_USING_INTERRUPT_INFO - isr_table[i].counter++; -#endif /* RT_USING_INTERRUPT_INFO */ - - /* ack interrupt */ - __intc_ack_irq(irq); - } - - if (pending_im & CAUSEF_IP0) - rt_kprintf("CAUSEF_IP0\n"); - if (pending_im & CAUSEF_IP1) - rt_kprintf("CAUSEF_IP1\n"); - if (pending_im & CAUSEF_IP4) - rt_kprintf("CAUSEF_IP4\n"); - if (pending_im & CAUSEF_IP5) - rt_kprintf("CAUSEF_IP5\n"); - if (pending_im & CAUSEF_IP6) - rt_kprintf("CAUSEF_IP6\n"); - if (pending_im & CAUSEF_IP7) - rt_kprintf("CAUSEF_IP7\n"); -#else - static rt_uint32_t pending = 0; - - /* the hardware interrupt */ - pending |= REG_INTC_IPR; - if (!pending) return; - - for (i = INTERRUPTS_MAX; i > 0; --i) - { - if ((pending & (1<<i))) - { - pending &= ~(1<<i); - - /* do interrupt */ - irq_func = isr_table[i].handler; - param = isr_table[i].param; - (*irq_func)(i, param); - -#ifdef RT_USING_INTERRUPT_INFO - isr_table[i].counter++; -#endif /* RT_USING_INTERRUPT_INFO */ - - /* ack interrupt */ - __intc_ack_irq(i); - } - } -#endif -} - -/*@}*/ diff --git a/libcpu/mips/xburst/mipscfg.c b/libcpu/mips/xburst/mipscfg.c deleted file mode 100644 index 1e9b0c032f..0000000000 --- a/libcpu/mips/xburst/mipscfg.c +++ /dev/null @@ -1,358 +0,0 @@ -/* - * File : mipscfg.c - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2010-05-27 swkyer first version - */ -#include <rtthread.h> -#include "../common/mipsregs.h" -#include "../common/mipscfg.h" - -mips32_core_cfg_t g_mips_core = -{ - 16, /* icache_line_size */ - 256, /* icache_lines_per_way */ - 4, /* icache_ways */ - 16, /* dcache_line_size */ - 256, /* dcache_lines_per_way */ - 4, /* dcache_ways */ - 16, /* max_tlb_entries */ -}; - -static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) -{ - rt_uint16_t rets = 1; - - while (n--) - rets *= b; - - return rets; -} - -/** - * read core attribute - */ -void mips32_cfg_init(void) -{ - rt_uint16_t val; - rt_uint32_t cp0_config1; - - cp0_config1 = read_c0_config(); - if (cp0_config1 & 0x80000000) - { - cp0_config1 = read_c0_config1(); - - val = (cp0_config1 & (7<<22))>>22; - g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<19))>>19; - g_mips_core.icache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<16))>>16; - g_mips_core.icache_ways = val + 1; - - val = (cp0_config1 & (7<<13))>>13; - g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); - val = (cp0_config1 & (7<<10))>>10; - g_mips_core.dcache_line_size = 2 * m_pow(2, val); - val = (cp0_config1 & (7<<7))>>7; - g_mips_core.dcache_ways = val + 1; - - val = (cp0_config1 & (0x3F<<25))>>25; - g_mips_core.max_tlb_entries = val + 1; - } -} - -#ifdef RT_USING_FINSH -#include <finsh.h> -static void CP0_status_analyze(unsigned long value) -{ - if(value & (1<<26)) - rt_kprintf(" FR"); - if(value & (1<<23)) - rt_kprintf(" PX"); - if(value & (1<<22)) - rt_kprintf(" BEV"); - if(value & (1<<20)) - rt_kprintf(" SR"); - if(value & (1<<19)) - rt_kprintf(" NMI"); - if(value & (1<<20)) - rt_kprintf(" SR"); - if(value & (0xFF<<8)) - rt_kprintf(" IM:0x%02X", (value >> 8) & 0xFF); - if(value & (1<<7)) - rt_kprintf(" KX"); - if(value & (1<<6)) - rt_kprintf(" SX"); - if(value & (1<<5)) - rt_kprintf(" UX"); - if(value & (0x03<<3)) - rt_kprintf(" KSU:0x%02X", (value >> 3) & 0x03); - if(value & (1<<2)) - rt_kprintf(" ERL"); - if(value & (1<<1)) - rt_kprintf(" EXL"); - if(value & (1<<0)) - rt_kprintf(" IE"); -} - -static void CP0_config0_analyze(unsigned long value) -{ - /* [31] M */ - if(value & (1UL<<31)) - rt_kprintf(" M"); - - /* [15] BE */ - if(value & (1<<15)) - rt_kprintf(" big-endian"); - else - rt_kprintf(" little-endian"); - - /* [14:13] AT */ - { - int AT = (value >> 13) & 0x03; - - if(AT == 0) - { - rt_kprintf(" MIPS32"); - } - else if(AT == 1) - { - rt_kprintf(" MIPS64/A32"); - } - else if(AT == 2) - { - rt_kprintf(" MIPS64/A64"); - } - else - { - rt_kprintf(" unkown"); - } - } - - /* [12:10] AR */ - { - int AR = (value >> 10) & 0x07; - - if(AR == 0) - { - rt_kprintf(" R1"); - } - else if(AR == 1) - { - rt_kprintf(" R2"); - } - else - { - rt_kprintf(" reserve"); - } - } - - /* [3] VI */ - if(value & (1UL<<31)) - rt_kprintf(" VI"); - - /* [2:0] K0 */ - { - int K0 = value & 0x07; - - if(K0 == 2) - { - rt_kprintf(" uncached"); - } - else if(K0 == 3) - { - rt_kprintf(" cacheable"); - } - else - { - rt_kprintf(" K0:reserve"); - } - } -} - -static void CP0_config1_analyze(unsigned long value) -{ - /* [31] M */ - if(value & (1UL<<31)) - rt_kprintf(" M"); - - /* [30:25] MMU size */ - { - int MMU_size = (value >> 25) & 0x3F; - rt_kprintf(" TLB:%d", MMU_size + 1); - } - - /* [24:22] IS, [21:19] IL, [18:16] IA */ - { - int IS = (value >> 22) & 0x07; - int IL = (value >> 19) & 0x07; - int IA = (value >> 16) & 0x07; - - IA = IA + 1; - IS = 64 << IS; - IL = 2 << IL; - rt_kprintf(" Icache-%dKB:%dway*%dset*%dbyte", - (IA*IS*IL) >> 10, IA, IS, IL); - } - - /* [15:13] DS, [12:10] DL, [9:7] DA */ - { - int DS = (value >> 13) & 0x07; - int DL = (value >> 10) & 0x07; - int DA = (value >> 7) & 0x07; - - DA = DA + 1; - DS = 64 << DS; - DL = 2 << DL; - rt_kprintf(" Dcache-%dKB:%dway*%dset*%dbyte", - (DA*DS*DL) >> 10, DA, DS, DL); - } - - /* [6] C2 */ - if(value & (1UL<<6)) - rt_kprintf(" CP2"); - - /* [5] MD */ - if(value & (1UL<<5)) - rt_kprintf(" MDMX-ASE"); - - /* [4] PC */ - if(value & (1UL<<4)) - rt_kprintf(" performa-count"); - - /* [3] WR */ - if(value & (1UL<<3)) - rt_kprintf(" Watch"); - - /* [2] CA */ - if(value & (1UL<<2)) - rt_kprintf(" MIPS16e"); - - /* [1] EP */ - if(value & (1UL<<1)) - rt_kprintf(" EJTAG"); - - /* [0] FP */ - if(value & (1UL<<0)) - rt_kprintf(" FPU"); -} - -static void CP0_config2_analyze(unsigned long value) -{ - /* [31] M */ - if(value & (1UL<<31)) - rt_kprintf(" M"); -} - -static void CP0_config3_analyze(unsigned long value) -{ - /* [31] M */ - if(value & (1UL<<31)) - rt_kprintf(" M"); -} - -static void list_mips(void) -{ - unsigned long value; - unsigned long num = 0; - - rt_kprintf("MIPS coprocessor register:\r\n"); - - rt_kprintf("( 0,0) INDEX : 0x%08X\r\n", read_c0_index()); - rt_kprintf("( 1,0) RANDOM : 0x%08X\r\n", read_c0_random()); - rt_kprintf("( 2,0) ENTRYLO0 : 0x%08X\r\n", read_c0_entrylo0()); - rt_kprintf("( 3,0) ENTRYLO1 : 0x%08X\r\n", read_c0_entrylo1()); - rt_kprintf("( 4,0) CONTEXT : 0x%08X\r\n", read_c0_context()); - rt_kprintf("( 5,0) PAGEMASK : 0x%08X\r\n", read_c0_pagemask()); - rt_kprintf("( 6,0) WIRED : 0x%08X\r\n", read_c0_wired()); - rt_kprintf("( 7,0) INFO : 0x%08X\r\n", read_c0_info()); - rt_kprintf("( 8,0) BADVADDR : 0x%08X\r\n", read_c0_badvaddr()); - rt_kprintf("( 9,0) COUNT : 0x%08X\r\n", read_c0_count()); - rt_kprintf("(10,0) ENTRYHI : 0x%08X\r\n", read_c0_entryhi()); - rt_kprintf("(11,0) COMPARE : 0x%08X\r\n", read_c0_compare()); - - value = read_c0_status(); - rt_kprintf("(12,0) STATUS : 0x%08X", value); - CP0_status_analyze(value); - rt_kprintf("\r\n"); - - /* - rt_kprintf("(12,1) INTCTL : 0x%08X\r\n", __read_32bit_c0_register(12, 1)); - rt_kprintf("(12,2) SRSCTL : 0x%08X\r\n", __read_32bit_c0_register(12, 2)); - */ - - rt_kprintf("(13,0) CAUSE : 0x%08X\r\n", read_c0_cause()); - rt_kprintf("(14,0) EPC : 0x%08X\r\n", read_c0_epc()); - rt_kprintf("(15,0) PRID : 0x%08X\r\n", read_c0_prid()); - rt_kprintf("(15,1) EBASE : 0x%08X\r\n", read_c0_ebase()); - - value = read_c0_config(); - rt_kprintf("(16,0) CONFIG : 0x%08X", value); - CP0_config0_analyze(value); - rt_kprintf("\r\n"); - if(value & (1UL << 31)) - { - value = read_c0_config1(); - rt_kprintf("(16,1) CONFIG1 : 0x%08X", value); - CP0_config1_analyze(value); - rt_kprintf("\r\n"); - - if(value & (1UL << 31)) - { - value = read_c0_config2(); - rt_kprintf("(16,2) CONFIG2 : 0x%08X\r\n", value); - CP0_config2_analyze(value); - rt_kprintf("\r\n"); - - if(value & (1UL << 31)) - { - value = read_c0_config3(); - rt_kprintf("(16,3) CONFIG3 : 0x%08X\r\n", value); - CP0_config3_analyze(value); - rt_kprintf("\r\n"); - } - } - } - - rt_kprintf("(17,0) LLADDR : 0x%08X\r\n", __read_32bit_c0_register($17, 0)); - rt_kprintf("(18,0) WATCHLO : 0x%08X\r\n", __read_32bit_c0_register($18, 0)); - rt_kprintf("(19,0) WATCHHI : 0x%08X\r\n", __read_32bit_c0_register($19, 0)); - rt_kprintf("(20,0) XCONTEXT : 0x%08X\r\n", __read_32bit_c0_register($20, 0)); - rt_kprintf("(21,0) FRAMEMASK : 0x%08X\r\n", __read_32bit_c0_register($21, 0)); - rt_kprintf("(22,0) DIAGNOSTIC: 0x%08X\r\n", __read_32bit_c0_register($22, 0)); - rt_kprintf("(23,0) DEBUG : 0x%08X\r\n", __read_32bit_c0_register($23, 0)); - rt_kprintf("(24,0) DEPC : 0x%08X\r\n", __read_32bit_c0_register($24, 0)); - - rt_kprintf("(25,0) PERFCTL0 : 0x%08X\r\n", __read_32bit_c0_register($25, 0)); - rt_kprintf("(26,0) ECC : 0x%08X\r\n", __read_32bit_c0_register($26, 0)); - rt_kprintf("(27,0) CACHEERR : 0x%08X\r\n", __read_32bit_c0_register($27, 0)); - rt_kprintf("(28,0) TAGLO : 0x%08X\r\n", __read_32bit_c0_register($28, 0)); - rt_kprintf("(29,0) TAGHI : 0x%08X\r\n", __read_32bit_c0_register($29, 0)); - - /* - rt_kprintf("(30,0) ERROREPC : 0x%08X\r\n", __read_32bit_c0_register($30, 0)); - rt_kprintf("(31,0) DESAVE : 0x%08X\r\n", __read_32bit_c0_register($31, 0)); - */ - - - rt_kprintf("\r\n"); -} -FINSH_FUNCTION_EXPORT(list_mips, list CPU info) -#endif /* RT_USING_FINSH */ - diff --git a/libcpu/mips/xburst/stack.c b/libcpu/mips/xburst/stack.c deleted file mode 100644 index ceba8b9d9d..0000000000 --- a/libcpu/mips/xburst/stack.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * File : stack.c - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-07-07 Bernard porting to Ingenic CPU - */ -#include <rtthread.h> - -/** - * @addtogroup Ingenic - */ -/*@{*/ - -extern rt_uint32_t cp0_get_cause(void); -extern rt_uint32_t cp0_get_status(void); -extern rt_uint32_t cp0_get_hi(void); -extern rt_uint32_t cp0_get_lo(void); - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - static rt_uint32_t g_sr = 0; - - if (g_sr == 0) - { - g_sr = cp0_get_status(); - g_sr &= 0xfffffffe; - g_sr |= 0x0403; - } - - /** Start at stack top */ - stk = (rt_uint32_t *)stack_addr; - *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ - *(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */ - *(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */ - *(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */ - *(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */ - *(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */ - *(--stk) = (rt_uint32_t) texit; /* ra */ - *(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */ - *(--stk) = (rt_uint32_t) stack_addr; /* sp */ - *(--stk) = (rt_uint32_t) 0x0000001c; /* gp */ - *(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */ - *(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */ - *(--stk) = (rt_uint32_t) 0x00000019; /* t9 */ - *(--stk) = (rt_uint32_t) 0x00000018; /* t8 */ - *(--stk) = (rt_uint32_t) 0x00000017; /* s7 */ - *(--stk) = (rt_uint32_t) 0x00000016; /* s6 */ - *(--stk) = (rt_uint32_t) 0x00000015; /* s5 */ - *(--stk) = (rt_uint32_t) 0x00000014; /* s4 */ - *(--stk) = (rt_uint32_t) 0x00000013; /* s3 */ - *(--stk) = (rt_uint32_t) 0x00000012; /* s2 */ - *(--stk) = (rt_uint32_t) 0x00000011; /* s1 */ - *(--stk) = (rt_uint32_t) 0x00000010; /* s0 */ - *(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */ - *(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */ - *(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */ - *(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */ - *(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */ - *(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */ - *(--stk) = (rt_uint32_t) 0x00000009; /* t1 */ - *(--stk) = (rt_uint32_t) 0x00000008; /* t0 */ - *(--stk) = (rt_uint32_t) 0x00000007; /* a3 */ - *(--stk) = (rt_uint32_t) 0x00000006; /* a2 */ - *(--stk) = (rt_uint32_t) 0x00000005; /* a1 */ - *(--stk) = (rt_uint32_t) parameter; /* a0 */ - *(--stk) = (rt_uint32_t) 0x00000003; /* v1 */ - *(--stk) = (rt_uint32_t) 0x00000002; /* v0 */ - *(--stk) = (rt_uint32_t) 0x00000001; /* at */ - *(--stk) = (rt_uint32_t) 0x00000000; /* zero */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - -/*@}*/ diff --git a/libcpu/mips/xburst/stack.h b/libcpu/mips/xburst/stack.h deleted file mode 100644 index 5bb7206c11..0000000000 --- a/libcpu/mips/xburst/stack.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * File : stack.h - * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes -*/ - -#ifndef __STACK_H__ -#define __STACK_H__ - -#define SYSTEM_STACK 0x80003fe8 /* the kernel system stack address */ - -#endif diff --git a/libcpu/mips/xburst/start_gcc.S b/libcpu/mips/xburst/start_gcc.S deleted file mode 100644 index 322c2beae8..0000000000 --- a/libcpu/mips/xburst/start_gcc.S +++ /dev/null @@ -1,150 +0,0 @@ -/* - * File : start_gcc.S - * Change Logs: - * Date Author Notes - * 2010-05-17 swkyer first version - * 2010-09-04 bernard porting to Jz47xx - */ - -#include "../common/mips.inc" -#include "../common/stackframe.h" -#include "stack.h" - - .section ".start", "ax" - .set noreorder - - /* the program entry */ - .globl _start -_start: - .set noreorder - la ra, _start - - li t1, 0x00800000 - mtc0 t1, CP0_CAUSE - - /* init cp0 registers. */ - li t0, 0x0000FC00 /* BEV = 0 and mask all interrupt */ - mtc0 t0, CP0_STATUS - - /* setup stack pointer */ - li sp, SYSTEM_STACK - la gp, _gp - - /* init caches, assumes a 4way * 128set * 32byte I/D cache */ - mtc0 zero, CP0_TAGLO /* TAGLO reg */ - mtc0 zero, CP0_TAGHI /* TAGHI reg */ - li t0, 3 /* enable cache for kseg0 accesses */ - mtc0 t0, CP0_CONFIG /* CONFIG reg */ - la t0, 0x80000000 /* an idx op should use an unmappable address */ - ori t1, t0, 0x4000 /* 16kB cache */ - -_cache_loop: - cache 0x8, 0(t0) /* index store icache tag */ - cache 0x9, 0(t0) /* index store dcache tag */ - bne t0, t1, _cache_loop - addiu t0, t0, 0x20 /* 32 bytes per cache line */ - nop - - /* invalidate BTB */ - mfc0 t0, CP0_CONFIG - nop - ori t0, 2 - mtc0 t0, CP0_CONFIG - nop - - /* copy IRAM section */ - la t0, _iramcopy - la t1, _iramstart - la t2, _iramend -_iram_loop: - lw t3, 0(t0) - sw t3, 0(t1) - addiu t1, 4 - bne t1, t2, _iram_loop - addiu t0, 4 - /* clear bss */ - la t0, __bss_start - la t1, __bss_end -_clr_bss_loop: - sw zero, 0(t0) - bne t0, t1, _clr_bss_loop - addiu t0, t0, 4 - - /* jump to RT-Thread RTOS */ - jal rtthread_startup - nop - - /* restart, never die */ - j _start - nop - .set reorder - - .globl cp0_get_cause -cp0_get_cause: - mfc0 v0, CP0_CAUSE - jr ra - nop - - .globl cp0_get_status -cp0_get_status: - mfc0 v0, CP0_STATUS - jr ra - nop - - .globl cp0_get_hi -cp0_get_hi: - mfhi v0 - jr ra - nop - - .globl cp0_get_lo -cp0_get_lo: - mflo v0 - jr ra - nop - - .extern tlb_refill_handler - .extern cache_error_handler - - /* Exception Handler */ - /* 0x0 - TLB refill handler */ - .section .vectors.1, "ax", %progbits - j tlb_refill_handler - nop - - /* 0x100 - Cache error handler */ - .section .vectors.2, "ax", %progbits - j cache_error_handler - nop - - /* 0x180 - Exception/Interrupt handler */ - .section .vectors.3, "ax", %progbits - j _general_exception_handler - nop - - /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */ - .section .vectors.4, "ax", %progbits - j _irq_handler - nop - - .section .vectors, "ax", %progbits - .extern mips_irq_handle - - /* general exception handler */ -_general_exception_handler: - .set noreorder - mfc0 k1, CP0_CAUSE - andi k1, k1, 0x7c - srl k1, k1, 2 - lw k0, sys_exception_handlers(k1) - jr k0 - nop - .set reorder - - /* interrupt handler */ -_irq_handler: - .set noreorder - la k0, mips_irq_handle - jr k0 - nop - .set reorder diff --git a/libcpu/mips/xburst/x1000.h b/libcpu/mips/xburst/x1000.h deleted file mode 100644 index 71d11783a3..0000000000 --- a/libcpu/mips/xburst/x1000.h +++ /dev/null @@ -1,329 +0,0 @@ -/* - * File : x1000.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2015-11-19 Urey the first version - */ - -#ifndef X1000_H__ -#define X1000_H__ - -#ifndef __ASSEMBLY__ - -// typedef unsigned int size_t; -#define u64 unsigned long long -#define u32 unsigned int -#define u16 unsigned short -#define u8 unsigned char - -#define U64 unsigned long long -#define U32 unsigned int -#define U16 unsigned short -#define U8 unsigned char - -#define S64 signed long long -#define S32 int -#define S16 short int -#define S8 signed char - -#define cache_unroll(base,op) \ - __asm__ __volatile__(" \ - .set noreorder; \ - .set mips3; \ - cache %1, (%0); \ - .set mips0; \ - .set reorder" \ - : \ - : "r" (base), \ - "i" (op)); - -/* cpu pipeline flush */ -static inline void jz_sync(void) -{ - __asm__ volatile ("sync"); -} - -static inline void writeb(u8 value, u32 address) -{ - *((volatile u8 *) address) = value; -} -static inline void writew( u16 value, u32 address) -{ - *((volatile u16 *) address) = value; -} -static inline void writel(u32 value, u32 address) -{ - *((volatile u32 *) address) = value; -} - -static inline u8 readb(u32 address) -{ - return *((volatile u8 *)address); -} - -static inline u16 readw(u32 address) -{ - return *((volatile u16 *)address); -} - -static inline u32 readl(u32 address) -{ - return *((volatile u32 *)address); -} - -static inline void jz_writeb(u32 address, u8 value) -{ - *((volatile u8 *)address) = value; -} - -static inline void jz_writew(u32 address, u16 value) -{ - *((volatile u16 *)address) = value; -} - -static inline void jz_writel(u32 address, u32 value) -{ - *((volatile u32 *)address) = value; -} - -static inline u8 jz_readb(u32 address) -{ - return *((volatile u8 *)address); -} - -static inline u16 jz_readw(u32 address) -{ - return *((volatile u16 *)address); -} - -static inline u32 jz_readl(u32 address) -{ - return *((volatile u32 *)address); -} - -#define REG8(addr) *((volatile u8 *)(addr)) -#define REG16(addr) *((volatile u16 *)(addr)) -#define REG32(addr) *((volatile u32 *)(addr)) - -#define BIT(n) (0x01u << (n)) - -#else - -#define REG8(addr) (addr) -#define REG16(addr) (addr) -#define REG32(addr) (addr) - -#endif /* !ASSEMBLY */ - - -//---------------------------------------------------------------------- -// Register Definitions -// -/* AHB0 BUS Devices Base */ -#define HARB0_BASE 0xB3000000 -#define EMC_BASE 0xB3010000 -#define DDRC_BASE 0xB3020000 -#define MDMAC_BASE 0xB3030000 -#define LCD_BASE 0xB3050000 -#define TVE_BASE 0xB3050000 -#define SLCD_BASE 0xB3050000 -#define CIM_BASE 0xB3060000 -#define IPU_BASE 0xB3080000 -/* AHB1 BUS Devices Base */ -#define HARB1_BASE 0xB3200000 -#define DMAGP0_BASE 0xB3210000 -#define DMAGP1_BASE 0xB3220000 -#define DMAGP2_BASE 0xB3230000 -#define MC_BASE 0xB3250000 -#define ME_BASE 0xB3260000 -#define DEBLK_BASE 0xB3270000 -#define IDCT_BASE 0xB3280000 -#define CABAC_BASE 0xB3290000 -#define TCSM0_BASE 0xB32B0000 -#define TCSM1_BASE 0xB32C0000 -#define SRAM_BASE 0xB32D0000 -/* AHB2 BUS Devices Base */ -#define HARB2_BASE 0xB3400000 -#define NEMC_BASE 0xB3410000 -#define DMAC_BASE 0xB3420000 -#define UHC_BASE 0xB3430000 -#define UDC_BASE 0xB3440000 -#define GPS_BASE 0xB3480000 -#define ETHC_BASE 0xB34B0000 -#define BCH_BASE 0xB34D0000 -#define MSC0_BASE 0xB3450000 -#define MSC1_BASE 0xB3460000 -#define MSC2_BASE 0xB3470000 - -/* APB BUS Devices Base */ -#define CPM_BASE 0xB0000000 -#define INTC_BASE 0xB0001000 -#define TCU_BASE 0xB0002000 -#define WDT_BASE 0xB0002000 -#define OST_BASE 0xB2000000 /* OS Timer */ -#define RTC_BASE 0xB0003000 -#define GPIO_BASE 0xB0010000 -#define AIC_BASE 0xB0020000 -#define DMIC_BASE 0xB0021000 -#define ICDC_BASE 0xB0020000 -#define UART0_BASE 0xB0030000 -#define UART1_BASE 0xB0031000 -#define UART2_BASE 0xB0032000 -#define UART3_BASE 0xB0033000 -#define SCC_BASE 0xB0040000 -#define SSI0_BASE 0xB0043000 -#define SSI1_BASE 0xB0044000 -#define SSI2_BASE 0xB0045000 -#define I2C0_BASE 0xB0050000 -#define I2C1_BASE 0xB0051000 -#define PS2_BASE 0xB0060000 -#define SADC_BASE 0xB0070000 -#define OWI_BASE 0xB0072000 -#define TSSI_BASE 0xB0073000 - -/* NAND CHIP Base Address*/ -#define NEMC_CS1_IOBASE 0Xbb000000 -#define NEMC_CS2_IOBASE 0Xba000000 -#define NEMC_CS3_IOBASE 0Xb9000000 -#define NEMC_CS4_IOBASE 0Xb8000000 -#define NEMC_CS5_IOBASE 0Xb7000000 -#define NEMC_CS6_IOBASE 0Xb6000000 - -/********************************************************************************************************* -** WDT -*********************************************************************************************************/ -#define WDT_TDR (WDT_BASE + 0x00) -#define WDT_TCER (WDT_BASE + 0x04) -#define WDT_TCNT (WDT_BASE + 0x08) -#define WDT_TCSR (WDT_BASE + 0x0C) - -#define REG_WDT_TDR REG16(WDT_TDR) -#define REG_WDT_TCER REG8(WDT_TCER) -#define REG_WDT_TCNT REG16(WDT_TCNT) -#define REG_WDT_TCSR REG16(WDT_TCSR) - -#define WDT_TSCR_WDTSC (1 << 16) - -#define WDT_TCSR_PRESCALE_1 (0 << 3) -#define WDT_TCSR_PRESCALE_4 (1 << 3) -#define WDT_TCSR_PRESCALE_16 (2 << 3) -#define WDT_TCSR_PRESCALE_64 (3 << 3) -#define WDT_TCSR_PRESCALE_256 (4 << 3) -#define WDT_TCSR_PRESCALE_1024 (5 << 3) - -#define WDT_TCSR_EXT_EN (1 << 2) -#define WDT_TCSR_RTC_EN (1 << 1) -#define WDT_TCSR_PCK_EN (1 << 0) - -#define WDT_TCER_TCEN (1 << 0) - -/********************************************************************************************************* -** �ж�Դ -*********************************************************************************************************/ -/* INTC (Interrupt Controller) */ -#define INTC_ISR(n) (INTC_BASE + 0x00 + (n) * 0x20) -#define INTC_IMR(n) (INTC_BASE + 0x04 + (n) * 0x20) -#define INTC_IMSR(n) (INTC_BASE + 0x08 + (n) * 0x20) -#define INTC_IMCR(n) (INTC_BASE + 0x0c + (n) * 0x20) -#define INTC_IPR(n) (INTC_BASE + 0x10 + (n) * 0x20) - -#define REG_INTC_ISR(n) REG32(INTC_ISR((n))) -#define REG_INTC_IMR(n) REG32(INTC_IMR((n))) -#define REG_INTC_IMSR(n) REG32(INTC_IMSR((n))) -#define REG_INTC_IMCR(n) REG32(INTC_IMCR((n))) -#define REG_INTC_IPR(n) REG32(INTC_IPR((n))) - -// interrupt controller interrupts -#define IRQ_DMIC 0 -#define IRQ_AIC0 1 -#define IRQ_RESERVED2 2 -#define IRQ_RESERVED3 3 -#define IRQ_RESERVED4 4 -#define IRQ_RESERVED5 5 -#define IRQ_RESERVED6 6 -#define IRQ_SFC 7 -#define IRQ_SSI0 8 -#define IRQ_RESERVED9 9 -#define IRQ_PDMA 10 -#define IRQ_PDMAD 11 -#define IRQ_RESERVED12 12 -#define IRQ_RESERVED13 13 -#define IRQ_GPIO3 14 -#define IRQ_GPIO2 15 -#define IRQ_GPIO1 16 -#define IRQ_GPIO0 17 -#define IRQ_RESERVED18 18 -#define IRQ_RESERVED19 19 -#define IRQ_RESERVED20 20 -#define IRQ_OTG 21 -#define IRQ_RESERVED22 22 -#define IRQ_AES 23 -#define IRQ_RESERVED24 24 -#define IRQ_TCU2 25 -#define IRQ_TCU1 26 -#define IRQ_TCU0 27 -#define IRQ_RESERVED28 28 -#define IRQ_RESERVED29 29 -#define IRQ_CIM 30 -#define IRQ_LCD 31 -#define IRQ_RTC 32 -#define IRQ_RESERVED33 33 -#define IRQ_RESERVED34 34 -#define IRQ_RESERVED35 35 -#define IRQ_MSC1 36 -#define IRQ_MSC0 37 -#define IRQ_SCC 38 -#define IRQ_RESERVED39 39 -#define IRQ_PCM0 40 -#define IRQ_RESERVED41 41 -#define IRQ_RESERVED42 42 -#define IRQ_RESERVED43 43 -#define IRQ_HARB2 44 -#define IRQ_RESERVED45 45 -#define IRQ_HARB0 46 -#define IRQ_CPM 47 -#define IRQ_RESERVED48 48 -#define IRQ_UART2 49 -#define IRQ_UART1 50 -#define IRQ_UART0 51 -#define IRQ_DDR 52 -#define IRQ_RESERVED53 53 -#define IRQ_EFUSE 54 -#define IRQ_MAC 55 -#define IRQ_RESERVED56 56 -#define IRQ_RESERVED57 57 -#define IRQ_I2C2 58 -#define IRQ_I2C1 59 -#define IRQ_I2C0 60 -#define IRQ_PDMAM 61 -#define IRQ_JPEG 62 -#define IRQ_RESERVED63 63 - -#define IRQ_INTC_MAX 63 - -#ifndef __ASSEMBLY__ - -#define __intc_unmask_irq(n) (REG_INTC_IMCR((n)/32) = (1 << ((n)%32))) -#define __intc_mask_irq(n) (REG_INTC_IMSR((n)/32) = (1 << ((n)%32))) -#define __intc_ack_irq(n) (REG_INTC_IPR((n)/32) = (1 << ((n)%32))) /* A dummy ack, as the Pending Register is Read Only. Should we remove __intc_ack_irq() */ - -#endif /* !__ASSEMBLY__ */ - -#endif /* _JZ_M150_H_ */ diff --git a/libcpu/nios/SConscript b/libcpu/nios/SConscript new file mode 100644 index 0000000000..4f1441895c --- /dev/null +++ b/libcpu/nios/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +group = [] +list = os.listdir(cwd) + +# cpu porting code files +group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) + +Return('group') diff --git a/libcpu/nios/nios_ii/SConscript b/libcpu/nios/nios_ii/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/nios/nios_ii/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/ppc/SConscript b/libcpu/ppc/SConscript new file mode 100644 index 0000000000..640e46a4fb --- /dev/null +++ b/libcpu/ppc/SConscript @@ -0,0 +1,18 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +group = [] +list = os.listdir(cwd) + +# add common code files +group = group + SConscript(os.path.join('common', 'SConscript')) + +# cpu porting code files +group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) + +Return('group') diff --git a/libcpu/ppc/common/SConscript b/libcpu/ppc/common/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/ppc/common/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/ppc/common/ptrace.h b/libcpu/ppc/common/ptrace.h index d60e7fdcef..72ef31bfbc 100644 --- a/libcpu/ppc/common/ptrace.h +++ b/libcpu/ppc/common/ptrace.h @@ -21,20 +21,20 @@ #define PPC_REG unsigned long struct pt_regs { - PPC_REG gpr[32]; - PPC_REG nip; - PPC_REG msr; - PPC_REG orig_gpr3; /* Used for restarting system calls */ - PPC_REG ctr; - PPC_REG link; - PPC_REG xer; - PPC_REG ccr; - PPC_REG mq; /* 601 only (not used at present) */ - /* Used on APUS to hold IPL value. */ - PPC_REG trap; /* Reason for being here */ - PPC_REG dar; /* Fault registers */ - PPC_REG dsisr; - PPC_REG result; /* Result of a system call */ + PPC_REG gpr[32]; + PPC_REG nip; + PPC_REG msr; + PPC_REG orig_gpr3; /* Used for restarting system calls */ + PPC_REG ctr; + PPC_REG link; + PPC_REG xer; + PPC_REG ccr; + PPC_REG mq; /* 601 only (not used at present) */ + /* Used on APUS to hold IPL value. */ + PPC_REG trap; /* Reason for being here */ + PPC_REG dar; /* Fault registers */ + PPC_REG dsisr; + PPC_REG result; /* Result of a system call */ }__attribute__((packed)) CELL_STACK_FRAME_t; #endif diff --git a/libcpu/ppc/ppc405/SConscript b/libcpu/ppc/ppc405/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/ppc/ppc405/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/risc-v/SConscript b/libcpu/risc-v/SConscript new file mode 100644 index 0000000000..dece8b0423 --- /dev/null +++ b/libcpu/risc-v/SConscript @@ -0,0 +1,26 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +group = [] +list = os.listdir(cwd) + +# add common code files +if rtconfig.CPU == "e906" : + group = group +elif rtconfig.CPU == "nuclei" : + group = group +else : + group = group + SConscript(os.path.join(cwd, 'common', 'SConscript')) + +# cpu porting code files +if rtconfig.CPU == "e906" : + group = group + SConscript(os.path.join(cwd, rtconfig.VENDOR, rtconfig.CPU, 'SConscript')) +else : + group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript')) + +Return('group') diff --git a/libcpu/risc-v/bumblebee/SConscript b/libcpu/risc-v/bumblebee/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/risc-v/bumblebee/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/risc-v/bumblebee/interrupt_gcc.S b/libcpu/risc-v/bumblebee/interrupt_gcc.S new file mode 100644 index 0000000000..5a86e7d748 --- /dev/null +++ b/libcpu/risc-v/bumblebee/interrupt_gcc.S @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include "cpuport.h" + + .section .text.entry + .align 6 /* In ECLIC mode, the trap entry must be 64bytes aligned */ + .global irq_entry +irq_entry: + + /* save all from thread context */ + addi sp, sp, -32 * REGBYTES + + STORE x1, 1 * REGBYTES(sp) + li t0, 0x80 + STORE t0, 2 * REGBYTES(sp) + + STORE x4, 4 * REGBYTES(sp) + STORE x5, 5 * REGBYTES(sp) + STORE x6, 6 * REGBYTES(sp) + STORE x7, 7 * REGBYTES(sp) + STORE x8, 8 * REGBYTES(sp) + STORE x9, 9 * REGBYTES(sp) + STORE x10, 10 * REGBYTES(sp) + STORE x11, 11 * REGBYTES(sp) + STORE x12, 12 * REGBYTES(sp) + STORE x13, 13 * REGBYTES(sp) + STORE x14, 14 * REGBYTES(sp) + STORE x15, 15 * REGBYTES(sp) + STORE x16, 16 * REGBYTES(sp) + STORE x17, 17 * REGBYTES(sp) + STORE x18, 18 * REGBYTES(sp) + STORE x19, 19 * REGBYTES(sp) + STORE x20, 20 * REGBYTES(sp) + STORE x21, 21 * REGBYTES(sp) + STORE x22, 22 * REGBYTES(sp) + STORE x23, 23 * REGBYTES(sp) + STORE x24, 24 * REGBYTES(sp) + STORE x25, 25 * REGBYTES(sp) + STORE x26, 26 * REGBYTES(sp) + STORE x27, 27 * REGBYTES(sp) + STORE x28, 28 * REGBYTES(sp) + STORE x29, 29 * REGBYTES(sp) + STORE x30, 30 * REGBYTES(sp) + STORE x31, 31 * REGBYTES(sp) + + move s0, sp + + /* switch to interrupt stack */ + la sp, _sp + + /* interrupt handle */ + call rt_interrupt_enter + csrr a0, mcause + csrr a1, mepc + mv a2, sp + csrrw ra, 0x07ED, ra + call rt_interrupt_leave + + /* switch to from thread stack */ + move sp, s0 + + /* need to switch new thread */ + la s0, rt_thread_switch_interrupt_flag + lw s2, 0(s0) + beqz s2, spurious_interrupt + /* clear switch interrupt flag */ + sw zero, 0(s0) + + csrr a0, mepc + STORE a0, 0 * REGBYTES(sp) + + la s0, rt_interrupt_from_thread + LOAD s1, 0(s0) + STORE sp, 0(s1) + + la s0, rt_interrupt_to_thread + LOAD s1, 0(s0) + LOAD sp, 0(s1) + + LOAD a0, 0 * REGBYTES(sp) + csrw mepc, a0 + +spurious_interrupt: + LOAD x1, 1 * REGBYTES(sp) + + /* Remain in M-mode after mret */ + li t0, 0x00001800 + csrs mstatus, t0 + LOAD t0, 2 * REGBYTES(sp) + csrs mstatus, t0 + + LOAD x4, 4 * REGBYTES(sp) + LOAD x5, 5 * REGBYTES(sp) + LOAD x6, 6 * REGBYTES(sp) + LOAD x7, 7 * REGBYTES(sp) + LOAD x8, 8 * REGBYTES(sp) + LOAD x9, 9 * REGBYTES(sp) + LOAD x10, 10 * REGBYTES(sp) + LOAD x11, 11 * REGBYTES(sp) + LOAD x12, 12 * REGBYTES(sp) + LOAD x13, 13 * REGBYTES(sp) + LOAD x14, 14 * REGBYTES(sp) + LOAD x15, 15 * REGBYTES(sp) + LOAD x16, 16 * REGBYTES(sp) + LOAD x17, 17 * REGBYTES(sp) + LOAD x18, 18 * REGBYTES(sp) + LOAD x19, 19 * REGBYTES(sp) + LOAD x20, 20 * REGBYTES(sp) + LOAD x21, 21 * REGBYTES(sp) + LOAD x22, 22 * REGBYTES(sp) + LOAD x23, 23 * REGBYTES(sp) + LOAD x24, 24 * REGBYTES(sp) + LOAD x25, 25 * REGBYTES(sp) + LOAD x26, 26 * REGBYTES(sp) + LOAD x27, 27 * REGBYTES(sp) + LOAD x28, 28 * REGBYTES(sp) + LOAD x29, 29 * REGBYTES(sp) + LOAD x30, 30 * REGBYTES(sp) + LOAD x31, 31 * REGBYTES(sp) + + addi sp, sp, 32 * REGBYTES + mret diff --git a/libcpu/risc-v/common/SConscript b/libcpu/risc-v/common/SConscript new file mode 100644 index 0000000000..2f698f530a --- /dev/null +++ b/libcpu/risc-v/common/SConscript @@ -0,0 +1,12 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/risc-v/common/context_gcc.S b/libcpu/risc-v/common/context_gcc.S index 94ae5d9df4..5c9f05c4e8 100644 --- a/libcpu/risc-v/common/context_gcc.S +++ b/libcpu/risc-v/common/context_gcc.S @@ -6,10 +6,16 @@ * Change Logs: * Date Author Notes * 2018/10/28 Bernard The unify RISC-V porting implementation + * 2018/12/27 Jesven Add SMP support */ #include "cpuport.h" +#ifdef RT_USING_SMP +#define rt_hw_interrupt_disable rt_hw_local_irq_disable +#define rt_hw_interrupt_enable rt_hw_local_irq_enable +#endif + /* * rt_base_t rt_hw_interrupt_disable(void); */ @@ -27,60 +33,39 @@ rt_hw_interrupt_enable: ret /* - * void rt_hw_context_switch_to(rt_ubase_t to) + * #ifdef RT_USING_SMP + * void rt_hw_context_switch_to(rt_ubase_t to, stuct rt_thread *to_thread); + * #else + * void rt_hw_context_switch_to(rt_ubase_t to); + * #endif * a0 --> to + * a1 --> to_thread */ .globl rt_hw_context_switch_to rt_hw_context_switch_to: LOAD sp, (a0) - /* load epc from stack */ - LOAD a0, 0 * REGBYTES(sp) - csrw mepc, a0 - LOAD x1, 1 * REGBYTES(sp) - /* load mstatus from stack */ +#ifdef RT_USING_SMP + mv a0, a1 + jal rt_cpus_lock_status_restore +#endif LOAD a0, 2 * REGBYTES(sp) csrw mstatus, a0 - LOAD x4, 4 * REGBYTES(sp) - LOAD x5, 5 * REGBYTES(sp) - LOAD x6, 6 * REGBYTES(sp) - LOAD x7, 7 * REGBYTES(sp) - LOAD x8, 8 * REGBYTES(sp) - LOAD x9, 9 * REGBYTES(sp) - LOAD x10, 10 * REGBYTES(sp) - LOAD x11, 11 * REGBYTES(sp) - LOAD x12, 12 * REGBYTES(sp) - LOAD x13, 13 * REGBYTES(sp) - LOAD x14, 14 * REGBYTES(sp) - LOAD x15, 15 * REGBYTES(sp) - LOAD x16, 16 * REGBYTES(sp) - LOAD x17, 17 * REGBYTES(sp) - LOAD x18, 18 * REGBYTES(sp) - LOAD x19, 19 * REGBYTES(sp) - LOAD x20, 20 * REGBYTES(sp) - LOAD x21, 21 * REGBYTES(sp) - LOAD x22, 22 * REGBYTES(sp) - LOAD x23, 23 * REGBYTES(sp) - LOAD x24, 24 * REGBYTES(sp) - LOAD x25, 25 * REGBYTES(sp) - LOAD x26, 26 * REGBYTES(sp) - LOAD x27, 27 * REGBYTES(sp) - LOAD x28, 28 * REGBYTES(sp) - LOAD x29, 29 * REGBYTES(sp) - LOAD x30, 30 * REGBYTES(sp) - LOAD x31, 31 * REGBYTES(sp) - - addi sp, sp, 32 * REGBYTES - mret + j rt_hw_context_switch_exit /* - * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to) + * #ifdef RT_USING_SMP + * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread); + * #else + * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to); + * #endif + * * a0 --> from * a1 --> to + * a2 --> to_thread */ .globl rt_hw_context_switch rt_hw_context_switch: - /* saved from thread context * x1/ra -> sp(0) * x1/ra -> sp(1) @@ -136,16 +121,63 @@ save_mpie: */ LOAD sp, (a1) +#ifdef RT_USING_SMP + mv a0, a2 + jal rt_cpus_lock_status_restore +#endif /*RT_USING_SMP*/ + + j rt_hw_context_switch_exit + +#ifdef RT_USING_SMP +/* + * void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread); + * + * a0 --> context + * a1 --> from + * a2 --> to + * a3 --> to_thread + */ + .globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + + STORE a0, 0(a1) + + LOAD sp, 0(a2) + move a0, a3 + call rt_cpus_lock_status_restore + + j rt_hw_context_switch_exit + +#endif + +.global rt_hw_context_switch_exit +rt_hw_context_switch_exit: +#ifdef RT_USING_SMP +#ifdef RT_USING_SIGNALS + mv a0, sp + + csrr t0, mhartid + /* switch interrupt stack of current cpu */ + la sp, __stack_start__ + addi t1, t0, 1 + li t2, __STACKSIZE__ + mul t1, t1, t2 + add sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */ + + call rt_signal_check + mv sp, a0 +#endif +#endif /* resw ra to mepc */ - LOAD a1, 0 * REGBYTES(sp) - csrw mepc, a1 + LOAD a0, 0 * REGBYTES(sp) + csrw mepc, a0 + LOAD x1, 1 * REGBYTES(sp) - /* force to machin mode(MPP=11) */ - li a1, 0x00001800; - csrs mstatus, a1 - LOAD a1, 2 * REGBYTES(sp) - csrs mstatus, a1 + li t0, 0x00001800 + csrw mstatus, t0 + LOAD a0, 2 * REGBYTES(sp) + csrs mstatus, a0 LOAD x4, 4 * REGBYTES(sp) LOAD x5, 5 * REGBYTES(sp) diff --git a/libcpu/risc-v/common/cpuport.c b/libcpu/risc-v/common/cpuport.c index 2ad77b99c5..a44dc40f79 100644 --- a/libcpu/risc-v/common/cpuport.c +++ b/libcpu/risc-v/common/cpuport.c @@ -13,9 +13,11 @@ #include "cpuport.h" +#ifndef RT_USING_SMP volatile rt_ubase_t rt_interrupt_from_thread = 0; volatile rt_ubase_t rt_interrupt_to_thread = 0; volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0; +#endif struct rt_hw_stack_frame { @@ -93,6 +95,14 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, return stk; } +/* + * #ifdef RT_USING_SMP + * void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread); + * #else + * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to); + * #endif + */ +#ifndef RT_USING_SMP void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to) { if (rt_thread_switch_interrupt_flag == 0) @@ -103,3 +113,17 @@ void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to) return ; } +#endif /* end of RT_USING_SMP */ + +/** shutdown CPU */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} diff --git a/libcpu/risc-v/e310/SConscript b/libcpu/risc-v/e310/SConscript index 4e4bc0c3d9..b0ae20ba02 100644 --- a/libcpu/risc-v/e310/SConscript +++ b/libcpu/risc-v/e310/SConscript @@ -1,13 +1,14 @@ -Import('rtconfig') +# RT-Thread building script for component + from building import * +Import('rtconfig') + cwd = GetCurrentDir() -src = Glob('*.c') +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] +ASFLAGS = '' -if rtconfig.PLATFORM == 'gcc': - src += Glob('*_gcc.S') - -group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH) +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) Return('group') diff --git a/libcpu/risc-v/e310/interrupt_gcc.S b/libcpu/risc-v/e310/interrupt_gcc.S index 297851d71e..1eac7af90a 100644 --- a/libcpu/risc-v/e310/interrupt_gcc.S +++ b/libcpu/risc-v/e310/interrupt_gcc.S @@ -69,9 +69,9 @@ trap_entry: /* need to switch new thread */ la s0, rt_thread_switch_interrupt_flag - LOAD s2, 0(s0) + lw s2, 0(s0) beqz s2, spurious_interrupt - STORE zero, 0(s0) + sw zero, 0(s0) csrr a0, mepc STORE a0, 0 * REGBYTES(sp) diff --git a/libcpu/risc-v/k210/SConscript b/libcpu/risc-v/k210/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/risc-v/k210/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/risc-v/k210/cpuport_smp.c b/libcpu/risc-v/k210/cpuport_smp.c new file mode 100644 index 0000000000..8c57dfeafc --- /dev/null +++ b/libcpu/risc-v/k210/cpuport_smp.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/12/23 Bernard The first version + * 2018/12/27 Jesven Add secondary cpu boot + */ + +#include <rthw.h> +#include <rtthread.h> +#include <stdint.h> + +#include "board.h" +#include <encoding.h> +#include <clint.h> +#include <atomic.h> + +#ifdef RT_USING_SMP + +int rt_hw_cpu_id(void) +{ + return read_csr(mhartid); +} + +void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock) +{ + ((spinlock_t *)lock)->lock = 0; +} + +void rt_hw_spin_lock(rt_hw_spinlock_t *lock) +{ + spinlock_lock((spinlock_t *)lock); +} + +void rt_hw_spin_unlock(rt_hw_spinlock_t *lock) +{ + spinlock_unlock((spinlock_t *)lock); +} + +void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) +{ + int idx; + + for (idx = 0; idx < RT_CPUS_NR; idx ++) + { + if (cpu_mask & (1 << idx)) + { + clint_ipi_send(idx); + } + } +} + +extern rt_base_t secondary_boot_flag; +void rt_hw_secondary_cpu_up(void) +{ + mb(); + secondary_boot_flag = 0xa55a; +} + +extern void rt_hw_scondary_interrupt_init(void); +extern int rt_hw_tick_init(void); +extern int rt_hw_clint_ipi_enable(void); + +void secondary_cpu_c_start(void) +{ + rt_hw_spin_lock(&_cpus_lock); + + /* initialize interrupt controller */ + rt_hw_scondary_interrupt_init(); + + rt_hw_tick_init(); + + rt_hw_clint_ipi_enable(); + + rt_system_scheduler_start(); +} + +void rt_hw_secondary_cpu_idle_exec(void) +{ + asm volatile ("wfi"); +} +#endif /*RT_USING_SMP*/ diff --git a/libcpu/risc-v/k210/interrupt.c b/libcpu/risc-v/k210/interrupt.c new file mode 100644 index 0000000000..b582599daf --- /dev/null +++ b/libcpu/risc-v/k210/interrupt.c @@ -0,0 +1,397 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/01 Bernard The first version + * 2018/12/27 Jesven Change irq enable/disable to cpu0 + */ + +#include <rthw.h> + +#include "tick.h" + +#include <plic.h> +#include <clint.h> +#include <interrupt.h> + +#define CPU_NUM 2 +#define MAX_HANDLERS IRQN_MAX + +static struct rt_irq_desc irq_desc[MAX_HANDLERS]; + +static rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param) +{ + rt_kprintf("UN-handled interrupt %d occurred!!!\n", vector); + return RT_NULL; +} + +int rt_hw_clint_ipi_enable(void) +{ + /* Set the Machine-Software bit in MIE */ + set_csr(mie, MIP_MSIP); + return 0; +} + +int rt_hw_clint_ipi_disable(void) +{ + /* Clear the Machine-Software bit in MIE */ + clear_csr(mie, MIP_MSIP); + return 0; +} + +int rt_hw_plic_irq_enable(plic_irq_t irq_number) +{ + unsigned long core_id = 0; + + /* Check parameters */ + if (PLIC_NUM_SOURCES < irq_number || 0 > irq_number) + return -1; + /* Get current enable bit array by IRQ number */ + uint32_t current = plic->target_enables.target[core_id].enable[irq_number / 32]; + /* Set enable bit in enable bit array */ + current |= (uint32_t)1 << (irq_number % 32); + /* Write back the enable bit array */ + plic->target_enables.target[core_id].enable[irq_number / 32] = current; + return 0; +} + +int rt_hw_plic_irq_disable(plic_irq_t irq_number) +{ + unsigned long core_id = 0; + + /* Check parameters */ + if (PLIC_NUM_SOURCES < irq_number || 0 > irq_number) + return -1; + /* Get current enable bit array by IRQ number */ + uint32_t current = plic->target_enables.target[core_id].enable[irq_number / 32]; + /* Clear enable bit in enable bit array */ + current &= ~((uint32_t)1 << (irq_number % 32)); + /* Write back the enable bit array */ + plic->target_enables.target[core_id].enable[irq_number / 32] = current; + return 0; +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + int idx; + int cpuid; + + cpuid = current_coreid(); + + /* Disable all interrupts for the current core. */ + for (idx = 0; idx < ((PLIC_NUM_SOURCES + 32u) / 32u); idx ++) + plic->target_enables.target[cpuid].enable[idx] = 0; + + /* Set priorities to zero. */ + for (idx = 0; idx < PLIC_NUM_SOURCES; idx++) + plic->source_priorities.priority[idx] = 0; + + /* Set the threshold to zero. */ + plic->targets.target[cpuid].priority_threshold = 0; + + /* init exceptions table */ + for (idx = 0; idx < MAX_HANDLERS; idx++) + { + rt_hw_interrupt_mask(idx); + irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle; + irq_desc[idx].param = RT_NULL; +#ifdef RT_USING_INTERRUPT_INFO + rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default"); + irq_desc[idx].counter = 0; +#endif + } + + /* Enable machine external interrupts. */ + set_csr(mie, MIP_MEIP); +} + +void rt_hw_scondary_interrupt_init(void) +{ + int idx; + int cpuid; + + cpuid = current_coreid(); + + /* Disable all interrupts for the current core. */ + for (idx = 0; idx < ((PLIC_NUM_SOURCES + 32u) / 32u); idx ++) + plic->target_enables.target[cpuid].enable[idx] = 0; + + /* Set the threshold to zero. */ + plic->targets.target[cpuid].priority_threshold = 0; + + /* Enable machine external interrupts. */ + set_csr(mie, MIP_MEIP); +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + rt_hw_plic_irq_disable(vector); +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + plic_set_priority(vector, 1); + rt_hw_plic_irq_enable(vector); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if(vector < MAX_HANDLERS) + { + old_handler = irq_desc[vector].handler; + if (handler != RT_NULL) + { + irq_desc[vector].handler = (rt_isr_handler_t)handler; + irq_desc[vector].param = param; +#ifdef RT_USING_INTERRUPT_INFO + rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name); + irq_desc[vector].counter = 0; +#endif + } + } + + return old_handler; +} + +RT_WEAK +void plic_irq_handle(plic_irq_t irq) +{ + rt_kprintf("UN-handled interrupt %d occurred!!!\n", irq); + return ; +} + +uintptr_t handle_irq_m_ext(uintptr_t cause, uintptr_t epc) +{ + /* + * After the highest-priority pending interrupt is claimed by a target + * and the corresponding IP bit is cleared, other lower-priority + * pending interrupts might then become visible to the target, and so + * the PLIC EIP bit might not be cleared after a claim. The interrupt + * handler can check the local meip/heip/seip/ueip bits before exiting + * the handler, to allow more efficient service of other interrupts + * without first restoring the interrupted context and taking another + * interrupt trap. + */ + if (read_csr(mip) & MIP_MEIP) + { + /* Get current core id */ + uint64_t core_id = current_coreid(); + /* Get primitive interrupt enable flag */ + uint64_t ie_flag = read_csr(mie); + /* Get current IRQ num */ + uint32_t int_num = plic->targets.target[core_id].claim_complete; + /* Get primitive IRQ threshold */ + uint32_t int_threshold = plic->targets.target[core_id].priority_threshold; + /* Set new IRQ threshold = current IRQ threshold */ + plic->targets.target[core_id].priority_threshold = plic->source_priorities.priority[int_num]; + + /* Disable software interrupt and timer interrupt */ + clear_csr(mie, MIP_MTIP | MIP_MSIP); + + if (irq_desc[int_num].handler == (rt_isr_handler_t)rt_hw_interrupt_handle) + { + /* default handler, route to kendryte bsp plic driver */ + plic_irq_handle(int_num); + } + else if (irq_desc[int_num].handler) + { + irq_desc[int_num].handler(int_num, irq_desc[int_num].param); + } + + /* Perform IRQ complete */ + plic->targets.target[core_id].claim_complete = int_num; + /* Set MPIE and MPP flag used to MRET instructions restore MIE flag */ + set_csr(mstatus, MSTATUS_MPIE | MSTATUS_MPP); + /* Restore primitive interrupt enable flag */ + write_csr(mie, ie_flag); + /* Restore primitive IRQ threshold */ + plic->targets.target[core_id].priority_threshold = int_threshold; + } + + return epc; +} +struct exception_stack_frame +{ + uint64_t x1; + uint64_t x2; + uint64_t x3; + uint64_t x4; + uint64_t x5; + uint64_t x6; + uint64_t x7; + uint64_t x8; + uint64_t x9; + uint64_t x10; + uint64_t x11; + uint64_t x12; + uint64_t x13; + uint64_t x14; + uint64_t x15; + uint64_t x16; + uint64_t x17; + uint64_t x18; + uint64_t x19; + uint64_t x20; + uint64_t x21; + uint64_t x22; + uint64_t x23; + uint64_t x24; + uint64_t x25; + uint64_t x26; + uint64_t x27; + uint64_t x28; + uint64_t x29; + uint64_t x30; + uint64_t x31; +}; + +void print_stack_frame(uintptr_t * sp) +{ + struct exception_stack_frame * esf = (struct exception_stack_frame *)(sp+1); + + rt_kprintf("\n=================================================================\n"); + rt_kprintf("x1 (ra : Return address ) ==> 0x%08x%08x\n", esf->x1 >> 32 , esf->x1 & UINT32_MAX); + rt_kprintf("x2 (sp : Stack pointer ) ==> 0x%08x%08x\n", esf->x2 >> 32 , esf->x2 & UINT32_MAX); + rt_kprintf("x3 (gp : Global pointer ) ==> 0x%08x%08x\n", esf->x3 >> 32 , esf->x3 & UINT32_MAX); + rt_kprintf("x4 (tp : Thread pointer ) ==> 0x%08x%08x\n", esf->x4 >> 32 , esf->x4 & UINT32_MAX); + rt_kprintf("x5 (t0 : Temporary ) ==> 0x%08x%08x\n", esf->x5 >> 32 , esf->x5 & UINT32_MAX); + rt_kprintf("x6 (t1 : Temporary ) ==> 0x%08x%08x\n", esf->x6 >> 32 , esf->x6 & UINT32_MAX); + rt_kprintf("x7 (t2 : Temporary ) ==> 0x%08x%08x\n", esf->x7 >> 32 , esf->x7 & UINT32_MAX); + rt_kprintf("x8 (s0/fp: Save register,frame pointer ) ==> 0x%08x%08x\n", esf->x8 >> 32 , esf->x8 & UINT32_MAX); + rt_kprintf("x9 (s1 : Save register ) ==> 0x%08x%08x\n", esf->x9 >> 32 , esf->x9 & UINT32_MAX); + rt_kprintf("x10(a0 : Function argument,return value) ==> 0x%08x%08x\n", esf->x10 >> 32 , esf->x10 & UINT32_MAX); + rt_kprintf("x11(a1 : Function argument,return value) ==> 0x%08x%08x\n", esf->x11 >> 32 , esf->x11 & UINT32_MAX); + rt_kprintf("x12(a2 : Function argument ) ==> 0x%08x%08x\n", esf->x12 >> 32 , esf->x12 & UINT32_MAX); + rt_kprintf("x13(a3 : Function argument ) ==> 0x%08x%08x\n", esf->x13 >> 32 , esf->x13 & UINT32_MAX); + rt_kprintf("x14(a4 : Function argument ) ==> 0x%08x%08x\n", esf->x14 >> 32 , esf->x14 & UINT32_MAX); + rt_kprintf("x15(a5 : Function argument ) ==> 0x%08x%08x\n", esf->x15 >> 32 , esf->x15 & UINT32_MAX); + rt_kprintf("x16(a6 : Function argument ) ==> 0x%08x%08x\n", esf->x16 >> 32 , esf->x16 & UINT32_MAX); + rt_kprintf("x17(a7 : Function argument ) ==> 0x%08x%08x\n", esf->x17 >> 32 , esf->x17 & UINT32_MAX); + rt_kprintf("x18(s2 : Save register ) ==> 0x%08x%08x\n", esf->x18 >> 32 , esf->x18 & UINT32_MAX); + rt_kprintf("x19(s3 : Save register ) ==> 0x%08x%08x\n", esf->x19 >> 32 , esf->x19 & UINT32_MAX); + rt_kprintf("x20(s4 : Save register ) ==> 0x%08x%08x\n", esf->x20 >> 32 , esf->x20 & UINT32_MAX); + rt_kprintf("x21(s5 : Save register ) ==> 0x%08x%08x\n", esf->x21 >> 32 , esf->x21 & UINT32_MAX); + rt_kprintf("x22(s6 : Save register ) ==> 0x%08x%08x\n", esf->x22 >> 32 , esf->x22 & UINT32_MAX); + rt_kprintf("x23(s7 : Save register ) ==> 0x%08x%08x\n", esf->x23 >> 32 , esf->x23 & UINT32_MAX); + rt_kprintf("x24(s8 : Save register ) ==> 0x%08x%08x\n", esf->x24 >> 32 , esf->x24 & UINT32_MAX); + rt_kprintf("x25(s9 : Save register ) ==> 0x%08x%08x\n", esf->x25 >> 32 , esf->x25 & UINT32_MAX); + rt_kprintf("x26(s10 : Save register ) ==> 0x%08x%08x\n", esf->x26 >> 32 , esf->x26 & UINT32_MAX); + rt_kprintf("x27(s11 : Save register ) ==> 0x%08x%08x\n", esf->x27 >> 32 , esf->x27 & UINT32_MAX); + rt_kprintf("x28(t3 : Temporary ) ==> 0x%08x%08x\n", esf->x28 >> 32 , esf->x28 & UINT32_MAX); + rt_kprintf("x29(t4 : Temporary ) ==> 0x%08x%08x\n", esf->x29 >> 32 , esf->x29 & UINT32_MAX); + rt_kprintf("x30(t5 : Temporary ) ==> 0x%08x%08x\n", esf->x30 >> 32 , esf->x30 & UINT32_MAX); + rt_kprintf("x31(t6 : Temporary ) ==> 0x%08x%08x\n", esf->x31 >> 32 , esf->x31 & UINT32_MAX); + rt_kprintf("=================================================================\n"); +} + + +uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc, uintptr_t * sp) +{ + int cause = mcause & CAUSE_MACHINE_IRQ_REASON_MASK; + + if (mcause & (1UL << 63)) + { + switch (cause) + { + case IRQ_M_SOFT: + { + uint64_t core_id = current_coreid(); + + clint_ipi_clear(core_id); + rt_schedule(); + } + break; + case IRQ_M_EXT: + handle_irq_m_ext(mcause, epc); + break; + case IRQ_M_TIMER: + tick_isr(); + break; + } + } + else + { + rt_thread_t tid; + extern long list_thread(); + + rt_hw_interrupt_disable(); + + tid = rt_thread_self(); + rt_kprintf("\nException:\n"); + switch (cause) + { + case CAUSE_MISALIGNED_FETCH: + rt_kprintf("Instruction address misaligned"); + break; + case CAUSE_FAULT_FETCH: + rt_kprintf("Instruction access fault"); + break; + case CAUSE_ILLEGAL_INSTRUCTION: + rt_kprintf("Illegal instruction"); + break; + case CAUSE_BREAKPOINT: + rt_kprintf("Breakpoint"); + break; + case CAUSE_MISALIGNED_LOAD: + rt_kprintf("Load address misaligned"); + break; + case CAUSE_FAULT_LOAD: + rt_kprintf("Load access fault"); + break; + case CAUSE_MISALIGNED_STORE: + rt_kprintf("Store address misaligned"); + break; + case CAUSE_FAULT_STORE: + rt_kprintf("Store access fault"); + break; + case CAUSE_USER_ECALL: + rt_kprintf("Environment call from U-mode"); + break; + case CAUSE_SUPERVISOR_ECALL: + rt_kprintf("Environment call from S-mode"); + break; + case CAUSE_HYPERVISOR_ECALL: + rt_kprintf("Environment call from H-mode"); + break; + case CAUSE_MACHINE_ECALL: + rt_kprintf("Environment call from M-mode"); + break; + default: + rt_kprintf("Uknown exception : %08lX", cause); + break; + } + rt_kprintf("\n"); + print_stack_frame(sp); + rt_kprintf("exception pc => 0x%08x\n", epc); + rt_kprintf("current thread: %.*s\n", RT_NAME_MAX, tid->name); +#ifdef RT_USING_FINSH + list_thread(); +#endif + while(1); + } + + return epc; +} diff --git a/libcpu/risc-v/k210/interrupt_gcc.S b/libcpu/risc-v/k210/interrupt_gcc.S new file mode 100644 index 0000000000..0393ea51f8 --- /dev/null +++ b/libcpu/risc-v/k210/interrupt_gcc.S @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/02 Bernard The first version + * 2018/12/27 Jesven Add SMP schedule + */ + +#include "cpuport.h" + + .section .text.entry + .align 2 + .global trap_entry +trap_entry: + + /* save thread context to thread stack */ + addi sp, sp, -32 * REGBYTES + + STORE x1, 1 * REGBYTES(sp) + + csrr x1, mstatus + STORE x1, 2 * REGBYTES(sp) + + csrr x1, mepc + STORE x1, 0 * REGBYTES(sp) + + STORE x4, 4 * REGBYTES(sp) + STORE x5, 5 * REGBYTES(sp) + STORE x6, 6 * REGBYTES(sp) + STORE x7, 7 * REGBYTES(sp) + STORE x8, 8 * REGBYTES(sp) + STORE x9, 9 * REGBYTES(sp) + STORE x10, 10 * REGBYTES(sp) + STORE x11, 11 * REGBYTES(sp) + STORE x12, 12 * REGBYTES(sp) + STORE x13, 13 * REGBYTES(sp) + STORE x14, 14 * REGBYTES(sp) + STORE x15, 15 * REGBYTES(sp) + STORE x16, 16 * REGBYTES(sp) + STORE x17, 17 * REGBYTES(sp) + STORE x18, 18 * REGBYTES(sp) + STORE x19, 19 * REGBYTES(sp) + STORE x20, 20 * REGBYTES(sp) + STORE x21, 21 * REGBYTES(sp) + STORE x22, 22 * REGBYTES(sp) + STORE x23, 23 * REGBYTES(sp) + STORE x24, 24 * REGBYTES(sp) + STORE x25, 25 * REGBYTES(sp) + STORE x26, 26 * REGBYTES(sp) + STORE x27, 27 * REGBYTES(sp) + STORE x28, 28 * REGBYTES(sp) + STORE x29, 29 * REGBYTES(sp) + STORE x30, 30 * REGBYTES(sp) + STORE x31, 31 * REGBYTES(sp) + + /* switch to interrupt stack */ + move s0, sp + + /* get cpu id */ + csrr t0, mhartid + + /* switch interrupt stack of current cpu */ + la sp, __stack_start__ + addi t1, t0, 1 + li t2, __STACKSIZE__ + mul t1, t1, t2 + add sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */ + + /* handle interrupt */ + call rt_interrupt_enter + csrr a0, mcause + csrr a1, mepc + mv a2, s0 + call handle_trap + call rt_interrupt_leave + +#ifdef RT_USING_SMP + /* s0 --> sp */ + mv sp, s0 + mv a0, s0 + call rt_scheduler_do_irq_switch + j rt_hw_context_switch_exit + +#else + + /* switch to from_thread stack */ + move sp, s0 + + /* need to switch new thread */ + la s0, rt_thread_switch_interrupt_flag + lw s2, 0(s0) + beqz s2, spurious_interrupt + sw zero, 0(s0) + + la s0, rt_interrupt_from_thread + LOAD s1, 0(s0) + STORE sp, 0(s1) + + la s0, rt_interrupt_to_thread + LOAD s1, 0(s0) + LOAD sp, 0(s1) + +#endif + +spurious_interrupt: + j rt_hw_context_switch_exit diff --git a/libcpu/risc-v/k210/startup_gcc.S b/libcpu/risc-v/k210/startup_gcc.S new file mode 100644 index 0000000000..f5c0d8fa94 --- /dev/null +++ b/libcpu/risc-v/k210/startup_gcc.S @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/01 Bernard The first version + * 2018/12/27 Jesven Add SMP support + */ + +#define MSTATUS_FS 0x00006000U /* initial state of FPU */ +#include <cpuport.h> + + .global _start + .section ".start", "ax" +_start: + j 1f + .word 0xdeadbeef + .align 3 + .global g_wake_up + g_wake_up: + .dword 1 + .dword 0 +1: + csrw mideleg, 0 + csrw medeleg, 0 + csrw mie, 0 + csrw mip, 0 + la t0, trap_entry + csrw mtvec, t0 + + li x1, 0 + li x2, 0 + li x3, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10,0 + li x11,0 + li x12,0 + li x13,0 + li x14,0 + li x15,0 + li x16,0 + li x17,0 + li x18,0 + li x19,0 + li x20,0 + li x21,0 + li x22,0 + li x23,0 + li x24,0 + li x25,0 + li x26,0 + li x27,0 + li x28,0 + li x29,0 + li x30,0 + li x31,0 + + /* set to initial state of FPU and disable interrupt */ + li t0, MSTATUS_FS + csrs mstatus, t0 + + fssr x0 + fmv.d.x f0, x0 + fmv.d.x f1, x0 + fmv.d.x f2, x0 + fmv.d.x f3, x0 + fmv.d.x f4, x0 + fmv.d.x f5, x0 + fmv.d.x f6, x0 + fmv.d.x f7, x0 + fmv.d.x f8, x0 + fmv.d.x f9, x0 + fmv.d.x f10,x0 + fmv.d.x f11,x0 + fmv.d.x f12,x0 + fmv.d.x f13,x0 + fmv.d.x f14,x0 + fmv.d.x f15,x0 + fmv.d.x f16,x0 + fmv.d.x f17,x0 + fmv.d.x f18,x0 + fmv.d.x f19,x0 + fmv.d.x f20,x0 + fmv.d.x f21,x0 + fmv.d.x f22,x0 + fmv.d.x f23,x0 + fmv.d.x f24,x0 + fmv.d.x f25,x0 + fmv.d.x f26,x0 + fmv.d.x f27,x0 + fmv.d.x f28,x0 + fmv.d.x f29,x0 + fmv.d.x f30,x0 + fmv.d.x f31,x0 + +.option push +.option norelax + la gp, __global_pointer$ +.option pop + + /* get cpu id */ + csrr a0, mhartid + + la sp, __stack_start__ + addi t1, a0, 1 + li t2, __STACKSIZE__ + mul t1, t1, t2 + add sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */ + + /* other cpu core, jump to cpu entry directly */ + bnez a0, secondary_cpu_entry + j primary_cpu_entry + +secondary_cpu_entry: +#ifdef RT_USING_SMP + la a0, secondary_boot_flag + ld a0, 0(a0) + li a1, 0xa55a + beq a0, a1, secondary_cpu_c_start +#endif + j secondary_cpu_entry + +#ifdef RT_USING_SMP +.data +.global secondary_boot_flag +.align 3 +secondary_boot_flag: + .dword 0 +#endif diff --git a/libcpu/risc-v/k210/tick.c b/libcpu/risc-v/k210/tick.c new file mode 100644 index 0000000000..144f7f1fff --- /dev/null +++ b/libcpu/risc-v/k210/tick.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/28 Bernard The unify RISC-V porting code. + */ + +#include <rthw.h> +#include <rtthread.h> + +#include <encoding.h> +#include <clint.h> +#include <sysctl.h> + +static volatile unsigned long tick_cycles = 0; +int tick_isr(void) +{ + uint64_t core_id = current_coreid(); + + clint->mtimecmp[core_id] += tick_cycles; + rt_tick_increase(); + + return 0; +} + +/* Sets and enable the timer interrupt */ +int rt_hw_tick_init(void) +{ + /* Read core id */ + unsigned long core_id = current_coreid(); + unsigned long interval = 1000/RT_TICK_PER_SECOND; + + /* Clear the Machine-Timer bit in MIE */ + clear_csr(mie, MIP_MTIP); + + /* calculate the tick cycles */ + tick_cycles = interval * sysctl_clock_get_freq(SYSCTL_CLOCK_CPU) / CLINT_CLOCK_DIV / 1000ULL - 1; + /* Set mtimecmp by core id */ + clint->mtimecmp[core_id] = clint->mtime + tick_cycles; + + /* Enable the Machine-Timer bit in MIE */ + set_csr(mie, MIP_MTIP); + + return 0; +} diff --git a/libcpu/risc-v/k210/tick.h b/libcpu/risc-v/k210/tick.h new file mode 100644 index 0000000000..0821004263 --- /dev/null +++ b/libcpu/risc-v/k210/tick.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018/10/28 Bernard The unify RISC-V porting code. + */ + +#ifndef TICK_H__ +#define TICK_H__ + +int tick_isr(void); +int rt_hw_tick_init(void); + +#endif diff --git a/libcpu/risc-v/nuclei/SConscript b/libcpu/risc-v/nuclei/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/risc-v/nuclei/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/risc-v/nuclei/context_gcc.S b/libcpu/risc-v/nuclei/context_gcc.S new file mode 100644 index 0000000000..fda453940d --- /dev/null +++ b/libcpu/risc-v/nuclei/context_gcc.S @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2019-Present Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/03/26 Huaqi First Nuclei RISC-V porting implementation + */ + +#include "riscv_encoding.h" + +#ifndef __riscv_32e +#define RT_SAVED_REGNUM 30 +#else +#define RT_SAVED_REGNUM 14 +#endif + +#define RT_CONTEXT_SIZE (RT_SAVED_REGNUM * REGBYTES) + + .extern rt_interrupt_from_thread + .extern rt_interrupt_to_thread + + +.section .text + + +/* + * void rt_hw_context_switch_to(rt_ubase_t to); + * a0 --> to_thread + */ + .globl rt_hw_context_switch_to + +/* Start the first task. This also clears the bit that indicates the FPU is + in use in case the FPU was used before the scheduler was started - which + would otherwise result in the unnecessary leaving of space in the stack + for lazy saving of FPU registers. */ +.align 3 +rt_hw_context_switch_to: + /* Setup Interrupt Stack using + The stack that was used by main() + before the scheduler is started is + no longer required after the scheduler is started. + Interrupt stack pointer is stored in CSR_MSCRATCH */ + la t0, _sp + csrw CSR_MSCRATCH, t0 + LOAD sp, 0x0(a0) /* Read sp from first TCB member(a0) */ + + /* Pop PC from stack and set MEPC */ + LOAD t0, 0 * REGBYTES(sp) + csrw CSR_MEPC, t0 + /* Pop mstatus from stack and set it */ + LOAD t0, (RT_SAVED_REGNUM - 1) * REGBYTES(sp) + csrw CSR_MSTATUS, t0 + /* Interrupt still disable here */ + /* Restore Registers from Stack */ + LOAD x1, 1 * REGBYTES(sp) /* RA */ + LOAD x5, 2 * REGBYTES(sp) + LOAD x6, 3 * REGBYTES(sp) + LOAD x7, 4 * REGBYTES(sp) + LOAD x8, 5 * REGBYTES(sp) + LOAD x9, 6 * REGBYTES(sp) + LOAD x10, 7 * REGBYTES(sp) + LOAD x11, 8 * REGBYTES(sp) + LOAD x12, 9 * REGBYTES(sp) + LOAD x13, 10 * REGBYTES(sp) + LOAD x14, 11 * REGBYTES(sp) + LOAD x15, 12 * REGBYTES(sp) +#ifndef __riscv_32e + LOAD x16, 13 * REGBYTES(sp) + LOAD x17, 14 * REGBYTES(sp) + LOAD x18, 15 * REGBYTES(sp) + LOAD x19, 16 * REGBYTES(sp) + LOAD x20, 17 * REGBYTES(sp) + LOAD x21, 18 * REGBYTES(sp) + LOAD x22, 19 * REGBYTES(sp) + LOAD x23, 20 * REGBYTES(sp) + LOAD x24, 21 * REGBYTES(sp) + LOAD x25, 22 * REGBYTES(sp) + LOAD x26, 23 * REGBYTES(sp) + LOAD x27, 24 * REGBYTES(sp) + LOAD x28, 25 * REGBYTES(sp) + LOAD x29, 26 * REGBYTES(sp) + LOAD x30, 27 * REGBYTES(sp) + LOAD x31, 28 * REGBYTES(sp) +#endif + + addi sp, sp, RT_CONTEXT_SIZE + + mret + +.align 2 +.global eclic_msip_handler +eclic_msip_handler: + addi sp, sp, -RT_CONTEXT_SIZE + STORE x1, 1 * REGBYTES(sp) /* RA */ + STORE x5, 2 * REGBYTES(sp) + STORE x6, 3 * REGBYTES(sp) + STORE x7, 4 * REGBYTES(sp) + STORE x8, 5 * REGBYTES(sp) + STORE x9, 6 * REGBYTES(sp) + STORE x10, 7 * REGBYTES(sp) + STORE x11, 8 * REGBYTES(sp) + STORE x12, 9 * REGBYTES(sp) + STORE x13, 10 * REGBYTES(sp) + STORE x14, 11 * REGBYTES(sp) + STORE x15, 12 * REGBYTES(sp) +#ifndef __riscv_32e + STORE x16, 13 * REGBYTES(sp) + STORE x17, 14 * REGBYTES(sp) + STORE x18, 15 * REGBYTES(sp) + STORE x19, 16 * REGBYTES(sp) + STORE x20, 17 * REGBYTES(sp) + STORE x21, 18 * REGBYTES(sp) + STORE x22, 19 * REGBYTES(sp) + STORE x23, 20 * REGBYTES(sp) + STORE x24, 21 * REGBYTES(sp) + STORE x25, 22 * REGBYTES(sp) + STORE x26, 23 * REGBYTES(sp) + STORE x27, 24 * REGBYTES(sp) + STORE x28, 25 * REGBYTES(sp) + STORE x29, 26 * REGBYTES(sp) + STORE x30, 27 * REGBYTES(sp) + STORE x31, 28 * REGBYTES(sp) +#endif + /* Push mstatus to stack */ + csrr t0, CSR_MSTATUS + STORE t0, (RT_SAVED_REGNUM - 1) * REGBYTES(sp) + + /* Push additional registers */ + + /* Store sp to task stack */ + LOAD t0, rt_interrupt_from_thread + STORE sp, 0(t0) + + csrr t0, CSR_MEPC + STORE t0, 0(sp) + + jal rt_hw_taskswitch + + /* Switch task context */ + LOAD t0, rt_interrupt_to_thread + LOAD sp, 0x0(t0) + + /* Pop PC from stack and set MEPC */ + LOAD t0, 0 * REGBYTES(sp) + csrw CSR_MEPC, t0 + + /* Pop additional registers */ + + /* Pop mstatus from stack and set it */ + LOAD t0, (RT_SAVED_REGNUM - 1) * REGBYTES(sp) + csrw CSR_MSTATUS, t0 + /* Interrupt still disable here */ + /* Restore Registers from Stack */ + LOAD x1, 1 * REGBYTES(sp) /* RA */ + LOAD x5, 2 * REGBYTES(sp) + LOAD x6, 3 * REGBYTES(sp) + LOAD x7, 4 * REGBYTES(sp) + LOAD x8, 5 * REGBYTES(sp) + LOAD x9, 6 * REGBYTES(sp) + LOAD x10, 7 * REGBYTES(sp) + LOAD x11, 8 * REGBYTES(sp) + LOAD x12, 9 * REGBYTES(sp) + LOAD x13, 10 * REGBYTES(sp) + LOAD x14, 11 * REGBYTES(sp) + LOAD x15, 12 * REGBYTES(sp) +#ifndef __riscv_32e + LOAD x16, 13 * REGBYTES(sp) + LOAD x17, 14 * REGBYTES(sp) + LOAD x18, 15 * REGBYTES(sp) + LOAD x19, 16 * REGBYTES(sp) + LOAD x20, 17 * REGBYTES(sp) + LOAD x21, 18 * REGBYTES(sp) + LOAD x22, 19 * REGBYTES(sp) + LOAD x23, 20 * REGBYTES(sp) + LOAD x24, 21 * REGBYTES(sp) + LOAD x25, 22 * REGBYTES(sp) + LOAD x26, 23 * REGBYTES(sp) + LOAD x27, 24 * REGBYTES(sp) + LOAD x28, 25 * REGBYTES(sp) + LOAD x29, 26 * REGBYTES(sp) + LOAD x30, 27 * REGBYTES(sp) + LOAD x31, 28 * REGBYTES(sp) +#endif + + addi sp, sp, RT_CONTEXT_SIZE + mret diff --git a/libcpu/risc-v/nuclei/cpuport.c b/libcpu/risc-v/nuclei/cpuport.c new file mode 100644 index 0000000000..e456438f70 --- /dev/null +++ b/libcpu/risc-v/nuclei/cpuport.c @@ -0,0 +1,259 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2019-Present Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/03/26 Huaqi Nuclei RISC-V Core porting code. + */ + +#include <rthw.h> +#include <rtthread.h> +#include <sys/types.h> +#include <unistd.h> + +#include "cpuport.h" + +#define SYSTICK_TICK_CONST (SOC_TIMER_FREQ / RT_TICK_PER_SECOND) + +/* Interrupt level for kernel systimer interrupt and software timer interrupt */ +#define RT_KERNEL_INTERRUPT_LEVEL 0 + +/* Initial CSR MSTATUS value when thread created */ +#define RT_INITIAL_MSTATUS (MSTATUS_MPP | MSTATUS_MPIE | MSTATUS_FS_INITIAL) + +/** + * @brief from thread used interrupt context switch + * + */ +volatile rt_ubase_t rt_interrupt_from_thread = 0; +/** + * @brief to thread used interrupt context switch + * + */ +volatile rt_ubase_t rt_interrupt_to_thread = 0; +/** + * @brief flag to indicate context switch in interrupt or not + * + */ +volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0; + +/** + * @brief thread stack frame of saved context + * + */ +struct rt_hw_stack_frame +{ + rt_ubase_t epc; /*!< epc - epc - program counter */ + rt_ubase_t ra; /*!< x1 - ra - return address for jumps */ + rt_ubase_t t0; /*!< x5 - t0 - temporary register 0 */ + rt_ubase_t t1; /*!< x6 - t1 - temporary register 1 */ + rt_ubase_t t2; /*!< x7 - t2 - temporary register 2 */ + rt_ubase_t s0_fp; /*!< x8 - s0/fp - saved register 0 or frame pointer */ + rt_ubase_t s1; /*!< x9 - s1 - saved register 1 */ + rt_ubase_t a0; /*!< x10 - a0 - return value or function argument 0 */ + rt_ubase_t a1; /*!< x11 - a1 - return value or function argument 1 */ + rt_ubase_t a2; /*!< x12 - a2 - function argument 2 */ + rt_ubase_t a3; /*!< x13 - a3 - function argument 3 */ + rt_ubase_t a4; /*!< x14 - a4 - function argument 4 */ + rt_ubase_t a5; /*!< x15 - a5 - function argument 5 */ +#ifndef __riscv_32e + rt_ubase_t a6; /*!< x16 - a6 - function argument 6 */ + rt_ubase_t a7; /*!< x17 - s7 - function argument 7 */ + rt_ubase_t s2; /*!< x18 - s2 - saved register 2 */ + rt_ubase_t s3; /*!< x19 - s3 - saved register 3 */ + rt_ubase_t s4; /*!< x20 - s4 - saved register 4 */ + rt_ubase_t s5; /*!< x21 - s5 - saved register 5 */ + rt_ubase_t s6; /*!< x22 - s6 - saved register 6 */ + rt_ubase_t s7; /*!< x23 - s7 - saved register 7 */ + rt_ubase_t s8; /*!< x24 - s8 - saved register 8 */ + rt_ubase_t s9; /*!< x25 - s9 - saved register 9 */ + rt_ubase_t s10; /*!< x26 - s10 - saved register 10 */ + rt_ubase_t s11; /*!< x27 - s11 - saved register 11 */ + rt_ubase_t t3; /*!< x28 - t3 - temporary register 3 */ + rt_ubase_t t4; /*!< x29 - t4 - temporary register 4 */ + rt_ubase_t t5; /*!< x30 - t5 - temporary register 5 */ + rt_ubase_t t6; /*!< x31 - t6 - temporary register 6 */ +#endif + rt_ubase_t mstatus; /*!< - machine status register */ +}; + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) +{ + struct rt_hw_stack_frame *frame; + rt_uint8_t *stk; + int i; + + stk = stack_addr + sizeof(rt_ubase_t); + stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES); + stk -= sizeof(struct rt_hw_stack_frame); + + frame = (struct rt_hw_stack_frame *)stk; + + for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++) + { + ((rt_ubase_t *)frame)[i] = 0xdeadbeef; + } + + frame->ra = (rt_ubase_t)texit; + frame->a0 = (rt_ubase_t)parameter; + frame->epc = (rt_ubase_t)tentry; + + frame->mstatus = RT_INITIAL_MSTATUS; + + return stk; +} + +/** + * @brief Do rt-thread context switch in interrupt context + * + * @param from thread sp of from thread + * @param to thread sp of to thread + */ +void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to) +{ + if (rt_thread_switch_interrupt_flag == 0) + rt_interrupt_from_thread = from; + + rt_interrupt_to_thread = to; + rt_thread_switch_interrupt_flag = 1; + RT_YIELD(); +} + +/** + * @brief Do rt-thread context switch in task context + * + * @param from thread sp of from thread + * @param to thread sp of to thread + */ +void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to) +{ + rt_interrupt_from_thread = from; + rt_interrupt_to_thread = to; + RT_YIELD(); +} + +/** + * @brief shutdown CPU + * + */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} + +/** + * @brief Do extra task switch code + * + * @details + * + * - Clear software timer interrupt request flag + * - clear rt_thread_switch_interrupt_flag to 0 + */ +void rt_hw_taskswitch(void) +{ + /* Clear Software IRQ, A MUST */ + SysTimer_ClearSWIRQ(); + rt_thread_switch_interrupt_flag = 0; +} + +/** + * @brief Setup systimer and software timer interrupt + * + * @details + * + * - Set Systimer interrupt as NON-VECTOR interrupt with lowest interrupt level + * - Set software timer interrupt as VECTOR interrupt with lowest interrupt level + * - Enable these two interrupts + */ +void rt_hw_ticksetup(void) +{ + uint64_t ticks = SYSTICK_TICK_CONST; + + /* Make SWI and SysTick the lowest priority interrupts. */ + /* Stop and clear the SysTimer. SysTimer as Non-Vector Interrupt */ + SysTick_Config(ticks); + ECLIC_DisableIRQ(SysTimer_IRQn); + ECLIC_SetLevelIRQ(SysTimer_IRQn, RT_KERNEL_INTERRUPT_LEVEL); + ECLIC_SetShvIRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT); + ECLIC_EnableIRQ(SysTimer_IRQn); + + /* Set SWI interrupt level to lowest level/priority, SysTimerSW as Vector Interrupt */ + ECLIC_SetShvIRQ(SysTimerSW_IRQn, ECLIC_VECTOR_INTERRUPT); + ECLIC_SetLevelIRQ(SysTimerSW_IRQn, RT_KERNEL_INTERRUPT_LEVEL); + ECLIC_EnableIRQ(SysTimerSW_IRQn); +} + +/** + * systimer interrupt handler eclic_mtip_handler + * is hard coded in startup_<Device>.S + * We define SysTick_Handler as eclic_mtip_handler + * for easy understanding + */ +#define SysTick_Handler eclic_mtip_handler + +/** + * @brief This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* Reload systimer */ + SysTick_Reload(SYSTICK_TICK_CONST); + + /* enter interrupt */ + rt_interrupt_enter(); + + /* tick increase */ + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * @brief Disable cpu interrupt + * + * @details + * + * - Disable cpu interrupt by clear MIE bit in MSTATUS + * - Return the previous value in MSTATUS before clear MIE bit + * + * @return the previous value in MSTATUS before clear MIE bit + */ +rt_base_t rt_hw_interrupt_disable(void) +{ + return __RV_CSR_READ_CLEAR(CSR_MSTATUS, MSTATUS_MIE); +} + +/** + * @brief Restore previous saved interrupt status + * + * @param level previous saved MSTATUS value + */ +void rt_hw_interrupt_enable(rt_base_t level) +{ + __RV_CSR_WRITE(CSR_MSTATUS, level); +} diff --git a/libcpu/risc-v/nuclei/cpuport.h b/libcpu/risc-v/nuclei/cpuport.h new file mode 100644 index 0000000000..3736f0078a --- /dev/null +++ b/libcpu/risc-v/nuclei/cpuport.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2019-Present Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/03/26 hqfang Nuclei RISC-V Core porting code. + */ + +#ifndef __CPUPORT_H__ +#define __CPUPORT_H__ + +#include <rtconfig.h> +#include <nuclei_sdk_soc.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Scheduler utilities. */ +#define RT_YIELD() \ +{ \ + /* Set a software interrupt(SWI) request to request a context switch. */ \ + SysTimer_SetSWIRQ(); \ + /* Barriers are normally not required but do ensure the code is completely \ + within the specified behaviour for the architecture. */ \ + __RWMB(); \ + __FENCE_I(); \ +} + +extern void rt_hw_ticksetup(void); +extern void rt_hw_taskswitch(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libcpu/risc-v/nuclei/interrupt_gcc.S b/libcpu/risc-v/nuclei/interrupt_gcc.S new file mode 100644 index 0000000000..02a3e3e760 --- /dev/null +++ b/libcpu/risc-v/nuclei/interrupt_gcc.S @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2019-Present Nuclei Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/03/26 hqfang First Nuclei RISC-V porting implementation + */ + +#include "riscv_encoding.h" + +.section .text.entry +.align 8 + +/** + * \brief Global interrupt disabled + * \details + * This function disable global interrupt. + * \remarks + * - All the interrupt requests will be ignored by CPU. + */ +.macro DISABLE_MIE + csrc CSR_MSTATUS, MSTATUS_MIE +.endm + +/** + * \brief Macro for context save + * \details + * This macro save ABI defined caller saved registers in the stack. + * \remarks + * - This Macro could use to save context when you enter to interrupt + * or exception +*/ +/* Save caller registers */ +.macro SAVE_CONTEXT + csrrw sp, CSR_MSCRATCHCSWL, sp + /* Allocate stack space for context saving */ +#ifndef __riscv_32e + addi sp, sp, -20*REGBYTES +#else + addi sp, sp, -14*REGBYTES +#endif /* __riscv_32e */ + + STORE x1, 0*REGBYTES(sp) + STORE x4, 1*REGBYTES(sp) + STORE x5, 2*REGBYTES(sp) + STORE x6, 3*REGBYTES(sp) + STORE x7, 4*REGBYTES(sp) + STORE x10, 5*REGBYTES(sp) + STORE x11, 6*REGBYTES(sp) + STORE x12, 7*REGBYTES(sp) + STORE x13, 8*REGBYTES(sp) + STORE x14, 9*REGBYTES(sp) + STORE x15, 10*REGBYTES(sp) +#ifndef __riscv_32e + STORE x16, 14*REGBYTES(sp) + STORE x17, 15*REGBYTES(sp) + STORE x28, 16*REGBYTES(sp) + STORE x29, 17*REGBYTES(sp) + STORE x30, 18*REGBYTES(sp) + STORE x31, 19*REGBYTES(sp) +#endif /* __riscv_32e */ +.endm + +/** + * \brief Macro for restore caller registers + * \details + * This macro restore ABI defined caller saved registers from stack. + * \remarks + * - You could use this macro to restore context before you want return + * from interrupt or exeception + */ +/* Restore caller registers */ +.macro RESTORE_CONTEXT + LOAD x1, 0*REGBYTES(sp) + LOAD x4, 1*REGBYTES(sp) + LOAD x5, 2*REGBYTES(sp) + LOAD x6, 3*REGBYTES(sp) + LOAD x7, 4*REGBYTES(sp) + LOAD x10, 5*REGBYTES(sp) + LOAD x11, 6*REGBYTES(sp) + LOAD x12, 7*REGBYTES(sp) + LOAD x13, 8*REGBYTES(sp) + LOAD x14, 9*REGBYTES(sp) + LOAD x15, 10*REGBYTES(sp) +#ifndef __riscv_32e + LOAD x16, 14*REGBYTES(sp) + LOAD x17, 15*REGBYTES(sp) + LOAD x28, 16*REGBYTES(sp) + LOAD x29, 17*REGBYTES(sp) + LOAD x30, 18*REGBYTES(sp) + LOAD x31, 19*REGBYTES(sp) + + /* De-allocate the stack space */ + addi sp, sp, 20*REGBYTES +#else + /* De-allocate the stack space */ + addi sp, sp, 14*REGBYTES +#endif /* __riscv_32e */ + csrrw sp, CSR_MSCRATCHCSWL, sp +.endm + +/** + * \brief Macro for save necessary CSRs to stack + * \details + * This macro store MCAUSE, MEPC, MSUBM to stack. + */ +.macro SAVE_CSR_CONTEXT + /* Store CSR mcause to stack using pushmcause */ + csrrwi x0, CSR_PUSHMCAUSE, 11 + /* Store CSR mepc to stack using pushmepc */ + csrrwi x0, CSR_PUSHMEPC, 12 + /* Store CSR msub to stack using pushmsub */ + csrrwi x0, CSR_PUSHMSUBM, 13 +.endm + +/** + * \brief Macro for restore necessary CSRs from stack + * \details + * This macro restore MSUBM, MEPC, MCAUSE from stack. + */ +.macro RESTORE_CSR_CONTEXT + LOAD x5, 13*REGBYTES(sp) + csrw CSR_MSUBM, x5 + LOAD x5, 12*REGBYTES(sp) + csrw CSR_MEPC, x5 + LOAD x5, 11*REGBYTES(sp) + csrw CSR_MCAUSE, x5 +.endm + +/** + * \brief Exception/NMI Entry + * \details + * This function provide common entry functions for exception/nmi. + * \remarks + * This function provide a default exception/nmi entry. + * ABI defined caller save register and some CSR registers + * to be saved before enter interrupt handler and be restored before return. + */ +.section .text.trap +/* In CLIC mode, the exeception entry must be 64bytes aligned */ +.align 6 +.global exc_entry +exc_entry: + /* Save the caller saving registers (context) */ + SAVE_CONTEXT + /* Save the necessary CSR registers */ + SAVE_CSR_CONTEXT + + /* + * Set the exception handler function arguments + * argument 1: mcause value + * argument 2: current stack point(SP) value + */ + csrr a0, mcause + mv a1, sp + /* + * TODO: Call the exception handler function + * By default, the function template is provided in + * system_Device.c, you can adjust it as you want + */ + call core_exception_handler + + /* Restore the necessary CSR registers */ + RESTORE_CSR_CONTEXT + /* Restore the caller saving registers (context) */ + RESTORE_CONTEXT + + /* Return to regular code */ + mret + +/** + * \brief Non-Vector Interrupt Entry + * \details + * This function provide common entry functions for handling + * non-vector interrupts + * \remarks + * This function provide a default non-vector interrupt entry. + * ABI defined caller save register and some CSR registers need + * to be saved before enter interrupt handler and be restored before return. + */ +.section .text.irq +/* In CLIC mode, the interrupt entry must be 4bytes aligned */ +.align 2 +.global irq_entry +/* This label will be set to MTVT2 register */ +irq_entry: + /* Save the caller saving registers (context) */ + SAVE_CONTEXT + /* Save the necessary CSR registers */ + SAVE_CSR_CONTEXT + + /* This special CSR read/write operation, which is actually + * claim the CLIC to find its pending highest ID, if the ID + * is not 0, then automatically enable the mstatus.MIE, and + * jump to its vector-entry-label, and update the link register + */ + csrrw ra, CSR_JALMNXTI, ra + + /* Critical section with interrupts disabled */ + DISABLE_MIE + + /* Restore the necessary CSR registers */ + RESTORE_CSR_CONTEXT + /* Restore the caller saving registers (context) */ + RESTORE_CONTEXT + + /* Return to regular code */ + mret + +/* Default Handler for Exceptions / Interrupts */ +.global default_intexc_handler +Undef_Handler: +default_intexc_handler: +1: + j 1b + diff --git a/libcpu/risc-v/rv32m1/SConscript b/libcpu/risc-v/rv32m1/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/risc-v/rv32m1/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/risc-v/rv32m1/interrupt_gcc.S b/libcpu/risc-v/rv32m1/interrupt_gcc.S index d74cf441bc..eacf667c67 100644 --- a/libcpu/risc-v/rv32m1/interrupt_gcc.S +++ b/libcpu/risc-v/rv32m1/interrupt_gcc.S @@ -69,10 +69,10 @@ IRQ_Handler: /* need to switch new thread */ la s0, rt_thread_switch_interrupt_flag - LOAD s2, 0(s0) + lw s2, 0(s0) beqz s2, spurious_interrupt /* clear switch interrupt flag */ - STORE zero, 0(s0) + sw zero, 0(s0) csrr a0, mepc STORE a0, 0 * REGBYTES(sp) diff --git a/libcpu/risc-v/t-head/e906/SConscript b/libcpu/risc-v/t-head/e906/SConscript new file mode 100644 index 0000000000..2f698f530a --- /dev/null +++ b/libcpu/risc-v/t-head/e906/SConscript @@ -0,0 +1,12 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/risc-v/t-head/e906/context_gcc.S b/libcpu/risc-v/t-head/e906/context_gcc.S new file mode 100644 index 0000000000..2f5223ae63 --- /dev/null +++ b/libcpu/risc-v/t-head/e906/context_gcc.S @@ -0,0 +1,323 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/08/20 zx.chen The T-HEAD RISC-V CPU E906 porting implementation + */ + +#include "cpuport.h" + +#ifdef RT_USING_SMP +#define rt_hw_interrupt_disable rt_hw_local_irq_disable +#define rt_hw_interrupt_enable rt_hw_local_irq_enable +#endif + +/* + * Functions: vPortYield + */ +.global vPortYield +.type vPortYield, %function +vPortYield: + li t0, 0xE080100C + lb t1, (t0) + li t2, 0x01 + or t1, t1, t2 + sb t1, (t0) + + ret + + + +/* + * #ifdef RT_USING_SMP + * void rt_hw_context_switch_to(rt_ubase_t to, stuct rt_thread *to_thread); + * #else + * void rt_hw_context_switch_to(rt_ubase_t to); + * #endif + * a0 --> to + * a1 --> to_thread + */ + .globl rt_hw_context_switch_to +rt_hw_context_switch_to: + /* save a0 to to_thread */ + la t0, rt_interrupt_to_thread + STORE a0, (t0) + + /* save 0 to from_thread */ + la t0, rt_interrupt_from_thread + li t1, 0 + STORE t1, (t0) + + /* set rt_thread_switch_interrupt_flag=1 */ + la t0, rt_thread_switch_interrupt_flag + li t1, 1 + STORE t1, (t0) + + /* enable mexstatus SPUSHEN and SPSWAPEN */ +#if ((CONFIG_CPU_E906==1) || (CONFIG_CPU_E906F==1) || (CONFIG_CPU_E906FD==1)) + uint32_t mexstatus; + mexstatus = __get_MEXSTATUS(); + mexstatus |= (0x2 << 16); + __set_MEXSTATUS(mexstatus); +#endif + + csrw mscratch, sp + /* set software interrupt */ + li t0, 0xE080100C + lb t1, (t0) + li t2, 0x01 + or t1, t1, t2 + sb t1, (t0) + + /* enable global interrup */ + csrsi mstatus, 8 + + ret + +/* + * #ifdef RT_USING_SMP + * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread); + * #else + * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to); + * #endif + * + * a0 --> from + * a1 --> to + * a2 --> to_thread + */ + .globl rt_hw_context_switch +rt_hw_context_switch: + .globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + /* check rt_thread_switch_interrupt_flag */ + la t0, rt_thread_switch_interrupt_flag + lw t1, (t0) + li t2, 1 + beq t1, t2, .reswitch + /* set rt_thread_switch_interrupt_flag=1 */ + STORE t2, (t0) + + /* update from_thread */ + la t0, rt_interrupt_from_thread + STORE a0, (t0) + +.reswitch: + /* update to_thread */ + la t0, rt_interrupt_to_thread + STORE a1, (t0) + /* set software interrupt */ + li t0, 0xE080100C + lb t1, (t0) + li t2, 0x01 + or t1, t1, t2 + sb t1, (t0) + + ret + +/* + * PendSV_Handler + */ +.global PendSV_Handler +.type PendSV_Handler, %function +PendSV_Handler: + + /* check rt_thread_switch_interrupt_flag */ + sw t0, (-4)(sp) + sw t1, (-8)(sp) + la t0, rt_thread_switch_interrupt_flag + lw t1, (t0) + beqz t1, .pendsv_exit + + /* clear rt_thread_switch_interrupt_flag */ + li t1, 0x0 + sw t1, (t0) + + /* check rt_interrupt_from_thread */ + la t0, rt_interrupt_from_thread + lw t1, (t0) + beqz t1, .switch_to_thead + + /* save from thread context */ + lw t0, (-4)(sp) + lw t1, (-8)(sp) + +#ifdef ARCH_RISCV_FPU + addi sp, sp, -32 * FREGBYTES + + FSTORE f0, 0 * FREGBYTES(sp) + FSTORE f1, 1 * FREGBYTES(sp) + FSTORE f2, 2 * FREGBYTES(sp) + FSTORE f3, 3 * FREGBYTES(sp) + FSTORE f4, 4 * FREGBYTES(sp) + FSTORE f5, 5 * FREGBYTES(sp) + FSTORE f6, 6 * FREGBYTES(sp) + FSTORE f7, 7 * FREGBYTES(sp) + FSTORE f8, 8 * FREGBYTES(sp) + FSTORE f9, 9 * FREGBYTES(sp) + FSTORE f10, 10 * FREGBYTES(sp) + FSTORE f11, 11 * FREGBYTES(sp) + FSTORE f12, 12 * FREGBYTES(sp) + FSTORE f13, 13 * FREGBYTES(sp) + FSTORE f14, 14 * FREGBYTES(sp) + FSTORE f15, 15 * FREGBYTES(sp) + FSTORE f16, 16 * FREGBYTES(sp) + FSTORE f17, 17 * FREGBYTES(sp) + FSTORE f18, 18 * FREGBYTES(sp) + FSTORE f19, 19 * FREGBYTES(sp) + FSTORE f20, 20 * FREGBYTES(sp) + FSTORE f21, 21 * FREGBYTES(sp) + FSTORE f22, 22 * FREGBYTES(sp) + FSTORE f23, 23 * FREGBYTES(sp) + FSTORE f24, 24 * FREGBYTES(sp) + FSTORE f25, 25 * FREGBYTES(sp) + FSTORE f26, 26 * FREGBYTES(sp) + FSTORE f27, 27 * FREGBYTES(sp) + FSTORE f28, 28 * FREGBYTES(sp) + FSTORE f29, 29 * FREGBYTES(sp) + FSTORE f30, 30 * FREGBYTES(sp) + FSTORE f31, 31 * FREGBYTES(sp) +#endif + + addi sp, sp, -32 * REGBYTES + + STORE x1, 1 * REGBYTES(sp) + csrr x1, mepc + STORE x1, 0 * REGBYTES(sp) + csrr x1, mstatus + andi x1, x1, 8 + beqz x1, .save_mpie + li x1, 0x80 +.save_mpie: + STORE x1, 2 * REGBYTES(sp) + /* x3 don't need save */ + STORE x4, 4 * REGBYTES(sp) + STORE x5, 5 * REGBYTES(sp) + STORE x6, 6 * REGBYTES(sp) + STORE x7, 7 * REGBYTES(sp) + STORE x8, 8 * REGBYTES(sp) + STORE x9, 9 * REGBYTES(sp) + STORE x10, 10 * REGBYTES(sp) + STORE x11, 11 * REGBYTES(sp) + STORE x12, 12 * REGBYTES(sp) + STORE x13, 13 * REGBYTES(sp) + STORE x14, 14 * REGBYTES(sp) + STORE x15, 15 * REGBYTES(sp) + STORE x16, 16 * REGBYTES(sp) + STORE x17, 17 * REGBYTES(sp) + STORE x18, 18 * REGBYTES(sp) + STORE x19, 19 * REGBYTES(sp) + STORE x20, 20 * REGBYTES(sp) + STORE x21, 21 * REGBYTES(sp) + STORE x22, 22 * REGBYTES(sp) + STORE x23, 23 * REGBYTES(sp) + STORE x24, 24 * REGBYTES(sp) + STORE x25, 25 * REGBYTES(sp) + STORE x26, 26 * REGBYTES(sp) + STORE x27, 27 * REGBYTES(sp) + STORE x28, 28 * REGBYTES(sp) + STORE x29, 29 * REGBYTES(sp) + STORE x30, 30 * REGBYTES(sp) + STORE x31, 31 * REGBYTES(sp) + + /* store from_thread sp */ + la t0, rt_interrupt_from_thread + lw t0, (t0) + sw sp, (t0) + +.switch_to_thead: + /* restore to thread context + * sp(0) -> epc; + * sp(1) -> ra; + * sp(i) -> x(i+2) + */ + la t0, rt_interrupt_to_thread + lw t0, (t0) + LOAD sp, (t0) + + /* restore ra to mepc */ + LOAD a1, 0 * REGBYTES(sp) + csrw mepc, a1 + LOAD x1, 1 * REGBYTES(sp) + + /* force to machin mode(MPP=11) */ + li a1, 0x1880 + csrs mstatus, a1 + LOAD a1, 2 * REGBYTES(sp) + csrs mstatus, a1 + /* x3 don't need restore */ + LOAD x4, 4 * REGBYTES(sp) + LOAD x5, 5 * REGBYTES(sp) + LOAD x6, 6 * REGBYTES(sp) + LOAD x7, 7 * REGBYTES(sp) + LOAD x8, 8 * REGBYTES(sp) + LOAD x9, 9 * REGBYTES(sp) + LOAD x10, 10 * REGBYTES(sp) + LOAD x11, 11 * REGBYTES(sp) + LOAD x12, 12 * REGBYTES(sp) + LOAD x13, 13 * REGBYTES(sp) + LOAD x14, 14 * REGBYTES(sp) + LOAD x15, 15 * REGBYTES(sp) + LOAD x16, 16 * REGBYTES(sp) + LOAD x17, 17 * REGBYTES(sp) + LOAD x18, 18 * REGBYTES(sp) + LOAD x19, 19 * REGBYTES(sp) + LOAD x20, 20 * REGBYTES(sp) + LOAD x21, 21 * REGBYTES(sp) + LOAD x22, 22 * REGBYTES(sp) + LOAD x23, 23 * REGBYTES(sp) + LOAD x24, 24 * REGBYTES(sp) + LOAD x25, 25 * REGBYTES(sp) + LOAD x26, 26 * REGBYTES(sp) + LOAD x27, 27 * REGBYTES(sp) + LOAD x28, 28 * REGBYTES(sp) + LOAD x29, 29 * REGBYTES(sp) + LOAD x30, 30 * REGBYTES(sp) + LOAD x31, 31 * REGBYTES(sp) + + addi sp, sp, 32 * REGBYTES + +#ifdef ARCH_RISCV_FPU + FLOAD f0, 0 * FREGBYTES(sp) + FLOAD f1, 1 * FREGBYTES(sp) + FLOAD f2, 2 * FREGBYTES(sp) + FLOAD f3, 3 * FREGBYTES(sp) + FLOAD f4, 4 * FREGBYTES(sp) + FLOAD f5, 5 * FREGBYTES(sp) + FLOAD f6, 6 * FREGBYTES(sp) + FLOAD f7, 7 * FREGBYTES(sp) + FLOAD f8, 8 * FREGBYTES(sp) + FLOAD f9, 9 * FREGBYTES(sp) + FLOAD f10, 10 * FREGBYTES(sp) + FLOAD f11, 11 * FREGBYTES(sp) + FLOAD f12, 12 * FREGBYTES(sp) + FLOAD f13, 13 * FREGBYTES(sp) + FLOAD f14, 14 * FREGBYTES(sp) + FLOAD f15, 15 * FREGBYTES(sp) + FLOAD f16, 16 * FREGBYTES(sp) + FLOAD f17, 17 * FREGBYTES(sp) + FLOAD f18, 18 * FREGBYTES(sp) + FLOAD f19, 19 * FREGBYTES(sp) + FLOAD f20, 20 * FREGBYTES(sp) + FLOAD f21, 21 * FREGBYTES(sp) + FLOAD f22, 22 * FREGBYTES(sp) + FLOAD f23, 23 * FREGBYTES(sp) + FLOAD f24, 24 * FREGBYTES(sp) + FLOAD f25, 25 * FREGBYTES(sp) + FLOAD f26, 26 * FREGBYTES(sp) + FLOAD f27, 27 * FREGBYTES(sp) + FLOAD f28, 28 * FREGBYTES(sp) + FLOAD f29, 29 * FREGBYTES(sp) + FLOAD f30, 30 * FREGBYTES(sp) + FLOAD f31, 31 * FREGBYTES(sp) + + addi sp, sp, 32 * FREGBYTES +#endif + +.pendsv_exit: + mret + + + diff --git a/libcpu/risc-v/t-head/e906/cpuport.c b/libcpu/risc-v/t-head/e906/cpuport.c new file mode 100644 index 0000000000..5597aa237a --- /dev/null +++ b/libcpu/risc-v/t-head/e906/cpuport.c @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/08/20 zx.chen The T-HEAD RISC-V CPU E906 porting code. + */ + +#include <rthw.h> +#include <rtthread.h> + +#include "cpuport.h" + +#ifndef RT_USING_SMP +volatile rt_ubase_t rt_interrupt_from_thread = 0; +volatile rt_ubase_t rt_interrupt_to_thread = 0; +volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0; +#endif + +struct rt_hw_stack_frame +{ + rt_ubase_t epc; /* epc - epc - program counter */ + rt_ubase_t ra; /* x1 - ra - return address for jumps */ + rt_ubase_t mstatus; /* - machine status register */ + rt_ubase_t gp; /* x3 - gp - global pointer */ + rt_ubase_t tp; /* x4 - tp - thread pointer */ + rt_ubase_t t0; /* x5 - t0 - temporary register 0 */ + rt_ubase_t t1; /* x6 - t1 - temporary register 1 */ + rt_ubase_t t2; /* x7 - t2 - temporary register 2 */ + rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */ + rt_ubase_t s1; /* x9 - s1 - saved register 1 */ + rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */ + rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */ + rt_ubase_t a2; /* x12 - a2 - function argument 2 */ + rt_ubase_t a3; /* x13 - a3 - function argument 3 */ + rt_ubase_t a4; /* x14 - a4 - function argument 4 */ + rt_ubase_t a5; /* x15 - a5 - function argument 5 */ + rt_ubase_t a6; /* x16 - a6 - function argument 6 */ + rt_ubase_t a7; /* x17 - s7 - function argument 7 */ + rt_ubase_t s2; /* x18 - s2 - saved register 2 */ + rt_ubase_t s3; /* x19 - s3 - saved register 3 */ + rt_ubase_t s4; /* x20 - s4 - saved register 4 */ + rt_ubase_t s5; /* x21 - s5 - saved register 5 */ + rt_ubase_t s6; /* x22 - s6 - saved register 6 */ + rt_ubase_t s7; /* x23 - s7 - saved register 7 */ + rt_ubase_t s8; /* x24 - s8 - saved register 8 */ + rt_ubase_t s9; /* x25 - s9 - saved register 9 */ + rt_ubase_t s10; /* x26 - s10 - saved register 10 */ + rt_ubase_t s11; /* x27 - s11 - saved register 11 */ + rt_ubase_t t3; /* x28 - t3 - temporary register 3 */ + rt_ubase_t t4; /* x29 - t4 - temporary register 4 */ + rt_ubase_t t5; /* x30 - t5 - temporary register 5 */ + rt_ubase_t t6; /* x31 - t6 - temporary register 6 */ +#ifdef ARCH_RISCV_FPU + rv_floatreg_t f0; /* f0 */ + rv_floatreg_t f1; /* f1 */ + rv_floatreg_t f2; /* f2 */ + rv_floatreg_t f3; /* f3 */ + rv_floatreg_t f4; /* f4 */ + rv_floatreg_t f5; /* f5 */ + rv_floatreg_t f6; /* f6 */ + rv_floatreg_t f7; /* f7 */ + rv_floatreg_t f8; /* f8 */ + rv_floatreg_t f9; /* f9 */ + rv_floatreg_t f10; /* f10 */ + rv_floatreg_t f11; /* f11 */ + rv_floatreg_t f12; /* f12 */ + rv_floatreg_t f13; /* f13 */ + rv_floatreg_t f14; /* f14 */ + rv_floatreg_t f15; /* f15 */ + rv_floatreg_t f16; /* f16 */ + rv_floatreg_t f17; /* f17 */ + rv_floatreg_t f18; /* f18 */ + rv_floatreg_t f19; /* f19 */ + rv_floatreg_t f20; /* f20 */ + rv_floatreg_t f21; /* f21 */ + rv_floatreg_t f22; /* f22 */ + rv_floatreg_t f23; /* f23 */ + rv_floatreg_t f24; /* f24 */ + rv_floatreg_t f25; /* f25 */ + rv_floatreg_t f26; /* f26 */ + rv_floatreg_t f27; /* f27 */ + rv_floatreg_t f28; /* f28 */ + rv_floatreg_t f29; /* f29 */ + rv_floatreg_t f30; /* f30 */ + rv_floatreg_t f31; /* f31 */ +#endif +}; + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, + void *parameter, + rt_uint8_t *stack_addr, + void *texit) +{ + struct rt_hw_stack_frame *frame; + rt_uint8_t *stk; + int i; + + stk = stack_addr + sizeof(rt_ubase_t); + stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES); + stk -= sizeof(struct rt_hw_stack_frame); + + frame = (struct rt_hw_stack_frame *)stk; + + for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++) + { + ((rt_ubase_t *)frame)[i] = 0xdeadbeef; + } + + frame->ra = (rt_ubase_t)texit; + frame->a0 = (rt_ubase_t)parameter; + frame->epc = (rt_ubase_t)tentry; + + /* force to machine mode(MPP=11) and set MPIE to 1 */ + frame->mstatus = 0x00007880; + + return stk; +} + + +/** + * This function will disable global interrupt + * + * @param none + * + * @return zero + */ + +rt_base_t rt_hw_interrupt_disable(void) +{ + __asm volatile("csrc mstatus, 8"); + return 0; +} + +/** + * This function will ennable global interrupt + * + * @param level not used + * + * @return none + */ +void rt_hw_interrupt_enable(rt_base_t level) +{ + __asm volatile("csrs mstatus, 8"); +} + +/** shutdown CPU */ +void rt_hw_cpu_shutdown() +{ + rt_uint32_t level; + rt_kprintf("shutdown...\n"); + + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } +} diff --git a/libcpu/risc-v/t-head/e906/cpuport.h b/libcpu/risc-v/t-head/e906/cpuport.h new file mode 100644 index 0000000000..90efc07653 --- /dev/null +++ b/libcpu/risc-v/t-head/e906/cpuport.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 zx.chen The first version + */ + +#ifndef CPUPORT_H__ +#define CPUPORT_H__ + +#include <rtconfig.h> + +/* bytes of register width */ +#ifdef ARCH_RISCV_64 +#define DFSTORE fsd +#define DFLOAD fld +#define SFSTORE fsw +#define SFLOAD flw +#define STORE sd +#define LOAD ld +#define REGBYTES 8 +#define SFREGBYTES 4 +#define DFREGBYTES 8 +#else +#define DFSTORE fsd +#define DFLOAD fld +#define SFSTORE fsw +#define SFLOAD flw +#define STORE sw +#define LOAD lw + +#define REGBYTES 4 +#define SFREGBYTES 4 +#define DFREGBYTES 8 +#endif + +#ifdef ARCH_RISCV_FPU +#ifdef ARCH_RISCV_FPU_D +#define FSTORE fsd +#define FLOAD fld +#define FREGBYTES 8 +#define rv_floatreg_t rt_int64_t +#endif +#ifdef ARCH_RISCV_FPU_S +#define FSTORE fsw +#define FLOAD flw +#define FREGBYTES 4 +#define rv_floatreg_t rt_int32_t +#endif +#endif + +#endif diff --git a/libcpu/rx/SConscript b/libcpu/rx/SConscript new file mode 100644 index 0000000000..e5890498c9 --- /dev/null +++ b/libcpu/rx/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_iar.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/rx/context_iar.S b/libcpu/rx/context_iar.S index 143ae00315..97c630e797 100644 --- a/libcpu/rx/context_iar.S +++ b/libcpu/rx/context_iar.S @@ -28,8 +28,8 @@ _rt_hw_interrupt_enable: MVTIPL #KERNEL_INTERRUPT_PRIORITY RTS -; r0 --> swith from thread stack -; r1 --> swith to thread stack +; r0 --> switch from thread stack +; r1 --> switch to thread stack ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack ___interrupt_27: @@ -73,12 +73,12 @@ ___interrupt_27: MOV.L #_rt_interrupt_from_thread, R15 MOV.L [ R15 ], R15 MOV.L R0, [ R15 ] - BRA swtich_to_thread + BRA switch_to_thread need_modify_isp: MVFC ISP, R15 ADD #12, R15 MVTC R15, ISP -swtich_to_thread: +switch_to_thread: SETPSW U MOV.L #_rt_interrupt_to_thread, R15 MOV.L [ R15 ], R15 diff --git a/libcpu/rx/cpuport.c b/libcpu/rx/cpuport.c index e8a75c629e..681c0e8e6e 100644 --- a/libcpu/rx/cpuport.c +++ b/libcpu/rx/cpuport.c @@ -58,7 +58,7 @@ struct stack_frame }; /** - * Initilial the threah stack. + * Initilial the thread stack. * * @author LXZ (2014/11/8) * @@ -158,7 +158,7 @@ void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to) ENTER_INTERRUPT(); } /** - * swithc thread out the interrupt + * switch thread out the interrupt * * @author LXZ (2014/11/8) * diff --git a/libcpu/sim/SConscript b/libcpu/sim/SConscript new file mode 100644 index 0000000000..4f1441895c --- /dev/null +++ b/libcpu/sim/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +group = [] +list = os.listdir(cwd) + +# cpu porting code files +group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) + +Return('group') diff --git a/libcpu/sim/posix/SConscript b/libcpu/sim/posix/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/sim/posix/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/sim/win32/SConscript b/libcpu/sim/win32/SConscript new file mode 100644 index 0000000000..afab42d47c --- /dev/null +++ b/libcpu/sim/win32/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/sparc-v8/SConscript b/libcpu/sparc-v8/SConscript new file mode 100644 index 0000000000..f6ea13fb91 --- /dev/null +++ b/libcpu/sparc-v8/SConscript @@ -0,0 +1,16 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() + +# add common code files +group = SConscript(os.path.join('common', 'SConscript')) + +# cpu porting code files +group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) + +Return('group') diff --git a/libcpu/sparc-v8/bm3803/SConscript b/libcpu/sparc-v8/bm3803/SConscript new file mode 100644 index 0000000000..1e96ff5837 --- /dev/null +++ b/libcpu/sparc-v8/bm3803/SConscript @@ -0,0 +1,17 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/sparc-v8/bm3803/bm3803.h b/libcpu/sparc-v8/bm3803/bm3803.h new file mode 100644 index 0000000000..17a9882eb2 --- /dev/null +++ b/libcpu/sparc-v8/bm3803/bm3803.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ + +#ifndef __BM3803_H__ +#define __BM3803_H__ + +struct lregs +{ + /* address = 0x80000000 */ + unsigned int memcfg1; /* 0x00 */ + unsigned int memcfg2; + unsigned int memcfg3; + unsigned int failaddr; + + unsigned int memstatus; /* 0x10 */ + unsigned int cachectrl; + unsigned int powerdown; + unsigned int writeprot1; + + unsigned int writeprot2; /* 0x20 */ + unsigned int pcr; + unsigned int dummy2; + unsigned int dummy3; + + unsigned int dummy4; /* 0x30 */ + unsigned int dummy5; + unsigned int dummy6; + unsigned int dummy7; + + unsigned int timercnt1; /* 0x40 */ + unsigned int timerload1; + unsigned int timerctrl1; + unsigned int wdog; + + unsigned int timercnt2; /* 0x50 */ + unsigned int timerload2; + unsigned int timerctrl2; + unsigned int dummy8; + + unsigned int scalercnt; /* 0x60 */ + unsigned int scalerload; + unsigned int dummy9; + unsigned int dummy10; + + unsigned int uartdata1; /* 0x70 */ + unsigned int uartstatus1; + unsigned int uartctrl1; + unsigned int uartscaler1; + + unsigned int uartdata2; /* 0x80 */ + unsigned int uartstatus2; + unsigned int uartctrl2; + unsigned int uartscaler2; + + unsigned int irqmask; /* 0x90 */ + unsigned int irqpend; + unsigned int irqforce; + unsigned int irqclear; + + unsigned int piodata; /* 0xA0 */ + unsigned int piodir; + unsigned int pioirq; + unsigned int dummy11; + + unsigned int imask2; /* 0xB0 */ + unsigned int ipend2; + unsigned int istat2; + unsigned int dummy12; + + unsigned int dummy13; /* 0xC0 */ + unsigned int dcomstatus; + unsigned int dcomctrl; + unsigned int dcomscaler; + + unsigned int dummy14; /* 0xD0 */ + unsigned int dummy15; + unsigned int dummy16; + unsigned int dummy17; + + unsigned int uartdata3; /* 0xE0 */ + unsigned int uartstatus3; + unsigned int uartctrl3; + unsigned int uartscaler3; +}; + +#define PREGS 0x80000000 + +#define UART1_BASE (PREGS + 0x70) + +#define TIMER2_TT 0x19 +#define UART1_TT 0x13 + +#endif diff --git a/libcpu/sparc-v8/bm3803/context_gcc.S b/libcpu/sparc-v8/bm3803/context_gcc.S new file mode 100644 index 0000000000..c0344a81d5 --- /dev/null +++ b/libcpu/sparc-v8/bm3803/context_gcc.S @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ + +#define SPARC_PSR_PIL_MASK 0x00000F00 +#define SPARC_PSR_ET_MASK 0x00000020 + +/* + * rt_base_t rt_hw_interrupt_disable(); + */ +.globl rt_hw_interrupt_disable +rt_hw_interrupt_disable: + mov %psr, %o0 + or %o0, SPARC_PSR_PIL_MASK, %o1 + mov %o1, %psr + nop + nop + nop + retl + nop + +/* + * void rt_hw_interrupt_enable(rt_base_t level); + */ +.globl rt_hw_interrupt_enable +rt_hw_interrupt_enable: + mov %o0, %psr + nop + nop + nop + retl + nop + +/* + * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); + * o0 --> from + * o1 --> to + */ +.globl rt_hw_context_switch +rt_hw_context_switch: + ta 2 + retl + nop + +/* + * void rt_hw_context_switch_to(rt_uint32 to); + * o0 --> to + */ +.globl rt_hw_context_switch_to +rt_hw_context_switch_to: + mov %o0, %o1 + ta 3 + retl + nop + +/* + * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); + */ +.globl rt_thread_switch_interrupt_flag +.globl rt_interrupt_from_thread +.globl rt_interrupt_to_thread +.globl rt_hw_context_switch_interrupt +rt_hw_context_switch_interrupt: + set rt_thread_switch_interrupt_flag, %o2 + ld [%o2], %o3 + cmp %o3, 1 + be _reswitch + nop + mov 1, %o3 + st %o3, [%o2] + set rt_interrupt_from_thread, %o2 + st %o0, [%o2] +_reswitch: + set rt_interrupt_to_thread, %o2 + st %o1, [%o2] + retl + nop diff --git a/libcpu/sparc-v8/bm3803/interrupt.c b/libcpu/sparc-v8/bm3803/interrupt.c new file mode 100644 index 0000000000..b3625862b4 --- /dev/null +++ b/libcpu/sparc-v8/bm3803/interrupt.c @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ + +#include <rthw.h> +#include <rtthread.h> + +#include "bm3803.h" +#include "interrupt.h" + +#define MAX_HANDLERS 256 + +extern volatile rt_uint8_t rt_interrupt_nest; +struct rt_irq_desc isr_table[MAX_HANDLERS]; +rt_uint32_t rt_interrupt_from_thread; +rt_uint32_t rt_interrupt_to_thread; +rt_uint32_t rt_thread_switch_interrupt_flag; + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + /* init exceptions table */ + rt_memset(isr_table, 0x00, sizeof(isr_table)); + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + if (vector > 0x1F || vector < 0x11) + return; + volatile struct lregs *regs = (struct lregs *)PREGS; + regs->irqmask &= ~(1 << (vector - 0x10)); +} + +/** + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + if (vector > 0x1F || vector < 0x11) + return; + volatile struct lregs *regs = (struct lregs *)PREGS; + regs->irqmask |= 1 << (vector - 0x10); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param new_handler the interrupt service routine to be installed + * @param old_handler the old interrupt service routine + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + + if (vector < MAX_HANDLERS || vector >= 0) + { + old_handler = isr_table[vector].handler; + + if (handler != RT_NULL) + { +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); +#endif /* RT_USING_INTERRUPT_INFO */ + isr_table[vector].handler = handler; + isr_table[vector].param = param; + } + } + + return old_handler; +} + +void rt_hw_interrupt_clear(int vector) +{ + if (vector > 0x1F || vector < 0x11) + return; + volatile struct lregs *regs = (struct lregs *)PREGS; + regs->irqclear |= 1 << (vector - 0x10); +} diff --git a/libcpu/sparc-v8/bm3803/interrupt.h b/libcpu/sparc-v8/bm3803/interrupt.h new file mode 100644 index 0000000000..666d5268f5 --- /dev/null +++ b/libcpu/sparc-v8/bm3803/interrupt.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + * 2020-10-21 Dystopia Add new function + */ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +void rt_hw_interrupt_clear(int vector); + +#endif diff --git a/libcpu/sparc-v8/bm3803/stack.c b/libcpu/sparc-v8/bm3803/stack.c new file mode 100644 index 0000000000..2fdc37b539 --- /dev/null +++ b/libcpu/sparc-v8/bm3803/stack.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ + +#include <rtthread.h> + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + rt_uint32_t *stk; + int window_index; + int register_index; + + stack_addr += sizeof(rt_uint32_t); + stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); + stk = (rt_uint32_t *)stack_addr; + + stk -= 24; + stk -= 8; + + for (register_index = 0; register_index != 8; register_index++) + stk[register_index] = 0xdeadbeef; + + for (window_index = 0; window_index != 8; window_index++) + { + stk -= 16; + for (register_index = 0; register_index != 16; register_index++) + stk[register_index] = 0xdeadbeef; + if (window_index == 0) + { + stk[8] = (rt_uint32_t)parameter; + stk[15] = (rt_uint32_t)texit - 8; + } + } + + stk -= 34; + for (register_index = 0; register_index != 34; register_index++) + stk[register_index] = 0; + + stk -= 4; + stk[0] = (rt_uint32_t)tentry; //pc + stk[1] = (rt_uint32_t)tentry + 4; //npc + stk[2] = 0x10C7; //psr + stk[3] = 0x2; //wim + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} diff --git a/libcpu/sparc-v8/bm3803/start_gcc.S b/libcpu/sparc-v8/bm3803/start_gcc.S new file mode 100644 index 0000000000..0f87aa17db --- /dev/null +++ b/libcpu/sparc-v8/bm3803/start_gcc.S @@ -0,0 +1,664 @@ +/* + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ + +#define PSR_INIT 0x10C0 +#define PREGS 0x80000000 +#define IMASK 0x90 +#define ICLEAR 0x9c +#define NWINDOWS 8 +#define CPU_INTERRUPT_FRAME_SIZE (0x60 + 0x50 + 34 * 4) +#define SPARC_PSR_PIL_MASK 0x00000F00 +#define SPARC_PSR_ET_MASK 0x00000020 +#define SPARC_PSR_CWP_MASK 0x07 + +.text + +.globl system_vectors +.globl _reset +.globl _context_switch + +_reset: + mov %g0, %asr16 + mov %g0, %asr17 + nop + nop + nop + + set PSR_INIT, %g1 + mov %g1, %psr + nop + nop + nop + + mov %g0, %wim + nop + nop + nop + + mov %g0, %g1 + mov %g0, %g2 + mov %g0, %g3 + mov %g0, %g4 + mov %g0, %g5 + mov %g0, %g6 + mov %g0, %g7 + + mov 0x8, %g1 +1: + mov %g0, %l0 + mov %g0, %l1 + mov %g0, %l2 + mov %g0, %l3 + mov %g0, %l4 + mov %g0, %l5 + mov %g0, %l6 + mov %g0, %l7 + mov %g0, %i0 + mov %g0, %i1 + mov %g0, %i2 + mov %g0, %i3 + mov %g0, %i4 + mov %g0, %i5 + mov %g0, %i6 + mov %g0, %i7 + subcc %g1, 1, %g1 + save + bne 1b + nop + + set 2, %g1 + mov %g1, %wim + nop + nop + nop + + sethi %hi(system_vectors), %g1 + mov %g1, %tbr + nop + nop + nop + + set PREGS, %g1 + set 0xffff, %g2 + st %g2, [%g1 + ICLEAR] + st %g0, [%g1 + IMASK] + + set 0x7C47907F, %g2 + st %g2, [%g1 + 4] + + set PSR_INIT | 0x20, %g1 + mov %g1, %psr + nop + nop + nop + + set _fsrinit, %g1 + ld [%g1], %fsr + nop + nop + nop + + set _fpdata, %g1 + ldd [%g1], %f0 + ldd [%g1], %f2 + ldd [%g1], %f4 + ldd [%g1], %f6 + ldd [%g1], %f8 + ldd [%g1], %f10 + ldd [%g1], %f12 + ldd [%g1], %f14 + ldd [%g1], %f16 + ldd [%g1], %f18 + ldd [%g1], %f20 + ldd [%g1], %f22 + ldd [%g1], %f24 + ldd [%g1], %f26 + ldd [%g1], %f28 + ldd [%g1], %f30 + + set __bss_start, %g2 + set __bss_end, %g3 + mov %g0, %g1 +bss_loop: + std %g0, [%g2] + add %g2, 8, %g2 + cmp %g2, %g3 + bleu,a bss_loop + nop + + set 0x401FFF00, %g1 + mov %g1, %sp + + /* start RT-Thread Kernel */ + call rtthread_startup + nop + +/* +l0 = psr +l1 = pc +l2 = npc +l3 = tbr +*/ +.globl _ISR_Handler +_ISR_Handler: + mov %g4, %l4 + mov %g5, %l5 + mov %wim, %g4 + srl %g4, %l0, %g5 + cmp %g5, 1 + bne dont_do_the_window + nop + srl %g4, 1, %g5 + sll %g4, NWINDOWS - 1, %g4 + or %g4, %g5, %g4 + save + mov %g4, %wim + nop + nop + nop + + std %l0, [%sp + 0x00] + std %l2, [%sp + 0x08] + std %l4, [%sp + 0x10] + std %l6, [%sp + 0x18] + + std %i0, [%sp + 0x20] + std %i2, [%sp + 0x28] + std %i4, [%sp + 0x30] + std %i6, [%sp + 0x38] + + restore + nop + +dont_do_the_window: + sub %fp, CPU_INTERRUPT_FRAME_SIZE, %sp + + std %l0, [%sp + 0x60] + st %l2, [%sp + 0x68] + st %g1, [%sp + 0x6c] + std %g2, [%sp + 0x70] + std %l4, [%sp + 0x78] + std %g6, [%sp + 0x80] + + std %i0, [%sp + 0x88] + std %i2, [%sp + 0x90] + std %i4, [%sp + 0x98] + std %i6, [%sp + 0xA0] + + mov %y, %g1 + st %g1, [%sp + 0xA8] + st %l6, [%sp + 0xAc] + + std %f0, [%sp + 0xB0 + 8 * 0x0] + std %f2, [%sp + 0xB0 + 8 * 0x1] + std %f4, [%sp + 0xB0 + 8 * 0x2] + std %f6, [%sp + 0xB0 + 8 * 0x3] + std %f8, [%sp + 0xB0 + 8 * 0x4] + std %f10, [%sp + 0xB0 + 8 * 0x5] + std %f12, [%sp + 0xB0 + 8 * 0x6] + std %f14, [%sp + 0xB0 + 8 * 0x7] + std %f16, [%sp + 0xB0 + 8 * 0x8] + std %f18, [%sp + 0xB0 + 8 * 0x9] + std %f20, [%sp + 0xB0 + 8 * 0xA] + std %f22, [%sp + 0xB0 + 8 * 0xB] + std %f24, [%sp + 0xB0 + 8 * 0xC] + std %f26, [%sp + 0xB0 + 8 * 0xD] + std %f28, [%sp + 0xB0 + 8 * 0xE] + std %f30, [%sp + 0xB0 + 8 * 0xF] + st %fsr, [%sp + 0xB0 + 8 * 0x10] + + mov %l0, %g5 + or %g5, SPARC_PSR_PIL_MASK, %g5 + wr %g5, SPARC_PSR_ET_MASK, %psr + nop + nop + nop + + call rt_interrupt_enter + nop + + and %l3, 0x0FF0, %l3 + srl %l3, 4, %o0 + mov %sp, %o1 + + call rt_hw_trap + nop + + call rt_interrupt_leave + nop + + mov %l0, %psr + nop + nop + nop + + ld [%sp + 0xA8], %l5 + mov %l5, %y + ldd [%sp + 0x60], %l0 + ld [%sp + 0x68], %l2 + + ld [%sp + 0x6c], %g1 + ldd [%sp + 0x70], %g2 + ldd [%sp + 0x78], %g4 + ldd [%sp + 0x80], %g6 + + ldd [%sp + 0x88], %i0 + ldd [%sp + 0x90], %i2 + ldd [%sp + 0x98], %i4 + ldd [%sp + 0xA0], %i6 + + ldd [%sp + 0xB0 + 8 * 0x0], %f0 + ldd [%sp + 0xB0 + 8 * 0x1], %f2 + ldd [%sp + 0xB0 + 8 * 0x2], %f4 + ldd [%sp + 0xB0 + 8 * 0x3], %f6 + ldd [%sp + 0xB0 + 8 * 0x4], %f8 + ldd [%sp + 0xB0 + 8 * 0x5], %f10 + ldd [%sp + 0xB0 + 8 * 0x6], %f12 + ldd [%sp + 0xB0 + 8 * 0x7], %f14 + ldd [%sp + 0xB0 + 8 * 0x8], %f16 + ldd [%sp + 0xB0 + 8 * 0x9], %f18 + ldd [%sp + 0xB0 + 8 * 0xA], %f20 + ldd [%sp + 0xB0 + 8 * 0xB], %f22 + ldd [%sp + 0xB0 + 8 * 0xC], %f24 + ldd [%sp + 0xB0 + 8 * 0xD], %f26 + ldd [%sp + 0xB0 + 8 * 0xE], %f28 + ldd [%sp + 0xB0 + 8 * 0xF], %f30 + ld [%sp + 0xB0 + 8 * 0x10], %fsr + nop + nop + nop + + mov %wim, %l4 + add %l0, 1, %l6 + and %l6, SPARC_PSR_CWP_MASK, %l6 + srl %l4, %l6, %l5 + cmp %l5, 1 + bne good_task_window + nop + sll %l4, 1, %l5 + srl %l4, NWINDOWS - 1, %l4 + or %l4, %l5, %l4 + mov %l4, %wim + nop + nop + nop + + restore + ldd [%sp + 0], %l0 ! Restore window from the stack + ldd [%sp + 8], %l2 + ldd [%sp + 16], %l4 + ldd [%sp + 24], %l6 + ldd [%sp + 32], %i0 + ldd [%sp + 40], %i2 + ldd [%sp + 48], %i4 + ldd [%sp + 56], %i6 + save + +good_task_window: + set rt_thread_switch_interrupt_flag, %l4 + ld [%l4], %l5 + cmp %l5, 1 + be rt_hw_context_switch_interrupt_do + nop + + mov %l0, %psr + nop + nop + nop + + jmp %l1 + rett %l2 + +rt_hw_context_switch_interrupt_do: + st %g0, [%l4] + + sub %fp, 0x20, %sp + std %g0, [%sp + 0x00] + std %g2, [%sp + 0x08] + std %g4, [%sp + 0x10] + std %g6, [%sp + 0x18] + + mov %sp, %g3 + mov %l1, %g4 + mov %l2, %g5 + mov %l0, %g6 + mov %wim, %g7 + + mov %g0, %wim + nop + nop + nop + set 0xFFFFFFF8, %g1 + and %g1, %g6, %g1 + mov %g1, %psr + nop + nop + nop + + mov %g0, %g1 +save_loop: + save + sub %g3, 0x40, %g3 + std %l0, [%g3 + 0x00] + std %l2, [%g3 + 0x08] + std %l4, [%g3 + 0x10] + std %l6, [%g3 + 0x18] + std %i0, [%g3 + 0x20] + std %i2, [%g3 + 0x28] + std %i4, [%g3 + 0x30] + std %i6, [%g3 + 0x38] + inc %g1 + cmp %g1, NWINDOWS + bne save_loop + nop + + sub %g3, 0x88, %g3 + std %f0, [%g3 + 0x00] + std %f2, [%g3 + 0x08] + std %f4, [%g3 + 0x10] + std %f6, [%g3 + 0x18] + std %f8, [%g3 + 0x20] + std %f10, [%g3 + 0x28] + std %f12, [%g3 + 0x30] + std %f14, [%g3 + 0x38] + std %f16, [%g3 + 0x40] + std %f18, [%g3 + 0x48] + std %f20, [%g3 + 0x50] + std %f22, [%g3 + 0x58] + std %f24, [%g3 + 0x60] + std %f26, [%g3 + 0x68] + std %f28, [%g3 + 0x70] + std %f30, [%g3 + 0x78] + mov %y, %g1 + st %g1, [%g3 + 0x80] + st %fsr, [%g3 + 0x84] + + sub %g3, 0x10, %g3 + std %g4, [%g3 + 0x00] + std %g6, [%g3 + 0x08] + + set rt_interrupt_from_thread, %g1 + ld [%g1], %g2 + st %g3, [%g2] + + set rt_interrupt_to_thread, %g1 + ld [%g1], %g1 + ld [%g1], %g3 + + ldd [%g3 + 0x00], %g4 + ldd [%g3 + 0x08], %g6 + add %g3, 0x10, %g3 + + ldd [%g3 + 0x00], %f0 + ldd [%g3 + 0x08], %f2 + ldd [%g3 + 0x10], %f4 + ldd [%g3 + 0x18], %f6 + ldd [%g3 + 0x20], %f8 + ldd [%g3 + 0x28], %f10 + ldd [%g3 + 0x30], %f12 + ldd [%g3 + 0x38], %f14 + ldd [%g3 + 0x40], %f16 + ldd [%g3 + 0x48], %f18 + ldd [%g3 + 0x50], %f20 + ldd [%g3 + 0x58], %f22 + ldd [%g3 + 0x60], %f24 + ldd [%g3 + 0x68], %f26 + ldd [%g3 + 0x70], %f28 + ldd [%g3 + 0x78], %f30 + ld [%g3 + 0x80], %g1 + mov %g1, %y + ld [%g3 + 0x84], %fsr + add %g3, 0x88, %g3 + + set NWINDOWS - 1, %g1 + or %g1, %g6, %g1 + mov %g1, %psr + nop + nop + nop + + mov %g0, %g1 +restore_loop: + restore + ldd [%g3 + 0x00], %l0 + ldd [%g3 + 0x08], %l2 + ldd [%g3 + 0x10], %l4 + ldd [%g3 + 0x18], %l6 + ldd [%g3 + 0x20], %i0 + ldd [%g3 + 0x28], %i2 + ldd [%g3 + 0x30], %i4 + ldd [%g3 + 0x38], %i6 + add %g3, 0x40, %g3 + inc %g1 + cmp %g1, NWINDOWS + bne restore_loop + nop + + mov %g6, %psr + nop + nop + nop + mov %g7, %wim + nop + nop + nop + + mov %g4, %l1 + mov %g5, %l2 + mov %g3, %sp + + ldd [%sp + 0x00], %g0 + ldd [%sp + 0x08], %g2 + ldd [%sp + 0x10], %g4 + ldd [%sp + 0x18], %g6 + add %sp, 0x20, %fp + jmp %l1 + rett %l2 + +/* +l0 = psr +l1 = pc +l2 = npc +l3 = tbr +*/ +_context_switch: + mov %l2, %l1 + add %l2, 4, %l2 + + mov %g4, %l4 + mov %g5, %l5 + mov %wim, %g4 + srl %g4, %l0, %g5 + cmp %g5, 1 + bne good_window + nop + srl %g4, 1, %g5 + sll %g4, NWINDOWS - 1, %g4 + or %g4, %g5, %g4 + save + mov %g4, %wim + nop + nop + nop + + std %l0, [%sp + 0x00] + std %l2, [%sp + 0x08] + std %l4, [%sp + 0x10] + std %l6, [%sp + 0x18] + + std %i0, [%sp + 0x20] + std %i2, [%sp + 0x28] + std %i4, [%sp + 0x30] + std %i6, [%sp + 0x38] + + restore + nop + +good_window: + and %l3, 0x0FF0, %l3 + srl %l3, 4, %l4 + cmp %l4, 0x82 + bne switch_to + nop + + sub %fp, 0x20, %sp + std %g0, [%sp + 0x00] + std %g2, [%sp + 0x08] + std %g4, [%sp + 0x10] + std %g6, [%sp + 0x18] + + mov %sp, %g3 + mov %l1, %g4 + mov %l2, %g5 + mov %l0, %g6 + mov %wim, %g7 + + mov %g0, %wim + nop + nop + nop + set 0xFFFFFFF8, %g1 + and %g1, %g6, %g1 + mov %g1, %psr + nop + nop + nop + + mov %g0, %g1 +save_window: + save + sub %g3, 0x40, %g3 + std %l0, [%g3 + 0x00] + std %l2, [%g3 + 0x08] + std %l4, [%g3 + 0x10] + std %l6, [%g3 + 0x18] + std %i0, [%g3 + 0x20] + std %i2, [%g3 + 0x28] + std %i4, [%g3 + 0x30] + std %i6, [%g3 + 0x38] + inc %g1 + cmp %g1, NWINDOWS + bne save_window + nop + + sub %g3, 0x88, %g3 + std %f0, [%g3 + 0x00] + std %f2, [%g3 + 0x08] + std %f4, [%g3 + 0x10] + std %f6, [%g3 + 0x18] + std %f8, [%g3 + 0x20] + std %f10, [%g3 + 0x28] + std %f12, [%g3 + 0x30] + std %f14, [%g3 + 0x38] + std %f16, [%g3 + 0x40] + std %f18, [%g3 + 0x48] + std %f20, [%g3 + 0x50] + std %f22, [%g3 + 0x58] + std %f24, [%g3 + 0x60] + std %f26, [%g3 + 0x68] + std %f28, [%g3 + 0x70] + std %f30, [%g3 + 0x78] + mov %y, %g1 + st %g1, [%g3 + 0x80] + st %fsr, [%g3 + 0x84] + + sub %g3, 0x10, %g3 + std %g4, [%g3 + 0x00] + std %g6, [%g3 + 0x08] + + mov %g6, %psr + nop + nop + nop + + st %g3, [%i0] +switch_to: + mov %g0, %wim + nop + nop + nop + ld [%i1], %g3 + + ldd [%g3 + 0x00], %g4 + ldd [%g3 + 0x08], %g6 + add %g3, 0x10, %g3 + + ldd [%g3 + 0x00], %f0 + ldd [%g3 + 0x08], %f2 + ldd [%g3 + 0x10], %f4 + ldd [%g3 + 0x18], %f6 + ldd [%g3 + 0x20], %f8 + ldd [%g3 + 0x28], %f10 + ldd [%g3 + 0x30], %f12 + ldd [%g3 + 0x38], %f14 + ldd [%g3 + 0x40], %f16 + ldd [%g3 + 0x48], %f18 + ldd [%g3 + 0x50], %f20 + ldd [%g3 + 0x58], %f22 + ldd [%g3 + 0x60], %f24 + ldd [%g3 + 0x68], %f26 + ldd [%g3 + 0x70], %f28 + ldd [%g3 + 0x78], %f30 + ld [%g3 + 0x80], %g1 + mov %g1, %y + ld [%g3 + 0x84], %fsr + add %g3, 0x88, %g3 + + set NWINDOWS - 1, %g1 + or %g1, %g6, %g1 + mov %g1, %psr + nop + nop + nop + + mov %g0, %g1 +restore_window: + restore + ldd [%g3 + 0x00], %l0 + ldd [%g3 + 0x08], %l2 + ldd [%g3 + 0x10], %l4 + ldd [%g3 + 0x18], %l6 + ldd [%g3 + 0x20], %i0 + ldd [%g3 + 0x28], %i2 + ldd [%g3 + 0x30], %i4 + ldd [%g3 + 0x38], %i6 + add %g3, 0x40, %g3 + inc %g1 + cmp %g1, NWINDOWS + bne restore_window + nop + + mov %g6, %psr + nop + nop + nop + mov %g7, %wim + nop + nop + nop + + mov %g4, %l1 + mov %g5, %l2 + mov %g3, %sp + + ldd [%sp + 0x00], %g0 + ldd [%sp + 0x08], %g2 + ldd [%sp + 0x10], %g4 + ldd [%sp + 0x18], %g6 + add %sp, 0x20, %fp + jmp %l1 + rett %l2 + +.data +.align 8 +_fpdata: + .word 0, 0 +_fsrinit: + .word 0 diff --git a/libcpu/sparc-v8/bm3803/trap.c b/libcpu/sparc-v8/bm3803/trap.c new file mode 100644 index 0000000000..b896a0d941 --- /dev/null +++ b/libcpu/sparc-v8/bm3803/trap.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ + +#include <rtthread.h> +#include <rthw.h> + +extern struct rt_irq_desc isr_table[]; + +void rt_hw_trap(int tt, unsigned int *sp) +{ + void *param; + rt_isr_handler_t isr_func; + + /* get interrupt service routine */ + isr_func = isr_table[tt].handler; + param = isr_table[tt].param; + + /* turn to interrupt service routine */ + if (isr_func != RT_NULL) + isr_func(tt, param); +} diff --git a/libcpu/sparc-v8/bm3803/vector_gcc.S b/libcpu/sparc-v8/bm3803/vector_gcc.S new file mode 100644 index 0000000000..0d243bee33 --- /dev/null +++ b/libcpu/sparc-v8/bm3803/vector_gcc.S @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2020, Shenzhen Academy of Aerospace Technology + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-16 Dystopia the first version + */ + +#define TRAPL(H) mov %g0, %l0; sethi %hi(H), %l4; jmp %l4 + %lo(H); nop; +#define TRAP(H) mov %psr, %l0; sethi %hi(H), %l4; jmp %l4 + %lo(H); nop; +#define TRAP_ENTRY(H) mov %psr, %l0; sethi %hi(H), %l4; jmp %l4 + %lo(H); mov %tbr, %l3; +#define BAD_TRAP ta 0; nop; nop; nop; +#define SOFT_TRAP BAD_TRAP +#define NWINDOWS 8 + +.section .vectors, "ax" + +.globl _ISR_Handler +.globl _window_overflow +.globl _window_underflow +.globl _reset +.globl _context_switch + +.globl system_vectors +system_vectors: + TRAPL(_reset); ! 00 reset trap + BAD_TRAP; ! 01 instruction_access_exception + BAD_TRAP; ! 02 illegal_instruction + BAD_TRAP; ! 03 priveleged_instruction + BAD_TRAP; + TRAP(_window_overflow); ! 05 window_overflow + TRAP(_window_underflow); ! 06 window_underflow + BAD_TRAP; ! 07 memory_add0ress_not_aligned + BAD_TRAP; ! 08 fp_exception + BAD_TRAP; ! 09 data_access_exception + BAD_TRAP; ! 0A tag_overflow + BAD_TRAP; ! 0B undefined + BAD_TRAP; ! 0C undefined + BAD_TRAP; ! 0D undefined + BAD_TRAP; ! 0E undefined + BAD_TRAP; ! 0F undefined + BAD_TRAP; ! 10 undefined + + /* Interrupt entries */ + TRAP_ENTRY(_ISR_Handler) ! 11 interrupt level 1 + TRAP_ENTRY(_ISR_Handler) ! 12 interrupt level 2 + TRAP_ENTRY(_ISR_Handler) ! 13 interrupt level 3 + TRAP_ENTRY(_ISR_Handler) ! 14 interrupt level 4 + TRAP_ENTRY(_ISR_Handler) ! 15 interrupt level 5 + TRAP_ENTRY(_ISR_Handler) ! 16 interrupt level 6 + TRAP_ENTRY(_ISR_Handler) ! 17 interrupt level 7 + TRAP_ENTRY(_ISR_Handler) ! 18 interrupt level 8 + TRAP_ENTRY(_ISR_Handler) ! 19 interrupt level 9 + TRAP_ENTRY(_ISR_Handler) ! 1A interrupt level 1 + TRAP_ENTRY(_ISR_Handler) ! 1B interrupt level 11 + TRAP_ENTRY(_ISR_Handler) ! 1C interrupt level 12 + TRAP_ENTRY(_ISR_Handler) ! 1D interrupt level 13 + TRAP_ENTRY(_ISR_Handler) ! 1E interrupt level 14 + TRAP_ENTRY(_ISR_Handler) ! 1F interrupt level 15 + + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 20 - 23 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 24 - 27 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 28 - 2B undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 2C - 2F undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 30 - 33 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 34 - 37 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 38 - 3B undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 3C - 3F undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 40 - 43 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 44 - 47 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 48 - 4B undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 4C - 4F undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 50 - 53 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 54 - 57 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 58 - 5B undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 5C - 5F undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 60 - 63 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 64 - 67 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 68 - 6B undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 6C - 6F undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 70 - 73 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 74 - 77 undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 78 - 7B undefined + BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 7C - 7F undefined + + /* Software traps */ + SOFT_TRAP; SOFT_TRAP; TRAP_ENTRY(_context_switch); TRAP_ENTRY(_context_switch) ! 80 - 83 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 84 - 87 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 88 - 8B + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 8C - 8F + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 90 - 93 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 94 - 97 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 98 - 9B + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 9C - 9F + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A0 - A3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A4 - A7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A8 - AB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! AC - AF + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B0 - B3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B4 - B7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B8 - BB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! BC - BF + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C0 - C3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C4 - C7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C8 - CB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! CC - CF + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D0 - D3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D4 - D7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D8 - DB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! DC - DF + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E0 - E3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E4 - E7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E8 - EB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! EC - EF + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F0 - F3 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F4 - F7 + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F8 - FB + SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! FC - FF + +_window_overflow: + mov %wim, %l3 ! Calculate next WIM + mov %g1, %l7 + srl %l3, 1, %g1 + sll %l3, NWINDOWS - 1, %l4 + or %l4, %g1, %g1 + save ! Get into window to be saved. + mov %g1, %wim + nop + nop + nop + std %l0, [%sp + 0] + std %l2, [%sp + 8] + std %l4, [%sp + 16] + std %l6, [%sp + 24] + std %i0, [%sp + 32] + std %i2, [%sp + 40] + std %i4, [%sp + 48] + std %i6, [%sp + 56] + restore ! Go back to trap window. + mov %l7, %g1 + jmp %l1 ! Re-execute save. + rett %l2 + +_window_underflow: + mov %wim, %l3 ! Calculate next WIM + sll %l3, 1, %l4 + srl %l3, NWINDOWS - 1, %l5 + or %l5, %l4, %l5 + mov %l5, %wim + nop + nop + nop + restore ! Two restores to get into the + restore ! window to restore + ldd [%sp + 0], %l0 ! Restore window from the stack + ldd [%sp + 8], %l2 + ldd [%sp + 16], %l4 + ldd [%sp + 24], %l6 + ldd [%sp + 32], %i0 + ldd [%sp + 40], %i2 + ldd [%sp + 48], %i4 + ldd [%sp + 56], %i6 + save ! Get back to the trap window. + save + jmp %l1 ! Re-execute restore. + rett %l2 diff --git a/libcpu/sparc-v8/common/SConscript b/libcpu/sparc-v8/common/SConscript new file mode 100644 index 0000000000..1e96ff5837 --- /dev/null +++ b/libcpu/sparc-v8/common/SConscript @@ -0,0 +1,17 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +if rtconfig.PLATFORM == 'gcc': + src += Glob('*_init.S') + src += Glob('*_gcc.S') + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/ti-dsp/SConscript b/libcpu/ti-dsp/SConscript new file mode 100644 index 0000000000..4f1441895c --- /dev/null +++ b/libcpu/ti-dsp/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +group = [] +list = os.listdir(cwd) + +# cpu porting code files +group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) + +Return('group') diff --git a/libcpu/ti-dsp/c28x/SConscript b/libcpu/ti-dsp/c28x/SConscript new file mode 100644 index 0000000000..08b274341b --- /dev/null +++ b/libcpu/ti-dsp/c28x/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*.s') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/ti-dsp/c28x/context.s b/libcpu/ti-dsp/c28x/context.s index 019b5def13..f21e0ddb6e 100644 --- a/libcpu/ti-dsp/c28x/context.s +++ b/libcpu/ti-dsp/c28x/context.s @@ -6,6 +6,8 @@ ; Change Logs: ; Date Author Notes ; 2018-09-01 xuzhuoyi the first version. +; 2019-06-17 zhaoxiaowei fix bugs of old c28x interrupt api. +; 2019-07-03 zhaoxiaowei add _rt_hw_calc_csb function to support __rt_ffs. ; .ref _rt_interrupt_to_thread @@ -15,6 +17,7 @@ .def _RTOSINT_Handler .def _rt_hw_get_st0 .def _rt_hw_get_st1 + .def _rt_hw_calc_csb .def _rt_hw_context_switch_interrupt .def _rt_hw_context_switch .def _rt_hw_context_switch_to @@ -73,7 +76,9 @@ RT_CTX_RESTORE .macro ; .asmfunc _rt_hw_interrupt_disable: - DINT + PUSH ST1 + SETC INTM,DBGM + MOV AL, *--SP LRETR .endasmfunc @@ -82,7 +87,8 @@ _rt_hw_interrupt_disable: ; .asmfunc _rt_hw_interrupt_enable: - EINT + MOV *SP++, AL + POP ST1 LRETR .endasmfunc @@ -94,11 +100,10 @@ _rt_hw_interrupt_enable: .asmfunc _rt_hw_context_switch_interrupt: -_rt_hw_context_switch: MOVL XAR0, #0 MOV AR0, AL MOVL XAR4, *-SP[4] - ; set rt_thread_switch_interrupt_flag to 1 + ; set rt_thread_switch_interrupt_flag to 1 MOVL XAR5, #_rt_thread_switch_interrupt_flag MOVL XAR6, *XAR5 MOVL ACC, XAR6 @@ -114,6 +119,36 @@ _reswitch: MOVL XAR5, #_rt_interrupt_to_thread ; set rt_interrupt_to_thread MOVL *XAR5, XAR4 + LRETR + .endasmfunc + +; +; void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; r0 --> from +; r4 --> to + + + .asmfunc +_rt_hw_context_switch: + MOVL XAR0, #0 + MOV AR0, AL + MOVL XAR4, *-SP[4] + ; set rt_thread_switch_interrupt_flag to 1 + MOVL XAR5, #_rt_thread_switch_interrupt_flag + MOVL XAR6, *XAR5 + MOVL ACC, XAR6 + CMPB AL, #1 + B _reswitch2, EQ + MOVL XAR6, #1 + MOVL *XAR5, XAR6 + + MOVL XAR5, #_rt_interrupt_from_thread ; set rt_interrupt_from_thread + MOVL *XAR5, XAR0 + +_reswitch2: + MOVL XAR5, #_rt_interrupt_to_thread ; set rt_interrupt_to_thread + MOVL *XAR5, XAR4 + TRAP #16 LRETR .endasmfunc @@ -139,8 +174,6 @@ _RTOSINT_Handler: MOV AR1, AL CMP AR1, #0 B switch_to_thread, EQ ; skip register save at the first time - - ;MOVZ AR1, @SP ; get from thread stack pointer ;#if defined (__VFP_FP__) && !defined(__SOFTFP__) ; TST lr, #0x10 ; if(!EXC_RETURN[4]) @@ -159,9 +192,9 @@ _RTOSINT_Handler: ;#endif MOV AL, *AR0 - MOV AR1, AL + MOV AR0, AL MOVZ AR1, @SP ; get from thread stack pointer - MOV *AR0, AR1 ; update from thread stack pointer + MOV *AR0, AR1 ; update from thread stack pointer switch_to_thread: MOV AR1, #_rt_interrupt_to_thread @@ -175,7 +208,7 @@ switch_to_thread: ;#endif MOV @SP, AR1 - INC SP + RT_CTX_RESTORE ; pop r4 - r11 register rtosint_exit: @@ -199,6 +232,25 @@ _rt_hw_get_st1: LRETR .endasmfunc +; C28x do not have a build-in "__ffs" func in its C compiler. +; We can use the "Count Sign Bits" (CSB) instruction to make one. +; CSB will return the number of 0's minus 1 above the highest set bit. +; The count is placed in T. For example: +; ACC T maxbit +; 0x00000001 30 0 +; 0x00000010 26 4 +; 0x000001FF 22 8 +; 0x000001F0 22 8 + .asmfunc +_rt_hw_calc_csb: + MOV AH, #0 + CSB ACC ; T = no. of sign bits - 1 + MOVU ACC, T ; ACC = no. of sign bits - 1 + SUBB ACC, #30 ; ACC = ACC - 30 + ABS ACC ; ACC = |ACC| + lretr + .endasmfunc + ; ; * void rt_hw_context_switch_to(rt_uint32 to); ; * r0 --> to diff --git a/libcpu/ti-dsp/c28x/cpuport.c b/libcpu/ti-dsp/c28x/cpuport.c index 8885f647a9..3f88606c65 100644 --- a/libcpu/ti-dsp/c28x/cpuport.c +++ b/libcpu/ti-dsp/c28x/cpuport.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2018-09-01 xuzhuoyi the first version. + * 2019-07-03 zhaoxiaowei add support for __rt_ffs. */ #include <rtthread.h> @@ -17,6 +18,10 @@ rt_uint32_t rt_thread_switch_interrupt_flag; /* exception hook */ static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL; +extern rt_uint16_t rt_hw_get_st0(void); +extern rt_uint16_t rt_hw_get_st1(void); +extern int rt_hw_calc_csb(int value); + struct exception_stack_frame { rt_uint32_t t_st0; @@ -59,6 +64,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, stk = stack_addr; stk = (rt_uint8_t *)RT_ALIGN((rt_uint32_t)stk, 8); //stk -= sizeof(struct stack_frame); + stk += 1; stack_frame = (struct stack_frame *)stk; @@ -72,7 +78,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, stack_frame->exception_stack_frame.acc = 0x33332222; stack_frame->exception_stack_frame.ar1_ar0 = 0x00001111 & (unsigned long)parameter; /* ar0 : argument */ stack_frame->exception_stack_frame.p = 0x55554444; /* p */ - stack_frame->exception_stack_frame.dp_st1 = (0x00000000) | rt_hw_get_st1(); /* dp_st1 */ + stack_frame->exception_stack_frame.dp_st1 = (0x00000000) | rt_hw_get_st1() & 0xFFFFFFFE; /* dp_st1 */ stack_frame->exception_stack_frame.dbgstat_ier = 0; /* dbgstat_ier */ stack_frame->exception_stack_frame.return_address = (unsigned long)tentry; /* return_address */ stack_frame->rpc = (unsigned long)texit; @@ -98,6 +104,19 @@ struct exception_info struct stack_frame stack_frame; }; +#ifdef RT_USING_CPU_FFS +/* + * This function called rt_hw_calc_csb to finds the first bit set in value. + * rt_hw_calc_csb is a native assembly program that use "CSB" instruction in C28x. + * When you use this function, remember that "int" is only 16-bit in C28x's C compiler. + * If value is a number bigger that 0xFFFF, trouble may be caused. + * Maybe change "int __rt_ffs(int value)" to "rt_int32_t __rt_ffs(rt_int32_t value)" will be better. + */ +int __rt_ffs(int value) +{ + return rt_hw_calc_csb(value); +} +#endif /** * shutdown CPU diff --git a/libcpu/unicore32/SConscript b/libcpu/unicore32/SConscript new file mode 100644 index 0000000000..4f1441895c --- /dev/null +++ b/libcpu/unicore32/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +group = [] +list = os.listdir(cwd) + +# cpu porting code files +group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) + +Return('group') diff --git a/libcpu/unicore32/sep6200/SConscript b/libcpu/unicore32/sep6200/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/unicore32/sep6200/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/v850/70f34/SConscript b/libcpu/v850/70f34/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/v850/70f34/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') diff --git a/libcpu/v850/SConscript b/libcpu/v850/SConscript new file mode 100644 index 0000000000..4f1441895c --- /dev/null +++ b/libcpu/v850/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +group = [] +list = os.listdir(cwd) + +# cpu porting code files +group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) + +Return('group') diff --git a/libcpu/xilinx/SConscript b/libcpu/xilinx/SConscript new file mode 100644 index 0000000000..4f1441895c --- /dev/null +++ b/libcpu/xilinx/SConscript @@ -0,0 +1,15 @@ +# RT-Thread building script for bridge + +import os +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +group = [] +list = os.listdir(cwd) + +# cpu porting code files +group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) + +Return('group') diff --git a/libcpu/xilinx/microblaze/SConscript b/libcpu/xilinx/microblaze/SConscript new file mode 100644 index 0000000000..b0ae20ba02 --- /dev/null +++ b/libcpu/xilinx/microblaze/SConscript @@ -0,0 +1,14 @@ +# RT-Thread building script for component + +from building import * + +Import('rtconfig') + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] +ASFLAGS = '' + +group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) + +Return('group') |