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-rw-r--r--libcpu/aarch64/common/cache.h1
-rw-r--r--libcpu/aarch64/common/trap.c7
-rw-r--r--libcpu/arm/cortex-a/mmu.c21
-rw-r--r--libcpu/arm/cortex-a/mmu.h1
-rw-r--r--libcpu/arm/cortex-a/trap.c6
-rw-r--r--libcpu/risc-v/t-head/c906/trap.c6
-rw-r--r--libcpu/risc-v/virt64/cache.h2
-rw-r--r--libcpu/risc-v/virt64/trap.c6
8 files changed, 34 insertions, 16 deletions
diff --git a/libcpu/aarch64/common/cache.h b/libcpu/aarch64/common/cache.h
index 86f5e84ea4..e94e4b65da 100644
--- a/libcpu/aarch64/common/cache.h
+++ b/libcpu/aarch64/common/cache.h
@@ -26,7 +26,6 @@ static inline void rt_hw_icache_invalidate_all(void)
__asm_invalidate_icache_all();
}
-void rt_hw_icache_invalidate_range(unsigned long start_addr, int size);
void rt_hw_cpu_icache_invalidate(void *addr, rt_size_t size);
void rt_hw_cpu_dcache_clean_and_invalidate(void *addr, rt_size_t size);
diff --git a/libcpu/aarch64/common/trap.c b/libcpu/aarch64/common/trap.c
index 7527440f9f..59378d08e4 100644
--- a/libcpu/aarch64/common/trap.c
+++ b/libcpu/aarch64/common/trap.c
@@ -90,6 +90,7 @@ int check_user_stack(unsigned long esr, struct rt_hw_exp_stack *regs)
break;
case 0x21:
case 0x24:
+ case 0x25:
fault_op = MM_FAULT_OP_WRITE;
fault_type = _get_type(esr);
break;
@@ -101,12 +102,12 @@ int check_user_stack(unsigned long esr, struct rt_hw_exp_stack *regs)
if (fault_op)
{
asm volatile("mrs %0, far_el1":"=r"(dfar));
- struct rt_mm_fault_msg msg = {
+ struct rt_aspace_fault_msg msg = {
.fault_op = fault_op,
.fault_type = fault_type,
- .vaddr = dfar,
+ .fault_vaddr = dfar,
};
- if (rt_mm_fault_try_fix(&msg))
+ if (rt_aspace_fault_try_fix(&msg))
{
ret = 1;
}
diff --git a/libcpu/arm/cortex-a/mmu.c b/libcpu/arm/cortex-a/mmu.c
index ed96e96d18..c573611616 100644
--- a/libcpu/arm/cortex-a/mmu.c
+++ b/libcpu/arm/cortex-a/mmu.c
@@ -11,6 +11,10 @@
#include <rthw.h>
#include <rtthread.h>
+#define DBG_TAG "hw.mmu"
+#define DBG_LVL DBG_LOG
+#include <rtdbg.h>
+
#include <board.h>
#include "cp15.h"
#include "mm_page.h"
@@ -55,11 +59,26 @@ void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd,
void rt_hw_init_mmu_table(struct mem_desc *mdesc, rt_uint32_t size)
{
+ void *vaddr;
+ size_t length;
+ /* init kernel space */
+#ifdef RT_USING_SMART
+ rt_aspace_init(&rt_kernel_space, (void *)USER_VADDR_TOP, -USER_VADDR_TOP, (void *)MMUTable);
+#else
+ rt_aspace_init(&rt_kernel_space, (void *)0x1000, 0 - 0x1000, (void *)MMUTable);
+#endif /* RT_USING_SMART */
+
/* set page table */
for(; size > 0; size--)
{
if (mdesc->paddr_start == (rt_uint32_t)ARCH_MAP_FAILED)
mdesc->paddr_start = mdesc->vaddr_start + PV_OFFSET;
+
+ vaddr = (void *)mdesc->vaddr_start;
+ length = mdesc->vaddr_end - mdesc->vaddr_start;
+ rt_aspace_map_static(&rt_kernel_space, &mdesc->varea, &vaddr, length,
+ mdesc->attr, MMF_MAP_FIXED, &rt_mm_dummy_mapper, 0);
+
rt_hw_mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end,
mdesc->paddr_start, mdesc->attr);
mdesc++;
@@ -123,12 +142,10 @@ int rt_hw_mmu_map_init(struct rt_aspace *aspace, void* v_address, size_t size, s
}
#ifdef RT_USING_SMART
- rt_aspace_init(&rt_kernel_space, (void *)USER_VADDR_TOP, 0 - USER_VADDR_TOP, vtable);
rt_ioremap_start = v_address;
rt_ioremap_size = size;
rt_mpr_start = rt_ioremap_start - rt_mpr_size;
#else
- rt_aspace_init(&rt_kernel_space, (void *)0x1000, 0 - 0x1000, vtable);
rt_mpr_start = (void *)0 - rt_mpr_size;
#endif
diff --git a/libcpu/arm/cortex-a/mmu.h b/libcpu/arm/cortex-a/mmu.h
index 2d09c1281d..61b47a9402 100644
--- a/libcpu/arm/cortex-a/mmu.h
+++ b/libcpu/arm/cortex-a/mmu.h
@@ -52,6 +52,7 @@ struct mem_desc
rt_uint32_t vaddr_end;
rt_uint32_t paddr_start;
rt_uint32_t attr;
+ struct rt_varea varea;
};
#define MMU_MAP_MTBL_XN (1<<0)
diff --git a/libcpu/arm/cortex-a/trap.c b/libcpu/arm/cortex-a/trap.c
index 425e51b9d0..0aafa55968 100644
--- a/libcpu/arm/cortex-a/trap.c
+++ b/libcpu/arm/cortex-a/trap.c
@@ -50,12 +50,12 @@ int check_user_stack(struct rt_hw_exp_stack *regs)
if ((dfar >= (void *)USER_STACK_VSTART) && (dfar < (void *)USER_STACK_VEND))
{
- struct rt_mm_fault_msg msg = {
+ struct rt_aspace_fault_msg msg = {
.fault_op = MM_FAULT_OP_WRITE,
.fault_type = MM_FAULT_TYPE_PAGE_FAULT,
- .vaddr = dfar,
+ .fault_vaddr = dfar,
};
- if (rt_mm_fault_try_fix(&msg))
+ if (rt_aspace_fault_try_fix(&msg))
{
regs->pc -= 8;
return 1;
diff --git a/libcpu/risc-v/t-head/c906/trap.c b/libcpu/risc-v/t-head/c906/trap.c
index 2600ee0c37..c95facb0f7 100644
--- a/libcpu/risc-v/t-head/c906/trap.c
+++ b/libcpu/risc-v/t-head/c906/trap.c
@@ -203,13 +203,13 @@ void handle_user(rt_size_t scause, rt_size_t stval, rt_size_t sepc, struct rt_hw
if (fault_op)
{
- struct rt_mm_fault_msg msg = {
+ struct rt_aspace_fault_msg msg = {
.fault_op = fault_op,
.fault_type = fault_type,
- .vaddr = (void *)stval,
+ .fault_vaddr = (void *)stval,
};
- if (rt_mm_fault_try_fix(&msg))
+ if (rt_aspace_fault_try_fix(&msg))
{
return;
}
diff --git a/libcpu/risc-v/virt64/cache.h b/libcpu/risc-v/virt64/cache.h
index 5b625a37d5..5529e02458 100644
--- a/libcpu/risc-v/virt64/cache.h
+++ b/libcpu/risc-v/virt64/cache.h
@@ -48,7 +48,7 @@ ALWAYS_INLINE void rt_hw_cpu_icache_invalidate_all_local() {}
#define rt_hw_icache_invalidate_all rt_hw_cpu_icache_invalidate_all
/** instruction barrier */
-void rt_hw_cpu_sync(void);
+static inline void rt_hw_cpu_sync(void) {}
/**
* @brief local cpu icahce & dcache synchronization
diff --git a/libcpu/risc-v/virt64/trap.c b/libcpu/risc-v/virt64/trap.c
index b9f30ed715..944cee629a 100644
--- a/libcpu/risc-v/virt64/trap.c
+++ b/libcpu/risc-v/virt64/trap.c
@@ -200,13 +200,13 @@ void handle_user(rt_size_t scause, rt_size_t stval, rt_size_t sepc, struct rt_hw
if (fault_op)
{
- struct rt_mm_fault_msg msg = {
+ struct rt_aspace_fault_msg msg = {
.fault_op = fault_op,
.fault_type = fault_type,
- .vaddr = (void *)stval,
+ .fault_vaddr = (void *)stval,
};
- if (rt_mm_fault_try_fix(&msg))
+ if (rt_aspace_fault_try_fix(&msg))
{
return;
}
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-30 15:56:13 +0000