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Otherwise report runtime error:
[E/kernel.obj] Object name sys workq exceeds RT_NAME_MAX=8, consider increasing RT_NAME_MAX.
(obj_name_len <= RT_NAME_MAX - 1) assertion failed at function:rt_object_allocate, line number:520
Increase the value of RT_NAME_MAX to 16 for c906B.
The value of RT_NAME_MAX for BSP of C906L and ARM core already meet
the requirement of more than 8.
Signed-off-by: Chen Wang <[email protected]>
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Regarding link script, some memory offsets and sizes are different
between the standard version and the smart version (such as
"__STACKSIZE__", kernel start address, kernel memory size, etc.).
Original solution is replacing link scripts and use INCLUDE,
which is relatively complicated.
This improvement uses macros to replace constants in the link
script. The preprocessing mechanism provided by gcc is used
to dynamically replace constant values during the build process.
In addition, the kernel load address (the corresponding
KERNEL_VADDR_START for smart) was originally configured as
0xFFFFFFC000200000, which is default value of riscv with
kernelmap enabled (0xffffffc000000000) plus offset to skip over
bootloader (0x200000). This caused a trouble: due to
default bsp configuration is for smart, if we switched to the
standard version and build, and then switched back to the smart
version, the value of KERNEL_VADDR_START will be default back to
0xffffffc000000000, which is different from the original configuration
value, resulting in the need to manually reconfigure it, which
is easy to forget and cause problems.
The current solution is to use the default value
0xffffffc000000000 in the configuration. Add offset to the code
and link script when using it.
This patch update the default .config and rtconfig.h for cv18xx_riscv.
Signed-off-by: Chen Wang <[email protected]>
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Confirmed with milkv, only the sd card version is sold
by default for duo in the market. The spi pins are
provided through stamp holes, so that users can solder
the corresponding components on their baseboard during
secondary development.
In order to simplify maintenance work, the mainline
will only support the sd-card version and no longer
support spinor/spinand.
Updated config files the same in this patch.
Signed-off-by: Chen Wang <[email protected]>
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ROMFS is Read-Only Memory Filesystem. But ext4/fat are not read-only.
So renamed:
- mnt_romfs.c -> mnt_diskfs.c
- BSP_ROOTFS_TYPE_ROMFS -> BSP_ROOTFS_TYPE_DISKFS
Signed-off-by: Chen Wang <[email protected]>
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1. switches memory management to SLA
2. use ioremap modification driver
Signed-off-by: flyingcys [email protected]
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1. 修改 ENABLE_FPU 为 ARCH_RISCV_FPU，与libcpu/common 保持统一
2. 对 bsp/cvitek/cv18xx_risc-v 中增加使能 ARCH_RISCV_FPU 的动作。解决了 issue #9075
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Analysis: Some macro definition names are not standardized
and lack prefixes.
Solution: Add BSP_ prefix to GPIO_IRQ_BASE SYS_GPIO_IRQ_BASE
PLIC_PHY_ADDR TIMER_CLK_FREQ UART_IRQ_BASE I2C_IRQ_BASE.
Signed-off-by: Shicheng Chu <[email protected]>
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Analysis: The IRQ_MAX_NR value of cv18xx_risc-v is wrong.
The wrong IRQ_MAX_NR will cause the install of an interrupt
number larger than its value to fail.
Solution: Change IRQ_MAX_NR to the correct value 101 in
the datasheet.
Signed-off-by: Shicheng Chu <[email protected]>
Reviewed-by: Chen Wang <[email protected]>
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Changes:
- board.c: add static assert for KERNEL_VADDR_START to check if it's valid
- board.h: updated deafult KERNEL_VADDR_START for standard version
- config bsp for v5.2.0 smart requirements
- kconfig: update bsp Kconfig for remap kernel
Signed-off-by: Shell <[email protected]>
Reviewed-on: https://github.com/RT-Thread/rt-thread/pull/9229
Reviewed-by: Chen Wang <[email protected]>
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In the original Sconstruct script, `GetDepend('__STACKSIZE__')`
is placed before the call to `PrepareBuilding()`, which causes
the value of `GetDepend('__STACKSIZE__')` to always be False,
and the value of `__STACKSIZE__` in `link_stacksize.lds` will
not be updated.
Solution: move the call if `PrepareBuilding()` ahead.
Also sync and update the .config and rtconfig.h, plus the
link_stacksize.lds.
Signed-off-by: Chen Wang <[email protected]>
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Board level UART pinmux summary, following capability
should be controlled by pinname whitelist.
Duo:
NAME UART CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX
GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX
GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX
GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX
GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX
GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX
GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX
GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX
GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX
GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX
GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX
GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX
GP3 UART4_RX PWR_GPIO[25] SD1_GPIO0__UART4_RX
GP2 UART4_TX PWR_GPIO[26] SD1_GPIO1__UART4_TX
Duo 256m:
NAME UART CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX
GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX
GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX
GP3 UART1_RX XGPIOA[18] JTAG_CPU_TCK__UART1_RX
GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX
GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX
GP2 UART1_TX XGPIOA[19] JTAG_CPU_TMS__UART1_TX
GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX
GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX
GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX
GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX
GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX
GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX
GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX
Note: this patch also update the .config and rtconfig.h
because this patch modify some configuration items's name,
for example: RT_USIMG_UART0 -> BSP_USING_UART0.
FIXME: only handle RISC-V related, no ARM.
Signed-off-by: Chen Wang <[email protected]>
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The changes unify the tick.c implementations for all risc-v64
architectures, leveraging the CPUTIME feature. This refactoring was
necessary to streamline the codebase, and ensure consistent timer
handling across different platforms.
Changes:
- Updated `Kconfig` in `bsp/cvitek/cv18xx_risc-v` to fix formatting issues.
- Updated .config for BSPs to update `CPUTIME_TIMER_FREQ`
- Updated header of for API `riscv_cputime_init`
- Initialized riscv timer on `rt_hw_tick_init`
- Refactored `tick.c` and `tick.h` in `libcpu/risc-v/t-head/c906` and `libcpu/risc-v/virt64`:
- Replaced direct use of `rdtime` with `clock_cpu_gettime`.
- Removed redundant timer frequency definitions.
- Added static assertions to check the value of `CPUTIME_TIMER_FREQ`.
- Initialized `tick_cycles` based on `CPUTIME_TIMER_FREQ`.
- Integrated `ktime` support for tick initialization.
Signed-off-by: Shell <[email protected]>
Reviewed-on: https://github.com/RT-Thread/rt-thread/pull/9164
Reviewed-by: Chen Wang <[email protected]>
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support cvitek sdhci drvier
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update cv18xx series README.md
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