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Otherwise report runtime error:
[E/kernel.obj] Object name sys workq exceeds RT_NAME_MAX=8, consider increasing RT_NAME_MAX.
(obj_name_len <= RT_NAME_MAX - 1) assertion failed at function:rt_object_allocate, line number:520
Increase the value of RT_NAME_MAX to 16 for c906B.
The value of RT_NAME_MAX for BSP of C906L and ARM core already meet
the requirement of more than 8.
Signed-off-by: Chen Wang <[email protected]>
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Regarding link script, some memory offsets and sizes are different
between the standard version and the smart version (such as
"__STACKSIZE__", kernel start address, kernel memory size, etc.).
Original solution is replacing link scripts and use INCLUDE,
which is relatively complicated.
This improvement uses macros to replace constants in the link
script. The preprocessing mechanism provided by gcc is used
to dynamically replace constant values during the build process.
In addition, the kernel load address (the corresponding
KERNEL_VADDR_START for smart) was originally configured as
0xFFFFFFC000200000, which is default value of riscv with
kernelmap enabled (0xffffffc000000000) plus offset to skip over
bootloader (0x200000). This caused a trouble: due to
default bsp configuration is for smart, if we switched to the
standard version and build, and then switched back to the smart
version, the value of KERNEL_VADDR_START will be default back to
0xffffffc000000000, which is different from the original configuration
value, resulting in the need to manually reconfigure it, which
is easy to forget and cause problems.
The current solution is to use the default value
0xffffffc000000000 in the configuration. Add offset to the code
and link script when using it.
This patch update the default .config and rtconfig.h for cv18xx_riscv.
Signed-off-by: Chen Wang <[email protected]>
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Based on the patch "bsp: cvitek: use rttpkgtool
to replace cvitek_bootloader", continue cleanup useless files.
Signed-off-by: Chen Wang <[email protected]>
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Originally, for riscv big and little cores under bsp/cvitek,
after generating rtthread.bin, the cvitek_bootloader tool
would be used to package it and generate fip.bin and boot.sd
files that can be burned into sdcard. However, the
cvitek_bootloader tool repository is relatively large, and
it compiles and generates firmware such as fsbl, opensbi and
uboot from the source code level. And when using it, it
needs to be downloaded to the bsp/cvitek directory, which
will introduce pollution to source files in the RTT repository
under the original working path.
The new solution uses rttpkgtool, which is similar to
cvitek_bootloader, but it uses prebuilt firmware, so it is
very small and does not introduce pollution to the source file.
Signed-off-by: Chen Wang <[email protected]>
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Duo's CPU combination is more complicated:
| BSP | B/L core| ISA | UART |
| ------------- | ------- |---------------- |-------|
| cv18xx_risc-v | Big | RISC-V C906 | UART0 |
| c906-little | Littel | RISC-V C906 | UART1 |
| cv18xx_aarch64| Big | ARM Cortex A53 | UART0 |
Printing ISA and big and small core information
during the boot process helps developers/testers
determine the CPU and serial port corresponding to
the current console.
In addition, the RTT logo printing has already
distinguished whether it is smart, so the bsp
printing no longer distinguishes.
Updated README to sync with this change.
Signed-off-by: Chen Wang <[email protected]>
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Confirmed with milkv, only the sd card version is sold
by default for duo in the market. The spi pins are
provided through stamp holes, so that users can solder
the corresponding components on their baseboard during
secondary development.
In order to simplify maintenance work, the mainline
will only support the sd-card version and no longer
support spinor/spinand.
Updated config files the same in this patch.
Signed-off-by: Chen Wang <[email protected]>
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ROMFS is Read-Only Memory Filesystem. But ext4/fat are not read-only.
So renamed:
- mnt_romfs.c -> mnt_diskfs.c
- BSP_ROOTFS_TYPE_ROMFS -> BSP_ROOTFS_TYPE_DISKFS
Signed-off-by: Chen Wang <[email protected]>
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1. switches memory management to SLA
2. use ioremap modification driver
Signed-off-by: flyingcys [email protected]
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CV18xx RISC-V C906L.
Configuration value for CPU and ARCH are already defined in rtconfig.py.
Remove these duplication from SConstruct.
Signed-off-by: Chen Wang <[email protected]>
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Supports both big and little cores of RISC-V C906,
but does not support ARM cores. Currently, only UART
drivers are supported on the peripherals.
Signed-off-by: Shicheng Chu <[email protected]>
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1. 修改 ENABLE_FPU 为 ARCH_RISCV_FPU，与libcpu/common 保持统一
2. 对 bsp/cvitek/cv18xx_risc-v 中增加使能 ARCH_RISCV_FPU 的动作。解决了 issue #9075
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Signed-off-by: Shicheng Chu <[email protected]>
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Analysis: Some macro definition names are not standardized
and lack prefixes.
Solution: Add BSP_ prefix to GPIO_IRQ_BASE SYS_GPIO_IRQ_BASE
PLIC_PHY_ADDR TIMER_CLK_FREQ UART_IRQ_BASE I2C_IRQ_BASE.
Signed-off-by: Shicheng Chu <[email protected]>
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For bsp/cvitek, all drivers related files are moved to the directory
bsp/cvitek/drivers, so the drivers_path_prefix processing in the
SConstruct of the three bsp projects can be simplified.
Signed-off-by: Chen Wang <[email protected]>
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Analysis: The IRQ_MAX_NR value of cv18xx_risc-v is wrong.
The wrong IRQ_MAX_NR will cause the install of an interrupt
number larger than its value to fail.
Solution: Change IRQ_MAX_NR to the correct value 101 in
the datasheet.
Signed-off-by: Shicheng Chu <[email protected]>
Reviewed-by: Chen Wang <[email protected]>
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Changes:
- board.c: add static assert for KERNEL_VADDR_START to check if it's valid
- board.h: updated deafult KERNEL_VADDR_START for standard version
- config bsp for v5.2.0 smart requirements
- kconfig: update bsp Kconfig for remap kernel
Signed-off-by: Shell <[email protected]>
Reviewed-on: https://github.com/RT-Thread/rt-thread/pull/9229
Reviewed-by: Chen Wang <[email protected]>
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To support more choice on bootfs. romfs, cromfs are now supported on
risc_v_big platform.
Changes:
- added mount operations under port
- added prototypes for cromfs init APIs
Signed-off-by: Shell <[email protected]>
Reviewed-on: https://github.com/RT-Thread/rt-thread/pull/9229
Reviewed-by: Chen Wang <[email protected]>
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In the original Sconstruct script, `GetDepend('__STACKSIZE__')`
is placed before the call to `PrepareBuilding()`, which causes
the value of `GetDepend('__STACKSIZE__')` to always be False,
and the value of `__STACKSIZE__` in `link_stacksize.lds` will
not be updated.
Solution: move the call if `PrepareBuilding()` ahead.
Also sync and update the .config and rtconfig.h, plus the
link_stacksize.lds.
Signed-off-by: Chen Wang <[email protected]>
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Currently, the documents under bsp/cvitek are a bit
messy. There are currently four readme files:
- bsp/cvitek/README.md (Chinese)
- bsp/cvitek/c906_little/README.md (Chinese/English)
- bsp/cvitek/cv18xx_aarch64/README.md (Chinese)
- bsp/cvitek/cv18xx_risc-v/README.md (Chinese/English)
Regarding the working mode of the big + small cores, it
is meaningless to describe the small core alone, or the
large core alone. This can also be seen in the existing
files. The readme of the small core will also introduce
the programming of the large core, and vice versa.
Considering that the official default mode is
C906B + C906L. ARM large core can be treataed as a
special case. So the document structure is modified as
follows:
- Remove `bsp/cvitek/c906_little/README.md` and
`bsp/cvitek/cv18xx_risc-v/README.md`, merge them all
into `bsp/cvitek/README.md`
- Add a link to `bsp/cvitek/cv18xx_aarch64/README.md`
in `bsp/cvitek/README.md`
FIXME: The modified document does not provide English
version. Is it really necessary?
Signed-off-by: Chen Wang <[email protected]>
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Signed-off-by: Chen Wang <[email protected]>
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Board level pin available info:
duo & duo256:
NAME SPI CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP6 SPI2_SCK PWR_GPIO[23] SD1_CLK__SPI2_SCK
GP7 SPI2_SDO PWR_GPIO[22] SD1_CMD__SPI2_SDO
GP8 SPI2_SDI PWR_GPIO[21] SD1_D0__SPI2_SDI
GP9 SPI2_CS_X PWR_GPIO[18] SD1_D3__SPI2_CS_X
Signed-off-by: Chen Wang <[email protected]>
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Board level pin available info is summarized and list here for memo:
Duo:
NAME PWM CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
PWM-1
GP9 PWM4 PWR_GPIO[18] SD1_D3__PWM_4
GP12 PWM4 XGPIOA[16] UART0_TX__PWM_4
GP4 PWM5 PWR_GPIO[19] SD1_D2__PWM_5
GP13 PWM5 XGPIOA[17] UART0_RX__PWM_5
GP5 PWM6 PWR_GPIO[20] SD1_D1__PWM_6
GP8 PMW7 PWR_GPIO[21] SD1_D0__PWM_7
PWM-2
GP7 PWM8 PWR_GPIO[22] SD1_CMD__PWM_8
GP6 PWM9 PWR_GPIO[23] SD1_CLK__PWM_9
GP2 PWM10 PWR_GPIO[26] SD1_GPIO1__PWM_10
GP3 PWM11 PWR_GPIO[25] SD1_GPIO0__PWM_11
Duo256:
NAME PWM CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
PWM-1
GP9 PWM4 PWR_GPIO[18] SD1_D3__PWM_4
GP12 PWM4 XGPIOA[16] UART0_TX__PWM_4
GP4 PWM5 PWR_GPIO[19] SD1_D2__PWM_5
GP13 PWM5 XGPIOA[17] UART0_RX__PWM_5
GP3 PWM6 XGPIOA[18] JTAG_CPU_TCK__PWM_6
GP5 PWM6 PWR_GPIO[20] SD1_D1__PWM_6
GP2 PWM7 XGPIOA[19] JTAG_CPU_TMS__PWM_7
GP8 PMW7 PWR_GPIO[21] SD1_D0__PWM_7
PWM-2
GP7 PWM8 PWR_GPIO[22] SD1_CMD__PWM_8
GP6 PWM9 PWR_GPIO[23] SD1_CLK__PWM_9
GP10 PWM10 XGPIOC[14] PAD_MIPI_TXM1__PWM_10
GP11 PWM11 XGPIOC[15] PAD_MIPI_TXP1__PWM_11
Signed-off-by: Chen Wang <[email protected]>
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Board level UART pinmux summary, following capability
should be controlled by pinname whitelist.
Duo:
NAME UART CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX
GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX
GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX
GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX
GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX
GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX
GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX
GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX
GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX
GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX
GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX
GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX
GP3 UART4_RX PWR_GPIO[25] SD1_GPIO0__UART4_RX
GP2 UART4_TX PWR_GPIO[26] SD1_GPIO1__UART4_TX
Duo 256m:
NAME UART CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX
GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX
GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX
GP3 UART1_RX XGPIOA[18] JTAG_CPU_TCK__UART1_RX
GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX
GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX
GP2 UART1_TX XGPIOA[19] JTAG_CPU_TMS__UART1_TX
GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX
GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX
GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX
GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX
GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX
GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX
GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX
Note: this patch also update the .config and rtconfig.h
because this patch modify some configuration items's name,
for example: RT_USIMG_UART0 -> BSP_USING_UART0.
FIXME: only handle RISC-V related, no ARM.
Signed-off-by: Chen Wang <[email protected]>
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Based on new pinmux framework, add configuration for uart.
Board level pin available info is summarized and should be
controlled by pin whitelist.
Duo
NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP0 I2C0_SCL XGPIOA[28] IIC0_SCL__IIC0_SCL
GP1 I2C0_SDA XGPIOA[29] IIC0_SDA__IIC0_SDA
GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL
GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL
GP11 I2C1_SCL XGPIOC[10] PAD_MIPIRX0N__IIC1_SCL
GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA
GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA
GP10 I2C1_SDA XGPIOC[9] PAD_MIPIRX1P__IIC1_SDA
GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL
GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA
Duo256m
NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL
GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL
GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA
GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA
GP11 I2C2_SCL XGPIOC[15] PAD_MIPI_TXP1__IIC2_SCL
GP10 I2C2_SDA XGPIOC[14] PAD_MIPI_TXM1__IIC2_SDA
GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL
GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA
Duo S(Note, we have not supported duo S, just list for memo)
NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
J3-B18 I2C1_SCL XGPIOB[18] VIVO_D3__IIC1_SCL
J3-B12 I2C1_SCL XGPIOB[12] VIVO_D9__IIC1_SCL
J3-B11 I2C1_SDA XGPIOB[11] VIVO_D10__IIC1_SDA
J3-B13 I2C2_SCL XGPIOB[13] VIVO_D8__IIC2_SCL
J4-E1 I2C2_SCL PWR_GPIO[1] PWR_GPIO1__IIC2_SCL
J3-B14 I2C2_SDA XGPIOB[14] VIVO_D7__IIC2_SDA
J4-E2 I2C2_SDA PWR_GPIO[2] PWR_GPIO2__IIC2_SDA
J3-B20 I2C4_SCL XGPIOB[20] VIVO_D1__IIC4_SCL
J4-B1 I2C4_SCL XGPIOB[1] ADC3__IIC4_SCL
J3-B21 I2C4_SDA XGPIOB[21] VIVO_D0__IIC4_SDA
J4-B2 I2C4_SDA XGPIOB[2] ADC2__IIC4_SDA
Signed-off-by: Chen Wang <[email protected]>
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The contents of the SOC type part in the Kconfig configuration
are retained, and other parts related to I2C pin multiplexing
selection have been rolled back.
Signed-off-by: Chen Wang <[email protected]>
Reviewed-by: Yuanjie He <[email protected]>
Reviewed-by: Shell <[email protected]>
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The changes unify the tick.c implementations for all risc-v64
architectures, leveraging the CPUTIME feature. This refactoring was
necessary to streamline the codebase, and ensure consistent timer
handling across different platforms.
Changes:
- Updated `Kconfig` in `bsp/cvitek/cv18xx_risc-v` to fix formatting issues.
- Updated .config for BSPs to update `CPUTIME_TIMER_FREQ`
- Updated header of for API `riscv_cputime_init`
- Initialized riscv timer on `rt_hw_tick_init`
- Refactored `tick.c` and `tick.h` in `libcpu/risc-v/t-head/c906` and `libcpu/risc-v/virt64`:
- Replaced direct use of `rdtime` with `clock_cpu_gettime`.
- Removed redundant timer frequency definitions.
- Added static assertions to check the value of `CPUTIME_TIMER_FREQ`.
- Initialized `tick_cycles` based on `CPUTIME_TIMER_FREQ`.
- Integrated `ktime` support for tick initialization.
Signed-off-by: Shell <[email protected]>
Reviewed-on: https://github.com/RT-Thread/rt-thread/pull/9164
Reviewed-by: Chen Wang <[email protected]>
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* [libcpu] support for ARCH_REMAP_KERNEL
These changes introduce support for the ARCH_REMAP_KERNEL configuration,
which isolates kernel space in high virtual address regions. This feature
is necessary to enhance memory protection and management by segregating
user and kernel spaces more effectively.
Changes:
- Updated conditional macros to check for ARCH_REMAP_KERNEL instead of
ARCH_KERNEL_IN_HIGH_VA in board initialization files to reflect the new
configuration option.
- Modified qemu-virt64-riscv Kconfig and SConstruct files to include and
utilize ARCH_REMAP_KERNEL.
- Created a new linker script `link_smart.lds` for smart linking in qemu-virt64-riscv.
- Updated rtconfig.py to use a more flexible execution path setup.
- Enhanced user address space definitions in `lwp_arch.h` to support the
new virtual address mappings.
- Adjusted kernel memory initialization and mapping logic in `c906/mmu.c`
and `virt64/mmu.c` to account for high virtual address regions.
- Added Kconfig option to enable ARCH_REMAP_KERNEL for RISCV64 architectures.
- Enhanced memory setup functions to support new mapping scheme, including
updates to early page table setup and address relocation logic.
These modifications ensure that the system can utilize high memory
addresses for the kernel, improving memory isolation and system stability.
Signed-off-by: Shell <[email protected]>
* fixup: CI run failed
* bsp: default config without using smart
* fixup: static checks
* restore rt_hw_mmu_kernel_map_init for D1
---------
Signed-off-by: Shell <[email protected]>
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* bsp: cvitek: kconfig: add wdt for cv18xx_riscv
Add Watchdog timer in Kconfig.
Signed-off-by: Chen Wang <[email protected]>
* drv: cvitek: remove using macro from source file
Building of source file should be controlled by SConscript,
but not in source file itself.
Signed-off-by: Chen Wang <[email protected]>
* bsp: cvitek: kconfig: add i2c for cv18xx_riscv
Add I2C in Kconfig for c906B.
Note, the IRQ# is different from that of c906L.
Signed-off-by: Chen Wang <[email protected]>
* bsp: cvitek: kconfig: add rtc for cv18xx_riscv
Add RTC in Kconfig for c906B.
Signed-off-by: Chen Wang <[email protected]>
* bsp: cvitek: fix channel issue for pwm driver
The original code confuses the concepts of controllers and channels.
Fixed it and do some code cleanup.
Signed-off-by: Chen Wang <[email protected]>
* bsp:cvitek: add i2c pinmux config for cv18xx_riscv
Pinmux in driver code is controlled by SOC type, bcos driver
code should be general and support all pins defined by SoC.
Pinmux configuration in Kconfig is controlled by BOARD type,
bcos when we operate on board, it does not expose all chip-level
pin signals and we can only use part of them.
Following is I2C signals exported by duo family. Details see
https://milkv.io/docs/duo/overview.
Note: we have not added support for duo-S.
Duo
===
NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP0 I2C0_SCL XGPIOA[28] IIC0_SCL__IIC0_SCL
GP1 I2C0_SDA XGPIOA[29] IIC0_SDA__IIC0_SDA
GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL
GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL
GP11 I2C1_SCL XGPIOC[10] PAD_MIPIRX0N__IIC1_SCL
GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA
GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA
GP10 I2C1_SDA XGPIOC[9] PAD_MIPIRX1P__IIC1_SDA
GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL
GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA
Duo 256m
========
NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL
GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL
GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA
GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA
GP11 I2C2_SCL XGPIOC[15] PAD_MIPI_TXP1__IIC2_SCL
GP10 I2C2_SDA XGPIOC[14] PAD_MIPI_TXM1__IIC2_SDA
GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL
GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA
Duo S
=====
NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
J3-B18 I2C1_SCL XGPIOB[18] VIVO_D3__IIC1_SCL
J3-B12 I2C1_SCL XGPIOB[12] VIVO_D9__IIC1_SCL
J3-B11 I2C1_SDA XGPIOB[11] VIVO_D10__IIC1_SDA
J3-B13 I2C2_SCL XGPIOB[13] VIVO_D8__IIC2_SCL
J4-E1 I2C2_SCL PWR_GPIO[1] PWR_GPIO1__IIC2_SCL
J3-B14 I2C2_SDA XGPIOB[14] VIVO_D7__IIC2_SDA
J4-E2 I2C2_SDA PWR_GPIO[2] PWR_GPIO2__IIC2_SDA
J3-B20 I2C4_SCL XGPIOB[20] VIVO_D1__IIC4_SCL
J4-B1 I2C4_SCL XGPIOB[1] ADC3__IIC4_SCL
J3-B21 I2C4_SDA XGPIOB[21] VIVO_D0__IIC4_SDA
J4-B2 I2C4_SDA XGPIOB[2] ADC2__IIC4_SDA
Signed-off-by: Chen Wang <[email protected]>
Signed-off-by: flyingcys <[email protected]>
* bsp:cvitek: remove using macro from source file for i2c
Signed-off-by: Chen Wang <[email protected]>
* bsp:cvitek: unify menu message text for i2c as other drivers
Other dirvers has no extra word "HW".
Signed-off-by: Chen Wang <[email protected]>
* bsp:cvitek: add i2c pinmux config for c906_little
Porting what we have done in commit "bsp:cvitek: add i2c pinmux config
for cv18xx_riscv" to c906_little.
Signed-off-by: Chen Wang <[email protected]>
---------
Signed-off-by: Chen Wang <[email protected]>
Signed-off-by: flyingcys <[email protected]>
Co-authored-by: flyingcys <[email protected]>
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update gpio driver
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update cvitek sdhci drvier
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support cvitek sdhci drvier
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update cv18xx series README.md
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提交 cvitek 下大核 被gitignore 编译依赖文件
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