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Signed-off-by: flyingcys [email protected]
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See https://github.com/RT-Thread/rt-thread/issues/10138.
Signed-off-by: Chen Wang <[email protected]>
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Build error: 'struct _device_spi' has no member named 'base_addr'
Analyze: the name should be dws.regs
Solution: change base_addr to dws.regs
Signed-off-by: zdtyuiop4444 <[email protected]>
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Confirmed with milkv, only the sd card version is sold
by default for duo in the market. The spi pins are
provided through stamp holes, so that users can solder
the corresponding components on their baseboard during
secondary development.
In order to simplify maintenance work, the mainline
will only support the sd-card version and no longer
support spinor/spinand.
Updated config files the same in this patch.
Signed-off-by: Chen Wang <[email protected]>
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For ARM, RT-smart and RT-standard both enable mmc (see
rt_hw_board_init() in bsp/cvitek/cv18xx_aarch64/board/board.c,
rt_hw_mmu_setup is called both for smart or standard).
So ioremap is must to do for ARM.
Signed-off-by: Chen Wang <[email protected]>
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GPL is conflict with Apache, which is used by RTT.
See <https://www.apache.org/licenses/GPL-compatibility.html>
Also clean up and remove some words such "LINUX".
Signed-off-by: Chen Wang <[email protected]>
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When RTC is enabled, a warning appear during compiling:
warning: implicit declaration of function 'rtc_alarm_enable' [-Wimplicit-function-declaration]
366 | rtc_alarm_enable(alarm->enable);
| ^~~~~~~~~~~~~~~~
It's due to _rtc_set_alarm is not covered by RT_USING_ALARM. It's wrong.
Solution: cover all functions including _rtc_get_alarm & _rtc_set_alarm
under RT_USING_ALARM macro conditional defintion.
Signed-off-by: Chen Wang <[email protected]>
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Support mount rootfs automaticly during booting up.
First try ext, then fat.
Plus some code cleanup, such as remove BSP_USING_ON_CHIP_FLASH_FS,
which is not defined and unused.
Signed-off-by: Chen Wang <[email protected]>
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ROMFS is Read-Only Memory Filesystem. But ext4/fat are not read-only.
So renamed:
- mnt_romfs.c -> mnt_diskfs.c
- BSP_ROOTFS_TYPE_ROMFS -> BSP_ROOTFS_TYPE_DISKFS
Signed-off-by: Chen Wang <[email protected]>
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1. switches memory management to SLA
2. use ioremap modification driver
Signed-off-by: flyingcys [email protected]
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https://github.com/RT-Thread/rt-thread/pull/9420
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After first called from uart open, the dw8250_uart_configure
API cannot be called again. Otherwise, this will mess up the
device, and uart will not act properly to interrupt again.
Analysis: Configure uart device will close recive interrupte,
causing uart device to malfunction.
Solution: After configure uart device, enable the device's
recive interrupte.
Signed-off-by: Shicheng Chu <[email protected]>
Reviewed-by: Chen Wang <[email protected]>
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Signed-off-by: flyingcys <[email protected]>
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修正命令超时后触发两次信号量的问题
详解:
中断状态寄存器的BIT0仅表示sdhci处理命令完成，完成结果由其它位指示，当出错时
BIT0也会值1产生中断
Signed-off-by: heyuanjie87 <[email protected]>
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Supports both big and little cores of RISC-V C906,
but does not support ARM cores. Currently, only UART
drivers are supported on the peripherals.
Signed-off-by: Shicheng Chu <[email protected]>
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Signed-off-by: Shicheng Chu <[email protected]>
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Analysis: Some macro definition names are not standardized
and lack prefixes.
Solution: Add BSP_ prefix to GPIO_IRQ_BASE SYS_GPIO_IRQ_BASE
PLIC_PHY_ADDR TIMER_CLK_FREQ UART_IRQ_BASE I2C_IRQ_BASE.
Signed-off-by: Shicheng Chu <[email protected]>
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Cvitek adc dirver only supports one adc controller now,
but the other adc controller RTCSYS_SARADC is missing.
Signed-off-by: Shicheng Chu <[email protected]>
Reviewed-by: Chen Wang <[email protected]>
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To support more choice on bootfs. romfs, cromfs are now supported on
risc_v_big platform.
Changes:
- added mount operations under port
- added prototypes for cromfs init APIs
Signed-off-by: Shell <[email protected]>
Reviewed-on: https://github.com/RT-Thread/rt-thread/pull/9229
Reviewed-by: Chen Wang <[email protected]>
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Some drivers use INIT_BOARD_EXPORT, it is not necessary,
it is enough to use INIT_DEVICE_EXPORT for genearl drivers.
Signed-off-by: Chen Wang <[email protected]>
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bsp: cvitek: accuulated bugfixes for wdt driver
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bsp: cvitek: re-wrote spi driver
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See `components/drivers/include/drivers/watchdog.h`
maco definition of
RT_DEVICE_CTRL_WDT_GET_TIMEOUT
RT_DEVICE_CTRL_WDT_SET_TIMEOUT
RT_DEVICE_CTRL_WDT_GET_TIMELEFT
The wdt timeout time unit is defined as seconds in the API, but
the code incorrectly uses ms.
Correct this and comply with the API definition.
Signed-off-by: Chen Wang <[email protected]>
Reviewed-by: Yuanjie He <[email protected]>
Reviewed-by: Shell <[email protected]>
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Rewrote the spi driver.
Reuse the driver code from https://github.com/sophgo/cvi_alios_open,
which is Apache 2.0 licenced.
Signed-off-by: flyingcys <[email protected]>
Reviewed-by: Chen Wang <[email protected]>
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```
./bsp/cvitek/drivers/drv_wdt.c: In function '_wdt_control':
warning: assignment to 'void *' from 'unsigned int' makes pointer
from integer without a cast [-Wint-conversion]
119 | wdt_device->parent.user_data = (rt_uint32_t)(*(rt_uint32_t *)arg);
| ^
warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
122 | *(rt_uint32_t *)arg = (rt_uint32_t)wdt_device->parent.user_data;
| ^
```
Rootcasue: It's not portable to store integar in a pointer.
Solution: use global _wdt_dev to store the timeout value.
Signed-off-by: Chen Wang <[email protected]>
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Optimize the original i2c driver code.
Signed-off-by: flyingcys <[email protected]>
Reviewed-by: Chen Wang <[email protected]>
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Signed-off-by: Chen Wang <[email protected]>
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Board level pin available info:
duo & duo256:
NAME SPI CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP6 SPI2_SCK PWR_GPIO[23] SD1_CLK__SPI2_SCK
GP7 SPI2_SDO PWR_GPIO[22] SD1_CMD__SPI2_SDO
GP8 SPI2_SDI PWR_GPIO[21] SD1_D0__SPI2_SDI
GP9 SPI2_CS_X PWR_GPIO[18] SD1_D3__SPI2_CS_X
Signed-off-by: Chen Wang <[email protected]>
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Board level pin available info is summarized and list here for memo:
Duo:
NAME PWM CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
PWM-1
GP9 PWM4 PWR_GPIO[18] SD1_D3__PWM_4
GP12 PWM4 XGPIOA[16] UART0_TX__PWM_4
GP4 PWM5 PWR_GPIO[19] SD1_D2__PWM_5
GP13 PWM5 XGPIOA[17] UART0_RX__PWM_5
GP5 PWM6 PWR_GPIO[20] SD1_D1__PWM_6
GP8 PMW7 PWR_GPIO[21] SD1_D0__PWM_7
PWM-2
GP7 PWM8 PWR_GPIO[22] SD1_CMD__PWM_8
GP6 PWM9 PWR_GPIO[23] SD1_CLK__PWM_9
GP2 PWM10 PWR_GPIO[26] SD1_GPIO1__PWM_10
GP3 PWM11 PWR_GPIO[25] SD1_GPIO0__PWM_11
Duo256:
NAME PWM CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
PWM-1
GP9 PWM4 PWR_GPIO[18] SD1_D3__PWM_4
GP12 PWM4 XGPIOA[16] UART0_TX__PWM_4
GP4 PWM5 PWR_GPIO[19] SD1_D2__PWM_5
GP13 PWM5 XGPIOA[17] UART0_RX__PWM_5
GP3 PWM6 XGPIOA[18] JTAG_CPU_TCK__PWM_6
GP5 PWM6 PWR_GPIO[20] SD1_D1__PWM_6
GP2 PWM7 XGPIOA[19] JTAG_CPU_TMS__PWM_7
GP8 PMW7 PWR_GPIO[21] SD1_D0__PWM_7
PWM-2
GP7 PWM8 PWR_GPIO[22] SD1_CMD__PWM_8
GP6 PWM9 PWR_GPIO[23] SD1_CLK__PWM_9
GP10 PWM10 XGPIOC[14] PAD_MIPI_TXM1__PWM_10
GP11 PWM11 XGPIOC[15] PAD_MIPI_TXP1__PWM_11
Signed-off-by: Chen Wang <[email protected]>
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Board level UART pinmux summary, following capability
should be controlled by pinname whitelist.
Duo:
NAME UART CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX
GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX
GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX
GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX
GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX
GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX
GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX
GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX
GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX
GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX
GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX
GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX
GP3 UART4_RX PWR_GPIO[25] SD1_GPIO0__UART4_RX
GP2 UART4_TX PWR_GPIO[26] SD1_GPIO1__UART4_TX
Duo 256m:
NAME UART CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP13 UART0_RX XGPIOA[17] UART0_RX__UART0_RX
GP12 UART0_TX XGPIOA[16] UART0_TX__UART0_TX
GP1 UART1_RX XGPIOA[29] IIC0_SDA__UART1_RX
GP3 UART1_RX XGPIOA[18] JTAG_CPU_TCK__UART1_RX
GP13 UART1_RX XGPIOA[17] UART0_RX__UART1_RX
GP0 UART1_TX XGPIOA[28] IIC0_SCL__UART1_TX
GP2 UART1_TX XGPIOA[19] JTAG_CPU_TMS__UART1_TX
GP12 UART1_TX XGPIOA[16] UART0_TX__UART1_TX
GP1 UART2_RX XGPIOA[29] IIC0_SDA__UART2_RX
GP5 UART2_RX PWR_GPIO[20] SD1_D1__UART2_RX
GP0 UART2_TX XGPIOA[28] IIC0_SCL__UART2_TX
GP4 UART2_TX PWR_GPIO[19] SD1_D2__UART2_TX
GP5 UART3_RX PWR_GPIO[20] SD1_D1__UART3_RX
GP4 UART3_TX PWR_GPIO[19] SD1_D2__UART3_TX
Note: this patch also update the .config and rtconfig.h
because this patch modify some configuration items's name,
for example: RT_USIMG_UART0 -> BSP_USING_UART0.
FIXME: only handle RISC-V related, no ARM.
Signed-off-by: Chen Wang <[email protected]>
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Based on new pinmux framework, add configuration for uart.
Board level pin available info is summarized and should be
controlled by pin whitelist.
Duo
NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP0 I2C0_SCL XGPIOA[28] IIC0_SCL__IIC0_SCL
GP1 I2C0_SDA XGPIOA[29] IIC0_SDA__IIC0_SDA
GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL
GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL
GP11 I2C1_SCL XGPIOC[10] PAD_MIPIRX0N__IIC1_SCL
GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA
GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA
GP10 I2C1_SDA XGPIOC[9] PAD_MIPIRX1P__IIC1_SDA
GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL
GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA
Duo256m
NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL
GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL
GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA
GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA
GP11 I2C2_SCL XGPIOC[15] PAD_MIPI_TXP1__IIC2_SCL
GP10 I2C2_SDA XGPIOC[14] PAD_MIPI_TXM1__IIC2_SDA
GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL
GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA
Duo S(Note, we have not supported duo S, just list for memo)
NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
J3-B18 I2C1_SCL XGPIOB[18] VIVO_D3__IIC1_SCL
J3-B12 I2C1_SCL XGPIOB[12] VIVO_D9__IIC1_SCL
J3-B11 I2C1_SDA XGPIOB[11] VIVO_D10__IIC1_SDA
J3-B13 I2C2_SCL XGPIOB[13] VIVO_D8__IIC2_SCL
J4-E1 I2C2_SCL PWR_GPIO[1] PWR_GPIO1__IIC2_SCL
J3-B14 I2C2_SDA XGPIOB[14] VIVO_D7__IIC2_SDA
J4-E2 I2C2_SDA PWR_GPIO[2] PWR_GPIO2__IIC2_SDA
J3-B20 I2C4_SCL XGPIOB[20] VIVO_D1__IIC4_SCL
J4-B1 I2C4_SCL XGPIOB[1] ADC3__IIC4_SCL
J3-B21 I2C4_SDA XGPIOB[21] VIVO_D0__IIC4_SDA
J4-B2 I2C4_SDA XGPIOB[2] ADC2__IIC4_SDA
Signed-off-by: Chen Wang <[email protected]>
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The ADC controller needs to be calibrated during the initialization
phase, otherwise the measured voltage value will be inaccurate.
Signed-off-by: Chen Wang <[email protected]>
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In the new design, we require the user to manually enter the
PinName (as a string) in menuconfig instead of being given
menu items to select.
The original method will lead to too many menu item-related
macros being defined in the code, causing ifdef and other
codes scatter everywhere in the driver code, which is
inconvenient to maintain.
The new design adds a pinmux driver module to manage the
multiplexing of pins. This patch provides this driver module.
P.S., the reason why users are allowed to specify pinname
in a string instead of the pin number is mainly because
the technical manual provided by the SOC manufacturer
does not have numbers for some pins, only names.
Signed-off-by: Chen Wang <[email protected]>
Reviewed-by: Yuanjie He <[email protected]>
Reviewed-by: Shell <[email protected]>
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The contents of the SOC type part in the Kconfig configuration
are retained, and other parts related to I2C pin multiplexing
selection have been rolled back.
Signed-off-by: Chen Wang <[email protected]>
Reviewed-by: Yuanjie He <[email protected]>
Reviewed-by: Shell <[email protected]>
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ioremap后地址可能超32位
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* bsp: cvitek: kconfig: add wdt for cv18xx_riscv
Add Watchdog timer in Kconfig.
Signed-off-by: Chen Wang <[email protected]>
* drv: cvitek: remove using macro from source file
Building of source file should be controlled by SConscript,
but not in source file itself.
Signed-off-by: Chen Wang <[email protected]>
* bsp: cvitek: kconfig: add i2c for cv18xx_riscv
Add I2C in Kconfig for c906B.
Note, the IRQ# is different from that of c906L.
Signed-off-by: Chen Wang <[email protected]>
* bsp: cvitek: kconfig: add rtc for cv18xx_riscv
Add RTC in Kconfig for c906B.
Signed-off-by: Chen Wang <[email protected]>
* bsp: cvitek: fix channel issue for pwm driver
The original code confuses the concepts of controllers and channels.
Fixed it and do some code cleanup.
Signed-off-by: Chen Wang <[email protected]>
* bsp:cvitek: add i2c pinmux config for cv18xx_riscv
Pinmux in driver code is controlled by SOC type, bcos driver
code should be general and support all pins defined by SoC.
Pinmux configuration in Kconfig is controlled by BOARD type,
bcos when we operate on board, it does not expose all chip-level
pin signals and we can only use part of them.
Following is I2C signals exported by duo family. Details see
https://milkv.io/docs/duo/overview.
Note: we have not added support for duo-S.
Duo
===
NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP0 I2C0_SCL XGPIOA[28] IIC0_SCL__IIC0_SCL
GP1 I2C0_SDA XGPIOA[29] IIC0_SDA__IIC0_SDA
GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL
GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL
GP11 I2C1_SCL XGPIOC[10] PAD_MIPIRX0N__IIC1_SCL
GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA
GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA
GP10 I2C1_SDA XGPIOC[9] PAD_MIPIRX1P__IIC1_SDA
GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL
GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA
Duo 256m
========
NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
GP4 I2C1_SCL PWR_GPIO[19] SD1_D2__IIC1_SCL
GP9 I2C1_SCL PWR_GPIO[18] SD1_D3__IIC1_SCL
GP5 I2C1_SDA PWR_GPIO[20] SD1_D1__IIC1_SDA
GP8 I2C1_SDA PWR_GPIO[21] SD1_D0__IIC1_SDA
GP11 I2C2_SCL XGPIOC[15] PAD_MIPI_TXP1__IIC2_SCL
GP10 I2C2_SDA XGPIOC[14] PAD_MIPI_TXM1__IIC2_SDA
GP7 I2C3_SCL PWR_GPIO[22] SD1_CMD__IIC3_SCL
GP6 I2C3_SDA PWR_GPIO[23] SD1_CLK__IIC3_SDA
Duo S
=====
NAME I2C CV1800B/GPIO <PINNAME>__<FUNCNAME>
---- --- ------------ ---------------------
J3-B18 I2C1_SCL XGPIOB[18] VIVO_D3__IIC1_SCL
J3-B12 I2C1_SCL XGPIOB[12] VIVO_D9__IIC1_SCL
J3-B11 I2C1_SDA XGPIOB[11] VIVO_D10__IIC1_SDA
J3-B13 I2C2_SCL XGPIOB[13] VIVO_D8__IIC2_SCL
J4-E1 I2C2_SCL PWR_GPIO[1] PWR_GPIO1__IIC2_SCL
J3-B14 I2C2_SDA XGPIOB[14] VIVO_D7__IIC2_SDA
J4-E2 I2C2_SDA PWR_GPIO[2] PWR_GPIO2__IIC2_SDA
J3-B20 I2C4_SCL XGPIOB[20] VIVO_D1__IIC4_SCL
J4-B1 I2C4_SCL XGPIOB[1] ADC3__IIC4_SCL
J3-B21 I2C4_SDA XGPIOB[21] VIVO_D0__IIC4_SDA
J4-B2 I2C4_SDA XGPIOB[2] ADC2__IIC4_SDA
Signed-off-by: Chen Wang <[email protected]>
Signed-off-by: flyingcys <[email protected]>
* bsp:cvitek: remove using macro from source file for i2c
Signed-off-by: Chen Wang <[email protected]>
* bsp:cvitek: unify menu message text for i2c as other drivers
Other dirvers has no extra word "HW".
Signed-off-by: Chen Wang <[email protected]>
* bsp:cvitek: add i2c pinmux config for c906_little
Porting what we have done in commit "bsp:cvitek: add i2c pinmux config
for cv18xx_riscv" to c906_little.
Signed-off-by: Chen Wang <[email protected]>
---------
Signed-off-by: Chen Wang <[email protected]>
Signed-off-by: flyingcys <[email protected]>
Co-authored-by: flyingcys <[email protected]>
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update gpio driver
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update cvitek sdhci drvier
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support cvitek sdhci drvier
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Initialize the board using the device tree
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