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path: root/bsp/rm48x50/application/application.c
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2013-06-03rm48x50: remove useless reg_test codeGrissiom
2013-05-30rm48x50: remove unused vPortTaskUsesFPUGrissiom
2013-05-29rm48x50: add finsh supportGrissiom
2013-05-29rm48x50: now it has consoleGrissiom
2013-05-26rm48x50: add vRegTestTask2Grissiom
2013-05-26rm48x50: add reg_test from FreeRTOSGrissiom
The code is GPLv2 so I think we could use it for free(both free beer and free speech).
2013-05-24add rm48x50 bsp and libcpuGrissiom
We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.