| Age | Commit message (Collapse) | Author |
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In RT-Smart, `rt_hw_interrupt_init` will call
`rt_ioremap` to map GIC's MMIO registers. There
is a `rt_malloc` called in rt_ioremap, that will
fail if we not init the mem heap yet.
Signed-off-by: GuEe-GUI <[email protected]>
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and remvoe duplicated default functions in each cpu/bsp level
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We support OFW API to replace fdt old API, and add
IRQ, IO, Platform-Bus, CPUs ... OFW node contorl.
To support work with Device Tree or ACPI in drivers
that use IRQ, we make a programmable interrupt
controller driver's model.
Signed-off-by: GuEe-GUI <[email protected]>
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* sync and update
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* Add ADT Kconfig and fix MMU kconfig issue in Cortex-A
* [BSP] enable ADT
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synchronize virtual memory system works.
adding kernel virtual memory management layer for page-based MMU enabled architecture
porting libcpu MMU codes
porting lwp memory related codes
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* [smart/aarch64] sync aarch64
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* Synchronize the code of the rt mart branch to the master branch.
* TTY device
* Add lwP code from rt-smart
* Add vnode in DFS, but DFS will be re-write for rt-smart
* There are three libcpu for rt-smart:
* arm/cortex-a, arm/aarch64
* riscv64
Co-authored-by: Rbb666 <[email protected]>
Co-authored-by: zhkag <[email protected]>
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GCC(4.7)。
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* [libcpu/aarch64] add smp support
* [libcpu/aarch64] rt_hw_trap_irq get irq instead of iar when using gicv2
* [libcpu/aarch64] disable irq/fiq when switch thread
* [libcpu/aarch64] add gtimer frq set and stack align
* [libcpu/aarch64] add gicv3 support and bsp/rockchip/rk3568
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