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add PWM driver, output checked with logic analyzer
spi_xfer() bug fix for cs_pin and message looping
uart pin_mode init moved to uart driver
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* ch569w-evt : add spi master driver, SPI0 tested
* Update bsp/wch/risc-v/ch569w-evt/board/Kconfig
* Update bsp/wch/risc-v/ch569w-evt/board/Kconfig
Co-authored-by: Man, Jianting (Meco) <[email protected]>
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WCH CH569W-R0-1v0 evt board bsp port, first version
dev/test under Ubuntu 20.04
toolchain from MounRiver_Studio_Community_Linux_x64_V120
tested drivers : SysTick, gpio, gpio interrupt, uart1 (RX interrupt, TX polling)
libcpu/risc-v/SConscript :
group includes rtconfig.CPU only if folder exists
libcpu/risc-v/common/cpuport.c/rt_hw_context_switch_interrupt() :
make it RT_WEAK for customization
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feat: move MRS demo source to bsp and libraries folder
feat: update Sconscript
feat: modify SConstruct in the bsp
feat: use the rtconfig.py of gd32vf103v-eval bsp to modify
feat: use the MRS's rtconfig.h temoporarily
feat: update Kconfig files
feat: use the MRS's .ld and rename as link.lds
feat: add ch32v1 porting folder
perf: remove board/system_ch32v10x.c
fix: define SOC_ARM_SERIES_CH32V103 in rtconfig.h
fix: add some neccessary macros in rtconfig.h
perf: use the menuconfig to generate rtconfig.h
feat: add readme.md
fix: correct the bad encode in main.c
fix: include board.h in main.c
perf: check and update README.md
perf: remove ch32f10x_port_cn.md
feat: ignore the standard libraries's CI checking
feat: add sdk_dist.py
fix: correct some style errors again
perf: simply the board/kconfig
fix: format ch32v103r-evt
fix: format drvs and libcpu
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