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Co-authored-by: BernardXiong <[email protected]>
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* [bsp/Infineon] Fix PWM macro mismatches left by the CHx_PORTy rename
Commit e5382cb733 renamed the PWM table guards in drv_pwm.c to the
CHx_PORTy convention but only adapted the psoc6-evk Kconfig, leaving
several mismatches behind:
- The psoc6-evaluationkit-062S2 slider sample still tested the old
flat name BSP_USING_PWM0_PORT0 while the board Kconfig defines
BSP_USING_PWM0_CH0_PORT0, so the PWM init was compiled out.
- The PORT13 entry was renamed to BSP_USING_PWM0_CH7_PORT13, a macro
that no Kconfig defines, and the channel is wrong anyway:
PWM0_CH3_PORT13_CONFIG carries .channel = 3, PORT13 sits under the
PWM0 CH3 menu, and the slider demo selects CH3 + PORT13.
- The PSOC62 template and five psoc6 boards (cy8ckit-062-BLE,
cy8ckit-062-WIFI-BT, cy8ckit-062S2-43012, cy8ckit-062s4,
cy8cproto-062S3-4343W) still define the old flat names.
Fix all of them by migrating the evaluationkit sample to
BSP_USING_PWM0_CH0_PORT0 and renaming the PORT13 group to
BSP_USING_PWM0_CH3_PORT13 across drv_pwm.c, the PSOC62 template and
the five boards' Kconfigs/slider samples, so Kconfig, driver table
and samples match again.
Note: the sibling guards BSP_USING_PWM0_CH7_PORT2/5/7/9/10/12 are
still not generated by these boards' Kconfigs; left untouched for a
separate discussion.
* style: format code with clang-format [skip ci]
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Configure TX as alternate-function push-pull and RX as pull-up input on GD32E50x/F10x/F20x/F30x. Remove the GPIO API alias that incorrectly configured both pins as general-purpose push-pull outputs.
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Add the missing UART4 RX DMA definitions for STM32H7.
UART4 RX DMA uses DMA1 Stream0 with the UART4 RX DMA request.
The configuration is enabled when BSP_UART4_RX_USING_DMA is selected.
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'NAME_MAX' to 24 #11798
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将函数声明从static改为extern，解决跨文件调用时的链接错误，
确保DMA、BDMA和GPDMA类型的日志标签能够正确生成。
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The N32H7xx branch of drv_hard_i2c.c had never been compiled. The file takes
its peripheral declarations from board.h, and only n32h497zgl7-evb includes
n32h49x_i2c.h, so on H7xx every I2C symbol was undefined and the option could
not build at all. Include the peripheral header from the driver itself, the way
drv_sdram.c already does.
I2C_ABORT_ON_TIMEOUT also degraded to a bare `state = I2C_READY` on H7xx, at the
four rt_completion_wait() timeouts in n32_i2c_master_xfer(). The H49x
implementation is written against the older IP - I2C_ClrIntPendingBit,
I2C_STS2_BUSY, I2C_CTRL1_STOPGEN - none of which exist in the H7xx SDK, so give
H7xx its own teardown. It disables the interrupt and DMA request sources,
disables the DMA channel that would otherwise stay armed against the caller's
buffer, releases the bus and clears the status residue.
Only flags with a matching INTCLR bit may be passed to I2C_ClrFlag(), which is a
plain "INTCLR |= flag" write; TFC (0x40) and BUSY (0x8000) have none.
I2C_Configuration() was called from n32_i2c_init() but defined nowhere in the
tree. It is a board hook for pin mux, which is not the driver's job - the H49x
path configures no pins either - so drop the call.
Verified by building n32h760zil7-stb with BSP_USING_HARD_I2C1 and its TX/RX DMA
enabled, which now compiles and links with no warnings, and n32h497zgl7-evb with
I2C1/I2C2 DMA enabled, whose image size is unchanged. Neither board routes I2C
pins yet, so this is build-verified only, not hardware-verified.
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drv_sdram.c includes <sdram_port.h> unconditionally under BSP_USING_SDRAM,
and n32h497zgl7-evb had no such header, so the option could not build at
all. Add one for the M12L64164A fitted on this board: 4 banks x 1M x 16
bits = 8 MB, 12 row address bits, 8 column address bits, SDRAM1 mapped at
0x98000000. The timing values are the ones validated on this board in
hardware.
Three of the Kconfig defaults described a different part:
BSP_SDRAM_DATA_WIDTH_SEL default 32 -> 16
BSP_SDRAM_COLUMN_BITS_SEL default 9 -> 8
BSP_SDRAM_SIZE default 32 -> 8
BANK1, ROW_BIT_12 and CAS_LATENCY_3 already matched and are unchanged.
Verified by building n32h497zgl7-evb with BSP_PERIPH_PIN_CFG_READY and
BSP_USING_SDRAM enabled: drv_sdram.c and the SDK's n32h49x_sdram.c compile
and link with no warnings.
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- qspi: both XSPI variants poll the status flags with no bound, so an
unresponsive bus hangs the caller and silently defeats the timeout it
passed in. Route every wait through the timeout-carrying helpers,
return -RT_ETIMEOUT and disable the controller on failure, and replace
the "poll then send" loops with one bounded wait per element.
- hard_i2c: the interrupt receive path programs the BYTENUM window once
and never reloads it, so a longer message was truncated and still
reported as success; refuse it with -RT_EINVAL (enable RX DMA for
longer reads) instead of capping XferSize. Stop capping the transmit
byte count at the window size as well: BYTENUM counts received bytes
only, and the cap stopped feeding DAT after byte 255 while TXDATE
stayed asserted. Reject RT_I2C_NO_START/RT_I2C_NO_STOP on the series
without frame chaining, where they would silently become a fresh START
and a STOP, and tear the DMA channel down when the address phase times
out instead of leaving it armed against a buffer about to unwind.
- spi: the H7xx LLI chain advanced the memory side by SPI_DMA_BLOCK_MAX
bytes although BlkTfrSize counts elements, so a 16-bit transfer walked
half a word early per node; advance by elements and scale both the
chunk offset and the staging buffer by the data width. Propagate the
DMA arm failure that was ignored.
- nand: an odd data length has no halfword-only encoding on the 16-bit
bus and padding would program a byte the caller never asked for, so
refuse it before the command phase; issue the empty-page dummy store
as a halfword there too, where 8-bit AHB writes are unsupported.
- Kconfig: gate the Ethernet/SDRAM/LCD/QSPI/NAND options behind
BSP_PERIPH_PIN_CFG_READY on all three boards. The peripheral clock and
IO are not configured for these boards yet, so selecting one of them
builds a driver whose pins stay in the reset function.
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- libraries/N32_Drivers: add ADC/DAC/I2C/SPI config headers for the
h47x_48x, h49x and h7xx series, and extend the shared drivers
(adc, dac, eth, gpio, hard_i2c, nand, qspi, sdram, spi, usart, wdt).
- n32h487zgl7-evb / n32h497zgl7-evb: add board ports (femc_timing,
phy_reset, usb_config) and update Kconfig, SConscript, rtconfig and
the IAR/Keil project files.
- n32h760zil7-stb: update Kconfig and rtconfig.
- CI: register the three n32hxxx boards.
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* [bsp][stm32] Add stm32n657-st-nucleo BSP
* style: format STM32 HAL drivers and STM32N657 BSP with clang-format
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- Unify DMA/BDMA/GPDMA descriptors in drv_dma (common fields + per-type union)
- Support BDMA in SPI driver with h7 dma/spi config header updates
- Add SPI6 TX/RX BDMA Kconfig options for H7
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The link points to launchpad.net, which shut down its gcc-arm-embedded
downloads years ago (the URL now returns 503), and the tarball it names
is a 2016 Q3 build (gcc 5.4).
- Point to Arm GNU Toolchain Downloads, matching the link already used
in bsp/nxp/imx/imx91/README.md. The old gnu-rm page covers the
GNU Arm Embedded Toolchain, which Arm has superseded.
- Mention installing the toolchain from the distribution package
manager, with Debian/Ubuntu as an example, since rtconfig.py already
defaults EXEC_PATH to /usr/bin. libstdc++-arm-none-eabi-newlib is
listed because LFLAGS links with -lsupc++.
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修复 SCI SPI 分频参数和运行时配置生命周期，保持位宽单位一致，应用模式及片选配置，并在收发超时或错误后停止传输、清理状态。
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Without CXX = rtconfig.CXX the scons Environment falls back to the
default host 'g++', and CXXFLAGS stays an empty CLVar, so the C++
group flags appended by DefineGroup end up as a single unquoted
argument and the build fails as soon as RT_USING_CPLUSPLUS is on:
g++: error: -fno-exceptions -fno-rtti ... -Wl,--gc-sections:
linker input file not found: No such file or directory
Found by the CI C++ ctor (.init_array) check.
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在 v1/v2 串口文件边界复制已知用户参数，补齐 v2 unread count 和 termios 缓冲区保护。
在 imx6ull UART 编程前校验波特率，并在硬件配置成功后提交串口状态。
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Pass -mpoke-function-name to the compiler and assembler when
RT_BACKTRACE_FUNCTION_NAME is enabled for the Cortex-A9 QEMU BSP.
Keep the BSP configuration opt-in so users can enable symbolized
backtraces through menuconfig without changing the default build.
The flag is appended through CCFLAGS and ASPPCOM after the build
environment is created instead of concatenating it into
CFLAGS/CXXFLAGS/ASFLAGS: when the toolchain is selected with
--exec-path, PrepareBuilding() reloads rtconfig and
_apply_exec_path_override() overwrites those variables, which would
silently drop the option. The build still succeeds but function names
are missing from the text section, leaving backtraces without usable
frames.
Example backtrace in QEMU (vexpress-a9, RT_BACKTRACE_FUNCTION_NAME=y,
fault triggered from msh through cmd_fault -> fault_level1 ->
fault_level2 -> fault_level3):
backtrace:
0x600475a8 @ fault_level3
0x600475dc @ fault_level2
0x60047608 @ fault_level1
0x60047630 @ cmd_fault
0x6006ca80 @ _msh_exec_cmd
0x6006cb3c @ msh_exec
0x600717b4 @ finsh_thread_entry
Signed-off-by: Hui Su <[email protected]>
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Enable RT_USING_HW_STACK_GUARD on Cortex-M4, which was previously only
available on Cortex-M7 and Cortex-M33.
Core porting (libcpu/arm/cortex-m4/):
- Add mpu.c/mpu.h/mputype.h aligned with the Cortex-M7 MPU layer. The only
difference is the default memory type attribute: Cortex-M4 has no L1 cache,
so the cacheability bits are reduced to three cases.
- Add rt_hw_stack_guard_init() to cpuport.c.
- Add missing #include <rtconfig.h> to context_gcc.S and invoke
rt_hw_mpu_table_switch() in the PendSV context switch path.
- Update SConscript to exclude mpu.c when memory protection is disabled.
BSP reference (bsp/stm32/stm32f407-fk407m2-zgt6/):
- board.h: include rtthread.h and define NUM_STATIC_REGIONS.
- board.c: define static_regions[] marking the Flash region read-only,
guarded by RT_USING_MEM_PROTECTION so it is not enabled by default.
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erase and write operation occurs.
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(#11715)
* updated template files, conifg files and script files to support hypperram, multicore kickoff, rpmsg-lite, netc, cherryusb and ethercat.
* updated different link files of GCC, IAR and KEIL, for supporting multicore kick-off and different loading methods
* Updated .ini files to support debugging in keil. And updeated .mac files to support deugging in iar.
* Updated template files, conifg files and script files of CM7 to support hypperram, multicore kickoff, rpmsg-lite, netc, cherryusb and ethercat.
* Updated different link files of GCC, IAR and KEIL of CM7 project, for supporting multicore kick-off and different loading methods.
* Modify LittleFS to use the last 1 MB of flash and update CM7 support for LittleFS on QSPI flash.
* Updated different link files of loading to hyperram.
* Updated .ini files of CM7 to support debugging in keil. And updeated .mac files of CM7 to support deugging in iar.
* Remove Keil projects and keep templates only.
* Remove RAMFUNC due to IAR compilation issues, and use linker configuration to place all flash operation code in RAM.
* Add related code to support kick-offing CM7 and rpmsg-lite.
* Add codes to support cherryUSB for CM33 and CM7.
* Add mnt.c to support littleFS for CM7.
* Add codes to support etherCAT for CM7.
* Add codes to support USART12 for RT1180.
* Modify the drv_uart_v2.c to fix some bug to make it can work in CM33, but still cannot work in CM7. Will continue to update in next version.
* Updated README with both Chinese and English versions.
* Move the EtherCAT code into the packages\nxp-imxrt-sdk-latest.
* Remove EtherCAT-related sources, keep only SConscript.
* updated ci.attachconfig.yml for cm33 and cm7 projects.
* Fixed BSP_ROOT path error in rtconfig.py.
* Added drv_netc.c and updated SConscript for netc.
* Updated cherryusb_port.c to avoid worning.
* Updated sconscript to locate multicore directory in packages for header inclusion.
* Updated cm33/board/board.c to avoid worning when enable cm33_kickoff_cm7.
* Deleted peripheral.ethercat, because the related protocol stack has not been uploaded. And added CONFIG_BSP_USING_GPIO=y for Peripheral.netc.:
* Removed the SConscript of multicore and ethercat to packages.
* Added CONFIG_BSP_USING_GPIO=y to Peripheral.hyperflash_dma.
* Added CONFIG_BSP_USING_GPIO=y for Peripheral.hyperflash.
* Reformat code according to coding standards.
* Reformat code according to coding standards.
* Added features of RTC, CAN, I2C DMA, SPI and SDIO for CM33.
* Updated flexspi_port.h to support using flexspi api only.
* Added ci.attachconfig of UART, RTC, CAN, I2C DMA, SPI, DWT and SDIO for CM33.
* Added features of RTC, CAN, I2C DMA, SPI and SDIO for CM7.
* Added ci.attachconfig of UART, RTC, CAN, I2C DMA, SPI, DWT and SDIO for CM7.
* Added driver of DWT.
* Added driver of flexCAN for RT1180.
* Added driver of i2c dma for RT1180.
* Added driver of lpspi and dma for RT1180.
* Added driver of sdio for RT1180.
* Added driver of RTC for RT1180.
* Updated driver of drv_uart.c and fixed some bugs in drv_uart_v2.c.
* Updated README of imxrt1180-nxp-evk.
* Reformat codes according to tools/ci/clang_format_check.py
* fix: use unsigned shift to avoid UB in drv_can.c
* Removed unnecessary build artifacts and test files.
* bsp/nxp/imxrt: fix CI build errors for non-RT1180 BSPs
* bsp/nxp/imxrt: clang-format drv_lpadc.c to fix CI format check
* Fixed standalone driver compilation errors and code formatting issues.
* Fixed CI attach failures by updating the default linker script for CM7-only ITCM builds with large .text sections.
* [bsp][imxrt] fix BBNSM GPR epoch truncation by storing epoch in two 32-bit GPRs
* [bsp][imxrt] define DBG_TAG/DBG_LVL before rtdbg.h in cm7 mnt.c
* [bsp][imxrt1180] fix(sdcard): add timeout to sd0 wait loop in mnt.c
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Improve the Rust build integration across core, applications, components, and module examples. Fix build failure propagation, target and feature handling, linker flags, example configuration semantics, and add STM32 CI attach coverage.
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Add support for audio, display, Ethernet, PCIe, PHY, SDIO, UFS,
hardware crypto and multimedia accelerators. Update the RK3300 and
RK3500 configurations and validation applications accordingly.
Signed-off-by: GuEe-GUI <[email protected]>
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- reorganize common Raspberry Pi drivers under the device framework
- add the Raspberry Pi 5 BSP, configuration and documentation
- add BCM2712 and DesignWare AXI DMA controller support
- distinguish BCM2712 DMA32 and DMA40 channels by channel mask
- restore DesignWare AXI DMA enable bits after controller reset
- support a shared AXI maximum burst length across DMA channels
Signed-off-by: GuEe-GUI <[email protected]>
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Signed-off-by: GuEe-GUI <[email protected]>
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* [dm][dma] update DMA interface
Extend DMA mapping to honor OFW dma-ranges even
when no reserved memory pool is present,
and add PCI host-bridge DMA-region translation for PCI devices.
Prefer 32-bit-addressable allocations for translated devices,
improve pool allocation fallbacks and synchronization,
and establish a linear mapping for installed DMA pools when possible.
Signed-off-by: GuEe-GUI <[email protected]>
* [dm][dma] fixup PL330 work flow
Fix PL330 channel allocation so device-tree cells
select peripheral request lines rather than execution channels.
Generate proper peripheral DMA microcode using DMAWFP, DMALDP, DMASTP, and DMAFLUSHP,
encode burst lengths correctly,
honor transfer direction and non-secure attributes,
and allocate microcode from DMA-coherent memory.
Signed-off-by: GuEe-GUI <[email protected]>
* style: format code with clang-format
* style: format complete changed files with clang-format
* drivers: dma: fix diagnostic format types
* style: format DMA changes for current master
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Signed-off-by: GuEe-GUI <[email protected]>
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