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* [doxygen] add adc driver example for doxygen
* add data structures
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PIC may free because some wrongs in debug.
We should remove in PIC list or there are
some undefined behavior will happen.
Signed-off-by: GuEe-GUI <[email protected]>
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https://github.com/RT-Thread/rt-thread/pull/9420
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DMA and CPU address view is different, we need to convert them:
+--------+ +--------+ +---------+ +--------+
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| CPUs | | DEV0 | | IOMMU <----+ | DEV1 |
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+----+---+ +----+---+ +----+----+ | +----+---+
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0x200000 | 0x1000 | 0x1000 | | 0x8000 |
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+-------------+-----------+ +----------+
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+--------v----------------------------------------------------+
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| Address BUS |
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+-------------------------------------------------------------+
Signed-off-by: GuEe-GUI <[email protected]>
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Maybe use for memory/DMA buffer init before
ofw_node unflatten.
Signed-off-by: GuEe-GUI <[email protected]>
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Signed-off-by: GuEe-GUI <[email protected]>
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When the driver request a API gets RT_NULL which return value is ptr,
they could not know why get a RT_NULL.
some API return RT_NULL, is not error internal maybe, it just not
supported for this platform, but the driver still could work ok,
the API can return (RT_NULL + -RT_EEMPTY) to driver.
on the other hand, the driver can do more behaviors by error no.
When the API return the -RT_EBUSY, driver can wait for a moment and retry.
When the API return the -RT_ENOSYS, driver can try the next mode or request's name.
Signed-off-by: GuEe-GUI <[email protected]>
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PCI/PCIe have better performance and more devices support, such as
NVMe, GPU, Powerful NIC (Like RDMA). PCI/PCIe can access control by
IOMMU that the virtualiztion and userspace driver will more safety.
PCI/PCIe device could hot plugging, no design modifications SoC required,
PCI/PCIe on Embedded SoC is popular now.
We make a simple framework to support them.
Feature Lists:
1.PCI INTx: the INT[A-D] pin IRQ for legacy PCI, work with platform PIC.
2.MSI/MSI-X: the message write IRQ for PCIe, work with platform's PIC.
3.PME: we only support the D0, D1, D2, D3HOT, D3COLD init by framework.
4.Endpoint: a simple EP framework for PCI FPGA or NTB function.
5.OFW: we only support work on OFW SoC, ACPI support in the future maybe.
Host controller:
1. Common PCI host controller on ECAM.
2. Generic PCI host controller on ECAM.
Signed-off-by: GuEe-GUI <[email protected]>
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1. RT_FIELD_PREP: prepare a bitfield element.
2. RT_FIELD_GET: extract a bitfield element.
3. rt_offsetof: member offset of a struct
4. rt_upper_32_bits: high 32 bits of value.
5. rt_lower_32_bits: lower 32 bits of value.
6. rt_upper_16_bits: high 16 bits of value.
7. rt_lower_16_bits: lower 16 bits of value.
8. rt_max_t: fix type of max(...).
9. rt_ilog2: integer logarithm base 2.
Signed-off-by: GuEe-GUI <[email protected]>
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Since the completion is used to sync with ISR mostly, we should set the
default semantic to ISR-safe. So most user will be happy and don't see
any weird behavior in their codes.
Changes:
- Added `rt_completion_wait_noisr` and
`rt_completion_wait_flags_noisr` functions in `completion.h`,
`completion_comm.c`, `completion_mp.c`, and `completion_up.c`.
- The new APIs allow waiting for completions in non-ISR contexts
while ensuring thread context safety.
- Existing documentation and comments were updated to clarify
usage contexts and emphasize restrictions on ISR usage.
Signed-off-by: Shell <[email protected]>
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The changes unify the tick.c implementations for all risc-v64
architectures, leveraging the CPUTIME feature. This refactoring was
necessary to streamline the codebase, and ensure consistent timer
handling across different platforms.
Changes:
- Updated `Kconfig` in `bsp/cvitek/cv18xx_risc-v` to fix formatting issues.
- Updated .config for BSPs to update `CPUTIME_TIMER_FREQ`
- Updated header of for API `riscv_cputime_init`
- Initialized riscv timer on `rt_hw_tick_init`
- Refactored `tick.c` and `tick.h` in `libcpu/risc-v/t-head/c906` and `libcpu/risc-v/virt64`:
- Replaced direct use of `rdtime` with `clock_cpu_gettime`.
- Removed redundant timer frequency definitions.
- Added static assertions to check the value of `CPUTIME_TIMER_FREQ`.
- Initialized `tick_cycles` based on `CPUTIME_TIMER_FREQ`.
- Integrated `ktime` support for tick initialization.
Signed-off-by: Shell <[email protected]>
Reviewed-on: https://github.com/RT-Thread/rt-thread/pull/9164
Reviewed-by: Chen Wang <[email protected]>
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(#8972)
* support period time
* enable multiple ktimer
* mv set delay_cnt to hrtimer_start
* add ktime debug info
* change current_irq_begin to local var
* fix bug: setting current timer and setting timeout in driver aren't atomicly
* create->init
* refactoring ktime
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* [DM/feature] Implement PIC irq state { get; set }
There are some common state for irq:
1. Pending: IRQ was triggered, but software not ACK.
2. Active: IRQ was ACK, but not EOI.
3. Masked: IRQ was masked or umasked.
Signed-off-by: GuEe-GUI <[email protected]>
* [DM/pic] Support IRQ state { get; set } for ARM GICv2/v3
Signed-off-by: GuEe-GUI <[email protected]>
---------
Signed-off-by: GuEe-GUI <[email protected]>
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* [Feature] Power domain for device
1.Support device power on/off.
2.Support attach/detach device.
3.Support power domain driver api.
Signed-off-by: GuEe-GUI <[email protected]>
* [DM/platform] Enhanced platform bus
1.Add power domain for device.
2.Support `remove` and `shutdown` bus interface.
Signed-off-by: GuEe-GUI <[email protected]>
---------
Signed-off-by: GuEe-GUI <[email protected]>
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- add parameter phy to specify multiple-phy instance
Signed-off-by: Jiading Xu <[email protected]>
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For some CPU memory access devices, that the drivers
will find memory and CPU affinity to config device.
Signed-off-by: GuEe-GUI <[email protected]>
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* [PIC] Make affinity helper interface
Signed-off-by: GuEe-GUI <[email protected]>
* [PIC/GIC] Fixup GIC affinity init
GICv2 is not support if current CPU is not startup,
but RT-Thread SMP is startup after the devices init
in the `main` thread.
This patch fixup the cpumask to init once and check
the init status in affinity interface.
Signed-off-by: GuEe-GUI <[email protected]>
---------
Signed-off-by: GuEe-GUI <[email protected]>
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The OFW map id is always use in DMA, PCI, IOMMU
bus system to find the device identity. this is
a access interface.
Signed-off-by: GuEe-GUI <[email protected]>
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- added SDR50, SDR104 and DDR50 support to SD driver
Signed-off-by: Fan YANG <[email protected]>
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- added HS400 supprt (both eMMC5.0 and eMMC5.1 flavor are supported)
Signed-off-by: Fan YANG <[email protected]>
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add isr statistics
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fix compiler error in serial dm
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* [ipc] lockless rt_completion implementation
The new rt_completion implemented by lockless algorithm can improve timer resolution for up to ~12%, compare to sem IPC.
Signed-off-by: Shell <[email protected]>
* fixup: error
* remove useless changes
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Signed-off-by: Shell <[email protected]>
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In this patch, a hook list has been introduced to address the concerns
regarding coupling issues arising from modifications to the serial code
for integrating TTY logic.
Signed-off-by: Shell <[email protected]>
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* serial-tty fix
* v2
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Signed-off-by: xqyjlj <[email protected]>
Signed-off-by: Shell <[email protected]>
Co-authored-by: xqyjlj <[email protected]>
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Signed-off-by: Shell <[email protected]>
Co-authored-by: xqyjlj <[email protected]>
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sensor v2框架仍在开发中
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