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Age	Commit message (Collapse)	Author
2025-08-25	[DM/PCI] Fixup the bus-range probe	GuEe-GUI
	Signed-off-by: GuEe-GUI <[email protected]>
2024-11-26	[DM/FIXUP] Fixup PCI device ofw private node for MSI	GuEe-GUI
	Some PCI device devicetree is like: ```dts pcie@fe270000 { device_type = "pci"; msi-map = <0x1000 0x9c 0x1000 0x1000>; pcie@10 { reg = <0x100000 0x00 0x00 0x00 0x00>; #address-cells = <0x03>; #size-cells = <0x02>; pcie@10,0 { reg = <0x00 0x00 0x00 0x00 0x00>; }; }; }; ``` that the pcie@10,0 have a private ofw node, it will find property name `msi-map` or `msi-parent` fail. We should only find the property in host bridge's ofw node. Signed-off-by: GuEe-GUI <[email protected]>
2024-09-06	[DM/Feature] Basic PCI/PCIe (Peripheral Component Interconnect Express) bus	GuEe-GUI
	PCI/PCIe have better performance and more devices support, such as NVMe, GPU, Powerful NIC (Like RDMA). PCI/PCIe can access control by IOMMU that the virtualiztion and userspace driver will more safety. PCI/PCIe device could hot plugging, no design modifications SoC required, PCI/PCIe on Embedded SoC is popular now. We make a simple framework to support them. Feature Lists: 1.PCI INTx: the INT[A-D] pin IRQ for legacy PCI, work with platform PIC. 2.MSI/MSI-X: the message write IRQ for PCIe, work with platform's PIC. 3.PME: we only support the D0, D1, D2, D3HOT, D3COLD init by framework. 4.Endpoint: a simple EP framework for PCI FPGA or NTB function. 5.OFW: we only support work on OFW SoC, ACPI support in the future maybe. Host controller: 1. Common PCI host controller on ECAM. 2. Generic PCI host controller on ECAM. Signed-off-by: GuEe-GUI <[email protected]>