| Age | Commit message (Collapse) | Author |
|---|
|
1. There is only one GPIO device in System.
2. For Pin API input is pin number
3. Add sets pin debounce time API.
So we need a virtual pin for multi gpio chip.
Signed-off-by: GuEe-GUI <[email protected]>
|
|
Signed-off-by: GuEe-GUI <[email protected]>
|
|
Only check HIGH or LOW
Signed-off-by: GuEe-GUI <[email protected]>
|
|
Signed-off-by: GuEe-GUI <[email protected]>
|
|
Signed-off-by: GuEe-GUI <[email protected]>
|
|
Work together can make DMA engine device drivers
knows how want a chan easy.
Signed-off-by: GuEe-GUI <[email protected]>
|
|
Signed-off-by: GuEe-GUI <[email protected]>
|
|
|
|
Too many PCI controllers base on DesignWare PCIe.
This is a modules.
Signed-off-by: GuEe-GUI <[email protected]>
|
|
Signed-off-by: GuEe-GUI <[email protected]>
|
|
Signed-off-by: GuEe-GUI <[email protected]>
|
|
Provides general LED control API and drivers.
It can work on PWM, GPIO and Syscon...
Signed-off-by: GuEe-GUI <[email protected]>
|
|
Signed-off-by: GuEe-GUI <[email protected]>
|
|
1. Fixed regulator.
2. GPIO regulator.
Signed-off-by: GuEe-GUI <[email protected]>
|
|
1. Add the regulator driver framework.
2. Add the generic voltage and current regulator API support
for drivers.
Signed-off-by: GuEe-GUI <[email protected]>
|
|
|
|
|
|
Add ACHI drivers to support some old platform
driver such as SATA.
Signed-off-by: GuEe-GUI <[email protected]>
|
|
We should wait a while for success or failure
after link status change or will communicate
fail with the endpoint.
Signed-off-by: GuEe-GUI <[email protected]>
|
|
Some PCI device devicetree is like:
```dts
pcie@fe270000 {
device_type = "pci";
msi-map = <0x1000 0x9c 0x1000 0x1000>;
pcie@10 {
reg = <0x100000 0x00 0x00 0x00 0x00>;
#address-cells = <0x03>;
#size-cells = <0x02>;
pcie@10,0 {
reg = <0x00 0x00 0x00 0x00 0x00>;
};
};
};
```
that the pcie@10,0 have a private ofw node, it will find
property name `msi-map` or `msi-parent` fail.
We should only find the property in host bridge's ofw node.
Signed-off-by: GuEe-GUI <[email protected]>
|
|
* [DM/FEATURE] Support reset controller
Reset controllers are central units that control
the reset signals to multiple peripherals.
The reset controller API is split into two parts:
1. The consumer driver interface, which allows
peripheral drivers to request control over
their reset input signals
2. The reset controller driver interface
which is used by drivers for reset controller devices to
register their reset controls to provide them to the consumers.
* [RESET/SIMPLE] Support simple reset
Currently this driver supports:
- Altera SoCFPGAs
- ASPEED BMC SoCs
- Bitmain BM1880 SoC
- Realtek SoCs
- RCC reset controller in STM32 MCUs
- Allwinner SoCs
- SiFive FU740 SoCs
- Sophgo SoCs
Signed-off-by: GuEe-GUI <[email protected]>
|
|
* [DM/FEATURE] Support hardware mailbox
* [MAILBOX/PIC] Add PIC Mailbox drivers.
The mailbox device(s) may be instantiated in one of three equivalent way:
Device Tree node, eg.:
```dts
interrupt-controller@0 {
interrupt-controller;
#interrupt-cells = <1>;
};
pic_mailbox@10000 {
compatible = "rt-thread,pic-mailbox";
reg = <0x10000 0x100>;
position = <0>;
interrupts = <34>;
peer-interrupts = <35>;
uid = <0>;
#mbox-cells = <1>;
};
```
Signed-off-by: GuEe-GUI <[email protected]>
|
|
This framework will be of use only to devices that use
external PHY (PHY functionality is not embedded within the controller).
Use in PCIE, USB, HDMI, DP...
Signed-off-by: GuEe-GUI <[email protected]>
|
|
|
|
* [DM/FEATURE] Support NVME
1. Support PRP and SGL (>= NVME v1.1) transport.
2. Support MSI/MSI-X for IO queues.
3. Support NVME on PCI.
Signed-off-by: GuEe-GUI <[email protected]>
|
|
|
|
|
|
* [DM/FEATURE] Support block for SCSI
1. Support SD and CD-ROM.
2. SD will port to UFS and ATA device.
Signed-off-by: GuEe-GUI <[email protected]>
|
|
1. DMA pool management for platform.
2. DMA engine driver API.
Signed-off-by: GuEe-GUI <[email protected]>
|
|
|
|
still in use and dosen't destory the mutex either.
|
|
and always return EINVAL.
|
|
|
|
[DM/FEATURE] Support IIO (Industrial I/O)
Signed-off-by: GuEe-GUI <[email protected]>
|
|
Signed-off-by: GuEe-GUI <[email protected]>
|
|
Signed-off-by: GuEe-GUI <[email protected]>
|
|
Open Kconfig will not fail if using osource,
This way can make SoC Kconfig to DM easy.
Link: ecb89b1370ec27be650a0a2fae7c6802b4246933
Signed-off-by: GuEe-GUI <[email protected]>
|
|
Signed-off-by: GuEe-GUI <[email protected]>
|
|
Don't use `irq` as a var when clear MSI global
irq map, the irq which alloc before will rewrite.
Signed-off-by: GuEe-GUI <[email protected]>
|
|
1. remove gpt.
2. remove block device custom.
Signed-off-by: GuEe-GUI <[email protected]>
|
|
1. Disk and blk device management.
2. Support partitions probe auto.
3. Support DFS and user mode fops, ioctl.
4. Add a cmd for blk info.
Signed-off-by: GuEe-GUI <[email protected]>
|
|
MFD (Multifunction device) with System Controller Register Read/Write.
Signed-off-by: GuEe-GUI <[email protected]>
|
|
Signed-off-by: GuEe-GUI <[email protected]>
|
|
1. Default return OK when input NULL (if is not necessary in device).
2. Support object parse in OFW.
3. Support CLK depends fix auto.
4. Fixup rt_clk_array_prepare_enable and rt_clk_array_disable_unprepare.
Signed-off-by: GuEe-GUI <[email protected]>
|
|
old phy bus is too simple add phy_bus is not adapt rt_bus framework,so writer a stronger phy bus framework.
here is my commit message:
add mdio bus and phy bus to kernel,the phy bus use rt_bus framewok ,driver writer can write phy_driver first .when mac driver need to use phy they can register phy_device and pjhy_devie will serach for driver which match by uid and mask,if no driver match with the device that you register,phy_bus will return the genphy to you device,the genphy driver is the general driver for phy,so you can use it but it can not support the capcity of chip it may be cause performance is not up to peak
|
|
|
|
|
|
|
|
Signed-off-by: GuEe-GUI <[email protected]>
|
|
We need a API to fix the driver load auto when
a second driver get it in probe process that
we can not be careful of the driver-to-driver's
depends in different SoC.
Signed-off-by: GuEe-GUI <[email protected]>
|
