| Age | Commit message (Collapse) | Author |
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* add all soft timer
* update wq
* add timer test
* shield LOG_D
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* first
* second
* thrid
* Update SConscript
* tmpfs testcase default n
* Update dfs_tmpfs.c
* format document
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Co-authored-by: zhujiale <[email protected]>
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* [smart] fixup: precise mm fault type
Also, fixup arm64 read access fault
* arm64: using meaningful macro on trap
* fixup: renaming macro
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* [utest] add device find
Signed-off-by: Shell <[email protected]>
* fixup: add test
* fixup: ptr aliasing
* quality: meaning parameter
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Signed-off-by: Shell <[email protected]>
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* [libcpu/arm64] add C11 atomic ticket spinlock
Replace the former implementation of flag-based spinlock which is unfair
Besides, C11 atomic implementation is more readable (it's C anyway),
and maintainable. Cause toolchain can use their builtin optimization and
tune for different micro-architectures. For example armv8.5 introduces a
better instruction. The compiler can help with that when it knows your
target platform in support of it.
Signed-off-by: Shell <[email protected]>
* fixup: RT_CPUS_NR
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Signed-off-by: Shell <[email protected]>
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* [ipc] lockless rt_completion implementation
The new rt_completion implemented by lockless algorithm can improve timer resolution for up to ~12%, compare to sem IPC.
Signed-off-by: Shell <[email protected]>
* fixup: error
* remove useless changes
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Signed-off-by: Shell <[email protected]>
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Signed-off-by: xqyjlj <[email protected]>
Signed-off-by: Shell <[email protected]>
Co-authored-by: xqyjlj <[email protected]>
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Signed-off-by: Shell <[email protected]>
Co-authored-by: xqyjlj <[email protected]>
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Signed-off-by: Shell <[email protected]>
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Signed-off-by: Shell <[email protected]>
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Signed-off-by: shell <[email protected]>
Signed-off-by: Shell <[email protected]>
Co-authored-by: xqyjlj <[email protected]>
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Signed-off-by: Shell <[email protected]>
Co-authored-by: Shell <[email protected]>
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Signed-off-by: shell <[email protected]>
Signed-off-by: Shell <[email protected]>
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Prev implementation of lwp_new() including the create of lwp object
and the pid allocation. But not every lwp object need a pid.
So this patch split out the business of lwp_new() to improve the
maintainability.
Signed-off-by: Shell <[email protected]>
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位机器导致的栈异常 (#8057)
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Signed-off-by: Shell <[email protected]>
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Signed-off-by: Shell <[email protected]>
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�问题 (#7717)
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这个文件里存在使用fopen函数后没有关闭文件fclose的问题,而且stream=NULL时是不需要fclose的
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atoi_tc.c中的"sizeof(test_data[0])" 和atol_tc.c中的"sizeof(test_data1[0]"错误,小于实际数组中的数据个数
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��题 (#7483)
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for better readability
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* [utest][atomic]添加返回值测试
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* [utest/mm] add testcase for create/init
format codes of create/init in components/mm
* [libcpu/aarch64] fix user stack check routine
* [kservice] export API for utest
* [utest/mm] testcase for aspace_map
format & modify the files under components/mm related with aspace_map
* [lwp/user_mm] add user_map_varea for mmap feature
* [mm] rename rt_mm_fault_try_fix to rt_aspace_fault_try_fix
* [utest/mm] testcase for synchronization
* [mm] modify unmap api to improve throughput
* [utest/mm] testcases for cache and varea map
* [format] remove extra space
* [utest/mm] fix testcase problem in header
* [lwp] extend map_user_varea with a flag
* [utest/mm] testcase for lwp_map_user_varea
* [libcpu/arm/cortex-a] fix kernel space layout
* [utest/mm] adjust for armv7 arch
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* Update Kconfig
* Update trap_gcc.S
* Update bsp/hifive1/drivers/SConscript
Co-authored-by: Man, Jianting (Meco) <[email protected]>
* Update SConscript
* [atomic]提交一份arm与risc-v架构下的常用原子操作函数
* 修改变量类型
* 更新rtatomic.h与atomic_port.c
* 更新rt-thread\libcpu\arm\common\atomic_port.c
* 更新include/rtatomic.h与libcpu/arm/common/SConscript
* 更新include/rtatomic.h
* 修正格式与Kconfig
* 修正格式与文件结构
* 规范文件格式与文件重命名
* 添加测试用例与CI
* 添加函数声明
* 修改virt64/SConscript 添加atomic_riscv.c
* 1.规范代码风格
* 2.添加RISC-V64原子指令支持 解决在RV64下编译器将32-bit运算结果扩展为64-bit 导致判断错误
* 添加C11标准库原子操作测试
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Co-authored-by: Man, Jianting (Meco) <[email protected]>
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* [fix] implementation fault on avl
* [fix] mm may free varea allocated statically
* [test] add test and benchmark for avl
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