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feat: [libcpu/c906] support ARCH_REMAP_KERNEL
This change was necessary to enable the remapping of the kernel image to
a high virtual address region on the c906 platform.
Changes:
- Introduced new configuration options `ARCH_REMAP_KERNEL`, and
`ARCH_USING_ASID` under the `ARCH_RISCV64` section.
- Updated MMU initialization and switching functions to incorporate
remapping handling.
- Modified page table setup for proper memory attribute settings.
- Added support for early memory setup, kernel remapping
- Added conditional compilation for ASID support in the `rt_aspace` struct,
since this is not enable currently for most architecture.
Signed-off-by: Shell <[email protected]>
Co-authored-by: Shell <[email protected]>
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* memory setup using memblock
* map pages later
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* [libcpu] support for ARCH_REMAP_KERNEL
These changes introduce support for the ARCH_REMAP_KERNEL configuration,
which isolates kernel space in high virtual address regions. This feature
is necessary to enhance memory protection and management by segregating
user and kernel spaces more effectively.
Changes:
- Updated conditional macros to check for ARCH_REMAP_KERNEL instead of
ARCH_KERNEL_IN_HIGH_VA in board initialization files to reflect the new
configuration option.
- Modified qemu-virt64-riscv Kconfig and SConstruct files to include and
utilize ARCH_REMAP_KERNEL.
- Created a new linker script `link_smart.lds` for smart linking in qemu-virt64-riscv.
- Updated rtconfig.py to use a more flexible execution path setup.
- Enhanced user address space definitions in `lwp_arch.h` to support the
new virtual address mappings.
- Adjusted kernel memory initialization and mapping logic in `c906/mmu.c`
and `virt64/mmu.c` to account for high virtual address regions.
- Added Kconfig option to enable ARCH_REMAP_KERNEL for RISCV64 architectures.
- Enhanced memory setup functions to support new mapping scheme, including
updates to early page table setup and address relocation logic.
These modifications ensure that the system can utilize high memory
addresses for the kernel, improving memory isolation and system stability.
Signed-off-by: Shell <[email protected]>
* fixup: CI run failed
* bsp: default config without using smart
* fixup: static checks
* restore rt_hw_mmu_kernel_map_init for D1
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Signed-off-by: Shell <[email protected]>
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* [libcpu] arm64: Add hardware thread_self support
This patch introduces hardware-based thread self-identification
for the AArch64 architecture. It optimizes thread management by
using hardware registers to store and access the current thread's
pointer, reducing overhead and improving overall performance.
Changes include:
- Added `ARCH_USING_HW_THREAD_SELF` configuration option.
- Modified `rtdef.h`, `rtsched.h` to conditionally include
`critical_switch_flag` based on the new config.
- Updated context management in `context_gcc.S`, `cpuport.h`
to support hardware-based thread self.
- Enhanced `scheduler_mp.c` and `thread.c` to leverage the new
hardware thread self feature.
These modifications ensure better scheduling and thread handling,
particularly in multi-core environments, by minimizing the
software overhead associated with thread management.
Signed-off-by: Shell <[email protected]>
* fixup: address suggestion
* fixup: rt_current_thread as global
* scheduler: add cpu object for UP scheduler
Also, maintain the rt_current_thread in cpu object on UP scheduler.
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Signed-off-by: Shell <[email protected]>
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* [libcpu/arm64] add C11 atomic ticket spinlock
Replace the former implementation of flag-based spinlock which is unfair
Besides, C11 atomic implementation is more readable (it's C anyway),
and maintainable. Cause toolchain can use their builtin optimization and
tune for different micro-architectures. For example armv8.5 introduces a
better instruction. The compiler can help with that when it knows your
target platform in support of it.
Signed-off-by: Shell <[email protected]>
* fixup: RT_CPUS_NR
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Signed-off-by: Shell <[email protected]>
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Signed-off-by: Shell <[email protected]>
Co-authored-by: Shell <[email protected]>
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Signed-off-by: GuEe-GUI <[email protected]>
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Signed-off-by: GuEe-GUI <[email protected]>
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适配A55架构, 添加aarch64 rt_… (#7628)
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* Update Kconfig
* Update trap_gcc.S
* Update bsp/hifive1/drivers/SConscript
Co-authored-by: Man, Jianting (Meco) <[email protected]>
* Update SConscript
* [atomic]提交一份arm与risc-v架构下的常用原子操作函数
* 修改变量类型
* 更新rtatomic.h与atomic_port.c
* 更新rt-thread\libcpu\arm\common\atomic_port.c
* 更新include/rtatomic.h与libcpu/arm/common/SConscript
* 更新include/rtatomic.h
* 修正格式与Kconfig
* 修正格式与文件结构
* 规范文件格式与文件重命名
* 添加测试用例与CI
* 添加函数声明
* 修改virt64/SConscript 添加atomic_riscv.c
* 1.规范代码风格
* 2.添加RISC-V64原子指令支持 解决在RV64下编译器将32-bit运算结果扩展为64-bit 导致判断错误
* 添加C11标准库原子操作测试
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Co-authored-by: Man, Jianting (Meco) <[email protected]>
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* [rt-smart/mem] remove pv_offset
* [rt-smart] list kernel space command
* [rt-smart] restore ioremap region
* [revert] restore kernel space isolation
* [rt-smart/pv_off] code format
* [rt-smart] add get_pvoff()
* [pvoffset] pvoff as constant for C codes
* [pvoff] pvoff as interfaces
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* Add ADT Kconfig and fix MMU kconfig issue in Cortex-A
* [BSP] enable ADT
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* [smart/aarch64] sync aarch64
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* [dfs] sync cromfs
* [rt-smart]Weaken RT_USING_LWP, use RT_USING_SMART as macro configuration
* [format] fix some format issue.
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* Synchronize the code of the rt mart branch to the master branch.
* TTY device
* Add lwP code from rt-smart
* Add vnode in DFS, but DFS will be re-write for rt-smart
* There are three libcpu for rt-smart:
* arm/cortex-a, arm/aarch64
* riscv64
Co-authored-by: Rbb666 <[email protected]>
Co-authored-by: zhkag <[email protected]>
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* [cpu][cm33] Support running in secure mode
* [bsp][lpc55sxx] Using the cortex cm33
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* [cpu] 增加ARCH_CPU_BIG_ENDIAN
- 之前RT_USING_BIG_ENDIAN的命名并不合理，予以替换为ARCH_CPU_BIG_ENDIAN
- 删除一处多余的ARCH_CPU_64BIT
- 整理了libcpu/Kconfig的格式
* [libcpu][Kconfig] Cortex-M4&7 select ARCH_ARM_CORTEX_FPU
* revert last commit
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添加gicv3中断控制器代码，更新menuconfig配置选项与utest的config.h
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添加对 TI C2000 DSP 的移植
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1. Add IPADDR/GWADDR etc;
2. Add Kconfig for libcpu.
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