| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-06-28 | [format] cleanup libcpu/aarch64 (#8950) | Shell | |
| * [dfs] fixup compiler warning Signed-off-by: Shell <[email protected]> * [format] libcpu/arm64: separate context switching codes Signed-off-by: Shell <[email protected]> * [format] libcpu/arm64: separate vector Signed-off-by: Shell <[email protected]> * [format] libcpu/arm64: separate context_gcc.S Signed-off-by: Shell <[email protected]> * [format] libcpu/arm64: moving headers to include directory Signed-off-by: Shell <[email protected]> * style: replace tab with space --------- Signed-off-by: Shell <[email protected]> | |||
| 2024-05-16 | [libcpu/arm64] add C11 atomic ticket spinlock (#8882) | Shell | |
| * [libcpu/arm64] add C11 atomic ticket spinlock Replace the former implementation of flag-based spinlock which is unfair Besides, C11 atomic implementation is more readable (it's C anyway), and maintainable. Cause toolchain can use their builtin optimization and tune for different micro-architectures. For example armv8.5 introduces a better instruction. The compiler can help with that when it knows your target platform in support of it. Signed-off-by: Shell <[email protected]> * fixup: RT_CPUS_NR --------- Signed-off-by: Shell <[email protected]> | |||
| 2022-12-20 | [smart/aarch64] code sync (#6750) | Shell | |
| * [smart/aarch64] sync aarch64 | |||
| 2022-01-20 | [asm] 解决tab和空格混用的问题 | Meco Man | |
| 2020-04-16 | add raspi4 bsp | bigmagic | |
