| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-05-12 | [BSP][qemu-vexpress-a9] code cleaup for compiling warning. | Bernard Xiong | |
| 2019-05-11 | fix signal code | shaojinchun | |
| 2019-05-09 | [libcpu][arm/cortex-a] Add correct comments. | Bernard Xiong | |
| 2019-04-27 | 修改lwp支持中arm cortex-a的swi入口函数处理 | shaojinchun | |
| 2019-04-26 | Rename 'platform.h' in 'imx6ul' and 'qemu-vexpress-a9' BSPs. | qz721 | |
| This filename conflicts with the 'mbedtls' package. They are renamed in the name of the corresponding chips and included in 'board.h'. Files that rely on this file should include 'board.h' instead. | |||
| 2019-04-01 | Disable the data alignment check. | qz721 | |
| 2019-03-29 | Add standard rt-thread cache interfaces for arm/cortex-a. | qz721 | |
| Add cache invalidate and clean interfaces. Adjust the default cache type of memory to 'WriteBach with WriteAllocate'. | |||
| 2019-03-25 | Make 'qemu-vexpress-a9' and 'imx6ul' use the same libcpu code. | qz721 | |
| 2019-01-07 | [libcpu] Add SConscript in libcpu. | Bernard Xiong | |
| 2018-12-05 | [libcpu/arm/cortex-a]rt_hw_interrupt_install函数name参数增加const限定 | liruncong | |
| 2018-10-15 | [license] Change the license of libarm to Apache. | Bernard Xiong | |
| 2017-12-21 | [libcpu]: add 8-byte alignment for arm architecture && optimize code format | SummerGift | |
| 2017-11-01 | [BSP] add i.MX 6UL BSP | Bernard Xiong | |
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index : rt-thread.git | |
| Unnamed repository; edit this file 'description' to name the repository. |
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