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2013-06-18Signed-off-by: visitor83 <[email protected]>visitor83
format the s3c24x0 serial.c and mini2440 rtconfig.py
2013-06-16ident formatvisitor83
Signed-off-by: visitor83 <root@wolflouis.(none)>
2013-06-12rm48x50: rt_interrupt_nest should be `volatile rt_uint8_t`Grissiom
2013-06-12rm48x50: add cache_{enable, disable}Grissiom
2013-06-05cortex-r4: wrap asm functions with .asmfunc/.endasmfuncGrissiom
2013-06-05cortex-r4: add __rt_ffsGrissiom
2013-05-31move libcpu/arm/rm48x50/ to libcpu/arm/cortex-r4Grissiom
2013-05-31rm48x50: VFP lazy stackingGrissiom
You need to turn on RT_VFP_LAZY_STACKING in rtconfig.h. By default, RTT will turn on VFP for all threads and stack all the VFP registers. When doing lazy stacking, VFP will only be turned on for the thread who issued VFP instructions. Currently, if a thread turned on VFP, it cannot be turned off. RTT will never know what time the thread doesn't need VFP any more. The thread might could turn off the VFP for it self in proper time.
2013-05-31rm48x50: change STMFD/LDMFD to STMDB/LDMIAGrissiom
VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31rm48x50: turn on VFP supportGrissiom
This support Common VFPv2 sub-architecture.
2013-05-30rm48x50: small cleanup on context_ccs.asmGrissiom
2013-05-29rm48x50: fix bug in rt_hw_interrupt_{mask,unmask}Grissiom
2013-05-26rm48x50: optimize a BEQGrissiom
Use condition flag in the ORR. This could eliminate a BEQ.
2013-05-26rm48x50: optimize context_switch_interrupt_to by reuse registersGrissiom
When saving thread registers in context_switch_interrupt_to, we don't change them, just move them. So there is no need to always r0-r3 from stack to the real r0-r3. So just use the intermediate registers and eliminate 2 MOV.
2013-05-26rm48x50: optimize context_switch_interrupt_doGrissiom
Substitude STMFD, MOV, ADD with STMFD, SUB. It reduce one instruction. Tested on board and it works like a charm.
2013-05-26rm48x50: utilize CPS instruction and remove some useless codeGrissiom
2013-05-24add rm48x50 bsp and libcpuGrissiom
We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.
2013-04-10fixed compiling error related to the RT_USING_INTERRUPT_INFO in mini4020yiyue.fang
2013-04-08Use SRAM as EMAC transmit buffer, to avoid the underrun error, especially in ↵weety
the large amount of data communication.
2013-04-02clean up codeweety
2013-04-02fixed context thread issue when using armcc compileweety
2013-04-02enable at91sam9260 mmu, update SDIO and EMAC driversweety
2013-04-02fixed at91sam9260 context thread issue, avoid idle thread stack overflowweety
2013-03-31Merge pull request #56 from aozima/aozimaBernard Xiong
Modify the interrupt interface implementations.
2013-03-31update LPC2478: Modify the interrupt interface implementations.aozima
2013-03-31fix issue when print interrupt infoweety
2013-03-31update LPC214X: Modify the interrupt interface implementations.aozima
2013-03-31update AT91SAM7X: Modify the interrupt interface implementations.aozima
2013-03-31update sep4020: Modify the interrupt interface implementations.aozima
2013-03-31update mini2440: Modify the interrupt interface implementations.aozima
2013-03-30update to interrupt descriptionBernard Xiong
2013-03-26code cleanup for interrupt descriptionBernard Xiong
2013-03-24implement __rt_ffs for armv5weety
2013-03-23implement __rt_ffs in kernel service libraryBernard Xiong
2013-03-19remain the old handler to keep forward compatibilityweety
2013-03-19Modified the interrupt function commentsweety
2013-03-19Modify the interrupt interface implementations, changes in the part of the ↵weety
parameter definition.
2013-02-20port stm32f0x to gcc.aozima
2013-01-08convert end of lineBernard Xiong
2013-01-04remove lpc122x because there is a common cortex-m0 porting.Ubuntu
2012-12-29Add exception hook function.[email protected]
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2551 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-12-24fixed the coding style in libcpu/arm[email protected]
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2518 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-12-24rename the file name using low case[email protected]
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2514 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-12-24fixed the fixed the gcc compiling error in ubuntu host OS[email protected]
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2512 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-12-23stack addr align to 8byte.wuyangyong
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2509 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-12-17add LPC4330 BSP based on NGX xplorer development board[email protected]
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2487 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-11-13revert wrongly commit. bernard.xiong
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2408 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-11-13remove nuc1xx because there is a cortex-m0 branch.bernard.xiong
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2407 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-11-13remove lpc1100 because there is a cortex-m0 branch.bernard.xiong
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2406 bbd45198-f89e-11dd-88c7-29a3b14d5316
2012-08-22fixed bug: store r8 - r11.wuyangyong
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2258 bbd45198-f89e-11dd-88c7-29a3b14d5316
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