rt-thread.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author
2015-10-09	Merge patch from master to prepare release v2.0.2	Bernard Xiong

2014-09-20	Merge pull request #2 from RT-Thread/master	陈豪
	sync
2014-09-11	[libcpu] Add builtin ffs implementation for Cortex-M4.	bernard

2014-08-12	[libcpu]am335x edit vector	陈豪
	vector_undef and vector_dabt
2014-07-31	Fix some spell error;	aozima

2014-06-27	bsp: add zynq7000	Grissiom

2014-04-08	[bsp/rva8] enable group{0,1} interrupt forwarding in gic initialization	Grissiom
	When RT-Thread is running stand alone, it forgot to enable the distributor of GIC.
2014-04-08	[libcpu/arm] remove useless cpsr updating in rt_hw_context_switch_to	Grissiom
	This piece of code will enable the interrupt early before switching to the first thread. Although it is harmless, but not prefect.
2014-04-03	[vmm] add realview-pb-a8 VMM support	Grissiom

2014-01-11	add CM_PER_UARTx_CLKCTRL	RTsien

2013-11-17	cortex-r4: use byte to allocate the stack	Grissiom
	Unit of "byte" is more intuitive than "long".
2013-11-17	cortex-r4: let svc mode reuse the stack of IRQ on startup	Grissiom
	As the svc stack is the stack of threads, there is no need to allocate a separate stack for the startup. Reuse the IRQ stack should be OK. Tested on rm48 board.
2013-11-04	Fix hardfault bug for gcc port	Bright Pan
	for 2013-02-20 aozima commmit "port for gcc", but the commit is not tested,and the kernel is breakdown in context_gcc.S, the file is a copy from cortex-m3,but not port for cortex-m0, so i complete this port for aozima, test it in stm32f0discovery board , and it works fine.
2013-10-20	cortex-r4: dump register on traps	Grissiom
	We could not handle any traps except IRQ/FIQ.
2013-10-20	cortex-r4: remove RM48x50.h and add armv7.h	Grissiom

2013-10-20	rm48: move some asm file to libcpu	Grissiom

2013-10-20	rm48x50: add GCC support	Grissiom

2013-09-22	Delete SConscript	Bernard Xiong

2013-09-20	Import beaglebone porting	bernard

2013-07-21	Embedded GPLv2 license.	weety

2013-07-21	fix compiling error	weety

2013-07-21	commit again	weety

2013-07-21	update at91sam9260 project directory structure.	weety

2013-07-21	update AT91SAM9260 usart driver， using serial driver component.	weety

2013-07-09	enhancement hard fault exception handler.	aozima

2013-06-24	fix spelling error.	aozima

2013-06-23	update libcpu/arm/cortex-m4: support lazy stack optimized.	aozima

2013-06-23	fixed bug: correct cortex-m SCB->VTOR address.	aozima

2013-06-23	format code by Astyle.	aozima

2013-06-22	update libcpu/arm/cortex-m0: restore MSP.	aozima

2013-06-22	update libcpu/arm/cortex-m3: restore MSP.	aozima

2013-06-22	update libcpu/arm/cortex-m4: restore MSP.	aozima

2013-06-19	Merge pull request #109 from grissiom/rm48x50	Bernard Xiong
	Rm48x50
2013-06-18	Signed-off-by: visitor83 <[email protected]>	visitor83
	format the s3c24x0 serial.c and mini2440 rtconfig.py
2013-06-16	ident format	visitor83
	Signed-off-by: visitor83 <root@wolflouis.(none)>
2013-06-12	rm48x50: rt_interrupt_nest should be `volatile rt_uint8_t`	Grissiom

2013-06-12	rm48x50: add cache_{enable, disable}	Grissiom

2013-06-05	cortex-r4: wrap asm functions with .asmfunc/.endasmfunc	Grissiom

2013-06-05	cortex-r4: add __rt_ffs	Grissiom

2013-05-31	move libcpu/arm/rm48x50/ to libcpu/arm/cortex-r4	Grissiom

2013-05-31	rm48x50: VFP lazy stacking	Grissiom
	You need to turn on RT_VFP_LAZY_STACKING in rtconfig.h. By default, RTT will turn on VFP for all threads and stack all the VFP registers. When doing lazy stacking, VFP will only be turned on for the thread who issued VFP instructions. Currently, if a thread turned on VFP, it cannot be turned off. RTT will never know what time the thread doesn't need VFP any more. The thread might could turn off the VFP for it self in proper time.
2013-05-31	rm48x50: change STMFD/LDMFD to STMDB/LDMIA	Grissiom
	VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31	rm48x50: turn on VFP support	Grissiom
	This support Common VFPv2 sub-architecture.
2013-05-30	rm48x50: small cleanup on context_ccs.asm	Grissiom

2013-05-29	rm48x50: fix bug in rt_hw_interrupt_{mask,unmask}	Grissiom

2013-05-26	rm48x50: optimize a BEQ	Grissiom
	Use condition flag in the ORR. This could eliminate a BEQ.
2013-05-26	rm48x50: optimize context_switch_interrupt_to by reuse registers	Grissiom
	When saving thread registers in context_switch_interrupt_to, we don't change them, just move them. So there is no need to always r0-r3 from stack to the real r0-r3. So just use the intermediate registers and eliminate 2 MOV.
2013-05-26	rm48x50: optimize context_switch_interrupt_do	Grissiom
	Substitude STMFD, MOV, ADD with STMFD, SUB. It reduce one instruction. Tested on board and it works like a charm.
2013-05-26	rm48x50: utilize CPS instruction and remove some useless code	Grissiom

2013-05-24	add rm48x50 bsp and libcpu	Grissiom
	We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties.