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2015-05-11[libcpu][am335x] Fix the booting failure when enabling MMUAdrian Huang
Since the 16 domains are configured as the client domains in mmu_setttbase(), a Permission fault is generated if the XN bit (Execute-never) is set in the short-descriptor translation table (for section and supersection). This leads to the booting failure when enabling MMU for beagleboard bsp. Here is log: ---------------------------------------------------------------- SD/MMC found on device 0 reading uEnv.txt 117 bytes read in 3 ms (38.1 KiB/s) Loaded environment from uEnv.txt Importing environment from mmc ... Running uenvcmd ... reading rtthread.bin 162624 bytes read in 24 ms (6.5 MiB/s) \## Starting application at 0x80200000 ... ---------------------------------------------------------------- This commit removes the XN bit configuration in the section of the short-descriptor translation table. The OS can be booted successfully with applying this commit.
2015-05-04[libcpu][arm926] Optimize irq trap code.ardafu
2015-04-22[libcpu][arm926] Optimize codeardafu
1. Combine code for IAR and GCC in file mmu.c and cpuport.c 2. Remove remap code in start_xxx.S. User should config MMU to map vector table to visual address 0x0
2015-04-16[libcpu][arm926] Remove unused SPSR register PUSH/POP when os switch thread.ardafu
2015-04-16[libcpu][arm926] Define vector table start at BSP/{board}/platform/ assemble ↵ardafu
INC files.
2015-04-151. [bsp][sam9260] Fix the bug that auto reset after boot 20s. Disable ↵ardafu
watchdog in rt_lovel_level_init function. 2. [bsp][sam9260] Modify SCONS scripts to support IAR tool chain. 3. [bsp][sam9260] Move link strips in to folder link_scripts. 4. [libcpu][arm926] Add copy right to source file and format code.
2015-04-141. [cpu] split ARM926 cpu code from AT91SAM9260 BSPardafu
2015-03-09Fix compile warning:Bright Pan
..\..\libcpu\arm\cortex-m3\context_rvds.S(207): warning: A1581W: Added 2 bytes of padding at address 0xd6
2014-09-20Merge pull request #2 from RT-Thread/master陈豪
sync
2014-09-11[libcpu] Add builtin ffs implementation for Cortex-M4.bernard
2014-08-12[libcpu]am335x edit vector陈豪
vector_undef and vector_dabt
2014-07-31Fix some spell error;aozima
2014-06-27bsp: add zynq7000Grissiom
2014-04-08[bsp/rva8] enable group{0,1} interrupt forwarding in gic initializationGrissiom
When RT-Thread is running stand alone, it forgot to enable the distributor of GIC.
2014-04-08[libcpu/arm] remove useless cpsr updating in rt_hw_context_switch_toGrissiom
This piece of code will enable the interrupt early before switching to the first thread. Although it is harmless, but not prefect.
2014-04-03[vmm] add realview-pb-a8 VMM supportGrissiom
2014-01-11add CM_PER_UARTx_CLKCTRLRTsien
2013-11-17cortex-r4: use byte to allocate the stackGrissiom
Unit of "byte" is more intuitive than "long".
2013-11-17cortex-r4: let svc mode reuse the stack of IRQ on startupGrissiom
As the svc stack is the stack of threads, there is no need to allocate a separate stack for the startup. Reuse the IRQ stack should be OK. Tested on rm48 board.
2013-11-04Fix hardfault bug for gcc portBright Pan
for 2013-02-20 aozima commmit "port for gcc", but the commit is not tested,and the kernel is breakdown in context_gcc.S, the file is a copy from cortex-m3,but not port for cortex-m0, so i complete this port for aozima, test it in stm32f0discovery board , and it works fine.
2013-10-20cortex-r4: dump register on trapsGrissiom
We could not handle any traps except IRQ/FIQ.
2013-10-20cortex-r4: remove RM48x50.h and add armv7.hGrissiom
2013-10-20rm48: move some asm file to libcpuGrissiom
2013-10-20rm48x50: add GCC supportGrissiom
2013-09-22Delete SConscriptBernard Xiong
2013-09-20Import beaglebone portingbernard
2013-07-21Embedded GPLv2 license.weety
2013-07-21fix compiling errorweety
2013-07-21commit againweety
2013-07-21update at91sam9260 project directory structure.weety
2013-07-21update AT91SAM9260 usart driver, using serial driver component.weety
2013-07-09enhancement hard fault exception handler.aozima
2013-06-24fix spelling error.aozima
2013-06-23update libcpu/arm/cortex-m4: support lazy stack optimized.aozima
2013-06-23fixed bug: correct cortex-m SCB->VTOR address.aozima
2013-06-23format code by Astyle.aozima
2013-06-22update libcpu/arm/cortex-m0: restore MSP.aozima
2013-06-22update libcpu/arm/cortex-m3: restore MSP.aozima
2013-06-22update libcpu/arm/cortex-m4: restore MSP.aozima
2013-06-19Merge pull request #109 from grissiom/rm48x50Bernard Xiong
Rm48x50
2013-06-18Signed-off-by: visitor83 <[email protected]>visitor83
format the s3c24x0 serial.c and mini2440 rtconfig.py
2013-06-16ident formatvisitor83
Signed-off-by: visitor83 <root@wolflouis.(none)>
2013-06-12rm48x50: rt_interrupt_nest should be `volatile rt_uint8_t`Grissiom
2013-06-12rm48x50: add cache_{enable, disable}Grissiom
2013-06-05cortex-r4: wrap asm functions with .asmfunc/.endasmfuncGrissiom
2013-06-05cortex-r4: add __rt_ffsGrissiom
2013-05-31move libcpu/arm/rm48x50/ to libcpu/arm/cortex-r4Grissiom
2013-05-31rm48x50: VFP lazy stackingGrissiom
You need to turn on RT_VFP_LAZY_STACKING in rtconfig.h. By default, RTT will turn on VFP for all threads and stack all the VFP registers. When doing lazy stacking, VFP will only be turned on for the thread who issued VFP instructions. Currently, if a thread turned on VFP, it cannot be turned off. RTT will never know what time the thread doesn't need VFP any more. The thread might could turn off the VFP for it self in proper time.
2013-05-31rm48x50: change STMFD/LDMFD to STMDB/LDMIAGrissiom
VFP instructions only have IA(Increment After)/DB(Decrement Before) mode. To keep consistency, just change STM/LDM to DB/IA accordingly.
2013-05-31rm48x50: turn on VFP supportGrissiom
This support Common VFPv2 sub-architecture.