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* Revert safety MMU initialization.
Co-authored-by: Wayne Lin <[email protected]>
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* [utest][atomic]添加返回值测试
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* [utest/mm] add testcase for create/init
format codes of create/init in components/mm
* [libcpu/aarch64] fix user stack check routine
* [kservice] export API for utest
* [utest/mm] testcase for aspace_map
format & modify the files under components/mm related with aspace_map
* [lwp/user_mm] add user_map_varea for mmap feature
* [mm] rename rt_mm_fault_try_fix to rt_aspace_fault_try_fix
* [utest/mm] testcase for synchronization
* [mm] modify unmap api to improve throughput
* [utest/mm] testcases for cache and varea map
* [format] remove extra space
* [utest/mm] fix testcase problem in header
* [lwp] extend map_user_varea with a flag
* [utest/mm] testcase for lwp_map_user_varea
* [libcpu/arm/cortex-a] fix kernel space layout
* [utest/mm] adjust for armv7 arch
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* Update Kconfig
* Update trap_gcc.S
* Update bsp/hifive1/drivers/SConscript
Co-authored-by: Man, Jianting (Meco) <[email protected]>
* Update SConscript
* [atomic]提交一份arm与risc-v架构下的常用原子操作函数
* 修改变量类型
* 更新rtatomic.h与atomic_port.c
* 更新rt-thread\libcpu\arm\common\atomic_port.c
* 更新include/rtatomic.h与libcpu/arm/common/SConscript
* 更新include/rtatomic.h
* 修正格式与Kconfig
* 修正格式与文件结构
* 规范文件格式与文件重命名
* 添加测试用例与CI
* 添加函数声明
* 修改virt64/SConscript 添加atomic_riscv.c
* 1.规范代码风格
* 2.添加RISC-V64原子指令支持 解决在RV64下编译器将32-bit运算结果扩展为64-bit 导致判断错误
* 添加C11标准库原子操作测试
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Co-authored-by: Man, Jianting (Meco) <[email protected]>
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* [syscall] move sys_cacheflush to lwp_syscall.c
* [syscall] improve assertion
* [format] rename to rt_ctassert
* [debug] modified ct assertion on mm_page.c
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fix bugs on cache maintenance when starting user app
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* [rt-smart/mem] remove pv_offset
* [rt-smart] list kernel space command
* [rt-smart] restore ioremap region
* [revert] restore kernel space isolation
* [rt-smart/pv_off] code format
* [rt-smart] add get_pvoff()
* [pvoffset] pvoff as constant for C codes
* [pvoff] pvoff as interfaces
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rt_ssize_t can give negative error code, which follows the unix style correctly
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synchronize virtual memory system works.
adding kernel virtual memory management layer for page-based MMU enabled architecture
porting libcpu MMU codes
porting lwp memory related codes
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* [dfs] sync cromfs
* [rt-smart]Weaken RT_USING_LWP, use RT_USING_SMART as macro configuration
* [format] fix some format issue.
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* [rtdef] rename RT_WEAK attribute as rt_weak
* [rtdef] rename RT_USED attribute as rt_used
* [rtdef] rename RT_SECTION attribute as rt_section
* [rtdef] rename ALIGN attribute as rt_align
* [legacy] add RT_USED ALIGN RT_SECTION RT_WEAK as legacy support
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* Synchronize the code of the rt mart branch to the master branch.
* TTY device
* Add lwP code from rt-smart
* Add vnode in DFS, but DFS will be re-write for rt-smart
* There are three libcpu for rt-smart:
* arm/cortex-a, arm/aarch64
* riscv64
Co-authored-by: Rbb666 <[email protected]>
Co-authored-by: zhkag <[email protected]>
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If the application defines dozens of global variables,
the speed of clearing the bss segment will be slower.
Because icache can be enabled before the mmu enabled.
Therefore, in order to speed up the process of clearing the BSS segment,
enable icache needs to be put ahead.
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* bsp beaglebone: add IAR template files and fix it's build error
ATTENTION:
project.* was generated by scons, so I add it to gitignore.
rtconfig.py *FLAGS located in "PLATFORM == 'iccarm'" are unverified and maybe wrong.
(我只是从STM32里面抄来,然后根据自己的理解改了一下,并没有验证这些参数的正确性,
我也不知道怎么用命令行调用这些参数来编译)
* bsp beaglebone: add beaglebone_ram.icf ROM address from uboot_cmd.txt
am335x_DDR.icf use 0x82000000, different to uboot_cmd.txt & gcc beaglebone_ram.lds,
the difference will easy cause later developer got below error:
=> go 0x80200000
## Starting application at 0x80200000 ...
undefined instruction
pc : [<8200956c>] lr : [<8ff62497>]
reloc pc : [<728a956c>] lr : [<80802497>]
sp : 8df37358 ip : 00000000 fp : 00000002
r10: 8df4d448 r9 : 8df3feb8 r8 : 8ffd30f8
r7 : 8ff78089 r6 : 00000002 r5 : 80200000 r4 : 8df4d44c
r3 : 80200000 r2 : 8df4d44c r1 : 8df4d44c r0 : 00000001
Flags: nzCv IRQs off FIQs on Mode SVC_32
Code: 5dbffcdd bb9bdf7f abf85423 eff1f77f (7ed7daaf)
Resetting CPU ...
resetting ...
* libcpu am335x: context_iar.S rt_hw_context_switch: add thumb mode support
IAR new project defualt Processor mode is Thumb, this will cause user
easy occur the following error:
...
msh />Execption:
r00:0x8800aaa8 r01:0x802080c5 r02:0x00000000 r03:0x88009b4c
r04:0x00001000 r05:0x00000000 r06:0x00001403 r07:0x00100000
r08:0x00000000 r09:0x00000000 r10:0x0000000a
fp :0x0000000a ip :0x65687374
sp :0x00006c6c lr :0x0000008a pc :0x88008be0
cpsr:0x880001bc
software interrupt
shutdown...
(0) assertion failed at function:rt_hw_cpu_shutdown, line number:160
* bsp beaglebone: change IAR template.ewp code use Arm mode
Arm mode bin size will bigger than Thumb mode
* libcpu am335x: IAR: use rt_hw_cpu_dcache_enable instead of rt_cpu_dcache_enable
Reviewer mysterywolf say:
麻烦把rt_cpu_icache_enable 和 rt_cpu_dcache_enable, 统一改成 rt_hw_cpu_icache_enable 和 rt_hw_cpu_dcache_enable
rt_hw_cpu_icache_enable 和 rt_hw_cpu_dcache_enable 是其他bsp也是这么命名的 这是个命名统一的函数
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* bsp beaglebone: rerun menuconfg
* bsp beaglebone: add uart0 support
* bsp beaglebone: use uart0 as console
* bsp beaglebone: add heap init
fix rt_application_init() error:
(m != RT_NULL) assertion failed at function:rt_smem_alloc, line number:288
* bsp beaglebone: add mmu & interrupt init
must init mmu, otherwise no interrupt is generated, cause scheduler can't work.
I don't know why need mmu, just seen: bsp/rockchip/rk3568/driver/board.c
* libcpu am335x: reset interrupt controller before init vector
I think reset before init is more better
AM335X_StarterWare_02_00_01_01\system_config\armv7a\am335x\interrupt.c
IntAINTCInit()
* bsp beaglebone: full gpio driver support
* bsp beaglebone: add tftpboot way to uboot_cmd.txt
* bsp beaglebone: optimize am33xx_gpio_hdr, check irqstatus is the last one
Co-authored-by: YangZhongQing <[email protected]>
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clean_invalid must be set at the same time, and call
clean_invalid, or call clean/invalid
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* Fix some compilation warning
* 补充修正一些数据类型的使用错误
Co-authored-by: Meco Man <[email protected]>
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* [cpu][cm33] Support running in secure mode
* [bsp][lpc55sxx] Using the cortex cm33
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* [rtc] use gmtime_r to replace gmtime
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IAR统一使用iccarm作为判断条件而不是是用IDE的名字来进行判断
因为不确定后续IAR是否会像Keil一样内含有不同的编译工具链
此外,将判断条件改为列表方式,这样更方便后续增加其他可能的IAR编译链
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将GCC判断条件改为列表方式,方便后续增加新的编译工具链
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used in GCC4.7 and later versions.
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* [gcc][armcc][armclang] rtconfig.CROSS_TOOL->rtconfig.PLATFORM
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rt_hw_context_switch_to (#5748)
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gcc编译会出现__rt_ffs() 函数重定义,导致编译不通过的问题; (#5755)
2、解决bsp/rm48x50工程使用arm-gcc编译下载后,程序运行出现prefetch abort异常的问题。
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* 1. 新增了i2c/spi/rtc/crypto等驱动;2. 删除了部分文件中的未使用到的头文件包含; 3. 修改keil编译时pm文件atoi的头文件stdlib未包含的警告
* 修改文件格式
* BSP
1. 修改f4系列bsp的readme文件与工程文件
2. 修改f0系列源文件的版权信息、删除目前没有的库文件。
3. 其他
* 修改IAR环境下arm cortex-m33内核的syscall_iar.S文件编译错误
* 还原.gitignore文件
Co-authored-by: aisino2200 <[email protected]>
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[bugfix] libcpu/arm/cortex-m/context_gcc: 修复thumb指令集汇编语法错误
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This reverts commit a5f6fdc780d55f2bf2a1624815879e15c51082b5.
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当使用thumb指令集时,要求汇编语法中的“条件执行”要跟在IT指令后面,否则会编译不通过。
报错如下:Error: thumb conditional instruction should be in IT block -- `moveq r4,#0x01'
虽然可以通过指定"-Wa,-mimplicit-it=thumb"选项来告诉编译器识别隐式的IT指令,但是能在代码里面直接加上IT指令的话更好。
thumb指令集“条件执行”arm官网文档:
https://developer.arm.com/documentation/dui0473/m/condition-codes/conditional-execution-in-thumb-state
参考论坛帖子:
https://club.rt-thread.org/ask/question/433887.html
https://club.rt-thread.org/ask/question/4188.html
Signed-off-by: Mingrui Ren <[email protected]>
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[update] support armclang
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