| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2023-04-14 | [HUST][CSE]mips/common/exception.c/rt_set_except_vector (#7238) | d1zzy126 | |
| * mips/common/exception.c/rt_set_except_vector * Update exception.c --------- Co-authored-by: Bernard Xiong <[email protected]> | |||
| 2022-04-20 | uniform code writing-disable interrupt | thewon86 | |
| 2021-03-27 | [libcpu] auto formatted | Meco Man | |
| 2020-09-14 | MIPS:fix the RT_EXCEPTION_MAX value | michael | |
| from <see mips run> know that cp0_cause's ExcCode have 5 bit filed and the max exception is 32. | |||
| 2020-09-04 | fixed loongson bsp build on windows | bigmagic | |
| 2020-09-04 | add ls2k mmu | bigmagic | |
| 2020-06-21 | fix ls2k libc and irq | bigamgic | |
| 2020-04-07 | add ls2k bsp config | bigmagic | |
| 2020-04-07 | fix mips64 some bug | bigmagic | |
| 2019-12-11 | [libcpu] Refine MIPS common code | Jiaxun Yang | |
| MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <[email protected]> | |||
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index : rt-thread.git | |
| Unnamed repository; edit this file 'description' to name the repository. |
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