| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2017-08-26 | [BSP] cleanup for hifive1 bsp. | Bernard Xiong | |
| 2017-07-31 | fix bug in context_gcc.s and start_gcc.s: | zhangjun | |
| save mie into stack msh running normaly | |||
| 2017-07-30 | fix bug in rt_hw_context_switch_interrupt_do | zhangjun | |
| save sp to old thread clear rt_thread_switch_interrupt_flag always enable interrupt after rt_hw_context_switch judeg the type of interrupt in trap_entry, then call handler(Machine timer interrupt of Machine external interrupt) | |||
| 2017-07-30 | 修改： ../../libcpu/risc-v/e310/context_gcc.S | zhangjun | |
| enable interrupt after return form rt_hw_context_switch | |||
| 2017-07-29 | fix trap_entry | zhangjun | |
| 2017-07-26 | remove "csrrc a5, mstatus, MSTATUS_MIE" in rt_hw_interrupt_enable(); | zhangjun | |
| it will lead to interrupt again in interrupt | |||
| 2017-07-17 | add context_gcc.s | zhangjun | |
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index : rt-thread.git | |
| Unnamed repository; edit this file 'description' to name the repository. |
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