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2017-08-26[BSP] cleanup for hifive1 bsp.Bernard Xiong
2017-07-31modify: drivers/cpuusage.czhangjun
modify: ../../libcpu/risc-v/e310/stack.c rmove unused macro definition modify: ../../src/idle.c Return to the original version
2017-07-31new file: ../../libcpu/risc-v/e310/trap.czhangjun
add file that forget to submit before auto change timer mtimercmp register on the base of RT_TICK_PER_SECOND in rtconfig.h no flashing led new file: ../../src/idle.c recover old file
2017-07-31fix bug in context_gcc.s and start_gcc.s:zhangjun
save mie into stack msh running normaly
2017-07-30fix bug in rt_hw_context_switch_interrupt_dozhangjun
save sp to old thread clear rt_thread_switch_interrupt_flag always enable interrupt after rt_hw_context_switch judeg the type of interrupt in trap_entry, then call handler(Machine timer interrupt of Machine external interrupt)
2017-07-30 修改: ../../libcpu/risc-v/e310/context_gcc.Szhangjun
enable interrupt after return form rt_hw_context_switch
2017-07-29fix trap_entryzhangjun
2017-07-26 modified: ../../libcpu/risc-v/e310/context_gcc.Szhangjun
fix open timer intrrupt
2017-07-26remove "csrrc a5, mstatus, MSTATUS_MIE" in rt_hw_interrupt_enable();zhangjun
it will lead to interrupt again in interrupt
2017-07-17deleted: rtthread.s /*just for debug*/zhangjun
modified: ../../libcpu/risc-v/e310/context_gcc.S change ret to mret and switch to new task with mepc
2017-07-17add context_gcc.szhangjun