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* [libcpu] support for ARCH_REMAP_KERNEL
These changes introduce support for the ARCH_REMAP_KERNEL configuration,
which isolates kernel space in high virtual address regions. This feature
is necessary to enhance memory protection and management by segregating
user and kernel spaces more effectively.
Changes:
- Updated conditional macros to check for ARCH_REMAP_KERNEL instead of
ARCH_KERNEL_IN_HIGH_VA in board initialization files to reflect the new
configuration option.
- Modified qemu-virt64-riscv Kconfig and SConstruct files to include and
utilize ARCH_REMAP_KERNEL.
- Created a new linker script `link_smart.lds` for smart linking in qemu-virt64-riscv.
- Updated rtconfig.py to use a more flexible execution path setup.
- Enhanced user address space definitions in `lwp_arch.h` to support the
new virtual address mappings.
- Adjusted kernel memory initialization and mapping logic in `c906/mmu.c`
and `virt64/mmu.c` to account for high virtual address regions.
- Added Kconfig option to enable ARCH_REMAP_KERNEL for RISCV64 architectures.
- Enhanced memory setup functions to support new mapping scheme, including
updates to early page table setup and address relocation logic.
These modifications ensure that the system can utilize high memory
addresses for the kernel, improving memory isolation and system stability.
Signed-off-by: Shell <[email protected]>
* fixup: CI run failed
* bsp: default config without using smart
* fixup: static checks
* restore rt_hw_mmu_kernel_map_init for D1
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Signed-off-by: Shell <[email protected]>
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* GPIO驱动与QSPI驱动适配
* C++支持
* update
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Co-authored-by: 张衍 <[email protected]>
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[feat] Enhance support for backtrace service
rt_backtrace_formatted_print() and rt_backtrace_to_buffer() to help
debug routines.
Also, following modification are included:
- make rt_backtrace_frame patchable with weak attr
- replace lwp backtrace with sync output
Signed-off-by: Shell <[email protected]>
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* [smart] fixup: precise mm fault type
Also, fixup arm64 read access fault
* arm64: using meaningful macro on trap
* fixup: renaming macro
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* [libcpu] arm64: Add hardware thread_self support
This patch introduces hardware-based thread self-identification
for the AArch64 architecture. It optimizes thread management by
using hardware registers to store and access the current thread's
pointer, reducing overhead and improving overall performance.
Changes include:
- Added `ARCH_USING_HW_THREAD_SELF` configuration option.
- Modified `rtdef.h`, `rtsched.h` to conditionally include
`critical_switch_flag` based on the new config.
- Updated context management in `context_gcc.S`, `cpuport.h`
to support hardware-based thread self.
- Enhanced `scheduler_mp.c` and `thread.c` to leverage the new
hardware thread self feature.
These modifications ensure better scheduling and thread handling,
particularly in multi-core environments, by minimizing the
software overhead associated with thread management.
Signed-off-by: Shell <[email protected]>
* fixup: address suggestion
* fixup: rt_current_thread as global
* scheduler: add cpu object for UP scheduler
Also, maintain the rt_current_thread in cpu object on UP scheduler.
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Signed-off-by: Shell <[email protected]>
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* [libcpu] rv64: discard rt_current_thread
* arm: using rt_thread_self to fetch current TCB
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* [libcpu/arm64] add C11 atomic ticket spinlock
Replace the former implementation of flag-based spinlock which is unfair
Besides, C11 atomic implementation is more readable (it's C anyway),
and maintainable. Cause toolchain can use their builtin optimization and
tune for different micro-architectures. For example armv8.5 introduces a
better instruction. The compiler can help with that when it knows your
target platform in support of it.
Signed-off-by: Shell <[email protected]>
* fixup: RT_CPUS_NR
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Signed-off-by: Shell <[email protected]>
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* [smart] fixup arm64 aspace switch
Signed-off-by: Shell <[email protected]>
* fixup: arm add arch_kernel_mmu_table_get
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Signed-off-by: Shell <[email protected]>
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* fix rt_hw_secondary_cpu_bsp_start() bug
* timer init
* comment
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* [ipc] lockless rt_completion implementation
The new rt_completion implemented by lockless algorithm can improve timer resolution for up to ~12%, compare to sem IPC.
Signed-off-by: Shell <[email protected]>
* fixup: error
* remove useless changes
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Signed-off-by: Shell <[email protected]>
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* [ofw] dealing with mem region out of kernel space
- Fix parameter checking in _out_of_range() that NULL is excluded for
fixed mapping
- Split page install with a deferred stage to avoid mapping over
ARCH_EARLY_MAP_SIZE
Signed-off-by: Shell <[email protected]>
* fixup: restrict vstart for using of RT_NULL
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Signed-off-by: Shell <[email protected]>
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- added 'DEVICE' to rtconfig.py
- fixed compiling error cuased by change in interrupt_gcc.S
Signed-off-by: Fan YANG <[email protected]>
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support cvitek sdhci drvier
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* update smp 4
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[bsp/rpi4] fixup startup issues
Signed-off-by: Shell <[email protected]>
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* serial-tty fix
* v2
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Signed-off-by: Shell <[email protected]>
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Signed-off-by: xqyjlj <[email protected]>
Signed-off-by: Shell <[email protected]>
Co-authored-by: xqyjlj <[email protected]>
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Signed-off-by: Shell <[email protected]>
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Signed-off-by: Shell <[email protected]>
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Signed-off-by: LiuLingze <[email protected]>
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Signed-off-by: LiuLingze <[email protected]>
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[libcpu/arm/cortex-a]修改arm/cortex-a启动方式，解决cortex-a开启SMP工作异常问题 (#8517)
Co-authored-by: wangzongqiang <[email protected]>
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Signed-off-by: Shell <[email protected]>
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Signed-off-by: Shell <[email protected]>
Co-authored-by: xqyjlj <[email protected]>
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时编译报错问题
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Co-authored-by: StackYuan <[email protected]>
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Signed-off-by: Shell <[email protected]>
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Including the patch for memory allocation, testsuites and fixups of
static analysis.
Signed-off-by: Shell <[email protected]>
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