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2026-01-31[components][clock_time] Refactor time subsystem around clock_time (#11111)Bernard Xiong
* [components][clock_time] Refactor time subsystem around clock_time Introduce the clock_time core with clock source/event separation, high-resolution scheduling, and boot-time helpers, plus clock_timer adapters for timer peripherals. Remove legacy ktime/cputime/hwtimer implementations and migrate arch and BSP time paths to the new subsystem while keeping POSIX time integration functional. Update drivers, Kconfig/SConscript wiring, documentation, and tests; add clock_time overview docs and align naming to clock_boottime/clock_hrtimer/clock_timer. * [components][clock_time] Use BSP-provided clock timer frequency on riscv64 * [risc-v] Use runtime clock timer frequency for tick and delays * [bsp] Add clock timer frequency hooks for riscv64 boards * [bsp] Update Renesas RA driver doc clock_timer link * [bsp] Sync zynqmp-r5-axu4ev rtconfig after config refresh * [bsp][rk3500] Update rk3500 clock configuration * [bsp][hpmicro] Add rt_hw_us_delay hook and update board delays * [bsp][stm32l496-st-nucleo] enable clock_time for hwtimer sample in ci * [bsp][hpmicro] Fix rtconfig include scope for hpm6750evk Move rtconfig.h include outside the ENET_MULTIPLE_PORT guard for hpm6750evk and hpm6750evk2 so configuration macros are available regardless of ENET settings. * [bsp][raspi3] select clock time for systimer * [bsp][hpm5300evk] Trim trailing blank line * [bsp][hpm5301evklite] Trim trailing blank line * [bsp][hpm5e00evk] Trim trailing blank line * [bsp][hpm6200evk] Trim trailing blank line * [bsp][hpm6300evk] Trim trailing blank line * [bsp][hpm6750evk] Trim trailing blank line * [bsp][hpm6750evk2] Trim trailing blank line * [bsp][hpm6750evkmini] Trim trailing blank line * [bsp][hpm6800evk] Trim trailing blank line * [bsp][hpm6e00evk] Trim trailing blank line * [bsp][nxp] switch lpc178x to gcc and remove mcx timer source * [bsp][stm32] fix the CONFIG_RT_USING_CLOCK_TIME issue. * [docs][clock_time] add clock time documentation * [docs][clock_time] Update clock time subsystem documentation - Update device driver index to use correct page reference - Clarify upper layer responsibilities in architecture overview - Update README to describe POSIX/libc, Soft RTC, and device driver usage - Refine architecture diagram with improved layout and color scheme - Remove obsolete clock_timer.md file * [kernel][utest] Trim trailing space * [clock_time] Fix hrtimer wrap handling * [clock_time] fix the static rt_inline issue * [clock_time] fix the rt_clock_hrtimer_control result issue
2026-01-13[libcpu][aarch64] Replace x8 with a callee-saved registerTang Qingmei
2026-01-12[risc-v][common64] Make rt_hw_cpu_shutdown weak to resolve multiple ↵Copilot
definition with RT_USING_DM (#11100) * Initial plan * [risc-v][common64] Make rt_hw_cpu_shutdown weak to fix multiple definition error Co-authored-by: BernardXiong <[email protected]> --------- Co-authored-by: copilot-swe-agent[bot] <[email protected]> Co-authored-by: BernardXiong <[email protected]>
2026-01-10[libcpu][arm][cortex-a] Fixup mmu setup earlylaidene
Correct the starting virtual address of _reset alignment to 16MB
2026-01-09Update libcpu/arm/cortex-a/gic.claidene
2026-01-09[docs][libcpu][arm][cortex-a] add comment for gic.claidene
2026-01-04[docs][libcpu][arm][cortex-a] add comment for mmu.h (#11104)caicunjun
* [docs][libcpu][arm][cortex-a] add comment for mmu.h * [docs][libcpu][arm][cortex-a] beautify comment for mmu.h * [docs][libcpu][arm][cortex-a] delete extra space at the end of lines
2025-12-26 [docs][libcpu][arm][cortex-a] update comment for start_gcc.S #11089caicunjun
2025-12-19[libcpu][aarch64] Update for DMGuEe-GUI
1. PSCI port to system power. 2. Support builtin fdt. 3. Update system aspace size. 4. Support DMA memory probe. 5. Fixup not backtrace in Serror for device bus fault. Signed-off-by: GuEe-GUI <[email protected]>
2025-12-11update: [libcpu][risc-v][common] allow overriding isr numbers for MCUFan YANG
- allow overriding the isr numbers via RT_HW_ISR_NUM macro Signed-off-by: Fan YANG <[email protected]>
2025-12-04[libcpu-riscv]: [surpport SMP]: Add SMP support for qemu-virt64-riscvTm-C-mT
1.Add the necessary function declarations for SMP enablement and implement the corresponding functionalities, including rt_hw_secondary_cpu_up, secondary_cpu_entry, rt_hw_local_irq_disable, rt_hw_local_irq_enable, rt_hw_secondary_cpu_idle_exec, rt_hw_spin_lock_init, rt_hw_spin_lock, rt_hw_spin_unlock, rt_hw_ipi_send, rt_hw_interrupt_set_priority, rt_hw_interrupt_get_priority, rt_hw_ipi_init, rt_hw_ipi_handler_install, and rt_hw_ipi_handler. 2.In the two functions (rt_hw_context_switch_to and rt_hw_context_switch) in context_gcc.S, add a call to rt_cpus_lock_status_restore to update the scheduler information. 3.If the MMU is enabled, use the .percpu section and record different hartids by configuring special page tables; if the MMU is not enabled, record them directly in the satp register. Additionally, add dynamic startup based on core configuration.The .percpu section is only used when both ARCH_MM_MMU and RT_USING_SMP are enabled. However, there is a certain amount of space waste since no macro guard is added for it in the link script currently. 4.The physical memory of QEMU started in CI is 128MB, so RT_HW_PAGE_END is modified from the original +256MB to +128MB. Modify the SConscript file under the common64 directory to include common/atomic_riscv.c in the compilation process. Signed-off-by: Mengchen Teng <[email protected]>
2025-11-16Reorganize Group names in build system for clarity and IDE integration #10923Copilot
2025-11-12[libcpu][cortex-a] Refactor FPU stack initialization for maintainability ↵Copilot
(#10919) * Initial plan * [libcpu][cortex-a] Improve FPU stack initialization implementation Co-authored-by: BernardXiong <[email protected]> * [libcpu][cortex-a] Replace FPU init loop with rt_memset Co-authored-by: BernardXiong <[email protected]> --------- Co-authored-by: copilot-swe-agent[bot] <[email protected]> Co-authored-by: BernardXiong <[email protected]>
2025-11-07[Components] Remove vbus component and realview-a8-vmm libcpu (#10863)Copilot
* Initial plan * Remove vbus component and related code Co-authored-by: BernardXiong <[email protected]> --------- Co-authored-by: copilot-swe-agent[bot] <[email protected]> Co-authored-by: BernardXiong <[email protected]>
2025-11-02[libcpu/arm/cortex-m33]: Fix incorrect CPU architecture in GCC context switchYucai Liu
The context_gcc.S file was incorrectly marked as cortex-m4 in both the doxygen comment and .cpu directive, while the IAR and KEIL versions correctly specify cortex-m33. This file uses ARMv8-M specific features (PSPLIM register, TrustZone support) that are not available in Cortex-M4. Changes: - Update doxygen group from cortex-m4 to cortex-m33 - Change .cpu directive from cortex-m4 to cortex-m33
2025-10-23aarch64: document the CNTFRQ_EL0Yonggang Luo
Signed-off-by: Yonggang Luo <[email protected]>
2025-10-21[aarch64] Fix rt_aspace_init error when KERNEL_VADDR_START >= 0x80000000Siwei Xu
2025-10-13Remove unused rt_hw_set_gtimer_frqYonggang Luo
2025-10-11bsp/w60x: fixes cppcheck: (#10781)Yonggang Luo
[cpp_check.py 80 INFO] bsp/w60x/drivers/drv_rtc.c:58:11: error: Syntax Error: AST broken, binary operator '&=' doesn't have two operands. [internalAstError] [cpp_check.py 80 INFO] libcpu/arm/s3c24x0/rtc.c:34:12: error: Expression 'RTCCON|=RTCCON|=0x01' depends on order of evaluation of side effects [unknownEvaluationOrder]
2025-10-10Remove rarely used rt_time_tYonggang Luo
next_delay should be rt_tick_t Use time_t for RT_DEVICE_CTRL_RTC_GET_TIME
2025-10-10[CPU/AARCH64] 增加 libcpu/aarch64 KERNEL_ASPACE_START 配置 #10757zhangyan
针对不同的 Aarch64 BSP 针对 KERNEL_VADDR_START 宏定义进行区分
2025-09-28fix:Fixed compilation error for libcpu/cortex-m4. (#10756)R b b666
2025-09-03fix(risc-v, virt64, plic): use volatile rw for claim and completeHaojin Tang
2025-09-01fix(risc-v, mmu): fix type mismatch of `_query`Haojin Tang
2025-09-01fix(risc-v/virt64, cpp): add spaces to fix `Wliteral-suffix`Haojin Tang
2025-09-01fix(riscv, cpp): remove `rt_hw_cpu_id` in `cpuport.h` to fix errorHaojin Tang
2025-09-01fix: warnings generated by Kconfig.maosql
2025-08-20[libcpu][cortex-m33]Added HardFault_Handler to save floating point registersRbb666
2025-08-19[libcpu][cortex-m4]Added HardFault_Handler to save floating point registers.Rbb666
2025-08-19[libcpu ][cm3]The parameter passed to the unified rt_exception_hook is ↵R b b666
exception_stack. (#10619)
2025-07-23[lwp][rv64] restore tp register in arch_thread_signal_enter to fix user-mode ↵Yulong Wang
memory access
2025-07-16[ARCH/AARCH64] Update Hypercall APIGuEe-GUI
Signed-off-by: GuEe-GUI <[email protected]>
2025-07-08[aarch64]Fixup linker warning #10466GUI
2025-07-07Fixup the boot EL checkGuEe-GUI
The boot EL will save in x0, when current EL is EL3, kernel will jump to the EL2 after EL3. But the x0 value is **3**, The init for EL2 will not work. To fix it: the EL3 should jump to the EL2 init branch with not check, and when SoC boot in EL2, kernel will jump to the EL2 test branch. Link: https://club.rt-thread.org/ask/question/ec320a6765389f67.html Signed-off-by: wusongjie <[email protected]>
2025-07-04[CPU/AARCH64] Fixup MMUGuEe-GUI
1. Configure the kernel default vaddr by RAM and TEXT offset. 2. Check the p_addr 2M align when set the stride in `rt_hw_mmu_map`. Signed-off-by: GuEe-GUI <[email protected]>
2025-06-24libcpu/bsp: fix the M33 assembly syntax errors and fix the compilation error ↵kurisaw
of bsp
2025-05-30[bsp]增加超睿DP1000 bsp支持ZhangJing
2025-05-30移除无用文件，该文件未被任何BSP使用Yaochenger
2025-05-30[libcpu/common] ↵Yaochenger
修正对RV32E的支持，RV32E不支持s2寄存器，修改为s1寄存器
2025-05-28[libcpu][risc-v]:add comment for the round down of symb_pczhangjing
2025-05-28[libcpu][risc-v] fix:only map the 1GB space where the original code segment ↵zhangjing
is located
2025-04-28import rercitach
2025-04-28Fix Aarch64 architecture runtime issuesrcitach
该问题由5b3320624da5149fc21c2d3e1f321d855e3d0dfe引入，导致工具链编译时加上了 -std=gnu99,其他架构是否出问题暂时未知
2025-04-13libcpu: aarch64: Fix NORMAL_NOCACHE_MEM attr (#10180)mouch6131
Signed-off-by: Cliff Chen <[email protected]> Signed-off-by: mouch6131 <[email protected]> Co-authored-by: Cliff Chen <[email protected]>
2025-04-11libcpu: riscv: declare external symbols insideChen Wang
libcpu/risc-v/common64/mmu.c uses the external symbol "__bss_end" (this symbol generally is defined in the link script file) and depends on the extern declaration of this symbol in the bsp's "board.h". This is not a problem in implementation, but it is not a good habit. If this extern symbol is used locally, just declare it locally should be better. In this way, there will be no dependency of the kernel core on the bsp header file. And there will be no special requirements for the bsp board code, such as the need to make extern declarations for these "__bss_end" symbols in "board.h". This patch currently only explicitly externly declares "__bss_end" inside libcpu itself. The code of "#include <board.h>" is kept, because the modification involved is too large, it is necessary to clean up the bsp involved before cleaning this include code line uniformly. Signed-off-by: Chen Wang <[email protected]>
2025-04-11libcpu: cleanup undefined rt_hw_mmu_kernel_map_init (#10177)Chen Wang
* libcpu: cleanup undefined rt_hw_mmu_kernel_map_init rt_hw_mmu_kernel_map_init() is declared in header files but no definition found, cleanup the code. Signed-off-by: Chen Wang <[email protected]> * bsp: allwinner: d1: remove calling of rt_hw_mmu_kernel_map_init rt_hw_mmu_kernel_map_init is an undefined function, calling it is meaningless. Signed-off-by: Chen Wang <[email protected]> --------- Signed-off-by: Chen Wang <[email protected]>
2025-03-28[libcpu][aarch64]fix gicv3 mpidr table (#9284)zms123456
* fix gicv3 mpidr error * phytium should support rt_cpu_mpidr_table by using common_setup
2025-03-18[bsp][stm32][artpi]:fix artpi nano (#10122)CYFS
2025-03-17[fix]Fix cm33 compilation problem when block is turned onRbb666
2025-03-17[libcpu][risc-v]add code for handling exception scenarios in _unmap_area.ligr
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