rt-thread.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author
2017-12-21	Merge pull request #1124 from SummerGGift/add_arm_8-byte_alignment	Bernard Xiong
	[libcpu]: add 8-byte alignment for arm architecture && optimize code …
2017-12-21	[libcpu]: add 8-byte alignment for arm architecture && optimize code format	SummerGift

2017-12-21	Merge pull request #1123 from SummerGGift/8-byte_alignment	Bernard Xiong
	[libcpu]: add 8-byte alignment for armv6 architecture
2017-12-21	[libcpu]: add 8-byte alignment for armv6 architecture	SummerGift

2017-12-21	[libcpu]:optimize code format	SummerGift

2017-12-21	[libcpu]:optimize code format	SummerGift

2017-12-21	[libcpu]: add 8-byte alignment for armv6 architecture	SummerGift

2017-12-19	[libcpu] Add ARCH_ARM_ARM9/11 type	Bernard Xiong

2017-11-22	[libcpu] add volatile for __asm.	SummerGift

2017-11-22	[libcpu] add volatile for asm (" mcr ") or asm (" mrc ") instruct.	SummerGift

2017-11-10	[libcpu]Support x1000 CPU	tangyuxin

2017-11-01	[BSP] add i.MX 6UL BSP	Bernard Xiong

2017-10-31	Update Kconfig.	bernard
	1. Add IPADDR/GWADDR etc; 2. Add Kconfig for libcpu.
2017-10-19	[bsp][at91sam9260] Fix the problem of the finsh function failure by using ↵	weety
	component initialization.
2017-10-16	[BSP] change the type of cmd.	bernard
	1. Change the type of cmd to 'int'; 2. Remove RT_LWIP_USING_RT_MEM macro;
2017-10-09	[libcpu] code cleanup for nds32.	bernard

2017-10-06	Update cpuport.c	Bernard Xiong

2017-10-06	Merge pull request #826 from ArcherChang/master	Bernard Xiong
	[BSP] Add Andes N1068 porting and simple bsp.
2017-09-14	Merge pull request #845 from caogos/master	Bernard Xiong
	[BSP] Add FPU option for loongson1c.
2017-09-13	在配置文件“rtconfig.h”中增加硬浮点FPU的配置项，	勤为本
	浮点经常会用到，所以默认使用硬浮点。
2017-09-01	update libcpu: cortex-m0 fault handlers always enable.	aozima

2017-08-26	[BSP] cleanup for hifive1 bsp.	Bernard Xiong

2017-08-25	[1] Andes N1068体系移植	ArcherChang
	a. Libc改用官方版本（工具链附带版本）； b. 去除未使用文件；
2017-08-25	Merge pull request #827 from caogos/master	Bernard Xiong
	[BSP] Add EMAC driver in loongson1C (ported by chinesebear, https://github.com/chinesebear/rtt-net)
2017-08-25	[1] 添加Andes N1068体系；	ArcherChang
	[2] 基于AE210P EVB板； [3] 详细信息参阅bsp/AE210P/readme文件夹；《Andes工程创建和调试》文档；等。
2017-08-23	update cortex-m libcpu: fixed compile error.	aozima

2017-08-23	添加龙芯1C片内网卡的驱动（原创作者是chinesebear，https://g ↵	勤为本
	ithub.com/chinesebear/rtt-net）
2017-08-18	update libcpu: ensure fault enable.	aozima

2017-08-10	Merge pull request #784 from zhangjun1996/master	Bernard Xiong
	[BSP] add bsp for sifive(risc-v e310).
2017-08-10	增加龙芯1c硬浮点的支持（可以使用硬浮点了）	勤为本

2017-07-31	modify： drivers/cpuusage.c	zhangjun
	modify： ../../libcpu/risc-v/e310/stack.c rmove unused macro definition modify： ../../src/idle.c Return to the original version
2017-07-31	Merge branch 'master' of https://github.com/RT-Thread/rt-thread	zhangjun
	add new bsp for risc-v
2017-07-31	new file： ../../libcpu/risc-v/e310/trap.c	zhangjun
	add file that forget to submit before auto change timer mtimercmp register on the base of RT_TICK_PER_SECOND in rtconfig.h no flashing led new file： ../../src/idle.c recover old file
2017-07-31	fix bug in context_gcc.s and start_gcc.s:	zhangjun
	save mie into stack msh running normaly
2017-07-30	fix bug in rt_hw_context_switch_interrupt_do	zhangjun
	save sp to old thread clear rt_thread_switch_interrupt_flag always enable interrupt after rt_hw_context_switch judeg the type of interrupt in trap_entry, then call handler(Machine timer interrupt of Machine external interrupt)
2017-07-30	修改： ../../libcpu/risc-v/e310/context_gcc.S	zhangjun
	enable interrupt after return form rt_hw_context_switch
2017-07-29	fix trap_entry	zhangjun

2017-07-26	modified: ../../libcpu/risc-v/e310/context_gcc.S	zhangjun
	fix open timer intrrupt
2017-07-26	remove "csrrc a5, mstatus, MSTATUS_MIE" in rt_hw_interrupt_enable();	zhangjun
	it will lead to interrupt again in interrupt
2017-07-20	支持GPIO中断（外部中断）	勤为本

2017-07-20	将支持的中断个数从32个扩展到160个，至此可以支持所有中断	勤为本

2017-07-18	修正龙芯1c的中断号	勤为本

2017-07-17	deleted: rtthread.s /just for debug/	zhangjun
	modified: ../../libcpu/risc-v/e310/context_gcc.S change ret to mret and switch to new task with mepc
2017-07-17	add context_gcc.s	zhangjun

2017-02-06	Add libcpu/arm/am335x/context_iar.S file	zchong-cht

2016-06-15	flush cache after exception code install	kontais

2016-05-20	[BSP] Update VFP code in armv6.	Bernard Xiong
	committed by FH.
2016-05-20	[BSP] Enable VFP.	Bernard Xiong
	committed by FH.
2016-04-24	[BSP] Add BSP for Ingenic X1000 CPU	Bernard Xiong

2016-04-19	start exception by chinesebear	chinesebear