+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 ((q31_t)(0x100))
+#define DELTA_Q15 ((q15_t)0x5)
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+ #define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE 512
+#define FAST_MATH_Q31_SHIFT (32 - 10)
+#define FAST_MATH_Q15_SHIFT (16 - 10)
+#define CONTROLLER_Q31_SHIFT (32 - 9)
+#define TABLE_SPACING_Q31 0x400000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+ /**
+ * @brief Macros for complex numbers
+ */
+
+ /* Dimension C vector space */
+ #define CMPLX_DIM 2
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief vector types
+ */
+#if defined(ARM_MATH_NEON) || defined (ARM_MATH_MVEI)
+ /**
+ * @brief 64-bit fractional 128-bit vector data type in 1.63 format
+ */
+ typedef int64x2_t q63x2_t;
+
+ /**
+ * @brief 32-bit fractional 128-bit vector data type in 1.31 format.
+ */
+ typedef int32x4_t q31x4_t;
+
+ /**
+ * @brief 16-bit fractional 128-bit vector data type with 16-bit alignement in 1.15 format.
+ */
+ typedef __ALIGNED(2) int16x8_t q15x8_t;
+
+ /**
+ * @brief 8-bit fractional 128-bit vector data type with 8-bit alignement in 1.7 format.
+ */
+ typedef __ALIGNED(1) int8x16_t q7x16_t;
+
+ /**
+ * @brief 32-bit fractional 128-bit vector pair data type in 1.31 format.
+ */
+ typedef int32x4x2_t q31x4x2_t;
+
+ /**
+ * @brief 32-bit fractional 128-bit vector quadruplet data type in 1.31 format.
+ */
+ typedef int32x4x4_t q31x4x4_t;
+
+ /**
+ * @brief 16-bit fractional 128-bit vector pair data type in 1.15 format.
+ */
+ typedef int16x8x2_t q15x8x2_t;
+
+ /**
+ * @brief 16-bit fractional 128-bit vector quadruplet data type in 1.15 format.
+ */
+ typedef int16x8x4_t q15x8x4_t;
+
+ /**
+ * @brief 8-bit fractional 128-bit vector pair data type in 1.7 format.
+ */
+ typedef int8x16x2_t q7x16x2_t;
+
+ /**
+ * @brief 8-bit fractional 128-bit vector quadruplet data type in 1.7 format.
+ */
+ typedef int8x16x4_t q7x16x4_t;
+
+ /**
+ * @brief 32-bit fractional data type in 9.23 format.
+ */
+ typedef int32_t q23_t;
+
+ /**
+ * @brief 32-bit fractional 128-bit vector data type in 9.23 format.
+ */
+ typedef int32x4_t q23x4_t;
+
+ /**
+ * @brief 64-bit status 128-bit vector data type.
+ */
+ typedef int64x2_t status64x2_t;
+
+ /**
+ * @brief 32-bit status 128-bit vector data type.
+ */
+ typedef int32x4_t status32x4_t;
+
+ /**
+ * @brief 16-bit status 128-bit vector data type.
+ */
+ typedef int16x8_t status16x8_t;
+
+ /**
+ * @brief 8-bit status 128-bit vector data type.
+ */
+ typedef int8x16_t status8x16_t;
+
+
+#endif
+
+#if defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF) /* floating point vector*/
+ /**
+ * @brief 32-bit floating-point 128-bit vector type
+ */
+ typedef float32x4_t f32x4_t;
+
+#if defined(ARM_MATH_FLOAT16)
+ /**
+ * @brief 16-bit floating-point 128-bit vector data type
+ */
+ typedef __ALIGNED(2) float16x8_t f16x8_t;
+#endif
+
+ /**
+ * @brief 32-bit floating-point 128-bit vector pair data type
+ */
+ typedef float32x4x2_t f32x4x2_t;
+
+ /**
+ * @brief 32-bit floating-point 128-bit vector quadruplet data type
+ */
+ typedef float32x4x4_t f32x4x4_t;
+
+#if defined(ARM_MATH_FLOAT16)
+ /**
+ * @brief 16-bit floating-point 128-bit vector pair data type
+ */
+ typedef float16x8x2_t f16x8x2_t;
+
+ /**
+ * @brief 16-bit floating-point 128-bit vector quadruplet data type
+ */
+ typedef float16x8x4_t f16x8x4_t;
+#endif
+
+ /**
+ * @brief 32-bit ubiquitous 128-bit vector data type
+ */
+ typedef union _any32x4_t
+ {
+ float32x4_t f;
+ int32x4_t i;
+ } any32x4_t;
+
+#if defined(ARM_MATH_FLOAT16)
+ /**
+ * @brief 16-bit ubiquitous 128-bit vector data type
+ */
+ typedef union _any16x8_t
+ {
+ float16x8_t f;
+ int16x8_t i;
+ } any16x8_t;
+#endif
+
+#endif
+
+#if defined(ARM_MATH_NEON)
+ /**
+ * @brief 32-bit fractional 64-bit vector data type in 1.31 format.
+ */
+ typedef int32x2_t q31x2_t;
+
+ /**
+ * @brief 16-bit fractional 64-bit vector data type in 1.15 format.
+ */
+ typedef __ALIGNED(2) int16x4_t q15x4_t;
+
+ /**
+ * @brief 8-bit fractional 64-bit vector data type in 1.7 format.
+ */
+ typedef __ALIGNED(1) int8x8_t q7x8_t;
+
+ /**
+ * @brief 32-bit float 64-bit vector data type.
+ */
+ typedef float32x2_t f32x2_t;
+
+#if defined(ARM_MATH_FLOAT16)
+ /**
+ * @brief 16-bit float 64-bit vector data type.
+ */
+ typedef __ALIGNED(2) float16x4_t f16x4_t;
+#endif
+
+ /**
+ * @brief 32-bit floating-point 128-bit vector triplet data type
+ */
+ typedef float32x4x3_t f32x4x3_t;
+
+#if defined(ARM_MATH_FLOAT16)
+ /**
+ * @brief 16-bit floating-point 128-bit vector triplet data type
+ */
+ typedef float16x8x3_t f16x8x3_t;
+#endif
+
+ /**
+ * @brief 32-bit fractional 128-bit vector triplet data type in 1.31 format
+ */
+ typedef int32x4x3_t q31x4x3_t;
+
+ /**
+ * @brief 16-bit fractional 128-bit vector triplet data type in 1.15 format
+ */
+ typedef int16x8x3_t q15x8x3_t;
+
+ /**
+ * @brief 8-bit fractional 128-bit vector triplet data type in 1.7 format
+ */
+ typedef int8x16x3_t q7x16x3_t;
+
+ /**
+ * @brief 32-bit floating-point 64-bit vector pair data type
+ */
+ typedef float32x2x2_t f32x2x2_t;
+
+ /**
+ * @brief 32-bit floating-point 64-bit vector triplet data type
+ */
+ typedef float32x2x3_t f32x2x3_t;
+
+ /**
+ * @brief 32-bit floating-point 64-bit vector quadruplet data type
+ */
+ typedef float32x2x4_t f32x2x4_t;
+
+#if defined(ARM_MATH_FLOAT16)
+ /**
+ * @brief 16-bit floating-point 64-bit vector pair data type
+ */
+ typedef float16x4x2_t f16x4x2_t;
+
+ /**
+ * @brief 16-bit floating-point 64-bit vector triplet data type
+ */
+ typedef float16x4x3_t f16x4x3_t;
+
+ /**
+ * @brief 16-bit floating-point 64-bit vector quadruplet data type
+ */
+ typedef float16x4x4_t f16x4x4_t;
+#endif
+
+ /**
+ * @brief 32-bit fractional 64-bit vector pair data type in 1.31 format
+ */
+ typedef int32x2x2_t q31x2x2_t;
+
+ /**
+ * @brief 32-bit fractional 64-bit vector triplet data type in 1.31 format
+ */
+ typedef int32x2x3_t q31x2x3_t;
+
+ /**
+ * @brief 32-bit fractional 64-bit vector quadruplet data type in 1.31 format
+ */
+ typedef int32x4x3_t q31x2x4_t;
+
+ /**
+ * @brief 16-bit fractional 64-bit vector pair data type in 1.15 format
+ */
+ typedef int16x4x2_t q15x4x2_t;
+
+ /**
+ * @brief 16-bit fractional 64-bit vector triplet data type in 1.15 format
+ */
+ typedef int16x4x2_t q15x4x3_t;
+
+ /**
+ * @brief 16-bit fractional 64-bit vector quadruplet data type in 1.15 format
+ */
+ typedef int16x4x3_t q15x4x4_t;
+
+ /**
+ * @brief 8-bit fractional 64-bit vector pair data type in 1.7 format
+ */
+ typedef int8x8x2_t q7x8x2_t;
+
+ /**
+ * @brief 8-bit fractional 64-bit vector triplet data type in 1.7 format
+ */
+ typedef int8x8x3_t q7x8x3_t;
+
+ /**
+ * @brief 8-bit fractional 64-bit vector quadruplet data type in 1.7 format
+ */
+ typedef int8x8x4_t q7x8x4_t;
+
+ /**
+ * @brief 32-bit ubiquitous 64-bit vector data type
+ */
+ typedef union _any32x2_t
+ {
+ float32x2_t f;
+ int32x2_t i;
+ } any32x2_t;
+
+#if defined(ARM_MATH_FLOAT16)
+ /**
+ * @brief 16-bit ubiquitous 64-bit vector data type
+ */
+ typedef union _any16x4_t
+ {
+ float16x4_t f;
+ int16x4_t i;
+ } any16x4_t;
+#endif
+
+ /**
+ * @brief 32-bit status 64-bit vector data type.
+ */
+ typedef int32x4_t status32x2_t;
+
+ /**
+ * @brief 16-bit status 64-bit vector data type.
+ */
+ typedef int16x8_t status16x4_t;
+
+ /**
+ * @brief 8-bit status 64-bit vector data type.
+ */
+ typedef int8x16_t status8x8_t;
+
+#endif
+
+
+
+/**
+ @brief definition to read/write two 16 bit values.
+ @deprecated
+ */
+#if defined ( __CC_ARM )
+ #define __SIMD32_TYPE int32_t __packed
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+ #define __SIMD32_TYPE int32_t
+#elif defined ( __GNUC__ )
+ #define __SIMD32_TYPE int32_t
+#elif defined ( __ICCARM__ )
+ #define __SIMD32_TYPE int32_t __packed
+#elif defined ( __TI_ARM__ )
+ #define __SIMD32_TYPE int32_t
+#elif defined ( __CSMC__ )
+ #define __SIMD32_TYPE int32_t
+#elif defined ( __TASKING__ )
+ #define __SIMD32_TYPE __un(aligned) int32_t
+#elif defined(_MSC_VER )
+ #define __SIMD32_TYPE int32_t
+#else
+ #error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr))
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr))
+#define __SIMD64(addr) (*( int64_t **) & (addr))
+
+#define STEP(x) (x) <= 0 ? 0 : 1
+#define SQ(x) ((x) * (x))
+
+/* SIMD replacement */
+
+
+/**
+ @brief Read 2 Q15 from Q15 pointer.
+ @param[in] pQ15 points to input value
+ @return Q31 value
+ */
+__STATIC_FORCEINLINE q31_t read_q15x2 (
+ q15_t * pQ15)
+{
+ q31_t val;
+
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (&val, pQ15, 4);
+#else
+ val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF) ;
+#endif
+
+ return (val);
+}
+
+/**
+ @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards.
+ @param[in] pQ15 points to input value
+ @return Q31 value
+ */
+__STATIC_FORCEINLINE q31_t read_q15x2_ia (
+ q15_t ** pQ15)
+{
+ q31_t val;
+
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (&val, *pQ15, 4);
+#else
+ val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF);
+#endif
+
+ *pQ15 += 2;
+ return (val);
+}
+
+/**
+ @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards.
+ @param[in] pQ15 points to input value
+ @return Q31 value
+ */
+__STATIC_FORCEINLINE q31_t read_q15x2_da (
+ q15_t ** pQ15)
+{
+ q31_t val;
+
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (&val, *pQ15, 4);
+#else
+ val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF);
+#endif
+
+ *pQ15 -= 2;
+ return (val);
+}
+
+/**
+ @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards.
+ @param[in] pQ15 points to input value
+ @param[in] value Q31 value
+ @return none
+ */
+__STATIC_FORCEINLINE void write_q15x2_ia (
+ q15_t ** pQ15,
+ q31_t value)
+{
+ q31_t val = value;
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (*pQ15, &val, 4);
+#else
+ (*pQ15)[0] = (val & 0x0FFFF);
+ (*pQ15)[1] = (val >> 16) & 0x0FFFF;
+#endif
+
+ *pQ15 += 2;
+}
+
+/**
+ @brief Write 2 Q15 to Q15 pointer.
+ @param[in] pQ15 points to input value
+ @param[in] value Q31 value
+ @return none
+ */
+__STATIC_FORCEINLINE void write_q15x2 (
+ q15_t * pQ15,
+ q31_t value)
+{
+ q31_t val = value;
+
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (pQ15, &val, 4);
+#else
+ pQ15[0] = val & 0x0FFFF;
+ pQ15[1] = val >> 16;
+#endif
+}
+
+
+/**
+ @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards.
+ @param[in] pQ7 points to input value
+ @return Q31 value
+ */
+__STATIC_FORCEINLINE q31_t read_q7x4_ia (
+ q7_t ** pQ7)
+{
+ q31_t val;
+
+
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (&val, *pQ7, 4);
+#else
+ val =(((*pQ7)[3] & 0x0FF) << 24) | (((*pQ7)[2] & 0x0FF) << 16) | (((*pQ7)[1] & 0x0FF) << 8) | ((*pQ7)[0] & 0x0FF);
+#endif
+
+ *pQ7 += 4;
+
+ return (val);
+}
+
+/**
+ @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards.
+ @param[in] pQ7 points to input value
+ @return Q31 value
+ */
+__STATIC_FORCEINLINE q31_t read_q7x4_da (
+ q7_t ** pQ7)
+{
+ q31_t val;
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (&val, *pQ7, 4);
+#else
+ val = ((((*pQ7)[3]) & 0x0FF) << 24) | ((((*pQ7)[2]) & 0x0FF) << 16) | ((((*pQ7)[1]) & 0x0FF) << 8) | ((*pQ7)[0] & 0x0FF);
+#endif
+ *pQ7 -= 4;
+
+ return (val);
+}
+
+/**
+ @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards.
+ @param[in] pQ7 points to input value
+ @param[in] value Q31 value
+ @return none
+ */
+__STATIC_FORCEINLINE void write_q7x4_ia (
+ q7_t ** pQ7,
+ q31_t value)
+{
+ q31_t val = value;
+#ifdef __ARM_FEATURE_UNALIGNED
+ memcpy (*pQ7, &val, 4);
+#else
+ (*pQ7)[0] = val & 0x0FF;
+ (*pQ7)[1] = (val >> 8) & 0x0FF;
+ (*pQ7)[2] = (val >> 16) & 0x0FF;
+ (*pQ7)[3] = (val >> 24) & 0x0FF;
+
+#endif
+ *pQ7 += 4;
+}
+
+/*
+
+Normally those kind of definitions are in a compiler file
+in Core or Core_A.
+
+But for MSVC compiler it is a bit special. The goal is very specific
+to CMSIS-DSP and only to allow the use of this library from other
+systems like Python or Matlab.
+
+MSVC is not going to be used to cross-compile to ARM. So, having a MSVC
+compiler file in Core or Core_A would not make sense.
+
+*/
+#if defined ( _MSC_VER ) || defined(__GNUC_PYTHON__)
+ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data)
+ {
+ if (data == 0U) { return 32U; }
+
+ uint32_t count = 0U;
+ uint32_t mask = 0x80000000U;
+
+ while ((data & mask) == 0U)
+ {
+ count += 1U;
+ mask = mask >> 1U;
+ }
+ return count;
+ }
+
+ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+ {
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+ }
+
+ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+ {
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+ }
+#endif
+
+#ifndef ARM_MATH_DSP
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+ #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+ #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+#endif
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+ #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+ #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ __STATIC_FORCEINLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ __STATIC_FORCEINLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ __STATIC_FORCEINLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ __STATIC_FORCEINLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+ __STATIC_FORCEINLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y) ) );
+ }
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+ __STATIC_FORCEINLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ const q31_t * pRecipTable)
+ {
+ q31_t out;
+ uint32_t tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if (in > 0)
+ {
+ signBits = ((uint32_t) (__CLZ( in) - 1));
+ }
+ else
+ {
+ signBits = ((uint32_t) (__CLZ(-in) - 1));
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 24);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0U; i < 2U; i++)
+ {
+ tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+ tempVal = 0x7FFFFFFFu - tempVal;
+ /* 1.31 with exp 1 */
+ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1U);
+ }
+
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+ __STATIC_FORCEINLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ const q15_t * pRecipTable)
+ {
+ q15_t out = 0;
+ uint32_t tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if (in > 0)
+ {
+ signBits = ((uint32_t)(__CLZ( in) - 17));
+ }
+ else
+ {
+ signBits = ((uint32_t)(__CLZ(-in) - 17));
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 8);
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0U; i < 2U; i++)
+ {
+ tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFFu - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+ }
+
+/**
+ * @brief Integer exponentiation
+ * @param[in] x value
+ * @param[in] nb integer exponent >= 1
+ * @return x^nb
+ *
+ */
+__STATIC_INLINE float32_t arm_exponent_f32(float32_t x, int32_t nb)
+{
+ float32_t r = x;
+ nb --;
+ while(nb > 0)
+ {
+ r = r * x;
+ nb--;
+ }
+ return(r);
+}
+
+/**
+ * @brief 64-bit to 32-bit unsigned normalization
+ * @param[in] in is input unsigned long long value
+ * @param[out] normalized is the 32-bit normalized value
+ * @param[out] norm is norm scale
+ */
+__STATIC_INLINE void arm_norm_64_to_32u(uint64_t in, int32_t * normalized, int32_t *norm)
+{
+ int32_t n1;
+ int32_t hi = (int32_t) (in >> 32);
+ int32_t lo = (int32_t) ((in << 32) >> 32);
+
+ n1 = __CLZ(hi) - 32;
+ if (!n1)
+ {
+ /*
+ * input fits in 32-bit
+ */
+ n1 = __CLZ(lo);
+ if (!n1)
+ {
+ /*
+ * MSB set, need to scale down by 1
+ */
+ *norm = -1;
+ *normalized = (((uint32_t) lo) >> 1);
+ } else
+ {
+ if (n1 == 32)
+ {
+ /*
+ * input is zero
+ */
+ *norm = 0;
+ *normalized = 0;
+ } else
+ {
+ /*
+ * 32-bit normalization
+ */
+ *norm = n1 - 1;
+ *normalized = lo << *norm;
+ }
+ }
+ } else
+ {
+ /*
+ * input fits in 64-bit
+ */
+ n1 = 1 - n1;
+ *norm = -n1;
+ /*
+ * 64 bit normalization
+ */
+ *normalized = (((uint32_t) lo) >> n1) | (hi << (32 - n1));
+ }
+}
+
+__STATIC_INLINE q31_t arm_div_q63_to_q31(q63_t num, q31_t den)
+{
+ q31_t result;
+ uint64_t absNum;
+ int32_t normalized;
+ int32_t norm;
+
+ /*
+ * if sum fits in 32bits
+ * avoid costly 64-bit division
+ */
+ absNum = num > 0 ? num : -num;
+ arm_norm_64_to_32u(absNum, &normalized, &norm);
+ if (norm > 0)
+ /*
+ * 32-bit division
+ */
+ result = (q31_t) num / den;
+ else
+ /*
+ * 64-bit division
+ */
+ result = (q31_t) (num / den);
+
+ return result;
+}
+
+
+/*
+ * @brief C custom defined intrinsic functions
+ */
+#if !defined (ARM_MATH_DSP)
+
+ /*
+ * @brief C custom defined QADD8
+ */
+ __STATIC_FORCEINLINE uint32_t __QADD8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB8
+ */
+ __STATIC_FORCEINLINE uint32_t __QSUB8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QADD16
+ */
+ __STATIC_FORCEINLINE uint32_t __QADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
+ q31_t r = 0, s = 0;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHADD16
+ */
+ __STATIC_FORCEINLINE uint32_t __SHADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB16
+ */
+ __STATIC_FORCEINLINE uint32_t __QSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSUB16
+ */
+ __STATIC_FORCEINLINE uint32_t __SHSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QASX
+ */
+ __STATIC_FORCEINLINE uint32_t __QASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHASX
+ */
+ __STATIC_FORCEINLINE uint32_t __SHASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSAX
+ */
+ __STATIC_FORCEINLINE uint32_t __QSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSAX
+ */
+ __STATIC_FORCEINLINE uint32_t __SHSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSDX
+ */
+ __STATIC_FORCEINLINE uint32_t __SMUSDX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+ /*
+ * @brief C custom defined SMUADX
+ */
+ __STATIC_FORCEINLINE uint32_t __SMUADX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined QADD
+ */
+ __STATIC_FORCEINLINE int32_t __QADD(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB
+ */
+ __STATIC_FORCEINLINE int32_t __QSUB(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined SMLAD
+ */
+ __STATIC_FORCEINLINE uint32_t __SMLAD(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLADX
+ */
+ __STATIC_FORCEINLINE uint32_t __SMLADX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLSDX
+ */
+ __STATIC_FORCEINLINE uint32_t __SMLSDX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALD
+ */
+ __STATIC_FORCEINLINE uint64_t __SMLALD(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALDX
+ */
+ __STATIC_FORCEINLINE uint64_t __SMLALDX(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUAD
+ */
+ __STATIC_FORCEINLINE uint32_t __SMUAD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSD
+ */
+ __STATIC_FORCEINLINE uint32_t __SMUSD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16
+ */
+ __STATIC_FORCEINLINE uint32_t __SXTB16(
+ uint32_t x)
+ {
+ return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+ ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
+ }
+
+ /*
+ * @brief C custom defined SMMLA
+ */
+ __STATIC_FORCEINLINE int32_t __SMMLA(
+ int32_t x,
+ int32_t y,
+ int32_t sum)
+ {
+ return (sum + (int32_t) (((int64_t) x * y) >> 32));
+ }
+
+#endif /* !defined (ARM_MATH_DSP) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] S points to an instance of the Q7 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ const q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] S points to an instance of the Q15 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter (fast version).
+ * @param[in] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns either
+ * ARM_MATH_SUCCESS if initialization was successful or
+ * ARM_MATH_ARGUMENT_ERROR if numTaps is not a supported value.
+ */
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter (fast version).
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] S points to an instance of the floating-point FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ const q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q15;
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ const q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ const float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_casd_df1_inst_f32;
+
+#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+ /**
+ * @brief Instance structure for the modified Biquad coefs required by vectorized code.
+ */
+ typedef struct
+ {
+ float32_t coeffs[8][4]; /**< Points to the array of modified coefficients. The array is of length 32. There is one per stage */
+ } arm_biquad_mod_coef_f32;
+#endif
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pCoeffsMod points to the modified filter coefficients (only MVE version).
+ * @param[in] pState points to the state buffer.
+ */
+#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+ void arm_biquad_cascade_df1_mve_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ arm_biquad_mod_coef_f32 * pCoeffsMod,
+ float32_t * pState);
+#endif
+
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Compute the logical bitwise AND of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_and_u16(
+ const uint16_t * pSrcA,
+ const uint16_t * pSrcB,
+ uint16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise AND of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_and_u32(
+ const uint32_t * pSrcA,
+ const uint32_t * pSrcB,
+ uint32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise AND of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_and_u8(
+ const uint8_t * pSrcA,
+ const uint8_t * pSrcB,
+ uint8_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise OR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_or_u16(
+ const uint16_t * pSrcA,
+ const uint16_t * pSrcB,
+ uint16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise OR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_or_u32(
+ const uint32_t * pSrcA,
+ const uint32_t * pSrcB,
+ uint32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise OR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_or_u8(
+ const uint8_t * pSrcA,
+ const uint8_t * pSrcB,
+ uint8_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise NOT of a fixed-point vector.
+ * @param[in] pSrc points to input vector
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_not_u16(
+ const uint16_t * pSrc,
+ uint16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise NOT of a fixed-point vector.
+ * @param[in] pSrc points to input vector
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_not_u32(
+ const uint32_t * pSrc,
+ uint32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise NOT of a fixed-point vector.
+ * @param[in] pSrc points to input vector
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_not_u8(
+ const uint8_t * pSrc,
+ uint8_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Compute the logical bitwise XOR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_xor_u16(
+ const uint16_t * pSrcA,
+ const uint16_t * pSrcB,
+ uint16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise XOR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_xor_u32(
+ const uint32_t * pSrcA,
+ const uint32_t * pSrcB,
+ uint32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise XOR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_xor_u8(
+ const uint8_t * pSrcA,
+ const uint8_t * pSrcB,
+ uint8_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Struct for specifying sorting algorithm
+ */
+ typedef enum
+ {
+ ARM_SORT_BITONIC = 0,
+ /**< Bitonic sort */
+ ARM_SORT_BUBBLE = 1,
+ /**< Bubble sort */
+ ARM_SORT_HEAP = 2,
+ /**< Heap sort */
+ ARM_SORT_INSERTION = 3,
+ /**< Insertion sort */
+ ARM_SORT_QUICK = 4,
+ /**< Quick sort */
+ ARM_SORT_SELECTION = 5
+ /**< Selection sort */
+ } arm_sort_alg;
+
+ /**
+ * @brief Struct for specifying sorting algorithm
+ */
+ typedef enum
+ {
+ ARM_SORT_DESCENDING = 0,
+ /**< Descending order (9 to 0) */
+ ARM_SORT_ASCENDING = 1
+ /**< Ascending order (0 to 9) */
+ } arm_sort_dir;
+
+ /**
+ * @brief Instance structure for the sorting algorithms.
+ */
+ typedef struct
+ {
+ arm_sort_alg alg; /**< Sorting algorithm selected */
+ arm_sort_dir dir; /**< Sorting order (direction) */
+ } arm_sort_instance_f32;
+
+ /**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_sort_f32(
+ const arm_sort_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @param[in,out] S points to an instance of the sorting structure.
+ * @param[in] alg Selected algorithm.
+ * @param[in] dir Sorting order.
+ */
+ void arm_sort_init_f32(
+ arm_sort_instance_f32 * S,
+ arm_sort_alg alg,
+ arm_sort_dir dir);
+
+ /**
+ * @brief Instance structure for the sorting algorithms.
+ */
+ typedef struct
+ {
+ arm_sort_dir dir; /**< Sorting order (direction) */
+ float32_t * buffer; /**< Working buffer */
+ } arm_merge_sort_instance_f32;
+
+ /**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in,out] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_merge_sort_f32(
+ const arm_merge_sort_instance_f32 * S,
+ float32_t *pSrc,
+ float32_t *pDst,
+ uint32_t blockSize);
+
+ /**
+ * @param[in,out] S points to an instance of the sorting structure.
+ * @param[in] dir Sorting order.
+ * @param[in] buffer Working buffer.
+ */
+ void arm_merge_sort_init_f32(
+ arm_merge_sort_instance_f32 * S,
+ arm_sort_dir dir,
+ float32_t * buffer);
+
+ /**
+ * @brief Struct for specifying cubic spline type
+ */
+ typedef enum
+ {
+ ARM_SPLINE_NATURAL = 0, /**< Natural spline */
+ ARM_SPLINE_PARABOLIC_RUNOUT = 1 /**< Parabolic runout spline */
+ } arm_spline_type;
+
+ /**
+ * @brief Instance structure for the floating-point cubic spline interpolation.
+ */
+ typedef struct
+ {
+ arm_spline_type type; /**< Type (boundary conditions) */
+ const float32_t * x; /**< x values */
+ const float32_t * y; /**< y values */
+ uint32_t n_x; /**< Number of known data points */
+ float32_t * coeffs; /**< Coefficients buffer (b,c, and d) */
+ } arm_spline_instance_f32;
+
+ /**
+ * @brief Processing function for the floating-point cubic spline interpolation.
+ * @param[in] S points to an instance of the floating-point spline structure.
+ * @param[in] xq points to the x values ot the interpolated data points.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples of output data.
+ */
+ void arm_spline_f32(
+ arm_spline_instance_f32 * S,
+ const float32_t * xq,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point cubic spline interpolation.
+ * @param[in,out] S points to an instance of the floating-point spline structure.
+ * @param[in] type type of cubic spline interpolation (boundary conditions)
+ * @param[in] x points to the x values of the known data points.
+ * @param[in] y points to the y values of the known data points.
+ * @param[in] n number of known data points.
+ * @param[in] coeffs coefficients array for b, c, and d
+ * @param[in] tempBuffer buffer array for internal computations
+ */
+ void arm_spline_init_f32(
+ arm_spline_instance_f32 * S,
+ arm_spline_type type,
+ const float32_t * x,
+ const float32_t * y,
+ uint32_t n,
+ float32_t * coeffs,
+ float32_t * tempBuffer);
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float64_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f64;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q31;
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pScratch);
+
+ /**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#if !defined (ARM_MATH_DSP)
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the q15 PID Control structure
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+#if defined(ARM_MATH_MVEI)
+ const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \
+ const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \
+ const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \
+ const q15_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \
+ const q15_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \
+ const q15_t *rearranged_twiddle_stride3;
+#endif
+ } arm_cfft_instance_q15;
+
+arm_status arm_cfft_init_q15(
+ arm_cfft_instance_q15 * S,
+ uint16_t fftLen);
+
+void arm_cfft_q15(
+ const arm_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+#if defined(ARM_MATH_MVEI)
+ const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \
+ const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \
+ const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \
+ const q31_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \
+ const q31_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \
+ const q31_t *rearranged_twiddle_stride3;
+#endif
+ } arm_cfft_instance_q31;
+
+arm_status arm_cfft_init_q31(
+ arm_cfft_instance_q31 * S,
+ uint16_t fftLen);
+
+void arm_cfft_q31(
+ const arm_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+ const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \
+ const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \
+ const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \
+ const float32_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \
+ const float32_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \
+ const float32_t *rearranged_twiddle_stride3;
+#endif
+ } arm_cfft_instance_f32;
+
+
+ arm_status arm_cfft_init_f32(
+ arm_cfft_instance_f32 * S,
+ uint16_t fftLen);
+
+ void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+
+ /**
+ * @brief Instance structure for the Double Precision Floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float64_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_f64;
+
+ void arm_cfft_f64(
+ const arm_cfft_instance_f64 * S,
+ float64_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ const q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ const q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+#if defined(ARM_MATH_MVEI)
+ arm_cfft_instance_q15 cfftInst;
+#else
+ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+#endif
+ } arm_rfft_instance_q15;
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ const q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ const q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+#if defined(ARM_MATH_MVEI)
+ arm_cfft_instance_q31 cfftInst;
+#else
+ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+#endif
+ } arm_rfft_instance_q31;
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ const float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ const float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the Double Precision Floating-point RFFT/RIFFT function.
+ */
+typedef struct
+ {
+ arm_cfft_instance_f64 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ const float64_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f64 ;
+
+arm_status arm_rfft_fast_init_f64 (
+ arm_rfft_fast_instance_f64 * S,
+ uint16_t fftLen);
+
+
+void arm_rfft_fast_f64(
+ arm_rfft_fast_instance_f64 * S,
+ float64_t * p, float64_t * pOut,
+ uint8_t ifftFlag);
+
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct
+ {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+
+ void arm_rfft_fast_f32(
+ const arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ const float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ const float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
+ */
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ const q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ const q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q31 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ const q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ const q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q15 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_f32(
+ const float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q7(
+ const q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q15(
+ const q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q31(
+ const q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q7(
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q7(
+ const q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q15(
+ const q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q31(
+ const q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_f32(
+ const float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q7(
+ const q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q15(
+ const q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q31(
+ const q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q7(
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q7(
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_f32(
+ const float32_t * pSrcA,
+ uint32_t srcALen,
+ const float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_fast_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_f32(
+ const float32_t * pSrcA,
+ uint32_t srcALen,
+ const float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q31;
+
+/**
+ @brief Instance structure for floating-point FIR decimator.
+ */
+typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_f32;
+
+
+/**
+ @brief Processing function for floating-point FIR decimator.
+ @param[in] S points to an instance of the floating-point FIR decimator structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ */
+void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ @brief Initialization function for the floating-point FIR decimator.
+ @param[in,out] S points to an instance of the floating-point FIR decimator structure
+ @param[in] numTaps number of coefficients in the filter
+ @param[in] M decimation factor
+ @param[in] pCoeffs points to the filter coefficients
+ @param[in] pState points to the state buffer
+ @param[in] blockSize number of input samples to process per call
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M
+ */
+arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ const q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ const q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ const float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f64;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64 * S,
+ const float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+#if defined(ARM_MATH_NEON)
+void arm_biquad_cascade_df2T_compute_coefs_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs);
+#endif
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ const float64_t * pCoeffs,
+ float64_t * pState);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ const q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ const q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ */
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ const q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ const q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_f32(
+ const float32_t * pSrcA,
+ uint32_t srcALen,
+ const float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+/**
+ @brief Correlation of Q15 sequences
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+*/
+void arm_correlate_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+/**
+ @brief Correlation of Q15 sequences.
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+/**
+ @brief Correlation of Q15 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ @return none
+ */
+void arm_correlate_fast_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+/**
+ @brief Correlation of Q15 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence.
+ @param[in] srcALen length of the first input sequence.
+ @param[in] pSrcB points to the second input sequence.
+ @param[in] srcBLen length of the second input sequence.
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+void arm_correlate_fast_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+/**
+ @brief Correlation of Q31 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_fast_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_correlate_opt_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ const q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ const q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cos output.
+ */
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal);
+
+
+ /**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cosine output.
+ */
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * S points to an instance of the PID control data structure. in
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ *
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd
+ *
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return processed output sample.
+ */
+ __STATIC_FORCEINLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+/**
+ @brief Process function for the Q31 PID Control.
+ @param[in,out] S points to an instance of the Q31 PID Control structure
+ @param[in] in input sample to process
+ @return processed output sample.
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 64-bit accumulator.
+ The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ Thus, if the accumulator result overflows it wraps around rather than clip.
+ In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+__STATIC_FORCEINLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31U);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+
+/**
+ @brief Process function for the Q15 PID Control.
+ @param[in,out] S points to an instance of the Q15 PID Control structure
+ @param[in] in input sample to process
+ @return processed output sample.
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using a 64-bit internal accumulator.
+ Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+__STATIC_FORCEINLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+#if defined (ARM_MATH_DSP)
+ /* Implementation of PID controller */
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc);
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((q31_t)(acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64 * src,
+ arm_matrix_instance_f64 * dst);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents
+ * in the two-phase orthogonal stator axis Ialpha and Ibeta.
+ * When Ialpha is superposed with Ia as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
+ * can be calculated using only Ia and Ib.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where Ia and Ib are the instantaneous stator phases and
+ * pIalpha and pIbeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none
+ */
+ __STATIC_FORCEINLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+ }
+
+
+/**
+ @brief Clarke transform for Q31 version
+ @param[in] Ia input three-phase coordinate a
+ @param[in] Ib input three-phase coordinate b
+ @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ @return none
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the addition, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where pIa and pIb are the instantaneous stator phases and
+ * Ialpha and Ibeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate a
+ * @param[out] pIb points to output three-phase coordinate b
+ * @return none
+ */
+ __STATIC_FORCEINLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+ }
+
+
+/**
+ @brief Inverse Clarke transform for Q31 version
+ @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ @param[in] Ibeta input two-phase orthogonal vector axis beta
+ @param[out] pIa points to output three-phase coordinate a
+ @param[out] pIb points to output three-phase coordinate b
+ @return none
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where Ialpha and Ibeta are the stator vector components,
+ * pId and pIq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+ __STATIC_FORCEINLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+ }
+
+
+/**
+ @brief Park transform for Q31 version
+ @param[in] Ialpha input two-phase vector coordinate alpha
+ @param[in] Ibeta input two-phase vector coordinate beta
+ @param[out] pId points to output rotor reference frame d
+ @param[out] pIq points to output rotor reference frame q
+ @param[in] sinVal sine value of rotation angle theta
+ @param[in] cosVal cosine value of rotation angle theta
+ @return none
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where pIalpha and pIbeta are the stator vector components,
+ * Id and Iq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none
+ */
+ __STATIC_FORCEINLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+ }
+
+
+/**
+ @brief Inverse Park transform for Q31 version
+ @param[in] Id input coordinate of rotor reference frame d
+ @param[in] Iq input coordinate of rotor reference frame q
+ @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ @param[in] sinVal sine value of rotation angle theta
+ @param[in] cosVal cosine value of rotation angle theta
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the addition, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ *
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ *
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * S points to an instance of the Linear Interpolate function data structure.
+ * x is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+ __STATIC_FORCEINLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if (i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if ((uint32_t)i >= (S->nValues - 1))
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ __STATIC_FORCEINLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (q31_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1U);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ __STATIC_FORCEINLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (int32_t)0xFFF00000) >> 20);
+
+ if (index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if (index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (q15_t) (y >> 20);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+ __STATIC_FORCEINLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0)
+ {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+ if (index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (q7_t) (y >> 20);
+ }
+ }
+
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+ float32_t arm_sin_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q31_t arm_sin_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q15_t arm_sin_q15(
+ q15_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+ float32_t arm_cos_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q31_t arm_cos_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+/**
+ @brief Floating-point vector of log values.
+ @param[in] pSrc points to the input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+ void arm_vlog_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+/**
+ @brief Floating-point vector of exp values.
+ @param[in] pSrc points to the input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+ void arm_vexp_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ *
+ * x1 = x0 - f(x0)/f'(x0)
+ *
+ * where x1 is the current estimate,
+ * x0 is the previous estimate, and
+ * f'(x0) is the derivative of f() evaluated at x0.
+ * For the square root function, the algorithm reduces to:
+ *
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ *
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+/**
+ @brief Floating-point square root function.
+ @param[in] in input value
+ @param[out] pOut square root of input value
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : input value is positive
+ - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
+ */
+__STATIC_FORCEINLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+ {
+ if (in >= 0.0f)
+ {
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ *pOut = __sqrtf(in);
+ #else
+ *pOut = sqrtf(in);
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+ #else
+ *pOut = sqrtf(in);
+ #endif
+
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+ }
+
+
+/**
+ @brief Q31 square root function.
+ @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF
+ @param[out] pOut points to square root of input value
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : input value is positive
+ - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
+ */
+arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+
+/**
+ @brief Q15 square root function.
+ @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF
+ @param[out] pOut points to square root of input value
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : input value is positive
+ - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
+ */
+arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+ /**
+ * @brief Vector Floating-point square root function.
+ * @param[in] pIn input vector.
+ * @param[out] pOut vector of square roots of input elements.
+ * @param[in] len length of input vector.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+ void arm_vsqrt_f32(
+ float32_t * pIn,
+ float32_t * pOut,
+ uint16_t len);
+
+ void arm_vsqrt_q31(
+ q31_t * pIn,
+ q31_t * pOut,
+ uint16_t len);
+
+ void arm_vsqrt_q15(
+ q15_t * pIn,
+ q15_t * pOut,
+ uint16_t len);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+ __STATIC_FORCEINLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ __STATIC_FORCEINLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t rOffset;
+ int32_t* dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = dst_base + dst_length;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+ __STATIC_FORCEINLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ __STATIC_FORCEINLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset;
+ q15_t* dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = dst_base + dst_length;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+ __STATIC_FORCEINLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ __STATIC_FORCEINLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset;
+ q7_t* dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = dst_base + dst_length;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q15(
+ const q15_t * pSrcCmplx,
+ const q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q31(
+ const q31_t * pSrcCmplx,
+ const q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_f32(
+ const float32_t * pSrcCmplx,
+ const float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ @brief Maximum value of a floating-point vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult maximum value returned here
+ @return none
+ */
+ void arm_max_no_idx_f32(
+ const float32_t *pSrc,
+ uint32_t blockSize,
+ float32_t *pResult);
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q31(
+ const float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q15(
+ const float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q7(
+ const float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_float(
+ const q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q15(
+ const q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q7(
+ const q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_float(
+ const q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q31(
+ const q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q7(
+ const q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q7_to_float(
+ const q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q31(
+ const q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q15(
+ const q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Struct for specifying SVM Kernel
+ */
+typedef enum
+{
+ ARM_ML_KERNEL_LINEAR = 0,
+ /**< Linear kernel */
+ ARM_ML_KERNEL_POLYNOMIAL = 1,
+ /**< Polynomial kernel */
+ ARM_ML_KERNEL_RBF = 2,
+ /**< Radial Basis Function kernel */
+ ARM_ML_KERNEL_SIGMOID = 3
+ /**< Sigmoid kernel */
+} arm_ml_kernel_type;
+
+
+/**
+ * @brief Instance structure for linear SVM prediction function.
+ */
+typedef struct
+{
+ uint32_t nbOfSupportVectors; /**< Number of support vectors */
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ float32_t intercept; /**< Intercept */
+ const float32_t *dualCoefficients; /**< Dual coefficients */
+ const float32_t *supportVectors; /**< Support vectors */
+ const int32_t *classes; /**< The two SVM classes */
+} arm_svm_linear_instance_f32;
+
+
+/**
+ * @brief Instance structure for polynomial SVM prediction function.
+ */
+typedef struct
+{
+ uint32_t nbOfSupportVectors; /**< Number of support vectors */
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ float32_t intercept; /**< Intercept */
+ const float32_t *dualCoefficients; /**< Dual coefficients */
+ const float32_t *supportVectors; /**< Support vectors */
+ const int32_t *classes; /**< The two SVM classes */
+ int32_t degree; /**< Polynomial degree */
+ float32_t coef0; /**< Polynomial constant */
+ float32_t gamma; /**< Gamma factor */
+} arm_svm_polynomial_instance_f32;
+
+/**
+ * @brief Instance structure for rbf SVM prediction function.
+ */
+typedef struct
+{
+ uint32_t nbOfSupportVectors; /**< Number of support vectors */
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ float32_t intercept; /**< Intercept */
+ const float32_t *dualCoefficients; /**< Dual coefficients */
+ const float32_t *supportVectors; /**< Support vectors */
+ const int32_t *classes; /**< The two SVM classes */
+ float32_t gamma; /**< Gamma factor */
+} arm_svm_rbf_instance_f32;
+
+/**
+ * @brief Instance structure for sigmoid SVM prediction function.
+ */
+typedef struct
+{
+ uint32_t nbOfSupportVectors; /**< Number of support vectors */
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ float32_t intercept; /**< Intercept */
+ const float32_t *dualCoefficients; /**< Dual coefficients */
+ const float32_t *supportVectors; /**< Support vectors */
+ const int32_t *classes; /**< The two SVM classes */
+ float32_t coef0; /**< Independant constant */
+ float32_t gamma; /**< Gamma factor */
+} arm_svm_sigmoid_instance_f32;
+
+/**
+ * @brief SVM linear instance init function
+ * @param[in] S Parameters for SVM functions
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @return none.
+ *
+ */
+
+
+void arm_svm_linear_init_f32(arm_svm_linear_instance_f32 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float32_t intercept,
+ const float32_t *dualCoefficients,
+ const float32_t *supportVectors,
+ const int32_t *classes);
+
+/**
+ * @brief SVM linear prediction
+ * @param[in] S Pointer to an instance of the linear SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult Decision value
+ * @return none.
+ *
+ */
+
+void arm_svm_linear_predict_f32(const arm_svm_linear_instance_f32 *S,
+ const float32_t * in,
+ int32_t * pResult);
+
+
+/**
+ * @brief SVM polynomial instance init function
+ * @param[in] S points to an instance of the polynomial SVM structure.
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @param[in] degree Polynomial degree
+ * @param[in] coef0 coeff0 (scikit-learn terminology)
+ * @param[in] gamma gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+
+void arm_svm_polynomial_init_f32(arm_svm_polynomial_instance_f32 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float32_t intercept,
+ const float32_t *dualCoefficients,
+ const float32_t *supportVectors,
+ const int32_t *classes,
+ int32_t degree,
+ float32_t coef0,
+ float32_t gamma
+ );
+
+/**
+ * @brief SVM polynomial prediction
+ * @param[in] S Pointer to an instance of the polynomial SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult Decision value
+ * @return none.
+ *
+ */
+void arm_svm_polynomial_predict_f32(const arm_svm_polynomial_instance_f32 *S,
+ const float32_t * in,
+ int32_t * pResult);
+
+
+/**
+ * @brief SVM radial basis function instance init function
+ * @param[in] S points to an instance of the polynomial SVM structure.
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @param[in] gamma gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+void arm_svm_rbf_init_f32(arm_svm_rbf_instance_f32 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float32_t intercept,
+ const float32_t *dualCoefficients,
+ const float32_t *supportVectors,
+ const int32_t *classes,
+ float32_t gamma
+ );
+
+/**
+ * @brief SVM rbf prediction
+ * @param[in] S Pointer to an instance of the rbf SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult decision value
+ * @return none.
+ *
+ */
+void arm_svm_rbf_predict_f32(const arm_svm_rbf_instance_f32 *S,
+ const float32_t * in,
+ int32_t * pResult);
+
+/**
+ * @brief SVM sigmoid instance init function
+ * @param[in] S points to an instance of the rbf SVM structure.
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @param[in] coef0 coeff0 (scikit-learn terminology)
+ * @param[in] gamma gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+void arm_svm_sigmoid_init_f32(arm_svm_sigmoid_instance_f32 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float32_t intercept,
+ const float32_t *dualCoefficients,
+ const float32_t *supportVectors,
+ const int32_t *classes,
+ float32_t coef0,
+ float32_t gamma
+ );
+
+/**
+ * @brief SVM sigmoid prediction
+ * @param[in] S Pointer to an instance of the rbf SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult Decision value
+ * @return none.
+ *
+ */
+void arm_svm_sigmoid_predict_f32(const arm_svm_sigmoid_instance_f32 *S,
+ const float32_t * in,
+ int32_t * pResult);
+
+
+
+/**
+ * @brief Instance structure for Naive Gaussian Bayesian estimator.
+ */
+typedef struct
+{
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ uint32_t numberOfClasses; /**< Number of different classes */
+ const float32_t *theta; /**< Mean values for the Gaussians */
+ const float32_t *sigma; /**< Variances for the Gaussians */
+ const float32_t *classPriors; /**< Class prior probabilities */
+ float32_t epsilon; /**< Additive value to variances */
+} arm_gaussian_naive_bayes_instance_f32;
+
+/**
+ * @brief Naive Gaussian Bayesian Estimator
+ *
+ * @param[in] S points to a naive bayes instance structure
+ * @param[in] in points to the elements of the input vector.
+ * @param[in] pBuffer points to a buffer of length numberOfClasses
+ * @return The predicted class
+ *
+ */
+
+
+uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S,
+ const float32_t * in,
+ float32_t *pBuffer);
+
+/**
+ * @brief Computation of the LogSumExp
+ *
+ * In probabilistic computations, the dynamic of the probability values can be very
+ * wide because they come from gaussian functions.
+ * To avoid underflow and overflow issues, the values are represented by their log.
+ * In this representation, multiplying the original exp values is easy : their logs are added.
+ * But adding the original exp values is requiring some special handling and it is the
+ * goal of the LogSumExp function.
+ *
+ * If the values are x1...xn, the function is computing:
+ *
+ * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that
+ * rounding issues are minimised.
+ *
+ * The max xm of the values is extracted and the function is computing:
+ * xm + ln(exp(x1 - xm) + ... + exp(xn - xm))
+ *
+ * @param[in] *in Pointer to an array of input values.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return LogSumExp
+ *
+ */
+
+
+float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize);
+
+/**
+ * @brief Dot product with log arithmetic
+ *
+ * Vectors are containing the log of the samples
+ *
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[in] pTmpBuffer temporary buffer of length blockSize
+ * @return The log of the dot product .
+ *
+ */
+
+
+float32_t arm_logsumexp_dot_prod_f32(const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t *pTmpBuffer);
+
+/**
+ * @brief Entropy
+ *
+ * @param[in] pSrcA Array of input values.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Entropy -Sum(p ln p)
+ *
+ */
+
+
+float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize);
+
+
+/**
+ * @brief Entropy
+ *
+ * @param[in] pSrcA Array of input values.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Entropy -Sum(p ln p)
+ *
+ */
+
+
+float64_t arm_entropy_f64(const float64_t * pSrcA, uint32_t blockSize);
+
+
+/**
+ * @brief Kullback-Leibler
+ *
+ * @param[in] pSrcA Pointer to an array of input values for probability distribution A.
+ * @param[in] pSrcB Pointer to an array of input values for probability distribution B.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Kullback-Leibler Divergence D(A || B)
+ *
+ */
+float32_t arm_kullback_leibler_f32(const float32_t * pSrcA
+ ,const float32_t * pSrcB
+ ,uint32_t blockSize);
+
+
+/**
+ * @brief Kullback-Leibler
+ *
+ * @param[in] pSrcA Pointer to an array of input values for probability distribution A.
+ * @param[in] pSrcB Pointer to an array of input values for probability distribution B.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Kullback-Leibler Divergence D(A || B)
+ *
+ */
+float64_t arm_kullback_leibler_f64(const float64_t * pSrcA,
+ const float64_t * pSrcB,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Weighted sum
+ *
+ *
+ * @param[in] *in Array of input values.
+ * @param[in] *weigths Weights
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Weighted sum
+ *
+ */
+float32_t arm_weighted_sum_f32(const float32_t *in
+ , const float32_t *weigths
+ , uint32_t blockSize);
+
+
+/**
+ * @brief Barycenter
+ *
+ *
+ * @param[in] in List of vectors
+ * @param[in] weights Weights of the vectors
+ * @param[out] out Barycenter
+ * @param[in] nbVectors Number of vectors
+ * @param[in] vecDim Dimension of space (vector dimension)
+ * @return None
+ *
+ */
+void arm_barycenter_f32(const float32_t *in
+ , const float32_t *weights
+ , float32_t *out
+ , uint32_t nbVectors
+ , uint32_t vecDim);
+
+/**
+ * @brief Euclidean distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Bray-Curtis distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Canberra distance between two vectors
+ *
+ * This function may divide by zero when samples pA[i] and pB[i] are both zero.
+ * The result of the computation will be correct. So the division per zero may be
+ * ignored.
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+
+/**
+ * @brief Chebyshev distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+
+/**
+ * @brief Cityblock (Manhattan) distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Correlation distance between two vectors
+ *
+ * The input vectors are modified in place !
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t arm_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Cosine distance between two vectors
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+float32_t arm_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Jensen-Shannon distance between two vectors
+ *
+ * This function is assuming that elements of second vector are > 0
+ * and 0 only when the corresponding element of first vector is 0.
+ * Otherwise the result of the computation does not make sense
+ * and for speed reasons, the cases returning NaN or Infinity are not
+ * managed.
+ *
+ * When the function is computing x log (x / y) with x 0 and y 0,
+ * it will compute the right value (0) but a division per zero will occur
+ * and shoudl be ignored in client code.
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB,uint32_t blockSize);
+
+/**
+ * @brief Minkowski distance between two vectors
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] n Norm order (>= 2)
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+
+
+float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize);
+
+/**
+ * @brief Dice distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] order Distance order
+ * @param[in] blockSize Number of samples
+ * @return distance
+ *
+ */
+
+
+float32_t arm_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Hamming distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_hamming_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Jaccard distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_jaccard_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Kulsinski distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Roger Stanimoto distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Russell-Rao distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Sokal-Michener distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Sokal-Sneath distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Yule distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function f(x, y) is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * Algorithm
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ *
+ *
+ * \par
+ * where numRows specifies the number of rows in the table;
+ * numCols specifies the number of columns in the table;
+ * and pData points to an array of size numRows*numCols values.
+ * The data table pTable is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.
+ *
+ * \par
+ * Let (x, y) specify the desired interpolation point. Then define:
+ *
+ * XF = floor(x)
+ * YF = floor(y)
+ *
+ * \par
+ * The interpolated output point is computed as:
+ *
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ *
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+ __STATIC_FORCEINLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+ {
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (xIndex < 0 || xIndex > (S->numCols - 2) || yIndex < 0 || yIndex > (S->numRows - 2))
+ {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex ) + (yIndex ) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex ) + (yIndex+1) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ __STATIC_FORCEINLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11U;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
+ x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11U;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
+ y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return ((q31_t)(acc << 2));
+ }
+
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ __STATIC_FORCEINLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0x0FFFFF - xfract)) >> 4U);
+ acc = ((q63_t) out * (0x0FFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0x0FFFFF - yfract)) >> 4U);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0x0FFFFF - xfract)) >> 4U);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return ((q15_t)(acc >> 36));
+ }
+
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ __STATIC_FORCEINLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return ((q7_t)(acc >> 40));
+ }
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( __ARM_ARCH_7EM__ )
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("push") \
+ _Pragma ("O1")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #if defined ( __ARM_ARCH_7EM__ )
+ #define LOW_OPTIMIZATION_EXIT \
+ _Pragma ("pop")
+ #else
+ #define LOW_OPTIMIZATION_EXIT
+ #endif
+
+ /* Enter low optimization region - place directly above function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __GNUC__ )
+ #define LOW_OPTIMIZATION_ENTER \
+ __attribute__(( optimize("-O1") ))
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __ICCARM__ )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined ( __ARM_ARCH_7EM__ )
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define LOW_OPTIMIZATION_EXIT
+
+ /* Enter low optimization region - place directly above function definition */
+ #if defined ( __ARM_ARCH_7EM__ )
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TI_ARM__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __CSMC__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TASKING__ )
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( _MSC_VER ) || defined(__GNUC_PYTHON__)
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+#endif
+
+
+
+/* Compiler specific diagnostic adjustment */
+#if defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#elif defined ( _MSC_VER )
+
+#else
+ #error Unknown compiler
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/arm_mve_tables.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/arm_mve_tables.h
new file mode 100644
index 0000000000..4d2c135ac6
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/arm_mve_tables.h
@@ -0,0 +1,235 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_mve_tables.h
+ * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc
+ * used for MVE implementation only
+ *
+ * $Date: 08. January 2020
+ * $Revision: V1.7.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2020 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ #ifndef _ARM_MVE_TABLES_H
+ #define _ARM_MVE_TABLES_H
+
+ #include "arm_math.h"
+
+
+
+
+
+
+#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2];
+extern float32_t rearranged_twiddle_stride1_16_f32[8];
+extern float32_t rearranged_twiddle_stride2_16_f32[8];
+extern float32_t rearranged_twiddle_stride3_16_f32[8];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3];
+extern float32_t rearranged_twiddle_stride1_64_f32[40];
+extern float32_t rearranged_twiddle_stride2_64_f32[40];
+extern float32_t rearranged_twiddle_stride3_64_f32[40];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4];
+extern float32_t rearranged_twiddle_stride1_256_f32[168];
+extern float32_t rearranged_twiddle_stride2_256_f32[168];
+extern float32_t rearranged_twiddle_stride3_256_f32[168];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f32[5];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f32[5];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f32[5];
+extern float32_t rearranged_twiddle_stride1_1024_f32[680];
+extern float32_t rearranged_twiddle_stride2_1024_f32[680];
+extern float32_t rearranged_twiddle_stride3_1024_f32[680];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) || defined(ARM_TABLE_TWIDDLECOEF_F32_8192)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f32[6];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f32[6];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f32[6];
+extern float32_t rearranged_twiddle_stride1_4096_f32[2728];
+extern float32_t rearranged_twiddle_stride2_4096_f32[2728];
+extern float32_t rearranged_twiddle_stride3_4096_f32[2728];
+#endif
+
+
+#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
+
+#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */
+
+
+
+#if defined(ARM_MATH_MVEI)
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q31[2];
+extern q31_t rearranged_twiddle_stride1_16_q31[8];
+extern q31_t rearranged_twiddle_stride2_16_q31[8];
+extern q31_t rearranged_twiddle_stride3_16_q31[8];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3];
+extern q31_t rearranged_twiddle_stride1_64_q31[40];
+extern q31_t rearranged_twiddle_stride2_64_q31[40];
+extern q31_t rearranged_twiddle_stride3_64_q31[40];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4];
+extern q31_t rearranged_twiddle_stride1_256_q31[168];
+extern q31_t rearranged_twiddle_stride2_256_q31[168];
+extern q31_t rearranged_twiddle_stride3_256_q31[168];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5];
+extern q31_t rearranged_twiddle_stride1_1024_q31[680];
+extern q31_t rearranged_twiddle_stride2_1024_q31[680];
+extern q31_t rearranged_twiddle_stride3_1024_q31[680];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q31_8192)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6];
+extern q31_t rearranged_twiddle_stride1_4096_q31[2728];
+extern q31_t rearranged_twiddle_stride2_4096_q31[2728];
+extern q31_t rearranged_twiddle_stride3_4096_q31[2728];
+#endif
+
+
+#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
+
+#endif /* defined(ARM_MATH_MVEI) */
+
+
+
+#if defined(ARM_MATH_MVEI)
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q15[2];
+extern q15_t rearranged_twiddle_stride1_16_q15[8];
+extern q15_t rearranged_twiddle_stride2_16_q15[8];
+extern q15_t rearranged_twiddle_stride3_16_q15[8];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3];
+extern q15_t rearranged_twiddle_stride1_64_q15[40];
+extern q15_t rearranged_twiddle_stride2_64_q15[40];
+extern q15_t rearranged_twiddle_stride3_64_q15[40];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4];
+extern q15_t rearranged_twiddle_stride1_256_q15[168];
+extern q15_t rearranged_twiddle_stride2_256_q15[168];
+extern q15_t rearranged_twiddle_stride3_256_q15[168];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5];
+extern q15_t rearranged_twiddle_stride1_1024_q15[680];
+extern q15_t rearranged_twiddle_stride2_1024_q15[680];
+extern q15_t rearranged_twiddle_stride3_1024_q15[680];
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q15_8192)
+
+extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6];
+extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6];
+extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6];
+extern q15_t rearranged_twiddle_stride1_4096_q15[2728];
+extern q15_t rearranged_twiddle_stride2_4096_q15[2728];
+extern q15_t rearranged_twiddle_stride3_4096_q15[2728];
+#endif
+
+
+#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
+
+#endif /* defined(ARM_MATH_MVEI) */
+
+
+
+#if defined(ARM_MATH_MVEI)
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
+
+
+#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
+
+#endif /* defined(ARM_MATH_MVEI) */
+
+
+
+#endif /*_ARM_MVE_TABLES_H*/
+
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/arm_vec_math.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/arm_vec_math.h
new file mode 100644
index 0000000000..0ce9464bcb
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/arm_vec_math.h
@@ -0,0 +1,372 @@
+/******************************************************************************
+ * @file arm_vec_math.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.7.0
+ * @date 15. October 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_VEC_MATH_H
+#define _ARM_VEC_MATH_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+#include "arm_helium_utils.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
+
+#define INV_NEWTON_INIT_F32 0x7EF127EA
+
+static const float32_t __logf_rng_f32=0.693147180f;
+
+
+/* fast inverse approximation (3x newton) */
+__STATIC_INLINE f32x4_t vrecip_medprec_f32(
+ f32x4_t x)
+{
+ q31x4_t m;
+ f32x4_t b;
+ any32x4_t xinv;
+ f32x4_t ax = vabsq(x);
+
+ xinv.f = ax;
+ m = 0x3F800000 - (xinv.i & 0x7F800000);
+ xinv.i = xinv.i + m;
+ xinv.f = 1.41176471f - 0.47058824f * xinv.f;
+ xinv.i = xinv.i + m;
+
+ b = 2.0f - xinv.f * ax;
+ xinv.f = xinv.f * b;
+
+ b = 2.0f - xinv.f * ax;
+ xinv.f = xinv.f * b;
+
+ b = 2.0f - xinv.f * ax;
+ xinv.f = xinv.f * b;
+
+ xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f));
+ /*
+ * restore sign
+ */
+ xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f));
+
+ return xinv.f;
+}
+
+/* fast inverse approximation (4x newton) */
+__STATIC_INLINE f32x4_t vrecip_hiprec_f32(
+ f32x4_t x)
+{
+ q31x4_t m;
+ f32x4_t b;
+ any32x4_t xinv;
+ f32x4_t ax = vabsq(x);
+
+ xinv.f = ax;
+
+ m = 0x3F800000 - (xinv.i & 0x7F800000);
+ xinv.i = xinv.i + m;
+ xinv.f = 1.41176471f - 0.47058824f * xinv.f;
+ xinv.i = xinv.i + m;
+
+ b = 2.0f - xinv.f * ax;
+ xinv.f = xinv.f * b;
+
+ b = 2.0f - xinv.f * ax;
+ xinv.f = xinv.f * b;
+
+ b = 2.0f - xinv.f * ax;
+ xinv.f = xinv.f * b;
+
+ b = 2.0f - xinv.f * ax;
+ xinv.f = xinv.f * b;
+
+ xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f));
+ /*
+ * restore sign
+ */
+ xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f));
+
+ return xinv.f;
+}
+
+__STATIC_INLINE f32x4_t vdiv_f32(
+ f32x4_t num, f32x4_t den)
+{
+ return vmulq(num, vrecip_hiprec_f32(den));
+}
+
+/**
+ @brief Single-precision taylor dev.
+ @param[in] x f32 quad vector input
+ @param[in] coeffs f32 quad vector coeffs
+ @return destination f32 quad vector
+ */
+
+__STATIC_INLINE f32x4_t vtaylor_polyq_f32(
+ f32x4_t x,
+ const float32_t * coeffs)
+{
+ f32x4_t A = vfmasq(vdupq_n_f32(coeffs[4]), x, coeffs[0]);
+ f32x4_t B = vfmasq(vdupq_n_f32(coeffs[6]), x, coeffs[2]);
+ f32x4_t C = vfmasq(vdupq_n_f32(coeffs[5]), x, coeffs[1]);
+ f32x4_t D = vfmasq(vdupq_n_f32(coeffs[7]), x, coeffs[3]);
+ f32x4_t x2 = vmulq(x, x);
+ f32x4_t x4 = vmulq(x2, x2);
+ f32x4_t res = vfmaq(vfmaq_f32(A, B, x2), vfmaq_f32(C, D, x2), x4);
+
+ return res;
+}
+
+__STATIC_INLINE f32x4_t vmant_exp_f32(
+ f32x4_t x,
+ int32x4_t * e)
+{
+ any32x4_t r;
+ int32x4_t n;
+
+ r.f = x;
+ n = r.i >> 23;
+ n = n - 127;
+ r.i = r.i - (n << 23);
+
+ *e = n;
+ return r.f;
+}
+
+
+__STATIC_INLINE f32x4_t vlogq_f32(f32x4_t vecIn)
+{
+ q31x4_t vecExpUnBiased;
+ f32x4_t vecTmpFlt0, vecTmpFlt1;
+ f32x4_t vecAcc0, vecAcc1, vecAcc2, vecAcc3;
+ f32x4_t vecExpUnBiasedFlt;
+
+ /*
+ * extract exponent
+ */
+ vecTmpFlt1 = vmant_exp_f32(vecIn, &vecExpUnBiased);
+
+ vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1;
+ /*
+ * a = (__logf_lut_f32[4] * r.f) + (__logf_lut_f32[0]);
+ */
+ vecAcc0 = vdupq_n_f32(__logf_lut_f32[0]);
+ vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f32[4]);
+ /*
+ * b = (__logf_lut_f32[6] * r.f) + (__logf_lut_f32[2]);
+ */
+ vecAcc1 = vdupq_n_f32(__logf_lut_f32[2]);
+ vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f32[6]);
+ /*
+ * c = (__logf_lut_f32[5] * r.f) + (__logf_lut_f32[1]);
+ */
+ vecAcc2 = vdupq_n_f32(__logf_lut_f32[1]);
+ vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f32[5]);
+ /*
+ * d = (__logf_lut_f32[7] * r.f) + (__logf_lut_f32[3]);
+ */
+ vecAcc3 = vdupq_n_f32(__logf_lut_f32[3]);
+ vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f32[7]);
+ /*
+ * a = a + b * xx;
+ */
+ vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0);
+ /*
+ * c = c + d * xx;
+ */
+ vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0);
+ /*
+ * xx = xx * xx;
+ */
+ vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0;
+ vecExpUnBiasedFlt = vcvtq_f32_s32(vecExpUnBiased);
+ /*
+ * r.f = a + c * xx;
+ */
+ vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0);
+ /*
+ * add exponent
+ * r.f = r.f + ((float32_t) m) * __logf_rng_f32;
+ */
+ vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f32);
+ // set log0 down to -inf
+ vecAcc0 = vdupq_m(vecAcc0, -INFINITY, vcmpeqq(vecIn, 0.0f));
+ return vecAcc0;
+}
+
+__STATIC_INLINE f32x4_t vexpq_f32(
+ f32x4_t x)
+{
+ // Perform range reduction [-log(2),log(2)]
+ int32x4_t m = vcvtq_s32_f32(vmulq_n_f32(x, 1.4426950408f));
+ f32x4_t val = vfmsq_f32(x, vcvtq_f32_s32(m), vdupq_n_f32(0.6931471805f));
+
+ // Polynomial Approximation
+ f32x4_t poly = vtaylor_polyq_f32(val, exp_tab);
+
+ // Reconstruct
+ poly = (f32x4_t) (vqaddq_s32((q31x4_t) (poly), vqshlq_n_s32(m, 23)));
+
+ poly = vdupq_m(poly, 0.0f, vcmpltq_n_s32(m, -126));
+ return poly;
+}
+
+__STATIC_INLINE f32x4_t arm_vec_exponent_f32(f32x4_t x, int32_t nb)
+{
+ f32x4_t r = x;
+ nb--;
+ while (nb > 0) {
+ r = vmulq(r, x);
+ nb--;
+ }
+ return (r);
+}
+
+__STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn)
+{
+ f32x4_t vecSx, vecW, vecTmp;
+ any32x4_t v;
+
+ vecSx = vabsq(vecIn);
+
+ v.f = vecIn;
+ v.i = vsubq(vdupq_n_s32(INV_NEWTON_INIT_F32), v.i);
+
+ vecW = vmulq(vecSx, v.f);
+
+ // v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w)))))));
+ vecTmp = vsubq(vdupq_n_f32(8.0f), vecW);
+ vecTmp = vfmasq(vecW, vecTmp, -28.0f);
+ vecTmp = vfmasq(vecW, vecTmp, 56.0f);
+ vecTmp = vfmasq(vecW, vecTmp, -70.0f);
+ vecTmp = vfmasq(vecW, vecTmp, 56.0f);
+ vecTmp = vfmasq(vecW, vecTmp, -28.0f);
+ vecTmp = vfmasq(vecW, vecTmp, 8.0f);
+ v.f = vmulq(v.f, vecTmp);
+
+ v.f = vdupq_m(v.f, INFINITY, vcmpeqq(vecIn, 0.0f));
+ /*
+ * restore sign
+ */
+ v.f = vnegq_m(v.f, v.f, vcmpltq(vecIn, 0.0f));
+ return v.f;
+}
+
+__STATIC_INLINE f32x4_t vtanhq_f32(
+ f32x4_t val)
+{
+ f32x4_t x =
+ vminnmq_f32(vmaxnmq_f32(val, vdupq_n_f32(-10.f)), vdupq_n_f32(10.0f));
+ f32x4_t exp2x = vexpq_f32(vmulq_n_f32(x, 2.f));
+ f32x4_t num = vsubq_n_f32(exp2x, 1.f);
+ f32x4_t den = vaddq_n_f32(exp2x, 1.f);
+ f32x4_t tanh = vmulq_f32(num, vrecip_f32(den));
+ return tanh;
+}
+
+__STATIC_INLINE f32x4_t vpowq_f32(
+ f32x4_t val,
+ f32x4_t n)
+{
+ return vexpq_f32(vmulq_f32(n, vlogq_f32(val)));
+}
+
+#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/
+
+#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM))
+#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */
+
+#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE)
+
+#include "NEMath.h"
+/**
+ * @brief Vectorized integer exponentiation
+ * @param[in] x value
+ * @param[in] nb integer exponent >= 1
+ * @return x^nb
+ *
+ */
+__STATIC_INLINE float32x4_t arm_vec_exponent_f32(float32x4_t x, int32_t nb)
+{
+ float32x4_t r = x;
+ nb --;
+ while(nb > 0)
+ {
+ r = vmulq_f32(r , x);
+ nb--;
+ }
+ return(r);
+}
+
+
+__STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x)
+{
+ float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN));
+ float32x4_t e = vrsqrteq_f32(x1);
+ e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e);
+ e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e);
+ return vmulq_f32(x, e);
+}
+
+__STATIC_INLINE int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec)
+{
+ float32x4_t tempF;
+ int32x4_t tempHI,tempLO;
+
+ tempLO = vmovl_s16(vget_low_s16(vec));
+ tempF = vcvtq_n_f32_s32(tempLO,15);
+ tempF = __arm_vec_sqrt_f32_neon(tempF);
+ tempLO = vcvtq_n_s32_f32(tempF,15);
+
+ tempHI = vmovl_s16(vget_high_s16(vec));
+ tempF = vcvtq_n_f32_s32(tempHI,15);
+ tempF = __arm_vec_sqrt_f32_neon(tempF);
+ tempHI = vcvtq_n_s32_f32(tempF,15);
+
+ return(vcombine_s16(vqmovn_s32(tempLO),vqmovn_s32(tempHI)));
+}
+
+__STATIC_INLINE int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec)
+{
+ float32x4_t temp;
+
+ temp = vcvtq_n_f32_s32(vec,31);
+ temp = __arm_vec_sqrt_f32_neon(temp);
+ return(vcvtq_n_s32_f32(temp,31));
+}
+
+#endif /* (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _ARM_VEC_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cachel1_armv7.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cachel1_armv7.h
new file mode 100644
index 0000000000..d2c3e2291f
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cachel1_armv7.h
@@ -0,0 +1,411 @@
+/******************************************************************************
+ * @file cachel1_armv7.h
+ * @brief CMSIS Level 1 Cache API for Armv7-M and later
+ * @version V1.0.0
+ * @date 03. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_CACHEL1_ARMV7_H
+#define ARM_CACHEL1_ARMV7_H
+
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions
+ \brief Functions that configure Instruction and Data cache.
+ @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
+
+#ifndef __SCB_DCACHE_LINE_SIZE
+#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+#endif
+
+#ifndef __SCB_ICACHE_LINE_SIZE
+#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+#endif
+
+/**
+ \brief Enable I-Cache
+ \details Turns on I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_EnableICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
+
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable I-Cache
+ \details Turns off I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_DisableICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate I-Cache
+ \details Invalidates I-Cache
+ */
+__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL;
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief I-Cache Invalidate by address
+ \details Invalidates I-Cache for the given address.
+ I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ I-Cache memory blocks which are part of given address + given size are invalidated.
+ \param[in] addr address
+ \param[in] isize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
+{
+ #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ if ( isize > 0 ) {
+ int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_ICACHE_LINE_SIZE;
+ op_size -= __SCB_ICACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief Enable D-Cache
+ \details Turns on D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_EnableDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+ __DSB();
+
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable D-Cache
+ \details Turns off D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_DisableDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate D-Cache
+ \details Invalidates D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean D-Cache
+ \details Cleans D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_CleanDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean & Invalidate D-Cache
+ \details Cleans and Invalidates D-Cache
+ */
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = 0U; /* select Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways-- != 0U);
+ } while(sets-- != 0U);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Invalidate by address
+ \details Invalidates D-Cache for the given address.
+ D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are invalidated.
+ \param[in] addr address
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean by address
+ \details Cleans D-Cache for the given address
+ D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are cleaned.
+ \param[in] addr address
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean and Invalidate by address
+ \details Cleans and invalidates D_Cache for the given address
+ D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
+ D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if ( dsize > 0 ) {
+ int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+
+ __DSB();
+
+ do {
+ SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ op_addr += __SCB_DCACHE_LINE_SIZE;
+ op_size -= __SCB_DCACHE_LINE_SIZE;
+ } while ( op_size > 0 );
+
+ __DSB();
+ __ISB();
+ }
+ #endif
+}
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+#endif /* ARM_CACHEL1_ARMV7_H */
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_armcc.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_armcc.h
new file mode 100644
index 0000000000..237ff6ec3e
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_armcc.h
@@ -0,0 +1,885 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version V5.2.1
+ * @date 26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
+ #define __ARM_ARCH_6M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
+ #define __ARM_ARCH_7M__ 1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+ #define __ARM_ARCH_7EM__ 1
+#endif
+
+ /* __ARM_ARCH_8M_BASE__ not applicable */
+ /* __ARM_ARCH_8M_MAIN__ not applicable */
+ /* __ARM_ARCH_8_1M_MAIN__ not applicable */
+
+/* CMSIS compiler control DSP macros */
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __ARM_FEATURE_DSP 1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE static __forceinline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __declspec(noreturn)
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT __packed struct
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION __packed union
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __memory_changed()
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return result;
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_armclang.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_armclang.h
new file mode 100644
index 0000000000..90de9dbf8f
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_armclang.h
@@ -0,0 +1,1467 @@
+/**************************************************************************//**
+ * @file cmsis_armclang.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V5.3.1
+ * @date 26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF)
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
+
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
+ (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+#define __SADD8 __builtin_arm_sadd8
+#define __QADD8 __builtin_arm_qadd8
+#define __SHADD8 __builtin_arm_shadd8
+#define __UADD8 __builtin_arm_uadd8
+#define __UQADD8 __builtin_arm_uqadd8
+#define __UHADD8 __builtin_arm_uhadd8
+#define __SSUB8 __builtin_arm_ssub8
+#define __QSUB8 __builtin_arm_qsub8
+#define __SHSUB8 __builtin_arm_shsub8
+#define __USUB8 __builtin_arm_usub8
+#define __UQSUB8 __builtin_arm_uqsub8
+#define __UHSUB8 __builtin_arm_uhsub8
+#define __SADD16 __builtin_arm_sadd16
+#define __QADD16 __builtin_arm_qadd16
+#define __SHADD16 __builtin_arm_shadd16
+#define __UADD16 __builtin_arm_uadd16
+#define __UQADD16 __builtin_arm_uqadd16
+#define __UHADD16 __builtin_arm_uhadd16
+#define __SSUB16 __builtin_arm_ssub16
+#define __QSUB16 __builtin_arm_qsub16
+#define __SHSUB16 __builtin_arm_shsub16
+#define __USUB16 __builtin_arm_usub16
+#define __UQSUB16 __builtin_arm_uqsub16
+#define __UHSUB16 __builtin_arm_uhsub16
+#define __SASX __builtin_arm_sasx
+#define __QASX __builtin_arm_qasx
+#define __SHASX __builtin_arm_shasx
+#define __UASX __builtin_arm_uasx
+#define __UQASX __builtin_arm_uqasx
+#define __UHASX __builtin_arm_uhasx
+#define __SSAX __builtin_arm_ssax
+#define __QSAX __builtin_arm_qsax
+#define __SHSAX __builtin_arm_shsax
+#define __USAX __builtin_arm_usax
+#define __UQSAX __builtin_arm_uqsax
+#define __UHSAX __builtin_arm_uhsax
+#define __USAD8 __builtin_arm_usad8
+#define __USADA8 __builtin_arm_usada8
+#define __SSAT16 __builtin_arm_ssat16
+#define __USAT16 __builtin_arm_usat16
+#define __UXTB16 __builtin_arm_uxtb16
+#define __UXTAB16 __builtin_arm_uxtab16
+#define __SXTB16 __builtin_arm_sxtb16
+#define __SXTAB16 __builtin_arm_sxtab16
+#define __SMUAD __builtin_arm_smuad
+#define __SMUADX __builtin_arm_smuadx
+#define __SMLAD __builtin_arm_smlad
+#define __SMLADX __builtin_arm_smladx
+#define __SMLALD __builtin_arm_smlald
+#define __SMLALDX __builtin_arm_smlaldx
+#define __SMUSD __builtin_arm_smusd
+#define __SMUSDX __builtin_arm_smusdx
+#define __SMLSD __builtin_arm_smlsd
+#define __SMLSDX __builtin_arm_smlsdx
+#define __SMLSLD __builtin_arm_smlsld
+#define __SMLSLDX __builtin_arm_smlsldx
+#define __SEL __builtin_arm_sel
+#define __QADD __builtin_arm_qadd
+#define __QSUB __builtin_arm_qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_armclang_ltm.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_armclang_ltm.h
new file mode 100644
index 0000000000..0e5c7349d3
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_armclang_ltm.h
@@ -0,0 +1,1893 @@
+/**************************************************************************//**
+ * @file cmsis_armclang_ltm.h
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version V1.3.0
+ * @date 26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE __inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static __inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma clang diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq(); see arm_compat.h */
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR() ((uint32_t)0U)
+#endif
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#define __set_FPSCR __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x) ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF)
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF)
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV(value) __builtin_bswap32(value)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __builtin_arm_rbit
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __builtin_arm_ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_compiler.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_compiler.h
new file mode 100644
index 0000000000..adbf296f15
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_compiler.h
@@ -0,0 +1,283 @@
+/**************************************************************************//**
+ * @file cmsis_compiler.h
+ * @brief CMSIS compiler generic header file
+ * @version V5.1.0
+ * @date 09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include
+
+/*
+ * Arm Compiler 4/5
+ */
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+ #include "cmsis_armclang_ltm.h"
+
+ /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+ #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+ #include
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __attribute__((packed))
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed))
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed))
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #endif
+ #ifndef __RESTRICT
+ #define __RESTRICT __restrict
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+ #ifndef __ASM
+ #define __ASM __asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((noreturn))
+ #endif
+ #ifndef __USED
+ #define __USED __attribute__((used))
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+ #endif
+ #ifndef __PACKED
+ #define __PACKED __packed__
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __packed__
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION union __packed__
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ struct __packed__ T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #define __ALIGNED(x) __align(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+ #include
+
+ #ifndef __ASM
+ #define __ASM _asm
+ #endif
+ #ifndef __INLINE
+ #define __INLINE inline
+ #endif
+ #ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+ #endif
+ #ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __STATIC_INLINE
+ #endif
+ #ifndef __NO_RETURN
+ // NO RETURN is automatically detected hence no warning here
+ #define __NO_RETURN
+ #endif
+ #ifndef __USED
+ #warning No compiler specific solution for __USED. __USED is ignored.
+ #define __USED
+ #endif
+ #ifndef __WEAK
+ #define __WEAK __weak
+ #endif
+ #ifndef __PACKED
+ #define __PACKED @packed
+ #endif
+ #ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT @packed struct
+ #endif
+ #ifndef __PACKED_UNION
+ #define __PACKED_UNION @packed union
+ #endif
+ #ifndef __UNALIGNED_UINT32 /* deprecated */
+ @packed struct T_UINT32 { uint32_t v; };
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT16_WRITE
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT16_READ
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __UNALIGNED_UINT32_WRITE
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+ #endif
+ #ifndef __UNALIGNED_UINT32_READ
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+ #endif
+ #ifndef __ALIGNED
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+ #ifndef __RESTRICT
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+ #define __RESTRICT
+ #endif
+ #ifndef __COMPILER_BARRIER
+ #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+ #define __COMPILER_BARRIER() (void)0
+ #endif
+
+
+#else
+ #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_gcc.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_gcc.h
new file mode 100644
index 0000000000..a2778f58e8
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_gcc.h
@@ -0,0 +1,2177 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS compiler GCC header file
+ * @version V5.3.0
+ * @date 26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+ #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
+#endif
+#ifndef __NO_RETURN
+ #define __NO_RETURN __attribute__((__noreturn__))
+#endif
+#ifndef __USED
+ #define __USED __attribute__((used))
+#endif
+#ifndef __WEAK
+ #define __WEAK __attribute__((weak))
+#endif
+#ifndef __PACKED
+ #define __PACKED __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_STRUCT
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef __PACKED_UNION
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+#endif
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef __UNALIGNED_UINT16_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT16_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __UNALIGNED_UINT32_WRITE
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef __UNALIGNED_UINT32_READ
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpacked"
+ #pragma GCC diagnostic ignored "-Wattributes"
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+ #pragma GCC diagnostic pop
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef __ALIGNED
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+#endif
+#ifndef __RESTRICT
+ #define __RESTRICT __restrict
+#endif
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+/* ######################### Startup and Lowlevel Init ######################## */
+
+#ifndef __PROGRAM_START
+
+/**
+ \brief Initializes data and bss sections
+ \details This default implementations initialized all data and additional bss
+ sections relying on .copy.table and .zero.table specified properly
+ in the used linker script.
+
+ */
+__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+{
+ extern void _start(void) __NO_RETURN;
+
+ typedef struct {
+ uint32_t const* src;
+ uint32_t* dest;
+ uint32_t wlen;
+ } __copy_table_t;
+
+ typedef struct {
+ uint32_t* dest;
+ uint32_t wlen;
+ } __zero_table_t;
+
+ extern const __copy_table_t __copy_table_start__;
+ extern const __copy_table_t __copy_table_end__;
+ extern const __zero_table_t __zero_table_start__;
+ extern const __zero_table_t __zero_table_end__;
+
+ for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
+ for(uint32_t i=0u; iwlen; ++i) {
+ pTable->dest[i] = pTable->src[i];
+ }
+ }
+
+ for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
+ for(uint32_t i=0u; iwlen; ++i) {
+ pTable->dest[i] = 0u;
+ }
+ }
+
+ _start();
+}
+
+#define __PROGRAM_START __cmsis_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP __StackTop
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT __StackLimit
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors")))
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+ \return SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+ \param [in] topOfStack Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+/**
+ \brief Get Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)ProcStackPtrLimit;
+#else
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always in non-secure
+ mode.
+
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+ return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence zero is returned always.
+
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ return 0U;
+#else
+ uint32_t result;
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return result;
+#endif
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored in non-secure
+ mode.
+
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+ Stack Pointer Limit register hence the write is silently ignored.
+
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)MainStackPtrLimit;
+#else
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_get_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ return __builtin_arm_get_fpscr();
+#else
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#endif
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+ __builtin_arm_set_fpscr(fpscr);
+#else
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+ (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP() __ASM volatile ("nop")
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI() __ASM volatile ("wfi":::"memory")
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE() __ASM volatile ("wfe":::"memory")
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV() __ASM volatile ("sev")
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (int16_t)__builtin_bswap16(value);
+#else
+ int16_t result;
+
+ __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return result;
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+ __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value != 0U; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return result;
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+ /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+ __builtin_clz(0) is undefined behaviour, so handle this case specially.
+ This guarantees ARM-compatible results if happening to compile on a non-ARM
+ target, and ensures the compiler doesn't decide to activate any
+ optimisations using the logic "value was passed to __builtin_clz, so it
+ is non-zero".
+ ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+ single CLZ instruction.
+ */
+ if (value == 0U)
+ {
+ return 32U;
+ }
+ return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1, ARG2) \
+__extension__ \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] ARG1 Value to be saturated
+ \param [in] ARG2 Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1, ARG2) \
+ __extension__ \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+}
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+ return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1, ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1, ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
+ __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
+{
+ uint32_t result;
+
+ __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );
+
+ return result;
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_iccarm.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_iccarm.h
new file mode 100644
index 0000000000..7eeffca5c7
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_iccarm.h
@@ -0,0 +1,968 @@
+/**************************************************************************//**
+ * @file cmsis_iccarm.h
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version V5.2.0
+ * @date 28. January 2020
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2019 IAR Systems
+// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+ #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+ #define __ICCARM_V8 1
+#else
+ #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+ #if __ICCARM_V8
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #elif (__VER__ >= 7080000)
+ /* Needs IAR language extensions */
+ #define __ALIGNED(x) __attribute__((aligned(x)))
+ #else
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+ #define __ALIGNED(x)
+ #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+ #if __ARM_ARCH == 6
+ #define __ARM_ARCH_6M__ 1
+ #elif __ARM_ARCH == 7
+ #if __ARM_FEATURE_DSP
+ #define __ARM_ARCH_7EM__ 1
+ #else
+ #define __ARM_ARCH_7M__ 1
+ #endif
+ #endif /* __ARM_ARCH */
+ #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+ #define __ARM_ARCH_6M__ 1
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+ #define __ARM_ARCH_7M__ 1
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+ #define __ARM_ARCH_7EM__ 1
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+ #define __ARM_ARCH_8M_BASE__ 1
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+ #define __ARM_ARCH_8M_MAIN__ 1
+ #else
+ #error "Unknown target."
+ #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+ #define __IAR_M0_FAMILY 1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+ #define __IAR_M0_FAMILY 1
+#else
+ #define __IAR_M0_FAMILY 0
+#endif
+
+
+#ifndef __ASM
+ #define __ASM __asm
+#endif
+
+#ifndef __COMPILER_BARRIER
+ #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+#ifndef __INLINE
+ #define __INLINE inline
+#endif
+
+#ifndef __NO_RETURN
+ #if __ICCARM_V8
+ #define __NO_RETURN __attribute__((__noreturn__))
+ #else
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+ #endif
+#endif
+
+#ifndef __PACKED
+ #if __ICCARM_V8
+ #define __PACKED __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED __packed
+ #endif
+#endif
+
+#ifndef __PACKED_STRUCT
+ #if __ICCARM_V8
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_STRUCT __packed struct
+ #endif
+#endif
+
+#ifndef __PACKED_UNION
+ #if __ICCARM_V8
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+ #else
+ /* Needs IAR language extensions */
+ #define __PACKED_UNION __packed union
+ #endif
+#endif
+
+#ifndef __RESTRICT
+ #if __ICCARM_V8
+ #define __RESTRICT __restrict
+ #else
+ /* Needs IAR language extensions */
+ #define __RESTRICT restrict
+ #endif
+#endif
+
+#ifndef __STATIC_INLINE
+ #define __STATIC_INLINE static inline
+#endif
+
+#ifndef __FORCEINLINE
+ #define __FORCEINLINE _Pragma("inline=forced")
+#endif
+
+#ifndef __STATIC_FORCEINLINE
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+ return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+ *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+ return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+ *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32 /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef __USED
+ #if __ICCARM_V8
+ #define __USED __attribute__((used))
+ #else
+ #define __USED _Pragma("__root")
+ #endif
+#endif
+
+#ifndef __WEAK
+ #if __ICCARM_V8
+ #define __WEAK __attribute__((weak))
+ #else
+ #define __WEAK _Pragma("__weak")
+ #endif
+#endif
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START __iar_program_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP CSTACK$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT CSTACK$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE __vector_table
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
+#endif
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+ #define __ICCARM_INTRINSICS_VERSION__ 0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+ #if defined(__CLZ)
+ #undef __CLZ
+ #endif
+ #if defined(__REVSH)
+ #undef __REVSH
+ #endif
+ #if defined(__RBIT)
+ #undef __RBIT
+ #endif
+ #if defined(__SSAT)
+ #undef __SSAT
+ #endif
+ #if defined(__USAT)
+ #undef __USAT
+ #endif
+
+ #include "iccarm_builtin.h"
+
+ #define __disable_fault_irq __iar_builtin_disable_fiq
+ #define __disable_irq __iar_builtin_disable_interrupt
+ #define __enable_fault_irq __iar_builtin_enable_fiq
+ #define __enable_irq __iar_builtin_enable_interrupt
+ #define __arm_rsr __iar_builtin_rsr
+ #define __arm_wsr __iar_builtin_wsr
+
+
+ #define __get_APSR() (__arm_rsr("APSR"))
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
+
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
+ #else
+ #define __get_FPSCR() ( 0 )
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #define __get_IPSR() (__arm_rsr("IPSR"))
+ #define __get_MSP() (__arm_rsr("MSP"))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __get_MSPLIM() (0U)
+ #else
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
+ #endif
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
+ #define __get_PSP() (__arm_rsr("PSP"))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __get_PSPLIM() (0U)
+ #else
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
+ #endif
+
+ #define __get_xPSR() (__arm_rsr("xPSR"))
+
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
+ #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
+ #endif
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))
+ #else
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
+ #endif
+
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
+ #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ #define __TZ_get_PSPLIM_NS() (0U)
+ #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+ #else
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+ #endif
+
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+ #define __NOP __iar_builtin_no_operation
+
+ #define __CLZ __iar_builtin_CLZ
+ #define __CLREX __iar_builtin_CLREX
+
+ #define __DMB __iar_builtin_DMB
+ #define __DSB __iar_builtin_DSB
+ #define __ISB __iar_builtin_ISB
+
+ #define __LDREXB __iar_builtin_LDREXB
+ #define __LDREXH __iar_builtin_LDREXH
+ #define __LDREXW __iar_builtin_LDREX
+
+ #define __RBIT __iar_builtin_RBIT
+ #define __REV __iar_builtin_REV
+ #define __REV16 __iar_builtin_REV16
+
+ __IAR_FT int16_t __REVSH(int16_t val)
+ {
+ return (int16_t) __iar_builtin_REVSH(val);
+ }
+
+ #define __ROR __iar_builtin_ROR
+ #define __RRX __iar_builtin_RRX
+
+ #define __SEV __iar_builtin_SEV
+
+ #if !__IAR_M0_FAMILY
+ #define __SSAT __iar_builtin_SSAT
+ #endif
+
+ #define __STREXB __iar_builtin_STREXB
+ #define __STREXH __iar_builtin_STREXH
+ #define __STREXW __iar_builtin_STREX
+
+ #if !__IAR_M0_FAMILY
+ #define __USAT __iar_builtin_USAT
+ #endif
+
+ #define __WFE __iar_builtin_WFE
+ #define __WFI __iar_builtin_WFI
+
+ #if __ARM_MEDIA__
+ #define __SADD8 __iar_builtin_SADD8
+ #define __QADD8 __iar_builtin_QADD8
+ #define __SHADD8 __iar_builtin_SHADD8
+ #define __UADD8 __iar_builtin_UADD8
+ #define __UQADD8 __iar_builtin_UQADD8
+ #define __UHADD8 __iar_builtin_UHADD8
+ #define __SSUB8 __iar_builtin_SSUB8
+ #define __QSUB8 __iar_builtin_QSUB8
+ #define __SHSUB8 __iar_builtin_SHSUB8
+ #define __USUB8 __iar_builtin_USUB8
+ #define __UQSUB8 __iar_builtin_UQSUB8
+ #define __UHSUB8 __iar_builtin_UHSUB8
+ #define __SADD16 __iar_builtin_SADD16
+ #define __QADD16 __iar_builtin_QADD16
+ #define __SHADD16 __iar_builtin_SHADD16
+ #define __UADD16 __iar_builtin_UADD16
+ #define __UQADD16 __iar_builtin_UQADD16
+ #define __UHADD16 __iar_builtin_UHADD16
+ #define __SSUB16 __iar_builtin_SSUB16
+ #define __QSUB16 __iar_builtin_QSUB16
+ #define __SHSUB16 __iar_builtin_SHSUB16
+ #define __USUB16 __iar_builtin_USUB16
+ #define __UQSUB16 __iar_builtin_UQSUB16
+ #define __UHSUB16 __iar_builtin_UHSUB16
+ #define __SASX __iar_builtin_SASX
+ #define __QASX __iar_builtin_QASX
+ #define __SHASX __iar_builtin_SHASX
+ #define __UASX __iar_builtin_UASX
+ #define __UQASX __iar_builtin_UQASX
+ #define __UHASX __iar_builtin_UHASX
+ #define __SSAX __iar_builtin_SSAX
+ #define __QSAX __iar_builtin_QSAX
+ #define __SHSAX __iar_builtin_SHSAX
+ #define __USAX __iar_builtin_USAX
+ #define __UQSAX __iar_builtin_UQSAX
+ #define __UHSAX __iar_builtin_UHSAX
+ #define __USAD8 __iar_builtin_USAD8
+ #define __USADA8 __iar_builtin_USADA8
+ #define __SSAT16 __iar_builtin_SSAT16
+ #define __USAT16 __iar_builtin_USAT16
+ #define __UXTB16 __iar_builtin_UXTB16
+ #define __UXTAB16 __iar_builtin_UXTAB16
+ #define __SXTB16 __iar_builtin_SXTB16
+ #define __SXTAB16 __iar_builtin_SXTAB16
+ #define __SMUAD __iar_builtin_SMUAD
+ #define __SMUADX __iar_builtin_SMUADX
+ #define __SMMLA __iar_builtin_SMMLA
+ #define __SMLAD __iar_builtin_SMLAD
+ #define __SMLADX __iar_builtin_SMLADX
+ #define __SMLALD __iar_builtin_SMLALD
+ #define __SMLALDX __iar_builtin_SMLALDX
+ #define __SMUSD __iar_builtin_SMUSD
+ #define __SMUSDX __iar_builtin_SMUSDX
+ #define __SMLSD __iar_builtin_SMLSD
+ #define __SMLSDX __iar_builtin_SMLSDX
+ #define __SMLSLD __iar_builtin_SMLSLD
+ #define __SMLSLDX __iar_builtin_SMLSLDX
+ #define __SEL __iar_builtin_SEL
+ #define __QADD __iar_builtin_QADD
+ #define __QSUB __iar_builtin_QSUB
+ #define __PKHBT __iar_builtin_PKHBT
+ #define __PKHTB __iar_builtin_PKHTB
+ #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #define __CLZ __cmsis_iar_clz_not_active
+ #define __SSAT __cmsis_iar_ssat_not_active
+ #define __USAT __cmsis_iar_usat_not_active
+ #define __RBIT __cmsis_iar_rbit_not_active
+ #define __get_APSR __cmsis_iar_get_APSR_not_active
+ #endif
+
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+ #endif
+
+ #ifdef __INTRINSICS_INCLUDED
+ #error intrinsics.h is already included previously!
+ #endif
+
+ #include
+
+ #if __IAR_M0_FAMILY
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+ #undef __CLZ
+ #undef __SSAT
+ #undef __USAT
+ #undef __RBIT
+ #undef __get_APSR
+
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+ {
+ if (data == 0U) { return 32U; }
+
+ uint32_t count = 0U;
+ uint32_t mask = 0x80000000U;
+
+ while ((data & mask) == 0U)
+ {
+ count += 1U;
+ mask = mask >> 1U;
+ }
+ return count;
+ }
+
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+ {
+ uint8_t sc = 31U;
+ uint32_t r = v;
+ for (v >>= 1U; v; v >>= 1U)
+ {
+ r <<= 1U;
+ r |= v & 1U;
+ sc--;
+ }
+ return (r << sc);
+ }
+
+ __STATIC_INLINE uint32_t __get_APSR(void)
+ {
+ uint32_t res;
+ __asm("MRS %0,APSR" : "=r" (res));
+ return res;
+ }
+
+ #endif
+
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
+ #undef __get_FPSCR
+ #undef __set_FPSCR
+ #define __get_FPSCR() (0)
+ #define __set_FPSCR(VALUE) ((void)VALUE)
+ #endif
+
+ #pragma diag_suppress=Pe940
+ #pragma diag_suppress=Pe177
+
+ #define __enable_irq __enable_interrupt
+ #define __disable_irq __disable_interrupt
+ #define __NOP __no_operation
+
+ #define __get_xPSR __get_PSR
+
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+ {
+ return __LDREX((unsigned long *)ptr);
+ }
+
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+ {
+ return __STREX(value, (unsigned long *)ptr);
+ }
+ #endif
+
+
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+ #if (__CORTEX_M >= 0x03)
+
+ __IAR_FT uint32_t __RRX(uint32_t value)
+ {
+ uint32_t result;
+ __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value));
+ return(result);
+ }
+
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
+ }
+
+
+ #define __enable_fault_irq __enable_fiq
+ #define __disable_fault_irq __disable_fiq
+
+
+ #endif /* (__CORTEX_M >= 0x03) */
+
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+ {
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+ }
+
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+ __IAR_FT uint32_t __get_MSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_MSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure MSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __get_PSPLIM(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __set_PSPLIM(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
+ {
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));
+ return res;
+ }
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)
+ {
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
+ {
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
+ {
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
+ }
+
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
+ {
+ uint32_t res;
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ res = 0U;
+ #else
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
+ #endif
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
+ {
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
+ // without main extensions, the non-secure PSPLIM is RAZ/WI
+ (void)value;
+ #else
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
+ #endif
+ }
+
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
+ {
+ uint32_t res;
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
+ return res;
+ }
+
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
+ {
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
+ }
+
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+ {
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+ }
+
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+ {
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+ }
+#endif
+
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+ {
+ __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+ {
+ __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+ }
+
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+ {
+ __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+ }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
+
+
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+ {
+ __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+ {
+ __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+ {
+ __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+ }
+
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint8_t)res);
+ }
+
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return ((uint16_t)res);
+ }
+
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+ {
+ uint32_t res;
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+ return res;
+ }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_version.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_version.h
new file mode 100644
index 0000000000..2f048e4552
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file cmsis_version.h
+ * @brief CMSIS Core(M) Version definitions
+ * @version V5.0.4
+ * @date 23. July 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/* CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
+#endif
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_armv81mml.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_armv81mml.h
new file mode 100644
index 0000000000..1ad19e215a
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_armv81mml.h
@@ -0,0 +1,4191 @@
+/**************************************************************************//**
+ * @file core_armv81mml.h
+ * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File
+ * @version V1.3.1
+ * @date 27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#elif defined ( __GNUC__ )
+ #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
+#endif
+
+#ifndef __CORE_ARMV81MML_H_GENERIC
+#define __CORE_ARMV81MML_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_ARMV81MML
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS ARMV81MML definitions */
+#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \
+ __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (81U) /*!< Cortex-M Core */
+
+#if defined ( __CC_ARM )
+ #error Legacy Arm Compiler does not support Armv8.1-M target architecture.
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV81MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV81MML_H_DEPENDANT
+#define __CORE_ARMV81MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __ARMv81MML_REV
+ #define __ARMv81MML_REV 0x0000U
+ #warning "__ARMv81MML_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #if __FPU_PRESENT != 0U
+ #ifndef __FPU_DP
+ #define __FPU_DP 0U
+ #warning "__FPU_DP not defined in device header file; using default!"
+ #endif
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ICACHE_PRESENT
+ #define __ICACHE_PRESENT 0U
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DCACHE_PRESENT
+ #define __DCACHE_PRESENT 0U
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __PMU_PRESENT
+ #define __PMU_PRESENT 0U
+ #warning "__PMU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #if __PMU_PRESENT != 0U
+ #ifndef __PMU_NUM_EVENTCNT
+ #define __PMU_NUM_EVENTCNT 2U
+ #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!"
+ #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2)
+ #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */
+ #endif
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv81MML */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */
+ uint32_t RESERVED4[14U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */
+#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */
+
+#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */
+#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */
+#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */
+
+#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */
+#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */
+
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */
+#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */
+
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */
+#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */
+
+#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */
+#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */
+
+#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */
+#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */
+
+#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */
+#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */
+
+#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */
+#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */
+
+#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */
+#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */
+
+#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */
+#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */
+
+#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */
+#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */
+
+/* SCB Debug Feature Register 0 Definitions */
+#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */
+#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */
+
+#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */
+#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB RAS Fault Status Register Definitions */
+#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */
+#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */
+
+#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */
+#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */
+
+#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */
+#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[3U];
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */
+#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_PMU Performance Monitoring Unit (PMU)
+ \brief Type definitions for the Performance Monitoring Unit (PMU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Performance Monitoring Unit (PMU).
+ */
+typedef struct
+{
+ __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */
+#if __PMU_NUM_EVENTCNT<31
+ uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT];
+#endif
+ __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */
+ uint32_t RESERVED1[224];
+ __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */
+#if __PMU_NUM_EVENTCNT<31
+ uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT];
+#endif
+ __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */
+ uint32_t RESERVED3[480];
+ __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */
+ uint32_t RESERVED4[7];
+ __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */
+ uint32_t RESERVED5[7];
+ __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */
+ uint32_t RESERVED6[7];
+ __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */
+ uint32_t RESERVED7[7];
+ __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */
+ uint32_t RESERVED8[7];
+ __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */
+ uint32_t RESERVED9[7];
+ __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */
+ uint32_t RESERVED10[79];
+ __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */
+ uint32_t RESERVED11[108];
+ __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */
+ __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */
+ uint32_t RESERVED12[4];
+ __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */
+ __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */
+ uint32_t RESERVED13[3];
+ __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */
+ __IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */
+ __IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */
+ __IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */
+ uint32_t RESERVED14[3];
+ __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */
+ __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */
+ __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */
+ __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */
+} PMU_Type;
+
+/** \brief PMU Event Counter Registers (0-30) Definitions */
+
+#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */
+#define PMU_EVCNTR_CNT_Msk (16UL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */
+
+/** \brief PMU Event Type and Filter Registers (0-30) Definitions */
+
+#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */
+#define PMU_EVTYPER_EVENTTOCNT_Msk (16UL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */
+
+/** \brief PMU Count Enable Set Register Definitions */
+
+#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */
+#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */
+#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */
+#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */
+#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */
+#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */
+#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */
+#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */
+#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */
+#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */
+#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */
+#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */
+#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */
+#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */
+#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */
+#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */
+#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */
+#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */
+#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */
+#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */
+#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */
+#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */
+#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */
+#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */
+#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */
+#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */
+#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */
+#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */
+#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */
+#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */
+#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */
+#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */
+
+#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */
+#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */
+
+/** \brief PMU Count Enable Clear Register Definitions */
+
+#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */
+#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */
+#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */
+
+#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */
+#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */
+#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */
+#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */
+#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */
+#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */
+#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */
+#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */
+#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */
+#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */
+#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */
+#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */
+#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */
+#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */
+#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */
+#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */
+#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */
+#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */
+#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */
+#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */
+#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */
+#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */
+#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */
+#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */
+#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */
+#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */
+#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */
+#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */
+#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */
+#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */
+#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */
+
+/** \brief PMU Interrupt Enable Set Register Definitions */
+
+#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */
+#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */
+
+/** \brief PMU Interrupt Enable Clear Register Definitions */
+
+#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */
+
+#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */
+
+/** \brief PMU Overflow Flag Status Set Register Definitions */
+
+#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */
+#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */
+#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */
+#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */
+#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */
+#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */
+#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */
+#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */
+#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */
+#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */
+#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */
+#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */
+#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */
+#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */
+#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */
+#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */
+#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */
+#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */
+#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */
+#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */
+#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */
+#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */
+#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */
+#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */
+#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */
+#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */
+#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */
+#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */
+#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */
+#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */
+#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */
+#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */
+
+#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */
+#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */
+
+/** \brief PMU Overflow Flag Status Clear Register Definitions */
+
+#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */
+#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */
+#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */
+
+#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */
+#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */
+#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */
+#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */
+#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */
+#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */
+#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */
+#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */
+#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */
+#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */
+#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */
+#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */
+#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */
+#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */
+#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */
+#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */
+#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */
+#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */
+#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */
+#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */
+#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */
+#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */
+#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */
+#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */
+#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */
+#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */
+#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */
+#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */
+#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */
+#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */
+#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */
+
+/** \brief PMU Software Increment Counter */
+
+#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */
+#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */
+
+#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */
+#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */
+
+#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */
+#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */
+
+#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */
+#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */
+
+#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */
+#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */
+
+#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */
+#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */
+
+#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */
+#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */
+
+#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */
+#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */
+
+#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */
+#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */
+
+#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */
+#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */
+
+#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */
+#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */
+
+#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */
+#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */
+
+#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */
+#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */
+
+#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */
+#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */
+
+#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */
+#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */
+
+#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */
+#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */
+
+#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */
+#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */
+
+#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */
+#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */
+
+#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */
+#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */
+
+#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */
+#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */
+
+#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */
+#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */
+
+#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */
+#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */
+
+#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */
+#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */
+
+#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */
+#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */
+
+#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */
+#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */
+
+#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */
+#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */
+
+#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */
+#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */
+
+#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */
+#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */
+
+#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */
+#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */
+
+#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */
+#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */
+
+#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */
+#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */
+
+/** \brief PMU Control Register Definitions */
+
+#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */
+#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */
+
+#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */
+#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */
+
+#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */
+#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */
+
+#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */
+#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */
+
+#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */
+#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */
+
+#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */
+#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */
+
+/** \brief PMU Type Register Definitions */
+
+#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */
+#define PMU_TYPE_NUM_CNTS_Msk (8UL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */
+
+#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */
+#define PMU_TYPE_SIZE_CNTS_Msk (6UL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */
+
+#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */
+#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */
+
+#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */
+#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */
+
+#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */
+#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */
+
+/*@} end of group CMSIS_PMU */
+#endif
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */
+#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */
+#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */
+
+#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */
+#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */
+
+/* Media and VFP Feature Register 0 Definitions */
+#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */
+#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */
+
+#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */
+#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */
+
+#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */
+#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */
+#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */
+
+#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */
+#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */
+
+#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */
+#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */
+
+/* Media and VFP Feature Register 1 Definitions */
+#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */
+#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */
+
+#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */
+#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */
+
+#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */
+#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */
+
+#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */
+#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */
+
+#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */
+#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */
+
+#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */
+#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */
+
+/* Media and VFP Feature Register 2 Definitions */
+#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
+#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */
+#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */
+
+#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */
+#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */
+
+#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */
+#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */
+
+#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */
+#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */
+#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Set Clear Exception and Monitor Control Register Definitions */
+#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */
+#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */
+
+#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */
+#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */
+
+#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */
+#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */
+
+#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */
+#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */
+#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */
+#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */
+#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DCB Debug Control Block
+ \brief Type definitions for the Debug Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */
+#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */
+
+#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */
+#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */
+
+#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */
+#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */
+
+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */
+#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */
+
+#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
+#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
+#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
+
+#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
+#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
+
+#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
+#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
+
+#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
+#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
+
+#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
+#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
+
+#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
+#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
+
+#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
+#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
+
+#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
+#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
+#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
+
+#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
+#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
+
+#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
+#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
+
+#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
+#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
+
+#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
+#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
+
+#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
+#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */
+#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */
+#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */
+
+#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */
+#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */
+
+#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */
+#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */
+
+#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */
+#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */
+#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */
+
+#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */
+#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */
+
+#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */
+#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */
+
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DIB Debug Identification Block
+ \brief Type definitions for the Debug Identification Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+ __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
+ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */
+#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */
+
+#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
+ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
+ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+ #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */
+ #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
+ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
+ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
+ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
+ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## PMU functions and events #################################### */
+
+#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+
+#include "pmu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+/* ########################## MVE functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_MveFunctions MVE Functions
+ \brief Function that provides MVE type.
+ @{
+ */
+
+/**
+ \brief get MVE type
+ \details returns the MVE type
+ \returns
+ - \b 0: No Vector Extension (MVE)
+ - \b 1: Integer Vector Extension (MVE-I)
+ - \b 2: Floating-point Vector Extension (MVE-F)
+ */
+__STATIC_INLINE uint32_t SCB_GetMVEType(void)
+{
+ const uint32_t mvfr1 = FPU->MVFR1;
+ if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos))
+ {
+ return 2U;
+ }
+ else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos))
+ {
+ return 1U;
+ }
+ else
+ {
+ return 0U;
+ }
+}
+
+
+/*@} end of CMSIS_Core_MveFunctions */
+
+
+/* ########################## Cache functions #################################### */
+
+#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
+ (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
+#include "cachel1_armv7.h"
+#endif
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## Debug Control function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+ \brief Functions that access the Debug Control Block.
+ @{
+ */
+
+
+/**
+ \brief Set Debug Authentication Control Register
+ \details writes to Debug Authentication Control register.
+ \param [in] value value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register
+ \details Reads Debug Authentication Control register.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+ return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Debug Authentication Control Register (non-secure)
+ \details writes to non-secure Debug Authentication Control register when in secure state.
+ \param [in] value value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB_NS->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register (non-secure)
+ \details Reads non-secure Debug Authentication Control register when in secure state.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+ return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## Debug Identification function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+ \brief Functions that access the Debug Identification Block.
+ @{
+ */
+
+
+/**
+ \brief Get Debug Authentication Status Register
+ \details Reads Debug Authentication Status register.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+ return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Debug Authentication Status Register (non-secure)
+ \details Reads non-secure Debug Authentication Status register when in secure state.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+ return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV81MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_armv8mbl.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_armv8mbl.h
new file mode 100644
index 0000000000..932d3d188b
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_armv8mbl.h
@@ -0,0 +1,2222 @@
+/**************************************************************************//**
+ * @file core_armv8mbl.h
+ * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
+ * @version V5.1.0
+ * @date 27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#elif defined ( __GNUC__ )
+ #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_ARMv8MBL
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+ __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (2U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __ARMv8MBL_REV
+ #define __ARMv8MBL_REV 0x0000U
+ #warning "__ARMv8MBL_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ETM_PRESENT
+ #define __ETM_PRESENT 0U
+ #warning "__ETM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MTB_PRESENT
+ #define __MTB_PRESENT 0U
+ #warning "__MTB_PRESENT not defined in device header file; using default!"
+ #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DCB Debug Control Block
+ \brief Type definitions for the Debug Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DIB Debug Identification Block
+ \brief Type definitions for the Debug Identification Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+ __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
+ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
+ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
+ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
+ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
+ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
+ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
+ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## Debug Control function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+ \brief Functions that access the Debug Control Block.
+ @{
+ */
+
+
+/**
+ \brief Set Debug Authentication Control Register
+ \details writes to Debug Authentication Control register.
+ \param [in] value value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register
+ \details Reads Debug Authentication Control register.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+ return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Debug Authentication Control Register (non-secure)
+ \details writes to non-secure Debug Authentication Control register when in secure state.
+ \param [in] value value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB_NS->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register (non-secure)
+ \details Reads non-secure Debug Authentication Control register when in secure state.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+ return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## Debug Identification function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+ \brief Functions that access the Debug Identification Block.
+ @{
+ */
+
+
+/**
+ \brief Get Debug Authentication Status Register
+ \details Reads Debug Authentication Status register.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+ return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Debug Authentication Status Register (non-secure)
+ \details Reads non-secure Debug Authentication Status register when in secure state.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+ return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_armv8mml.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_armv8mml.h
new file mode 100644
index 0000000000..71f000bcad
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_armv8mml.h
@@ -0,0 +1,3196 @@
+/**************************************************************************//**
+ * @file core_armv8mml.h
+ * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
+ * @version V5.2.0
+ * @date 27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#elif defined ( __GNUC__ )
+ #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_ARMv8MML
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS Armv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+ __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (80U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __ARMv8MML_REV
+ #define __ARMv8MML_REV 0x0000U
+ #warning "__ARMv8MML_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and VFP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and VFP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and VFP Feature Register 2 Definitions */
+#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
+#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DCB Debug Control Block
+ \brief Type definitions for the Debug Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
+#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
+#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
+
+#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
+#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
+
+#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
+#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
+
+#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
+#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
+
+#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
+#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
+
+#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
+#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
+
+#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
+#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
+
+#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
+#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
+#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
+
+#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
+#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
+
+#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
+#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
+
+#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
+#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
+
+#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
+#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
+
+#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
+#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DIB Debug Identification Block
+ \brief Type definitions for the Debug Identification Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+ __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
+ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
+ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
+ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
+ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
+ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
+ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
+ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+/* ########################## Cache functions #################################### */
+
+#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
+ (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
+#include "cachel1_armv7.h"
+#endif
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## Debug Control function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+ \brief Functions that access the Debug Control Block.
+ @{
+ */
+
+
+/**
+ \brief Set Debug Authentication Control Register
+ \details writes to Debug Authentication Control register.
+ \param [in] value value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register
+ \details Reads Debug Authentication Control register.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+ return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Debug Authentication Control Register (non-secure)
+ \details writes to non-secure Debug Authentication Control register when in secure state.
+ \param [in] value value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB_NS->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register (non-secure)
+ \details Reads non-secure Debug Authentication Control register when in secure state.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+ return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## Debug Identification function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+ \brief Functions that access the Debug Identification Block.
+ @{
+ */
+
+
+/**
+ \brief Get Debug Authentication Status Register
+ \details Reads Debug Authentication Status register.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+ return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Debug Authentication Status Register (non-secure)
+ \details Reads non-secure Debug Authentication Status register when in secure state.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+ return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm0.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm0.h
new file mode 100644
index 0000000000..6441ff3419
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm0.h
@@ -0,0 +1,952 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V5.0.8
+ * @date 21. August 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M0
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (0U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000U
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ Address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
+ *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
+ /* ARM Application Note 321 states that the M0 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
+ return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm0plus.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm0plus.h
new file mode 100644
index 0000000000..4e7179a614
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm0plus.h
@@ -0,0 +1,1087 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V5.0.9
+ * @date 21. August 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex-M0+
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (0U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000U
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0+ header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+#else
+ uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
+ *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
+#endif
+ /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+#else
+ uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
+ return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
+#endif
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm1.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm1.h
new file mode 100644
index 0000000000..76b4569743
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm1.h
@@ -0,0 +1,979 @@
+/**************************************************************************//**
+ * @file core_cm1.h
+ * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
+ * @version V1.0.1
+ * @date 12. November 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM1_H_GENERIC
+#define __CORE_CM1_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M1
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM1 definitions */
+#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
+ __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (1U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM1_H_DEPENDANT
+#define __CORE_CM1_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM1_REV
+ #define __CM1_REV 0x0100U
+ #warning "__CM1_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M1 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ Address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M1 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)0x0U;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm23.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm23.h
new file mode 100644
index 0000000000..55fff99509
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm23.h
@@ -0,0 +1,2297 @@
+/**************************************************************************//**
+ * @file core_cm23.h
+ * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version V5.1.0
+ * @date 11. February 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#elif defined ( __GNUC__ )
+ #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M23
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS definitions */
+#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+ __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (23U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM23_REV
+ #define __CM23_REV 0x0000U
+ #warning "__CM23_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ETM_PRESENT
+ #define __ETM_PRESENT 0U
+ #warning "__ETM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MTB_PRESENT
+ #define __MTB_PRESENT 0U
+ #warning "__MTB_PRESENT not defined in device header file; using default!"
+ #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ uint32_t RESERVED0[6U];
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ uint32_t RESERVED0[7U];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DCB Debug Control Block
+ \brief Type definitions for the Debug Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DIB Debug Identification Block
+ \brief Type definitions for the Debug Identification Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+ __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
+ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
+ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
+ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
+ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
+ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
+ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
+ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping() (0U)
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ If VTOR is not present address 0 must be mapped to SRAM.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+ uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## Debug Control function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+ \brief Functions that access the Debug Control Block.
+ @{
+ */
+
+
+/**
+ \brief Set Debug Authentication Control Register
+ \details writes to Debug Authentication Control register.
+ \param [in] value value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register
+ \details Reads Debug Authentication Control register.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+ return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Debug Authentication Control Register (non-secure)
+ \details writes to non-secure Debug Authentication Control register when in secure state.
+ \param [in] value value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB_NS->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register (non-secure)
+ \details Reads non-secure Debug Authentication Control register when in secure state.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+ return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## Debug Identification function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+ \brief Functions that access the Debug Identification Block.
+ @{
+ */
+
+
+/**
+ \brief Get Debug Authentication Status Register
+ \details Reads Debug Authentication Status register.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+ return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Debug Authentication Status Register (non-secure)
+ \details Reads non-secure Debug Authentication Status register when in secure state.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+ return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm3.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm3.h
new file mode 100644
index 0000000000..24453a8863
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm3.h
@@ -0,0 +1,1943 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V5.1.1
+ * @date 27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M3
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (3U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200U
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+#endif
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M3 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm33.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm33.h
new file mode 100644
index 0000000000..13359be3ed
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm33.h
@@ -0,0 +1,3264 @@
+/**************************************************************************//**
+ * @file core_cm33.h
+ * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version V5.2.0
+ * @date 27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#elif defined ( __GNUC__ )
+ #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M33
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+ __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (33U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined (__TARGET_FPU_VFP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined (__ARM_FP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined (__ARMVFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined (__TI_VFP_SUPPORT__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined (__FPU_VFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM33_REV
+ #define __CM33_REV 0x0000U
+ #warning "__CM33_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and VFP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and VFP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and VFP Feature Register 2 Definitions */
+#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
+#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DCB Debug Control Block
+ \brief Type definitions for the Debug Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
+#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
+#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
+
+#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
+#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
+
+#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
+#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
+
+#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
+#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
+
+#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
+#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
+
+#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
+#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
+
+#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
+#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
+
+#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
+#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
+#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
+
+#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
+#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
+
+#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
+#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
+
+#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
+#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
+
+#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
+#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
+
+#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
+#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DIB Debug Identification Block
+ \brief Type definitions for the Debug Identification Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+ __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
+ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
+ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
+ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
+ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
+ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
+ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
+ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## Debug Control function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+ \brief Functions that access the Debug Control Block.
+ @{
+ */
+
+
+/**
+ \brief Set Debug Authentication Control Register
+ \details writes to Debug Authentication Control register.
+ \param [in] value value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register
+ \details Reads Debug Authentication Control register.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+ return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Debug Authentication Control Register (non-secure)
+ \details writes to non-secure Debug Authentication Control register when in secure state.
+ \param [in] value value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB_NS->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register (non-secure)
+ \details Reads non-secure Debug Authentication Control register when in secure state.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+ return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## Debug Identification function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+ \brief Functions that access the Debug Identification Block.
+ @{
+ */
+
+
+/**
+ \brief Get Debug Authentication Status Register
+ \details Reads Debug Authentication Status register.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+ return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Debug Authentication Status Register (non-secure)
+ \details Reads non-secure Debug Authentication Status register when in secure state.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+ return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm35p.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm35p.h
new file mode 100644
index 0000000000..6a5f6ad147
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm35p.h
@@ -0,0 +1,3264 @@
+/**************************************************************************//**
+ * @file core_cm35p.h
+ * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File
+ * @version V1.1.0
+ * @date 27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#elif defined ( __GNUC__ )
+ #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
+#endif
+
+#ifndef __CORE_CM35P_H_GENERIC
+#define __CORE_CM35P_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M35P
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM35P definitions */
+#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \
+ __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (35U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined (__TARGET_FPU_VFP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined (__ARM_FP)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined (__ARMVFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined (__TI_VFP_SUPPORT__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined (__FPU_VFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM35P_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM35P_H_DEPENDANT
+#define __CORE_CM35P_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM35P_REV
+ #define __CM35P_REV 0x0000U
+ #warning "__CM35P_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M35P */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[4U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
+ __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
+ __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and VFP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and VFP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and VFP Feature Register 2 Definitions */
+#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
+#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DCB Debug Control Block
+ \brief Type definitions for the Debug Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
+#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
+#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
+
+#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
+#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
+
+#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
+#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
+
+#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
+#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
+
+#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
+#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
+
+#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
+#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
+
+#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
+#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
+
+#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
+#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
+#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
+
+#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
+#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
+
+#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
+#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
+
+#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
+#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
+
+#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
+#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
+
+#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
+#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DIB Debug Identification Block
+ \brief Type definitions for the Debug Identification Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+ __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
+ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
+ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
+ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
+ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
+ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
+ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
+ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## Debug Control function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+ \brief Functions that access the Debug Control Block.
+ @{
+ */
+
+
+/**
+ \brief Set Debug Authentication Control Register
+ \details writes to Debug Authentication Control register.
+ \param [in] value value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register
+ \details Reads Debug Authentication Control register.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+ return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Debug Authentication Control Register (non-secure)
+ \details writes to non-secure Debug Authentication Control register when in secure state.
+ \param [in] value value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB_NS->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register (non-secure)
+ \details Reads non-secure Debug Authentication Control register when in secure state.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+ return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## Debug Identification function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+ \brief Functions that access the Debug Identification Block.
+ @{
+ */
+
+
+/**
+ \brief Get Debug Authentication Status Register
+ \details Reads Debug Authentication Status register.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+ return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Debug Authentication Status Register (non-secure)
+ \details Reads non-secure Debug Authentication Status register when in secure state.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+ return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM35P_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm4.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm4.h
new file mode 100644
index 0000000000..4e0e886697
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm4.h
@@ -0,0 +1,2129 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V5.1.1
+ * @date 27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M4
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (4U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000U
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
+#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M4 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm55.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm55.h
new file mode 100644
index 0000000000..6efaa3f842
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm55.h
@@ -0,0 +1,4215 @@
+/**************************************************************************//**
+ * @file core_cm55.h
+ * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File
+ * @version V1.0.0
+ * @date 27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2018-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#elif defined ( __GNUC__ )
+ #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
+#endif
+
+#ifndef __CORE_CM55_H_GENERIC
+#define __CORE_CM55_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_CM55
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM55 definitions */
+#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \
+ __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (55U) /*!< Cortex-M Core */
+
+#if defined ( __CC_ARM )
+ #error Legacy Arm Compiler does not support Armv8.1-M target architecture.
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+ #if defined(__ARM_FEATURE_DSP)
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+ #define __DSP_USED 1U
+ #else
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+ #define __DSP_USED 0U
+ #endif
+ #else
+ #define __DSP_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM55_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM55_H_DEPENDANT
+#define __CORE_CM55_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM55_REV
+ #define __CM55_REV 0x0000U
+ #warning "__CM55_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #if __FPU_PRESENT != 0U
+ #ifndef __FPU_DP
+ #define __FPU_DP 0U
+ #warning "__FPU_DP not defined in device header file; using default!"
+ #endif
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ICACHE_PRESENT
+ #define __ICACHE_PRESENT 0U
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DCACHE_PRESENT
+ #define __DCACHE_PRESENT 0U
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __PMU_PRESENT
+ #define __PMU_PRESENT 0U
+ #warning "__PMU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #if __PMU_PRESENT != 0U
+ #ifndef __PMU_NUM_EVENTCNT
+ #define __PMU_NUM_EVENTCNT 8U
+ #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!"
+ #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2)
+ #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */
+ #endif
+ #endif
+
+ #ifndef __SAUREGION_PRESENT
+ #define __SAUREGION_PRESENT 0U
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DSP_PRESENT
+ #define __DSP_PRESENT 0U
+ #warning "__DSP_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M55 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core SAU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[16U];
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[16U];
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[16U];
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[16U];
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[16U];
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
+ uint32_t RESERVED5[16U];
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED6[580U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
+ uint32_t RESERVED3[92U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */
+ uint32_t RESERVED4[14U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */
+#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */
+
+#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */
+#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */
+#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */
+
+#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */
+#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */
+
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */
+#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */
+
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */
+#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */
+
+#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */
+#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */
+
+#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */
+#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */
+
+#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */
+#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */
+
+#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */
+#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */
+
+#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */
+#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */
+
+#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */
+#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */
+
+#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */
+#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */
+
+/* SCB Debug Feature Register 0 Definitions */
+#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */
+#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */
+
+#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */
+#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB RAS Fault Status Register Definitions */
+#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */
+#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */
+
+#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */
+#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */
+
+#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */
+#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
+ uint32_t RESERVED6[3U];
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ uint32_t RESERVED3[1U];
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED4[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ uint32_t RESERVED5[1U];
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED6[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ uint32_t RESERVED7[1U];
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
+ uint32_t RESERVED9[1U];
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
+ uint32_t RESERVED10[1U];
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
+ uint32_t RESERVED11[1U];
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
+ uint32_t RESERVED12[1U];
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
+ uint32_t RESERVED13[1U];
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
+ uint32_t RESERVED14[1U];
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
+ uint32_t RESERVED15[1U];
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
+ uint32_t RESERVED16[1U];
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
+ uint32_t RESERVED17[1U];
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
+ uint32_t RESERVED18[1U];
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
+ uint32_t RESERVED19[1U];
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
+ uint32_t RESERVED20[1U];
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
+ uint32_t RESERVED21[1U];
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
+ uint32_t RESERVED22[1U];
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
+ uint32_t RESERVED23[1U];
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
+ uint32_t RESERVED24[1U];
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
+ uint32_t RESERVED25[1U];
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
+ uint32_t RESERVED26[1U];
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
+ uint32_t RESERVED27[1U];
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
+ uint32_t RESERVED28[1U];
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
+ uint32_t RESERVED29[1U];
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
+ uint32_t RESERVED30[1U];
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
+ uint32_t RESERVED31[1U];
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
+ uint32_t RESERVED32[934U];
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+ uint32_t RESERVED33[1U];
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
+ uint32_t RESERVED3[809U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
+ uint32_t RESERVED4[4U];
+ __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */
+#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_PMU Performance Monitoring Unit (PMU)
+ \brief Type definitions for the Performance Monitoring Unit (PMU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Performance Monitoring Unit (PMU).
+ */
+typedef struct
+{
+ __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */
+#if __PMU_NUM_EVENTCNT<31
+ uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT];
+#endif
+ __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */
+ uint32_t RESERVED1[224];
+ __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */
+#if __PMU_NUM_EVENTCNT<31
+ uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT];
+#endif
+ __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */
+ uint32_t RESERVED3[480];
+ __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */
+ uint32_t RESERVED4[7];
+ __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */
+ uint32_t RESERVED5[7];
+ __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */
+ uint32_t RESERVED6[7];
+ __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */
+ uint32_t RESERVED7[7];
+ __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */
+ uint32_t RESERVED8[7];
+ __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */
+ uint32_t RESERVED9[7];
+ __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */
+ uint32_t RESERVED10[79];
+ __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */
+ uint32_t RESERVED11[108];
+ __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */
+ __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */
+ uint32_t RESERVED12[4];
+ __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */
+ __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */
+ uint32_t RESERVED13[3];
+ __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */
+ __IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */
+ __IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */
+ __IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */
+ uint32_t RESERVED14[3];
+ __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */
+ __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */
+ __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */
+ __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */
+} PMU_Type;
+
+/** \brief PMU Event Counter Registers (0-30) Definitions */
+
+#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */
+#define PMU_EVCNTR_CNT_Msk (16UL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */
+
+/** \brief PMU Event Type and Filter Registers (0-30) Definitions */
+
+#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */
+#define PMU_EVTYPER_EVENTTOCNT_Msk (16UL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */
+
+/** \brief PMU Count Enable Set Register Definitions */
+
+#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */
+#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */
+#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */
+#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */
+#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */
+#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */
+#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */
+#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */
+#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */
+#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */
+#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */
+#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */
+#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */
+#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */
+#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */
+#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */
+#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */
+#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */
+#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */
+#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */
+#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */
+#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */
+#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */
+#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */
+#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */
+#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */
+#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */
+#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */
+#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */
+#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */
+#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */
+
+#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */
+#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */
+
+#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */
+#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */
+
+/** \brief PMU Count Enable Clear Register Definitions */
+
+#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */
+#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */
+#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */
+
+#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */
+#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */
+#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */
+#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */
+#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */
+#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */
+#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */
+#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */
+#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */
+#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */
+#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */
+#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */
+#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */
+#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */
+#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */
+#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */
+#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */
+#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */
+#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */
+#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */
+#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */
+#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */
+#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */
+#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */
+#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */
+#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */
+#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */
+#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */
+#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */
+#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */
+
+#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */
+#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */
+
+/** \brief PMU Interrupt Enable Set Register Definitions */
+
+#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */
+#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */
+
+#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */
+#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */
+
+/** \brief PMU Interrupt Enable Clear Register Definitions */
+
+#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */
+
+#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */
+
+#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */
+#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */
+
+/** \brief PMU Overflow Flag Status Set Register Definitions */
+
+#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */
+#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */
+#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */
+#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */
+#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */
+#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */
+#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */
+#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */
+#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */
+#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */
+#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */
+#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */
+#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */
+#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */
+#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */
+#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */
+#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */
+#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */
+#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */
+#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */
+#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */
+#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */
+#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */
+#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */
+#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */
+#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */
+#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */
+#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */
+#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */
+#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */
+#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */
+
+#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */
+#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */
+
+#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */
+#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */
+
+/** \brief PMU Overflow Flag Status Clear Register Definitions */
+
+#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */
+#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */
+#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */
+
+#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */
+#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */
+#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */
+#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */
+#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */
+#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */
+#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */
+#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */
+#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */
+#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */
+#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */
+#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */
+#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */
+#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */
+#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */
+#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */
+#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */
+#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */
+#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */
+#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */
+#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */
+#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */
+#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */
+#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */
+#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */
+#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */
+#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */
+#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */
+#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */
+#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */
+
+#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */
+#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */
+
+/** \brief PMU Software Increment Counter */
+
+#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */
+#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */
+
+#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */
+#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */
+
+#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */
+#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */
+
+#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */
+#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */
+
+#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */
+#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */
+
+#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */
+#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */
+
+#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */
+#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */
+
+#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */
+#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */
+
+#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */
+#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */
+
+#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */
+#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */
+
+#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */
+#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */
+
+#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */
+#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */
+
+#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */
+#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */
+
+#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */
+#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */
+
+#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */
+#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */
+
+#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */
+#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */
+
+#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */
+#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */
+
+#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */
+#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */
+
+#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */
+#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */
+
+#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */
+#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */
+
+#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */
+#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */
+
+#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */
+#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */
+
+#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */
+#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */
+
+#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */
+#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */
+
+#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */
+#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */
+
+#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */
+#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */
+
+#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */
+#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */
+
+#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */
+#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */
+
+#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */
+#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */
+
+#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */
+#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */
+
+#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */
+#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */
+
+/** \brief PMU Control Register Definitions */
+
+#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */
+#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */
+
+#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */
+#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */
+
+#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */
+#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */
+
+#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */
+#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */
+
+#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */
+#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */
+
+#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */
+#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */
+
+/** \brief PMU Type Register Definitions */
+
+#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */
+#define PMU_TYPE_NUM_CNTS_Msk (8UL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */
+
+#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */
+#define PMU_TYPE_SIZE_CNTS_Msk (6UL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */
+
+#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */
+#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */
+
+#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */
+#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */
+
+#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */
+#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */
+
+/*@} end of group CMSIS_PMU */
+#endif
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
+ uint32_t RESERVED0[1];
+ union {
+ __IOM uint32_t MAIR[2];
+ struct {
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
+ };
+ };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */
+#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */
+
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)
+ \brief Type definitions for the Security Attribution Unit (SAU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
+#else
+ uint32_t RESERVED0[3];
+#endif
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */
+#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */
+
+#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */
+#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */
+
+/* Media and VFP Feature Register 0 Definitions */
+#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */
+#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */
+
+#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */
+#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */
+
+#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */
+#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */
+#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */
+
+#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */
+#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */
+
+#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */
+#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */
+
+/* Media and VFP Feature Register 1 Definitions */
+#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */
+#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */
+
+#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */
+#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */
+
+#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */
+#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */
+
+#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */
+#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */
+
+#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */
+#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */
+
+#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */
+#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */
+
+/* Media and VFP Feature Register 2 Definitions */
+#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
+#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */
+#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */
+
+#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */
+#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */
+
+#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */
+#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */
+
+#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */
+#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */
+#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Set Clear Exception and Monitor Control Register Definitions */
+#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */
+#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */
+
+#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */
+#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */
+
+#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */
+#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */
+
+#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */
+#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */
+#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */
+#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */
+#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DCB Debug Control Block
+ \brief Type definitions for the Debug Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Control Block Registers (DCB).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+ __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
+} DCB_Type;
+
+/* DHCSR, Debug Halting Control and Status Register Definitions */
+#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
+#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
+
+#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
+#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
+
+#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
+#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
+
+#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
+#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
+
+#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */
+#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */
+
+#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */
+#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */
+
+#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */
+#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */
+
+#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
+#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
+
+#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
+#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
+
+#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
+#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
+
+#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
+#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
+
+#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
+#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
+
+#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */
+#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */
+
+#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
+#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
+
+#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
+#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
+
+#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
+#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
+
+#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
+#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
+
+#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
+#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
+
+/* DCRSR, Debug Core Register Select Register Definitions */
+#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
+#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
+
+#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
+#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
+
+/* DCRDR, Debug Core Register Data Register Definitions */
+#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
+#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
+
+/* DEMCR, Debug Exception and Monitor Control Register Definitions */
+#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
+#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
+
+#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
+#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
+
+#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
+#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
+
+#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
+#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
+
+#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
+#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
+
+#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
+#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
+
+#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
+#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
+
+#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
+#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
+
+#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
+#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
+
+#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
+#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
+
+#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
+#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
+
+#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
+#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
+
+#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
+#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
+
+#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
+#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
+
+#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
+#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
+
+#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
+#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
+
+#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
+#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
+
+/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */
+#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */
+#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */
+
+#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */
+#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */
+
+#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */
+#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */
+
+#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */
+#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */
+
+/* DAUTHCTRL, Debug Authentication Control Register Definitions */
+#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */
+#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */
+
+#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */
+#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */
+
+#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */
+#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */
+
+#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
+
+#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
+#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
+
+#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
+#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
+
+/* DSCSR, Debug Security Control and Status Register Definitions */
+#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
+#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
+
+#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
+#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
+
+#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
+#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
+
+#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
+#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
+
+/*@} end of group CMSIS_DCB */
+
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DIB Debug Identification Block
+ \brief Type definitions for the Debug Identification Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Debug Identification Block Registers (DIB).
+ */
+typedef struct
+{
+ __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
+ __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
+ __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
+ __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
+ __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
+} DIB_Type;
+
+/* DLAR, SCS Software Lock Access Register Definitions */
+#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
+#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
+
+/* DLSR, SCS Software Lock Status Register Definitions */
+#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
+#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
+
+#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
+#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
+
+#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
+#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
+
+/* DAUTHSTATUS, Debug Authentication Status Register Definitions */
+#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */
+#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */
+
+#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */
+#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */
+
+#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
+
+#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
+#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
+
+/* DDEVARCH, SCS Device Architecture Register Definitions */
+#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
+#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
+
+#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
+#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
+
+#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
+#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
+
+#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
+#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
+
+#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
+#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
+
+/* DDEVTYPE, SCS Device Type Register Definitions */
+#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
+#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
+
+#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
+#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
+
+
+/*@} end of group CMSIS_DIB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
+ #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
+ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
+ #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
+ #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+ #endif
+
+ #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+ #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */
+ #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */
+ #endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
+ #endif
+
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
+ #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
+ #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
+
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
+ #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
+ #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
+
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
+ #endif
+
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
+#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
+#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
+#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
+#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
+#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
+#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
+#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
+#else
+#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
+#endif
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Interrupt Target State
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ \return 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Target State
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Clear Interrupt Target State
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 if interrupt is assigned to Secure
+ 1 if interrupt is assigned to Non Secure
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Grouping (non-secure)
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB_NS->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping (non-secure)
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt (non-secure)
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status (non-secure)
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt (non-secure)
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt (non-secure)
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt (non-secure)
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt (non-secure)
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt (non-secure)
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority (non-secure)
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority (non-secure)
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ########################## PMU functions and events #################################### */
+
+#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)
+
+#include "pmu_armv8.h"
+
+/**
+ \brief Cortex-M55 PMU events
+ \note Architectural PMU events can be found in pmu_armv8.h
+*/
+
+#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */
+#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */
+#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */
+#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */
+#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */
+#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/
+#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */
+#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */
+#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */
+#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */
+#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */
+#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */
+#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */
+#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */
+#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */
+#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */
+#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */
+#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */
+
+#endif
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+/* ########################## MVE functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_MveFunctions MVE Functions
+ \brief Function that provides MVE type.
+ @{
+ */
+
+/**
+ \brief get MVE type
+ \details returns the MVE type
+ \returns
+ - \b 0: No Vector Extension (MVE)
+ - \b 1: Integer Vector Extension (MVE-I)
+ - \b 2: Floating-point Vector Extension (MVE-F)
+ */
+__STATIC_INLINE uint32_t SCB_GetMVEType(void)
+{
+ const uint32_t mvfr1 = FPU->MVFR1;
+ if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos))
+ {
+ return 2U;
+ }
+ else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos))
+ {
+ return 1U;
+ }
+ else
+ {
+ return 0U;
+ }
+}
+
+
+/*@} end of CMSIS_Core_MveFunctions */
+
+
+/* ########################## Cache functions #################################### */
+
+#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
+ (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
+#include "cachel1_armv7.h"
+#endif
+
+
+/* ########################## SAU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions
+ \brief Functions that configure the SAU.
+ @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ \brief Enable SAU
+ \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+ \brief Disable SAU
+ \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ################################## Debug Control function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
+ \brief Functions that access the Debug Control Block.
+ @{
+ */
+
+
+/**
+ \brief Set Debug Authentication Control Register
+ \details writes to Debug Authentication Control register.
+ \param [in] value value to be writen.
+ */
+__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register
+ \details Reads Debug Authentication Control register.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
+{
+ return (DCB->DAUTHCTRL);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Debug Authentication Control Register (non-secure)
+ \details writes to non-secure Debug Authentication Control register when in secure state.
+ \param [in] value value to be writen
+ */
+__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
+{
+ __DSB();
+ __ISB();
+ DCB_NS->DAUTHCTRL = value;
+ __DSB();
+ __ISB();
+}
+
+
+/**
+ \brief Get Debug Authentication Control Register (non-secure)
+ \details Reads non-secure Debug Authentication Control register when in secure state.
+ \return Debug Authentication Control Register.
+ */
+__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
+{
+ return (DCB_NS->DAUTHCTRL);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## Debug Identification function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
+ \brief Functions that access the Debug Identification Block.
+ @{
+ */
+
+
+/**
+ \brief Get Debug Authentication Status Register
+ \details Reads Debug Authentication Status register.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
+{
+ return (DIB->DAUTHSTATUS);
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Debug Authentication Status Register (non-secure)
+ \details Reads non-secure Debug Authentication Status register when in secure state.
+ \return Debug Authentication Status Register.
+ */
+__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
+{
+ return (DIB_NS->DAUTHSTATUS);
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_DCBFunctions */
+
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief System Tick Configuration (non-secure)
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM55_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm7.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm7.h
new file mode 100644
index 0000000000..e1c31c275d
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm7.h
@@ -0,0 +1,2362 @@
+/**************************************************************************//**
+ * @file core_cm7.h
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version V5.1.2
+ * @date 27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M7
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+ __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (7U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM7_REV
+ #define __CM7_REV 0x0000U
+ #warning "__CM7_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ICACHE_PRESENT
+ #define __ICACHE_PRESENT 0U
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DCACHE_PRESENT
+ #define __DCACHE_PRESENT 0U
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DTCM_PRESENT
+ #define __DTCM_PRESENT 0U
+ #warning "__DTCM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[1U];
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED3[93U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */
+#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */
+
+#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */
+#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */
+
+#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */
+#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */
+
+#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */
+#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */
+
+#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */
+#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */
+
+#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */
+#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */
+
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED3[981U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
+#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ __DSB();
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = SCB->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+ {
+ return 2U; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+/* ########################## Cache functions #################################### */
+
+#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
+ (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
+#include "cachel1_armv7.h"
+#endif
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_sc000.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_sc000.h
new file mode 100644
index 0000000000..dbc755fff3
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_sc000.h
@@ -0,0 +1,1030 @@
+/**************************************************************************//**
+ * @file core_sc000.h
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version V5.0.7
+ * @date 27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC000
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+ __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC (000U) /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC000_REV
+ #define __SC000_REV 0x0000U
+ #warning "__SC000_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ uint32_t RESERVED1[154U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the SC000 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_sc300.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_sc300.h
new file mode 100644
index 0000000000..e8914ba601
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_sc300.h
@@ -0,0 +1,1917 @@
+/**************************************************************************//**
+ * @file core_sc300.h
+ * @brief CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version V5.0.9
+ * @date 27. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC3000
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+ __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC (300U) /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC300_REV
+ #define __SC300_REV 0x0000U
+ #warning "__SC300_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED1[129U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M3 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ return 0U; /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/mpu_armv7.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/mpu_armv7.h
new file mode 100644
index 0000000000..791a8dae65
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/mpu_armv7.h
@@ -0,0 +1,275 @@
+/******************************************************************************
+ * @file mpu_armv7.h
+ * @brief CMSIS MPU API for Armv7-M MPU
+ * @version V5.1.1
+ * @date 10. February 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
+ ((Region) & MPU_RBAR_REGION_Msk) | \
+ (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+*
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
+ ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
+ (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
+ (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
+ (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
+ ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
+ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
+ (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
+ (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
+ (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
+ (((MPU_RASR_ENABLE_Msk))))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+* - TEX: 000b
+* - Shareable
+* - Non-cacheable
+* - Non-bufferable
+*/
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+* - TEX: 000b (if shareable) or 010b (if non-shareable)
+* - Shareable or non-shareable
+* - Non-cacheable
+* - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+* - TEX: 1BBb (reflecting outer cacheability rules)
+* - Shareable or non-shareable
+* - Cacheable or non-cacheable (reflecting inner cacheability rules)
+* - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; //!< The region base address register value (RBAR)
+ uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ __DMB();
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ __DSB();
+ __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+ __DSB();
+ __ISB();
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ MPU->RNR = rnr;
+ MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+ MPU->RNR = rnr;
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ while (cnt > MPU_TYPE_RALIASES) {
+ ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+ table += MPU_TYPE_RALIASES;
+ cnt -= MPU_TYPE_RALIASES;
+ }
+ ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/mpu_armv8.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/mpu_armv8.h
new file mode 100644
index 0000000000..ef44ad01df
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/mpu_armv8.h
@@ -0,0 +1,352 @@
+/******************************************************************************
+ * @file mpu_armv8.h
+ * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
+ * @version V5.1.2
+ * @date 10. February 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+ ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable */
+#define ARM_MPU_SH_NON (0U)
+
+/** \brief Normal memory outer shareable */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+ (((BASE) & MPU_RBAR_BASE_Msk) | \
+ (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+ (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+ (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+ (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+ (MPU_RLAR_EN_Msk))
+
+#if defined(MPU_RLAR_PXN_Pos)
+
+/** \brief Region Limit Address Register with PXN value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
+ (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+ (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
+ (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+ (MPU_RLAR_EN_Msk))
+
+#endif
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; /*!< Region Base Address Register value */
+ uint32_t RLAR; /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ __DMB();
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ __DSB();
+ __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+ __DSB();
+ __ISB();
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+ __DMB();
+ MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ __DSB();
+ __ISB();
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+ __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+ __DSB();
+ __ISB();
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+ const uint8_t reg = idx / 4U;
+ const uint32_t pos = ((idx % 4U) * 8U);
+ const uint32_t mask = 0xFFU << pos;
+
+ if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+ return; // invalid index
+ }
+
+ mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+ ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+ ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+ mpu->RNR = rnr;
+ mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{
+ ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ mpu->RNR = rnr;
+ mpu->RBAR = rbar;
+ mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ if (cnt == 1U) {
+ mpu->RNR = rnr;
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+ } else {
+ uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
+ uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+
+ mpu->RNR = rnrBase;
+ while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+ uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+ table += c;
+ cnt -= c;
+ rnrOffset = 0U;
+ rnrBase += MPU_TYPE_RALIASES;
+ mpu->RNR = rnrBase;
+ }
+
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/pmu_armv8.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/pmu_armv8.h
new file mode 100644
index 0000000000..dbd39d20c7
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/pmu_armv8.h
@@ -0,0 +1,337 @@
+/******************************************************************************
+ * @file pmu_armv8.h
+ * @brief CMSIS PMU API for Armv8.1-M PMU
+ * @version V1.0.0
+ * @date 24. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_PMU_ARMV8_H
+#define ARM_PMU_ARMV8_H
+
+/**
+ * \brief PMU Events
+ * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
+ * */
+
+#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
+#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */
+#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */
+#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */
+#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */
+#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */
+#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */
+#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */
+#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */
+#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
+#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */
+#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */
+#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
+#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */
+#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */
+#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */
+#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */
+#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */
+#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */
+#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */
+#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */
+#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */
+#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */
+#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */
+#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */
+#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */
+#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
+#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */
+#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */
+#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */
+#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */
+#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */
+#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */
+#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */
+#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */
+#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */
+#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */
+#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */
+#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */
+#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */
+#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */
+#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */
+#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */
+#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */
+#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */
+#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
+#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
+#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */
+#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */
+#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */
+#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */
+#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */
+#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */
+#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */
+#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */
+#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */
+#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */
+#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */
+#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */
+#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */
+#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */
+#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */
+#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */
+#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */
+#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */
+#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */
+#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */
+#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */
+#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */
+#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
+#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
+#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */
+#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */
+#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
+#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */
+#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */
+#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */
+#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */
+#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */
+#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
+#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */
+#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */
+#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */
+#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */
+#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */
+#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */
+#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */
+#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */
+#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
+#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
+#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
+#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
+#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */
+#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */
+#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */
+#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */
+#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */
+#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */
+#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */
+#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */
+#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */
+#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */
+#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */
+#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */
+
+/** \brief PMU Functions */
+
+__STATIC_INLINE void ARM_PMU_Enable(void);
+__STATIC_INLINE void ARM_PMU_Disable(void);
+
+__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
+
+__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
+__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
+
+__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
+__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
+
+__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
+__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
+
+__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
+__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
+
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
+
+__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
+
+/**
+ \brief Enable the PMU
+*/
+__STATIC_INLINE void ARM_PMU_Enable(void)
+{
+ PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
+}
+
+/**
+ \brief Disable the PMU
+*/
+__STATIC_INLINE void ARM_PMU_Disable(void)
+{
+ PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
+}
+
+/**
+ \brief Set event to count for PMU eventer counter
+ \param [in] num Event counter (0-30) to configure
+ \param [in] type Event to count
+*/
+__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
+{
+ PMU->EVTYPER[num] = type;
+}
+
+/**
+ \brief Reset cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
+{
+ PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
+}
+
+/**
+ \brief Reset all event counters
+*/
+__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
+{
+ PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
+}
+
+/**
+ \brief Enable counters
+ \param [in] mask Counters to enable
+ \note Enables one or more of the following:
+ - event counters (0-30)
+ - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
+{
+ PMU->CNTENSET = mask;
+}
+
+/**
+ \brief Disable counters
+ \param [in] mask Counters to enable
+ \note Disables one or more of the following:
+ - event counters (0-30)
+ - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
+{
+ PMU->CNTENCLR = mask;
+}
+
+/**
+ \brief Read cycle counter
+ \return Cycle count
+*/
+__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
+{
+ return PMU->CCNTR;
+}
+
+/**
+ \brief Read event counter
+ \param [in] num Event counter (0-30) to read
+ \return Event count
+*/
+__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
+{
+ return PMU->EVCNTR[num];
+}
+
+/**
+ \brief Read counter overflow status
+ \return Counter overflow status bits for the following:
+ - event counters (0-30)
+ - cycle counter
+*/
+__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
+{
+ return PMU->OVSSET;
+}
+
+/**
+ \brief Clear counter overflow status
+ \param [in] mask Counter overflow status bits to clear
+ \note Clears overflow status bits for one or more of the following:
+ - event counters (0-30)
+ - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
+{
+ PMU->OVSCLR = mask;
+}
+
+/**
+ \brief Enable counter overflow interrupt request
+ \param [in] mask Counter overflow interrupt request bits to set
+ \note Sets overflow interrupt request bits for one or more of the following:
+ - event counters (0-30)
+ - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
+{
+ PMU->INTENSET = mask;
+}
+
+/**
+ \brief Disable counter overflow interrupt request
+ \param [in] mask Counter overflow interrupt request bits to clear
+ \note Clears overflow interrupt request bits for one or more of the following:
+ - event counters (0-30)
+ - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
+{
+ PMU->INTENCLR = mask;
+}
+
+/**
+ \brief Software increment event counter
+ \param [in] mask Counters to increment
+ \note Software increment bits for one or more event counters (0-30)
+*/
+__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
+{
+ PMU->SWINC = mask;
+}
+
+#endif
diff --git a/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/tz_context.h b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/tz_context.h
new file mode 100644
index 0000000000..0d09749f3a
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/tz_context.h
@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file tz_context.h
+ * @brief Context Management for Armv8-M TrustZone
+ * @version V1.0.1
+ * @date 10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+
+#include
+
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in] module identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0 no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in] id TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+
+#endif // TZ_CONTEXT_H
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll.h
new file mode 100644
index 0000000000..f3a6a01670
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll.h
@@ -0,0 +1,343 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll.h
+ * @brief This file contains HC32 Series Device Driver Library file call
+ * management.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2022-11-02 CDT Modify version as 1.1.0
+ 2023-06-30 CDT Modify version as 1.2.0
+ 2023-09-30 CDT Modify version as 1.2.1
+ 2023-12-15 CDT Modify version as 1.3.0
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_H__
+#define __HC32_LL_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_Global
+ * @{
+ */
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup LL_Global_Macros LL Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup Peripheral_Register_WP_Global_Macros Peripheral Register Write Protection Global Macros
+ * @{
+ */
+#define LL_PERIPH_EFM (1UL << 0U)
+#define LL_PERIPH_FCG (1UL << 1U)
+#define LL_PERIPH_GPIO (1UL << 2U)
+#define LL_PERIPH_INTC (1UL << 3U)
+#define LL_PERIPH_LVD (1UL << 4U)
+#define LL_PERIPH_MPU (1UL << 5U)
+#define LL_PERIPH_PWC_CLK_RMU (1UL << 6U)
+#define LL_PERIPH_SRAM (1UL << 7U)
+#define LL_PERIPH_ALL (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_GPIO | LL_PERIPH_INTC | \
+ LL_PERIPH_LVD | LL_PERIPH_MPU | LL_PERIPH_SRAM | LL_PERIPH_PWC_CLK_RMU)
+/**
+ * @}
+ */
+
+/* Defined use Device Driver Library */
+#if !defined (USE_DDL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the Device Driver Library.
+ * In this case, the application code will be based on direct access to
+ * peripherals registers.
+ */
+/* #define USE_DDL_DRIVER */
+#endif /* USE_DDL_DRIVER */
+
+/**
+* @defgroup HC32_Series_DDL_Release_Version HC32 Series DDL Release Version
+* @{
+*/
+#define HC32_DDL_REV_MAIN 0x01U /*!< [31:24] main version */
+#define HC32_DDL_REV_SUB1 0x03U /*!< [23:16] sub1 version */
+#define HC32_DDL_REV_SUB2 0x00U /*!< [15:8] sub2 version */
+#define HC32_DDL_REV_PATCH 0x00U /*!< [7:0] patch version */
+#define HC32_DDL_REV ((HC32_DDL_REV_MAIN << 24) | (HC32_DDL_REV_SUB1 << 16) | \
+ (HC32_DDL_REV_SUB2 << 8 ) | (HC32_DDL_REV_PATCH))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Use Device Driver Library */
+#if defined (USE_DDL_DRIVER)
+
+/**
+ * @brief Include peripheral module's header file
+ */
+#if (LL_ADC_ENABLE == DDL_ON)
+#include "hc32_ll_adc.h"
+#endif /* LL_ADC_ENABLE */
+
+#if (LL_AES_ENABLE == DDL_ON)
+#include "hc32_ll_aes.h"
+#endif /* LL_AES_ENABLE */
+
+#if (LL_AOS_ENABLE == DDL_ON)
+#include "hc32_ll_aos.h"
+#endif /* LL_AOS_ENABLE */
+
+#if (LL_CAN_ENABLE == DDL_ON)
+#include "hc32_ll_can.h"
+#endif /* LL_CAN_ENABLE */
+
+#if (LL_CLK_ENABLE == DDL_ON)
+#include "hc32_ll_clk.h"
+#endif /* LL_CLK_ENABLE */
+
+#if (LL_CMP_ENABLE == DDL_ON)
+#include "hc32_ll_cmp.h"
+#endif /* LL_CMP_ENABLE */
+
+#if (LL_CRC_ENABLE == DDL_ON)
+#include "hc32_ll_crc.h"
+#endif /* LL_CRC_ENABLE */
+
+#if (LL_CTC_ENABLE == DDL_ON)
+#include "hc32_ll_ctc.h"
+#endif /* LL_CTC_ENABLE */
+
+#if (LL_DAC_ENABLE == DDL_ON)
+#include "hc32_ll_dac.h"
+#endif /* LL_DAC_ENABLE */
+
+#if (LL_DBGC_ENABLE == DDL_ON)
+#include "hc32_ll_dbgc.h"
+#endif /* LL_DBGC_ENABLE */
+
+#if (LL_DCU_ENABLE == DDL_ON)
+#include "hc32_ll_dcu.h"
+#endif /* LL_DCU_ENABLE */
+
+#if (LL_DMA_ENABLE == DDL_ON)
+#include "hc32_ll_dma.h"
+#endif /* LL_DMA_ENABLE */
+
+#if (LL_EFM_ENABLE == DDL_ON)
+#include "hc32_ll_efm.h"
+#endif /* LL_EFM_ENABLE */
+
+#if (LL_EMB_ENABLE == DDL_ON)
+#include "hc32_ll_emb.h"
+#endif /* LL_EMB_ENABLE */
+
+#if (LL_EVENT_PORT_ENABLE == DDL_ON)
+#include "hc32_ll_event_port.h"
+#endif /* LL_EVENT_PORT_ENABLE */
+
+#if (LL_FCG_ENABLE == DDL_ON)
+#include "hc32_ll_fcg.h"
+#endif /* LL_FCG_ENABLE */
+
+#if (LL_FCM_ENABLE == DDL_ON)
+#include "hc32_ll_fcm.h"
+#endif /* LL_FCM_ENABLE */
+
+#if (LL_FMAC_ENABLE == DDL_ON)
+#include "hc32_ll_fmac.h"
+#endif /* LL_FMAC_ENABLE */
+
+#if (LL_GPIO_ENABLE == DDL_ON)
+#include "hc32_ll_gpio.h"
+#endif /* LL_GPIO_ENABLE */
+
+#if (LL_HASH_ENABLE == DDL_ON)
+#include "hc32_ll_hash.h"
+#endif /* LL_HASH_ENABLE */
+
+#if (LL_I2C_ENABLE == DDL_ON)
+#include "hc32_ll_i2c.h"
+#endif /* LL_I2C_ENABLE */
+
+#if (LL_ICG_ENABLE == DDL_ON)
+#include "hc32_ll_icg.h"
+#endif /* LL_ICG_ENABLE */
+
+#if (LL_INTERRUPTS_ENABLE == DDL_ON)
+#include "hc32_ll_interrupts.h"
+#endif /* LL_INTERRUPTS_ENABLE */
+
+#if (LL_KEYSCAN_ENABLE == DDL_ON)
+#include "hc32_ll_keyscan.h"
+#endif /* LL_KEYSCAN_ENABLE */
+
+#if (LL_MAU_ENABLE == DDL_ON)
+#include "hc32_ll_mau.h"
+#endif /* LL_MAU_ENABLE */
+
+#if (LL_MDIO_ENABLE == DDL_ON)
+#include "hc32_ll_mdio.h"
+#endif /* LL_MDIO_ENABLE */
+
+#if (LL_MPU_ENABLE == DDL_ON)
+#include "hc32_ll_mpu.h"
+#endif /* LL_MPU_ENABLE */
+
+#if (LL_OTS_ENABLE == DDL_ON)
+#include "hc32_ll_ots.h"
+#endif /* LL_OTS_ENABLE */
+
+#if (LL_PWC_ENABLE == DDL_ON)
+#include "hc32_ll_pwc.h"
+#endif /* LL_PWC_ENABLE */
+
+#if (LL_PLA_ENABLE == DDL_ON)
+#include "hc32_ll_pla.h"
+#endif /* LL_PLA_ENABLE */
+
+#if (LL_QSPI_ENABLE == DDL_ON)
+#include "hc32_ll_qspi.h"
+#endif /* LL_QSPI_ENABLE */
+
+#if (LL_RMU_ENABLE == DDL_ON)
+#include "hc32_ll_rmu.h"
+#endif /* LL_RMU_ENABLE */
+
+#if (LL_RTC_ENABLE == DDL_ON)
+#include "hc32_ll_rtc.h"
+#endif /* LL_RTC_ENABLE */
+
+#if (LL_SMC_ENABLE == DDL_ON)
+#include "hc32_ll_smc.h"
+#endif /* LL_SMC_ENABLE */
+
+#if (LL_SPI_ENABLE == DDL_ON)
+#include "hc32_ll_spi.h"
+#endif /* LL_SPI_ENABLE */
+
+#if (LL_SRAM_ENABLE == DDL_ON)
+#include "hc32_ll_sram.h"
+#endif /* LL_SRAM_ENABLE */
+
+#if (LL_SWDT_ENABLE == DDL_ON)
+#include "hc32_ll_swdt.h"
+#endif /* LL_SWDT_ENABLE */
+
+#if (LL_TMR0_ENABLE == DDL_ON)
+#include "hc32_ll_tmr0.h"
+#endif /* LL_TMR0_ENABLE */
+
+#if (LL_TMR2_ENABLE == DDL_ON)
+#include "hc32_ll_tmr2.h"
+#endif /* LL_TMR2_ENABLE */
+
+#if (LL_TMR4_ENABLE == DDL_ON)
+#include "hc32_ll_tmr4.h"
+#endif /* LL_TMR4_ENABLE */
+
+#if (LL_TMR6_ENABLE == DDL_ON)
+#include "hc32_ll_tmr6.h"
+#endif /* LL_TMR6_ENABLE */
+
+#if (LL_TMRA_ENABLE == DDL_ON)
+#include "hc32_ll_tmra.h"
+#endif /* LL_TMRA_ENABLE */
+
+#if (LL_TRNG_ENABLE == DDL_ON)
+#include "hc32_ll_trng.h"
+#endif /* LL_TRNG_ENABLE */
+
+#if (LL_USART_ENABLE == DDL_ON)
+#include "hc32_ll_usart.h"
+#endif /* LL_USART_ENABLE */
+
+#if (LL_UTILITY_ENABLE == DDL_ON)
+#include "hc32_ll_utility.h"
+#endif /* LL_UTILITY_ENABLE */
+
+#if (LL_USB_ENABLE == DDL_ON)
+#include "hc32_ll_usb.h"
+#endif /* LL_USB_ENABLE */
+
+#if (LL_VREF_ENABLE == DDL_ON)
+#include "hc32_ll_vref.h"
+#endif /* LL_VREF_ENABLE */
+
+#if (LL_WDT_ENABLE == DDL_ON)
+#include "hc32_ll_wdt.h"
+#endif /* LL_WDT_ENABLE */
+
+#endif /* USE_DDL_DRIVER */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup LL_Global_Functions
+ * @{
+ */
+void LL_PERIPH_WE(uint32_t u32Peripheral);
+void LL_PERIPH_WP(uint32_t u32Peripheral);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_DDL_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_adc.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_adc.h
new file mode 100644
index 0000000000..41a0dcae2f
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_adc.h
@@ -0,0 +1,567 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_adc.h
+ * @brief This file contains all the functions prototypes of the ADC driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Modify typo
+ API fixed: ADC_DeInit()
+ 2023-12-15 CDT Add declaration of API ADC_MxChCmd(), ADC_ConvDataAverageMxChCmd(), and add defgroup ADC_Mx_Channel
+ Add declaration of API ADC_GetResolution()
+ Add note for group ADC_PGA_VSS
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_ADC_H__
+#define __HC32_LL_ADC_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_ADC
+ * @{
+ */
+
+#if (LL_ADC_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup ADC_Global_Types ADC Global Types
+ * @{
+ */
+/**
+ * @brief Structure definition of analog watchdog(AWD) configuration.
+ */
+typedef struct {
+ uint16_t u16WatchdogMode; /*!< Specifies the ADC analog watchdog mode.
+ This parameter can be a value of @ref ADC_AWD_Mode */
+ uint16_t u16LowThreshold; /*!< Specifies the ADC analog watchdog Low threshold value. */
+ uint16_t u16HighThreshold; /*!< Specifies the ADC analog watchdog High threshold value. */
+} stc_adc_awd_config_t;
+
+/**
+ * @brief Structure definition of ADC initialization.
+ */
+typedef struct {
+ uint16_t u16ScanMode; /*!< Specifies the ADC scan convert mode.
+ This parameter can be a value of @ref ADC_Scan_Mode */
+ uint16_t u16Resolution; /*!< Specifies the ADC resolution.
+ This parameter can be a value of @ref ADC_Resolution */
+ uint16_t u16DataAlign; /*!< Specifies ADC data alignment.
+ This parameter can be a value of @ref ADC_Data_Align */
+} stc_adc_init_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup ADC_Global_Macros ADC Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup ADC_Sequence ADC Sequence
+ * @{
+ */
+#define ADC_SEQ_A (0U) /*!< ADC sequence A. */
+#define ADC_SEQ_B (1U) /*!< ADC sequence B. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_Channel ADC Channel
+ * @{
+ */
+/**
+ * @note HC32F472JCTI/HC32F472JETI/HC32F472PCTI/HC32F472PETI: ADC1 can NOT use PB2, PB12, PB13, PB14
+ * ADC2 can NOT use PB12, PB13, PB14, PB15
+ * ADC3 can NOT use PB0, PB1, PC4, PC5, PB2
+ */
+#define ADC_CH0 (0U) /*!< Default input pin: PA0 for ADC1, ADC2 and ADC3. */
+#define ADC_CH1 (1U) /*!< Default input pin: PA1 for ADC1, ADC2 and ADC3. */
+#define ADC_CH2 (2U) /*!< Default input pin: PA2 for ADC1, ADC2 and ADC3. */
+#define ADC_CH3 (3U) /*!< Default input pin: PA3 for ADC1, ADC2 and ADC3. */
+#define ADC_CH4 (4U) /*!< Default input pin: PA4 for ADC1 and ADC2, PA8 for ADC3. */
+#define ADC_CH5 (5U) /*!< Default input pin: PA5 for ADC1 and ADC2, PA9 for ADC3. */
+#define ADC_CH6 (6U) /*!< Default input pin: PA6 for ADC1 and ADC2, PA10 for ADC3. */
+#define ADC_CH7 (7U) /*!< Default input pin: PA7 for ADC1 and ADC2, PA11 for ADC3. */
+#define ADC_CH8 (8U) /*!< Default input pin: PB0 for ADC1, ADC2 and ADC3. */
+#define ADC_CH9 (9U) /*!< Default input pin: PB1 for ADC1, ADC2 and ADC3. */
+#define ADC_CH10 (10U) /*!< Default input pin: PC0 for ADC1, ADC2 and ADC3. */
+#define ADC_CH11 (11U) /*!< Default input pin: PC1 for ADC1, ADC2 and ADC3. */
+#define ADC_CH12 (12U) /*!< Default input pin: PC2 for ADC1, ADC2 and ADC3. */
+#define ADC_CH13 (13U) /*!< Default input pin: PC3 for ADC1, ADC2 and ADC3. */
+#define ADC_CH14 (14U) /*!< Default input pin: PC4 for ADC1 and ADC2, PF4 for ADC3. */
+#define ADC_CH15 (15U) /*!< Default input pin: PC5 for ADC1 and ADC2, PF5 for ADC3. */
+#define ADC_CH16 (16U) /*!< Input pin: PB2 for ADC1, ADC2 and ADC3. */
+#define ADC_CH17 (17U) /*!< Input pin: PB12 for ADC1 and ADC2, PA12 for ADC3. */
+#define ADC_CH18 (18U) /*!< Input pin: PB13 for ADC1 and ADC2, PA15 for ADC3. */
+#define ADC_CH19 (19U) /*!< Input pin: PB14 for ADC1 and ADC2, PB3 for ADC3. */
+#define ADC_CH20 (20U) /*!< Input pin: PB15 for ADC1 and ADC2, PB4 for ADC3. */
+#define ADC_CH21 (21U) /*!< Input analog source:
+ ADC1: Internal reference voltage(ADVREF).
+ ADC2: Internal reference voltage(ADVREF).
+ ADC3: PB5. */
+#define ADC_CH22 (22U) /*!< Input analog source:
+ ADC1: CMP reference voltage(VREFINT).
+ ADC2: CMP reference voltage(VREFINT).
+ ADC3: Internal reference voltage(ADVREF). */
+#define ADC_CH23 (23U) /*!< Input analog source:
+ ADC1: Divided voltage of AVCC(AVCCDIVMON).
+ ADC2: Divided voltage of AVCC(AVCCDIVMON).
+ ADC3: CMP reference voltage(VREFINT). */
+#define ADC_CH24 (24U) /*!< Input analog source:
+ ADC1: NOT supported.
+ ADC2: NOT supported.
+ ADC3: Divider of AVCC(AVCCDIVMON). */
+#define ADC1_CH_ADVREF ADC_CH21
+#define ADC2_CH_ADVREF ADC_CH21
+#define ADC3_CH_ADVREF ADC_CH22
+
+#define ADC1_CH_VREFINT ADC_CH22
+#define ADC2_CH_VREFINT ADC_CH22
+#define ADC3_CH_VREFINT ADC_CH23
+
+#define ADC1_CH_AVCCDIV ADC_CH23
+#define ADC2_CH_AVCCDIV ADC_CH23
+#define ADC3_CH_AVCCDIV ADC_CH24
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_Mx_Channel ADC Channel
+ * @{
+ */
+#define ADC_MX_CH0 (1U << 0U) /*!< ADC channel 0 position */
+#define ADC_MX_CH1 (1U << 1U) /*!< ADC channel 1 position */
+#define ADC_MX_CH2 (1U << 2U) /*!< ADC channel 2 position */
+#define ADC_MX_CH3 (1U << 3U) /*!< ADC channel 3 position */
+#define ADC_MX_CH4 (1U << 4U) /*!< ADC channel 4 position */
+#define ADC_MX_CH5 (1U << 5U) /*!< ADC channel 5 position */
+#define ADC_MX_CH6 (1U << 6U) /*!< ADC channel 6 position */
+#define ADC_MX_CH7 (1U << 7U) /*!< ADC channel 7 position */
+#define ADC_MX_CH8 (1U << 8U) /*!< ADC channel 8 position */
+#define ADC_MX_CH9 (1U << 9U) /*!< ADC channel 9 position */
+#define ADC_MX_CH10 (1U << 10U) /*!< ADC channel 10 position */
+#define ADC_MX_CH11 (1U << 11U) /*!< ADC channel 11 position */
+#define ADC_MX_CH12 (1U << 12U) /*!< ADC channel 12 position */
+#define ADC_MX_CH13 (1U << 13U) /*!< ADC channel 13 position */
+#define ADC_MX_CH14 (1U << 14U) /*!< ADC channel 14 position */
+#define ADC_MX_CH15 (1U << 15U) /*!< ADC channel 15 position */
+#define ADC_MX_CH16 (1U << 16U) /*!< ADC channel 16 position */
+#define ADC_MX_CH17 (1U << 17U) /*!< ADC channel 17 position */
+#define ADC_MX_CH18 (1U << 18U) /*!< ADC channel 18 position */
+#define ADC_MX_CH19 (1U << 19U) /*!< ADC channel 19 position */
+#define ADC_MX_CH20 (1U << 20U) /*!< ADC channel 20 position */
+#define ADC_MX_CH21 (1U << 21U) /*!< ADC channel 21 position */
+#define ADC_MX_CH22 (1U << 22U) /*!< ADC channel 22 position */
+#define ADC_MX_CH23 (1U << 23U) /*!< ADC channel 23 position */
+#define ADC_MX_CH24 (1U << 24U) /*!< ADC channel 24 position */
+
+#define ADC1_MX_CH_ALL (0xFFFFFFUL) /*!< ADC1 Channel mask position */
+#define ADC2_MX_CH_ALL (0xFFFFFFUL) /*!< ADC2 Channel mask position */
+#define ADC3_MX_CH_ALL (0x1FFFFFFUL) /*!< ADC3 Channel mask position */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_Scan_Mode ADC Scan Convert Mode
+ * @{
+ */
+#define ADC_MD_SEQA_SINGLESHOT (0x0U) /*!< Sequence A single shot. Sequence B is disabled. */
+#define ADC_MD_SEQA_CONT (0x1U << ADC_CR0_MS_POS) /*!< Sequence A continuous. Sequence B is disabled. */
+#define ADC_MD_SEQA_SEQB_SINGLESHOT (0x2U << ADC_CR0_MS_POS) /*!< Sequence A and B both single shot. */
+#define ADC_MD_SEQA_CONT_SEQB_SINGLESHOT (0x3U << ADC_CR0_MS_POS) /*!< Sequence A continuous and sequence B single shot. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_Resolution ADC Resolution
+ * @{
+ */
+#define ADC_RESOLUTION_12BIT (0x0U) /*!< Resolution is 12 bit. */
+#define ADC_RESOLUTION_10BIT (ADC_CR0_ACCSEL_0) /*!< Resolution is 10 bit. */
+#define ADC_RESOLUTION_8BIT (ADC_CR0_ACCSEL_1) /*!< Resolution is 8 bit. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_Data_Align ADC Data Align
+ * @{
+ */
+#define ADC_DATAALIGN_RIGHT (0x0U) /*!< Right alignment of converted data. */
+#define ADC_DATAALIGN_LEFT (ADC_CR0_DFMT) /*!< Left alignment of converted data. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_Average_Count ADC Average Count
+ * @{
+ */
+#define ADC_AVG_CNT2 (0x0U) /*!< 2 consecutive average conversions. */
+#define ADC_AVG_CNT4 (0x1U << ADC_CR0_AVCNT_POS) /*!< 4 consecutive average conversions. */
+#define ADC_AVG_CNT8 (0x2U << ADC_CR0_AVCNT_POS) /*!< 8 consecutive average conversions. */
+#define ADC_AVG_CNT16 (0x3U << ADC_CR0_AVCNT_POS) /*!< 16 consecutive average conversions. */
+#define ADC_AVG_CNT32 (0x4U << ADC_CR0_AVCNT_POS) /*!< 32 consecutive average conversions. */
+#define ADC_AVG_CNT64 (0x5U << ADC_CR0_AVCNT_POS) /*!< 64 consecutive average conversions. */
+#define ADC_AVG_CNT128 (0x6U << ADC_CR0_AVCNT_POS) /*!< 128 consecutive average conversions. */
+#define ADC_AVG_CNT256 (0x7U << ADC_CR0_AVCNT_POS) /*!< 256 consecutive average conversions. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_SeqA_Resume_Mode ADC Sequence A Resume Mode
+ * @brief After interrupted by sequence B, sequence A continues to scan from the interrupt channel or the first channel.
+ * @{
+ */
+#define ADC_SEQA_RESUME_SCAN_CONT (0U) /*!< Scanning will continue from the interrupted channel. */
+#define ADC_SEQA_RESUME_SCAN_RESTART (ADC_CR1_RSCHSEL) /*!< Scanning will start from the first channel. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_Hard_Trigger_Sel ADC Hard Trigger Selection
+ * @{
+ */
+#define ADC_HARDTRIG_ADTRG_PIN (0x0U) /*!< Selects the following edge of pin ADTRG as the trigger of ADC sequence. */
+#define ADC_HARDTRIG_EVT0 (ADC_TRGSR_TRGSELA_0) /*!< Selects an internal event as the trigger of ADC sequence.
+ This event is specified by register ADCx_TRGSEL0(x=(null), 1, 2, 3). */
+#define ADC_HARDTRIG_EVT1 (ADC_TRGSR_TRGSELA_1) /*!< Selects an internal event as the trigger of ADC sequence.
+ This event is specified by register ADCx_TRGSEL1(x=(null), 1, 2, 3). */
+#define ADC_HARDTRIG_EVT0_EVT1 (ADC_TRGSR_TRGSELA) /*!< Selects two internal events as the trigger of ADC sequence.
+ The two events are specified by register ADCx_TRGSEL0 and register ADCx_TRGSEL1. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_Int_Type ADC Interrupt Type
+ * @{
+ */
+#define ADC_INT_EOCA (ADC_ICR_EOCAIEN) /*!< Interrupt of the end of conversion of sequence A. */
+#define ADC_INT_EOCB (ADC_ICR_EOCBIEN) /*!< Interrupt of the end of conversion of sequence B. */
+#define ADC_INT_ALL (ADC_INT_EOCA | ADC_INT_EOCB)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_Status_Flag ADC Status Flag
+ * @{
+ */
+#define ADC_FLAG_EOCA (ADC_ISR_EOCAF) /*!< Status flag of the end of conversion of sequence A. */
+#define ADC_FLAG_EOCB (ADC_ISR_EOCBF) /*!< Status flag of the end of conversion of sequence B. */
+#define ADC_FLAG_NESTED (ADC_ISR_SASTPDF) /*!< Status flag of sequence A was interrupted by sequence B. */
+#define ADC_FLAG_ALL (ADC_FLAG_EOCA | ADC_FLAG_EOCB | ADC_FLAG_NESTED)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_Sync_Unit ADC Synchronous Unit
+ * @{
+ */
+#define ADC_SYNC_ADC1_ADC2 (0U) /*!< ADC1 and ADC2 work synchronously. */
+#define ADC_SYNC_ADC1_ADC2_ADC3 (0x1U << ADC_SYNCCR_SYNCMD_POS) /*!< ADC1, ADC2 and ADC3 work synchronously. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_Sync_Mode ADC Synchronous Mode
+ * @{
+ */
+#define ADC_SYNC_SINGLE_DELAY_TRIG (0U) /*!< Single shot delayed trigger mode.
+ When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has).
+ All ADCs scan once. */
+#define ADC_SYNC_SINGLE_PARALLEL_TRIG (0x2U << ADC_SYNCCR_SYNCMD_POS) /*!< Single shot parallel trigger mode.
+ When the trigger condition occurs, all ADCs start at the same time.
+ All ADCs scan once. */
+#define ADC_SYNC_CYCLIC_DELAY_TRIG (0x4U << ADC_SYNCCR_SYNCMD_POS) /*!< Cyclic delayed trigger mode.
+ When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has).
+ All ADCs scan cyclicly(keep scanning till you stop them). */
+#define ADC_SYNC_CYCLIC_PARALLEL_TRIG (0x6U << ADC_SYNCCR_SYNCMD_POS) /*!< Single shot parallel trigger mode.
+ When the trigger condition occurs, all ADCs start at the same time.
+ All ADCs scan cyclicly(keep scanning till you stop them). */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_AWD_Unit ADC Analog Watchdog Unit
+ * @{
+ */
+#define ADC_AWD0 (0U) /*!< ADC analog watchdog 0. */
+#define ADC_AWD1 (1U) /*!< ADC analog watchdog 1. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_AWD_Int_Type ADC AWD Interrupt Type
+ * @{
+ */
+#define ADC_AWD_INT_AWD0 (ADC_AWDCR_AWD0IEN) /*!< Interrupt of AWD0. */
+#define ADC_AWD_INT_AWD1 (ADC_AWDCR_AWD1IEN) /*!< Interrupt of AWD1. */
+#define ADC_AWD_INT_ALL (ADC_AWD_INT_AWD0 | ADC_AWD_INT_AWD1)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_AWD_Mode ADC Analog Watchdog Mode
+ * @{
+ */
+#define ADC_AWD_MD_CMP_OUT (0x0U) /*!< ADCValue > HighThreshold or ADCValue < LowThreshold */
+#define ADC_AWD_MD_CMP_IN (0x1U) /*!< LowThreshold < ADCValue < HighThreshold */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_AWD_Comb_Mode ADC AWD(Analog Watchdog) Combination Mode
+ * @note If combination mode is valid(ADC_AWD_COMB_OR/ADC_AWD_COMB_AND/ADC_AWD_COMB_XOR) and
+ * the Channels selected by the AWD0 and AWD1 are deferent, make sure that the channel
+ * of AWD1 is converted after the channel conversion of AWD0 ends.
+ * @{
+ */
+#define ADC_AWD_COMB_INVD (0U) /*!< Combination mode is invalid. */
+#define ADC_AWD_COMB_OR (ADC_AWDCR_AWDCM_0) /*!< The status of AWD0 is set or the status of AWD1 is set, the status of combination mode is set. */
+#define ADC_AWD_COMB_AND (ADC_AWDCR_AWDCM_1) /*!< The status of AWD0 is set and the status of AWD1 is set, the status of combination mode is set. */
+#define ADC_AWD_COMB_XOR (ADC_AWDCR_AWDCM) /*!< Only one of the status of AWD0 and AWD1 is set, the status of combination mode is set. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_AWD_Status_Flag ADC AWD Status Flag
+ * @{
+ */
+#define ADC_AWD_FLAG_AWD0 (ADC_AWDSR_AWD0F) /*!< Flag of AWD0. */
+#define ADC_AWD_FLAG_AWD1 (ADC_AWDSR_AWD1F) /*!< Flag of AWD1. */
+#define ADC_AWD_FLAG_COMB (ADC_AWDSR_AWDCMF) /*!< Flag of combination of mode. */
+#define ADC_AWD_FLAG_ALL (ADC_AWD_FLAG_AWD0 | ADC_AWD_FLAG_AWD1 | ADC_AWD_FLAG_COMB)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_PGA_Unit ADC PGA Unit
+ * @{
+ */
+#define ADC_PGA1 (0U) /*!< PGA1, belongs to ADC1. Input pin is ADC12_IN7(PA7). */
+#define ADC_PGA2 (1U) /*!< PGA2, belongs to ADC2. Input pin is ADC123_IN8(PB0). */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_PGA_Gain ADC PGA Gain Factor
+ * @{
+ */
+#define ADC_PGA_GAIN_2 (0x0U) /*!< PGA gain factor is 2. */
+#define ADC_PGA_GAIN_2P133 (0x1U) /*!< PGA gain factor is 2.133. */
+#define ADC_PGA_GAIN_2P286 (0x2U) /*!< PGA gain factor is 2.286. */
+#define ADC_PGA_GAIN_2P667 (0x3U) /*!< PGA gain factor is 2.667. */
+#define ADC_PGA_GAIN_2P909 (0x4U) /*!< PGA gain factor is 2.909. */
+#define ADC_PGA_GAIN_3P2 (0x5U) /*!< PGA gain factor is 3.2. */
+#define ADC_PGA_GAIN_3P556 (0x6U) /*!< PGA gain factor is 2.556. */
+#define ADC_PGA_GAIN_4 (0x7U) /*!< PGA gain factor is 4. */
+#define ADC_PGA_GAIN_4P571 (0x8U) /*!< PGA gain factor is 4.571. */
+#define ADC_PGA_GAIN_5P333 (0x9U) /*!< PGA gain factor is 5.333. */
+#define ADC_PGA_GAIN_6P4 (0xAU) /*!< PGA gain factor is 6.4. */
+#define ADC_PGA_GAIN_8 (0xBU) /*!< PGA gain factor is 8. */
+#define ADC_PGA_GAIN_10P667 (0xCU) /*!< PGA gain factor is 10.667. */
+#define ADC_PGA_GAIN_16 (0xDU) /*!< PGA gain factor is 16. */
+#define ADC_PGA_GAIN_32 (0xEU) /*!< PGA gain factor is 32. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_PGA_VSS ADC PGA VSS
+ * @note HC32F472JCTI/HC32F472JETI/HC32F472PCTI/HC32F472PETI do NOT have pin PGAx_VSS
+ * @{
+ */
+#define ADC_PGA_VSS_PGAVSS (0U) /*!< Use pin PGAx_VSS as the reference GND of PGAx. */
+#define ADC_PGA_VSS_AVSS (1U) /*!< Use AVSS as the reference GND of PGAx. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_Remap_Pin ADC Remap Pin
+ * @{
+ */
+#define ADC12_PIN_PA0 (0U) /*!< ADC123_IN0(PA0): default channel is ADC_CH0 of ADC1 and ADC2 */
+#define ADC12_PIN_PA1 (1U) /*!< ADC123_IN1(PA1): default channel is ADC_CH1 of ADC1 and ADC2 */
+#define ADC12_PIN_PA2 (2U) /*!< ADC123_IN2(PA2): default channel is ADC_CH2 of ADC1 and ADC2 */
+#define ADC12_PIN_PA3 (3U) /*!< ADC123_IN3(PA3): default channel is ADC_CH3 of ADC1 and ADC2 */
+#define ADC12_PIN_PA4 (4U) /*!< ADC12_IN4(PA4): default channel is ADC_CH4 of ADC1 and ADC2 */
+#define ADC12_PIN_PA5 (5U) /*!< ADC12_IN5(PA5): default channel is ADC_CH5 of ADC1 and ADC2 */
+#define ADC12_PIN_PA6 (6U) /*!< ADC12_IN6(PA6): default channel is ADC_CH6 of ADC1 and ADC2 */
+#define ADC12_PIN_PA7 (7U) /*!< ADC12_IN7(PA7): default channel is ADC_CH7 of ADC1 and ADC2 */
+#define ADC12_PIN_PB0 (8U) /*!< ADC123_IN8(PB0): default channel is ADC_CH8 of ADC1 and ADC2 */
+#define ADC12_PIN_PB1 (9U) /*!< ADC123_IN9(PB1): default channel is ADC_CH9 of ADC1 and ADC2 */
+#define ADC12_PIN_PC0 (10U) /*!< ADC123_IN10(PC0): default channel is ADC_CH10 of ADC1 and ADC2 */
+#define ADC12_PIN_PC1 (11U) /*!< ADC123_IN11(PC1): default channel is ADC_CH11 of ADC1 and ADC2 */
+#define ADC12_PIN_PC2 (12U) /*!< ADC123_IN12(PC2): default channel is ADC_CH12 of ADC1 and ADC2 */
+#define ADC12_PIN_PC3 (13U) /*!< ADC123_IN13(PC3): default channel is ADC_CH13 of ADC1 and ADC2 */
+#define ADC12_PIN_PC4 (14U) /*!< ADC12_IN14(PC4): default channel is ADC_CH14 of ADC1 and ADC2 */
+#define ADC12_PIN_PC5 (15U) /*!< ADC12_IN15(PC5): default channel is ADC_CH15 of ADC1 and ADC2 */
+
+#define ADC3_PIN_PA0 (0U) /*!< ADC123_IN0(PA0): default channel is ADC_CH0 of ADC3 */
+#define ADC3_PIN_PA1 (1U) /*!< ADC123_IN1(PA1): default channel is ADC_CH1 of ADC3 */
+#define ADC3_PIN_PA2 (2U) /*!< ADC123_IN2(PA2): default channel is ADC_CH2 of ADC3 */
+#define ADC3_PIN_PA3 (3U) /*!< ADC123_IN3(PA3): default channel is ADC_CH3 of ADC3 */
+#define ADC3_PIN_PA8 (4U) /*!< ADC3_IN4(PA8): default channel is ADC_CH4 of ADC3 */
+#define ADC3_PIN_PA9 (5U) /*!< ADC3_IN5(PA9): default channel is ADC_CH5 of ADC3 */
+#define ADC3_PIN_PA10 (6U) /*!< ADC3_IN6(PA10): default channel is ADC_CH6 of ADC3 */
+#define ADC3_PIN_PA11 (7U) /*!< ADC3_IN7(PA11): default channel is ADC_CH7 of ADC3 */
+#define ADC3_PIN_PB0 (8U) /*!< ADC123_IN8(PB0): default channel is ADC_CH8 of ADC3 */
+#define ADC3_PIN_PB1 (9U) /*!< ADC123_IN9(PB1): default channel is ADC_CH9 of ADC3 */
+#define ADC3_PIN_PC0 (10U) /*!< ADC123_IN10(PC0): default channel is ADC_CH10 of ADC3 */
+#define ADC3_PIN_PC1 (11U) /*!< ADC123_IN11(PC1): default channel is ADC_CH11 of ADC3 */
+#define ADC3_PIN_PC2 (12U) /*!< ADC123_IN12(PC2): default channel is ADC_CH12 of ADC3 */
+#define ADC3_PIN_PC3 (13U) /*!< ADC123_IN13(PC3): default channel is ADC_CH13 of ADC3 */
+#define ADC3_PIN_PF4 (14U) /*!< ADC3_IN14(PF4): default channel is ADC_CH14 of ADC3 */
+#define ADC3_PIN_PF5 (15U) /*!< ADC3_IN15(PF5): default channel is ADC_CH15 of ADC3 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup ADC_Global_Functions
+ * @{
+ */
+/*******************************************************************************
+ Basic features
+ ******************************************************************************/
+int32_t ADC_Init(CM_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcAdcInit);
+int32_t ADC_DeInit(CM_ADC_TypeDef *ADCx);
+int32_t ADC_StructInit(stc_adc_init_t *pstcAdcInit);
+void ADC_ChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint8_t u8Ch, en_functional_state_t enNewState);
+void ADC_MxChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint32_t u32MxCh, en_functional_state_t enNewState);
+void ADC_SetSampleTime(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8SampleTime);
+
+/* Conversion data average calculation function. */
+void ADC_ConvDataAverageConfig(CM_ADC_TypeDef *ADCx, uint16_t u16AverageCount);
+void ADC_ConvDataAverageChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, en_functional_state_t enNewState);
+void ADC_ConvDataAverageMxChCmd(CM_ADC_TypeDef *ADCx, uint32_t u32MxCh, en_functional_state_t enNewState);
+
+void ADC_TriggerConfig(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint16_t u16TriggerSel);
+void ADC_TriggerCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enNewState);
+void ADC_IntCmd(CM_ADC_TypeDef *ADCx, uint8_t u8IntType, en_functional_state_t enNewState);
+int32_t ADC_Start(CM_ADC_TypeDef *ADCx);
+void ADC_Stop(CM_ADC_TypeDef *ADCx);
+uint16_t ADC_GetValue(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch);
+uint16_t ADC_GetResolution(const CM_ADC_TypeDef *ADCx);
+en_flag_status_t ADC_GetStatus(const CM_ADC_TypeDef *ADCx, uint8_t u8Flag);
+void ADC_ClearStatus(CM_ADC_TypeDef *ADCx, uint8_t u8Flag);
+/*******************************************************************************
+ Advanced features
+ ******************************************************************************/
+/* Channel remap. */
+void ADC_ChRemap(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8AdcPin);
+uint8_t ADC_GetChPin(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch);
+void ADC_ResetChMapping(CM_ADC_TypeDef *ADCx);
+
+/* Sync mode. */
+void ADC_SyncModeConfig(uint16_t u16SyncUnit, uint16_t u16SyncMode, uint8_t u8TriggerDelay);
+void ADC_SyncModeCmd(en_functional_state_t enNewState);
+
+/* Analog watchdog */
+int32_t ADC_AWD_Config(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch, const stc_adc_awd_config_t *pstcAwd);
+/* Combination mode. */
+void ADC_AWD_SetCombMode(CM_ADC_TypeDef *ADCx, uint16_t u16CombMode);
+void ADC_AWD_SetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16WatchdogMode);
+uint16_t ADC_AWD_GetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit);
+void ADC_AWD_SetThreshold(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16LowThreshold, uint16_t u16HighThreshold);
+void ADC_AWD_SelectCh(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch);
+void ADC_AWD_Cmd(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, en_functional_state_t enNewState);
+void ADC_AWD_IntCmd(CM_ADC_TypeDef *ADCx, uint16_t u16IntType, en_functional_state_t enNewState);
+en_flag_status_t ADC_AWD_GetStatus(const CM_ADC_TypeDef *ADCx, uint32_t u32Flag);
+void ADC_AWD_ClearStatus(CM_ADC_TypeDef *ADCx, uint32_t u32Flag);
+
+/* PGA */
+void ADC_PGA_Config(CM_ADC_TypeDef *ADCx, uint8_t u8PgaUnit, uint8_t u8Gain, uint8_t u8PgaVss);
+void ADC_PGA_Cmd(CM_ADC_TypeDef *ADCx, uint8_t u8PgaUnit, en_functional_state_t enNewState);
+
+void ADC_DataRegAutoClearCmd(CM_ADC_TypeDef *ADCx, en_functional_state_t enNewState);
+void ADC_SetSeqAResumeMode(CM_ADC_TypeDef *ADCx, uint16_t u16SeqAResumeMode);
+/**
+ * @}
+ */
+
+#endif /* LL_ADC_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_ADC_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_aes.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_aes.h
new file mode 100644
index 0000000000..f7190307dc
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_aes.h
@@ -0,0 +1,118 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_aes.h
+ * @brief This file contains all the functions prototypes of the AES driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Add API AES_DeInit()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_AES_H__
+#define __HC32_LL_AES_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_AES
+ * @{
+ */
+
+#if (LL_AES_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup AES_Global_Macros AES Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup AES_Key_Size AES Key Size
+ * @{
+ */
+#define AES_KEY_SIZE_16BYTE (16U)
+#define AES_KEY_SIZE_24BYTE (24U)
+#define AES_KEY_SIZE_32BYTE (32U)
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup AES_Global_Functions
+ * @{
+ */
+int32_t AES_Encrypt(const uint8_t *pu8Plaintext, uint32_t u32PlaintextSize,
+ const uint8_t *pu8Key, uint8_t u8KeySize,
+ uint8_t *pu8Ciphertext);
+
+int32_t AES_Decrypt(const uint8_t *pu8Ciphertext, uint32_t u32CiphertextSize,
+ const uint8_t *pu8Key, uint8_t u8KeySize,
+ uint8_t *pu8Plaintext);
+
+int32_t AES_DeInit(void);
+/**
+ * @}
+ */
+
+#endif /* LL_AES_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_AES_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_aos.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_aos.h
new file mode 100644
index 0000000000..c7465066c8
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_aos.h
@@ -0,0 +1,190 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_aos.h
+ * @brief This file contains all the functions prototypes of the AOS driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-01-15 CDT Modified parameters name of API AOS_CommonTriggerCmd() and AOS_SetTriggerEventSrc()
+ 2023-06-30 CDT Modify for new head file
+ Add AOS_DeInit function
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_AOS_H__
+#define __HC32_LL_AOS_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_AOS
+ * @{
+ */
+
+#if (LL_AOS_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup AOS_Global_Macros AOS Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup AOS_Target_Select AOS Target Select
+ * @{
+ */
+#define AOS_DCU1 (uint32_t)(&CM_AOS->DCU_TRGSEL1)
+#define AOS_DCU2 (uint32_t)(&CM_AOS->DCU_TRGSEL2)
+#define AOS_DCU3 (uint32_t)(&CM_AOS->DCU_TRGSEL3)
+#define AOS_DMA1_0 (uint32_t)(&CM_AOS->DMA1_TRGSEL0)
+#define AOS_DMA1_1 (uint32_t)(&CM_AOS->DMA1_TRGSEL1)
+#define AOS_DMA1_2 (uint32_t)(&CM_AOS->DMA1_TRGSEL2)
+#define AOS_DMA1_3 (uint32_t)(&CM_AOS->DMA1_TRGSEL3)
+#define AOS_DMA1_4 (uint32_t)(&CM_AOS->DMA1_TRGSEL4)
+#define AOS_DMA1_5 (uint32_t)(&CM_AOS->DMA1_TRGSEL5)
+#define AOS_DMA1_6 (uint32_t)(&CM_AOS->DMA1_TRGSEL6)
+#define AOS_DMA1_7 (uint32_t)(&CM_AOS->DMA1_TRGSEL7)
+#define AOS_DMA2_0 (uint32_t)(&CM_AOS->DMA2_TRGSEL0)
+#define AOS_DMA2_1 (uint32_t)(&CM_AOS->DMA2_TRGSEL1)
+#define AOS_DMA2_2 (uint32_t)(&CM_AOS->DMA2_TRGSEL2)
+#define AOS_DMA2_3 (uint32_t)(&CM_AOS->DMA2_TRGSEL3)
+#define AOS_DMA2_4 (uint32_t)(&CM_AOS->DMA2_TRGSEL4)
+#define AOS_DMA2_5 (uint32_t)(&CM_AOS->DMA2_TRGSEL5)
+#define AOS_DMA2_6 (uint32_t)(&CM_AOS->DMA2_TRGSEL6)
+#define AOS_DMA2_7 (uint32_t)(&CM_AOS->DMA2_TRGSEL7)
+#define AOS_DMA_RC (uint32_t)(&CM_AOS->DMA_RC_TRGSEL)
+#define AOS_TMR6_0 (uint32_t)(&CM_AOS->TMR6_TRGSEL0)
+#define AOS_TMR6_1 (uint32_t)(&CM_AOS->TMR6_TRGSEL1)
+#define AOS_TMR6_2 (uint32_t)(&CM_AOS->TMR6_TRGSEL2)
+#define AOS_TMR6_3 (uint32_t)(&CM_AOS->TMR6_TRGSEL3)
+#define AOS_TMR4 (uint32_t)(&CM_AOS->TMR4_TRGSEL)
+#define AOS_EVTPORT12 (uint32_t)(&CM_AOS->PEVNT_TRGSEL12)
+#define AOS_EVTPORT34 (uint32_t)(&CM_AOS->PEVNT_TRGSEL34)
+#define AOS_TMR0 (uint32_t)(&CM_AOS->TMR0_TRGSEL)
+#define AOS_TMR2 (uint32_t)(&CM_AOS->TMR2_TRGSEL)
+#define AOS_HASH_A (uint32_t)(&CM_AOS->HASH_TRGSEL0)
+#define AOS_HASH_B (uint32_t)(&CM_AOS->HASH_TRGSEL1)
+#define AOS_TMRA_0 (uint32_t)(&CM_AOS->TMRA_TRGSEL0)
+#define AOS_TMRA_1 (uint32_t)(&CM_AOS->TMRA_TRGSEL1)
+#define AOS_TMRA_2 (uint32_t)(&CM_AOS->TMRA_TRGSEL2)
+#define AOS_TMRA_3 (uint32_t)(&CM_AOS->TMRA_TRGSEL3)
+#define AOS_OTS (uint32_t)(&CM_AOS->OTS_TRGSEL)
+#define AOS_ADC1_0 (uint32_t)(&CM_AOS->ADC1_TRGSEL0)
+#define AOS_ADC1_1 (uint32_t)(&CM_AOS->ADC1_TRGSEL1)
+#define AOS_ADC2_0 (uint32_t)(&CM_AOS->ADC2_TRGSEL0)
+#define AOS_ADC2_1 (uint32_t)(&CM_AOS->ADC2_TRGSEL1)
+#define AOS_ADC3_0 (uint32_t)(&CM_AOS->ADC3_TRGSEL0)
+#define AOS_ADC3_1 (uint32_t)(&CM_AOS->ADC3_TRGSEL1)
+#define AOS_COMM_1 (uint32_t)(&CM_AOS->COMTRGSEL1)
+#define AOS_COMM_2 (uint32_t)(&CM_AOS->COMTRGSEL2)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup AOS_Common_Trigger_ID AOS Common Trigger ID
+ * @{
+ */
+#define AOS_COMM_TRIG1 (1UL << 30U)
+#define AOS_COMM_TRIG2 (1UL << 31U)
+#define AOS_COMM_TRIG_MASK (AOS_COMM_TRIG1 | AOS_COMM_TRIG2)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup AOS_Trigger_Select_Mask AOS Trigger Select Mask
+ * @{
+ */
+#define AOS_TRIG_SEL_MASK (0x1FFUL)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup AOS_Global_Functions
+ * @{
+ */
+
+/**
+ * @brief AOS software trigger.
+ * @param None
+ * @retval None
+ */
+__STATIC_INLINE void AOS_SW_Trigger(void)
+{
+ WRITE_REG32(bCM_AOS->INTSFTTRG_b.STRG, SET);
+}
+
+int32_t AOS_DeInit(void);
+void AOS_CommonTriggerCmd(uint32_t u32Target, uint32_t u32CommonTrigger, en_functional_state_t enNewState);
+void AOS_SetTriggerEventSrc(uint32_t u32Target, en_event_src_t enSource);
+/**
+ * @}
+ */
+
+#endif /* LL_AOS_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_AOS_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_can.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_can.h
new file mode 100644
index 0000000000..3e15c155c0
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_can.h
@@ -0,0 +1,721 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_can.h
+ * @brief This file contains all the functions prototypes of the CAN driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2022-10-31 CDT Remove CAN_FLAG_RX_BUF_OVF from CAN_FLAG_CLR_ALL
+ 2023-06-30 CDT Added 3 APIs for local-reset
+ Modify typo
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_CAN_H__
+#define __HC32_LL_CAN_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_CAN
+ * @{
+ */
+#if (LL_CAN_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup CAN_Global_Types CAN Global Types
+ * @{
+ */
+/**
+ * @brief CAN bit time configuration structure.
+ * @note 1. TQ = u32Prescaler / CANClock.
+ * @note 2. Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ.
+ * @note 3. Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2))
+ * @note 4. See user manual of the target MCU and ISO11898-1 for more details.
+ */
+typedef struct {
+ uint32_t u32Prescaler; /*!< Specifies the prescaler of CAN clock, [1, 256]. */
+ uint32_t u32TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1.
+ u32TimeSeg1 Contains synchronization segment,
+ propagation time segment and phase buffer segment 1. */
+ uint32_t u32TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2.
+ Phase buffer segment 2. */
+ uint32_t u32SJW; /*!< Synchronization Jump Width.
+ Specifies the maximum number of time quanta the CAN hardware
+ is allowed to lengthen or shorten a bit to perform resynchronization. */
+} stc_can_bit_time_config_t;
+
+/**
+ * @brief CAN acceptance filter configuration structure.
+ */
+typedef struct {
+ uint32_t u32ID; /*!< Specifies the identifier(ID). 11 bits standard ID or 29 bits extended ID, depending on IDE. */
+ uint32_t u32IDMask; /*!< Specifies the identifier(ID) mask. The mask bits of ID will be ignored by the acceptance filter. */
+ uint32_t u32IDType; /*!< Specifies the identifier(ID) type. This parameter can be a value of @ref CAN_ID_Type */
+} stc_can_filter_config_t;
+
+/**
+ * @brief CAN-FD configuration structure.
+ */
+typedef struct {
+ stc_can_bit_time_config_t stcBitCfg; /*!< Bit time configuration of flexible data-rate bit. */
+ uint8_t u8Mode; /*!< CAN-FD mode, Bosch CAN-FD or ISO 11898-1:2015 CAN-FD.
+ This parameter can be a value of @ref CAN_FD_Mode */
+ uint8_t u8TDC; /*!< Enable or disable Transmitter Delay Compensation.
+ This parameter can be a value of @ref CAN_FD_TDC_En */
+ uint8_t u8SSPOffset; /*!< Specifies Secondary Sample Point offset.
+ The transmitter delay plus u8SSPOffset defines the time of the secondary sample point for TDC.
+ u8SSPOffset is given as a number of TQ. Range is [0, 127] */
+} stc_canfd_config_t;
+
+/**
+ * @brief TTCAN configuration structure.
+ */
+typedef struct {
+ uint32_t u32RefMsgID; /*!< Reference message identifier. */
+ uint32_t u32RefMsgIDE; /*!< Reference message identifier extension bit.
+ '1' to set the ID which is specified by parameter 'u32RefMsgID' as an extended ID while
+ '0' to set it as a standard ID. */
+ uint8_t u8NTUPrescaler; /*!< Prescaler of NTU(network time unit). The source is the bit time which is defined by SBT.
+ This parameter can be a value of @ref TTCAN_NTU_Prescaler */
+ uint8_t u8TxBufMode; /*!< TTCAN Transmit Buffer Mode.
+ This parameter can be a value of @ref TTCAN_Tx_Buf_Mode */
+ uint16_t u16TriggerType; /*!< Trigger type of TTCAN.
+ This parameter can be a value of @ref TTCAN_Trigger_Type */
+ uint16_t u16TxEnableWindow; /*!< Tx_Enable window. Time period within which the transmission of a message may be started. Range is [1, 16] */
+ uint16_t u16TxTriggerTime; /*!< Specifies for the referred message the time window of the matrix cycle at which it is to be transmitted. Range is [0, 65535] */
+ uint16_t u16WatchTriggerTime; /*!< Time mark used to check whether the time since the last valid reference message has been too long. Range is [0, 65535] */
+} stc_can_ttc_config_t;
+
+/**
+ * @brief CAN initialization structure.
+ */
+typedef struct {
+ stc_can_bit_time_config_t stcBitCfg; /*!< Bit time configuration of classical CAN bit. @ref stc_can_bit_time_config_t */
+ stc_can_filter_config_t *pstcFilter; /*!< Pointer to a @ref stc_can_filter_config_t structure that
+ contains the configuration informations for the acceptance filters. */
+ uint16_t u16FilterSelect; /*!< Selects acceptance filters.
+ This parameter can be values of @ref CAN_Acceptance_Filter */
+ uint8_t u8WorkMode; /*!< Specifies the work mode of CAN.
+ This parameter can be a value of @ref CAN_Work_Mode */
+ uint8_t u8PTBSingleShotTx; /*!< Enable or disable single shot transmission of PTB.
+ This parameter can be a value of @ref PTB_SingleShot_Tx_En */
+ uint8_t u8STBSingleShotTx; /*!< Enable or disable single shot transmission of STB.
+ This parameter can be a value of @ref STB_SingleShot_Tx_En */
+ uint8_t u8STBPrioMode; /*!< Enable or disable the priority decision mode of STB.
+ This parameter can be a value of @ref CAN_STB_Prio_Mode_En
+ NOTE: A frame in the PTB has always the highest priority regardless of the ID. */
+ uint8_t u8RxWarnLimit; /*!< Specifies receive buffer almost full warning limit. Rang is [1, 8].
+ Each CAN unit has 8 receive buffers. When the number of received frames reaches
+ the value specified by u8RxWarnLimit, register bit RTIF.RAFIF is set and the interrupt occurred
+ if it was enabled. */
+ uint8_t u8ErrorWarnLimit; /*!< Specifies programmable error warning limit. Range is [0, 15].
+ Error warning limit = (u8ErrorWarnLimit + 1) * 8. */
+ uint8_t u8RxAllFrame; /*!< Enable or disable receive all frames(includes frames with error).
+ This parameter can be a value of @ref CAN_Rx_All_En */
+ uint8_t u8RxOvfMode; /*!< Receive buffer overflow mode. In case of a full receive buffer when a new frame is received.
+ This parameter can be a value of @ref CAN_Rx_Ovf_Mode */
+ uint8_t u8SelfAck; /*!< Enable or disable self-acknowledge.
+ This parameter can be a value of @ref CAN_Self_ACK_En */
+ stc_canfd_config_t *pstcCanFd; /*!< Pointer to a CAN-FD configuration structure. @ref stc_canfd_config_t
+ Set it to NULL if not needed CAN-FD. */
+
+ stc_can_ttc_config_t *pstcCanTtc; /*!< Pointer to a TTCAN configuration structure. @ref stc_can_ttc_config_t
+ Set it to NULL if not needed TTCAN. */
+} stc_can_init_t;
+
+/**
+ * @brief CAN error information structure.
+ */
+typedef struct {
+ uint8_t u8ArbitrLostPos; /*!< Bit position in the frame where the arbitration has been lost. */
+ uint8_t u8ErrorType; /*!< CAN error type. This parameter can be a value of @ref CAN_Err_Type */
+ uint8_t u8RxErrorCount; /*!< Receive error count. */
+ uint8_t u8TxErrorCount; /*!< Transmit error count. */
+} stc_can_error_info_t;
+
+/**
+ * @brief CAN TX frame data structure.
+ */
+typedef struct {
+ uint32_t u32ID; /*!< 11 bits standard ID or 29 bits extended ID, depending on IDE. */
+ union {
+ uint32_t u32Ctrl;
+ struct {
+ uint32_t DLC: 4; /*!< Data length code. Length of the data segment of data frame.
+ It should be zero while the frame is remote frame.
+ This parameter can be a value of @ref CAN_Data_Length_Code */
+ uint32_t BRS: 1; /*!< Bit rate switch. */
+ uint32_t FDF: 1; /*!< CAN FD frame. */
+ uint32_t RTR: 1; /*!< Remote transmission request bit.
+ It is used to distinguish between data frames and remote frames. */
+ uint32_t IDE: 1; /*!< Identifier extension flag.
+ It is used to distinguish between standard format and extended format.
+ This parameter can be a 1 or 0. */
+ uint32_t RSVD: 24; /*!< Reserved bits. */
+ };
+ };
+ uint8_t au8Data[64U]; /*!< TX data payload. */
+} stc_can_tx_frame_t;
+
+/**
+ * @brief CAN RX frame data structure.
+ */
+typedef struct {
+ uint32_t u32ID; /*!< 11 bits standard ID or 29 bits extended ID, depending on IDE. */
+ union {
+ uint32_t u32Ctrl;
+ struct {
+ uint32_t DLC: 4; /*!< Data length code. Length of the data segment of data frame.
+ It should be zero while the frame is remote frame.
+ This parameter can be a value of @ref CAN_Data_Length_Code */
+ uint32_t BRS: 1; /*!< Bit rate switch. */
+ uint32_t FDF: 1; /*!< CAN FD frame. */
+ uint32_t RTR: 1; /*!< Remote transmission request bit.
+ It is used to distinguish between data frames and remote frames. */
+ uint32_t IDE: 1; /*!< Identifier extension flag.
+ It is used to distinguish between standard format and extended format.
+ This parameter can be 1 or 0. */
+ uint32_t RSVD: 4; /*!< Reserved bits. */
+ uint32_t TX: 1; /*!< This bit is set to 1 when receiving self-transmitted data in loopback mode. */
+ uint32_t ERRT: 3; /*!< Error type. */
+ uint32_t CYCLE_TIME: 16; /*!< Cycle time of time-triggered communication(TTC). */
+ };
+ };
+ uint8_t au8Data[64U]; /*!< RX data payload. */
+} stc_can_rx_frame_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup CAN_Global_Macros CAN Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup CAN_Work_Mode CAN Work Mode
+ * @{
+ */
+#define CAN_WORK_MD_NORMAL (0U) /*!< Normal work mode. */
+#define CAN_WORK_MD_SILENT (1U) /*!< Silent work mode. Prohibit data transmission. */
+#define CAN_WORK_MD_ILB (2U) /*!< Internal loop back mode, just for self-test while developing. */
+#define CAN_WORK_MD_ELB (3U) /*!< External loop back mode, just for self-test while developing. */
+#define CAN_WORK_MD_ELB_SILENT (4U) /*!< External loop back silent mode, just for self-test while developing.
+ It is forbidden to respond to received frames and error frames,
+ but data can be transmitted. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_Tx_Buf_Type CAN Transmit Buffer Type
+ * @{
+ */
+#define CAN_TX_BUF_PTB (0U) /*!< Primary transmit buffer. */
+#define CAN_TX_BUF_STB (1U) /*!< Secondary transmit buffer. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_Data_Length_Code CAN Data Length Code
+ * @{
+ */
+#define CAN_DLC0 (0x0U) /*!< CAN2.0 and CAN FD: the size of data field is 0 bytes. */
+#define CAN_DLC1 (0x1U) /*!< CAN2.0 and CAN FD: the size of data field is 1 bytes. */
+#define CAN_DLC2 (0x2U) /*!< CAN2.0 and CAN FD: the size of data field is 2 bytes. */
+#define CAN_DLC3 (0x3U) /*!< CAN2.0 and CAN FD: the size of data field is 3 bytes. */
+#define CAN_DLC4 (0x4U) /*!< CAN2.0 and CAN FD: the size of data field is 4 bytes. */
+#define CAN_DLC5 (0x5U) /*!< CAN2.0 and CAN FD: the size of data field is 5 bytes. */
+#define CAN_DLC6 (0x6U) /*!< CAN2.0 and CAN FD: the size of data field is 6 bytes. */
+#define CAN_DLC7 (0x7U) /*!< CAN2.0 and CAN FD: the size of data field is 7 bytes. */
+#define CAN_DLC8 (0x8U) /*!< CAN2.0 and CAN FD: the size of data field is 8 bytes. */
+#define CAN_DLC12 (0x9U) /*!< CAN FD: the size of data field is 12 bytes. */
+#define CAN_DLC16 (0xAU) /*!< CAN FD: the size of data field is 16 bytes. */
+#define CAN_DLC20 (0xBU) /*!< CAN FD: the size of data field is 20 bytes. */
+#define CAN_DLC24 (0xCU) /*!< CAN FD: the size of data field is 24 bytes. */
+#define CAN_DLC32 (0xDU) /*!< CAN FD: the size of data field is 32 bytes. */
+#define CAN_DLC48 (0xEU) /*!< CAN FD: the size of data field is 48 bytes. */
+#define CAN_DLC64 (0xFU) /*!< CAN FD: the size of data field is 64 bytes. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PTB_SingleShot_Tx_En PTB Single Shot Transmission Function Control
+ * @{
+ */
+#define CAN_PTB_SINGLESHOT_TX_DISABLE (0x0U) /*!< Primary transmit buffer auto retransmit. */
+#define CAN_PTB_SINGLESHOT_TX_ENABLE (CAN_CFG_STAT_TPSS) /*!< Primary transmit buffer single short transmit. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup STB_SingleShot_Tx_En STB Single Shot Transmission Function Control
+ * @{
+ */
+#define CAN_STB_SINGLESHOT_TX_DISABLE (0x0U) /*!< Secondary transmit buffer auto retransmit. */
+#define CAN_STB_SINGLESHOT_TX_ENABLE (CAN_CFG_STAT_TSSS) /*!< Secondary transmit buffer single short transmit. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_Tx_Request CAN Transmission Request
+ * @{
+ */
+#define CAN_TX_REQ_STB_ONE (CAN_TCMD_TSONE) /*!< Transmit one STB frame. */
+#define CAN_TX_REQ_STB_ALL (CAN_TCMD_TSALL) /*!< Transmit all STB frames. */
+#define CAN_TX_REQ_PTB (CAN_TCMD_TPE) /*!< Transmit PTB frame. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_STB_Prio_Mode_En CAN STB Priority Mode Function Control
+ * @note A frame in the PTB has always the highest priority regardless of the ID.
+ * @{
+ */
+#define CAN_STB_PRIO_MD_DISABLE (0x0U) /*!< The frame first in will first be transmitted. */
+#define CAN_STB_PRIO_MD_ENABLE (CAN_TCTRL_TSMODE) /*!< The frame with lower ID will first be transmitted. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_Tx_Buf_Status CAN Transmit Buffer Status
+ * @{
+ */
+#define CAN_TX_BUF_EMPTY (0x0U) /*!< TTCAN is disabled(TTEN == 0): STB is empty.
+ TTCAN is disabled(TTEN == 1) and transmit buffer is specified by TBPTR and TTPTR(TTTBM == 1):
+ PTB and STB are both empty. */
+#define CAN_TX_BUF_NOT_MORE_THAN_HALF (0x1U) /*!< TTEN == 0: STB is less than or equal to half full;
+ TTEN == 1 && TTTBM == 1: PTB and STB are neither empty. */
+#define CAN_TX_BUF_MORE_THAN_HALF (0x2U) /*!< TTEN == 0: STB is more than half full;
+ TTEN == 1 && TTTBM == 1: reserved value. */
+#define CAN_TX_BUF_FULL (0x3U) /*!< TTEN == 0: STB is full;
+ TTEN == 1 && TTTBM == 1: PTB and STB are both full. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_Rx_Buf_Status CAN Receive Buffer Status
+ * @{
+ */
+#define CAN_RX_BUF_EMPTY (0x0U) /*!< Receive buffer is empty. */
+#define CAN_RX_BUF_NOT_WARN (0x1U) /*!< Receive buffer is not empty, but is less than almost full warning limit. */
+#define CAN_RX_BUF_WARN (0x2U) /*!< Receive buffer is not full and not overflow, but is more than or equal to almost full warning limit. */
+#define CAN_RX_BUF_FULL (0x3U) /*!< Receive buffer is full. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_Rx_All_En CAN Receive All Frames
+ * @{
+ */
+#define CAN_RX_ALL_FRAME_DISABLE (0x0U) /*!< Only receives correct frames. */
+#define CAN_RX_ALL_FRAME_ENABLE (CAN_RCTRL_RBALL) /*!< Receives all frames, including frames with error. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_Rx_Ovf_Mode CAN Receive Buffer Overflow Mode
+ * @{
+ */
+#define CAN_RX_OVF_SAVE_NEW (0x0U) /*!< Saves the newly received data and the oldest frame will be overwritten. */
+#define CAN_RX_OVF_DISCARD_NEW (CAN_RCTRL_ROM) /*!< Discard the newly received data. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_Self_ACK_En CAN Self-ACK Function Control
+ * @{
+ */
+#define CAN_SELF_ACK_DISABLE (0x0U) /*!< Disable self-acknowledge. */
+#define CAN_SELF_ACK_ENABLE (CAN_RCTRL_SACK) /*!< Enable self-acknowledge. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_Interrupt_Type CAN Interrupt Type
+ * @{
+ */
+#define CAN_INT_ERR_INT (1UL << 1U) /*!< Register bit RTIE.EIE. The interrupt RTIF.EIF will be set if enabled by RTIE.EIE under the following conditions:
+ The border of the error warning limit has been crossed in either direction by RECNT or TECNT or
+ the BUSOFF bit has been changed in either direction. */
+#define CAN_INT_STB_TX (1UL << 2U) /*!< Register bit RTIE.TSIE. STB was transmitted. */
+#define CAN_INT_PTB_TX (1UL << 3U) /*!< Register bit RTIE.TPIE. PTB was transmitted. */
+#define CAN_INT_RX_BUF_WARN (1UL << 4U) /*!< Register bit RTIE.RAFIE. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. */
+#define CAN_INT_RX_BUF_FULL (1UL << 5U) /*!< Register bit RTIE.RFIE. The FIFO of receive buffer is full. */
+#define CAN_INT_RX_OVERRUN (1UL << 6U) /*!< Register bit RTIE.ROIE. Receive buffers are full and there is a further message to be stored. */
+#define CAN_INT_RX (1UL << 7U) /*!< Register bit RTIE.RIE. Received a valid data frame or remote frame. */
+#define CAN_INT_BUS_ERR (1UL << 9U) /*!< Register bit ERRINT.BEIE. Each of the error defined by EALCAP.KOER can cause bus-error interrupt. */
+#define CAN_INT_ARBITR_LOST (1UL << 11U) /*!< Register bit ERRINT.ALIE. Arbitration lost. */
+#define CAN_INT_ERR_PASSIVE (1UL << 13U) /*!< Register bit ERRINT.EPIE. A change from error-passive to error-active or error-active to error-passive has occurred. */
+
+#define CAN_INT_ALL (CAN_INT_ERR_INT | \
+ CAN_INT_STB_TX | \
+ CAN_INT_PTB_TX | \
+ CAN_INT_RX_BUF_WARN | \
+ CAN_INT_RX_BUF_FULL | \
+ CAN_INT_RX_OVERRUN | \
+ CAN_INT_RX | \
+ CAN_INT_BUS_ERR | \
+ CAN_INT_ARBITR_LOST | \
+ CAN_INT_ERR_PASSIVE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_Status_Flag CAN Status Flag
+ * @{
+ */
+#define CAN_FLAG_BUS_OFF (1UL << 0U) /*!< Register bit CFG_STAT.BUSOFF. CAN bus off. */
+#define CAN_FLAG_TX_GOING (1UL << 1U) /*!< Register bit CFG_STAT.TACTIVE. CAN bus is transmitting. */
+#define CAN_FLAG_RX_GOING (1UL << 2U) /*!< Register bit CFG_STAT.RACTIVE. CAN bus is receiving. */
+#define CAN_FLAG_RX_BUF_OVF (1UL << 5U) /*!< Register bit RCTRL.ROV. Receive buffer is full and there is a further bit to be stored. At least one frame will be lost. */
+#define CAN_FLAG_TX_BUF_FULL (1UL << 8U) /*!< Register bit RTIE.TSFF. Transmit buffers are all full.
+ TTCFG.TTEN == 0 or TCTRL.TTTEM == 0: ALL STB slots are filled.
+ TTCFG.TTEN == 1 and TCTRL.TTTEM == 1: Transmit buffer that pointed by TBSLOT.TBPTR is filled.*/
+#define CAN_FLAG_TX_ABORTED (1UL << 16U) /*!< Register bit RTIF.AIF. Transmit messages requested via TCMD.TPA and TCMD.TSA were successfully canceled. */
+#define CAN_FLAG_ERR_INT (1UL << 17U) /*!< Register bit RTIF.EIF. The interrupt RTIF.EIF will be set if enabled by RTIE.EIE under the following conditions:
+ The border of the error warning limit has been crossed in either direction by RECNT or TECNT or
+ the BUSOFF bit has been changed in either direction. */
+#define CAN_FLAG_STB_TX (1UL << 18U) /*!< Register bit RTIF.TSIF. STB was transmitted. */
+#define CAN_FLAG_PTB_TX (1UL << 19U) /*!< Register bit RTIF.TPIF. PTB was transmitted. */
+#define CAN_FLAG_RX_BUF_WARN (1UL << 20U) /*!< Register bit RTIF.RAFIF. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. */
+#define CAN_FLAG_RX_BUF_FULL (1UL << 21U) /*!< Register bit RTIF.RFIF. The FIFO of receive buffer is full. */
+#define CAN_FLAG_RX_OVERRUN (1UL << 22U) /*!< Register bit RTIF.ROIF. Receive buffers are all full and there is a further message to be stored. */
+#define CAN_FLAG_RX (1UL << 23U) /*!< Register bit RTIF.RIF. Received a valid data frame or remote frame. */
+#define CAN_FLAG_BUS_ERR (1UL << 24U) /*!< Register bit ERRINT.BEIF. Each of the error defined by EALCAP.KOER can make this flag set. */
+#define CAN_FLAG_ARBITR_LOST (1UL << 26U) /*!< Register bit ERRINT.ALIF. Arbitration lost. */
+#define CAN_FLAG_ERR_PASSIVE (1UL << 28U) /*!< Register bit ERRINT.EPIF. A change from error-passive to error-active or error-active to error-passive has occurred. */
+#define CAN_FLAG_ERR_PASSIVE_NODE (1UL << 30U) /*!< Register bit ERRINT.EPASS. The node is an error-passive node. */
+#define CAN_FLAG_TEC_REC_WARN (1UL << 31U) /*!< Register bit ERRINT.EWARN. REC or TEC is greater than or equal to the LIMIT.EWL setting value. */
+
+#define CAN_FLAG_ALL (CAN_FLAG_BUS_OFF | \
+ CAN_FLAG_TX_GOING | \
+ CAN_FLAG_RX_GOING | \
+ CAN_FLAG_RX_BUF_OVF | \
+ CAN_FLAG_TX_BUF_FULL | \
+ CAN_FLAG_TX_ABORTED | \
+ CAN_FLAG_ERR_INT | \
+ CAN_FLAG_STB_TX | \
+ CAN_FLAG_PTB_TX | \
+ CAN_FLAG_RX_BUF_WARN | \
+ CAN_FLAG_RX_BUF_FULL | \
+ CAN_FLAG_RX_OVERRUN | \
+ CAN_FLAG_RX | \
+ CAN_FLAG_BUS_ERR | \
+ CAN_FLAG_ARBITR_LOST | \
+ CAN_FLAG_ERR_PASSIVE | \
+ CAN_FLAG_ERR_PASSIVE_NODE | \
+ CAN_FLAG_TEC_REC_WARN)
+
+#define CAN_FLAG_CLR_ALL (CAN_FLAG_TX_ABORTED | \
+ CAN_FLAG_ERR_INT | \
+ CAN_FLAG_STB_TX | \
+ CAN_FLAG_PTB_TX | \
+ CAN_FLAG_RX_BUF_WARN | \
+ CAN_FLAG_RX_BUF_FULL | \
+ CAN_FLAG_RX_OVERRUN | \
+ CAN_FLAG_RX | \
+ CAN_FLAG_BUS_ERR | \
+ CAN_FLAG_ARBITR_LOST | \
+ CAN_FLAG_ERR_PASSIVE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_ID_Type CAN Identifier Type
+ * @{
+ */
+#define CAN_ID_STD_EXT (0x0U) /*!< Acceptance filter accept frames with both standard ID and extended ID. */
+#define CAN_ID_STD (CAN_ACF_AIDEE) /*!< Acceptance filter accept frames with only standard ID. */
+#define CAN_ID_EXT (CAN_ACF_AIDEE | \
+ CAN_ACF_AIDE) /*!< Acceptance filter accept frames with only extended ID. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_Err_Type CAN Error Type
+ * @{
+ */
+#define CAN_ERR_NONE (0U) /*!< No error. */
+#define CAN_ERR_BIT (0x1U) /*!< Error is bit error. */
+#define CAN_ERR_FORM (0x2U) /*!< Error is form error. */
+#define CAN_ERR_STUFF (0x3U) /*!< Error is stuff error. */
+#define CAN_ERR_ACK (0x4U) /*!< Error is ACK error. */
+#define CAN_ERR_CRC (0x5U) /*!< Error is CRC error. */
+#define CAN_ERR_OTHER (0x6U) /*!< Error is other error.
+ Dominant bits after own error flag, received active Error Flag too long,
+ dominant bit during Passive-Error-Flag after ACK error. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_Acceptance_Filter CAN Acceptance Filter
+ * @{
+ */
+#define CAN_FILTER1 (CAN_ACFEN_AE_1) /*!< Acceptance filter 1 select bit. */
+#define CAN_FILTER2 (CAN_ACFEN_AE_2) /*!< Acceptance filter 2 select bit. */
+#define CAN_FILTER3 (CAN_ACFEN_AE_3) /*!< Acceptance filter 3 select bit. */
+#define CAN_FILTER4 (CAN_ACFEN_AE_4) /*!< Acceptance filter 4 select bit. */
+#define CAN_FILTER5 (CAN_ACFEN_AE_5) /*!< Acceptance filter 5 select bit. */
+#define CAN_FILTER6 (CAN_ACFEN_AE_6) /*!< Acceptance filter 6 select bit. */
+#define CAN_FILTER7 (CAN_ACFEN_AE_7) /*!< Acceptance filter 7 select bit. */
+#define CAN_FILTER8 (CAN_ACFEN_AE_8) /*!< Acceptance filter 8 select bit. */
+#define CAN_FILTER9 (CAN_ACFEN_AE_9) /*!< Acceptance filter 9 select bit. */
+#define CAN_FILTER10 (CAN_ACFEN_AE_10) /*!< Acceptance filter 10 select bit. */
+#define CAN_FILTER11 (CAN_ACFEN_AE_11) /*!< Acceptance filter 11 select bit. */
+#define CAN_FILTER12 (CAN_ACFEN_AE_12) /*!< Acceptance filter 12 select bit. */
+#define CAN_FILTER13 (CAN_ACFEN_AE_13) /*!< Acceptance filter 13 select bit. */
+#define CAN_FILTER14 (CAN_ACFEN_AE_14) /*!< Acceptance filter 14 select bit. */
+#define CAN_FILTER15 (CAN_ACFEN_AE_15) /*!< Acceptance filter 15 select bit. */
+#define CAN_FILTER16 (CAN_ACFEN_AE_16) /*!< Acceptance filter 16 select bit. */
+#define CAN_FILTER_ALL (0xFFFFU)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_FD_Mode CAN-FD Mode
+ * @{
+ */
+#define CAN_FD_MD_BOSCH (0x0U) /*!< Bosch CAN FD (non-ISO) mode. */
+#define CAN_FD_MD_ISO (CAN_TCTRL_FD_ISO) /*!< ISO CAN FD mode (ISO 11898-1:2015). */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_FD_TDC_En CAN-FD TDC Function Control
+ * @{
+ */
+#define CAN_FD_TDC_DISABLE (0x0U) /*!< Disable transmitter delay compensation. */
+#define CAN_FD_TDC_ENABLE (CAN_TDC_TDCEN) /*!< Enable transmitter delay compensation. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TTCAN_Tx_Buf_Mode TTCAN Transmit Buffer Mode
+ * @{
+ */
+#define CAN_TTC_TX_BUF_MD_CAN (0x0U) /*!< Normal CAN mode. TTCAN transmit buffer depends on the priority mode of STB which is defined by @ref CAN_STB_Prio_Mode_En */
+#define CAN_TTC_TX_BUF_MD_TTCAN (CAN_TCTRL_TTTBM) /*!< Full TTCAN mode. TTCAN transmit buffer is pointed by TBSLOT.TBPTR(for data filling) and
+ TRG_CFG.TTPTR(for data transmission). */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TTCAN_Tx_Buf_Sel TTCAN Transmit Buffer Selection
+ * @{
+ */
+#define CAN_TTC_TX_BUF_PTB (0x0U) /*!< Point to PTB. */
+#define CAN_TTC_TX_BUF_STB1 (0x1U) /*!< Point to STB slot 1. */
+#define CAN_TTC_TX_BUF_STB2 (0x2U) /*!< Point to STB slot 2. */
+#define CAN_TTC_TX_BUF_STB3 (0x3U) /*!< Point to STB slot 3. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TTCAN_Tx_Buf_Mark_State TTCAN Transmit Buffer Mark State
+ * @{
+ */
+#define CAN_TTC_TX_BUF_MARK_EMPTY (CAN_TBSLOT_TBE) /*!< Marks the transmit buffer selected by TBSLOT.TBPTR as "empty".
+ TBE is automatically reset to 0 as soon as the slot is marked as empty and TSFF=0.
+ If a transmission from this slot is active, then TBE stays set as long as either the
+ transmission completes or after a transmission error or arbitration loss the transmission
+ is not active any more. If both TBF and TBE are set, then TBE wins. */
+#define CAN_TTC_TX_BUF_MARK_FILLED (CAN_TBSLOT_TBF) /*!< Marks the transmit buffer selected by TBSLOT.TBPTR as "filled".
+ TBF is automatically reset to 0 as soon as the slot is marked as filled and RTIE.TSFF=1.
+ If both TBF and TBE are set, then TBE wins. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TTCAN_Interrupt_Type TTCAN Interrupt Type
+ * @{
+ */
+#define CAN_TTC_INT_TIME_TRIG (CAN_TTCFG_TTIE) /*!< Time trigger interrupt. */
+#define CAN_TTC_INT_WATCH_TRIG (CAN_TTCFG_WTIE) /*!< Watch trigger interrupt. */
+#define CAN_TTC_INT_ALL (CAN_TTC_INT_TIME_TRIG | \
+ CAN_TTC_INT_WATCH_TRIG)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TTCAN_Status_Flag TTCAN Status Flag
+ * @{
+ */
+#define CAN_TTC_FLAG_TIME_TRIG (CAN_TTCFG_TTIF) /*!< Time trigger interrupt flag. */
+#define CAN_TTC_FLAG_TRIG_ERR (CAN_TTCFG_TEIF) /*!< Trigger error interrupt flag. */
+#define CAN_TTC_FLAG_WATCH_TRIG (CAN_TTCFG_WTIF) /*!< Watch trigger interrupt flag. */
+
+#define CAN_TTC_FLAG_ALL (CAN_TTC_FLAG_TIME_TRIG | \
+ CAN_TTC_FLAG_TRIG_ERR | \
+ CAN_TTC_FLAG_WATCH_TRIG)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TTCAN_NTU_Prescaler TTCAN Network Time Unit Prescaler
+ * @{
+ */
+#define CAN_TTC_NTU_PRESCALER1 (0x0U) /*!< NTU is SBT bit time * 1. */
+#define CAN_TTC_NTU_PRESCALER2 (CAN_TTCFG_T_PRESC_0) /*!< NTU is SBT bit time * 2. */
+#define CAN_TTC_NTU_PRESCALER4 (CAN_TTCFG_T_PRESC_1) /*!< NTU is SBT bit time * 4. */
+#define CAN_TTC_NTU_PRESCALER8 (CAN_TTCFG_T_PRESC) /*!< NTU is SBT bit time * 8. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TTCAN_Trigger_Type TTCAN Trigger Type
+ * @note Except for the immediate trigger, all triggers set TTIF if TTIE is enabled.
+ * @{
+ */
+#define CAN_TTC_TRIG_IMMED_TRIG (0x0U) /*!< Immediate trigger for immediate transmission. */
+#define CAN_TTC_TRIG_TIME_TRIG (CAN_TRG_CFG_TTYPE_0) /*!< Time trigger for receive triggers. */
+#define CAN_TTC_TRIG_SINGLESHOT_TX_TRIG (CAN_TRG_CFG_TTYPE_1) /*!< Single shot transmit trigger for exclusive time windows. */
+#define CAN_TTC_TRIG_TX_START_TRIG (CAN_TRG_CFG_TTYPE_1 | \
+ CAN_TRG_CFG_TTYPE_0) /*!< Transmit start trigger for merged arbitrating time windows. */
+#define CAN_TTC_TRIG_TX_STOP_TRIG (CAN_TRG_CFG_TTYPE_2) /*!< Transmit stop trigger for merged arbitrating time windows. */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup CAN_Global_Functions
+ * @{
+ */
+/* Classical CAN */
+int32_t CAN_Init(CM_CAN_TypeDef *CANx, const stc_can_init_t *pstcCanInit);
+int32_t CAN_StructInit(stc_can_init_t *pstcCanInit);
+void CAN_DeInit(CM_CAN_TypeDef *CANx);
+void CAN_IntCmd(CM_CAN_TypeDef *CANx, uint32_t u32IntType, en_functional_state_t enNewState);
+int32_t CAN_FillTxFrame(CM_CAN_TypeDef *CANx, uint8_t u8TxBufType, const stc_can_tx_frame_t *pstcTx);
+void CAN_StartTx(CM_CAN_TypeDef *CANx, uint8_t u8TxRequest);
+void CAN_AbortTx(CM_CAN_TypeDef *CANx, uint8_t u8TxBufType);
+int32_t CAN_GetRxFrame(CM_CAN_TypeDef *CANx, stc_can_rx_frame_t *pstcRx);
+
+void CAN_EnterLocalReset(CM_CAN_TypeDef *CANx);
+void CAN_ExitLocalReset(CM_CAN_TypeDef *CANx);
+en_flag_status_t CAN_GetLocalResetStatus(CM_CAN_TypeDef *CANx);
+
+en_flag_status_t CAN_GetStatus(const CM_CAN_TypeDef *CANx, uint32_t u32Flag);
+void CAN_ClearStatus(CM_CAN_TypeDef *CANx, uint32_t u32Flag);
+uint32_t CAN_GetStatusValue(const CM_CAN_TypeDef *CANx);
+int32_t CAN_GetErrorInfo(const CM_CAN_TypeDef *CANx, stc_can_error_info_t *pstcErr);
+uint8_t CAN_GetTxBufStatus(const CM_CAN_TypeDef *CANx);
+uint8_t CAN_GetRxBufStatus(const CM_CAN_TypeDef *CANx);
+void CAN_FilterCmd(CM_CAN_TypeDef *CANx, uint16_t u16FilterSelect, en_functional_state_t enNewState);
+void CAN_SetRxWarnLimit(CM_CAN_TypeDef *CANx, uint8_t u8RxWarnLimit);
+void CAN_SetErrorWarnLimit(CM_CAN_TypeDef *CANx, uint8_t u8ErrorWarnLimit);
+
+int32_t CAN_FD_StructInit(stc_canfd_config_t *pstcCanFd);
+void CAN_FD_Cmd(const CM_CAN_TypeDef *CANx, en_functional_state_t enNewState);
+
+/* TTCAN */
+int32_t CAN_TTC_StructInit(stc_can_ttc_config_t *pstcCanTtc);
+int32_t CAN_TTC_Config(CM_CAN_TypeDef *CANx, const stc_can_ttc_config_t *pstcCanTtc);
+void CAN_TTC_IntCmd(CM_CAN_TypeDef *CANx, uint8_t u8IntType, en_functional_state_t enNewState);
+void CAN_TTC_Cmd(CM_CAN_TypeDef *CANx, en_functional_state_t enNewState);
+
+en_flag_status_t CAN_TTC_GetStatus(const CM_CAN_TypeDef *CANx, uint8_t u8Flag);
+void CAN_TTC_ClearStatus(CM_CAN_TypeDef *CANx, uint8_t u8Flag);
+uint8_t CAN_TTC_GetStatusValue(const CM_CAN_TypeDef *CANx);
+
+void CAN_TTC_SetTriggerType(CM_CAN_TypeDef *CANx, uint16_t u16TriggerType);
+void CAN_TTC_SetTxEnableWindow(CM_CAN_TypeDef *CANx, uint16_t u16TxEnableWindow);
+void CAN_TTC_SetTxTriggerTime(CM_CAN_TypeDef *CANx, uint16_t u16TxTriggerTime);
+void CAN_TTC_SetWatchTriggerTime(CM_CAN_TypeDef *CANx, uint16_t u16WatchTriggerTime);
+
+int32_t CAN_TTC_FillTxFrame(CM_CAN_TypeDef *CANx, uint8_t u8CANTTCTxBuf, const stc_can_tx_frame_t *pstcTx);
+
+int32_t CAN_TTC_GetConfig(const CM_CAN_TypeDef *CANx, stc_can_ttc_config_t *pstcCanTtc);
+
+/**
+ * @}
+ */
+
+#endif /* LL_CAN_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_CAN_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_clk.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_clk.h
new file mode 100644
index 0000000000..3de4b1233e
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_clk.h
@@ -0,0 +1,700 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_clk.h
+ * @brief This file contains all the functions prototypes of the CLK driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-12-15 CDT Modify comment
+ Refine API CLK_XtalStdInit. and add API CLK_XtalStdCmd, CLK_SetXtalStdExceptionType
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_CLK_H__
+#define __HC32_LL_CLK_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_CLK
+ * @{
+ */
+
+#if (LL_CLK_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup CLK_Global_Types CLK Global Types
+ * @{
+ */
+/**
+ * @brief CLK XTAL configuration structure definition
+ */
+typedef struct {
+ uint8_t u8State; /*!< The new state of the XTAL.
+ This parameter can be a value of @ref CLK_XTAL_State */
+ uint8_t u8Drv; /*!< The XTAL drive ability.
+ This parameter can be a value of @ref CLK_XTAL_Driver */
+ uint8_t u8Mode; /*!< The XTAL mode selection osc or exclk.
+ This parameter can be a value of @ref CLK_XTAL_Mode_Selection */
+ uint8_t u8StableTime; /*!< The XTAL stable time selection.
+ This parameter can be a value of @ref CLK_XTAL_Stable_Time_Selection */
+} stc_clock_xtal_init_t;
+
+/**
+ * @brief CLK XTAL fault detect configuration structure definition
+ */
+typedef struct {
+ uint8_t u8State; /*!< Specifies the new state of XTALSTD.
+ This parameter can be a value of @ref CLK_XTALSTD_State */
+ uint8_t u8ExceptionType; /*!< Specifies the XTALSTD exception type.
+ This parameter can be a value of @ref CLK_XTALSTD_Exception_type */
+} stc_clock_xtalstd_init_t;
+
+/**
+ * @brief CLK XTAL divide structure definition
+ */
+typedef struct {
+ uint32_t u32State; /*!< The new state of the XTAL divide.
+ This parameter can be a value of @ref CLK_XTALDIV_State */
+ uint32_t u32Num; /*!< The numerator of XTAL divide. */
+ uint32_t u32Den; /*!< The denominator of XTAL divide. */
+} stc_clock_xtaldiv_init_t;
+
+/**
+ * @brief CLK XTAL32 configuration structure definition
+ */
+typedef struct {
+ uint8_t u8State; /*!< The new state of the XTAL32 divide.
+ This parameter can be a value of @ref CLK_XTAL32_State */
+ uint8_t u8Drv; /*!< The Xtal32 drive ability setting,
+ This parameter can be a value of @ref CLK_XTAL32_Drive */
+ uint8_t u8Filter; /*!< Xtal32 noise filter setting,
+ This parameter can be a value of@ref CLK_XTAL32_Filter_Selection */
+} stc_clock_xtal32_init_t;
+
+/**
+ * @brief CLK clock frequency configuration structure definition
+ */
+typedef struct {
+ union {
+ uint32_t SCFGR; /*!< clock frequency config register */
+ struct {
+ uint32_t PCLK0S : 3; /*!< PCLK0 */
+ uint32_t resvd0 : 1; /*!< reserved */
+ uint32_t PCLK1S : 3; /*!< PCLK1 */
+ uint32_t resvd1 : 1; /*!< reserved */
+ uint32_t PCLK2S : 3; /*!< PCLK2 */
+ uint32_t resvd2 : 1; /*!< reserved */
+ uint32_t PCLK3S : 3; /*!< PCLK3 */
+ uint32_t resvd3 : 1; /*!< reserved */
+ uint32_t PCLK4S : 3; /*!< PCLK4 */
+ uint32_t resvd4 : 1; /*!< reserved */
+ uint32_t EXCKS : 3; /*!< EXCLK */
+ uint32_t resvd5 : 1; /*!< reserved */
+ uint32_t HCLKS : 3; /*!< HCLK */
+ uint32_t resvd6 : 5; /*!< reserved */
+ } SCFGR_f;
+ };
+} stc_clock_scale_t;
+
+/**
+ * @brief CLK PLL configuration structure definition
+ */
+typedef struct {
+ uint8_t u8PLLState; /*!< PLL new state, @ref CLK_PLL_State for details */
+ union {
+ uint32_t PLLCFGR; /*!< PLL config register */
+ struct {
+ uint32_t PLLM : 5; /*!< PLL M divide */
+ uint32_t resvd0 : 2; /*!< reserved */
+ uint32_t PLLSRC : 1; /*!< PLL/PLLA source clock select */
+ uint32_t PLLN : 9; /*!< PLL N multi */
+ uint32_t resvd1 : 3; /*!< reserved */
+ uint32_t PLLR : 4; /*!< PLL R divide */
+ uint32_t PLLQ : 4; /*!< PLL Q divide */
+ uint32_t PLLP : 4; /*!< PLL P divide */
+ } PLLCFGR_f;
+ };
+} stc_clock_pll_init_t;
+
+/**
+ * @brief CLK bus frequency structure definition
+ */
+typedef struct {
+ uint32_t u32SysclkFreq; /*!< System clock frequency. */
+ uint32_t u32HclkFreq; /*!< Hclk frequency. */
+ uint32_t u32Pclk0Freq; /*!< Pclk0 frequency. */
+ uint32_t u32Pclk1Freq; /*!< Pclk1 frequency. */
+ uint32_t u32Pclk2Freq; /*!< Pclk2 frequency. */
+ uint32_t u32Pclk3Freq; /*!< Pclk3 frequency. */
+ uint32_t u32Pclk4Freq; /*!< Pclk4 frequency. */
+ uint32_t u32ExclkFreq; /*!< Exclk frequency. */
+} stc_clock_freq_t;
+
+/**
+ * @brief CLK PLL clock frequency structure definition
+ */
+typedef struct {
+ uint32_t u32PllVcin; /*!< PLL vcin clock frequency. */
+ uint32_t u32PllVco; /*!< PLL vco clock frequency. */
+ uint32_t u32PllP; /*!< PLLp clock frequency. */
+ uint32_t u32PllQ; /*!< PLLq clock frequency. */
+ uint32_t u32PllR; /*!< PLLr clock frequency. */
+} stc_pll_clock_freq_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup CLK_Global_Macros CLK Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup CLK_PLL_State PLL state on or off
+ * @{
+ */
+#define CLK_PLL_OFF (0x01U)
+#define CLK_PLL_ON (0x00U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_PLL_Source_Clock PLL source clock selection
+ * @{
+ */
+#define CLK_PLL_SRC_XTAL (0x00UL)
+#define CLK_PLL_SRC_HRC (0x01UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_XTAL_State XTAL function config
+ * @{
+ */
+#define CLK_XTAL_OFF (CMU_XTALCR_XTALSTP)
+#define CLK_XTAL_ON (0x00U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_XTAL_Driver XTAL drive ability
+ * @note
+ * @verbatim
+ * High | Mid | Low | ULow |
+ * [20~25] | [16~20) | (8~16) | [4~8] |
+ * @endverbatim
+ * @{
+ */
+#define CLK_XTAL_DRV_HIGH (0x00U << CMU_XTALCFGR_XTALDRV_POS)
+#define CLK_XTAL_DRV_MID (0x01U << CMU_XTALCFGR_XTALDRV_POS)
+#define CLK_XTAL_DRV_LOW (0x02U << CMU_XTALCFGR_XTALDRV_POS)
+#define CLK_XTAL_DRV_ULOW (0x03U << CMU_XTALCFGR_XTALDRV_POS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_XTAL_Mode_Selection XTAL mode selection osc or exclk
+ * @{
+ */
+#define CLK_XTAL_MD_OSC (0x00U)
+#define CLK_XTAL_MD_EXCLK (CMU_XTALCFGR_XTALMS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_XTAL_Stable_Time_Selection XTAL stable time selection
+ * @note a cycle of stable counter = a cycle of LRC divide by 8
+ * @{
+ */
+#define CLK_XTAL_STB_133US (0x01U) /*!< 35 stable count cycle, approx. 133us */
+#define CLK_XTAL_STB_255US (0x02U) /*!< 67 stable count cycle, approx. 255us */
+#define CLK_XTAL_STB_499US (0x03U) /*!< 131 stable count cycle, approx. 499us */
+#define CLK_XTAL_STB_988US (0x04U) /*!< 259 stable count cycle, approx. 988us */
+#define CLK_XTAL_STB_2MS (0x05U) /*!< 547 stable count cycle, approx. 2ms */
+#define CLK_XTAL_STB_4MS (0x06U) /*!< 1059 stable count cycle, approx. 4ms */
+#define CLK_XTAL_STB_8MS (0x07U) /*!< 2147 stable count cycle, approx. 8ms */
+#define CLK_XTAL_STB_16MS (0x08U) /*!< 4291 stable count cycle, approx. 16ms */
+#define CLK_XTAL_STB_31MS (0x09U) /*!< 8163 stable count cycle, approx. 32ms */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_XTALDIV_State XTAL divide state Config
+ * @{
+ */
+#define CLK_XTALDIV_OFF (0x00UL)
+#define CLK_XTALDIV_ON (CMU_XTALDIVCR_FRADIVEN)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_XTALSTD_State XTAL error detection on or off
+ * @{
+ */
+#define CLK_XTALSTD_OFF (0x00U)
+#define CLK_XTALSTD_ON (CMU_XTALSTDCR_XTALSTDE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_XTALSTD_Exception_type XTALSTD exception type
+ * @{
+ */
+#define CLK_XTALSTD_EXP_TYPE_NONE (0x00U)
+#define CLK_XTALSTD_EXP_TYPE_RST (CMU_XTALSTDCR_XTALSTDRIS | CMU_XTALSTDCR_XTALSTDRE)
+#define CLK_XTALSTD_EXP_TYPE_INT (CMU_XTALSTDCR_XTALSTDIE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_XTAL32_State XTAL32 state on or off
+ * @{
+ */
+#define CLK_XTAL32_OFF (CMU_XTAL32CR_XTAL32STP)
+#define CLK_XTAL32_ON (0x00U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_XTAL32_Drive XTAL32 drive ability
+ * @{
+ */
+#define CLK_XTAL32_DRV_MID (0x00U)
+#define CLK_XTAL32_DRV_HIGH (0x01U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_XTAL32_Filter_Selection XTAL32 filtering selection.
+ * @{
+ */
+#define CLK_XTAL32_FILTER_ALL_MD (0x00U) /*!< Valid in run,stop,power down mode. */
+#define CLK_XTAL32_FILTER_RUN_MD (0x01U) /*!< Valid in run mode. */
+#define CLK_XTAL32_FILTER_OFF (0x03U) /*!< Invalid in run,stop,power down mode. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_HRC_Config HRC Config
+ * @{
+ */
+#define CLK_HRC_OFF (CMU_HRCCR_HRCSTP)
+#define CLK_HRC_ON (0x00U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_STB_Flag CLK Stable Flags
+ * @{
+ */
+#define CLK_STB_FLAG_HRC (CMU_OSCSTBSR_HRCSTBF)
+#define CLK_STB_FLAG_XTAL (CMU_OSCSTBSR_XTALSTBF)
+#define CLK_STB_FLAG_PLL (CMU_OSCSTBSR_PLLHSTBF)
+#define CLK_STB_FLAG_MASK (CMU_OSCSTBSR_HRCSTBF | CMU_OSCSTBSR_XTALSTBF | CMU_OSCSTBSR_PLLHSTBF)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_System_Clock_Source System Clock Source
+ * @{
+ */
+#define CLK_SYSCLK_SRC_HRC (0x00U)
+#define CLK_SYSCLK_SRC_MRC (0x01U)
+#define CLK_SYSCLK_SRC_LRC (0x02U)
+#define CLK_SYSCLK_SRC_XTAL (0x03U)
+#define CLK_SYSCLK_SRC_XTAL32 (0x04U)
+#define CLK_SYSCLK_SRC_PLL (0x05U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_Bus_Clock_Sel Clock Bus Clock Category Selection
+ * @{
+ */
+#define CLK_BUS_PCLK0 (CMU_SCFGR_PCLK0S)
+#define CLK_BUS_PCLK1 (CMU_SCFGR_PCLK1S)
+#define CLK_BUS_PCLK2 (CMU_SCFGR_PCLK2S)
+#define CLK_BUS_PCLK3 (CMU_SCFGR_PCLK3S)
+#define CLK_BUS_PCLK4 (CMU_SCFGR_PCLK4S)
+#define CLK_BUS_EXCLK (CMU_SCFGR_EXCKS)
+#define CLK_BUS_HCLK (CMU_SCFGR_HCLKS)
+#define CLK_BUS_CLK_ALL (CLK_BUS_PCLK0 | CLK_BUS_PCLK1 | CLK_BUS_PCLK2 | CLK_BUS_PCLK3 | \
+ CLK_BUS_PCLK4 | CLK_BUS_EXCLK | CLK_BUS_HCLK)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_Clock_Divider Clock Divider
+ * @{
+ */
+
+/**
+ * @defgroup CLK_System_Clock_Divider System Clock Divider
+ * @{
+ */
+#define CLK_SYSCLK_DIV1 (0x00U)
+#define CLK_SYSCLK_DIV2 (0x01U)
+#define CLK_SYSCLK_DIV4 (0x02U)
+#define CLK_SYSCLK_DIV8 (0x03U)
+#define CLK_SYSCLK_DIV16 (0x04U)
+#define CLK_SYSCLK_DIV32 (0x05U)
+#define CLK_SYSCLK_DIV64 (0x06U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_HCLK_Divider CLK HCLK Divider
+ * @{
+ */
+#define CLK_HCLK_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_HCLKS_POS)
+#define CLK_HCLK_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_HCLKS_POS)
+#define CLK_HCLK_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_HCLKS_POS)
+#define CLK_HCLK_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_HCLKS_POS)
+#define CLK_HCLK_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_HCLKS_POS)
+#define CLK_HCLK_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_HCLKS_POS)
+#define CLK_HCLK_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_HCLKS_POS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_PCLK1_Divider CLK PCLK1 Divider
+ * @{
+ */
+#define CLK_PCLK1_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK1S_POS)
+#define CLK_PCLK1_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK1S_POS)
+#define CLK_PCLK1_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK1S_POS)
+#define CLK_PCLK1_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK1S_POS)
+#define CLK_PCLK1_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK1S_POS)
+#define CLK_PCLK1_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK1S_POS)
+#define CLK_PCLK1_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK1S_POS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_PCLK4_Divider CLK PCLK4 Divider
+ * @{
+ */
+#define CLK_PCLK4_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK4S_POS)
+#define CLK_PCLK4_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK4S_POS)
+#define CLK_PCLK4_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK4S_POS)
+#define CLK_PCLK4_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK4S_POS)
+#define CLK_PCLK4_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK4S_POS)
+#define CLK_PCLK4_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK4S_POS)
+#define CLK_PCLK4_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK4S_POS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_PCLK3_Divider CLK PCLK3 Divider
+ * @{
+ */
+#define CLK_PCLK3_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK3S_POS)
+#define CLK_PCLK3_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK3S_POS)
+#define CLK_PCLK3_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK3S_POS)
+#define CLK_PCLK3_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK3S_POS)
+#define CLK_PCLK3_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK3S_POS)
+#define CLK_PCLK3_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK3S_POS)
+#define CLK_PCLK3_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK3S_POS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_EXCLK_Divider CLK EXCLK Divider
+ * @{
+ */
+#define CLK_EXCLK_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_EXCKS_POS)
+#define CLK_EXCLK_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_EXCKS_POS)
+#define CLK_EXCLK_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_EXCKS_POS)
+#define CLK_EXCLK_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_EXCKS_POS)
+#define CLK_EXCLK_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_EXCKS_POS)
+#define CLK_EXCLK_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_EXCKS_POS)
+#define CLK_EXCLK_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_EXCKS_POS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_PCLK2_Divider CLK PCLK2 Divider
+ * @{
+ */
+#define CLK_PCLK2_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK2S_POS)
+#define CLK_PCLK2_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK2S_POS)
+#define CLK_PCLK2_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK2S_POS)
+#define CLK_PCLK2_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK2S_POS)
+#define CLK_PCLK2_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK2S_POS)
+#define CLK_PCLK2_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK2S_POS)
+#define CLK_PCLK2_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK2S_POS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_PCLK0_Divider CLK PCLK0 Divider
+ * @{
+ */
+#define CLK_PCLK0_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK0S_POS)
+#define CLK_PCLK0_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK0S_POS)
+#define CLK_PCLK0_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK0S_POS)
+#define CLK_PCLK0_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK0S_POS)
+#define CLK_PCLK0_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK0S_POS)
+#define CLK_PCLK0_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK0S_POS)
+#define CLK_PCLK0_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK0S_POS)
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_USBCLK_Sel CLK USB Clock Selection
+ * @{
+ */
+#define CLK_USBCLK_SYSCLK_DIV2 (0x01U << CMU_USBCKCFGR_USBCKS_POS)
+#define CLK_USBCLK_SYSCLK_DIV3 (0x02U << CMU_USBCKCFGR_USBCKS_POS)
+#define CLK_USBCLK_SYSCLK_DIV4 (0x03U << CMU_USBCKCFGR_USBCKS_POS)
+#define CLK_USBCLK_SYSCLK_DIV5 (0x04U << CMU_USBCKCFGR_USBCKS_POS)
+#define CLK_USBCLK_SYSCLK_DIV6 (0x05U << CMU_USBCKCFGR_USBCKS_POS)
+#define CLK_USBCLK_SYSCLK_DIV7 (0x06U << CMU_USBCKCFGR_USBCKS_POS)
+#define CLK_USBCLK_SYSCLK_DIV8 (0x07U << CMU_USBCKCFGR_USBCKS_POS)
+#define CLK_USBCLK_PLLQ (0x08U << CMU_USBCKCFGR_USBCKS_POS)
+#define CLK_USBCLK_PLLR (0x09U << CMU_USBCKCFGR_USBCKS_POS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_CANCLK_Sel CLK CAN Clock Selection
+ * @{
+ */
+#define CLK_CANCLK_SYSCLK_DIV2 (0x01U)
+#define CLK_CANCLK_SYSCLK_DIV3 (0x02U)
+#define CLK_CANCLK_SYSCLK_DIV4 (0x03U)
+#define CLK_CANCLK_SYSCLK_DIV5 (0x04U)
+#define CLK_CANCLK_SYSCLK_DIV6 (0x05U)
+#define CLK_CANCLK_SYSCLK_DIV7 (0x06U)
+#define CLK_CANCLK_SYSCLK_DIV8 (0x07U)
+#define CLK_CANCLK_PLLQ (0x08U)
+#define CLK_CANCLK_PLLR (0x09U)
+#define CLK_CANCLK_XTAL (0x0DU)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_CAN_Sel CLK CAN Channel Selection
+ * @{
+ */
+#define CLK_CAN1 (0x01U)
+#define CLK_CAN2 (0x02U)
+#define CLK_CAN3 (0x04U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_PERIPH_Sel CLK Peripheral Clock Selection
+ * @note ADC,I2S,DAC,TRNG
+ * @{
+ */
+/* PCLK2 is used for ADC clock, PCLK4 is used for DAC/TRNG clock */
+#define CLK_PERIPHCLK_PCLK (0x0000U)
+#define CLK_PERIPHCLK_PLLQ (0x0008U)
+#define CLK_PERIPHCLK_PLLR (0x0009U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_TPIU_Divider TPIU clock divider
+ * @{
+ */
+#define CLK_TPIUCLK_DIV1 (0x00U)
+#define CLK_TPIUCLK_DIV2 (0x01U)
+#define CLK_TPIUCLK_DIV4 (0x02U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_MCO_Channel_Sel CLK MCO Channel Select
+ * @{
+ */
+#define CLK_MCO1 (0x00U)
+#define CLK_MCO2 (0x01U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_MCO_Clock_Source CLK MCO Clock Source
+ * @{
+ */
+#define CLK_MCO_SRC_HRC (0x00U)
+#define CLK_MCO_SRC_MRC (0x01U)
+#define CLK_MCO_SRC_LRC (0x02U)
+#define CLK_MCO_SRC_XTAL (0x03U)
+#define CLK_MCO_SRC_XTAL32 (0x04U)
+#define CLK_MCO_SRC_PLLP (0x06U)
+#define CLK_MCO_SRC_PLLQ (0x08U)
+#define CLK_MCO_SRC_HCLK (0x0BU)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_MCO_Clock_Prescaler CLK MCO Clock Prescaler
+ * @{
+ */
+#define CLK_MCO_DIV1 (0x00U << CMU_MCOCFGR_MCODIV_POS)
+#define CLK_MCO_DIV2 (0x01U << CMU_MCOCFGR_MCODIV_POS)
+#define CLK_MCO_DIV4 (0x02U << CMU_MCOCFGR_MCODIV_POS)
+#define CLK_MCO_DIV8 (0x03U << CMU_MCOCFGR_MCODIV_POS)
+#define CLK_MCO_DIV16 (0x04U << CMU_MCOCFGR_MCODIV_POS)
+#define CLK_MCO_DIV32 (0x05U << CMU_MCOCFGR_MCODIV_POS)
+#define CLK_MCO_DIV64 (0x06U << CMU_MCOCFGR_MCODIV_POS)
+#define CLK_MCO_DIV128 (0x07U << CMU_MCOCFGR_MCODIV_POS)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup CLK_Global_Functions
+ * @{
+ */
+int32_t CLK_HrcCmd(en_functional_state_t enNewState);
+int32_t CLK_MrcCmd(en_functional_state_t enNewState);
+int32_t CLK_LrcCmd(en_functional_state_t enNewState);
+
+void CLK_HrcTrim(int8_t i8TrimVal);
+void CLK_MrcTrim(int8_t i8TrimVal);
+void CLK_LrcTrim(int8_t i8TrimVal);
+
+int32_t CLK_XtalStructInit(stc_clock_xtal_init_t *pstcXtalInit);
+int32_t CLK_XtalInit(const stc_clock_xtal_init_t *pstcXtalInit);
+int32_t CLK_XtalCmd(en_functional_state_t enNewState);
+
+void CLK_XtalDivCmd(en_functional_state_t enNewState);
+int32_t CLK_XtalDivStructInit(stc_clock_xtaldiv_init_t *pstcXtalDivInit);
+int32_t CLK_XtalDivInit(const stc_clock_xtaldiv_init_t *pstcXtalDivInit);
+
+void CLK_XtalStdCmd(en_functional_state_t enNewState);
+int32_t CLK_XtalStdInit(uint8_t u8State, uint8_t u8ExceptionType);
+int32_t CLK_SetXtalStdExceptionType(uint8_t u8ExceptionType);
+void CLK_ClearXtalStdStatus(void);
+en_flag_status_t CLK_GetXtalStdStatus(void);
+
+int32_t CLK_Xtal32StructInit(stc_clock_xtal32_init_t *pstcXtal32Init);
+int32_t CLK_Xtal32Init(const stc_clock_xtal32_init_t *pstcXtal32Init);
+int32_t CLK_Xtal32Cmd(en_functional_state_t enNewState);
+
+void CLK_SetPLLSrc(uint32_t u32PllSrc);
+int32_t CLK_PLLStructInit(stc_clock_pll_init_t *pstcPLLInit);
+int32_t CLK_PLLInit(const stc_clock_pll_init_t *pstcPLLInit);
+int32_t CLK_PLLCmd(en_functional_state_t enNewState);
+int32_t CLK_GetPLLClockFreq(stc_pll_clock_freq_t *pstcPllClkFreq);
+
+void CLK_MCOConfig(uint8_t u8Ch, uint8_t u8Src, uint8_t u8Div);
+void CLK_MCOCmd(uint8_t u8Ch, en_functional_state_t enNewState);
+
+en_flag_status_t CLK_GetStableStatus(uint8_t u8Flag);
+void CLK_SetSysClockSrc(uint8_t u8Src);
+void CLK_SetClockDiv(uint32_t u32Clock, uint32_t u32Div);
+int32_t CLK_GetClockFreq(stc_clock_freq_t *pstcClockFreq);
+uint32_t CLK_GetBusClockFreq(uint32_t u32Clock);
+
+void CLK_SetPeriClockSrc(uint16_t u16Src);
+void CLK_SetUSBClockSrc(uint8_t u8Src);
+void CLK_SetCANClockSrc(uint8_t u8Unit, uint8_t u8Src);
+
+void CLK_TpiuClockCmd(en_functional_state_t enNewState);
+void CLK_SetTpiuClockDiv(uint8_t u8Div);
+/**
+ * @}
+ */
+
+#endif /* LL_CLK_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_CLK_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_cmp.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_cmp.h
new file mode 100644
index 0000000000..4cec59fc70
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_cmp.h
@@ -0,0 +1,487 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_cmp.h
+ * @brief This file contains all the functions prototypes of the CMP driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-12-15 CDT Modify comments related to chip series
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_CMP_H__
+#define __HC32_LL_CMP_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_CMP
+ * @{
+ */
+
+#if (LL_CMP_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup CMP_Global_Types CMP Global Types
+ * @{
+ */
+
+/**
+ * @brief CMP normal mode configuration structure
+ */
+typedef struct {
+ uint16_t u16PositiveInput; /*!< Positive(compare voltage) input @ref CMP_Positive_Input_Select */
+ uint16_t u16NegativeInput; /*!< Negative(Reference voltage) input @ref CMP_Negative_Input_Select */
+ uint16_t u16OutPolarity; /*!< Output polarity select, @ref CMP_Out_Polarity_Select */
+ uint16_t u16OutDetectEdge; /*!< Output detect edge, @ref CMP_Out_Detect_Edge_Select */
+ uint16_t u16OutFilter; /*!< Output Filter, @ref CMP_Out_Filter */
+ uint16_t u16HystVoltage; /*!< CMP hysteresis voltage @ref CMP_Hyst_Voltage */
+} stc_cmp_init_t;
+
+/**
+ * @brief CMP window mode configuration structure
+ */
+typedef struct {
+ uint16_t u16PositiveInput; /*!< Window mode Positive(compare voltage) input @ref CMP_Window_Positive_Select */
+ uint16_t u16WinVolLow; /*!< CMP reference low voltage for window mode @ref CMP_Window_Low_Select */
+ uint16_t u16WinVolHigh; /*!< CMP reference high voltage for window mode @ref CMP_Window_High_Select */
+ uint16_t u16OutPolarity; /*!< Output polarity select, @ref CMP_Out_Polarity_Select */
+ uint16_t u16OutDetectEdge; /*!< Output detect edge, @ref CMP_Out_Detect_Edge_Select */
+ uint16_t u16OutFilter; /*!< Output Filter, @ref CMP_Out_Filter */
+ uint16_t u16HystVoltage; /*!< CMP hysteresis voltage @ref CMP_Hyst_Voltage */
+} stc_cmp_window_init_t;
+
+/**
+ * @brief CMP blank window function configuration structure
+ */
+typedef struct {
+ uint8_t u8Mode; /*!< blank window mode select, @ref CMP_BlankWindow_Mode */
+ uint16_t u16Src; /*!< blank window source select,
+ can be any combination of @ref CMP_BlankWindow_Src */
+ uint16_t u16ValidLevelEdge; /*!< Valid level for blank window level mode @ref CMP_BlankWindow_Valid_Level
+ Valid edge for blank window edge mode @ref CMP_BlankWindow_Valid_Edge */
+ uint16_t u16MaskWidth; /*!< Mask width when valid edge occurs for blank window edge mode, which range
+ from 0~255 */
+ uint8_t u8OutLevel; /*!< CMP output level when blank window valid @ref CMP_BlankWindow_output_Level */
+} stc_cmp_blankwindow_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/**
+ * @defgroup CMP_Global_Macros CMP Global Macros
+ * @{
+ */
+
+#define VISR_OFFSET (8U)
+
+/**
+ * @defgroup CMP_Window_Mode_Unit CMP Window Mode Unit
+ * @{
+ */
+#define CMP_WIN_CMP12 (0x01U)
+#define CMP_WIN_CMP34 (0x02U) /* Only effective for HC32F472KCHI/HC32F472KEHI */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CMP_Positive_Input_Select CMP Positive(Compare) Voltage Input
+ * @{
+ */
+#define CMP_POSITIVE_NONE (0x0U)
+/* Positive input select table
+ CMP1 CMP2 CMP3 CMP4
+-------------------------------------
+INP1 PA1 PA1 PB0 PB0
+INP2 PA3 PA3 PB11 PB11
+INP3 PA4 PA4 PGA1 PGA1 (Only effective for HC32F472KCHI/HC32F472KEHI)
+INP4 PA7 PA7 PGA2 PGA2 (Only effective for HC32F472KCHI/HC32F472KEHI)
+*/
+#define CMP_POSITIVE_INP1 (CMP_PMSR_CVSL_0 >> CMP_PMSR_CVSL_POS)
+#define CMP_POSITIVE_INP2 (CMP_PMSR_CVSL_1 >> CMP_PMSR_CVSL_POS)
+#define CMP_POSITIVE_INP3 (CMP_PMSR_CVSL_2 >> CMP_PMSR_CVSL_POS)
+#define CMP_POSITIVE_INP4 (CMP_PMSR_CVSL_3 >> CMP_PMSR_CVSL_POS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CMP_Window_Positive_Select CMP Window Mode positive(compare) Voltage
+ * @{
+ */
+#define CMP_WIN_POSITIVE_NONE (0x0U)
+/* Positive input select table for window mode
+ WIN_CMP12 WIN_CMP34
+----------------------------------------------
+INP1 PA1 PB0
+INP2 PA3 PB11
+INP3 PA4 PGA1 (Only effective for HC32F472KCHI/HC32F472KEHI)
+INP4 PA7 PGA2 (Only effective for HC32F472KCHI/HC32F472KEHI)
+*/
+#define CMP_WIN_POSITIVE_INP1 (CMP_PMSR_CVSL_0 >> CMP_PMSR_CVSL_POS)
+#define CMP_WIN_POSITIVE_INP2 (CMP_PMSR_CVSL_1 >> CMP_PMSR_CVSL_POS)
+#define CMP_WIN_POSITIVE_INP3 (CMP_PMSR_CVSL_2 >> CMP_PMSR_CVSL_POS)
+#define CMP_WIN_POSITIVE_INP4 (CMP_PMSR_CVSL_3 >> CMP_PMSR_CVSL_POS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CMP_Negative_Input_Select CMP Negative(Reference) Voltage Input
+ * @{
+ */
+#define CMP_NEGATIVE_NONE (0x0U)
+/* Negative input select table for HC32F472KCHI/HC32F472KEHI
+ CMP1 CMP2 CMP3 CMP4
+-------------------------------------------------------
+INM1 VREF*1/4 VREF*1/4 VREF*1/4 VREF*1/4
+INM2 VREF*1/2 VREF*1/2 VREF*1/2 VREF*1/2
+INM3 VREF*3/4 VREF*3/4 VREF*3/4 VREF*3/4
+INM4 VREF VREF VREF VREF
+INM5 DA3O2 DA1O2 DA2O1 DA2O2
+INM6 DA3O1 DA3O1 DA3O1 DA3O1
+INM7 PA0 PA2 PB15 PB2
+INM8 PA2 PA4 PA4 PA4
+INM9 PA4 PA6 PA5 PA5
+INM10 PA5 PA7 PA7 PA6
+*/
+/* Negative input select table for HC32F472JCTI/HC32F472JETI/HC32F472PCTI/HC32F472PETI
+ CMP1 CMP2
+------------------------------
+INM1 VREF*1/4 VREF*1/4
+INM2 VREF*1/2 VREF*1/2
+INM3 VREF*3/4 VREF*3/4
+INM4 VREF VREF
+INM5 DA1O1 DA1O2
+INM6 DA1O2 DA1O2
+INM7 PA0 PA2
+INM8 PA2 -
+*/
+#define CMP_NEGATIVE_INM1 (CMP_PMSR_RVSL_0)
+#define CMP_NEGATIVE_INM2 (CMP_PMSR_RVSL_1)
+#define CMP_NEGATIVE_INM3 (CMP_PMSR_RVSL_2)
+#define CMP_NEGATIVE_INM4 (CMP_PMSR_RVSL_3)
+#define CMP_NEGATIVE_INM5 (CMP_PMSR_RVSL_4)
+#define CMP_NEGATIVE_INM6 (CMP_PMSR_RVSL_5)
+#define CMP_NEGATIVE_INM7 (CMP_PMSR_RVSL_6)
+#define CMP_NEGATIVE_INM8 (CMP_PMSR_RVSL_7)
+#define CMP_NEGATIVE_INM9 (CMP_PMSR_RVSL_8)
+#define CMP_NEGATIVE_INM10 (CMP_PMSR_RVSL_9)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CMP_Window_Low_Select CMP Window Mode Window Low Voltage
+ * @{
+ */
+#define CMP_WIN_LOW_NONE (0x0U)
+/* Window mode low voltage select table
+ WIN_CMP12 WIN_CMP34
+--------------------------------
+INM1 VREF*1/4 VREF*1/4
+INM2 VREF*1/2 VREF*1/2
+INM3 VREF*3/4 VREF*3/4
+INM4 VREF VREF
+INM5 DA3O2 DA2O1
+INM6 DA3O1 DA3O1
+INM7 PA0 PB15
+INM8 PA2 PA4
+INM9 PA4 PA5 (Only effective for HC32F472KCHI/HC32F472KEHI)
+INM10 PA5 PA7 (Only effective for HC32F472KCHI/HC32F472KEHI)
+*/
+#define CMP_WIN_LOW_INM1 (CMP_PMSR_RVSL_0)
+#define CMP_WIN_LOW_INM2 (CMP_PMSR_RVSL_1)
+#define CMP_WIN_LOW_INM3 (CMP_PMSR_RVSL_2)
+#define CMP_WIN_LOW_INM4 (CMP_PMSR_RVSL_3)
+#define CMP_WIN_LOW_INM5 (CMP_PMSR_RVSL_4)
+#define CMP_WIN_LOW_INM6 (CMP_PMSR_RVSL_5)
+#define CMP_WIN_LOW_INM7 (CMP_PMSR_RVSL_6)
+#define CMP_WIN_LOW_INM8 (CMP_PMSR_RVSL_7)
+#define CMP_WIN_LOW_INM9 (CMP_PMSR_RVSL_8)
+#define CMP_WIN_LOW_INM10 (CMP_PMSR_RVSL_9)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CMP_Window_High_Select CMP Window Mode Window High Voltage
+ * @{
+ */
+#define CMP_WIN_HIGH_NONE (0x0U)
+/* Window mode high voltage select table
+ WIN_CMP12 WIN_CMP34
+-------------------------------------------------------
+INM1 VREF*1/4 VREF*1/4
+INM2 VREF*1/2 VREF*1/2
+INM3 VREF*3/4 VREF*3/4
+INM4 VREF VREF
+INM5 DA1O2 DA2O2
+INM6 DA3O1 DA3O1
+INM7 PA2 PB2
+INM8 PA4 PA4 (Only effective for HC32F472KCHI/HC32F472KEHI)
+INM9 PA6 PA5 (Only effective for HC32F472KCHI/HC32F472KEHI)
+INM10 PA7 PA6 (Only effective for HC32F472KCHI/HC32F472KEHI)
+*/
+#define CMP_WIN_HIGH_INM1 (CMP_PMSR_RVSL_0)
+#define CMP_WIN_HIGH_INM2 (CMP_PMSR_RVSL_1)
+#define CMP_WIN_HIGH_INM3 (CMP_PMSR_RVSL_2)
+#define CMP_WIN_HIGH_INM4 (CMP_PMSR_RVSL_3)
+#define CMP_WIN_HIGH_INM5 (CMP_PMSR_RVSL_4)
+#define CMP_WIN_HIGH_INM6 (CMP_PMSR_RVSL_5)
+#define CMP_WIN_HIGH_INM7 (CMP_PMSR_RVSL_6)
+#define CMP_WIN_HIGH_INM8 (CMP_PMSR_RVSL_7)
+#define CMP_WIN_HIGH_INM9 (CMP_PMSR_RVSL_8)
+#define CMP_WIN_HIGH_INM10 (CMP_PMSR_RVSL_9)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CMP_Out_Polarity_Select CMP Output Polarity
+ * @{
+ */
+#define CMP_OUT_INVT_OFF (0x0U) /*!< CMP output don't reverse */
+#define CMP_OUT_INVT_ON (CMP_OCR_COPS) /*!< CMP output level reverse */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CMP_Out_Detect_Edge_Select CMP Output Detect Edge
+ * @{
+ */
+#define CMP_DETECT_EDGS_NONE (0U) /*!< Do not detect edge */
+#define CMP_DETECT_EDGS_RISING (1U << CMP_FIR_EDGS_POS) /*!< Detect rising edge */
+#define CMP_DETECT_EDGS_FALLING (2U << CMP_FIR_EDGS_POS) /*!< Detect falling edge */
+#define CMP_DETECT_EDGS_BOTH (3U << CMP_FIR_EDGS_POS) /*!< Detect rising and falling edges */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CMP_Out_Filter CMP Output Filter Configuration
+ * @{
+ */
+#define CMP_OUT_FILTER_NONE (0U) /*!< Do not filter */
+#define CMP_OUT_FILTER_CLK (1U << CMP_FIR_FCKS_POS)
+#define CMP_OUT_FILTER_CLK_DIV2 (2U << CMP_FIR_FCKS_POS)
+#define CMP_OUT_FILTER_CLK_DIV4 (3U << CMP_FIR_FCKS_POS)
+#define CMP_OUT_FILTER_CLK_DIV8 (4U << CMP_FIR_FCKS_POS)
+#define CMP_OUT_FILTER_CLK_DIV16 (5U << CMP_FIR_FCKS_POS)
+#define CMP_OUT_FILTER_CLK_DIV32 (6U << CMP_FIR_FCKS_POS)
+#define CMP_OUT_FILTER_CLK_DIV64 (7U << CMP_FIR_FCKS_POS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CMP_BlankWindow_Src CMP Output blank window Function Control Signal
+ * @{
+ */
+/* Blank window PWM source select table
+ CMP1 CMP2 CMP3 CMP4
+------------------------------------------------------------------------
+SRC1 TIMA_1_PWM1 TIMA_3_PWM1 TIMA_1_PWM1 TIMA_2_PWM1
+SRC2 TIMA_1_PWM2 TIMA_3_PWM2 TIMA_1_PWM2 TIMA_2_PWM2
+SRC3 TIMA_1_PWM3 TIMA_3_PWM3 TIMA_1_PWM3 TIMA_2_PWM3
+SRC4 TIMA_2_PWM1 TIMA_4_PWM1 TIMA_3_PWM1 TIMA_4_PWM1
+SRC5 TIMA_2_PWM2 TIMA_4_PWM2 TIMA_3_PWM2 TIMA_4_PWM2
+SRC6 TIMA_2_PWM3 TIMA_4_PWM3 TIMA_3_PWM3 TIMA_4_PWM3
+SRC7 TIM6_1_PWMA TIM6_2_PWMA TIM6_1_PWMA TIM6_2_PWMA
+SRC8 TIM6_3_PWMA TIM6_4_PWMA TIM6_3_PWMA TIM6_4_PWMA
+SRC9 TIM6_5_PWMA TIM6_6_PWMA TIM6_5_PWMA TIM6_6_PWMA
+SRC10 TIM6_7_PWMA TIM6_8_PWMA TIM6_7_PWMA TIM6_8_PWMA
+SRC11 TIM4_1_OUH TIM4_1_OUH TIM4_1_OUH TIM4_1_OUH
+SRC12 TIM4_1_OUL TIM4_1_OUL TIM4_1_OUL TIM4_1_OUL
+SRC13 TIM4_1_OVH TIM4_1_OVH TIM4_1_OVH TIM4_1_OVH
+SRC14 TIM4_1_OVL TIM4_1_OVL TIM4_1_OVL TIM4_1_OVL
+SRC15 TIM4_1_OWH TIM4_1_OWH TIM4_1_OWH TIM4_1_OWH
+SRC16 TIM4_1_OWL TIM4_1_OWL TIM4_1_OWL TIM4_1_OWL
+*/
+#define CMP_BLANKWIN_SRC1 (CMP_BWSR1_CTWS0)
+#define CMP_BLANKWIN_SRC2 (CMP_BWSR1_CTWS1)
+#define CMP_BLANKWIN_SRC3 (CMP_BWSR1_CTWS2)
+#define CMP_BLANKWIN_SRC4 (CMP_BWSR1_CTWS3)
+#define CMP_BLANKWIN_SRC5 (CMP_BWSR1_CTWS4)
+#define CMP_BLANKWIN_SRC6 (CMP_BWSR1_CTWS5)
+#define CMP_BLANKWIN_SRC7 (CMP_BWSR1_CTWS6)
+#define CMP_BLANKWIN_SRC8 (CMP_BWSR1_CTWS7)
+#define CMP_BLANKWIN_SRC9 (CMP_BWSR1_CTWS8)
+#define CMP_BLANKWIN_SRC10 (CMP_BWSR1_CTWS9)
+#define CMP_BLANKWIN_SRC11 (CMP_BWSR1_CTWS10)
+#define CMP_BLANKWIN_SRC12 (CMP_BWSR1_CTWS11)
+#define CMP_BLANKWIN_SRC13 (CMP_BWSR1_CTWS12)
+#define CMP_BLANKWIN_SRC14 (CMP_BWSR1_CTWS13)
+#define CMP_BLANKWIN_SRC15 (CMP_BWSR1_CTWS14)
+#define CMP_BLANKWIN_SRC16 (CMP_BWSR1_CTWS15)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CMP_BlankWindow_Valid_Level CMP Blank Window Valid Level
+ * @{
+ */
+#define CMP_BLANKWIN_VALID_LVL_LOW (0U) /*!< Blank window valid level is low */
+#define CMP_BLANKWIN_VALID_LVL_HIGH (1U) /*!< Blank window valid level is high */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CMP_BlankWindow_output_Level CMP Output Level When Blank Windows Valid
+ * @{
+ */
+#define CMP_BLANKWIN_OUTPUT_LVL_LOW (0U) /*!< Output low when blank windows valid */
+#define CMP_BLANKWIN_OUTPUT_LVL_HIGH (1U << CMP_OCR_BWOL_POS) /*!< Output high when blank windows valid */
+#define CMP_BLANKWIN_OUTPUT_LVL_HOLD (2U << CMP_OCR_BWOL_POS) /*!< Output level hold when blank windows valid */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CMP_BlankWindow_Mode CMP Blank Windows Mode
+ * @{
+ */
+#define CMP_BLANKWIN_MD_LVL (0U)
+#define CMP_BLANKWIN_MD_EDGE (CMP_OCR_BWMD)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CMP_BlankWindow_Valid_Edge CMP Blank Windows valid edge for edge mode
+ * @{
+ */
+#define CMP_BLANKWIN_VALID_EDGE_NONE (0U) /*!< Blank window valid edge none */
+#define CMP_BLANKWIN_VALID_EDGE_RISING (CMP_BWSR2_TWEG_0) /*!< Blank window rising edge valid */
+#define CMP_BLANKWIN_VALID_EDGE_FALLING (CMP_BWSR2_TWEG_1) /*!< Blank window falling edge valid */
+#define CMP_BLANKWIN_VALID_EDGE_ALL (CMP_BWSR2_TWEG_0 | CMP_BWSR2_TWEG_1) /*!< Blank window all edge valid */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CMP_Hyst_Voltage CMP Hysteresis Voltage
+ * @{
+ */
+#define CMP_HYST_VOLT_NONE (0U)
+#define CMP_HYST_VOLT_10MV (1U << CMP_MDR_HYST_POS)
+#define CMP_HYST_VOLT_20MV (2U << CMP_MDR_HYST_POS)
+#define CMP_HYST_VOLT_30MV (3U << CMP_MDR_HYST_POS)
+#define CMP_HYST_VOLT_40MV (4U << CMP_MDR_HYST_POS)
+#define CMP_HYST_VOLT_50MV (5U << CMP_MDR_HYST_POS)
+#define CMP_HYST_VOLT_60MV (6U << CMP_MDR_HYST_POS)
+#define CMP_HYST_VOLT_70MV (7U << CMP_MDR_HYST_POS)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup CMP_Global_Functions
+ * @{
+ */
+/** Note: The parameter CMPx for CMP API
+ * HC32F472KCHI/HC32F472KEHI: CM_CMP1/CM_CMP2/CM_CMP3/CM_CMP4
+ * HC32F472JCTI/HC32F472JETI/HC32F472PCTI/HC32F472PETI: CM_CMP1/CM_CMP2
+ */
+
+int32_t CMP_StructInit(stc_cmp_init_t *pstcCmpInit);
+int32_t CMP_NormalModeInit(CM_CMP_TypeDef *CMPx, const stc_cmp_init_t *pstcCmpInit);
+void CMP_DeInit(CM_CMP_TypeDef *CMPx);
+
+void CMP_FuncCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState);
+void CMP_IntCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState);
+void CMP_CompareOutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState);
+void CMP_PinVcoutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState);
+en_flag_status_t CMP_GetStatus(const CM_CMP_TypeDef *CMPx);
+void CMP_SetOutDetectEdge(CM_CMP_TypeDef *CMPx, uint8_t u8CmpEdges);
+void CMP_SetOutFilter(CM_CMP_TypeDef *CMPx, uint8_t u8CmpFilter);
+void CMP_SetOutPolarity(CM_CMP_TypeDef *CMPx, uint16_t u16CmpPolarity);
+void CMP_SetPositiveInput(CM_CMP_TypeDef *CMPx, uint16_t u16PositiveInput);
+void CMP_SetNegativeInput(CM_CMP_TypeDef *CMPx, uint16_t u16NegativeInput);
+void CMP_SetHystVoltage(CM_CMP_TypeDef *CMPx, uint16_t u16HystVoltage);
+void CMP_ClearOutDetectFlag(CM_CMP_TypeDef *CMPx, uint8_t u8CmpEdges);
+en_flag_status_t CMP_GetOutDetectFlag(const CM_CMP_TypeDef *CMPx, uint8_t u8CmpEdges);
+
+int32_t CMP_WindowModeInit(uint8_t u8WinCMPx, const stc_cmp_window_init_t *pstcCmpWindowInit);
+int32_t CMP_WindowStructInit(stc_cmp_window_init_t *pstcCmpWindowInit);
+
+void CMP_BlankWindowSrcDisable(CM_CMP_TypeDef *CMPx, uint16_t u16BlankWindowSrc);
+int32_t CMP_BlankWindowConfig(CM_CMP_TypeDef *CMPx, const stc_cmp_blankwindow_t *pstcBlankWindowConfig);
+int32_t CMP_BlankWindowStructInit(stc_cmp_blankwindow_t *pstcBlankWindowConfig);
+void CMP_BlankWindowCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState);
+void CMP_BlankWindowMode(CM_CMP_TypeDef *CMPx, uint8_t u8Mode);
+
+/**
+ * @}
+ */
+
+#endif /* LL_CMP_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_CMP_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_crc.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_crc.h
new file mode 100644
index 0000000000..1791809e09
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_crc.h
@@ -0,0 +1,164 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_crc.h
+ * @brief This file contains all the functions prototypes of the CRC driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Reconstruct interface function relate to calculate CRC
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_CRC_H__
+#define __HC32_LL_CRC_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_CRC
+ * @{
+ */
+
+#if (LL_CRC_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup CRC_Global_Types CRC Global Types
+ * @{
+ */
+
+/**
+ * @brief CRC initialization structure definition
+ */
+typedef struct {
+ uint32_t u32Protocol; /*!< Specifies CRC Protocol.
+ This parameter can be a value of @ref CRC_Protocol_Control_Bit */
+ uint32_t u32InitValue; /*!< Specifies initial CRC value.
+ This parameter can be CRC_INIT_VALUE_DEFAULT @ref CRC_Init_Value_Default */
+} stc_crc_init_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup CRC_Global_Macros CRC Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup CRC_Protocol_Control_Bit CRC Protocol Control Bit
+ * @{
+ */
+#define CRC_CRC16 (0x0UL)
+#define CRC_CRC32 (CRC_CR_CR)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CRC_DATA_Bit_Width CRC Data Bit Width
+ * @{
+ */
+#define CRC_DATA_WIDTH_8BIT (1U)
+#define CRC_DATA_WIDTH_16BIT (2U)
+#define CRC_DATA_WIDTH_32BIT (4U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CRC_Init_Value_Default CRC Default Computation Initialization Value
+ * @{
+ */
+#define CRC_INIT_VALUE_DEFAULT (0xFFFFFFFFUL)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup CRC_Global_Functions
+ * @{
+ */
+int32_t CRC_StructInit(stc_crc_init_t *pstcCrcInit);
+int32_t CRC_Init(const stc_crc_init_t *pstcCrcInit);
+int32_t CRC_DeInit(void);
+
+en_flag_status_t CRC_GetResultStatus(void);
+
+uint16_t CRC_CRC16_AccumulateData(uint8_t u8DataWidth, const void *pvData, uint32_t u32Len);
+uint16_t CRC_CRC16_Calculate(uint16_t u16InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len);
+en_flag_status_t CRC_CRC16_CheckData(uint16_t u16InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len, uint16_t u16ExpectValue);
+en_flag_status_t CRC_CRC16_GetCheckResult(uint16_t u16ExpectValue);
+
+uint32_t CRC_CRC32_AccumulateData(uint8_t u8DataWidth, const void *pvData, uint32_t u32Len);
+uint32_t CRC_CRC32_Calculate(uint32_t u32InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len);
+en_flag_status_t CRC_CRC32_CheckData(uint32_t u32InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len, uint32_t u32ExpectValue);
+en_flag_status_t CRC_CRC32_GetCheckResult(uint32_t u32ExpectValue);
+
+/**
+ * @}
+ */
+
+#endif /* LL_CRC_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_CRC_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_ctc.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_ctc.h
new file mode 100644
index 0000000000..f04c42edb7
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_ctc.h
@@ -0,0 +1,249 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_ctc.h
+ * @brief This file contains all the functions prototypes of the Clock Trimming
+ * Controller(CTC) driver library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_CTC_H__
+#define __HC32_LL_CTC_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_CTC
+ * @{
+ */
+
+#if (LL_CTC_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup CTC_Global_Types CTC Global Types
+ * @{
+ */
+
+/**
+ * @brief CTC continuous trim initialization structure definition
+ */
+typedef struct {
+ uint32_t u32HrcClockDiv; /*!< HRC clock division
+ This parameter can be a value of @ref CTC_HRC_Clock_Division */
+ uint32_t u32RefClockFreq; /*!< Reference clock frequency
+ This parameter should refer user manual recommended values */
+ uint32_t u32RefClockSrc; /*!< Reference clock source selection
+ This parameter can be a value of @ref CTC_Continuous_Trim_Reference_Clock_Source */
+ uint32_t u32RefClockDiv; /*!< Reference clock division
+ This parameter can be a value of @ref CTC_Reference_Clock_Division */
+ float32_t f32TolerantErrRate; /*!< CTC tolerance deviation
+ This parameter can be a value between Min_Data=0.0 and Max_Data=1.0(100%) */
+ uint8_t u8TrimValue; /*!< CTC TRMVAL value
+ This parameter can be a value between Min_Data=0 and Max_Data=0x3F */
+} stc_ctc_ct_init_t;
+
+/**
+ * @brief CTC single trim initialization structure definition
+ */
+typedef struct {
+ uint32_t u32HrcClockDiv; /*!< HRC clock division
+ This parameter can be a value of @ref CTC_HRC_Clock_Division */
+ uint32_t u32CtcRefEdge; /*!< CTCREF edge
+ This parameter can be a value of @ref CTC_Single_Trim_CTCREF_Edge */
+ float32_t f32CtcRefEdgeTime; /*!< CTCREF edge time(unit:S)
+ This parameter should refer user actual CTCREF edge time */
+ float32_t f32TolerantErrRate; /*!< CTC tolerance deviation
+ This parameter can be a value between Min_Data=0.0 and Max_Data=1.0(100%) */
+ uint8_t u8TrimValue; /*!< CTC TRMVAL value
+ This parameter can be a value between Min_Data=0 and Max_Data=0x3F */
+} stc_ctc_st_init_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup CTC_Global_Macros CTC Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup CTC_Continuous_Trim_Reference_Clock_Source CTC Continuous Trim Reference Clock Source
+ * @{
+ */
+#define CTC_REF_CLK_SRC_CTCREF (0UL) /*!< Clock source: CTCREF */
+#define CTC_REF_CLK_SRC_XTAL (CTC_CR1_REFCKS) /*!< Clock source: XTAL */
+#define CTC_REF_CLK_SRC_XTAL32 (CTC_CR1_REFCKS_1) /*!< Clock source: XTAL32 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CTC_Flag CTC Flag
+ * @{
+ */
+#define CTC_FLAG_TRIM_OK (CTC_STR_TRIMOK) /*!< Trimming OK flag */
+#define CTC_FLAG_TRIM_OVF (CTC_STR_TRMOVF) /*!< Trimming overflow flag */
+#define CTC_FLAG_TRIM_UDF (CTC_STR_TRMUDF) /*!< Trimming underflow flag */
+#define CTC_FLAG_BUSY (CTC_STR_CTCBSY) /*!< CTC busy flag */
+#define CTC_FLAG_ALL (CTC_FLAG_TRIM_OVF | CTC_FLAG_TRIM_UDF | \
+ CTC_FLAG_TRIM_OK | CTC_FLAG_BUSY)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CTC_Reference_Clock_Division CTC Reference Clock Division
+ * @{
+ */
+#define CTC_REF_CLK_DIV2 (0UL) /*!< REFCLK/2 */
+#define CTC_REF_CLK_DIV4 (1UL) /*!< REFCLK/4 */
+#define CTC_REF_CLK_DIV8 (2UL) /*!< REFCLK/8 */
+#define CTC_REF_CLK_DIV16 (3UL) /*!< REFCLK/16 */
+#define CTC_REF_CLK_DIV64 (4UL) /*!< REFCLK/64 */
+#define CTC_REF_CLK_DIV256 (5UL) /*!< REFCLK/256 */
+#define CTC_REF_CLK_DIV1024 (6UL) /*!< REFCLK/1024 */
+#define CTC_REF_CLK_DIV4096 (7UL) /*!< REFCLK/4096 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CTC_HRC_Clock_Division CTC HRC Clock Division
+ * @{
+ */
+#define CTC_HRC_CLK_DIV1 (0UL) /*!< HRCCLK/1 */
+#define CTC_HRC_CLK_DIV2 (1UL) /*!< HRCCLK/2 */
+#define CTC_HRC_CLK_DIV4 (2UL) /*!< HRCCLK/4 */
+#define CTC_HRC_CLK_DIV8 (3UL) /*!< HRCCLK/8 */
+#define CTC_HRC_CLK_DIV32 (4UL) /*!< HRCCLK/32 */
+#define CTC_HRC_CLK_DIV128 (5UL) /*!< HRCCLK/128 */
+#define CTC_HRC_CLK_DIV512 (6UL) /*!< HRCCLK/512 */
+#define CTC_HRC_CLK_DIV2048 (7UL) /*!< HRCCLK/2048 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CTC_Single_Trim_CTCREF_Edge CTC Single Trim CTCREF Edge
+ * @{
+ */
+#define CTC_CTCREF_RISING_RISING (0UL) /*!< CTC trim between CTCREF rising and CTCREF rising */
+#define CTC_CTCREF_RISING_FALLING (CTC_CR1_REFEDG_0) /*!< CTC trim between CTCREF rising and CTCREF failing */
+#define CTC_CTCREF_FALLING_RISING (CTC_CR1_REFEDG_1) /*!< CTC trim between CTCREF failing and CTCREF rising */
+#define CTC_CTCREF_FALLING_FALLING (CTC_CR1_REFEDG) /*!< CTC trim between CTCREF failing and CTCREF failing */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup CTC_Global_Functions
+ * @{
+ */
+
+/**
+ * @brief Start CTC trimming.
+ * @param None
+ * @retval None
+ */
+__STATIC_INLINE void CTC_Start(void)
+{
+ SET_REG32_BIT(CM_CTC->CR1, CTC_CR1_CTCEN);
+}
+
+/**
+ * @brief Stop CTC trimming.
+ * @param None
+ * @retval None
+ */
+__STATIC_INLINE void CTC_Stop(void)
+{
+ CLR_REG32_BIT(CM_CTC->CR1, CTC_CR1_CTCEN);
+}
+
+int32_t CTC_CT_StructInit(stc_ctc_ct_init_t *pstcCtcInit);
+int32_t CTC_CT_Init(const stc_ctc_ct_init_t *pstcCtcInit);
+
+int32_t CTC_ST_StructInit(stc_ctc_st_init_t *pstcCtcInit);
+int32_t CTC_ST_Init(const stc_ctc_st_init_t *pstcCtcInit);
+
+int32_t CTC_DeInit(void);
+void CTC_IntCmd(en_functional_state_t enNewState);
+en_flag_status_t CTC_GetStatus(uint32_t u32Flag);
+void CTC_SetTrimValue(uint8_t u8TrimValue);
+uint8_t CTC_GetTrimValue(void);
+void CTC_SetReloadValue(uint16_t u16ReloadValue);
+uint16_t CTC_GetReloadValue(void);
+void CTC_SetOffsetValue(uint8_t u8OffsetValue);
+uint8_t CTC_GetOffsetValue(void);
+
+uint16_t CTC_GetCountValue(void);
+
+/**
+ * @}
+ */
+
+#endif /* LL_CTC_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_CTC_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_dac.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_dac.h
new file mode 100644
index 0000000000..b897cabd41
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_dac.h
@@ -0,0 +1,190 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_dac.h
+ * @brief This file contains all the functions prototypes of the DAC driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Refine definition of dac resolution
+ 2023-09-30 CDT Modify API for Reference Manual Rev1.0
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_DAC_H__
+#define __HC32_LL_DAC_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_DAC
+ * @{
+ */
+
+#if (LL_DAC_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup DAC_Global_Types DAC Global Types
+ * @{
+ */
+
+/**
+ * @brief Structure definition of DAC initialization.
+ */
+typedef struct {
+ en_functional_state_t enOutput; /*!< Enable or disable analog output
+ This parameter can be a value of @ref en_functional_state_t */
+} stc_dac_init_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/**
+ * @defgroup DAC_Global_Macros DAC Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup DAC_CH DAC channel
+ * @{
+ */
+#define DAC_CH1 (0U)
+#define DAC_CH2 (1U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DAC_DATAREG_ALIGN_PATTERN DAC data register alignment pattern
+ * @{
+ */
+#define DAC_DATA_ALIGN_LEFT (DAC_DACR_DPSEL)
+#define DAC_DATA_ALIGN_RIGHT (0U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DAC_AMP_GAIN DAC amp gain
+ * @{
+ */
+#define DAC_AMP_GAIN_1 (0U)
+#define DAC_AMP_GAIN_2 (DAC_DACR_DAOGS1)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DAC_RESOLUTION DAC resolution
+ * @{
+ */
+#define DAC_RESOLUTION_12BIT (12U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DAC_ADP_SELECT DAC ADCx priority select
+ * @{
+ */
+#define DAC_ADP_SEL_ADC1 (DAC_DAADPCR_ADCSL1)
+#define DAC_ADP_SEL_ADC2 (DAC_DAADPCR_ADCSL2)
+#define DAC_ADP_SEL_ADC3 (DAC_DAADPCR_ADCSL3)
+#define DAC_ADP_SEL_ALL (DAC_DAADPCR_ADCSL1 | DAC_DAADPCR_ADCSL2 | DAC_DAADPCR_ADCSL3)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup DAC_Global_Functions
+ * @{
+ */
+
+int32_t DAC_StructInit(stc_dac_init_t *pstcDacInit);
+int32_t DAC_Init(CM_DAC_TypeDef *DACx, uint16_t u16Ch, const stc_dac_init_t *pstcDacInit);
+int32_t DAC_DeInit(CM_DAC_TypeDef *DACx);
+
+void DAC_DataRegAlignConfig(CM_DAC_TypeDef *DACx, uint16_t u16Align);
+void DAC_OutputCmd(CM_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState);
+void DAC_AMPCmd(CM_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState);
+void DAC_SetAmpGain(CM_DAC_TypeDef *DACx, uint16_t u16Ch, uint16_t u16Gain);
+void DAC_ADCPrioCmd(CM_DAC_TypeDef *DACx, en_functional_state_t enNewState);
+void DAC_ADCPrioConfig(CM_DAC_TypeDef *DACx, uint16_t u16ADCxPrio, en_functional_state_t enNewState);
+
+int32_t DAC_Start(CM_DAC_TypeDef *DACx, uint16_t u16Ch);
+int32_t DAC_Stop(CM_DAC_TypeDef *DACx, uint16_t u16Ch);
+void DAC_StartDualCh(CM_DAC_TypeDef *DACx);
+void DAC_StopDualCh(CM_DAC_TypeDef *DACx);
+
+void DAC_SetChData(CM_DAC_TypeDef *DACx, uint16_t u16Ch, uint16_t u16Data);
+void DAC_SetDualChData(CM_DAC_TypeDef *DACx, uint16_t u16Data1, uint16_t u16Data2);
+int32_t DAC_GetChConvertState(const CM_DAC_TypeDef *DACx, uint16_t u16Ch);
+
+/**
+ * @}
+ */
+
+#endif /* LL_DAC_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_DAC_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_dbgc.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_dbgc.h
new file mode 100644
index 0000000000..1a39b5e2f3
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_dbgc.h
@@ -0,0 +1,159 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_dbgc.h
+ * @brief This file contains all the functions prototypes of the DBGC driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2023-06-30 CDT First version
+ 2023-09-30 CDT Add macro definition DBGC_Trace_Mode
+ Add declaration of API DBGC_TraceIoCmd,DBGC_TraceModeConfig
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_DBGC_H__
+#define __HC32_LL_DBGC_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_DBGC
+ * @{
+ */
+
+#if (LL_DBGC_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup DBGC_Global_Macros DBGC Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup DBGC_Periph_Sel DBGC Periph Selection
+ * @{
+ */
+#define DBGC_PERIPH_SWDT (DBGC_MCUSTPCTL_SWDTSTP)
+#define DBGC_PERIPH_WDT (DBGC_MCUSTPCTL_WDTSTP )
+#define DBGC_PERIPH_RTC (DBGC_MCUSTPCTL_RTCSTP )
+#define DBGC_PERIPH_TMR0_1 (DBGC_MCUSTPCTL_M06STP)
+#define DBGC_PERIPH_TMR0_2 (DBGC_MCUSTPCTL_M07STP)
+#define DBGC_PERIPH_TMR2_1 (DBGC_MCUSTPCTL_M08STP)
+#define DBGC_PERIPH_TMR2_2 (DBGC_MCUSTPCTL_M09STP)
+#define DBGC_PERIPH_TMR2_3 (DBGC_MCUSTPCTL_M10STP)
+#define DBGC_PERIPH_TMR2_4 (DBGC_MCUSTPCTL_M11STP)
+#define DBGC_PERIPH_TMR4 (DBGC_MCUSTPCTL_M12STP)
+#define DBGC_PERIPH_TMR6_1 (DBGC_MCUSTPCTL_M15STP)
+#define DBGC_PERIPH_TMR6_2 (DBGC_MCUSTPCTL_M16STP)
+#define DBGC_PERIPH_TMR6_3 (DBGC_MCUSTPCTL_M17STP)
+#define DBGC_PERIPH_TMR6_4 (DBGC_MCUSTPCTL_M18STP)
+#define DBGC_PERIPH_TMR6_5 (DBGC_MCUSTPCTL_M19STP)
+#define DBGC_PERIPH_TMR6_6 (DBGC_MCUSTPCTL_M20STP)
+#define DBGC_PERIPH_TMR6_7 (DBGC_MCUSTPCTL_M21STP)
+#define DBGC_PERIPH_TMR6_8 (DBGC_MCUSTPCTL_M22STP)
+#define DBGC_PERIPH_TMR6_9 (DBGC_MCUSTPCTL_M23STP)
+#define DBGC_PERIPH_TMR6_10 (DBGC_MCUSTPCTL_M24STP)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DBGC_Periph2_Sel DBGC Periph2 Selection
+ * @{
+ */
+#define DBGC_PERIPH_TMRA_1 (DBGC_MCUSTPCTL2_M32STP)
+#define DBGC_PERIPH_TMRA_2 (DBGC_MCUSTPCTL2_M33STP)
+#define DBGC_PERIPH_TMRA_3 (DBGC_MCUSTPCTL2_M34STP)
+#define DBGC_PERIPH_TMRA_4 (DBGC_MCUSTPCTL2_M35STP)
+#define DBGC_PERIPH_TMRA_5 (DBGC_MCUSTPCTL2_M36STP)
+#define DBGC_PERIPH_TMRA_6 (DBGC_MCUSTPCTL2_M37STP)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DBGC_Trace_Mode DBGC trace mode
+ * @{
+ */
+#define DBGC_TRACE_ASYNC (0UL)
+#define DBGC_TRACE_SYNC_1BIT (DBGC_MCUTRACECTL_TRACEMODE_0)
+#define DBGC_TRACE_SYNC_2BIT (DBGC_MCUTRACECTL_TRACEMODE_1)
+#define DBGC_TRACE_SYNC_4BIT (DBGC_MCUTRACECTL_TRACEMODE)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup DBGC_Global_Functions
+ * @{
+ */
+void DBGC_PeriphCmd(uint32_t u32Periph, en_functional_state_t enNewState);
+void DBGC_Periph2Cmd(uint32_t u32Periph, en_functional_state_t enNewState);
+void DBGC_TraceIoCmd(en_functional_state_t enNewState);
+void DBGC_TraceModeConfig(uint32_t u32TraceMode);
+/**
+ * @}
+ */
+
+#endif /* LL_DBGC_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_DBGC_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_dcu.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_dcu.h
new file mode 100644
index 0000000000..a65e38c923
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_dcu.h
@@ -0,0 +1,269 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_dcu.h
+ * @brief This file contains all the functions prototypes of the DCU(Data
+ * Computing Unit) driver library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Modify typo
+ Delete macro definition: DCU_INT_SAWTOOTH_WAVE_RELOAD
+ Delete wave mode
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_DCU_H__
+#define __HC32_LL_DCU_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_DCU
+ * @{
+ */
+
+#if (LL_DCU_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup DCU_Global_Types DCU Global Types
+ * @{
+ */
+
+/**
+ * @brief DCU initialization structure definition
+ */
+typedef struct {
+ uint32_t u32Mode; /*!< Specifies DCU operation.
+ This parameter can be a value of @ref DCU_Mode */
+ uint32_t u32DataWidth; /*!< Specifies DCU data width.
+ This parameter can be a value of @ref DCU_Data_Width */
+} stc_dcu_init_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup DCU_Global_Macros DCU Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup DCU_Data_Width DCU Data Width
+ * @{
+ */
+#define DCU_DATA_WIDTH_8BIT (0UL) /*!< DCU data width: 8 bit */
+#define DCU_DATA_WIDTH_16BIT (DCU_CTL_DATASIZE_0) /*!< DCU data width: 16 bit */
+#define DCU_DATA_WIDTH_32BIT (DCU_CTL_DATASIZE_1) /*!< DCU data width: 32 bit */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DCU_Compare_Trigger_Condition DCU Compare Trigger Condition
+ * @{
+ */
+#define DCU_CMP_TRIG_DATA0 (0UL) /*!< DCU compare triggered by DATA0 */
+#define DCU_CMP_TRIG_DATA0_DATA1_DATA2 (DCU_CTL_COMPTRG) /*!< DCU compare triggered by DATA0 or DATA1 or DATA2 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DCU_Mode DCU Mode
+ * @{
+ */
+#define DCU_MD_INVD (0UL) /*!< DCU invalid */
+#define DCU_MD_ADD (1UL) /*!< DCU add operation */
+#define DCU_MD_SUB (2UL) /*!< DCU sub operation */
+#define DCU_MD_HW_ADD (3UL) /*!< DCU hardware trigger add */
+#define DCU_MD_HW_SUB (4UL) /*!< DCU hardware trigger sub */
+#define DCU_MD_CMP (5UL) /*!< DCU compare */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DCU_Flag DCU Flag
+ * @{
+ */
+#define DCU_FLAG_CARRY (DCU_FLAG_FLAG_OP) /*!< DCU addition overflow or subtraction underflow flag */
+#define DCU_FLAG_DATA0_LT_DATA2 (DCU_FLAG_FLAG_LS2) /*!< DCU DATA0 < DATA2 flag */
+#define DCU_FLAG_DATA0_EQ_DATA2 (DCU_FLAG_FLAG_EQ2) /*!< DCU DATA0 = DATA2 flag */
+#define DCU_FLAG_DATA0_GT_DATA2 (DCU_FLAG_FLAG_GT2) /*!< DCU DATA0 > DATA2 flag */
+#define DCU_FLAG_DATA0_LT_DATA1 (DCU_FLAG_FLAG_LS1) /*!< DCU DATA0 < DATA1 flag */
+#define DCU_FLAG_DATA0_EQ_DATA1 (DCU_FLAG_FLAG_EQ1) /*!< DCU DATA0 = DATA1 flag */
+#define DCU_FLAG_DATA0_GT_DATA1 (DCU_FLAG_FLAG_GT1) /*!< DCU DATA0 > DATA1 flag */
+
+#define DCU_FLAG_ALL (0x0000007FUL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DCU_Category DCU Category
+ * @{
+ */
+#define DCU_CATEGORY_OP (0UL) /*!< DCU operation result(overflow/underflow) */
+#define DCU_CATEGORY_CMP_WIN (1UL) /*!< DCU comparison(window) */
+#define DCU_CATEGORY_CMP_NON_WIN (2UL) /*!< DCU comparison(non-window) */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DCU_Interrupt_Type DCU Interrupt Type
+ * @{
+ */
+/**
+ * @defgroup DCU_Compare_Interrupt DCU Compare(Non-window) Interrupt
+ * @note Interrupt type DCU_Compare_Interrupt is valid when only select DCU_CATEGORY_CMP_NON_WIN
+ * @{
+ */
+#define DCU_INT_CMP_DATA0_LT_DATA2 (DCU_INTEVTSEL_SEL_LS2) /*!< DCU DATA0 < DATA2 interrupt */
+#define DCU_INT_CMP_DATA0_EQ_DATA2 (DCU_INTEVTSEL_SEL_EQ2) /*!< DCU DATA0 = DATA2 interrupt */
+#define DCU_INT_CMP_DATA0_GT_DATA2 (DCU_INTEVTSEL_SEL_GT2) /*!< DCU DATA0 > DATA2 interrupt */
+#define DCU_INT_CMP_DATA0_LT_DATA1 (DCU_INTEVTSEL_SEL_LS1) /*!< DCU DATA0 < DATA1 interrupt */
+#define DCU_INT_CMP_DATA0_EQ_DATA1 (DCU_INTEVTSEL_SEL_EQ1) /*!< DCU DATA0 = DATA1 interrupt */
+#define DCU_INT_CMP_DATA0_GT_DATA1 (DCU_INTEVTSEL_SEL_GT1) /*!< DCU DATA0 > DATA1 interrupt */
+#define DCU_INT_CMP_NON_WIN_ALL (DCU_INT_CMP_DATA0_LT_DATA2 | \
+ DCU_INT_CMP_DATA0_EQ_DATA2 | \
+ DCU_INT_CMP_DATA0_GT_DATA2 | \
+ DCU_INT_CMP_DATA0_LT_DATA1 | \
+ DCU_INT_CMP_DATA0_EQ_DATA1 | \
+ DCU_INT_CMP_DATA0_GT_DATA1)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DCU_Window_Compare_Interrupt DCU Window Compare Interrupt
+ * @note Interrupt type DCU_Window_Compare_Interrupt is valid when only select DCU_CATEGORY_CMP_WIN
+ * @{
+ */
+#define DCU_INT_CMP_WIN_INSIDE (DCU_INTEVTSEL_SEL_WIN_0) /*!< DCU comparison(DATA2 <= DATA0 <= DATA1) interrupt */
+#define DCU_INT_CMP_WIN_OUTSIDE (DCU_INTEVTSEL_SEL_WIN_1) /*!< DCU comparison(DATA0 < DATA2 & DATA0 > DATA1 ) interrupt */
+#define DCU_INT_CMP_WIN_ALL (DCU_INT_CMP_WIN_INSIDE | DCU_INT_CMP_WIN_OUTSIDE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DCU_Operation_Interrupt DCU Operation Interrupt
+ * @note DCU_Window_Compare_Interrupt selection is valid when only select DCU_CATEGORY_OP
+ * @{
+ */
+#define DCU_INT_OP_CARRY (DCU_INTEVTSEL_SEL_OP) /*!< DCU addition overflow or subtraction underflow interrupt */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DCU_Data_Register_Index DCU Data Register Index
+ * @{
+ */
+#define DCU_DATA0_IDX (0UL) /*!< DCU DATA0 */
+#define DCU_DATA1_IDX (1UL) /*!< DCU DATA1 */
+#define DCU_DATA2_IDX (2UL) /*!< DCU DATA2 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup DCU_Global_Functions
+ * @{
+ */
+
+/* Initialization and configuration functions */
+int32_t DCU_Init(CM_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcDcuInit);
+int32_t DCU_StructInit(stc_dcu_init_t *pstcDcuInit);
+int32_t DCU_DeInit(CM_DCU_TypeDef *DCUx);
+
+void DCU_SetMode(CM_DCU_TypeDef *DCUx, uint32_t u32Mode);
+void DCU_SetDataWidth(CM_DCU_TypeDef *DCUx, uint32_t u32DataWidth);
+void DCU_SetCompareCond(CM_DCU_TypeDef *DCUx, uint32_t u32Cond);
+
+/* Interrupt and flag management functions */
+en_flag_status_t DCU_GetStatus(const CM_DCU_TypeDef *DCUx, uint32_t u32Flag);
+void DCU_ClearStatus(CM_DCU_TypeDef *DCUx, uint32_t u32Flag);
+void DCU_GlobalIntCmd(CM_DCU_TypeDef *DCUx, en_functional_state_t enNewState);
+void DCU_IntCmd(CM_DCU_TypeDef *DCUx, uint32_t u32IntCategory, uint32_t u32IntType, en_functional_state_t enNewState);
+
+/* Read and write functions */
+uint8_t DCU_ReadData8(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex);
+void DCU_WriteData8(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint8_t u8Data);
+uint16_t DCU_ReadData16(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex);
+void DCU_WriteData16(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint16_t u16Data);
+uint32_t DCU_ReadData32(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex);
+void DCU_WriteData32(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint32_t u32Data);
+
+/**
+ * @}
+ */
+
+#endif /* LL_DCU_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_DCU_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_def.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_def.h
new file mode 100644
index 0000000000..56b11e53e0
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_def.h
@@ -0,0 +1,394 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_def.h
+ * @brief This file contains LL common definitions: enumeration, macros and
+ * structures definitions.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-01-15 CDT Implemented the definition of __NO_INIT for AC6 and ARM Compiler
+ ARM Compiler suppress warning message: diag_1296
+ 2023-06-30 CDT Modify typo
+ Add __NO_OPTIMIZE configuration item
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_DEF_H__
+#define __HC32_LL_DEF_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include
+#include
+
+/**
+ * @addtogroup LL_Common
+ * @{
+ */
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup LL_Common_Global_Types LL Common Global Types
+ * @{
+ */
+
+/**
+ * @brief Single precision floating point number (4 byte)
+ */
+typedef float float32_t;
+
+/**
+ * @brief Double precision floating point number (8 byte)
+ */
+typedef double float64_t;
+
+/**
+ * @brief Function pointer type to void/void function
+ */
+typedef void (*func_ptr_t)(void);
+
+/**
+ * @brief Functional state
+ */
+typedef enum {
+ DISABLE = 0U,
+ ENABLE = 1U,
+} en_functional_state_t;
+
+/**
+ * @brief Flag status
+ */
+typedef enum {
+ RESET = 0U,
+ SET = 1U,
+} en_flag_status_t, en_int_status_t;
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup LL_Common_Global_Macros LL Common Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup Compiler_Macros Compiler Macros
+ * @{
+ */
+#ifndef __UNUSED
+#define __UNUSED __attribute__((unused))
+#endif /* __UNUSED */
+
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#ifndef __WEAKDEF
+#define __WEAKDEF __attribute__((weak))
+#endif /* __WEAKDEF */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN __attribute__((aligned(4)))
+#endif /* __ALIGN_BEGIN */
+#ifndef __NOINLINE
+#define __NOINLINE __attribute__((noinline))
+#endif /* __NOINLINE */
+/* RAM functions are defined using the toolchain options.
+Functions that are executed in RAM should reside in a separate source module.
+Using the 'Options for File' dialog you can simply change the 'Code / Const'
+area of a module to a memory space in physical RAM. */
+#ifndef __RAM_FUNC
+#define __RAM_FUNC __attribute__((section("RAMCODE")))
+#endif /* __RAM_FUNC */
+#ifndef __NO_INIT
+#define __NO_INIT __attribute__((section(".bss.noinit")))
+#endif /* __NO_INIT */
+#ifndef __NO_OPTIMIZE
+#define __NO_OPTIMIZE __attribute__((optnone))
+#endif /* __NO_OPTIMIZE */
+#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /*!< GNU Compiler */
+#ifndef __WEAKDEF
+#define __WEAKDEF __attribute__((weak))
+#endif /* __WEAKDEF */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN __attribute__((aligned (4)))
+#endif /* __ALIGN_BEGIN */
+#ifndef __NOINLINE
+#define __NOINLINE __attribute__((noinline))
+#endif /* __NOINLINE */
+#ifndef __RAM_FUNC
+#define __RAM_FUNC __attribute__((long_call, section(".ramfunc")))
+/* Usage: __RAM_FUNC void foo(void) */
+#endif /* __RAM_FUNC */
+#ifndef __NO_INIT
+#define __NO_INIT __attribute__((section(".noinit")))
+#endif /* __NO_INIT */
+#ifndef __NO_OPTIMIZE
+#define __NO_OPTIMIZE __attribute__((optimize("O0")))
+#endif /* __NO_OPTIMIZE */
+#elif defined (__ICCARM__) /*!< IAR Compiler */
+#ifndef __WEAKDEF
+#define __WEAKDEF __weak
+#endif /* __WEAKDEF */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN _Pragma("data_alignment=4")
+#endif /* __ALIGN_BEGIN */
+#ifndef __NOINLINE
+#define __NOINLINE _Pragma("optimize = no_inline")
+#endif /* __NOINLINE */
+#ifndef __RAM_FUNC
+#define __RAM_FUNC __ramfunc
+#endif /* __RAM_FUNC */
+#ifndef __NO_INIT
+#define __NO_INIT __no_init
+#endif /* __NO_INIT */
+#ifndef __NO_OPTIMIZE
+#define __NO_OPTIMIZE _Pragma("optimize=none")
+#endif /* __NO_OPTIMIZE */
+#elif defined (__CC_ARM) /*!< ARM Compiler */
+#ifndef __WEAKDEF
+#define __WEAKDEF __attribute__((weak))
+#endif /* __WEAKDEF */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN __align(4)
+#endif /* __ALIGN_BEGIN */
+#ifndef __NOINLINE
+#define __NOINLINE __attribute__((noinline))
+#endif /* __NOINLINE */
+#ifndef __NO_INIT
+#define __NO_INIT __attribute__((section(".bss.noinit"), zero_init))
+#endif /* __NO_INIT */
+#ifndef __NO_OPTIMIZE
+#define __NO_OPTIMIZE
+#endif /* __NO_OPTIMIZE */
+/* RAM functions are defined using the toolchain options.
+Functions that are executed in RAM should reside in a separate source module.
+Using the 'Options for File' dialog you can simply change the 'Code / Const'
+area of a module to a memory space in physical RAM. */
+#ifndef __RAM_FUNC
+#define __RAM_FUNC __attribute__((section("RAMCODE")))
+#endif /* __RAM_FUNC */
+/* Suppress warning message: extended constant initializer used */
+#pragma diag_suppress 1296
+#else
+#error "unsupported compiler!!"
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @defgroup Extend_Macros Extend Macros
+ * @{
+ */
+/* Decimal to BCD */
+#define DEC2BCD(x) ((((x) / 10U) << 4U) + ((x) % 10U))
+
+/* BCD to decimal */
+#define BCD2DEC(x) ((((x) >> 4U) * 10U) + ((x) & 0x0FU))
+
+/* Returns the dimension of an array */
+#define ARRAY_SZ(x) ((sizeof(x)) / (sizeof((x)[0])))
+
+/* Returns the minimum value out of two values */
+#define LL_MIN(x, y) ((x) < (y) ? (x) : (y))
+
+/* Returns the maximum value out of two values */
+#define LL_MAX(x, y) ((x) > (y) ? (x) : (y))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup Check_Parameters_Validity Check Parameters Validity
+ * @{
+ */
+
+/* Check Functional State */
+#define IS_FUNCTIONAL_STATE(state) (((state) == DISABLE) || ((state) == ENABLE))
+
+/**
+ * @defgroup Check_Address_Align_Validity Check Address Align Validity
+ * @{
+ */
+#define IS_ADDR_ALIGN(addr, align) (0UL == (((uint32_t)(addr)) & (((uint32_t)(align)) - 1UL)))
+#define IS_ADDR_ALIGN_HALFWORD(addr) (0UL == (((uint32_t)(addr)) & 0x1UL))
+#define IS_ADDR_ALIGN_WORD(addr) (0UL == (((uint32_t)(addr)) & 0x3UL))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup Peripheral_Bit_Band Peripheral Bit Band
+ * @{
+ */
+#define __PERIPH_BIT_BAND_BASE (0x42000000UL)
+#define __PERIPH_BASE (0x40000000UL)
+#define __REG_OFS(regAddr) ((regAddr) - __PERIPH_BASE)
+#define __BIT_BAND_ADDR(regAddr, pos) ((__REG_OFS(regAddr) << 5U) + ((uint32_t)(pos) << 2U) + __PERIPH_BIT_BAND_BASE)
+#define PERIPH_BIT_BAND(regAddr, pos) (*(__IO uint32_t *)__BIT_BAND_ADDR((regAddr), (pos)))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup Generic_Error_Codes Generic Error Codes
+ * @{
+ */
+#define LL_OK (0) /*!< No error */
+#define LL_ERR (-1) /*!< Non-specific error code */
+#define LL_ERR_UNINIT (-2) /*!< Module (or part of it) was not initialized properly */
+#define LL_ERR_INVD_PARAM (-3) /*!< Provided parameter is not valid */
+#define LL_ERR_INVD_MD (-4) /*!< Operation not allowed in current mode */
+#define LL_ERR_NOT_RDY (-5) /*!< A requested final state is not reached */
+#define LL_ERR_BUSY (-6) /*!< A conflicting or requested operation is still in progress */
+#define LL_ERR_ADDR_ALIGN (-7) /*!< Address alignment does not match */
+#define LL_ERR_TIMEOUT (-8) /*!< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) */
+#define LL_ERR_BUF_EMPTY (-9) /*!< Circular buffer can not be read because the buffer is empty */
+#define LL_ERR_BUF_FULL (-10) /*!< Circular buffer can not be written because the buffer is full */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup Chip_Module_Switch Chip Module Switch
+ * @{
+ */
+#define DDL_ON (1U)
+#define DDL_OFF (0U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup Bit_Mask_Macros Bit Mask Macros
+ * @{
+ */
+#define BIT_MASK_00 (1UL << 0U)
+#define BIT_MASK_01 (1UL << 1U)
+#define BIT_MASK_02 (1UL << 2U)
+#define BIT_MASK_03 (1UL << 3U)
+#define BIT_MASK_04 (1UL << 4U)
+#define BIT_MASK_05 (1UL << 5U)
+#define BIT_MASK_06 (1UL << 6U)
+#define BIT_MASK_07 (1UL << 7U)
+#define BIT_MASK_08 (1UL << 8U)
+#define BIT_MASK_09 (1UL << 9U)
+#define BIT_MASK_10 (1UL << 10U)
+#define BIT_MASK_11 (1UL << 11U)
+#define BIT_MASK_12 (1UL << 12U)
+#define BIT_MASK_13 (1UL << 13U)
+#define BIT_MASK_14 (1UL << 14U)
+#define BIT_MASK_15 (1UL << 15U)
+#define BIT_MASK_16 (1UL << 16U)
+#define BIT_MASK_17 (1UL << 17U)
+#define BIT_MASK_18 (1UL << 18U)
+#define BIT_MASK_19 (1UL << 19U)
+#define BIT_MASK_20 (1UL << 20U)
+#define BIT_MASK_21 (1UL << 21U)
+#define BIT_MASK_22 (1UL << 22U)
+#define BIT_MASK_23 (1UL << 23U)
+#define BIT_MASK_24 (1UL << 24U)
+#define BIT_MASK_25 (1UL << 25U)
+#define BIT_MASK_26 (1UL << 26U)
+#define BIT_MASK_27 (1UL << 27U)
+#define BIT_MASK_28 (1UL << 28U)
+#define BIT_MASK_29 (1UL << 29U)
+#define BIT_MASK_30 (1UL << 30U)
+#define BIT_MASK_31 (1UL << 31U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup Register_Macros Register Macros
+ * @{
+ */
+#define RW_MEM8(addr) (*(volatile uint8_t *)(addr))
+#define RW_MEM16(addr) (*(volatile uint16_t *)(addr))
+#define RW_MEM32(addr) (*(volatile uint32_t *)(addr))
+
+#define SET_REG_BIT(REG, BIT) ((REG) |= (BIT))
+#define SET_REG8_BIT(REG, BIT) ((REG) |= ((uint8_t)(BIT)))
+#define SET_REG16_BIT(REG, BIT) ((REG) |= ((uint16_t)(BIT)))
+#define SET_REG32_BIT(REG, BIT) ((REG) |= ((uint32_t)(BIT)))
+
+#define CLR_REG_BIT(REG, BIT) ((REG) &= (~(BIT)))
+#define CLR_REG8_BIT(REG, BIT) ((REG) &= ((uint8_t)(~((uint8_t)(BIT)))))
+#define CLR_REG16_BIT(REG, BIT) ((REG) &= ((uint16_t)(~((uint16_t)(BIT)))))
+#define CLR_REG32_BIT(REG, BIT) ((REG) &= ((uint32_t)(~((uint32_t)(BIT)))))
+
+#define READ_REG_BIT(REG, BIT) ((REG) & (BIT))
+#define READ_REG8_BIT(REG, BIT) ((REG) & ((uint8_t)(BIT)))
+#define READ_REG16_BIT(REG, BIT) ((REG) & ((uint16_t)(BIT)))
+#define READ_REG32_BIT(REG, BIT) ((REG) & ((uint32_t)(BIT)))
+
+#define CLR_REG(REG) ((REG) = (0U))
+#define CLR_REG8(REG) ((REG) = ((uint8_t)(0U)))
+#define CLR_REG16(REG) ((REG) = ((uint16_t)(0U)))
+#define CLR_REG32(REG) ((REG) = ((uint32_t)(0UL)))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+#define WRITE_REG8(REG, VAL) ((REG) = ((uint8_t)(VAL)))
+#define WRITE_REG16(REG, VAL) ((REG) = ((uint16_t)(VAL)))
+#define WRITE_REG32(REG, VAL) ((REG) = ((uint32_t)(VAL)))
+
+#define READ_REG(REG) (REG)
+#define READ_REG8(REG) (REG)
+#define READ_REG16(REG) (REG)
+#define READ_REG32(REG) (REG)
+
+#define MODIFY_REG(REGS, CLRMASK, SETMASK) (WRITE_REG((REGS), (((READ_REG(REGS)) & (~(CLRMASK))) | ((SETMASK) & (CLRMASK)))))
+#define MODIFY_REG8(REGS, CLRMASK, SETMASK) (WRITE_REG8((REGS), (((READ_REG8((REGS))) & ((uint8_t)(~((uint8_t)(CLRMASK))))) | ((uint8_t)(SETMASK) & (uint8_t)(CLRMASK)))))
+#define MODIFY_REG16(REGS, CLRMASK, SETMASK) (WRITE_REG16((REGS), (((READ_REG16((REGS))) & ((uint16_t)(~((uint16_t)(CLRMASK))))) | ((uint16_t)(SETMASK) & (uint16_t)(CLRMASK)))))
+#define MODIFY_REG32(REGS, CLRMASK, SETMASK) (WRITE_REG32((REGS), (((READ_REG32((REGS))) & ((uint32_t)(~((uint32_t)(CLRMASK))))) | ((uint32_t)(SETMASK) & (uint32_t)(CLRMASK)))))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_DEF_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_dma.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_dma.h
new file mode 100644
index 0000000000..dd659d80ca
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_dma.h
@@ -0,0 +1,608 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_dma.h
+ * @brief This file contains all the functions prototypes of the DMA driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-12-15 CDT Modify API input param type:u16->u32
+ Add structure stc_dma_rc_nonseq_init_t
+ Add API DMA_ReconfigNonSeqStructInit() & DMA_ReconfigNonSeqInit()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_DMA_H__
+#define __HC32_LL_DMA_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_DMA
+ * @{
+ */
+
+#if (LL_DMA_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup DMA_Global_Types DMA Global Types
+ * @{
+ */
+
+/**
+ * @brief DMA basic configuration
+ */
+typedef struct {
+ uint32_t u32IntEn; /*!< Specifies the DMA interrupt function.
+ This parameter can be a value of @ref DMA_Int_Config */
+ uint32_t u32SrcAddr; /*!< Specifies the DMA source address. */
+ uint32_t u32DestAddr; /*!< Specifies the DMA destination address. */
+ uint32_t u32DataWidth; /*!< Specifies the DMA transfer data width.
+ This parameter can be a value of @ref DMA_DataWidth_Sel */
+ uint32_t u32BlockSize; /*!< Specifies the DMA block size. */
+ uint32_t u32TransCount; /*!< Specifies the DMA transfer count. */
+ uint32_t u32SrcAddrInc; /*!< Specifies the source address increment mode.
+ This parameter can be a value of @ref DMA_SrcAddr_Incremented_Mode */
+ uint32_t u32DestAddrInc; /*!< Specifies the destination address increment mode.
+ This parameter can be a value of @ref DMA_DesAddr_Incremented_Mode */
+} stc_dma_init_t;
+
+/**
+ * @brief DMA repeat mode configuration
+ */
+typedef struct {
+ uint32_t u32Mode; /*!< Specifies the DMA source repeat function.
+ This parameter can be a value of @ref DMA_Repeat_Config */
+ uint32_t u32SrcCount; /*!< Specifies the DMA source repeat size. */
+ uint32_t u32DestCount; /*!< Specifies the DMA destination repeat size. */
+} stc_dma_repeat_init_t;
+
+/**
+ * @brief DMA non-sequence mode configuration
+ */
+typedef struct {
+ uint32_t u32Mode; /*!< Specifies the DMA source non-sequence function.
+ This parameter can be a value of @ref DMA_NonSeq_Config */
+ uint32_t u32SrcCount; /*!< Specifies the DMA source non-sequence function count. */
+ uint32_t u32SrcOffset; /*!< Specifies the DMA source non-sequence function offset. */
+ uint32_t u32DestCount; /*!< Specifies the DMA destination non-sequence function count. */
+ uint32_t u32DestOffset; /*!< Specifies the DMA destination non-sequence function offset. */
+} stc_dma_nonseq_init_t;
+
+/**
+ * @brief DMA Link List Pointer (LLP) mode configuration
+ */
+typedef struct {
+ uint32_t u32State; /*!< Specifies the DMA LLP function.
+ This parameter can be a value of @ref DMA_Llp_En */
+ uint32_t u32Mode; /*!< Specifies the DMA LLP auto or wait REQ.
+ This parameter can be a value of @ref DMA_Llp_Mode */
+ uint32_t u32Addr; /*!< Specifies the DMA list pointer address for LLP function. */
+} stc_dma_llp_init_t;
+
+/**
+ * @brief DMA re-config function configuration
+ */
+typedef struct {
+ uint32_t u32CountMode; /*!< Specifies the DMA reconfig function count mode.
+ This parameter can be a value of @ref DMA_Reconfig_Count_Sel */
+ uint32_t u32DestAddrMode; /*!< Specifies the DMA reconfig function destination address mode.
+ This parameter can be a value of @ref DMA_Reconfig_DestAddr_Sel */
+ uint32_t u32SrcAddrMode; /*!< Specifies the DMA reconfig function source address mode.
+ This parameter can be a value of @ref DMA_Reconfig_SrcAddr_Sel */
+} stc_dma_reconfig_init_t;
+
+/**
+ * @brief DMA re-config non-sequence mode configuration
+ */
+typedef struct {
+ uint32_t u32Mode; /*!< Specifies the DMA source non-sequence function.
+ This parameter can be a value of @ref DMA_NonSeq_Config */
+ uint32_t u32SrcCount; /*!< Specifies the DMA source non-sequence function count. */
+ uint32_t u32SrcDist; /*!< Specifies the DMA source non-sequence function distance. */
+ uint32_t u32DestCount; /*!< Specifies the DMA destination non-sequence function count. */
+ uint32_t u32DestDist; /*!< Specifies the DMA destination non-sequence function distance. */
+} stc_dma_rc_nonseq_init_t;
+
+/**
+ * @brief Dma LLP(linked list pointer) descriptor structure definition
+ */
+typedef struct {
+ uint32_t SARx; /*!< LLP source address */
+ uint32_t DARx; /*!< LLP destination address */
+ uint32_t DTCTLx; /*!< LLP transfer count and block size */
+ uint32_t RPTx; /*!< LLP source & destination repeat size */
+ uint32_t SNSEQCTLx; /*!< LLP source non-seq count and offset */
+ uint32_t DNSEQCTLx; /*!< LLP destination non-seq count and offset */
+ uint32_t LLPx; /*!< LLP next list pointer */
+ uint32_t CHCTLx; /*!< LLP channel control */
+} stc_dma_llp_descriptor_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup DMA_Global_Macros DMA Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup DMA_Channel_selection DMA Channel Position selection
+ * @{
+ */
+#define DMA_CH0 (0x00U) /*!< DMA Channel 0 */
+#define DMA_CH1 (0x01U) /*!< DMA Channel 1 */
+#define DMA_CH2 (0x02U) /*!< DMA Channel 2 */
+#define DMA_CH3 (0x03U) /*!< DMA Channel 3 */
+#define DMA_CH4 (0x04U) /*!< DMA Channel 4 */
+#define DMA_CH5 (0x05U) /*!< DMA Channel 5 */
+#define DMA_CH6 (0x06U) /*!< DMA Channel 6 */
+#define DMA_CH7 (0x07U) /*!< DMA Channel 7 */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_Mx_Channel_selection DMA Multiplex Channel selection
+ * @{
+ */
+#define DMA_MX_CH0 (0x01UL) /*!< DMA Channel 0 position */
+#define DMA_MX_CH1 (0x02UL) /*!< DMA Channel 1 position */
+#define DMA_MX_CH_ALL (DMA_CHEN_CHEN) /*!< DMA Channel mask position */
+#define DMA_MX_CH2 (0x04UL) /*!< DMA Channel 2 position */
+#define DMA_MX_CH3 (0x08UL) /*!< DMA Channel 3 position */
+#define DMA_MX_CH4 (0x10UL) /*!< DMA Channel 4 position */
+#define DMA_MX_CH5 (0x20UL) /*!< DMA Channel 5 position */
+#define DMA_MX_CH6 (0x40UL) /*!< DMA Channel 6 position */
+#define DMA_MX_CH7 (0x80UL) /*!< DMA Channel 7 position */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_Flag_Request_Err_Sel DMA request error flag selection
+ * @{
+ */
+#define DMA_FLAG_REQ_ERR_CH0 (DMA_INTSTAT0_REQERR_0) /*!< DMA request error flag CH.0 */
+#define DMA_FLAG_REQ_ERR_CH1 (DMA_INTSTAT0_REQERR_1) /*!< DMA request error flag CH.1 */
+#define DMA_FLAG_REQ_ERR_CH2 (DMA_INTSTAT0_REQERR_2) /*!< DMA request error flag CH.2 */
+#define DMA_FLAG_REQ_ERR_CH3 (DMA_INTSTAT0_REQERR_3) /*!< DMA request error flag CH.3 */
+#define DMA_FLAG_REQ_ERR_CH4 (DMA_INTSTAT0_REQERR_4) /*!< DMA request error flag CH.4 */
+#define DMA_FLAG_REQ_ERR_CH5 (DMA_INTSTAT0_REQERR_5) /*!< DMA request error flag CH.5 */
+#define DMA_FLAG_REQ_ERR_CH6 (DMA_INTSTAT0_REQERR_6) /*!< DMA request error flag CH.6 */
+#define DMA_FLAG_REQ_ERR_CH7 (DMA_INTSTAT0_REQERR_7) /*!< DMA request error flag CH.7 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_Flag_Trans_Err_Sel DMA transfer error flag selection
+ * @{
+ */
+#define DMA_FLAG_TRANS_ERR_CH0 (DMA_INTSTAT0_TRNERR_0) /*!< DMA transfer error flag CH.0 */
+#define DMA_FLAG_TRANS_ERR_CH1 (DMA_INTSTAT0_TRNERR_1) /*!< DMA transfer error flag CH.1 */
+#define DMA_FLAG_TRANS_ERR_CH2 (DMA_INTSTAT0_TRNERR_2) /*!< DMA transfer error flag CH.2 */
+#define DMA_FLAG_TRANS_ERR_CH3 (DMA_INTSTAT0_TRNERR_3) /*!< DMA transfer error flag CH.3 */
+#define DMA_FLAG_TRANS_ERR_CH4 (DMA_INTSTAT0_TRNERR_4) /*!< DMA transfer error flag CH.4 */
+#define DMA_FLAG_TRANS_ERR_CH5 (DMA_INTSTAT0_TRNERR_5) /*!< DMA transfer error flag CH.5 */
+#define DMA_FLAG_TRANS_ERR_CH6 (DMA_INTSTAT0_TRNERR_6) /*!< DMA transfer error flag CH.6 */
+#define DMA_FLAG_TRANS_ERR_CH7 (DMA_INTSTAT0_TRNERR_7) /*!< DMA transfer error flag CH.7 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_Flag_Btc_Sel DMA block transfer completed flag selection
+ * @{
+ */
+#define DMA_FLAG_BTC_CH0 (DMA_INTSTAT1_BTC_0) /*!< DMA block transfer completed flag CH.0 */
+#define DMA_FLAG_BTC_CH1 (DMA_INTSTAT1_BTC_1) /*!< DMA block transfer completed flag CH.1 */
+#define DMA_FLAG_BTC_CH2 (DMA_INTSTAT1_BTC_2) /*!< DMA block transfer completed flag CH.2 */
+#define DMA_FLAG_BTC_CH3 (DMA_INTSTAT1_BTC_3) /*!< DMA block transfer completed flag CH.3 */
+#define DMA_FLAG_BTC_CH4 (DMA_INTSTAT1_BTC_4) /*!< DMA block transfer completed flag CH.4 */
+#define DMA_FLAG_BTC_CH5 (DMA_INTSTAT1_BTC_5) /*!< DMA block transfer completed flag CH.5 */
+#define DMA_FLAG_BTC_CH6 (DMA_INTSTAT1_BTC_6) /*!< DMA block transfer completed flag CH.6 */
+#define DMA_FLAG_BTC_CH7 (DMA_INTSTAT1_BTC_7) /*!< DMA block transfer completed flag CH.7 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_Flag_Tc_Sel DMA transfer completed flag selection
+ * @{
+ */
+#define DMA_FLAG_TC_CH0 (DMA_INTSTAT1_TC_0) /*!< DMA transfer completed flag CH.0 */
+#define DMA_FLAG_TC_CH1 (DMA_INTSTAT1_TC_1) /*!< DMA transfer completed flag CH.1 */
+#define DMA_FLAG_TC_CH2 (DMA_INTSTAT1_TC_2) /*!< DMA transfer completed flag CH.2 */
+#define DMA_FLAG_TC_CH3 (DMA_INTSTAT1_TC_3) /*!< DMA transfer completed flag CH.3 */
+#define DMA_FLAG_TC_CH4 (DMA_INTSTAT1_TC_4) /*!< DMA transfer completed flag CH.4 */
+#define DMA_FLAG_TC_CH5 (DMA_INTSTAT1_TC_5) /*!< DMA transfer completed flag CH.5 */
+#define DMA_FLAG_TC_CH6 (DMA_INTSTAT1_TC_6) /*!< DMA transfer completed flag CH.6 */
+#define DMA_FLAG_TC_CH7 (DMA_INTSTAT1_TC_7) /*!< DMA transfer completed flag CH.7 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_Int_Request_Err_Sel DMA request error interrupt selection
+ * @{
+ */
+#define DMA_INT_REQ_ERR_CH0 (DMA_INTMASK0_MSKREQERR_0) /*!< DMA request error interrupt CH.0 */
+#define DMA_INT_REQ_ERR_CH1 (DMA_INTMASK0_MSKREQERR_1) /*!< DMA request error interrupt CH.1 */
+#define DMA_INT_REQ_ERR_CH2 (DMA_INTMASK0_MSKREQERR_2) /*!< DMA request error interrupt CH.2 */
+#define DMA_INT_REQ_ERR_CH3 (DMA_INTMASK0_MSKREQERR_3) /*!< DMA request error interrupt CH.3 */
+#define DMA_INT_REQ_ERR_CH4 (DMA_INTMASK0_MSKREQERR_4) /*!< DMA request error interrupt CH.4 */
+#define DMA_INT_REQ_ERR_CH5 (DMA_INTMASK0_MSKREQERR_5) /*!< DMA request error interrupt CH.5 */
+#define DMA_INT_REQ_ERR_CH6 (DMA_INTMASK0_MSKREQERR_6) /*!< DMA request error interrupt CH.6 */
+#define DMA_INT_REQ_ERR_CH7 (DMA_INTMASK0_MSKREQERR_7) /*!< DMA request error interrupt CH.7 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_Int_Trans_Err_Sel DMA transfer error interrupt selection
+ * @{
+ */
+#define DMA_INT_TRANS_ERR_CH0 (DMA_INTMASK0_MSKTRNERR_0) /*!< DMA transfer error interrupt CH.0 */
+#define DMA_INT_TRANS_ERR_CH1 (DMA_INTMASK0_MSKTRNERR_1) /*!< DMA transfer error interrupt CH.1 */
+#define DMA_INT_TRANS_ERR_CH2 (DMA_INTMASK0_MSKTRNERR_2) /*!< DMA transfer error interrupt CH.2 */
+#define DMA_INT_TRANS_ERR_CH3 (DMA_INTMASK0_MSKTRNERR_3) /*!< DMA transfer error interrupt CH.3 */
+#define DMA_INT_TRANS_ERR_CH4 (DMA_INTMASK0_MSKTRNERR_4) /*!< DMA transfer error interrupt CH.4 */
+#define DMA_INT_TRANS_ERR_CH5 (DMA_INTMASK0_MSKTRNERR_5) /*!< DMA transfer error interrupt CH.5 */
+#define DMA_INT_TRANS_ERR_CH6 (DMA_INTMASK0_MSKTRNERR_6) /*!< DMA transfer error interrupt CH.6 */
+#define DMA_INT_TRANS_ERR_CH7 (DMA_INTMASK0_MSKTRNERR_7) /*!< DMA transfer error interrupt CH.7 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_Int_Btc_Sel DMA block transfer completed interrupt selection
+ * @{
+ */
+#define DMA_INT_BTC_CH0 (DMA_INTMASK1_MSKBTC_0) /*!< DMA block transfer completed interrupt CH.0 */
+#define DMA_INT_BTC_CH1 (DMA_INTMASK1_MSKBTC_1) /*!< DMA block transfer completed interrupt CH.1 */
+#define DMA_INT_BTC_CH2 (DMA_INTMASK1_MSKBTC_2) /*!< DMA block transfer completed interrupt CH.2 */
+#define DMA_INT_BTC_CH3 (DMA_INTMASK1_MSKBTC_3) /*!< DMA block transfer completed interrupt CH.3 */
+#define DMA_INT_BTC_CH4 (DMA_INTMASK1_MSKBTC_4) /*!< DMA block transfer completed interrupt CH.4 */
+#define DMA_INT_BTC_CH5 (DMA_INTMASK1_MSKBTC_5) /*!< DMA block transfer completed interrupt CH.5 */
+#define DMA_INT_BTC_CH6 (DMA_INTMASK1_MSKBTC_6) /*!< DMA block transfer completed interrupt CH.6 */
+#define DMA_INT_BTC_CH7 (DMA_INTMASK1_MSKBTC_7) /*!< DMA block transfer completed interrupt CH.7 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_Int_Tc_Sel DMA transfer completed interrupt selection
+ * @{
+ */
+#define DMA_INT_TC_CH0 (DMA_INTMASK1_MSKTC_0) /*!< DMA transfer completed interrupt CH.0 */
+#define DMA_INT_TC_CH1 (DMA_INTMASK1_MSKTC_1) /*!< DMA transfer completed interrupt CH.1 */
+#define DMA_INT_TC_CH2 (DMA_INTMASK1_MSKTC_2) /*!< DMA transfer completed interrupt CH.2 */
+#define DMA_INT_TC_CH3 (DMA_INTMASK1_MSKTC_3) /*!< DMA transfer completed interrupt CH.3 */
+#define DMA_INT_TC_CH4 (DMA_INTMASK1_MSKTC_4) /*!< DMA transfer completed interrupt CH.4 */
+#define DMA_INT_TC_CH5 (DMA_INTMASK1_MSKTC_5) /*!< DMA transfer completed interrupt CH.5 */
+#define DMA_INT_TC_CH6 (DMA_INTMASK1_MSKTC_6) /*!< DMA transfer completed interrupt CH.6 */
+#define DMA_INT_TC_CH7 (DMA_INTMASK1_MSKTC_7) /*!< DMA transfer completed interrupt CH.7 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_FlagMsk_Sel DMA flag mask selection
+ * @{
+ */
+#define DMA_FLAG_ERR_MASK (DMA_INTSTAT0_TRNERR | DMA_INTSTAT0_REQERR) /*!< DMA error flag mask */
+#define DMA_FLAG_TRANS_MASK (DMA_INTSTAT1_TC | DMA_INTSTAT1_BTC) /*!< DMA transfer flag mask */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_IntMsk_Sel DMA interrupt mask selection
+ * @{
+ */
+#define DMA_INT_ERR_MASK (DMA_INTMASK0_MSKREQERR | DMA_INTMASK0_MSKTRNERR) /*!< DMA error interrupt mask */
+#define DMA_INT_TRANS_MASK (DMA_INTMASK1_MSKTC | DMA_INTMASK1_MSKBTC) /*!< DMA transfer interrupt mask */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_Req_Status_Sel DMA request status
+ * @{
+ */
+#define DMA_STAT_REQ_RECONFIG (DMA_REQSTAT_RCFGREQ) /*!< DMA request from reconfig */
+#define DMA_STAT_REQ_CH0 (DMA_REQSTAT_CHREQ_0) /*!< DMA request from CH.0 */
+#define DMA_STAT_REQ_CH1 (DMA_REQSTAT_CHREQ_1) /*!< DMA request from CH.1 */
+#define DMA_STAT_REQ_CH2 (DMA_REQSTAT_CHREQ_2) /*!< DMA request from CH.2 */
+#define DMA_STAT_REQ_CH3 (DMA_REQSTAT_CHREQ_3) /*!< DMA request from CH.3 */
+#define DMA_STAT_REQ_CH4 (DMA_REQSTAT_CHREQ_4) /*!< DMA request from CH.4 */
+#define DMA_STAT_REQ_CH5 (DMA_REQSTAT_CHREQ_5) /*!< DMA request from CH.5 */
+#define DMA_STAT_REQ_CH6 (DMA_REQSTAT_CHREQ_6) /*!< DMA request from CH.6 */
+#define DMA_STAT_REQ_CH7 (DMA_REQSTAT_CHREQ_7) /*!< DMA request from CH.7 */
+
+#define DMA_STAT_REQ_MASK (DMA_REQSTAT_CHREQ | DMA_REQSTAT_RCFGREQ) /*!< DMA request mask */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_Trans_Status_Sel DMA transfer status
+ * @{
+ */
+#define DMA_STAT_TRANS_CH0 (DMA_CHSTAT_CHACT_0) /*!< DMA transfer status of CH.0 */
+#define DMA_STAT_TRANS_CH1 (DMA_CHSTAT_CHACT_1) /*!< DMA transfer status of CH.1 */
+#define DMA_STAT_TRANS_CH2 (DMA_CHSTAT_CHACT_2) /*!< DMA transfer status of CH.2 */
+#define DMA_STAT_TRANS_CH3 (DMA_CHSTAT_CHACT_3) /*!< DMA transfer status of CH.3 */
+#define DMA_STAT_TRANS_CH4 (DMA_CHSTAT_CHACT_4) /*!< DMA transfer status of CH.4 */
+#define DMA_STAT_TRANS_CH5 (DMA_CHSTAT_CHACT_5) /*!< DMA transfer status of CH.5 */
+#define DMA_STAT_TRANS_CH6 (DMA_CHSTAT_CHACT_6) /*!< DMA transfer status of CH.6 */
+#define DMA_STAT_TRANS_CH7 (DMA_CHSTAT_CHACT_7) /*!< DMA transfer status of CH.7 */
+#define DMA_STAT_TRANS_DMA (DMA_CHSTAT_DMAACT) /*!< DMA transfer status of the DMA */
+#define DMA_STAT_TRANS_RECONFIG (DMA_CHSTAT_RCFGACT) /*!< DMA reconfig status */
+
+#define DMA_STAT_TRANS_MASK (DMA_CHSTAT_DMAACT | DMA_CHSTAT_CHACT | DMA_CHSTAT_RCFGACT)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_DataWidth_Sel DMA transfer data width
+ * @{
+ */
+#define DMA_DATAWIDTH_8BIT (0x00000000UL) /*!< DMA transfer data width 8bit */
+#define DMA_DATAWIDTH_16BIT (DMA_CHCTL_HSIZE_0) /*!< DMA transfer data width 16bit */
+#define DMA_DATAWIDTH_32BIT (DMA_CHCTL_HSIZE_1) /*!< DMA transfer data width 32bit */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_Llp_En DMA LLP(linked list pinter) enable or disable
+ * @{
+ */
+#define DMA_LLP_DISABLE (0x00000000UL) /*!< DMA linked list pinter disable */
+#define DMA_LLP_ENABLE (DMA_CHCTL_LLPEN) /*!< DMA linked list pinter enable */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_Llp_Mode DMA linked list pinter mode while transferring complete
+ * @{
+ */
+#define DMA_LLP_WAIT (0x00000000UL) /*!< DMA Llp wait next request while transferring complete */
+#define DMA_LLP_RUN (DMA_CHCTL_LLPRUN) /*!< DMA Llp run right now while transferring complete */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_SrcAddr_Incremented_Mode DMA source address increment mode
+ * @{
+ */
+#define DMA_SRC_ADDR_FIX (0x00000000UL) /*!< DMA source address fix */
+#define DMA_SRC_ADDR_INC (DMA_CHCTL_SINC_0) /*!< DMA source address increment */
+#define DMA_SRC_ADDR_DEC (DMA_CHCTL_SINC_1) /*!< DMA source address decrement */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_DesAddr_Incremented_Mode DMA destination address increment mode
+ * @{
+ */
+#define DMA_DEST_ADDR_FIX (0x00000000UL) /*!< DMA destination address fix */
+#define DMA_DEST_ADDR_INC (DMA_CHCTL_DINC_0) /*!< DMA destination address increment */
+#define DMA_DEST_ADDR_DEC (DMA_CHCTL_DINC_1) /*!< DMA destination address decrement */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_Int_Config DMA interrupt function config
+ * @{
+ */
+#define DMA_INT_ENABLE (DMA_CHCTL_IE) /*!< DMA interrupt enable */
+#define DMA_INT_DISABLE (0x00000000UL) /*!< DMA interrupt disable */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_Repeat_Config DMA repeat mode function config
+ * @{
+ */
+#define DMA_RPT_NONE (0x00000000UL) /*!< DMA repeat disable */
+#define DMA_RPT_SRC (DMA_CHCTL_SRPTEN) /*!< DMA source repeat enable */
+#define DMA_RPT_DEST (DMA_CHCTL_DRPTEN) /*!< DMA destination repeat enable */
+#define DMA_RPT_BOTH (DMA_CHCTL_SRPTEN | DMA_CHCTL_DRPTEN) /*!< DMA source & destination repeat enable */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_NonSeq_Config DMA non-sequence mode function config
+ * @{
+ */
+#define DMA_NON_SEQ_NONE (0x00000000UL) /*!< DMA non-sequence disable */
+#define DMA_NON_SEQ_SRC (DMA_CHCTL_SNSEQEN) /*!< DMA source non-sequence enable */
+#define DMA_NON_SEQ_DEST (DMA_CHCTL_DNSEQEN) /*!< DMA destination non-sequence enable */
+#define DMA_NON_SEQ_BOTH (DMA_CHCTL_SNSEQEN | DMA_CHCTL_DNSEQEN) /*!< DMA source & destination non-sequence enable */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_Reconfig_Count_Sel DMA reconfig count mode selection
+ * @{
+ */
+#define DMA_RC_CNT_KEEP (0x00000000UL) /*!< Keep the original counting method */
+#define DMA_RC_CNT_SRC (DMA_RCFGCTL_CNTMD_0) /*!< Use source address counting method */
+#define DMA_RC_CNT_DEST (DMA_RCFGCTL_CNTMD_1) /*!< Use destination address counting method */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_Reconfig_DestAddr_Sel DMA reconfig destination address mode selection
+ * @{
+ */
+#define DMA_RC_DEST_ADDR_KEEP (0x00000000UL) /*!< Destination address Keep the original mode */
+#define DMA_RC_DEST_ADDR_NS (DMA_RCFGCTL_DARMD_0) /*!< Destination address non-sequence */
+#define DMA_RC_DEST_ADDR_RPT (DMA_RCFGCTL_DARMD_1) /*!< Destination address repeat */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DMA_Reconfig_SrcAddr_Sel DMA reconfig source address mode selection
+ * @{
+ */
+#define DMA_RC_SRC_ADDR_KEEP (0x00000000UL) /*!< Source address Keep the original mode */
+#define DMA_RC_SRC_ADDR_NS (DMA_RCFGCTL_SARMD_0) /*!< Source address non-sequence */
+#define DMA_RC_SRC_ADDR_RPT (DMA_RCFGCTL_SARMD_1) /*!< Source address repeat */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup DMA_Global_Functions
+ * @{
+ */
+void DMA_Cmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState);
+
+void DMA_ErrIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32ErrInt, en_functional_state_t enNewState);
+en_flag_status_t DMA_GetErrStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag);
+void DMA_ClearErrStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag);
+
+void DMA_TransCompleteIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32TransCompleteInt, en_functional_state_t enNewState);
+en_flag_status_t DMA_GetTransCompleteStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag);
+void DMA_ClearTransCompleteStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag);
+
+void DMA_MxChCmd(CM_DMA_TypeDef *DMAx, uint8_t u8MxCh, en_functional_state_t enNewState);
+int32_t DMA_ChCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState);
+
+en_flag_status_t DMA_GetRequestStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status);
+en_flag_status_t DMA_GetTransStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status);
+
+int32_t DMA_SetSrcAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr);
+int32_t DMA_SetDestAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr);
+int32_t DMA_SetTransCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Count);
+int32_t DMA_SetBlockSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size);
+int32_t DMA_SetDataWidth(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32DataWidth);
+
+int32_t DMA_SetSrcRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Size);
+int32_t DMA_SetDestRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Size);
+int32_t DMA_SetNonSeqSrcCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count);
+int32_t DMA_SetNonSeqDestCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count);
+int32_t DMA_SetNonSeqSrcOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset);
+int32_t DMA_SetNonSeqDestOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset);
+
+void DMA_SetLlpAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr);
+
+int32_t DMA_StructInit(stc_dma_init_t *pstcDmaInit);
+int32_t DMA_Init(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_init_t *pstcDmaInit);
+void DMA_DeInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
+int32_t DMA_UnitDeInit(CM_DMA_TypeDef *DMAx);
+
+int32_t DMA_RepeatStructInit(stc_dma_repeat_init_t *pstcDmaRepeatInit);
+int32_t DMA_RepeatInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_repeat_init_t *pstcDmaRepeatInit);
+
+int32_t DMA_NonSeqStructInit(stc_dma_nonseq_init_t *pstcDmaNonSeqInit);
+int32_t DMA_NonSeqInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_nonseq_init_t *pstcDmaNonSeqInit);
+
+int32_t DMA_LlpStructInit(stc_dma_llp_init_t *pstcDmaLlpInit);
+int32_t DMA_LlpInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_llp_init_t *pstcDmaLlpInit);
+
+void DMA_LlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState);
+
+int32_t DMA_ReconfigStructInit(stc_dma_reconfig_init_t *pstcDmaRCInit);
+int32_t DMA_ReconfigInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_reconfig_init_t *pstcDmaRCInit);
+void DMA_ReconfigCmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState);
+void DMA_ReconfigLlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState);
+int32_t DMA_ReconfigNonSeqStructInit(stc_dma_rc_nonseq_init_t *pstcDmaRcNonSeqInit);
+int32_t DMA_ReconfigNonSeqInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_rc_nonseq_init_t *pstcDmaRcNonSeqInit);
+
+uint32_t DMA_GetSrcAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
+uint32_t DMA_GetDestAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
+uint32_t DMA_GetTransCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
+uint32_t DMA_GetBlockSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
+uint32_t DMA_GetSrcRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
+uint32_t DMA_GetDestRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
+uint32_t DMA_GetNonSeqSrcCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
+uint32_t DMA_GetNonSeqDestCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
+uint32_t DMA_GetNonSeqSrcOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
+uint32_t DMA_GetNonSeqDestOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch);
+void DMA_AHB_HProtBufCacheCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState);
+
+/**
+ * @}
+ */
+
+#endif /* LL_DMA_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_DMA_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_efm.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_efm.h
new file mode 100644
index 0000000000..57a4875645
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_efm.h
@@ -0,0 +1,704 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_efm.h
+ * @brief This file contains all the functions prototypes of the EFM driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-12-15 CDT Rename EFM_DataCacheResetCmd() as EFM_CacheRamReset() and modify comment
+ Optimized macro group EFM_Remap_Size definitions
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_EFM_H__
+#define __HC32_LL_EFM_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_EFM
+ * @{
+ */
+
+#if (LL_EFM_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup EFM_Global_Types EFM Global Types
+ * @{
+ */
+/**
+ * @brief EFM unique ID definition
+ */
+typedef struct {
+ uint32_t u32UniqueID0; /*!< unique ID 0. */
+ uint32_t u32UniqueID1; /*!< unique ID 1. */
+ uint32_t u32UniqueID2; /*!< unique ID 2. */
+} stc_efm_unique_id_t;
+
+typedef struct {
+ uint32_t u32State;
+ uint32_t u32Addr;
+ uint32_t u32Size;
+} stc_efm_remap_init_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup EFM_Global_Macros EFM Global Macros
+ * @{
+ */
+/**
+ * @defgroup EFM_Address EFM Address Area
+ * @{
+ */
+#define EFM_START_ADDR (0x00000000UL) /*!< Flash start address */
+
+#define EFM_END_ADDR (0x0007FFFFUL) /*!< Flash end address */
+#define EFM_FLASH_1_START_ADDR (0x00040000UL)
+#define EFM_OTP_START_ADDR1 (0x00000000UL) /*!< OTP start address */
+#define EFM_OTP_END_ADDR1 (0x0001FFFFUL)
+#define EFM_OTP_START_ADDR (0x03000000UL)
+#define EFM_OTP_END_ADDR (0x030017FFUL) /*!< OTP end address */
+#define EFM_OTP_LOCK_ADDR_START (0x03001800UL) /*!< OTP lock address */
+#define EFM_OTP_LOCK_ADDR_END (0x03001AD7UL) /*!< OTP lock address */
+#define EFM_OTP_ENABLE_ADDR (0x03001AD8UL) /*!< OTP Enable address */
+#define EFM_SECURITY_START_ADDR (0x03004000UL) /*!< Flash security start address */
+#define EFM_SECURITY_END_ADDR (0x0300400BUL) /*!< Flash security end address */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_Chip_Sel EFM Chip Selection
+ * @{
+ */
+#define EFM_CHIP0 (EFM_FSTP_F0STP)
+#define EFM_CHIP1 (EFM_FSTP_F1STP)
+#define EFM_CHIP_ALL (EFM_FSTP_F0STP | EFM_FSTP_F1STP)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_Bus_Status EFM Bus Status
+ * @{
+ */
+#define EFM_BUS_HOLD (0x0UL) /*!< Bus busy while flash program or erase */
+#define EFM_BUS_RELEASE (0x1UL) /*!< Bus release while flash program or erase */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_Wait_Cycle EFM Wait Cycle
+ * @{
+ */
+
+#define EFM_WAIT_CYCLE0 (0U << EFM_FRMC_FLWT_POS) /*!< Don't insert read wait cycle */
+#define EFM_WAIT_CYCLE1 (1U << EFM_FRMC_FLWT_POS) /*!< Insert 1 read wait cycle */
+
+#define EFM_WAIT_CYCLE2 (2U << EFM_FRMC_FLWT_POS) /*!< Insert 2 read wait cycles */
+#define EFM_WAIT_CYCLE3 (3U << EFM_FRMC_FLWT_POS) /*!< Insert 3 read wait cycles */
+#define EFM_WAIT_CYCLE4 (4U << EFM_FRMC_FLWT_POS) /*!< Insert 4 read wait cycles */
+#define EFM_WAIT_CYCLE5 (5U << EFM_FRMC_FLWT_POS) /*!< Insert 5 read wait cycles */
+#define EFM_WAIT_CYCLE6 (6U << EFM_FRMC_FLWT_POS) /*!< Insert 6 read wait cycles */
+#define EFM_WAIT_CYCLE7 (7U << EFM_FRMC_FLWT_POS) /*!< Insert 7 read wait cycles */
+#define EFM_WAIT_CYCLE8 (8U << EFM_FRMC_FLWT_POS) /*!< Insert 8 read wait cycles */
+#define EFM_WAIT_CYCLE9 (9U << EFM_FRMC_FLWT_POS) /*!< Insert 9 read wait cycles */
+#define EFM_WAIT_CYCLE10 (10U << EFM_FRMC_FLWT_POS) /*!< Insert 10 read wait cycles */
+#define EFM_WAIT_CYCLE11 (11U << EFM_FRMC_FLWT_POS) /*!< Insert 11 read wait cycles */
+#define EFM_WAIT_CYCLE12 (12U << EFM_FRMC_FLWT_POS) /*!< Insert 12 read wait cycles */
+#define EFM_WAIT_CYCLE13 (13U << EFM_FRMC_FLWT_POS) /*!< Insert 13 read wait cycles */
+#define EFM_WAIT_CYCLE14 (14U << EFM_FRMC_FLWT_POS) /*!< Insert 14 read wait cycles */
+#define EFM_WAIT_CYCLE15 (15U << EFM_FRMC_FLWT_POS) /*!< Insert 15 read wait cycles */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_Swap_Address EFM Swap Address
+ * @{
+ */
+#define EFM_SWAP_ADDR (0x03002000UL)
+#define EFM_SWAP_DATA (0x005A5A5AUL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_WriteLock_Sel EFM Write Protect Lock Selection
+ * @{
+ */
+#define EFM_WRLOCK0 (EFM_WLOCK_WLOCK0) /*!< F0NWPRT controlled sector lock */
+#define EFM_WRLOCK1 (EFM_WLOCK_WLOCK1) /*!< F1NWPRT controlled sector lock */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_OperateMode_Sel EFM Operate Mode Selection
+ * @{
+ */
+#define EFM_MD_READONLY (0x0UL << EFM_FWMC_PEMOD_POS) /*!< Read only mode */
+#define EFM_MD_PGM_SINGLE (0x1UL << EFM_FWMC_PEMOD_POS) /*!< Program single mode */
+#define EFM_MD_PGM_READBACK (0x2UL << EFM_FWMC_PEMOD_POS) /*!< Program and read back mode */
+#define EFM_MD_PGM_SEQ (0x3UL << EFM_FWMC_PEMOD_POS) /*!< Program sequence mode */
+#define EFM_MD_ERASE_SECTOR (0x4UL << EFM_FWMC_PEMOD_POS) /*!< Sector erase mode */
+
+#define EFM_MD_ERASE_ONE_CHIP (0x5UL << EFM_FWMC_PEMOD_POS) /*!< A flash Chip erase mode */
+#define EFM_MD_ERASE_ALL_CHIP (0x6UL << EFM_FWMC_PEMOD_POS) /*!< All chip erase mode */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_Flag_Sel EFM Flag Selection
+ * @{
+ */
+#define EFM_FLAG_OTPWERR (EFM_FSR_OTPWERR0) /*!< EFM Flash0 otp Programming/erase error flag. */
+#define EFM_FLAG_PEPRTERR (EFM_FSR_PRTWERR0) /*!< EFM Flash0 write protect address error flag. */
+#define EFM_FLAG_PGSZERR (EFM_FSR_PGSZERR0) /*!< EFM Flash0 programming size error flag. */
+#define EFM_FLAG_PGMISMTCH (EFM_FSR_MISMTCH0) /*!< EFM Flash0 programming missing match error flag. */
+#define EFM_FLAG_OPTEND (EFM_FSR_OPTEND0) /*!< EFM Flash0 end of operation flag. */
+#define EFM_FLAG_COLERR (EFM_FSR_COLERR0) /*!< EFM Flash0 read collide error flag. */
+#define EFM_FLAG_RDY (EFM_FSR_RDY0) /*!< EFM Flash0 ready flag. */
+#define EFM_FLAG_PEPRTERR1 (EFM_FSR_PRTWERR1) /*!< EFM Flash1 write protect address error flag. */
+#define EFM_FLAG_PGSZERR1 (EFM_FSR_PGSZERR1) /*!< EFM Flash1 programming size error flag. */
+#define EFM_FLAG_PGMISMTCH1 (EFM_FSR_MISMTCH1) /*!< EFM Flash1 programming missing match error flag. */
+#define EFM_FLAG_OPTEND1 (EFM_FSR_OPTEND1) /*!< EFM Flash1 end of operation flag. */
+#define EFM_FLAG_COLERR1 (EFM_FSR_COLERR1) /*!< EFM Flash1 read collide error flag. */
+#define EFM_FLAG_RDY1 (EFM_FSR_RDY1) /*!< EFM Flash1 ready flag. */
+
+#define EFM_FLAG_ALL (EFM_FLAG_OTPWERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | EFM_FLAG_PGMISMTCH | \
+ EFM_FLAG_OPTEND | EFM_FLAG_COLERR | EFM_FLAG_PEPRTERR1 | EFM_FLAG_PGSZERR1 | \
+ EFM_FLAG_OPTEND1 | EFM_FLAG_COLERR1 | EFM_FLAG_RDY | EFM_FLAG_PGMISMTCH1 | \
+ EFM_FLAG_RDY1)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_Interrupt_Sel EFM Interrupt Selection
+ * @{
+ */
+#define EFM_INT_PEERR (EFM_FITE_PEERRITE) /*!< Program/erase error Interrupt source */
+#define EFM_INT_OPTEND (EFM_FITE_OPTENDITE) /*!< End of EFM operation Interrupt source */
+#define EFM_INT_COLERR (EFM_FITE_COLERRITE) /*!< Read collide error Interrupt source */
+
+#define EFM_INT_ALL (EFM_FITE_PEERRITE | EFM_FITE_OPTENDITE | EFM_FITE_COLERRITE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_Keys EFM Keys
+ * @{
+ */
+#define EFM_REG_UNLOCK_KEY1 (0x0123UL)
+#define EFM_REG_UNLOCK_KEY2 (0x3210UL)
+#define EFM_REG_LOCK_KEY (0x0000UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_Sector_Size EFM Sector Size
+ * @{
+ */
+#define SECTOR_SIZE (0x2000UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_Sector_Address EFM Sector Address
+ * @{
+ */
+#define EFM_SECTOR_ADDR(x) (uint32_t)(SECTOR_SIZE * (x))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_OTP_Base_Address EFM Otp Base Address
+ * @{
+ */
+#define EFM_OTP_BASE1_ADDR (0x00000000UL)
+#define EFM_OTP_BASE1_SIZE (0x2000UL)
+#define EFM_OTP_BASE1_OFFSET (0UL)
+#define EFM_OTP_BASE2_ADDR (0x03000000UL)
+#define EFM_OTP_BASE2_SIZE (0x800UL)
+#define EFM_OTP_BASE2_OFFSET (16UL)
+#define EFM_OTP_BASE3_ADDR (0x03001000UL)
+#define EFM_OTP_BASE3_SIZE (0x100UL)
+#define EFM_OTP_BASE3_OFFSET (18UL)
+#define EFM_OTP_BASE4_ADDR (0x03001400UL)
+#define EFM_OTP_BASE4_SIZE (0x10UL)
+#define EFM_OTP_BASE4_OFFSET (22UL)
+#define EFM_OTP_BASE5_ADDR (0x03001600UL)
+#define EFM_OTP_BASE5_SIZE (0x04UL)
+#define EFM_OTP_BASE5_OFFSET (54UL)
+#define EFM_OTP_LOCK_ADDR (0x03001800UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_OTP_Address EFM Otp Address
+ * @{
+ */
+#define EFM_OTP_BLOCK0 (EFM_OTP_BASE1_ADDR + ((0UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
+#define EFM_OTP_BLOCK1 (EFM_OTP_BASE1_ADDR + ((1UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
+#define EFM_OTP_BLOCK2 (EFM_OTP_BASE1_ADDR + ((2UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
+#define EFM_OTP_BLOCK3 (EFM_OTP_BASE1_ADDR + ((3UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
+#define EFM_OTP_BLOCK4 (EFM_OTP_BASE1_ADDR + ((4UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
+#define EFM_OTP_BLOCK5 (EFM_OTP_BASE1_ADDR + ((5UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
+#define EFM_OTP_BLOCK6 (EFM_OTP_BASE1_ADDR + ((6UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
+#define EFM_OTP_BLOCK7 (EFM_OTP_BASE1_ADDR + ((7UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
+#define EFM_OTP_BLOCK8 (EFM_OTP_BASE1_ADDR + ((8UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
+#define EFM_OTP_BLOCK9 (EFM_OTP_BASE1_ADDR + ((9UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
+#define EFM_OTP_BLOCK10 (EFM_OTP_BASE1_ADDR + ((10UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
+#define EFM_OTP_BLOCK11 (EFM_OTP_BASE1_ADDR + ((11UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
+#define EFM_OTP_BLOCK12 (EFM_OTP_BASE1_ADDR + ((12UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
+#define EFM_OTP_BLOCK13 (EFM_OTP_BASE1_ADDR + ((13UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
+#define EFM_OTP_BLOCK14 (EFM_OTP_BASE1_ADDR + ((14UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
+
+#define EFM_OTP_BLOCK15 (EFM_OTP_BASE1_ADDR + ((15UL - EFM_OTP_BASE1_OFFSET) * EFM_OTP_BASE1_SIZE))
+
+#define EFM_OTP_BLOCK16 (EFM_OTP_BASE2_ADDR + ((16UL - EFM_OTP_BASE2_OFFSET) * EFM_OTP_BASE2_SIZE))
+#define EFM_OTP_BLOCK17 (EFM_OTP_BASE2_ADDR + ((17UL - EFM_OTP_BASE2_OFFSET) * EFM_OTP_BASE2_SIZE))
+
+#define EFM_OTP_BLOCK18 (EFM_OTP_BASE3_ADDR + ((18UL - EFM_OTP_BASE3_OFFSET) * EFM_OTP_BASE3_SIZE))
+#define EFM_OTP_BLOCK19 (EFM_OTP_BASE3_ADDR + ((19UL - EFM_OTP_BASE3_OFFSET) * EFM_OTP_BASE3_SIZE))
+#define EFM_OTP_BLOCK20 (EFM_OTP_BASE3_ADDR + ((20UL - EFM_OTP_BASE3_OFFSET) * EFM_OTP_BASE3_SIZE))
+#define EFM_OTP_BLOCK21 (EFM_OTP_BASE3_ADDR + ((21UL - EFM_OTP_BASE3_OFFSET) * EFM_OTP_BASE3_SIZE))
+
+#define EFM_OTP_BLOCK22 (EFM_OTP_BASE4_ADDR + ((22UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK23 (EFM_OTP_BASE4_ADDR + ((23UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK24 (EFM_OTP_BASE4_ADDR + ((24UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK25 (EFM_OTP_BASE4_ADDR + ((25UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK26 (EFM_OTP_BASE4_ADDR + ((26UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK27 (EFM_OTP_BASE4_ADDR + ((27UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK28 (EFM_OTP_BASE4_ADDR + ((28UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK29 (EFM_OTP_BASE4_ADDR + ((29UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK30 (EFM_OTP_BASE4_ADDR + ((30UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK31 (EFM_OTP_BASE4_ADDR + ((31UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK32 (EFM_OTP_BASE4_ADDR + ((32UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK33 (EFM_OTP_BASE4_ADDR + ((33UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK34 (EFM_OTP_BASE4_ADDR + ((34UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK35 (EFM_OTP_BASE4_ADDR + ((35UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK36 (EFM_OTP_BASE4_ADDR + ((36UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK37 (EFM_OTP_BASE4_ADDR + ((37UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK38 (EFM_OTP_BASE4_ADDR + ((38UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK39 (EFM_OTP_BASE4_ADDR + ((39UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK40 (EFM_OTP_BASE4_ADDR + ((40UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK41 (EFM_OTP_BASE4_ADDR + ((41UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK42 (EFM_OTP_BASE4_ADDR + ((42UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK43 (EFM_OTP_BASE4_ADDR + ((43UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK44 (EFM_OTP_BASE4_ADDR + ((44UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK45 (EFM_OTP_BASE4_ADDR + ((45UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK46 (EFM_OTP_BASE4_ADDR + ((46UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK47 (EFM_OTP_BASE4_ADDR + ((47UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK48 (EFM_OTP_BASE4_ADDR + ((48UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK49 (EFM_OTP_BASE4_ADDR + ((49UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK50 (EFM_OTP_BASE4_ADDR + ((50UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK51 (EFM_OTP_BASE4_ADDR + ((51UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK52 (EFM_OTP_BASE4_ADDR + ((52UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+#define EFM_OTP_BLOCK53 (EFM_OTP_BASE4_ADDR + ((53UL - EFM_OTP_BASE4_OFFSET) * EFM_OTP_BASE4_SIZE))
+
+#define EFM_OTP_BLOCK54 (EFM_OTP_BASE5_ADDR + ((54UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK55 (EFM_OTP_BASE5_ADDR + ((55UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK56 (EFM_OTP_BASE5_ADDR + ((56UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK57 (EFM_OTP_BASE5_ADDR + ((57UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK58 (EFM_OTP_BASE5_ADDR + ((58UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK59 (EFM_OTP_BASE5_ADDR + ((59UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK60 (EFM_OTP_BASE5_ADDR + ((60UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK61 (EFM_OTP_BASE5_ADDR + ((61UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK62 (EFM_OTP_BASE5_ADDR + ((62UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK63 (EFM_OTP_BASE5_ADDR + ((63UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK64 (EFM_OTP_BASE5_ADDR + ((64UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK65 (EFM_OTP_BASE5_ADDR + ((65UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK66 (EFM_OTP_BASE5_ADDR + ((66UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK67 (EFM_OTP_BASE5_ADDR + ((67UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK68 (EFM_OTP_BASE5_ADDR + ((68UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK69 (EFM_OTP_BASE5_ADDR + ((69UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK70 (EFM_OTP_BASE5_ADDR + ((70UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK71 (EFM_OTP_BASE5_ADDR + ((71UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK72 (EFM_OTP_BASE5_ADDR + ((72UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK73 (EFM_OTP_BASE5_ADDR + ((73UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK74 (EFM_OTP_BASE5_ADDR + ((74UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK75 (EFM_OTP_BASE5_ADDR + ((75UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK76 (EFM_OTP_BASE5_ADDR + ((76UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK77 (EFM_OTP_BASE5_ADDR + ((77UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK78 (EFM_OTP_BASE5_ADDR + ((78UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK79 (EFM_OTP_BASE5_ADDR + ((79UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK80 (EFM_OTP_BASE5_ADDR + ((80UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK81 (EFM_OTP_BASE5_ADDR + ((81UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK82 (EFM_OTP_BASE5_ADDR + ((82UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK83 (EFM_OTP_BASE5_ADDR + ((83UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK84 (EFM_OTP_BASE5_ADDR + ((84UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK85 (EFM_OTP_BASE5_ADDR + ((85UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK86 (EFM_OTP_BASE5_ADDR + ((86UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK87 (EFM_OTP_BASE5_ADDR + ((87UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK88 (EFM_OTP_BASE5_ADDR + ((88UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK89 (EFM_OTP_BASE5_ADDR + ((89UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK90 (EFM_OTP_BASE5_ADDR + ((90UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK91 (EFM_OTP_BASE5_ADDR + ((91UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK92 (EFM_OTP_BASE5_ADDR + ((92UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK93 (EFM_OTP_BASE5_ADDR + ((93UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK94 (EFM_OTP_BASE5_ADDR + ((94UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK95 (EFM_OTP_BASE5_ADDR + ((95UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK96 (EFM_OTP_BASE5_ADDR + ((96UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK97 (EFM_OTP_BASE5_ADDR + ((97UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK98 (EFM_OTP_BASE5_ADDR + ((98UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK99 (EFM_OTP_BASE5_ADDR + ((99UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK100 (EFM_OTP_BASE5_ADDR + ((100UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK101 (EFM_OTP_BASE5_ADDR + ((101UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK102 (EFM_OTP_BASE5_ADDR + ((102UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK103 (EFM_OTP_BASE5_ADDR + ((103UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK104 (EFM_OTP_BASE5_ADDR + ((104UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK105 (EFM_OTP_BASE5_ADDR + ((105UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK106 (EFM_OTP_BASE5_ADDR + ((106UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK107 (EFM_OTP_BASE5_ADDR + ((107UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK108 (EFM_OTP_BASE5_ADDR + ((108UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK109 (EFM_OTP_BASE5_ADDR + ((109UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK110 (EFM_OTP_BASE5_ADDR + ((110UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK111 (EFM_OTP_BASE5_ADDR + ((111UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK112 (EFM_OTP_BASE5_ADDR + ((112UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK113 (EFM_OTP_BASE5_ADDR + ((113UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK114 (EFM_OTP_BASE5_ADDR + ((114UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK115 (EFM_OTP_BASE5_ADDR + ((115UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK116 (EFM_OTP_BASE5_ADDR + ((116UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK117 (EFM_OTP_BASE5_ADDR + ((117UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK118 (EFM_OTP_BASE5_ADDR + ((118UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK119 (EFM_OTP_BASE5_ADDR + ((119UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK120 (EFM_OTP_BASE5_ADDR + ((120UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK121 (EFM_OTP_BASE5_ADDR + ((121UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK122 (EFM_OTP_BASE5_ADDR + ((122UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK123 (EFM_OTP_BASE5_ADDR + ((123UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK124 (EFM_OTP_BASE5_ADDR + ((124UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK125 (EFM_OTP_BASE5_ADDR + ((125UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK126 (EFM_OTP_BASE5_ADDR + ((126UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK127 (EFM_OTP_BASE5_ADDR + ((127UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK128 (EFM_OTP_BASE5_ADDR + ((128UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK129 (EFM_OTP_BASE5_ADDR + ((129UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK130 (EFM_OTP_BASE5_ADDR + ((130UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK131 (EFM_OTP_BASE5_ADDR + ((131UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK132 (EFM_OTP_BASE5_ADDR + ((132UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK133 (EFM_OTP_BASE5_ADDR + ((133UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK134 (EFM_OTP_BASE5_ADDR + ((134UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK135 (EFM_OTP_BASE5_ADDR + ((135UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK136 (EFM_OTP_BASE5_ADDR + ((136UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK137 (EFM_OTP_BASE5_ADDR + ((137UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK138 (EFM_OTP_BASE5_ADDR + ((138UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK139 (EFM_OTP_BASE5_ADDR + ((139UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK140 (EFM_OTP_BASE5_ADDR + ((140UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK141 (EFM_OTP_BASE5_ADDR + ((141UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK142 (EFM_OTP_BASE5_ADDR + ((142UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK143 (EFM_OTP_BASE5_ADDR + ((143UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK144 (EFM_OTP_BASE5_ADDR + ((144UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK145 (EFM_OTP_BASE5_ADDR + ((145UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK146 (EFM_OTP_BASE5_ADDR + ((146UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK147 (EFM_OTP_BASE5_ADDR + ((147UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK148 (EFM_OTP_BASE5_ADDR + ((148UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK149 (EFM_OTP_BASE5_ADDR + ((149UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK150 (EFM_OTP_BASE5_ADDR + ((150UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK151 (EFM_OTP_BASE5_ADDR + ((151UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK152 (EFM_OTP_BASE5_ADDR + ((152UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK153 (EFM_OTP_BASE5_ADDR + ((153UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK154 (EFM_OTP_BASE5_ADDR + ((154UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK155 (EFM_OTP_BASE5_ADDR + ((155UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK156 (EFM_OTP_BASE5_ADDR + ((156UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK157 (EFM_OTP_BASE5_ADDR + ((157UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK158 (EFM_OTP_BASE5_ADDR + ((158UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK159 (EFM_OTP_BASE5_ADDR + ((159UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK160 (EFM_OTP_BASE5_ADDR + ((160UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK161 (EFM_OTP_BASE5_ADDR + ((161UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK162 (EFM_OTP_BASE5_ADDR + ((162UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK163 (EFM_OTP_BASE5_ADDR + ((163UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK164 (EFM_OTP_BASE5_ADDR + ((164UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK165 (EFM_OTP_BASE5_ADDR + ((165UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK166 (EFM_OTP_BASE5_ADDR + ((166UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK167 (EFM_OTP_BASE5_ADDR + ((167UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK168 (EFM_OTP_BASE5_ADDR + ((168UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK169 (EFM_OTP_BASE5_ADDR + ((169UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK170 (EFM_OTP_BASE5_ADDR + ((170UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK171 (EFM_OTP_BASE5_ADDR + ((171UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK172 (EFM_OTP_BASE5_ADDR + ((172UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK173 (EFM_OTP_BASE5_ADDR + ((173UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK174 (EFM_OTP_BASE5_ADDR + ((174UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK175 (EFM_OTP_BASE5_ADDR + ((175UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK176 (EFM_OTP_BASE5_ADDR + ((176UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK177 (EFM_OTP_BASE5_ADDR + ((177UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK178 (EFM_OTP_BASE5_ADDR + ((178UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK179 (EFM_OTP_BASE5_ADDR + ((179UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK180 (EFM_OTP_BASE5_ADDR + ((180UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+#define EFM_OTP_BLOCK181 (EFM_OTP_BASE5_ADDR + ((181UL - EFM_OTP_BASE5_OFFSET) * EFM_OTP_BASE5_SIZE))
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_OTP_Lock_Address EFM Otp Lock_address
+ * x at range of 0~181
+ * @{
+ */
+#define EFM_OTP_BLOCK_LOCKADDR(x) (EFM_OTP_LOCK_ADDR + 0x04UL * (x)) /*!< OTP block x lock address */
+/**
+ * @}
+ */
+
+#define EFM_REMAP_REG_LOCK_KEY (0x0000UL)
+#define EFM_REMAP_REG_UNLOCK_KEY1 (0x0123UL)
+#define EFM_REMAP_REG_UNLOCK_KEY2 (0x3210UL)
+
+/**
+ * @defgroup EFM_Remap_State EFM remap function state
+ * @{
+ */
+#define EFM_REMAP_OFF (0UL)
+#define EFM_REMAP_ON (EFM_MMF_REMCR_EN)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_Remap_Size EFM remap size definition
+ * @note refer to chip user manual for details size spec.
+ * @{
+ */
+#define EFM_REMAP_4K (12UL)
+#define EFM_REMAP_8K (13UL)
+#define EFM_REMAP_16K (14UL)
+#define EFM_REMAP_32K (15UL)
+#define EFM_REMAP_64K (16UL)
+#define EFM_REMAP_128K (17UL)
+#define EFM_REMAP_256K (18UL)
+#define EFM_REMAP_512K (19UL)
+#define EFM_REMAP_SIZE_MAX EFM_REMAP_512K
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_Remap_Index EFM remap index
+ * @{
+ */
+#define EFM_REMAP_IDX0 (0U)
+#define EFM_REMAP_IDX1 (1U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_Remap_BaseAddr EFM remap base address
+ * @{
+ */
+#define EFM_REMAP_BASE_ADDR0 (0x2000000UL)
+#define EFM_REMAP_BASE_ADDR1 (0x2080000UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_Remap_Region EFM remap ROM/RAM region
+ * @{
+ */
+#define EFM_REMAP_ROM_END_ADDR EFM_END_ADDR
+
+#define EFM_REMAP_RAM_START_ADDR (0x1FFF8000UL)
+#define EFM_REMAP_RAM_END_ADDR (0x1FFFFFFFUL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_Protect_Level EFM protect level
+ * @{
+ */
+#define EFM_PROTECT_LEVEL1 (1U)
+#define EFM_PROTECT_LEVEL2 (2U)
+#define EFM_PROTECT_LEVEL3 (4U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_MCU_Status EFM protect level
+ * @{
+ */
+#define EFM_MCU_PROTECT1_FREE (0U)
+#define EFM_MCU_PROTECT1_LOCK (1U)
+#define EFM_MCU_PROTECT1_UNLOCK (2U)
+#define EFM_MCU_PROTECT2_LOCK (4U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup EFM_Global_Functions
+ * @{
+ */
+
+/**
+ * @brief EFM Protect Unlock.
+ * @param None
+ * @retval None
+ */
+
+__STATIC_INLINE void EFM_REG_Unlock(void)
+{
+ WRITE_REG32(CM_EFM->FAPRT, EFM_REG_UNLOCK_KEY1);
+ WRITE_REG32(CM_EFM->FAPRT, EFM_REG_UNLOCK_KEY2);
+}
+
+/**
+ * @brief EFM Protect Lock.
+ * @param None
+ * @retval None
+ */
+__STATIC_INLINE void EFM_REG_Lock(void)
+{
+ WRITE_REG32(CM_EFM->FAPRT, EFM_REG_LOCK_KEY);
+}
+
+/**
+ * @brief EFM remap Unlock.
+ * @param None
+ * @retval None
+ */
+__STATIC_INLINE void EFM_REMAP_Unlock(void)
+{
+ WRITE_REG32(CM_EFM->MMF_REMPRT, EFM_REMAP_REG_UNLOCK_KEY1);
+ WRITE_REG32(CM_EFM->MMF_REMPRT, EFM_REMAP_REG_UNLOCK_KEY2);
+}
+
+/**
+ * @brief EFM remap Lock.
+ * @param None
+ * @retval None
+ */
+__STATIC_INLINE void EFM_REMAP_Lock(void)
+{
+ WRITE_REG32(CM_EFM->MMF_REMPRT, EFM_REMAP_REG_LOCK_KEY);
+}
+
+void EFM_Cmd(uint32_t u32Flash, en_functional_state_t enNewState);
+void EFM_FWMC_Cmd(en_functional_state_t enNewState);
+void EFM_SetBusStatus(uint32_t u32Status);
+void EFM_IntCmd(uint32_t u32EfmInt, en_functional_state_t enNewState);
+void EFM_ClearStatus(uint32_t u32Flag);
+int32_t EFM_SetWaitCycle(uint32_t u32WaitCycle);
+int32_t EFM_SetOperateMode(uint32_t u32Mode);
+int32_t EFM_ReadByte(uint32_t u32Addr, uint8_t *pu8ReadBuf, uint32_t u32ByteLen);
+int32_t EFM_Program(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len);
+int32_t EFM_ProgramWord(uint32_t u32Addr, uint32_t u32Data);
+int32_t EFM_ProgramWordReadBack(uint32_t u32Addr, uint32_t u32Data);
+int32_t EFM_SequenceProgram(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len);
+int32_t EFM_SectorErase(uint32_t u32Addr);
+int32_t EFM_ChipErase(uint8_t u8Chip);
+
+en_flag_status_t EFM_GetAnyStatus(uint32_t u32Flag);
+en_flag_status_t EFM_GetStatus(uint32_t u32Flag);
+void EFM_GetUID(stc_efm_unique_id_t *pstcUID);
+
+void EFM_CacheRamReset(en_functional_state_t enNewState);
+void EFM_PrefetchCmd(en_functional_state_t enNewState);
+void EFM_DCacheCmd(en_functional_state_t enNewState);
+void EFM_ICacheCmd(en_functional_state_t enNewState);
+
+void EFM_LowVoltageReadCmd(en_functional_state_t enNewState);
+int32_t EFM_SwapCmd(en_functional_state_t enNewState);
+en_flag_status_t EFM_GetSwapStatus(void);
+int32_t EFM_OTP_Lock(uint32_t u32Addr);
+
+int32_t EFM_REMAP_StructInit(stc_efm_remap_init_t *pstcEfmRemapInit);
+int32_t EFM_REMAP_Init(uint8_t u8RemapIdx, stc_efm_remap_init_t *pstcEfmRemapInit);
+void EFM_REMAP_DeInit(void);
+void EFM_REMAP_Cmd(uint8_t u8RemapIdx, en_functional_state_t enNewState);
+void EFM_REMAP_SetAddr(uint8_t u8RemapIdx, uint32_t u32Addr);
+void EFM_REMAP_SetSize(uint8_t u8RemapIdx, uint32_t u32Size);
+
+uint32_t EFM_GetCID(void);
+void EFM_OTP_WP_Unlock(void);
+void EFM_OTP_WP_Lock(void);
+int32_t EFM_OTP_Enable(void);
+void EFM_SectorProtectRegLock(uint32_t u32RegLock);
+void EFM_SingleSectorOperateCmd(uint8_t u8SectorNum, en_functional_state_t enNewState);
+void EFM_SequenceSectorOperateCmd(uint32_t u32StartSectorNum, uint16_t u16Count, en_functional_state_t enNewState);
+
+void EFM_Protect_Enable(uint8_t u8Level);
+int32_t EFM_WriteSecurityCode(uint8_t *pu8Buf, uint32_t u32Len);
+
+/**
+ * @}
+ */
+
+#endif /* LL_EFM_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_EFM_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_emb.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_emb.h
new file mode 100644
index 0000000000..fa2d3d50e0
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_emb.h
@@ -0,0 +1,586 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_emb.h
+ * @brief This file contains all the functions prototypes of the EMB
+ * (Emergency Brake) driver library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-09-30 CDT Update EMB_CTL1_CMPEN0~3 to EMB_CTL1_CMPEN1~4
+ Update EMB_INTEN_PORTINTEN to EMB_INTEN_PORTININTEN
+ 2023-12-15 CDT Add stc_emb_monitor_sys_t to combine osc, sram, lockup, lvd
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_EMB_H__
+#define __HC32_LL_EMB_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_EMB
+ * @{
+ */
+
+#if (LL_EMB_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup EMB_Global_Types EMB Global Types
+ * @{
+ */
+
+/**
+ * @brief EMB monitor system exception configuration
+ */
+typedef struct {
+ uint32_t u32Osc; /*!< Enable or disable EMB detect OSC failure function
+ This parameter can be a value of @ref EMB_OSC_Selection */
+ uint32_t u32SramEccError; /*!< EMB detect SRAM ECC error function
+ This parameter can be a value of @ref EMB_SRAM_ECC_Error_Selection */
+ uint32_t u32SramParityError; /*!< EMB detect SRAM parity error function
+ This parameter can be a value of @ref EMB_SRAM_Parity_Error_Selection */
+ uint32_t u32Lockup; /*!< EMB detect lockup function
+ This parameter can be a value of @ref EMB_Lockup_Selection */
+ uint32_t u32Lvd; /*!< EMB detect LVD function
+ This parameter can be a value of @ref EMB_LVD_Selection */
+} stc_emb_monitor_sys_t;
+
+/**
+ * @brief EMB monitor EMB port configuration
+ */
+typedef struct {
+ uint32_t u32PortState; /*!< Enable or disable EMB detect port in control function
+ This parameter can be a value of @ref EMB_Port_Selection */
+ uint32_t u32PortLevel; /*!< EMB detect port level
+ This parameter can be a value of @ref EMB_Detect_Port_Level */
+ uint32_t u32PortFilterDiv; /*!< EMB port filter division
+ This parameter can be a value of @ref EMB_Port_Filter_Clock_Division */
+ uint32_t u32PortFilterState; /*!< Enable or disable EMB detect port filter in control function
+ This parameter can be a value of @ref EMB_Port_Filter_Selection */
+} stc_emb_monitor_port_config_t;
+
+/**
+ * @brief EMB monitor PWM configuration
+ */
+typedef struct {
+ uint32_t u32PwmState; /*!< Enable or disable EMB detect timer same phase function
+ This parameter can be a value of @ref EMB_Detect_PWM state. */
+ uint32_t u32PwmLevel; /*!< Detect timer polarity level
+ This parameter can be a value of @ref EMB_Detect_PWM level */
+} stc_emb_monitor_tmr_pwm_t;
+
+/**
+ * @brief EMB monitor port in configuration
+ */
+typedef struct {
+ stc_emb_monitor_port_config_t stcPort1; /*!< EMB detect EMB port in function
+ This parameter details refer @ref stc_emb_monitor_port_config_t structure */
+ stc_emb_monitor_port_config_t stcPort2; /*!< EMB detect EMB port in function
+ This parameter details refer @ref stc_emb_monitor_port_config_t structure */
+ stc_emb_monitor_port_config_t stcPort3; /*!< EMB detect EMB port in function
+ This parameter details refer @ref stc_emb_monitor_port_config_t structure */
+ stc_emb_monitor_port_config_t stcPort4; /*!< EMB detect EMB port in function
+ This parameter details refer @ref stc_emb_monitor_port_config_t structure */
+ stc_emb_monitor_port_config_t stcPort5; /*!< EMB detect EMB port in function
+ This parameter details refer @ref stc_emb_monitor_port_config_t structure */
+} stc_emb_monitor_port_t;
+
+/**
+ * @brief EMB monitor CMP configuration
+ */
+typedef struct {
+ uint32_t u32Cmp1State; /*!< Enable or disable EMB detect CMP1 result function
+ This parameter can be a value of @ref EMB_CMP_Selection */
+ uint32_t u32Cmp2State; /*!< Enable or disable EMB detect CMP2 result function
+ This parameter can be a value of @ref EMB_CMP_Selection */
+ uint32_t u32Cmp3State; /*!< Enable or disable EMB detect CMP3 result function
+ This parameter can be a value of @ref EMB_CMP_Selection */
+ uint32_t u32Cmp4State; /*!< Enable or disable EMB detect CMP4 result function
+ This parameter can be a value of @ref EMB_CMP_Selection */
+} stc_emb_monitor_cmp_t;
+
+/**
+ * @brief EMB monitor TMR4 configuration
+ */
+typedef struct {
+ stc_emb_monitor_tmr_pwm_t stcTmr4PwmU; /*!< EMB detect TMR4 function
+ This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
+ stc_emb_monitor_tmr_pwm_t stcTmr4PwmV; /*!< EMB detect TMR4 function
+ This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
+ stc_emb_monitor_tmr_pwm_t stcTmr4PwmW; /*!< EMB detect TMR4 function
+ This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
+} stc_emb_monitor_tmr4_t;
+
+/**
+ * @brief EMB control TMR4 initialization configuration
+ */
+typedef struct {
+ stc_emb_monitor_cmp_t stcCmp; /*!< EMB detect CMP function
+ This parameter details refer @ref stc_emb_monitor_cmp_t structure */
+ stc_emb_monitor_port_t stcPort; /*!< EMB detect EMB port function
+ This parameter details refer @ref stc_emb_monitor_port_t structure */
+ stc_emb_monitor_tmr4_t stcTmr4; /*!< EMB detect TMR4 function
+ This parameter details refer @ref stc_emb_monitor_tmr4_t structure */
+ stc_emb_monitor_sys_t stcSys; /*!< EMB detect System function
+ This parameter details refer @ref stc_emb_monitor_sys_t structure */
+} stc_emb_tmr4_init_t;
+
+/**
+ * @brief EMB monitor TMR6 configuration
+ */
+typedef struct {
+ stc_emb_monitor_tmr_pwm_t stcTmr6_1; /*!< EMB detect TMR6 function
+ This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
+ stc_emb_monitor_tmr_pwm_t stcTmr6_2; /*!< EMB detect TMR6 function
+ This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
+ stc_emb_monitor_tmr_pwm_t stcTmr6_3; /*!< EMB detect TMR6 function
+ This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
+ stc_emb_monitor_tmr_pwm_t stcTmr6_4; /*!< EMB detect TMR6 function
+ This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
+ stc_emb_monitor_tmr_pwm_t stcTmr6_5; /*!< EMB detect TMR6 function
+ This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
+ stc_emb_monitor_tmr_pwm_t stcTmr6_6; /*!< EMB detect TMR6 function
+ This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
+ stc_emb_monitor_tmr_pwm_t stcTmr6_7; /*!< EMB detect TMR6 function
+ This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
+ stc_emb_monitor_tmr_pwm_t stcTmr6_8; /*!< EMB detect TMR6 function
+ This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
+ stc_emb_monitor_tmr_pwm_t stcTmr6_9; /*!< EMB detect TMR6 function
+ This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
+ stc_emb_monitor_tmr_pwm_t stcTmr6_10; /*!< EMB detect TMR6 function
+ This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */
+} stc_emb_monitor_tmr6_t;
+
+/**
+ * @brief EMB control TMR6 initialization configuration
+ */
+typedef struct {
+ stc_emb_monitor_cmp_t stcCmp; /*!< EMB detect CMP function
+ This parameter details refer @ref stc_emb_monitor_cmp_t structure */
+ stc_emb_monitor_port_t stcPort; /*!< EMB detect EMB port function
+ This parameter details refer @ref stc_emb_monitor_port_t structure */
+ stc_emb_monitor_tmr6_t stcTmr6; /*!< EMB detect TMR6 function
+ This parameter details refer @ref stc_emb_monitor_tmr6_t structure */
+ stc_emb_monitor_sys_t stcSys; /*!< EMB detect System function
+ This parameter details refer @ref stc_emb_monitor_sys_t structure */
+} stc_emb_tmr6_init_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup EMB_Global_Macros EMB Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup EMB_CMP_Selection EMB CMP Selection
+ * @{
+ */
+#define EMB_CMP1_DISABLE (0UL)
+#define EMB_CMP2_DISABLE (0UL)
+#define EMB_CMP3_DISABLE (0UL)
+#define EMB_CMP4_DISABLE (0UL)
+
+#define EMB_CMP1_ENABLE (EMB_CTL1_CMPEN1)
+#define EMB_CMP2_ENABLE (EMB_CTL1_CMPEN2)
+#define EMB_CMP3_ENABLE (EMB_CTL1_CMPEN3)
+#define EMB_CMP4_ENABLE (EMB_CTL1_CMPEN4)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EMB_OSC_Selection EMB OSC Selection
+ * @{
+ */
+#define EMB_OSC_DISABLE (0UL)
+#define EMB_OSC_ENABLE (EMB_CTL1_OSCSTPEN)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EMB_SRAM_ECC_Error_Selection EMB SRAM ECC Error Selection
+ * @{
+ */
+#define EMB_SRAM_ECC_ERR_DISABLE (0UL)
+#define EMB_SRAM_ECC_ERR_ENABLE (EMB_CTL1_SRAMERREN)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EMB_SRAM_Parity_Error_Selection EMB SRAM Parity Error Selection
+ * @{
+ */
+#define EMB_SRAM_PARITY_ERR_DISABLE (0UL)
+#define EMB_SRAM_PARITY_ERR_ENABLE (EMB_CTL1_SRAMPYERREN)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EMB_Lockup_Selection EMB Lockup Selection
+ * @{
+ */
+#define EMB_LOCKUP_DISABLE (0UL)
+#define EMB_LOCKUP_ENABLE (EMB_CTL1_LOCKUPEN)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EMB_LVD_Selection EMB LVD Selection
+ * @{
+ */
+#define EMB_LVD_DISABLE (0UL)
+#define EMB_LVD_ENABLE (EMB_CTL1_PVDEN)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EMB_Detect_PWM EMB Detect PWM
+ * @{
+ */
+/**
+ * @defgroup EMB_TMR4_PWM_Selection EMB TMR4 PWM Selection
+ * @{
+ */
+#define EMB_TMR4_PWM_W_DISABLE (0UL)
+#define EMB_TMR4_PWM_V_DISABLE (0UL)
+#define EMB_TMR4_PWM_U_DISABLE (0UL)
+
+#define EMB_TMR4_PWM_W_ENABLE (EMB_CTL1_PWMSEN0)
+#define EMB_TMR4_PWM_V_ENABLE (EMB_CTL1_PWMSEN1)
+#define EMB_TMR4_PWM_U_ENABLE (EMB_CTL1_PWMSEN2)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EMB_Detect_TMR4_PWM_Level EMB Detect TMR4 PWM Level
+ * @{
+ */
+#define EMB_DETECT_TMR4_PWM_W_BOTH_LOW (0UL)
+#define EMB_DETECT_TMR4_PWM_V_BOTH_LOW (0UL)
+#define EMB_DETECT_TMR4_PWM_U_BOTH_LOW (0UL)
+
+#define EMB_DETECT_TMR4_PWM_W_BOTH_HIGH (EMB_CTL2_PWMLV0)
+#define EMB_DETECT_TMR4_PWM_V_BOTH_HIGH (EMB_CTL2_PWMLV1)
+#define EMB_DETECT_TMR4_PWM_U_BOTH_HIGH (EMB_CTL2_PWMLV2)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EMB_TMR6_PWM_Selection EMB TMR6 PWM Selection
+ * @{
+ */
+#define EMB_TMR6_1_PWM_DISABLE (0UL)
+#define EMB_TMR6_2_PWM_DISABLE (0UL)
+#define EMB_TMR6_3_PWM_DISABLE (0UL)
+#define EMB_TMR6_4_PWM_DISABLE (0UL)
+#define EMB_TMR6_5_PWM_DISABLE (0UL)
+#define EMB_TMR6_6_PWM_DISABLE (0UL)
+#define EMB_TMR6_7_PWM_DISABLE (0UL)
+#define EMB_TMR6_8_PWM_DISABLE (0UL)
+#define EMB_TMR6_9_PWM_DISABLE (0UL)
+#define EMB_TMR6_10_PWM_DISABLE (0UL)
+
+#define EMB_TMR6_1_PWM_ENABLE (EMB_CTL1_PWMSEN0)
+#define EMB_TMR6_2_PWM_ENABLE (EMB_CTL1_PWMSEN1)
+#define EMB_TMR6_3_PWM_ENABLE (EMB_CTL1_PWMSEN2)
+#define EMB_TMR6_4_PWM_ENABLE (EMB_CTL1_PWMSEN3)
+#define EMB_TMR6_5_PWM_ENABLE (EMB_CTL1_PWMSEN4)
+#define EMB_TMR6_6_PWM_ENABLE (EMB_CTL1_PWMSEN5)
+#define EMB_TMR6_7_PWM_ENABLE (EMB_CTL1_PWMSEN6)
+#define EMB_TMR6_8_PWM_ENABLE (EMB_CTL1_PWMSEN7)
+#define EMB_TMR6_9_PWM_ENABLE (EMB_CTL1_PWMSEN8)
+#define EMB_TMR6_10_PWM_ENABLE (EMB_CTL1_PWMSEN9)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EMB_Detect_TMR6_PWM_Level EMB Detect TMR6 PWM Level
+ * @{
+ */
+#define EMB_DETECT_TMR6_1_PWM_BOTH_LOW (0UL)
+#define EMB_DETECT_TMR6_2_PWM_BOTH_LOW (0UL)
+#define EMB_DETECT_TMR6_3_PWM_BOTH_LOW (0UL)
+#define EMB_DETECT_TMR6_4_PWM_BOTH_LOW (0UL)
+#define EMB_DETECT_TMR6_5_PWM_BOTH_LOW (0UL)
+#define EMB_DETECT_TMR6_6_PWM_BOTH_LOW (0UL)
+#define EMB_DETECT_TMR6_7_PWM_BOTH_LOW (0UL)
+#define EMB_DETECT_TMR6_8_PWM_BOTH_LOW (0UL)
+#define EMB_DETECT_TMR6_9_PWM_BOTH_LOW (0UL)
+#define EMB_DETECT_TMR6_10_PWM_BOTH_LOW (0UL)
+
+#define EMB_DETECT_TMR6_1_PWM_BOTH_HIGH (EMB_CTL2_PWMLV0)
+#define EMB_DETECT_TMR6_2_PWM_BOTH_HIGH (EMB_CTL2_PWMLV1)
+#define EMB_DETECT_TMR6_3_PWM_BOTH_HIGH (EMB_CTL2_PWMLV2)
+#define EMB_DETECT_TMR6_4_PWM_BOTH_HIGH (EMB_CTL2_PWMLV3)
+#define EMB_DETECT_TMR6_5_PWM_BOTH_HIGH (EMB_CTL2_PWMLV4)
+#define EMB_DETECT_TMR6_6_PWM_BOTH_HIGH (EMB_CTL2_PWMLV5)
+#define EMB_DETECT_TMR6_7_PWM_BOTH_HIGH (EMB_CTL2_PWMLV6)
+#define EMB_DETECT_TMR6_8_PWM_BOTH_HIGH (EMB_CTL2_PWMLV7)
+#define EMB_DETECT_TMR6_9_PWM_BOTH_HIGH (EMB_CTL2_PWMLV8)
+#define EMB_DETECT_TMR6_10_PWM_BOTH_HIGH (EMB_CTL2_PWMLV9)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EMB_Port_Selection EMB Port Selection
+ * @{
+ */
+#define EMB_PORT1_DISABLE (0UL)
+#define EMB_PORT2_DISABLE (0UL)
+#define EMB_PORT3_DISABLE (0UL)
+#define EMB_PORT4_DISABLE (0UL)
+#define EMB_PORT5_DISABLE (0UL)
+
+#define EMB_PORT1_ENABLE (EMB_CTL1_PORTINEN1)
+#define EMB_PORT2_ENABLE (EMB_CTL1_PORTINEN2)
+#define EMB_PORT3_ENABLE (EMB_CTL1_PORTINEN3)
+#define EMB_PORT4_ENABLE (EMB_CTL1_PORTINEN4)
+#define EMB_PORT5_ENABLE (EMB_CTL1_PORTINEN5)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EMB_Detect_Port_Level EMB Detect Port Level
+ * @{
+ */
+#define EMB_PORT1_DETECT_LVL_HIGH (0UL)
+#define EMB_PORT2_DETECT_LVL_HIGH (0UL)
+#define EMB_PORT3_DETECT_LVL_HIGH (0UL)
+#define EMB_PORT4_DETECT_LVL_HIGH (0UL)
+#define EMB_PORT5_DETECT_LVL_HIGH (0UL)
+
+#define EMB_PORT1_DETECT_LVL_LOW (EMB_CTL1_INVSEL1)
+#define EMB_PORT2_DETECT_LVL_LOW (EMB_CTL1_INVSEL2)
+#define EMB_PORT3_DETECT_LVL_LOW (EMB_CTL1_INVSEL3)
+#define EMB_PORT4_DETECT_LVL_LOW (EMB_CTL1_INVSEL4)
+#define EMB_PORT5_DETECT_LVL_LOW (EMB_CTL1_INVSEL5)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EMB_Port_Filter_Selection EMB Port Filter Selection
+ * @{
+ */
+#define EMB_PORT1_FILTER_DISABLE (0UL)
+#define EMB_PORT2_FILTER_DISABLE (0UL)
+#define EMB_PORT3_FILTER_DISABLE (0UL)
+#define EMB_PORT4_FILTER_DISABLE (0UL)
+#define EMB_PORT5_FILTER_DISABLE (0UL)
+
+#define EMB_PORT1_FILTER_ENABLE (EMB_CTL2_NFEN1)
+#define EMB_PORT2_FILTER_ENABLE (EMB_CTL2_NFEN2)
+#define EMB_PORT3_FILTER_ENABLE (EMB_CTL2_NFEN3)
+#define EMB_PORT4_FILTER_ENABLE (EMB_CTL2_NFEN4)
+#define EMB_PORT5_FILTER_ENABLE (EMB_CTL2_NFEN5)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EMB_Port_Filter_Clock_Division EMB Port Filter Clock Division
+ * @{
+ */
+#define EMB_PORT1_FILTER_CLK_DIV1 (0UL << EMB_CTL2_NFSEL1_POS)
+#define EMB_PORT1_FILTER_CLK_DIV8 (1UL << EMB_CTL2_NFSEL1_POS)
+#define EMB_PORT1_FILTER_CLK_DIV32 (2UL << EMB_CTL2_NFSEL1_POS)
+#define EMB_PORT1_FILTER_CLK_DIV128 (3UL << EMB_CTL2_NFSEL1_POS)
+
+#define EMB_PORT2_FILTER_CLK_DIV1 (0UL << EMB_CTL2_NFSEL2_POS)
+#define EMB_PORT2_FILTER_CLK_DIV8 (1UL << EMB_CTL2_NFSEL2_POS)
+#define EMB_PORT2_FILTER_CLK_DIV32 (2UL << EMB_CTL2_NFSEL2_POS)
+#define EMB_PORT2_FILTER_CLK_DIV128 (3UL << EMB_CTL2_NFSEL2_POS)
+
+#define EMB_PORT3_FILTER_CLK_DIV1 (0UL << EMB_CTL2_NFSEL3_POS)
+#define EMB_PORT3_FILTER_CLK_DIV8 (1UL << EMB_CTL2_NFSEL3_POS)
+#define EMB_PORT3_FILTER_CLK_DIV32 (2UL << EMB_CTL2_NFSEL3_POS)
+#define EMB_PORT3_FILTER_CLK_DIV128 (3UL << EMB_CTL2_NFSEL3_POS)
+
+#define EMB_PORT4_FILTER_CLK_DIV1 (0UL << EMB_CTL2_NFSEL4_POS)
+#define EMB_PORT4_FILTER_CLK_DIV8 (1UL << EMB_CTL2_NFSEL4_POS)
+#define EMB_PORT4_FILTER_CLK_DIV32 (2UL << EMB_CTL2_NFSEL4_POS)
+#define EMB_PORT4_FILTER_CLK_DIV128 (3UL << EMB_CTL2_NFSEL4_POS)
+
+#define EMB_PORT5_FILTER_CLK_DIV1 (0UL << EMB_CTL2_NFSEL5_POS)
+#define EMB_PORT5_FILTER_CLK_DIV8 (1UL << EMB_CTL2_NFSEL5_POS)
+#define EMB_PORT5_FILTER_CLK_DIV32 (2UL << EMB_CTL2_NFSEL5_POS)
+#define EMB_PORT5_FILTER_CLK_DIV128 (3UL << EMB_CTL2_NFSEL5_POS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EMB_Flag_State EMB Flag State
+ * @{
+ */
+#define EMB_FLAG_PWMS (EMB_STAT_PWMSF)
+#define EMB_FLAG_CMP (EMB_STAT_CMPF)
+#define EMB_FLAG_SYS (EMB_STAT_SYSF)
+#define EMB_FLAG_PORT1 (EMB_STAT_PORTINF1)
+#define EMB_FLAG_PORT2 (EMB_STAT_PORTINF2)
+#define EMB_FLAG_PORT3 (EMB_STAT_PORTINF3)
+#define EMB_FLAG_PORT4 (EMB_STAT_PORTINF4)
+#define EMB_FLAG_PORT5 (EMB_STAT_PORTINF5)
+#define EMB_STAT_PWMS (EMB_STAT_PWMST)
+#define EMB_STAT_CMP (EMB_STAT_CMPST)
+#define EMB_STAT_SYS (EMB_STAT_SYSST)
+#define EMB_STAT_PORT1 (EMB_STAT_PORTINST1)
+#define EMB_STAT_PORT2 (EMB_STAT_PORTINST2)
+#define EMB_STAT_PORT3 (EMB_STAT_PORTINST3)
+#define EMB_STAT_PORT4 (EMB_STAT_PORTINST4)
+#define EMB_STAT_PORT5 (EMB_STAT_PORTINST5)
+#define EMB_FLAG_ALL (EMB_FLAG_PWMS | EMB_FLAG_CMP | EMB_FLAG_SYS | EMB_FLAG_PORT1 | \
+ EMB_FLAG_PORT2 | EMB_FLAG_PORT3 | EMB_FLAG_PORT4 | EMB_FLAG_PORT5 | \
+ EMB_STAT_PWMS | EMB_STAT_CMP | EMB_STAT_SYS | EMB_STAT_PORT1 | \
+ EMB_STAT_PORT2 | EMB_STAT_PORT3 | EMB_STAT_PORT4 | EMB_STAT_PORT5)
+#define EMB_FLAG_CLR_ALL (EMB_FLAG_PWMS | EMB_FLAG_CMP | EMB_FLAG_SYS | EMB_FLAG_PORT1 | \
+ EMB_FLAG_PORT2 | EMB_FLAG_PORT3 | EMB_FLAG_PORT4 | EMB_FLAG_PORT5)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EMB_Interrupt EMB Interrupt
+ * @{
+ */
+#define EMB_INT_PWMS (EMB_INTEN_PWMSINTEN)
+#define EMB_INT_CMP (EMB_INTEN_CMPINTEN)
+#define EMB_INT_SYS (EMB_INTEN_SYSINTEN)
+#define EMB_INT_PORT1 (EMB_INTEN_PORTININTEN1)
+#define EMB_INT_PORT2 (EMB_INTEN_PORTININTEN2)
+#define EMB_INT_PORT3 (EMB_INTEN_PORTININTEN3)
+#define EMB_INT_PORT4 (EMB_INTEN_PORTININTEN4)
+#define EMB_INT_PORT5 (EMB_INTEN_PORTININTEN5)
+#define EMB_INT_ALL (EMB_INT_PWMS | EMB_INT_CMP | EMB_INT_SYS | EMB_INT_PORT1 | \
+ EMB_INT_PORT2 | EMB_INT_PORT3 | EMB_INT_PORT4 | EMB_INT_PORT5)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EMB_Release_TMR_PWM_Condition EMB Release TMR PWM Condition
+ * @{
+ */
+#define EMB_RELEASE_PWM_COND_FLAG_ZERO (0UL)
+#define EMB_RELEASE_PWM_COND_STAT_ZERO (1UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EMB_Monitor_Event EMB Monitor Event
+ * @{
+ */
+#define EMB_EVT_PWMS (EMB_RLSSEL_PWMRSEL)
+#define EMB_EVT_CMP (EMB_RLSSEL_CMPRSEL)
+#define EMB_EVT_SYS (EMB_RLSSEL_SYSRSEL)
+#define EMB_EVT_PORT1 (EMB_RLSSEL_PORTINRSEL1)
+#define EMB_EVT_PORT2 (EMB_RLSSEL_PORTINRSEL2)
+#define EMB_EVT_PORT3 (EMB_RLSSEL_PORTINRSEL3)
+#define EMB_EVT_PORT4 (EMB_RLSSEL_PORTINRSEL4)
+#define EMB_EVT_PORT5 (EMB_RLSSEL_PORTINRSEL5)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup EMB_Global_Functions
+ * @{
+ */
+int32_t EMB_TMR4_StructInit(stc_emb_tmr4_init_t *pstcEmbInit);
+int32_t EMB_TMR4_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr4_init_t *pstcEmbInit);
+
+int32_t EMB_TMR6_StructInit(stc_emb_tmr6_init_t *pstcEmbInit);
+int32_t EMB_TMR6_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr6_init_t *pstcEmbInit);
+
+void EMB_DeInit(CM_EMB_TypeDef *EMBx);
+void EMB_IntCmd(CM_EMB_TypeDef *EMBx, uint32_t u32IntType, en_functional_state_t enNewState);
+void EMB_ClearStatus(CM_EMB_TypeDef *EMBx, uint32_t u32Flag);
+en_flag_status_t EMB_GetStatus(const CM_EMB_TypeDef *EMBx, uint32_t u32Flag);
+void EMB_SWBrake(CM_EMB_TypeDef *EMBx, en_functional_state_t enNewState);
+
+void EMB_SetReleasePwmCond(CM_EMB_TypeDef *EMBx, uint32_t u32Event, uint32_t u32Cond);
+
+/**
+ * @}
+ */
+
+#endif /* LL_EMB_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_EMB_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_event_port.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_event_port.h
new file mode 100644
index 0000000000..0bbe194da8
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_event_port.h
@@ -0,0 +1,231 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_event_port.h
+ * @brief This file contains all the functions prototypes of the Event Port
+ * driver library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_EVENT_PORT_H__
+#define __HC32_LL_EVENT_PORT_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_EVENT_PORT
+ * @{
+ */
+
+#if (LL_EVENT_PORT_ENABLE == DDL_ON)
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup EP_Global_Types Event Port Global Types
+ * @{
+ */
+
+/**
+ * @brief Event Pin Set and Reset enumeration
+ */
+typedef enum {
+ EVT_PIN_RESET = 0U, /*!< Pin reset */
+ EVT_PIN_SET = 1U /*!< Pin set */
+} en_ep_state_t;
+
+typedef struct {
+ uint32_t u32PinDir; /*!< Input/Output setting, @ref EP_PinDirection_Sel for details */
+ en_ep_state_t enPinState; /*!< Corresponding pin initial state, @ref en_ep_state_t for details */
+ uint32_t u32PinTriggerOps; /*!< Corresponding pin state after triggered, @ref EP_TriggerOps_Sel for details */
+ uint32_t u32Edge; /*!< Event port trigger edge, @ref EP_Trigger_Sel for details */
+ uint32_t u32Filter; /*!< Filter clock function setting, @ref EP_FilterClock_Sel for details */
+ uint32_t u32FilterClock; /*!< Filter clock, ref@ EP_FilterClock_Div for details */
+} stc_ep_init_t;
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup EP_Global_Macros Event Port Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup EP_Port_source EP Port Source
+ * @{
+ */
+#define EVT_PORT_1 (0U) /*!< Event port 1 */
+#define EVT_PORT_2 (1U) /*!< Event port 2 */
+#define EVT_PORT_3 (2U) /*!< Event port 3 */
+#define EVT_PORT_4 (3U) /*!< Event port 4 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EP_pins_define EP Pin Source
+ * @{
+ */
+#define EVT_PIN_00 (0x0001U) /*!< Event port Pin 00 */
+#define EVT_PIN_01 (0x0002U) /*!< Event port Pin 01 */
+#define EVT_PIN_02 (0x0004U) /*!< Event port Pin 02 */
+#define EVT_PIN_03 (0x0008U) /*!< Event port Pin 03 */
+#define EVT_PIN_04 (0x0010U) /*!< Event port Pin 04 */
+#define EVT_PIN_05 (0x0020U) /*!< Event port Pin 05 */
+#define EVT_PIN_06 (0x0040U) /*!< Event port Pin 06 */
+#define EVT_PIN_07 (0x0080U) /*!< Event port Pin 07 */
+#define EVT_PIN_08 (0x0100U) /*!< Event port Pin 08 */
+#define EVT_PIN_09 (0x0200U) /*!< Event port Pin 09 */
+#define EVT_PIN_10 (0x0400U) /*!< Event port Pin 10 */
+#define EVT_PIN_11 (0x0800U) /*!< Event port Pin 11 */
+#define EVT_PIN_12 (0x1000U) /*!< Event port Pin 12 */
+#define EVT_PIN_13 (0x2000U) /*!< Event port Pin 13 */
+#define EVT_PIN_14 (0x4000U) /*!< Event port Pin 14 */
+#define EVT_PIN_15 (0x8000U) /*!< Event port Pin 15 */
+#define EVT_PIN_All (0xFFFFU) /*!< All event pins are selected */
+#define EVT_PIN_MASK (0xFFFFU) /*!< Event pin mask for assert test */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EP_PinDirection_Sel EP Pin Input/Output Direction Selection
+ * @{
+ */
+#define EP_DIR_IN (0UL) /*!< EP input */
+#define EP_DIR_OUT (1UL) /*!< EP output */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EP_FilterClock_Sel Event Port Filter Function Selection
+ * @{
+ */
+#define EP_FILTER_OFF (0UL) /*!< EP filter function OFF */
+
+#define EP_FILTER_ON (1UL) /*!< EP filter function ON */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EP_FilterClock_Div Event Port Filter Sampling Clock Division Selection
+ * @{
+ */
+#define EP_FCLK_DIV1 (0UL) /*!< PCLK as EP filter clock source */
+#define EP_FCLK_DIV8 (1UL << AOS_PEVNTNFCR_DIVS1_POS) /*!< PCLK div8 as EP filter clock source */
+#define EP_FCLK_DIV32 (2UL << AOS_PEVNTNFCR_DIVS1_POS) /*!< PCLK div32 as EP filter clock source */
+#define EP_FCLK_DIV64 (3UL << AOS_PEVNTNFCR_DIVS1_POS) /*!< PCLK div64 as EP filter clock source */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EP_Trigger_Sel Event Port Trigger Edge Selection
+ * @{
+ */
+#define EP_TRIG_NONE (0UL) /*!< No Trigger by edge */
+#define EP_TRIG_FALLING (1UL) /*!< Trigger by falling edge */
+#define EP_TRIG_RISING (2UL) /*!< Trigger by rising edge */
+#define EP_TRIG_BOTH (3UL) /*!< Trigger by falling and rising edge */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EP_TriggerOps_Sel Event Port Operation
+ * @{
+ */
+#define EP_OPS_NONE (0UL) /*!< Pin no action after triggered */
+#define EP_OPS_LOW (1UL) /*!< Pin ouput low after triggered */
+#define EP_OPS_HIGH (2UL) /*!< Pin ouput high after triggered */
+#define EP_OPS_TOGGLE (3UL) /*!< Pin toggle after triggered */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup EP_Global_Functions
+ * @{
+ */
+void EP_DeInit(void);
+int32_t EP_StructInit(stc_ep_init_t *pstcEventPortInit);
+
+int32_t EP_Init(uint8_t u8EventPort, uint16_t u16EventPin, const stc_ep_init_t *pstcEventPortInit);
+int32_t EP_SetTriggerEdge(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Edge);
+int32_t EP_SetTriggerOps(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Ops);
+en_ep_state_t EP_ReadInputPins(uint8_t u8EventPort, uint16_t u16EventPin);
+uint16_t EP_ReadInputPort(uint8_t u8EventPort);
+en_ep_state_t EP_ReadOutputPins(uint8_t u8EventPort, uint16_t u16EventPin);
+uint16_t EP_ReadOutputPort(uint8_t u8EventPort);
+void EP_SetPins(uint8_t u8EventPort, uint16_t u16EventPin);
+void EP_ResetPins(uint8_t u8EventPort, uint16_t u16EventPin);
+void EP_SetDir(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Dir);
+
+/**
+ * @}
+ */
+
+#endif /* LL_EVENT_PORT_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_EVENT_PORT_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_fcg.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_fcg.h
new file mode 100644
index 0000000000..bdcfd9ff26
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_fcg.h
@@ -0,0 +1,225 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_fcg.h
+ * @brief This file contains all the functions prototypes of the FCG driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_FCG_H__
+#define __HC32_LL_FCG_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_FCG
+ * @{
+ */
+
+#if (LL_FCG_ENABLE == DDL_ON)
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup FCG_Global_Macros FCG Global Macros
+ * @{
+ */
+/**
+ * @defgroup FCG_FCG0_Peripheral FCG FCG0 peripheral
+ * @{
+ */
+#define FCG0_PERIPH_SRAMH (PWC_FCG0_SRAMH)
+#define FCG0_PERIPH_SRAM0 (PWC_FCG0_SRAM0)
+#define FCG0_PERIPH_SRAMRET (PWC_FCG0_SRAMRET)
+#define FCG0_PERIPH_PLA (PWC_FCG0_PLA)
+#define FCG0_PERIPH_KEY (PWC_FCG0_KEY)
+#define FCG0_PERIPH_DMA1 (PWC_FCG0_DMA1)
+#define FCG0_PERIPH_DMA2 (PWC_FCG0_DMA2)
+#define FCG0_PERIPH_FCM (PWC_FCG0_FCM)
+#define FCG0_PERIPH_AOS (PWC_FCG0_AOS)
+#define FCG0_PERIPH_CTC (PWC_FCG0_CTC)
+#define FCG0_PERIPH_MAU (PWC_FCG0_MAU)
+#define FCG0_PERIPH_AES (PWC_FCG0_AES)
+#define FCG0_PERIPH_HASH (PWC_FCG0_HASH)
+#define FCG0_PERIPH_TRNG (PWC_FCG0_TRNG)
+#define FCG0_PERIPH_CRC (PWC_FCG0_CRC)
+#define FCG0_PERIPH_DCU1 (PWC_FCG0_DCU1)
+#define FCG0_PERIPH_DCU2 (PWC_FCG0_DCU2)
+#define FCG0_PERIPH_DCU3 (PWC_FCG0_DCU3)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup FCG_FCG1_Peripheral FCG FCG1 peripheral
+ * @{
+ */
+#define FCG1_PERIPH_CAN1 (PWC_FCG1_CAN1)
+#define FCG1_PERIPH_CAN2 (PWC_FCG1_CAN2)
+#define FCG1_PERIPH_CAN3 (PWC_FCG1_CAN3)
+#define FCG1_PERIPH_QSPI (PWC_FCG1_QSPI)
+#define FCG1_PERIPH_I2C1 (PWC_FCG1_I2C1)
+#define FCG1_PERIPH_I2C2 (PWC_FCG1_I2C2)
+#define FCG1_PERIPH_I2C3 (PWC_FCG1_I2C3)
+#define FCG1_PERIPH_MDIO (PWC_FCG1_MDIO)
+#define FCG1_PERIPH_SPI1 (PWC_FCG1_SPI1)
+#define FCG1_PERIPH_SPI2 (PWC_FCG1_SPI2)
+#define FCG1_PERIPH_SPI3 (PWC_FCG1_SPI3)
+#define FCG1_PERIPH_SPI4 (PWC_FCG1_SPI4)
+#define FCG1_PERIPH_USBFS (PWC_FCG1_USBFS)
+#define FCG1_PERIPH_FMAC1 (PWC_FCG1_FMAC1)
+#define FCG1_PERIPH_FMAC2 (PWC_FCG1_FMAC2)
+#define FCG1_PERIPH_FMAC3 (PWC_FCG1_FMAC3)
+#define FCG1_PERIPH_FMAC4 (PWC_FCG1_FMAC4)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup FCG_FCG2_Peripheral FCG FCG2 peripheral
+ * @{
+ */
+#define FCG2_PERIPH_TMR6_1 (PWC_FCG2_TMR6_1)
+#define FCG2_PERIPH_TMR6_2 (PWC_FCG2_TMR6_2)
+#define FCG2_PERIPH_TMR6_3 (PWC_FCG2_TMR6_3)
+#define FCG2_PERIPH_TMR6_4 (PWC_FCG2_TMR6_4)
+#define FCG2_PERIPH_TMR6_5 (PWC_FCG2_TMR6_5)
+#define FCG2_PERIPH_TMR6_6 (PWC_FCG2_TMR6_6)
+#define FCG2_PERIPH_TMR6_7 (PWC_FCG2_TMR6_7)
+#define FCG2_PERIPH_TMR6_8 (PWC_FCG2_TMR6_8)
+#define FCG2_PERIPH_TMR6_9 (PWC_FCG2_TMR6_9)
+#define FCG2_PERIPH_TMR6_10 (PWC_FCG2_TMR6_10)
+#define FCG2_PERIPH_TMR4 (PWC_FCG2_TMR4)
+#define FCG2_PERIPH_TMR0_1 (PWC_FCG2_TMR0_1)
+#define FCG2_PERIPH_TMR0_2 (PWC_FCG2_TMR0_2)
+#define FCG2_PERIPH_EMB (PWC_FCG2_EMB)
+#define FCG2_PERIPH_TMR2_1 (PWC_FCG2_TMR2_1)
+#define FCG2_PERIPH_TMR2_2 (PWC_FCG2_TMR2_2)
+#define FCG2_PERIPH_TMR2_3 (PWC_FCG2_TMR2_3)
+#define FCG2_PERIPH_TMR2_4 (PWC_FCG2_TMR2_4)
+#define FCG2_PERIPH_TMRA_1 (PWC_FCG2_TMRA_1)
+#define FCG2_PERIPH_TMRA_2 (PWC_FCG2_TMRA_2)
+#define FCG2_PERIPH_TMRA_3 (PWC_FCG2_TMRA_3)
+#define FCG2_PERIPH_TMRA_4 (PWC_FCG2_TMRA_4)
+#define FCG2_PERIPH_TMRA_5 (PWC_FCG2_TMRA_5)
+#define FCG2_PERIPH_TMRA_6 (PWC_FCG2_TMRA_6)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup FCG_FCG3_Peripheral FCG FCG3 peripheral
+ * @{
+ */
+#define FCG3_PERIPH_ADC1 (PWC_FCG3_ADC1)
+#define FCG3_PERIPH_ADC2 (PWC_FCG3_ADC2)
+#define FCG3_PERIPH_ADC3 (PWC_FCG3_ADC3)
+#define FCG3_PERIPH_CMBIAS (PWC_FCG3_CMBIAS)
+#define FCG3_PERIPH_DAC1 (PWC_FCG3_DAC1)
+#define FCG3_PERIPH_DAC2 (PWC_FCG3_DAC2)
+#define FCG3_PERIPH_DAC3 (PWC_FCG3_DAC3)
+#define FCG3_PERIPH_DAC4 (PWC_FCG3_DAC4)
+#define FCG3_PERIPH_CMP1_2 (PWC_FCG3_CMP12)
+#define FCG3_PERIPH_CMP3_4 (PWC_FCG3_CMP34)
+#define FCG3_PERIPH_OTS (PWC_FCG3_OTS)
+#define FCG3_PERIPH_VREF (PWC_FCG3_VREF)
+#define FCG3_PERIPH_SMC (PWC_FCG3_SMC)
+#define FCG3_PERIPH_USART1 (PWC_FCG3_USART1)
+#define FCG3_PERIPH_USART2 (PWC_FCG3_USART2)
+#define FCG3_PERIPH_USART3 (PWC_FCG3_USART3)
+#define FCG3_PERIPH_USART4 (PWC_FCG3_USART4)
+#define FCG3_PERIPH_USART5 (PWC_FCG3_USART5)
+#define FCG3_PERIPH_USART6 (PWC_FCG3_USART6)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup FCG_FCGx_Peripheral_Mask FCG FCGx Peripheral Mask
+ * @{
+ */
+#define FCG_FCG0_PERIPH_MASK (0x07FFEC11UL)
+#define FCG_FCG1_PERIPH_MASK (0x0F4F017FUL)
+#define FCG_FCG2_PERIPH_MASK (0x03FFBFFFUL)
+#define FCG_FCG3_PERIPH_MASK (0x03F133FFUL)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup FCG_Global_Functions
+ * @{
+ */
+
+void FCG_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState);
+
+void FCG_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState);
+void FCG_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState);
+void FCG_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState);
+
+/**
+ * @}
+ */
+
+#endif /* LL_FCG_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_FCG_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_fcm.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_fcm.h
new file mode 100644
index 0000000000..c8bd5b95b3
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_fcm.h
@@ -0,0 +1,291 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_fcm.h
+ * @brief This file contains all the functions prototypes of the FCM driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Modify API FCM_DeInit()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_FCM_H__
+#define __HC32_LL_FCM_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_FCM
+ * @{
+ */
+
+#if (LL_FCM_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup FCM_Global_Types FCM Global Types
+ * @{
+ */
+/**
+ * @brief FCM Init structure definition
+ */
+typedef struct {
+ uint16_t u16LowerLimit; /*!< FCM lower limit value */
+ uint16_t u16UpperLimit; /*!< FCM upper limit value */
+ uint32_t u32TargetClock; /*!< FCM target clock source selection, @ref FCM_Target_Clock_Src */
+ uint32_t u32TargetClockDiv; /*!< FCM target clock source division selection, @ref FCM_Target_Clock_Div */
+ uint32_t u32ExtRefClockEnable; /*!< FCM external reference clock function config, @ref FCM_Ext_Ref_Clock_Config */
+ uint32_t u32RefClockEdge; /*!< FCM reference clock trigger edge selection, @ref FCM_Ref_Clock_Edge */
+ uint32_t u32DigitalFilter; /*!< FCM digital filter function config, @ref FCM_Digital_Filter_Config */
+ uint32_t u32RefClock; /*!< FCM reference clock source selection, @ref FCM_Ref_Clock_Src */
+ uint32_t u32RefClockDiv; /*!< FCM reference clock source division selection, @ref FCM_Ref_Clock_Div */
+ uint32_t u32ExceptionType; /*!< FCM exception type select, @ref FCM_Exception_Type */
+} stc_fcm_init_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup FCM_Global_Macros FCM Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup FCM_Target_Clock_Src FCM Target Clock Source
+ * @{
+ */
+#define FCM_TARGET_CLK_XTAL (0x00UL << FCM_MCCR_MCKS_POS)
+#define FCM_TARGET_CLK_XTAL32 (0x01UL << FCM_MCCR_MCKS_POS)
+#define FCM_TARGET_CLK_HRC (0x02UL << FCM_MCCR_MCKS_POS)
+#define FCM_TARGET_CLK_LRC (0x03UL << FCM_MCCR_MCKS_POS)
+#define FCM_TARGET_CLK_SWDTLRC (0x04UL << FCM_MCCR_MCKS_POS)
+#define FCM_TARGET_CLK_PCLK1 (0x05UL << FCM_MCCR_MCKS_POS)
+#define FCM_TARGET_CLK_MRC (0x07UL << FCM_MCCR_MCKS_POS)
+#define FCM_TARGET_CLK_PLLHP (0x08UL << FCM_MCCR_MCKS_POS)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup FCM_Target_Clock_Div FCM Target Clock Division
+ * @{
+ */
+#define FCM_TARGET_CLK_DIV1 (0x00UL << FCM_MCCR_MDIVS_POS)
+#define FCM_TARGET_CLK_DIV4 (0x01UL << FCM_MCCR_MDIVS_POS)
+#define FCM_TARGET_CLK_DIV8 (0x02UL << FCM_MCCR_MDIVS_POS)
+#define FCM_TARGET_CLK_DIV32 (0x03UL << FCM_MCCR_MDIVS_POS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup FCM_Ext_Ref_Clock_Config FCM External Reference Clock Config
+ * @{
+ */
+#define FCM_EXT_REF_OFF (0x00UL)
+#define FCM_EXT_REF_ON (FCM_RCCR_EXREFE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup FCM_Ref_Clock_Edge FCM Reference Clock Edge
+ * @{
+ */
+#define FCM_REF_CLK_RISING (0x00UL)
+#define FCM_REF_CLK_FALLING (FCM_RCCR_EDGES_0)
+#define FCM_REF_CLK_BOTH (FCM_RCCR_EDGES_1)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup FCM_Digital_Filter_Config FCM Digital Filter Config
+ * @{
+ */
+#define FCM_DIG_FILTER_OFF (0x00UL)
+#define FCM_DIG_FILTER_DIV1 (FCM_RCCR_DNFS_0)
+#define FCM_DIG_FILTER_DIV4 (FCM_RCCR_DNFS_1)
+#define FCM_DIG_FILTER_DIV16 (FCM_RCCR_DNFS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup FCM_Ref_Clock_Src FCM Reference Clock Source
+ * @{
+ */
+#define FCM_REF_CLK_EXTCLK (0x00UL << FCM_RCCR_RCKS_POS)
+#define FCM_REF_CLK_XTAL (0x10UL << FCM_RCCR_RCKS_POS)
+#define FCM_REF_CLK_XTAL32 (0x11UL << FCM_RCCR_RCKS_POS)
+#define FCM_REF_CLK_HRC (0x12UL << FCM_RCCR_RCKS_POS)
+#define FCM_REF_CLK_LRC (0x13UL << FCM_RCCR_RCKS_POS)
+#define FCM_REF_CLK_SWDTLRC (0x14UL << FCM_RCCR_RCKS_POS)
+#define FCM_REF_CLK_PCLK1 (0x15UL << FCM_RCCR_RCKS_POS)
+#define FCM_REF_CLK_MRC (0x17UL << FCM_RCCR_RCKS_POS)
+#define FCM_REF_CLK_PLLHP (0x18UL << FCM_RCCR_RCKS_POS)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup FCM_Ref_Clock_Div FCM Reference Clock Division
+ * @{
+ */
+#define FCM_REF_CLK_DIV32 (0x00UL << FCM_RCCR_RDIVS_POS)
+#define FCM_REF_CLK_DIV128 (0x01UL << FCM_RCCR_RDIVS_POS)
+#define FCM_REF_CLK_DIV1024 (0x02UL << FCM_RCCR_RDIVS_POS)
+#define FCM_REF_CLK_DIV8192 (0x03UL << FCM_RCCR_RDIVS_POS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup FCM_Abnormal_Reset_Func FCM Abnormal Reset Function Config
+ * @{
+ */
+#define FCM_ERR_RST_OFF (0x00UL)
+#define FCM_ERR_RST_ON (FCM_RIER_ERRE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup FCM_Exception_Type FCM Exception Type
+ * @{
+ */
+#define FCM_EXP_TYPE_INT (0x00UL)
+#define FCM_EXP_TYPE_RST (FCM_RIER_ERRINTRS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup FCM_Int_Type FCM Interrupt Type
+ * @{
+ */
+#define FCM_INT_OVF (FCM_RIER_OVFIE)
+#define FCM_INT_END (FCM_RIER_MENDIE)
+#define FCM_INT_ERR (FCM_RIER_ERRIE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup FCM_Flag_Sel FCM Status Flag Selection
+ * @{
+ */
+#define FCM_FLAG_ERR (FCM_SR_ERRF)
+#define FCM_FLAG_END (FCM_SR_MENDF)
+#define FCM_FLAG_OVF (FCM_SR_OVF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup FCM_Global_Functions
+ * @{
+ */
+
+/**
+ * @brief Set FCM upper limit value.
+ * @param u16Limit
+ * @retval None.
+ */
+__STATIC_INLINE void FCM_SetUpperLimit(uint16_t u16Limit)
+{
+ WRITE_REG32(CM_FCM->UVR, u16Limit);
+}
+
+/**
+ * @brief Set FCM lower limit value.
+ * @param u16Limit
+ * @retval None
+ */
+__STATIC_INLINE void FCM_SetLowerLimit(uint16_t u16Limit)
+{
+ WRITE_REG32(CM_FCM->LVR, u16Limit);
+}
+
+int32_t FCM_Init(const stc_fcm_init_t *pstcFcmInit);
+int32_t FCM_StructInit(stc_fcm_init_t *pstcFcmInit);
+int32_t FCM_DeInit(void);
+uint16_t FCM_GetCountValue(void);
+void FCM_SetUpperLimit(uint16_t u16Limit);
+void FCM_SetLowerLimit(uint16_t u16Limit);
+void FCM_SetTargetClock(uint32_t u32ClockSrc, uint32_t u32Div);
+void FCM_SetRefClock(uint32_t u32ClockSrc, uint32_t u32Div);
+en_flag_status_t FCM_GetStatus(uint32_t u32Flag);
+void FCM_ClearStatus(uint32_t u32Flag);
+void FCM_ResetCmd(en_functional_state_t enNewState);
+void FCM_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState);
+void FCM_Cmd(en_functional_state_t enNewState);
+
+/**
+ * @}
+ */
+
+#endif /* LL_FCM_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_FCM_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_fmac.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_fmac.h
new file mode 100644
index 0000000000..d5209adb9d
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_fmac.h
@@ -0,0 +1,203 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_fmac.h
+ * @brief This file contains all the functions prototypes of the FMAC driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_FMAC_H__
+#define __HC32_LL_FMAC_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_FMAC
+ * @{
+ */
+
+#if (LL_FMAC_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup FMAC_Global_Types FMAC Global Types
+ * @{
+ */
+
+/**
+ * @brief FMAC configuration structure
+ */
+typedef struct {
+ uint32_t u32Stage; /*!< FMAC filter stage number config.
+ This parameter can be a value of @ref FMAC_Filter_Stage.*/
+ uint32_t u32Shift; /*!< FMAC filter result right shift bits.
+ This parameter can be a value of @ref FMAC_Filter_Shift.*/
+ int16_t *pi16Factor; /*!< FMAC filter factor config. FIR factor array */
+ uint32_t u32IntCmd; /*!< Enable or disable FMAC interrupt.
+ This parameter can be a value of @ref FMAC_Interrupt_Selection.*/
+} stc_fmac_init_t;
+
+/**
+ * @brief FMAC result definition
+ */
+typedef struct {
+ uint32_t u32ResultHigh; /*!< The high value of the result. */
+ uint32_t u32ResultLow; /*!< The low value of the result. */
+} stc_fmac_result_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/**
+ * @defgroup FMAC_Global_Macros FMAC Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup FMAC_Interrupt_Selection FMAC Interrupt Selection
+ * @{
+ */
+#define FMAC_INT_ENABLE (FMAC_IER_INTEN)
+#define FMAC_INT_DISABLE (0x0UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup FMAC_Filter_Shift FMAC Filter Shift
+ * @{
+ */
+#define FMAC_FIR_SHIFT_0BIT (0U)
+#define FMAC_FIR_SHIFT_1BIT (1U)
+#define FMAC_FIR_SHIFT_2BIT (2U)
+#define FMAC_FIR_SHIFT_3BIT (3U)
+#define FMAC_FIR_SHIFT_4BIT (4U)
+#define FMAC_FIR_SHIFT_5BIT (5U)
+#define FMAC_FIR_SHIFT_6BIT (6U)
+#define FMAC_FIR_SHIFT_7BIT (7U)
+#define FMAC_FIR_SHIFT_8BIT (8U)
+#define FMAC_FIR_SHIFT_9BIT (9U)
+#define FMAC_FIR_SHIFT_10BIT (10U)
+#define FMAC_FIR_SHIFT_11BIT (11U)
+#define FMAC_FIR_SHIFT_12BIT (12U)
+#define FMAC_FIR_SHIFT_13BIT (13U)
+#define FMAC_FIR_SHIFT_14BIT (14U)
+#define FMAC_FIR_SHIFT_15BIT (15U)
+#define FMAC_FIR_SHIFT_16BIT (16U)
+#define FMAC_FIR_SHIFT_17BIT (17U)
+#define FMAC_FIR_SHIFT_18BIT (18U)
+#define FMAC_FIR_SHIFT_19BIT (19U)
+#define FMAC_FIR_SHIFT_20BIT (20U)
+#define FMAC_FIR_SHIFT_21BIT (21U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup FMAC_Filter_Stage FMAC Filter Stage
+ * @{
+ */
+#define FMAC_FIR_STAGE_0 (0U)
+#define FMAC_FIR_STAGE_1 (1U)
+#define FMAC_FIR_STAGE_2 (2U)
+#define FMAC_FIR_STAGE_3 (3U)
+#define FMAC_FIR_STAGE_4 (4U)
+#define FMAC_FIR_STAGE_5 (5U)
+#define FMAC_FIR_STAGE_6 (6U)
+#define FMAC_FIR_STAGE_7 (7U)
+#define FMAC_FIR_STAGE_8 (8U)
+#define FMAC_FIR_STAGE_9 (9U)
+#define FMAC_FIR_STAGE_10 (10U)
+#define FMAC_FIR_STAGE_11 (11U)
+#define FMAC_FIR_STAGE_12 (12U)
+#define FMAC_FIR_STAGE_13 (13U)
+#define FMAC_FIR_STAGE_14 (14U)
+#define FMAC_FIR_STAGE_15 (15U)
+#define FMAC_FIR_STAGE_16 (16U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup FMAC_Global_Functions
+ * @{
+ */
+int32_t FMAC_StructInit(stc_fmac_init_t *pstcFmacInit);
+int32_t FMAC_DeInit(CM_FMAC_TypeDef *FMACx);
+int32_t FMAC_Init(CM_FMAC_TypeDef *FMACx, const stc_fmac_init_t *pstcFmacInit);
+void FMAC_Cmd(CM_FMAC_TypeDef *FMACx, en_functional_state_t enNewState);
+void FMAC_SetResultShift(CM_FMAC_TypeDef *FMACx, uint32_t u32ShiftNum);
+void FMAC_SetStageFactor(CM_FMAC_TypeDef *FMACx, uint32_t u32FilterStage, int16_t *pi16Factor);
+void FMAC_IntCmd(CM_FMAC_TypeDef *FMACx, en_functional_state_t enNewState);
+void FMAC_FIRInput(CM_FMAC_TypeDef *FMACx, int16_t i16Factor);
+en_flag_status_t FMAC_GetStatus(const CM_FMAC_TypeDef *FMACx);
+int32_t FMAC_GetResult(const CM_FMAC_TypeDef *FMACx, stc_fmac_result_t *pstcResult);
+/**
+ * @}
+ */
+
+#endif /* LL_FMAC_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_FMAC_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_gpio.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_gpio.h
new file mode 100644
index 0000000000..4d09d9bac1
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_gpio.h
@@ -0,0 +1,469 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_gpio.h
+ * @brief This file contains all the functions prototypes of the GPIO driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Rename GPIO_ExIntCmd() as GPIO_ExtIntCmd
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_GPIO_H__
+#define __HC32_LL_GPIO_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_GPIO
+ * @{
+ */
+
+#if (LL_GPIO_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup GPIO_Global_Types GPIO Global Types
+ * @{
+ */
+
+/**
+ * @brief GPIO Pin Set and Reset enumeration
+ */
+typedef enum {
+ PIN_RESET = 0U, /*!< Pin reset */
+ PIN_SET = 1U /*!< Pin set */
+} en_pin_state_t;
+
+/**
+ * @brief GPIO Init structure definition
+ */
+typedef struct {
+ uint16_t u16PinState; /*!< Set pin state to High or Low, @ref GPIO_PinState_Sel for details */
+ uint16_t u16PinDir; /*!< Pin mode setting, @ref GPIO_PinDirection_Sel for details */
+ uint16_t u16PinOutputType; /*!< Output type setting, @ref GPIO_PinOutType_Sel for details */
+ uint16_t u16PinDrv; /*!< Pin drive capacity setting, @ref GPIO_PinDrv_Sel for details */
+ uint16_t u16Latch; /*!< Pin latch setting, @ref GPIO_PinLatch_Sel for details */
+ uint16_t u16PullUp; /*!< Internal pull-up resistor setting, @ref GPIO_PinPU_Sel for details */
+ uint16_t u16PullDown; /*!< Internal pull-down register setting, @ref GPIO_PinPD_Sel for details */
+ uint16_t u16InputMos; /*!< Input MOS always on selection, @ref GPIO_PinInputMOS_Sel for details */
+ uint16_t u16Invert; /*!< Pin input/output invert setting, @ref GPIO_PinInvert_Sel for details */
+ uint16_t u16ExtInt; /*!< External interrupt pin setting, @ref GPIO_PinExtInt_Sel for details */
+ uint16_t u16PinInputType; /*!< Input type setting, @ref GPIO_PinInType_Sel for details */
+ uint16_t u16PinAttr; /*!< Digital or analog attribute setting, @ref GPIO_PinMode_Sel for details */
+} stc_gpio_init_t;
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup GPIO_Global_Macros GPIO Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup GPIO_Pins_Define GPIO Pin Source
+ * @{
+ */
+#define GPIO_PIN_00 (0x0001U) /*!< Pin 00 selected */
+#define GPIO_PIN_01 (0x0002U) /*!< Pin 01 selected */
+#define GPIO_PIN_02 (0x0004U) /*!< Pin 02 selected */
+#define GPIO_PIN_03 (0x0008U) /*!< Pin 03 selected */
+#define GPIO_PIN_04 (0x0010U) /*!< Pin 04 selected */
+#define GPIO_PIN_05 (0x0020U) /*!< Pin 05 selected */
+#define GPIO_PIN_06 (0x0040U) /*!< Pin 06 selected */
+#define GPIO_PIN_07 (0x0080U) /*!< Pin 07 selected */
+#define GPIO_PIN_08 (0x0100U) /*!< Pin 08 selected */
+#define GPIO_PIN_09 (0x0200U) /*!< Pin 09 selected */
+#define GPIO_PIN_10 (0x0400U) /*!< Pin 10 selected */
+#define GPIO_PIN_11 (0x0800U) /*!< Pin 11 selected */
+#define GPIO_PIN_12 (0x1000U) /*!< Pin 12 selected */
+#define GPIO_PIN_13 (0x2000U) /*!< Pin 13 selected */
+#define GPIO_PIN_14 (0x4000U) /*!< Pin 14 selected */
+#define GPIO_PIN_15 (0x8000U) /*!< Pin 15 selected */
+#define GPIO_PIN_ALL (0xFFFFU) /*!< All pins selected */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup GPIO_All_Pins_Define GPIO All Pin Definition for Each Product
+ * @{
+ */
+#define GPIO_PIN_A_ALL (0xFFFFU) /*!< Pin A all*/
+#define GPIO_PIN_B_ALL (0xFFFFU) /*!< Pin B all*/
+#define GPIO_PIN_C_ALL (0xFFFFU) /*!< Pin C all*/
+#define GPIO_PIN_D_ALL (0xFFFFU) /*!< Pin D all*/
+#define GPIO_PIN_E_ALL (0xFFFFU) /*!< Pin E all*/
+#define GPIO_PIN_F_ALL (0x010FU) /*!< Pin F all*/
+/**
+ * @}
+ */
+
+/**
+ * @defgroup GPIO_Port_Source GPIO Port Source
+ * @{
+ */
+#define GPIO_PORT_A (0x00U) /*!< Port A selected */
+#define GPIO_PORT_B (0x01U) /*!< Port B selected */
+#define GPIO_PORT_C (0x02U) /*!< Port C selected */
+#define GPIO_PORT_D (0x03U) /*!< Port D selected */
+#define GPIO_PORT_E (0x04U) /*!< Port E selected */
+#define GPIO_PORT_F (0x05U) /*!< Port F selected */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup GPIO_Function_Sel GPIO Function Selection
+ * @{
+ */
+#define GPIO_FUNC_0 (0U)
+#define GPIO_FUNC_1 (1U)
+#define GPIO_FUNC_2 (2U)
+#define GPIO_FUNC_3 (3U)
+#define GPIO_FUNC_4 (4U)
+#define GPIO_FUNC_5 (5U)
+#define GPIO_FUNC_6 (6U)
+#define GPIO_FUNC_7 (7U)
+#define GPIO_FUNC_8 (8U)
+#define GPIO_FUNC_9 (9U)
+#define GPIO_FUNC_10 (10U)
+#define GPIO_FUNC_11 (11U)
+#define GPIO_FUNC_12 (12U)
+#define GPIO_FUNC_13 (13U)
+#define GPIO_FUNC_14 (14U)
+#define GPIO_FUNC_15 (15U)
+#define GPIO_FUNC_16 (16U)
+#define GPIO_FUNC_17 (17U)
+#define GPIO_FUNC_18 (18U)
+#define GPIO_FUNC_19 (19U)
+#define GPIO_FUNC_20 (20U)
+#define GPIO_FUNC_21 (21U)
+#define GPIO_FUNC_22 (22U)
+#define GPIO_FUNC_23 (23U)
+#define GPIO_FUNC_24 (24U)
+#define GPIO_FUNC_25 (25U)
+#define GPIO_FUNC_26 (26U)
+#define GPIO_FUNC_32 (32U)
+#define GPIO_FUNC_33 (33U)
+#define GPIO_FUNC_34 (34U)
+#define GPIO_FUNC_35 (35U)
+#define GPIO_FUNC_36 (36U)
+#define GPIO_FUNC_37 (37U)
+#define GPIO_FUNC_38 (38U)
+#define GPIO_FUNC_39 (39U)
+#define GPIO_FUNC_40 (40U)
+#define GPIO_FUNC_41 (41U)
+#define GPIO_FUNC_42 (42U)
+#define GPIO_FUNC_43 (43U)
+#define GPIO_FUNC_44 (44U)
+#define GPIO_FUNC_45 (45U)
+#define GPIO_FUNC_46 (46U)
+#define GPIO_FUNC_47 (47U)
+#define GPIO_FUNC_48 (48U)
+#define GPIO_FUNC_49 (49U)
+#define GPIO_FUNC_50 (50U)
+#define GPIO_FUNC_51 (51U)
+#define GPIO_FUNC_52 (52U)
+#define GPIO_FUNC_53 (53U)
+#define GPIO_FUNC_54 (54U)
+#define GPIO_FUNC_55 (55U)
+#define GPIO_FUNC_56 (56U)
+#define GPIO_FUNC_57 (57U)
+#define GPIO_FUNC_58 (58U)
+#define GPIO_FUNC_59 (59U)
+#define GPIO_FUNC_60 (60U)
+#define GPIO_FUNC_61 (61U)
+#define GPIO_FUNC_62 (62U)
+#define GPIO_FUNC_63 (63U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup GPIO_DebugPin_Sel GPIO Debug Pin Selection
+ * @{
+ */
+#define GPIO_PIN_TCK (0x01U)
+#define GPIO_PIN_TMS (0x02U)
+#define GPIO_PIN_TDO (0x04U)
+#define GPIO_PIN_TDI (0x08U)
+#define GPIO_PIN_TRST (0x10U)
+#define GPIO_PIN_DEBUG_JTAG (0x1FU)
+#define GPIO_PIN_SWCLK (0x01U)
+#define GPIO_PIN_SWDIO (0x02U)
+#define GPIO_PIN_SWO (0x04U)
+#define GPIO_PIN_DEBUG_SWD (0x07U)
+#define GPIO_PIN_DEBUG (0x1FU)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup GPIO_ReadCycle_Sel GPIO Pin Read Wait Cycle Selection
+ * @{
+ */
+#define GPIO_RD_WAIT0 (0x00U << GPIO_PCCR_RDWT_POS)
+#define GPIO_RD_WAIT1 (0x01U << GPIO_PCCR_RDWT_POS)
+#define GPIO_RD_WAIT2 (0x02U << GPIO_PCCR_RDWT_POS)
+#define GPIO_RD_WAIT3 (0x03U << GPIO_PCCR_RDWT_POS)
+#define GPIO_RD_WAIT4 (0x04U << GPIO_PCCR_RDWT_POS)
+#define GPIO_RD_WAIT5 (0x05U << GPIO_PCCR_RDWT_POS)
+#define GPIO_RD_WAIT6 (0x06U << GPIO_PCCR_RDWT_POS)
+#define GPIO_RD_WAIT7 (0x07U << GPIO_PCCR_RDWT_POS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup GPIO_PinState_Sel GPIO Pin Output State Selection
+ * @{
+ */
+#define PIN_STAT_RST (0U)
+#define PIN_STAT_SET (GPIO_PCR_POUT)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup GPIO_PinDirection_Sel GPIO Pin Input/Output Direction Selection
+ * @{
+ */
+#define PIN_DIR_IN (0U)
+#define PIN_DIR_OUT (GPIO_PCR_POUTE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup GPIO_PinOutType_Sel GPIO Pin Output Type Selection
+ * @{
+ */
+#define PIN_OUT_TYPE_CMOS (0U)
+#define PIN_OUT_TYPE_NMOS (GPIO_PCR_NOD)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup GPIO_PinDrv_Sel GPIO Pin Drive Capacity Selection
+ * @{
+ */
+#define PIN_LOW_DRV (0U)
+#define PIN_MID_DRV (GPIO_PCR_DRV_0)
+#define PIN_HIGH_DRV (GPIO_PCR_DRV_1)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup GPIO_PinLatch_Sel GPIO Pin Output Latch Selection
+ * @{
+ */
+#define PIN_LATCH_OFF (0U)
+#define PIN_LATCH_ON (GPIO_PCR_LTE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup GPIO_PinPU_Sel GPIO Pin Internal Pull-Up Resistor Selection
+ * @{
+ */
+#define PIN_PU_OFF (0U)
+#define PIN_PU_ON (GPIO_PCR_PUU)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup GPIO_PinPD_Sel GPIO Pin Internal Pull-Down Resistor Selection
+ * @{
+ */
+#define PIN_PD_OFF (0U)
+#define PIN_PD_ON (GPIO_PCR_PUD)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup GPIO_PinInputMOS_Sel GPIO Pin Input MOS Always On selection
+ * @{
+ */
+#define PIN_IN_MOS_OFF (0U)
+#define PIN_IN_MOS_ON (GPIO_PCR_PINAE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup GPIO_PinInvert_Sel GPIO Pin I/O Invert Selection
+ * @{
+ */
+#define PIN_INVT_OFF (0U)
+#define PIN_INVT_ON (GPIO_PCR_INVE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup GPIO_PinInType_Sel GPIO Pin Input Type Selection
+ * @{
+ */
+#define PIN_IN_TYPE_SMT (0U)
+#define PIN_IN_TYPE_CMOS (GPIO_PCR_CINSEL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup GPIO_PinExtInt_Sel GPIO Pin External Interrupt Selection
+ * @{
+ */
+#define PIN_EXTINT_OFF (0U)
+#define PIN_EXTINT_ON (GPIO_PCR_INTE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup GPIO_PinMode_Sel GPIO Pin Mode Selection
+ * @{
+ */
+#define PIN_ATTR_DIGITAL (0U)
+#define PIN_ATTR_ANALOG (GPIO_PCR_DDIS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup GPIO_PinSubFuncSet_Sel GPIO Pin Sub-function Enable or Disable
+ * @{
+ */
+#define PIN_SUBFUNC_DISABLE (0U)
+#define PIN_SUBFUNC_ENABLE (GPIO_PFSR_BFE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup GPIO_Register_Protect_Key GPIO Registers Protect Key
+ * @{
+ */
+#define GPIO_REG_LOCK_KEY (0xA500U)
+#define GPIO_REG_UNLOCK_KEY (0xA501U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup GPIO_Global_Functions
+ * @{
+ */
+/**
+ * @brief GPIO lock. PSPCR, PCCR, PINAER, PCRxy, PFSRxy write disable
+ * @param None
+ * @retval None
+ */
+__STATIC_INLINE void GPIO_REG_Lock(void)
+{
+ WRITE_REG16(CM_GPIO->PWPR, GPIO_REG_LOCK_KEY);
+}
+
+/**
+ * @brief GPIO unlock. PSPCR, PCCR, PINAER, PCRxy, PFSRxy write enable
+ * @param None
+ * @retval None
+ */
+__STATIC_INLINE void GPIO_REG_Unlock(void)
+{
+ WRITE_REG16(CM_GPIO->PWPR, GPIO_REG_UNLOCK_KEY);
+}
+
+int32_t GPIO_Init(uint8_t u8Port, uint16_t u16Pin, const stc_gpio_init_t *pstcGpioInit);
+void GPIO_DeInit(void);
+int32_t GPIO_StructInit(stc_gpio_init_t *pstcGpioInit);
+void GPIO_SetDebugPort(uint8_t u8DebugPort, en_functional_state_t enNewState);
+void GPIO_SetFunc(uint8_t u8Port, uint16_t u16Pin, uint16_t u16Func);
+void GPIO_SubFuncCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState);
+void GPIO_SetSubFunc(uint8_t u8Func);
+void GPIO_SetReadWaitCycle(uint16_t u16ReadWait);
+void GPIO_InputMOSCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState);
+void GPIO_OutputCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState);
+en_pin_state_t GPIO_ReadInputPins(uint8_t u8Port, uint16_t u16Pin);
+uint16_t GPIO_ReadInputPort(uint8_t u8Port);
+en_pin_state_t GPIO_ReadOutputPins(uint8_t u8Port, uint16_t u16Pin);
+uint16_t GPIO_ReadOutputPort(uint8_t u8Port);
+void GPIO_SetPins(uint8_t u8Port, uint16_t u16Pin);
+void GPIO_ResetPins(uint8_t u8Port, uint16_t u16Pin);
+void GPIO_WritePort(uint8_t u8Port, uint16_t u16PortVal);
+void GPIO_TogglePins(uint8_t u8Port, uint16_t u16Pin);
+void GPIO_ExtIntCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState);
+void GPIO_AnalogCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState);
+/**
+ * @}
+ */
+
+#endif /* LL_GPIO_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_GPIO_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_hash.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_hash.h
new file mode 100644
index 0000000000..8fbfc2703f
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_hash.h
@@ -0,0 +1,216 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_hash.h
+ * @brief This file contains all the functions prototypes of the HASH driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Add HASH_DeInit function
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_HASH_H__
+#define __HC32_LL_HASH_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_HASH
+ * @{
+ */
+
+#if (LL_HASH_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup HASH_Global_Macros HASH Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup HASH_Mode HASH Mode
+ * @{
+ */
+#define HASH_MD_SHA256 (0x0UL) /*!< SHA256 operating mode */
+#define HASH_MD_HMAC (HASH_CR_MODE_0) /*!< HMAC operating mode */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup HASH_Key_Size_Mode HASH Key Size Mode
+ * @{
+ */
+#define HASH_KEY_MD_SHORT_SIZE (0x0UL) /*!< Key length <= 64 Bytes */
+#define HASH_KEY_MD_LONG_SIZE (HASH_CR_LKEY) /*!< Key length > 64 Bytes */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup HASH_Interrupt HASH Interrupt
+ * @{
+ */
+#define HASH_INT_GRP (HASH_CR_HEIE) /*!< A set of data operations complete interrupt */
+#define HASH_INT_ALL_CPLT (HASH_CR_HCIE) /*!< All data operations complete interrupt */
+#define HASH_INT_ALL (HASH_INT_GRP | HASH_INT_ALL_CPLT)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup HASH_Msg_Group HASH Messages Group
+ * @{
+ */
+#define HASH_MSG_GRP_FIRST (HASH_CR_FST_GRP) /*!< The first group of messages or keys */
+#define HASH_MSG_GRP_END (HASH_CR_KMSG_END) /*!< The last group of messages or keys */
+#define HASH_MSG_GRP_ONLY_ONE (HASH_CR_FST_GRP | \
+ HASH_CR_KMSG_END) /*!< Only one set of message or key */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup HASH_Status_Flag HASH Status Flag
+ * @{
+ */
+#define HASH_FLAG_START (HASH_CR_START) /*!< Operation in progress */
+#define HASH_FLAG_BUSY (HASH_CR_BUSY) /*!< HASH in operation */
+#define HASH_FLAG_CYC_END (HASH_CR_CYC_END) /*!< key or message operation completed */
+#define HASH_FLAG_HMAC_END (HASH_CR_HMAC_END) /*!< HMAC operation completed */
+#define HASH_FLAG_ALL (HASH_FLAG_START | HASH_FLAG_BUSY | \
+ HASH_FLAG_CYC_END | HASH_FLAG_HMAC_END)
+#define HASH_FLAG_CLR_ALL (HASH_FLAG_CYC_END | HASH_FLAG_HMAC_END)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup HASH_Trigger_Event HASH Trigger Event
+ * @{
+ */
+#define HASH_TRIG_EVT_DMA1_TC0 (EVT_SRC_DMA1_TC0) /*!< Select the DMA1 ch0 transfer complete*/
+#define HASH_TRIG_EVT_DMA1_TC1 (EVT_SRC_DMA1_TC1) /*!< Select the DMA1 ch1 transfer complete*/
+#define HASH_TRIG_EVT_DMA1_TC2 (EVT_SRC_DMA1_TC2) /*!< Select the DMA1 ch2 transfer complete*/
+#define HASH_TRIG_EVT_DMA1_TC3 (EVT_SRC_DMA1_TC3) /*!< Select the DMA1 ch3 transfer complete*/
+#define HASH_TRIG_EVT_DMA1_TC4 (EVT_SRC_DMA1_TC4) /*!< Select the DMA1 ch4 transfer complete*/
+#define HASH_TRIG_EVT_DMA1_TC5 (EVT_SRC_DMA1_TC5) /*!< Select the DMA1 ch5 transfer complete*/
+#define HASH_TRIG_EVT_DMA1_TC6 (EVT_SRC_DMA1_TC6) /*!< Select the DMA1 ch6 transfer complete*/
+#define HASH_TRIG_EVT_DMA1_TC7 (EVT_SRC_DMA1_TC7) /*!< Select the DMA1 ch7 transfer complete*/
+#define HASH_TRIG_EVT_DMA1_BTC0 (EVT_SRC_DMA1_BTC0) /*!< Select the DMA1 ch0 block transfer complete */
+#define HASH_TRIG_EVT_DMA1_BTC1 (EVT_SRC_DMA1_BTC1) /*!< Select the DMA1 ch1 block transfer complete */
+#define HASH_TRIG_EVT_DMA1_BTC2 (EVT_SRC_DMA1_BTC2) /*!< Select the DMA1 ch2 block transfer complete */
+#define HASH_TRIG_EVT_DMA1_BTC3 (EVT_SRC_DMA1_BTC3) /*!< Select the DMA1 ch3 block transfer complete */
+#define HASH_TRIG_EVT_DMA1_BTC4 (EVT_SRC_DMA1_BTC4) /*!< Select the DMA1 ch4 block transfer complete */
+#define HASH_TRIG_EVT_DMA1_BTC5 (EVT_SRC_DMA1_BTC5) /*!< Select the DMA1 ch5 block transfer complete */
+#define HASH_TRIG_EVT_DMA1_BTC6 (EVT_SRC_DMA1_BTC6) /*!< Select the DMA1 ch6 block transfer complete */
+#define HASH_TRIG_EVT_DMA1_BTC7 (EVT_SRC_DMA1_BTC7) /*!< Select the DMA1 ch7 block transfer complete */
+
+#define HASH_TRIG_EVT_DMA2_TC0 (EVT_SRC_DMA2_TC0) /*!< Select the DMA2 ch0 transfer complete*/
+#define HASH_TRIG_EVT_DMA2_TC1 (EVT_SRC_DMA2_TC1) /*!< Select the DMA2 ch1 transfer complete*/
+#define HASH_TRIG_EVT_DMA2_TC2 (EVT_SRC_DMA2_TC2) /*!< Select the DMA2 ch2 transfer complete*/
+#define HASH_TRIG_EVT_DMA2_TC3 (EVT_SRC_DMA2_TC3) /*!< Select the DMA2 ch3 transfer complete*/
+#define HASH_TRIG_EVT_DMA2_TC4 (EVT_SRC_DMA2_TC4) /*!< Select the DMA2 ch4 transfer complete*/
+#define HASH_TRIG_EVT_DMA2_TC5 (EVT_SRC_DMA2_TC5) /*!< Select the DMA2 ch5 transfer complete*/
+#define HASH_TRIG_EVT_DMA2_TC6 (EVT_SRC_DMA2_TC6) /*!< Select the DMA2 ch6 transfer complete*/
+#define HASH_TRIG_EVT_DMA2_TC7 (EVT_SRC_DMA2_TC7) /*!< Select the DMA2 ch7 transfer complete*/
+#define HASH_TRIG_EVT_DMA2_BTC0 (EVT_SRC_DMA2_BTC0) /*!< Select the DMA2 ch0 block transfer complete */
+#define HASH_TRIG_EVT_DMA2_BTC1 (EVT_SRC_DMA2_BTC1) /*!< Select the DMA2 ch1 block transfer complete */
+#define HASH_TRIG_EVT_DMA2_BTC2 (EVT_SRC_DMA2_BTC2) /*!< Select the DMA2 ch2 block transfer complete */
+#define HASH_TRIG_EVT_DMA2_BTC3 (EVT_SRC_DMA2_BTC3) /*!< Select the DMA2 ch3 block transfer complete */
+#define HASH_TRIG_EVT_DMA2_BTC4 (EVT_SRC_DMA2_BTC4) /*!< Select the DMA2 ch4 block transfer complete */
+#define HASH_TRIG_EVT_DMA2_BTC5 (EVT_SRC_DMA2_BTC5) /*!< Select the DMA2 ch5 block transfer complete */
+#define HASH_TRIG_EVT_DMA2_BTC6 (EVT_SRC_DMA2_BTC6) /*!< Select the DMA2 ch6 block transfer complete */
+#define HASH_TRIG_EVT_DMA2_BTC7 (EVT_SRC_DMA2_BTC7) /*!< Select the DMA2 ch7 block transfer complete */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup HASH_Global_Functions
+ * @{
+ */
+
+int32_t HASH_DeInit(void);
+int32_t HASH_Calculate(const uint8_t *pu8SrcData, uint32_t u32SrcDataSize, uint8_t *pu8MsgDigest);
+
+int32_t HASH_HMAC_Calculate(const uint8_t *pu8SrcData, uint32_t u32SrcDataSize,
+ const uint8_t *pu8Key, uint32_t u32KeySize,
+ uint8_t *pu8MsgDigest);
+
+int32_t HASH_IntCmd(uint32_t u32HashInt, en_functional_state_t enNewState);
+en_flag_status_t HASH_GetStatus(uint32_t u32Flag);
+int32_t HASH_ClearStatus(uint32_t u32Flag);
+
+int32_t HASH_SetMode(uint32_t u32HashMode);
+int32_t HASH_SetKeySizeMode(uint32_t u32SizeMode);
+int32_t HASH_SetMsgGroup(uint32_t u32MsgGroup);
+int32_t HASH_Start(void);
+void HASH_GetMsgDigest(uint8_t *pu8MsgDigest);
+
+/**
+ * @}
+ */
+
+#endif /* LL_HASH_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_HASH_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_i2c.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_i2c.h
new file mode 100644
index 0000000000..06031f96af
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_i2c.h
@@ -0,0 +1,396 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_i2c.h
+ * @brief This file contains all the functions prototypes of the Inter-Integrated
+ * Circuit(I2C) driver library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2022-10-31 CDT Modify API for FIFO function
+ 2023-09-30 CDT Move macro define I2C_SRC_CLK to head file and add marco I2C_WIDTH_MAX_IMME
+ 2023-12-15 CDT Rename I2C_FIFO_FLAG_xx as I2C_FLAG_xx_FIFO_xx, I2C_INT_RFREQ as I2C_INT_RX_FIFO_REQ
+ Adjust I2C_FLAG_ALL & I2C_FLAG_CLR_ALL & I2C_INT_ALL
+ Add I2C_Flag_Clear def group
+ Remove API I2C_FIFO_ClearRequestStatus() & I2C_FIFO_GetStatus
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_I2C_H__
+#define __HC32_LL_I2C_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_I2C
+ * @{
+ */
+
+#if (LL_I2C_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup I2C_Global_Types I2C Global Types
+ * @{
+ */
+
+/**
+ * @brief I2c configuration structure
+ */
+typedef struct {
+ uint32_t u32ClockDiv; /*!< I2C clock division for i2c source clock */
+ uint32_t u32Baudrate; /*!< I2C baudrate config */
+ uint32_t u32SclTime; /*!< The SCL rising and falling time, count of T(i2c source clock after frequency divider) */
+} stc_i2c_init_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/**
+ * @defgroup I2C_Global_Macros I2C Global Macros
+ * @{
+ */
+
+#define I2C_SRC_CLK (SystemCoreClock >> ((CM_CMU->SCFGR & CMU_SCFGR_PCLK0S) >> CMU_SCFGR_PCLK0S_POS))
+
+#define I2C_WIDTH_MAX_IMME (516UL)
+
+/**
+ * @defgroup I2C_Trans_Dir I2C Transfer Direction
+ * @{
+ */
+#define I2C_DIR_TX (0x0U)
+#define I2C_DIR_RX (0x1U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup I2C_Addr_Config I2C Address Configure
+ * @{
+ */
+#define I2C_ADDR_DISABLE (0U)
+#define I2C_ADDR_7BIT (I2C_SLR0_SLADDR0EN)
+#define I2C_ADDR_10BIT (I2C_SLR0_ADDRMOD0 | I2C_SLR0_SLADDR0EN)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup I2C_Clock_Division I2C Clock Division
+ * @{
+ */
+#define I2C_CLK_DIV1 (0UL) /*!< I2c source clock/1 */
+#define I2C_CLK_DIV2 (1UL) /*!< I2c source clock/2 */
+#define I2C_CLK_DIV4 (2UL) /*!< I2c source clock/4 */
+#define I2C_CLK_DIV8 (3UL) /*!< I2c source clock/8 */
+#define I2C_CLK_DIV16 (4UL) /*!< I2c source clock/16 */
+#define I2C_CLK_DIV32 (5UL) /*!< I2c source clock/32 */
+#define I2C_CLK_DIV64 (6UL) /*!< I2c source clock/64 */
+#define I2C_CLK_DIV128 (7UL) /*!< I2c source clock/128 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup I2C_Address_Num I2C Address Number
+ * @{
+ */
+#define I2C_ADDR0 (0UL)
+#define I2C_ADDR1 (1UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup I2C_Ack_Config I2C ACK Configure
+ * @{
+ */
+#define I2C_ACK (0UL) /*!< Send ACK after date receive */
+#define I2C_NACK (I2C_CR1_ACK) /*!< Send NACK after date received */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup I2C_Smbus_Match_Config I2C SMBUS Address Match Configure
+ * @{
+ */
+#define I2C_SMBUS_MATCH_ALARM (I2C_CR1_SMBALRTEN)
+#define I2C_SMBUS_MATCH_DEFAULT (I2C_CR1_SMBDEFAULTEN)
+#define I2C_SMBUS_MATCH_HOST (I2C_CR1_SMBHOSTEN)
+#define I2C_SMBUS_MATCH_ALL (I2C_CR1_SMBALRTEN | I2C_CR1_SMBDEFAULTEN | I2C_CR1_SMBHOSTEN)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup I2C_Digital_Filter_Clock I2C Digital Filter Clock
+ * @{
+ */
+#define I2C_DIG_FILTER_CLK_DIV1 (0UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/1 */
+#define I2C_DIG_FILTER_CLK_DIV2 (1UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/2 */
+#define I2C_DIG_FILTER_CLK_DIV3 (2UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/3 */
+#define I2C_DIG_FILTER_CLK_DIV4 (3UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/4 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup I2C_Flag I2C Flag
+ * @{
+ */
+#define I2C_FLAG_START (I2C_SR_STARTF) /*!< Start condition detected */
+#define I2C_FLAG_MATCH_ADDR0 (I2C_SR_SLADDR0F) /*!< Address 0 detected */
+#define I2C_FLAG_MATCH_ADDR1 (I2C_SR_SLADDR1F) /*!< Address 1 detected */
+#define I2C_FLAG_TX_CPLT (I2C_SR_TENDF) /*!< Transfer end */
+#define I2C_FLAG_STOP (I2C_SR_STOPF) /*!< Stop condition detected */
+#define I2C_FLAG_RX_FULL (I2C_SR_RFULLF) /*!< Receive buffer full */
+#define I2C_FLAG_TX_EMPTY (I2C_SR_TEMPTYF) /*!< Transfer buffer empty */
+#define I2C_FLAG_ARBITRATE_FAIL (I2C_SR_ARLOF) /*!< Arbitration fails */
+#define I2C_FLAG_ACKR (I2C_SR_ACKRF) /*!< ACK status */
+#define I2C_FLAG_NACKF (I2C_SR_NACKF) /*!< NACK detected */
+#define I2C_FLAG_TMOUTF (I2C_SR_TMOUTF) /*!< Time out detected */
+#define I2C_FLAG_MASTER (I2C_SR_MSL) /*!< Master mode flag */
+#define I2C_FLAG_BUSY (I2C_SR_BUSY) /*!< Bus busy status */
+#define I2C_FLAG_TRA (I2C_SR_TRA) /*!< Transfer mode flag */
+#define I2C_FLAG_GENERAL_CALL (I2C_SR_GENCALLF) /*!< General call detected */
+#define I2C_FLAG_SMBUS_DEFAULT_MATCH (I2C_SR_SMBDEFAULTF) /*!< SMBUS default address detected */
+#define I2C_FLAG_SMBUS_HOST_MATCH (I2C_SR_SMBHOSTF) /*!< SMBUS host address detected */
+#define I2C_FLAG_SMBUS_ALARM_MATCH (I2C_SR_SMBALRTF) /*!< SMBUS alarm address detected */
+#define I2C_FLAG_RX_FIFO_REQ (I2C_SR_RFREQ) /*!< Receive FIFO request */
+#define I2C_FLAG_RX_FIFO_FULL (I2C_SR_RFFULL) /*!< Receive FIFO full */
+#define I2C_FLAG_RX_FIFO_EMPTY (I2C_SR_RFEMPTY) /*!< Receive FIFO empty */
+#define I2C_FLAG_TX_FIFO_FULL (I2C_SR_TFFULL) /*!< Transfer FIFO full */
+#define I2C_FLAG_TX_FIFO_EMPTY (I2C_SR_TFEMPTY) /*!< Transfer FIFO empty */
+
+#define I2C_FLAG_ALL (I2C_FLAG_START | I2C_FLAG_NACKF | \
+ I2C_FLAG_MATCH_ADDR0 | I2C_FLAG_TMOUTF | \
+ I2C_FLAG_MATCH_ADDR1 | I2C_FLAG_MASTER | \
+ I2C_FLAG_TX_CPLT | I2C_FLAG_BUSY | \
+ I2C_FLAG_STOP | I2C_FLAG_TRA | \
+ I2C_FLAG_RX_FULL | I2C_FLAG_GENERAL_CALL | \
+ I2C_FLAG_TX_EMPTY | I2C_FLAG_SMBUS_DEFAULT_MATCH | \
+ I2C_FLAG_ARBITRATE_FAIL | I2C_FLAG_SMBUS_HOST_MATCH | \
+ I2C_FLAG_ACKR | I2C_FLAG_SMBUS_ALARM_MATCH | \
+ I2C_FLAG_RX_FIFO_REQ | I2C_FLAG_RX_FIFO_FULL | \
+ I2C_FLAG_RX_FIFO_EMPTY | I2C_FLAG_TX_FIFO_FULL | \
+ I2C_FLAG_TX_FIFO_EMPTY)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup I2C_Flag_Clear I2C Flag to clear
+ * @{
+ */
+#define I2C_FLAG_CLR_START (I2C_CLR_STARTFCLR) /*!< Start condition detected */
+#define I2C_FLAG_CLR_MATCH_ADDR0 (I2C_CLR_SLADDR0FCLR) /*!< Address 0 detected */
+#define I2C_FLAG_CLR_MATCH_ADDR1 (I2C_CLR_SLADDR1FCLR) /*!< Address 1 detected */
+#define I2C_FLAG_CLR_TX_CPLT (I2C_CLR_TENDFCLR) /*!< Transfer end */
+#define I2C_FLAG_CLR_STOP (I2C_CLR_STOPFCLR) /*!< Stop condition detected */
+#define I2C_FLAG_CLR_RX_FULL (I2C_CLR_RFULLFCLR) /*!< Receive buffer full */
+#define I2C_FLAG_CLR_ARBITRATE_FAIL (I2C_CLR_ARLOFCLR) /*!< Arbitration fails */
+#define I2C_FLAG_CLR_NACK (I2C_CLR_NACKFCLR) /*!< NACK detected */
+#define I2C_FLAG_CLR_TMOUTF (I2C_CLR_TMOUTFCLR) /*!< Time out detected */
+#define I2C_FLAG_CLR_GENERAL_CALL (I2C_CLR_GENCALLFCLR) /*!< General call detected */
+#define I2C_FLAG_CLR_SMBUS_DEFAULT_MATCH (I2C_CLR_SMBDEFAULTFCLR) /*!< SMBUS default address detected */
+#define I2C_FLAG_CLR_SMBUS_HOST_MATCH (I2C_CLR_SMBHOSTFCLR) /*!< SMBUS host address detected */
+#define I2C_FLAG_CLR_SMBUS_ALARM_MATCH (I2C_CLR_SMBALRTFCLR) /*!< SMBUS alarm address detected */
+#define I2C_FLAG_CLR_RX_FIFO_REQ (I2C_CLR_RFREQCLR) /*!< Receive FIFO request */
+
+#define I2C_FLAG_CLR_ALL (I2C_FLAG_CLR_START | I2C_FLAG_CLR_ARBITRATE_FAIL | \
+ I2C_FLAG_CLR_MATCH_ADDR0 | I2C_FLAG_CLR_NACK | \
+ I2C_FLAG_CLR_MATCH_ADDR1 | I2C_FLAG_CLR_TMOUTF | \
+ I2C_FLAG_CLR_TX_CPLT | I2C_FLAG_CLR_GENERAL_CALL | \
+ I2C_FLAG_CLR_STOP | I2C_FLAG_CLR_SMBUS_DEFAULT_MATCH | \
+ I2C_FLAG_CLR_RX_FULL | I2C_FLAG_CLR_SMBUS_HOST_MATCH | \
+ I2C_FLAG_CLR_SMBUS_ALARM_MATCH | \
+ I2C_FLAG_CLR_RX_FIFO_REQ)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup I2C_FIFO_Data_Status I2C FIFO status
+ * @{
+ */
+#define I2C_FIFO_EMPTY (0U)
+#define I2C_FIFO_HALFFULL (1U)
+#define I2C_FIFO_FULL (2U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup I2C_Int_Flag I2C Interrupt Flag Bits
+ * @{
+ */
+#define I2C_INT_START (I2C_CR2_STARTIE)
+#define I2C_INT_MATCH_ADDR0 (I2C_CR2_SLADDR0IE)
+#define I2C_INT_MATCH_ADDR1 (I2C_CR2_SLADDR1IE)
+#define I2C_INT_TX_CPLT (I2C_CR2_TENDIE)
+#define I2C_INT_STOP (I2C_CR2_STOPIE)
+#define I2C_INT_RX_FULL (I2C_CR2_RFULLIE)
+#define I2C_INT_TX_EMPTY (I2C_CR2_TEMPTYIE)
+#define I2C_INT_ARBITRATE_FAIL (I2C_CR2_ARLOIE)
+#define I2C_INT_NACK (I2C_CR2_NACKIE)
+#define I2C_INT_TMOUTIE (I2C_CR2_TMOUTIE)
+#define I2C_INT_GENERAL_CALL (I2C_CR2_GENCALLIE)
+#define I2C_INT_SMBUS_DEFAULT_MATCH (I2C_CR2_SMBDEFAULTIE)
+#define I2C_INT_SMBUS_HOST_MATCH (I2C_CR2_SMBHOSTIE)
+#define I2C_INT_SMBUS_ALARM_MATCH (I2C_CR2_SMBALRTIE)
+#define I2C_INT_RX_FIFO_REQ (I2C_CR2_RFREQIE)
+#define I2C_INT_ALL (I2C_INT_START | I2C_INT_ARBITRATE_FAIL | \
+ I2C_INT_MATCH_ADDR0 | I2C_INT_NACK | \
+ I2C_INT_MATCH_ADDR1 | I2C_INT_TMOUTIE | \
+ I2C_INT_TX_CPLT | I2C_INT_GENERAL_CALL | \
+ I2C_INT_STOP | I2C_INT_SMBUS_DEFAULT_MATCH | \
+ I2C_INT_RX_FULL | I2C_INT_SMBUS_HOST_MATCH | \
+ I2C_INT_TX_EMPTY | I2C_INT_SMBUS_ALARM_MATCH | \
+ I2C_INT_RX_FIFO_REQ)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup I2C_Global_Functions
+ * @{
+ */
+
+/* Initialization and Configuration **********************************/
+int32_t I2C_StructInit(stc_i2c_init_t *pstcI2cInit);
+int32_t I2C_BaudrateConfig(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error);
+int32_t I2C_DeInit(CM_I2C_TypeDef *I2Cx);
+int32_t I2C_Init(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error);
+void I2C_SlaveAddrConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, uint32_t u32AddrMode, uint32_t u32Addr);
+void I2C_SlaveAddrCmd(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, en_functional_state_t enNewState);
+void I2C_Cmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
+void I2C_FastAckCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
+void I2C_BusWaitCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
+
+void I2C_SmbusConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32SmbusConfig, en_functional_state_t enNewState);
+void I2C_SmbusCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
+
+void I2C_DigitalFilterConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32FilterClock);
+void I2C_DigitalFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
+
+void I2C_AnalogFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
+
+void I2C_GeneralCallCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
+void I2C_SWResetCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
+void I2C_IntCmd(CM_I2C_TypeDef *I2Cx, uint32_t u32IntType, en_functional_state_t enNewState);
+
+void I2C_SlaveMaskAddrConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, uint32_t u32AddrMode, uint32_t u32MaskAddr);
+void I2C_SlaveMaskAddrCmd(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, en_functional_state_t enNewState);
+
+void I2C_BusFreeClearCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
+
+/* Start/Restart/Stop ************************************************/
+void I2C_GenerateStart(CM_I2C_TypeDef *I2Cx);
+void I2C_GenerateRestart(CM_I2C_TypeDef *I2Cx);
+void I2C_GenerateStop(CM_I2C_TypeDef *I2Cx);
+
+/* Status management *************************************************/
+en_flag_status_t I2C_GetStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag);
+void I2C_ClearStatus(CM_I2C_TypeDef *I2Cx, uint32_t u32Flag);
+
+/* FIFO *************************************************************/
+void I2C_FIFO_Cmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
+uint32_t I2C_FIFO_GetTxDataNum(const CM_I2C_TypeDef *I2Cx);
+uint32_t I2C_FIFO_GetRxDataStatus(const CM_I2C_TypeDef *I2Cx);
+uint32_t I2C_FIFO_GetTxDataStatus(const CM_I2C_TypeDef *I2Cx);
+void I2C_FIFO_NackResetFIFOCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
+void I2C_FIFO_TxFlush(CM_I2C_TypeDef *I2Cx);
+void I2C_FIFO_RxFlush(CM_I2C_TypeDef *I2Cx);
+
+/* Data transfer *****************************************************/
+void I2C_WriteData(CM_I2C_TypeDef *I2Cx, uint8_t u8Data);
+uint8_t I2C_ReadData(const CM_I2C_TypeDef *I2Cx);
+void I2C_AckConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AckConfig);
+
+/* Time out function *************************************************/
+void I2C_SCLHighTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutH);
+void I2C_SCLLowTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutL);
+void I2C_SCLHighTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
+void I2C_SCLLowTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
+void I2C_SCLTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState);
+
+/* High level functions for reference ********************************/
+int32_t I2C_Start(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout);
+int32_t I2C_Restart(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout);
+int32_t I2C_TransAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout);
+int32_t I2C_Trans10BitAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout);
+int32_t I2C_TransData(CM_I2C_TypeDef *I2Cx, uint8_t const au8TxData[], uint32_t u32Size, uint32_t u32Timeout);
+int32_t I2C_ReceiveData(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout);
+int32_t I2C_MasterReceiveDataAndStop(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout);
+int32_t I2C_Stop(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout);
+int32_t I2C_WaitStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout);
+
+/**
+ * @}
+ */
+
+#endif /* LL_I2C_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_I2C_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_icg.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_icg.h
new file mode 100644
index 0000000000..1d401f86b0
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_icg.h
@@ -0,0 +1,440 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_icg.h
+ * @brief This file contains all the Macro Definitions of the ICG driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-12-15 CDT Modify macro define：ICG_SWDT_LPM_CNT_CONTINUE -> ICG_SWDT_LPM_CNT_CONT
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_ICG_H__
+#define __HC32_LL_ICG_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_ICG
+ * @{
+ */
+
+#if (LL_ICG_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup ICG_Global_Macros ICG Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup ICG_SWDT_Reset_State ICG SWDT Reset State
+ * @{
+ */
+#define ICG_SWDT_RST_START (0UL) /*!< SWDT auto start after reset */
+#define ICG_SWDT_RST_STOP (ICG_ICG0_SWDTAUTS) /*!< SWDT stop after reset */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ICG_SWDT_Exception_Type ICG SWDT Exception Type
+ * @{
+ */
+#define ICG_SWDT_EXP_TYPE_INT (0UL) /*!< SWDT trigger interrupt */
+#define ICG_SWDT_EXP_TYPE_RST (ICG_ICG0_SWDTITS) /*!< SWDT trigger reset */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ICG_SWDT_Count_Period ICG SWDT Count Period
+ * @{
+ */
+#define ICG_SWDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */
+#define ICG_SWDT_CNT_PERIOD4096 (ICG_ICG0_SWDTPERI_0) /*!< 4096 clock cycle */
+#define ICG_SWDT_CNT_PERIOD16384 (ICG_ICG0_SWDTPERI_1) /*!< 16384 clock cycle */
+#define ICG_SWDT_CNT_PERIOD65536 (ICG_ICG0_SWDTPERI) /*!< 65536 clock cycle */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ICG_SWDT_Clock_Division ICG SWDT Clock Division
+ * @{
+ */
+#define ICG_SWDT_CLK_DIV1 (0UL) /*!< CLK */
+#define ICG_SWDT_CLK_DIV16 (0x04UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/16 */
+#define ICG_SWDT_CLK_DIV32 (0x05UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/32 */
+#define ICG_SWDT_CLK_DIV64 (0x06UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/64 */
+#define ICG_SWDT_CLK_DIV128 (0x07UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/128 */
+#define ICG_SWDT_CLK_DIV256 (0x08UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/256 */
+#define ICG_SWDT_CLK_DIV2048 (0x0BUL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/2048 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ICG_SWDT_Refresh_Range ICG SWDT Refresh Range
+ * @{
+ */
+#define ICG_SWDT_RANGE_0TO25PCT (0x01UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% */
+#define ICG_SWDT_RANGE_25TO50PCT (0x02UL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~50% */
+#define ICG_SWDT_RANGE_0TO50PCT (0x03UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~50% */
+#define ICG_SWDT_RANGE_50TO75PCT (0x04UL << ICG_ICG0_SWDTWDPT_POS) /*!< 50%~75% */
+#define ICG_SWDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% & 50%~75% */
+#define ICG_SWDT_RANGE_25TO75PCT (0x06UL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~75% */
+#define ICG_SWDT_RANGE_0TO75PCT (0x07UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~75% */
+#define ICG_SWDT_RANGE_75TO100PCT (0x08UL << ICG_ICG0_SWDTWDPT_POS) /*!< 75%~100% */
+#define ICG_SWDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% & 75%~100% */
+#define ICG_SWDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~50% & 75%~100% */
+#define ICG_SWDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~50% & 75%~100% */
+#define ICG_SWDT_RANGE_50TO100PCT (0x0CUL << ICG_ICG0_SWDTWDPT_POS) /*!< 50%~100% */
+#define ICG_SWDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% & 50%~100% */
+#define ICG_SWDT_RANGE_25TO100PCT (0x0EUL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~100% */
+#define ICG_SWDT_RANGE_0TO100PCT (0x0FUL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~100% */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ICG_SWDT_LPM_Count ICG SWDT Low Power Mode Count
+ * @brief Counting control of SWDT in sleep/stop mode
+ * @{
+ */
+#define ICG_SWDT_LPM_CNT_CONT (0UL) /*!< Continue counting in sleep/stop mode */
+#define ICG_SWDT_LPM_CNT_STOP (ICG_ICG0_SWDTSLPOFF) /*!< Stop counting in sleep/stop mode */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ICG_WDT_Reset_State ICG WDT Reset State
+ * @{
+ */
+#define ICG_WDT_RST_START (0UL) /*!< WDT auto start after reset */
+#define ICG_WDT_RST_STOP (ICG_ICG0_WDTAUTS) /*!< WDT stop after reset */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ICG_WDT_Exception_Type ICG WDT Exception Type
+ * @{
+ */
+#define ICG_WDT_EXP_TYPE_INT (0UL) /*!< WDT trigger interrupt */
+#define ICG_WDT_EXP_TYPE_RST (ICG_ICG0_WDTITS) /*!< WDT trigger reset */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ICG_WDT_Count_Period ICG WDT Count Period
+ * @{
+ */
+#define REDEF_ICG_WDTPERI_POS ICG_ICG0_WDTPERI_POS
+
+#define ICG_WDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */
+#define ICG_WDT_CNT_PERIOD4096 (0x01UL << REDEF_ICG_WDTPERI_POS) /*!< 4096 clock cycle */
+#define ICG_WDT_CNT_PERIOD16384 (0x02UL << REDEF_ICG_WDTPERI_POS) /*!< 16384 clock cycle */
+#define ICG_WDT_CNT_PERIOD65536 (0x03UL << REDEF_ICG_WDTPERI_POS) /*!< 65536 clock cycle */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ICG_WDT_Clock_Division ICG WDT Clock Division
+ * @{
+ */
+#define REDEF_ICG_WDTCKS_POS ICG_ICG0_WDTCKS_POS
+
+#define ICG_WDT_CLK_DIV4 (0x02UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/4 */
+#define ICG_WDT_CLK_DIV64 (0x06UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/64 */
+#define ICG_WDT_CLK_DIV128 (0x07UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/128 */
+#define ICG_WDT_CLK_DIV256 (0x08UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/256 */
+#define ICG_WDT_CLK_DIV512 (0x09UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/512 */
+#define ICG_WDT_CLK_DIV1024 (0x0AUL << REDEF_ICG_WDTCKS_POS) /*!< CLK/1024 */
+#define ICG_WDT_CLK_DIV2048 (0x0BUL << REDEF_ICG_WDTCKS_POS) /*!< CLK/2048 */
+#define ICG_WDT_CLK_DIV8192 (0x0DUL << REDEF_ICG_WDTCKS_POS) /*!< CLK/8192 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ICG_WDT_Refresh_Range ICG WDT Refresh Range
+ * @{
+ */
+#define REDEF_ICG_WDTWDPT_POS ICG_ICG0_WDTWDPT_POS
+
+#define ICG_WDT_RANGE_0TO25PCT (0x01UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% */
+#define ICG_WDT_RANGE_25TO50PCT (0x02UL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~50% */
+#define ICG_WDT_RANGE_0TO50PCT (0x03UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~50% */
+#define ICG_WDT_RANGE_50TO75PCT (0x04UL << REDEF_ICG_WDTWDPT_POS) /*!< 50%~75% */
+#define ICG_WDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% & 50%~75% */
+#define ICG_WDT_RANGE_25TO75PCT (0x06UL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~75% */
+#define ICG_WDT_RANGE_0TO75PCT (0x07UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~75% */
+#define ICG_WDT_RANGE_75TO100PCT (0x08UL << REDEF_ICG_WDTWDPT_POS) /*!< 75%~100% */
+#define ICG_WDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% & 75%~100% */
+#define ICG_WDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~50% & 75%~100% */
+#define ICG_WDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~50% & 75%~100% */
+#define ICG_WDT_RANGE_50TO100PCT (0x0CUL << REDEF_ICG_WDTWDPT_POS) /*!< 50%~100% */
+#define ICG_WDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% & 50%~100% */
+#define ICG_WDT_RANGE_25TO100PCT (0x0EUL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~100% */
+#define ICG_WDT_RANGE_0TO100PCT (0x0FUL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~100% */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ICG_WDT_LPM_Count ICG WDT Low Power Mode Count
+ * @brief Counting control of WDT in sleep mode
+ * @{
+ */
+#define ICG_WDT_LPM_CNT_CONT (0UL) /*!< Continue counting in sleep mode */
+#define ICG_WDT_LPM_CNT_STOP (ICG_ICG0_WDTSLPOFF) /*!< Stop counting in sleep mode */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ICG_BOR_Voltage_Threshold ICG BOR Voltage Threshold
+ * @{
+ */
+#define ICG_BOR_VOL_THRESHOLD_LVL0 (0UL) /*!< BOR voltage threshold 1.9V */
+#define ICG_BOR_VOL_THRESHOLD_LVL1 (ICG_ICG1_BOR_LEV_0) /*!< BOR voltage threshold 2.0V */
+#define ICG_BOR_VOL_THRESHOLD_LVL2 (ICG_ICG1_BOR_LEV_1) /*!< BOR voltage threshold 2.1V */
+#define ICG_BOR_VOL_THRESHOLD_LVL3 (ICG_ICG1_BOR_LEV) /*!< BOR voltage threshold 2.3V */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ICG_BOR_Reset_State ICG BOR Reset State
+ * @{
+ */
+#define ICG_BOR_RST_ENABLE (0UL) /*!< Enable BOR voltage detection after reset */
+#define ICG_BOR_RST_DISABLE (ICG_ICG1_BORDIS) /*!< Disable BOR voltage detection after reset */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ICG_HRC_Frequency_Select ICG HRC Frequency Select
+ * @{
+ */
+
+#define ICG_HRC_20M (0UL) /*!< HRC = 20MHZ */
+#define ICG_HRC_16M (ICG_ICG1_HRCFREQSEL) /*!< HRC = 16MHZ */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ICG_HRC_Reset_State ICG HRC Reset State
+ * @{
+ */
+#define ICG_HRC_RST_OSCILLATION (0UL) /*!< HRC Oscillation after reset */
+#define ICG_HRC_RST_STOP (ICG_ICG1_HRCSTOP) /*!< HRC stop after reset */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ICG_FLASH_Protect_Reset_State ICG FLASH Protect Reset State
+ * @brief Enable or disable D-BUS read protection for addresses 0x00000000 - 0x0001FFFF
+ * @{
+ */
+#define ICG_FLASH_PROTECT_RST_DISABLE (0xFFFFFFFFUL) /*!< Disable D-BUS read protection after reset */
+#define ICG_FLASH_PROTECT_RST_ENABLE (0x00004450UL) /*!< Enable D-BUS read protection after reset */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ICG_Register_Configuration ICG Register Configuration
+ * @{
+ */
+
+/**
+ * @defgroup ICG_SWDT_Preload_Configuration ICG SWDT Preload Configuration
+ * @{
+ */
+/* SWDT register config */
+#define ICG_RB_SWDT_AUTS (ICG_SWDT_RST_STOP)
+#define ICG_RB_SWDT_ITS (ICG_SWDT_EXP_TYPE_RST)
+#define ICG_RB_SWDT_PERI (ICG_SWDT_CNT_PERIOD65536)
+#define ICG_RB_SWDT_CKS (ICG_SWDT_CLK_DIV2048)
+#define ICG_RB_SWDT_WDPT (ICG_SWDT_RANGE_0TO100PCT)
+#define ICG_RB_SWDT_SLTPOFF (ICG_SWDT_LPM_CNT_STOP)
+
+/* SWDT register value */
+#define ICG_REG_SWDT_CONFIG (ICG_RB_SWDT_AUTS | ICG_RB_SWDT_ITS | ICG_RB_SWDT_PERI | \
+ ICG_RB_SWDT_CKS | ICG_RB_SWDT_WDPT | ICG_RB_SWDT_SLTPOFF)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ICG_WDT_Preload_Configuration ICG WDT Preload Configuration
+ * @{
+ */
+/* WDT register config */
+#define ICG_RB_WDT_AUTS (ICG_WDT_RST_STOP)
+#define ICG_RB_WDT_ITS (ICG_WDT_EXP_TYPE_RST)
+#define ICG_RB_WDT_PERI (ICG_WDT_CNT_PERIOD65536)
+#define ICG_RB_WDT_CKS (ICG_WDT_CLK_DIV8192)
+#define ICG_RB_WDT_WDPT (ICG_WDT_RANGE_0TO100PCT)
+#define ICG_RB_WDT_SLTPOFF (ICG_WDT_LPM_CNT_STOP)
+
+/* WDT register value */
+#define ICG_REG_WDT_CONFIG (ICG_RB_WDT_AUTS | ICG_RB_WDT_ITS | ICG_RB_WDT_PERI | \
+ ICG_RB_WDT_CKS | ICG_RB_WDT_WDPT | ICG_RB_WDT_SLTPOFF)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ICG_BOR_Preload_Configuration ICG BOR Preload Configuration
+ * @{
+ */
+/* BOR register config */
+#define ICG_RB_BOR_LEV (ICG_BOR_VOL_THRESHOLD_LVL3)
+#define ICG_RB_BOR_DIS (ICG_BOR_RST_DISABLE)
+
+/* BOR register value */
+#define ICG_REG_BOR_CONFIG (ICG_RB_BOR_LEV | ICG_RB_BOR_DIS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ICG_HRC_Preload_Configuration ICG HRC Preload Configuration
+ * @{
+ */
+/* HRC register config */
+#define ICG_RB_HRC_FREQSEL (ICG_HRC_16M)
+#define ICG_RB_HRC_STOP (ICG_HRC_RST_STOP)
+
+/* HRC register value */
+#define ICG_REG_HRC_CONFIG (ICG_RB_HRC_FREQSEL | ICG_RB_HRC_STOP)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ICG_FLASH_Protect_Preload_Configuration ICG FLASH Protect Preload Configuration
+ * @{
+ */
+/* FLASH Read Protect register value */
+#define ICG_REG_FLASH_PROTECT_CONFIG (ICG_FLASH_PROTECT_RST_DISABLE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ICG_FLASH_Boot_Source_Configuration ICG FLASH Boot Source Configuration
+ * @note The register is valid when the MD pin is at high voltage.
+ * @{
+ */
+/* Boot Source register value */
+#define ICG_REG_BOOT_SRC_MAIN_FLASH (0x48440682UL)
+#define ICG_REG_BOOT_SRC_SYS_FLASH (0xFFFFFFFFUL)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ICG_Register_Value ICG Register Value
+ * @{
+ */
+/* ICG register value */
+#ifndef ICG_REG_CFG0_CONST
+#define ICG_REG_CFG0_CONST (ICG_REG_WDT_CONFIG | ICG_REG_SWDT_CONFIG | 0xE000E000UL)
+#endif
+#ifndef ICG_REG_CFG1_CONST
+#define ICG_REG_CFG1_CONST (ICG_REG_BOR_CONFIG | ICG_REG_HRC_CONFIG | 0xFFF8FEFEUL)
+#endif
+#ifndef ICG_REG_CFG2_CONST
+#define ICG_REG_CFG2_CONST (0xFFFFFFFFUL)
+#endif
+#ifndef ICG_REG_CFG3_CONST
+#define ICG_REG_CFG3_CONST (ICG_REG_FLASH_PROTECT_CONFIG | 0xFFFF0000UL)
+#endif
+#ifndef ICG_REG_CFG4_CONST
+#define ICG_REG_CFG4_CONST (ICG_REG_BOOT_SRC_SYS_FLASH)
+#endif
+/* ICG reserved value */
+#define ICG_REG_RESV_CONST (0xFFFFFFFFUL)
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+
+#endif /* LL_ICG_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_ICG_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_interrupts.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_interrupts.h
new file mode 100644
index 0000000000..413ae9848f
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_interrupts.h
@@ -0,0 +1,479 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_interrupts.h
+ * @brief This file contains all the functions prototypes of the interrupt driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-12-15 CDT Add declaration of API INTC_GetIntSrcState()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_INTERRUPTS_H__
+#define __HC32_LL_INTERRUPTS_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_INTERRUPTS
+ * @{
+ */
+
+#if (LL_INTERRUPTS_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup INTC_Global_Types INTC Global Types
+ * @{
+ */
+
+/**
+ * @brief Interrupt registration structure definition
+ */
+typedef struct {
+ en_int_src_t enIntSrc; /*!< Peripheral interrupt number, can be any value @ref en_int_src_t */
+ IRQn_Type enIRQn; /*!< Peripheral IRQ type, can be INT000_IRQn~INT127_IRQn @ref IRQn_Type */
+ func_ptr_t pfnCallback; /*!< Callback function for corresponding peripheral IRQ */
+} stc_irq_signin_config_t;
+
+/**
+ * @brief NMI initialize configuration structure definition
+ */
+typedef struct {
+ uint32_t u32Src; /*!< NMI trigger source, @ref NMI_TriggerSrc_Sel for details */
+} stc_nmi_init_t;
+
+/**
+ * @brief EXTINT initialize configuration structure definition
+ */
+typedef struct {
+ uint32_t u32Filter; /*!< ExtInt filter (A) function setting, @ref EXTINT_FilterClock_Sel for details */
+ uint32_t u32FilterClock; /*!< ExtInt filter (A) clock division, @ref EXTINT_FilterClock_Div for details */
+ uint32_t u32Edge; /*!< ExtInt trigger edge, @ref EXTINT_Trigger_Sel for details */
+ uint32_t u32FilterB; /*!< NMI, ExtInt filter B function setting, @ref NMI_EXTINT_FilterBClock_Sel for details */
+ uint32_t u32FilterBClock; /*!< NMI, ExtInt filter B time, @ref NMI_EXTINT_FilterBTim_Sel for details */
+} stc_extint_init_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup INTC_Global_Macros INTC Global Macros
+ * @{
+ */
+/**
+ * @defgroup INTC_Priority_Sel Interrupt Priority Level 00 ~ 15
+ * @{
+ */
+#define DDL_IRQ_PRIO_00 (0U)
+#define DDL_IRQ_PRIO_01 (1U)
+#define DDL_IRQ_PRIO_02 (2U)
+#define DDL_IRQ_PRIO_03 (3U)
+#define DDL_IRQ_PRIO_04 (4U)
+#define DDL_IRQ_PRIO_05 (5U)
+#define DDL_IRQ_PRIO_06 (6U)
+#define DDL_IRQ_PRIO_07 (7U)
+#define DDL_IRQ_PRIO_08 (8U)
+#define DDL_IRQ_PRIO_09 (9U)
+#define DDL_IRQ_PRIO_10 (10U)
+#define DDL_IRQ_PRIO_11 (11U)
+#define DDL_IRQ_PRIO_12 (12U)
+#define DDL_IRQ_PRIO_13 (13U)
+#define DDL_IRQ_PRIO_14 (14U)
+#define DDL_IRQ_PRIO_15 (15U)
+
+#define DDL_IRQ_PRIO_DEFAULT (DDL_IRQ_PRIO_15)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup NMI_TriggerSrc_Sel NMI Trigger Source Selection
+ * @{
+ */
+#define NMI_SRC_SWDT (INTC_NMIFR_SWDTF)
+#define NMI_SRC_LVD1 (INTC_NMIFR_PVD1F)
+#define NMI_SRC_LVD2 (INTC_NMIFR_PVD2F)
+#define NMI_SRC_XTAL (INTC_NMIFR_XTALSTPF)
+#define NMI_SRC_SRAM_PARITY (INTC_NMIFR_RPARERRF)
+#define NMI_SRC_SRAM_ECC (INTC_NMIFR_RECCERRF)
+#define NMI_SRC_BUS_ERR (INTC_NMIFR_BUSERRF)
+#define NMI_SRC_WDT (INTC_NMIFR_WDTF)
+#define NMI_SRC_ALL (NMI_SRC_SWDT | NMI_SRC_LVD1 | NMI_SRC_LVD2 | \
+ NMI_SRC_XTAL | NMI_SRC_BUS_ERR | NMI_SRC_SRAM_PARITY | \
+ NMI_SRC_WDT | NMI_SRC_SRAM_ECC)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EXTINT_Channel_Sel External Interrupt Channel Selection
+ * @{
+ */
+#define EXTINT_CH00 (1UL << 0U)
+#define EXTINT_CH01 (1UL << 1U)
+#define EXTINT_CH02 (1UL << 2U)
+#define EXTINT_CH03 (1UL << 3U)
+#define EXTINT_CH04 (1UL << 4U)
+#define EXTINT_CH05 (1UL << 5U)
+#define EXTINT_CH06 (1UL << 6U)
+#define EXTINT_CH07 (1UL << 7U)
+#define EXTINT_CH08 (1UL << 8U)
+#define EXTINT_CH09 (1UL << 9U)
+#define EXTINT_CH10 (1UL <<10U)
+#define EXTINT_CH11 (1UL <<11U)
+#define EXTINT_CH12 (1UL <<12U)
+#define EXTINT_CH13 (1UL <<13U)
+#define EXTINT_CH14 (1UL <<14U)
+#define EXTINT_CH15 (1UL <<15U)
+#define EXTINT_CH_ALL (EXTINT_CH00 | EXTINT_CH01 | EXTINT_CH02 | EXTINT_CH03 | \
+ EXTINT_CH04 | EXTINT_CH05 | EXTINT_CH06 | EXTINT_CH07 | \
+ EXTINT_CH08 | EXTINT_CH09 | EXTINT_CH10 | EXTINT_CH11 | \
+ EXTINT_CH12 | EXTINT_CH13 | EXTINT_CH14 | EXTINT_CH15)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup INT_Channel_Sel Interrupt Channel Selection
+ * @{
+ */
+#define INTC_INT0 INTC_IER_IEN0
+#define INTC_INT1 INTC_IER_IEN1
+#define INTC_INT2 INTC_IER_IEN2
+#define INTC_INT3 INTC_IER_IEN3
+#define INTC_INT4 INTC_IER_IEN4
+#define INTC_INT5 INTC_IER_IEN5
+#define INTC_INT6 INTC_IER_IEN6
+#define INTC_INT7 INTC_IER_IEN7
+#define INTC_INT8 INTC_IER_IEN8
+#define INTC_INT9 INTC_IER_IEN9
+#define INTC_INT10 INTC_IER_IEN10
+#define INTC_INT11 INTC_IER_IEN11
+#define INTC_INT12 INTC_IER_IEN12
+#define INTC_INT13 INTC_IER_IEN13
+#define INTC_INT14 INTC_IER_IEN14
+#define INTC_INT15 INTC_IER_IEN15
+#define INTC_INT16 INTC_IER_IEN16
+#define INTC_INT17 INTC_IER_IEN17
+#define INTC_INT18 INTC_IER_IEN18
+#define INTC_INT19 INTC_IER_IEN19
+#define INTC_INT20 INTC_IER_IEN20
+#define INTC_INT21 INTC_IER_IEN21
+#define INTC_INT22 INTC_IER_IEN22
+#define INTC_INT23 INTC_IER_IEN23
+#define INTC_INT24 INTC_IER_IEN24
+#define INTC_INT25 INTC_IER_IEN25
+#define INTC_INT26 INTC_IER_IEN26
+#define INTC_INT27 INTC_IER_IEN27
+#define INTC_INT28 INTC_IER_IEN28
+#define INTC_INT29 INTC_IER_IEN29
+#define INTC_INT30 INTC_IER_IEN30
+#define INTC_INT31 INTC_IER_IEN31
+#define INTC_INT_ALL (0xFFFFFFFFUL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup INTC_Event_Channel_Sel Event Channel Selection
+ * @{
+ */
+#define INTC_EVT0 INTC_EVTER_EVTE0
+#define INTC_EVT1 INTC_EVTER_EVTE1
+#define INTC_EVT2 INTC_EVTER_EVTE2
+#define INTC_EVT3 INTC_EVTER_EVTE3
+#define INTC_EVT4 INTC_EVTER_EVTE4
+#define INTC_EVT5 INTC_EVTER_EVTE5
+#define INTC_EVT6 INTC_EVTER_EVTE6
+#define INTC_EVT7 INTC_EVTER_EVTE7
+#define INTC_EVT8 INTC_EVTER_EVTE8
+#define INTC_EVT9 INTC_EVTER_EVTE9
+#define INTC_EVT10 INTC_EVTER_EVTE10
+#define INTC_EVT11 INTC_EVTER_EVTE11
+#define INTC_EVT12 INTC_EVTER_EVTE12
+#define INTC_EVT13 INTC_EVTER_EVTE13
+#define INTC_EVT14 INTC_EVTER_EVTE14
+#define INTC_EVT15 INTC_EVTER_EVTE15
+#define INTC_EVT16 INTC_EVTER_EVTE16
+#define INTC_EVT17 INTC_EVTER_EVTE17
+#define INTC_EVT18 INTC_EVTER_EVTE18
+#define INTC_EVT19 INTC_EVTER_EVTE19
+#define INTC_EVT20 INTC_EVTER_EVTE20
+#define INTC_EVT21 INTC_EVTER_EVTE21
+#define INTC_EVT22 INTC_EVTER_EVTE22
+#define INTC_EVT23 INTC_EVTER_EVTE23
+#define INTC_EVT24 INTC_EVTER_EVTE24
+#define INTC_EVT25 INTC_EVTER_EVTE25
+#define INTC_EVT26 INTC_EVTER_EVTE26
+#define INTC_EVT27 INTC_EVTER_EVTE27
+#define INTC_EVT28 INTC_EVTER_EVTE28
+#define INTC_EVT29 INTC_EVTER_EVTE29
+#define INTC_EVT30 INTC_EVTER_EVTE30
+#define INTC_EVT31 INTC_EVTER_EVTE31
+#define INTC_EVT_ALL (0xFFFFFFFFUL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SWINT_Channel_Sel Software Interrupt Channel Selection
+ * @{
+ */
+#define SWINT_CH00 INTC_SWIER_SWIE0
+#define SWINT_CH01 INTC_SWIER_SWIE1
+#define SWINT_CH02 INTC_SWIER_SWIE2
+#define SWINT_CH03 INTC_SWIER_SWIE3
+#define SWINT_CH04 INTC_SWIER_SWIE4
+#define SWINT_CH05 INTC_SWIER_SWIE5
+#define SWINT_CH06 INTC_SWIER_SWIE6
+#define SWINT_CH07 INTC_SWIER_SWIE7
+#define SWINT_CH08 INTC_SWIER_SWIE8
+#define SWINT_CH09 INTC_SWIER_SWIE9
+#define SWINT_CH10 INTC_SWIER_SWIE10
+#define SWINT_CH11 INTC_SWIER_SWIE11
+#define SWINT_CH12 INTC_SWIER_SWIE12
+#define SWINT_CH13 INTC_SWIER_SWIE13
+#define SWINT_CH14 INTC_SWIER_SWIE14
+#define SWINT_CH15 INTC_SWIER_SWIE15
+#define SWINT_CH16 INTC_SWIER_SWIE16
+#define SWINT_CH17 INTC_SWIER_SWIE17
+#define SWINT_CH18 INTC_SWIER_SWIE18
+#define SWINT_CH19 INTC_SWIER_SWIE19
+#define SWINT_CH20 INTC_SWIER_SWIE20
+#define SWINT_CH21 INTC_SWIER_SWIE21
+#define SWINT_CH22 INTC_SWIER_SWIE22
+#define SWINT_CH23 INTC_SWIER_SWIE23
+#define SWINT_CH24 INTC_SWIER_SWIE24
+#define SWINT_CH25 INTC_SWIER_SWIE25
+#define SWINT_CH26 INTC_SWIER_SWIE26
+#define SWINT_CH27 INTC_SWIER_SWIE27
+#define SWINT_CH28 INTC_SWIER_SWIE28
+#define SWINT_CH29 INTC_SWIER_SWIE29
+#define SWINT_CH30 INTC_SWIER_SWIE30
+#define SWINT_CH31 INTC_SWIER_SWIE31
+#define SWINT_ALL (0xFFFFFFFFUL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EXTINT_FilterClock_Sel External Interrupt Filter A Function Selection
+ * @{
+ */
+#define EXTINT_FILTER_OFF (0UL)
+#define EXTINT_FILTER_ON INTC_EIRQCR_EFEN
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup NMI_EXTINT_FilterBClock_Sel External Interrupt Filter B Function Selection
+ * @{
+ */
+#define NMI_EXTINT_FILTER_B_OFF (0UL)
+#define NMI_EXTINT_FILTER_B_ON INTC_EIRQCR_NOCEN
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EXTINT_FilterClock_Div External Interrupt Filter A Sampling Clock Division Selection
+ * @{
+ */
+#define EXTINT_FCLK_DIV1 (0UL)
+#define EXTINT_FCLK_DIV8 (INTC_EIRQCR_EISMPCLK_0)
+#define EXTINT_FCLK_DIV32 (INTC_EIRQCR_EISMPCLK_1)
+#define EXTINT_FCLK_DIV64 (INTC_EIRQCR_EISMPCLK)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup NMI_EXTINT_FilterBTim_Sel External Interrupt Filter B Time Selection
+ * @{
+ */
+#define NMI_EXTINT_FCLK_B_500NS (0UL)
+#define NMI_EXTINT_FCLK_B_1US (INTC_EIRQCR_NOCSEL_0)
+#define NMI_EXTINT_FCLK_B_2US (INTC_EIRQCR_NOCSEL_1)
+#define NMI_EXTINT_FCLK_B_4US (INTC_EIRQCR_NOCSEL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EXTINT_Trigger_Sel External Interrupt Trigger Edge Selection
+ * @{
+ */
+#define EXTINT_TRIG_FALLING (0UL)
+#define EXTINT_TRIG_RISING INTC_EIRQCR_EIRQTRG_0
+#define EXTINT_TRIG_BOTH INTC_EIRQCR_EIRQTRG_1
+#define EXTINT_TRIG_LOW INTC_EIRQCR_EIRQTRG
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup INTC_Stop_Wakeup_Source_Sel Stop Mode Wakeup Source Selection
+ * @{
+ */
+#define INTC_STOP_WKUP_EXTINT_CH0 INTC_WKEN_EIRQWKEN_0
+#define INTC_STOP_WKUP_EXTINT_CH1 INTC_WKEN_EIRQWKEN_1
+#define INTC_STOP_WKUP_EXTINT_CH2 INTC_WKEN_EIRQWKEN_2
+#define INTC_STOP_WKUP_EXTINT_CH3 INTC_WKEN_EIRQWKEN_3
+#define INTC_STOP_WKUP_EXTINT_CH4 INTC_WKEN_EIRQWKEN_4
+#define INTC_STOP_WKUP_EXTINT_CH5 INTC_WKEN_EIRQWKEN_5
+#define INTC_STOP_WKUP_EXTINT_CH6 INTC_WKEN_EIRQWKEN_6
+#define INTC_STOP_WKUP_EXTINT_CH7 INTC_WKEN_EIRQWKEN_7
+#define INTC_STOP_WKUP_EXTINT_CH8 INTC_WKEN_EIRQWKEN_8
+#define INTC_STOP_WKUP_EXTINT_CH9 INTC_WKEN_EIRQWKEN_9
+#define INTC_STOP_WKUP_EXTINT_CH10 INTC_WKEN_EIRQWKEN_10
+#define INTC_STOP_WKUP_EXTINT_CH11 INTC_WKEN_EIRQWKEN_11
+#define INTC_STOP_WKUP_EXTINT_CH12 INTC_WKEN_EIRQWKEN_12
+#define INTC_STOP_WKUP_EXTINT_CH13 INTC_WKEN_EIRQWKEN_13
+#define INTC_STOP_WKUP_EXTINT_CH14 INTC_WKEN_EIRQWKEN_14
+#define INTC_STOP_WKUP_EXTINT_CH15 INTC_WKEN_EIRQWKEN_15
+#define INTC_STOP_WKUP_SWDT INTC_WKEN_SWDTWKEN
+#define INTC_STOP_WKUP_LVD1 INTC_WKEN_PVD1WKEN
+#define INTC_STOP_WKUP_LVD2 INTC_WKEN_PVD2WKEN
+#define INTC_STOP_WKUP_CMP1 INTC_WKEN_CMP1WKEN
+#define INTC_STOP_WKUP_WKTM INTC_WKEN_WKTMWKEN
+#define INTC_STOP_WKUP_RTC_ALM INTC_WKEN_RTCALMWKEN
+#define INTC_STOP_WKUP_RTC_PRD INTC_WKEN_RTCPRDWKEN
+#define INTC_STOP_WKUP_TMR0_CMP INTC_WKEN_TMR0CMPWKEN
+#define INTC_STOP_WKUP_TMR2_CMP INTC_WKEN_TMR2CMPWKEN
+#define INTC_STOP_WKUP_TMR2_OVF INTC_WKEN_TMR2OVFWKEN
+#define INTC_STOP_WKUP_USART1_RX INTC_WKEN_RXWKEN
+#define INTC_STOP_WKUP_USBFS INTC_WKN_USFWKEN
+#define INTC_STOP_WKUP_CMP2 INTC_WKEN_CMP2WKEN
+#define INTC_STOP_WKUP_CMP3 INTC_WKEN_CMP3WKEN
+#define INTC_STOP_WKUP_CMP4 INTC_WKEN_CMP4WKEN
+#define INTC_WUPEN_ALL (INTC_WKEN_EIRQWKEN | INTC_WKEN_SWDTWKEN | \
+ INTC_WKEN_PVD1WKEN | INTC_WKEN_PVD2WKEN | \
+ INTC_WKEN_CMP1WKEN | INTC_WKEN_WKTMWKEN | \
+ INTC_WKEN_RTCALMWKEN | INTC_WKEN_RTCPRDWKEN | \
+ INTC_WKEN_TMR0CMPWKEN | INTC_WKEN_TMR2CMPWKEN | \
+ INTC_WKEN_TMR2OVFWKEN | INTC_WKEN_RXWKEN | \
+ INTC_WKEN_USFWKEN | INTC_WKEN_CMP2WKEN | \
+ INTC_WKEN_CMP3WKEN | INTC_WKEN_CMP4WKEN)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup INTC_Global_Functions
+ * @{
+ */
+
+int32_t INTC_IrqSignIn(const stc_irq_signin_config_t *pstcIrqSignConfig);
+int32_t INTC_IrqSignOut(IRQn_Type enIRQn);
+void INTC_WakeupSrcCmd(uint32_t u32WakeupSrc, en_functional_state_t enNewState);
+void INTC_EventCmd(uint32_t u32Event, en_functional_state_t enNewState);
+void INTC_IntCmd(uint32_t u32Int, en_functional_state_t enNewState);
+void INTC_SWIntInit(uint32_t u32Ch, const func_ptr_t pfnCallback, uint32_t u32Priority);
+void INTC_SWIntCmd(uint32_t u32SWInt, en_functional_state_t enNewState);
+
+int32_t NMI_Init(const stc_nmi_init_t *pstcNmiInit);
+int32_t NMI_StructInit(stc_nmi_init_t *pstcNmiInit);
+en_flag_status_t NMI_GetNmiStatus(uint32_t u32Src);
+void NMI_NmiSrcCmd(uint32_t u32Src, en_functional_state_t enNewState);
+void NMI_ClearNmiStatus(uint32_t u32Src);
+
+int32_t EXTINT_Init(uint32_t u32Ch, const stc_extint_init_t *pstcExtIntInit);
+int32_t EXTINT_StructInit(stc_extint_init_t *pstcExtIntInit);
+en_flag_status_t EXTINT_GetExtIntStatus(uint32_t u32ExtIntCh);
+void EXTINT_ClearExtIntStatus(uint32_t u32ExtIntCh);
+void INTC_IntSrcCmd(en_int_src_t enIntSrc, en_functional_state_t enNewState);
+en_functional_state_t INTC_GetIntSrcState(en_int_src_t enIntSrc);
+
+void IRQ000_Handler(void);
+void IRQ001_Handler(void);
+void IRQ002_Handler(void);
+void IRQ003_Handler(void);
+void IRQ004_Handler(void);
+void IRQ005_Handler(void);
+void IRQ006_Handler(void);
+void IRQ007_Handler(void);
+
+void IRQ008_Handler(void);
+void IRQ009_Handler(void);
+void IRQ010_Handler(void);
+void IRQ011_Handler(void);
+void IRQ012_Handler(void);
+void IRQ013_Handler(void);
+void IRQ014_Handler(void);
+void IRQ015_Handler(void);
+
+/**
+ * @}
+ */
+
+#endif /* LL_INTERRUPTS_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_INTERRUPTS_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_keyscan.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_keyscan.h
new file mode 100644
index 0000000000..8bb8a087d9
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_keyscan.h
@@ -0,0 +1,241 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_keyscan.h
+ * @brief This file contains all the functions prototypes of the KEYSCAN driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Add function KEYSCAN_DeInit
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_KEYSCAN_H__
+#define __HC32_LL_KEYSCAN_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_KEYSCAN
+ * @{
+ */
+
+#if (LL_KEYSCAN_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup KEYSCAN_Global_Types KEYSCAN Global Types
+ * @{
+ */
+
+/**
+ * @brief KEYSCAN configuration
+ */
+typedef struct {
+ uint32_t u32HizCycle; /*!< Specifies the KEYSCAN Hiz cycles.
+ This parameter can be a value of @ref KEYSCAN_Hiz_Cycle_Sel */
+
+ uint32_t u32LowCycle; /*!< Specifies the KEYSCAN low cycles.
+ This parameter can be a value of @ref KEYSCAN_Low_Cycle_Sel */
+
+ uint32_t u32KeyClock; /*!< Specifies the KEYSCAN low cycles.
+ This parameter can be a value of @ref KEYSCAN_Clock_Sel */
+
+ uint32_t u32KeyOut; /*!< Specifies the KEYSCAN low cycles.
+ This parameter can be a value of @ref KEYSCAN_Keyout_Sel */
+
+ uint32_t u32KeyIn; /*!< Specifies the KEYSCAN low cycles.
+ This parameter can be a value of @ref KEYSCAN_Keyin_Sel */
+} stc_keyscan_init_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup KEYSCAN_Global_Macros KEYSCAN Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup KEYSCAN_Hiz_Cycle_Sel KEYSCAN Hiz cycles during low ouput selection
+ * @{
+ */
+#define KEYSCAN_HIZ_CYCLE_4 (0x00UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 4 cycles during low ouput */
+#define KEYSCAN_HIZ_CYCLE_8 (0x01UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 8 cycles during low ouput */
+#define KEYSCAN_HIZ_CYCLE_16 (0x02UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 16 cycles during low ouput */
+#define KEYSCAN_HIZ_CYCLE_32 (0x03UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 32 cycles during low ouput */
+#define KEYSCAN_HIZ_CYCLE_64 (0x04UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 64 cycles during low ouput */
+#define KEYSCAN_HIZ_CYCLE_256 (0x05UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 256 cycles during low ouput */
+#define KEYSCAN_HIZ_CYCLE_512 (0x06UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 512 cycles during low ouput */
+#define KEYSCAN_HIZ_CYCLE_1024 (0x07UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 1024 cycles during low ouput */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup KEYSCAN_Low_Cycle_Sel KEYSCAN low level output cycles selection
+ * @{
+ */
+#define KEYSCAN_LOW_CYCLE_4 (0x02UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^2=4 cycles */
+#define KEYSCAN_LOW_CYCLE_8 (0x03UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^3=8 cycles */
+#define KEYSCAN_LOW_CYCLE_16 (0x04UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^4=16 cycles */
+#define KEYSCAN_LOW_CYCLE_32 (0x05UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^5=32 cycles */
+#define KEYSCAN_LOW_CYCLE_64 (0x06UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^6=64 cycles */
+#define KEYSCAN_LOW_CYCLE_128 (0x07UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^7=128 cycles */
+#define KEYSCAN_LOW_CYCLE_256 (0x08UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^8=256 cycles */
+#define KEYSCAN_LOW_CYCLE_512 (0x09UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^9=512 cycles */
+#define KEYSCAN_LOW_CYCLE_1K (0x0AUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^10=1K cycles */
+#define KEYSCAN_LOW_CYCLE_2K (0x0BUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^11=2K cycles */
+#define KEYSCAN_LOW_CYCLE_4K (0x0CUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^12=4K cycles */
+#define KEYSCAN_LOW_CYCLE_8K (0x0DUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^13=8K cycles */
+#define KEYSCAN_LOW_CYCLE_16K (0x0EUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^14=16K cycles */
+#define KEYSCAN_LOW_CYCLE_32K (0x0FUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^15=32K cycles */
+#define KEYSCAN_LOW_CYCLE_64K (0x10UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^16=64K cycles */
+#define KEYSCAN_LOW_CYCLE_128K (0x11UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^17=128K cycles */
+#define KEYSCAN_LOW_CYCLE_256K (0x12UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^18=256K cycles */
+#define KEYSCAN_LOW_CYCLE_512K (0x13UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^19=512K cycles */
+#define KEYSCAN_LOW_CYCLE_1M (0x14UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^20=1M cycles */
+#define KEYSCAN_LOW_CYCLE_2M (0x15UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^21=2M cycles */
+#define KEYSCAN_LOW_CYCLE_4M (0x16UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^22=4M cycles */
+#define KEYSCAN_LOW_CYCLE_8M (0x17UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^23=8M cycles */
+#define KEYSCAN_LOW_CYCLE_16M (0x18UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^24=16M cycles */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup KEYSCAN_Clock_Sel KEYSCAN scan clock selection
+ * @{
+ */
+#define KEYSCAN_CLK_HCLK (0x00UL) /*!< Use as HCLK KEYSCAN clock */
+#define KEYSCAN_CLK_LRC (KEYSCAN_SCR_CKSEL_0) /*!< Use as LRC KEYSCAN clock */
+#define KEYSCAN_CLK_XTAL32 (KEYSCAN_SCR_CKSEL_1) /*!< Use as XTAL32 KEYSCAN clock */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup KEYSCAN_Keyout_Sel KEYSCAN keyout pins selection
+ * @{
+ */
+#define KEYSCAN_OUT_0T1 (0x01UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 1 are selected */
+#define KEYSCAN_OUT_0T2 (0x02UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 2 are selected */
+#define KEYSCAN_OUT_0T3 (0x03UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 3 are selected */
+#define KEYSCAN_OUT_0T4 (0x04UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 4 are selected */
+#define KEYSCAN_OUT_0T5 (0x05UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 5 are selected */
+#define KEYSCAN_OUT_0T6 (0x06UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 6 are selected */
+#define KEYSCAN_OUT_0T7 (0x07UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 7 are selected */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup KEYSCAN_Keyin_Sel KEYSCAN keyin pins selection
+ * @{
+ */
+#define KEYSCAN_IN_0 (1UL << 0U) /*!< KEYIN(EIRQ) 0 is selected */
+#define KEYSCAN_IN_1 (1UL << 1U) /*!< KEYIN(EIRQ) 1 is selected */
+#define KEYSCAN_IN_2 (1UL << 2U) /*!< KEYIN(EIRQ) 2 is selected */
+#define KEYSCAN_IN_3 (1UL << 3U) /*!< KEYIN(EIRQ) 3 is selected */
+#define KEYSCAN_IN_4 (1UL << 4U) /*!< KEYIN(EIRQ) 4 is selected */
+#define KEYSCAN_IN_5 (1UL << 5U) /*!< KEYIN(EIRQ) 5 is selected */
+#define KEYSCAN_IN_6 (1UL << 6U) /*!< KEYIN(EIRQ) 6 is selected */
+#define KEYSCAN_IN_7 (1UL << 7U) /*!< KEYIN(EIRQ) 7 is selected */
+#define KEYSCAN_IN_8 (1UL << 8U) /*!< KEYIN(EIRQ) 8 is selected */
+#define KEYSCAN_IN_9 (1UL << 9U) /*!< KEYIN(EIRQ) 9 is selected */
+#define KEYSCAN_IN_10 (1UL << 10U) /*!< KEYIN(EIRQ) 10 is selected */
+#define KEYSCAN_IN_11 (1UL << 11U) /*!< KEYIN(EIRQ) 11 is selected */
+#define KEYSCAN_IN_12 (1UL << 12U) /*!< KEYIN(EIRQ) 12 is selected */
+#define KEYSCAN_IN_13 (1UL << 13U) /*!< KEYIN(EIRQ) 13 is selected */
+#define KEYSCAN_IN_14 (1UL << 14U) /*!< KEYIN(EIRQ) 14 is selected */
+#define KEYSCAN_IN_15 (1UL << 15U) /*!< KEYIN(EIRQ) 15 is selected */
+#define KEYSCAN_IN_ALL (KEYSCAN_SCR_KEYINSEL) /*!< KEYIN(EIRQ) mask */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup KEYSCAN_Global_Functions
+ * @{
+ */
+/**
+ * @brief Get KEYOUT index.
+ * @param None
+ * @retval uint32_t: KEYOUT index 0~7.
+ */
+__STATIC_INLINE uint32_t KEYSCAN_GetKeyoutIdx(void)
+{
+ return READ_REG32_BIT(CM_KEYSCAN->SSR, KEYSCAN_SSR_INDEX);
+}
+
+int32_t KEYSCAN_StructInit(stc_keyscan_init_t *pstcKeyscanInit);
+int32_t KEYSCAN_Init(const stc_keyscan_init_t *pstcKeyscanInit);
+void KEYSCAN_Cmd(en_functional_state_t enNewState);
+int32_t KEYSCAN_DeInit(void);
+
+/**
+ * @}
+ */
+
+#endif /* LL_KEYSCAN_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_KEYSCAN_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_mau.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_mau.h
new file mode 100644
index 0000000000..aad622e431
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_mau.h
@@ -0,0 +1,124 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_mau.h
+ * @brief This file contains all the functions prototypes of the MAU driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Add API MAU_DeInit()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_MAU_H__
+#define __HC32_LL_MAU_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_MAU
+ * @{
+ */
+
+#if (LL_MAU_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/**
+ * @defgroup MAU_Global_Macros MAU Global Macros
+ * @{
+ */
+
+#define MAU_SQRT_TIMEOUT (HCLK_VALUE / 10000UL)/* About 1mS timeout */
+#define MAU_SQRT_OUTPUT_LSHIFT_MAX (16U)
+
+#define MAU_SIN_Q15_SCALAR (0x8000UL)
+#define MAU_SIN_ANGIDX_TOTAL (0x1000UL)
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+
+/**
+ * @addtogroup MAU_Global_Functions
+ * @{
+ */
+
+void MAU_SqrtInit(CM_MAU_TypeDef *MAUx, uint8_t u8ShiftNum, en_functional_state_t enNewState);
+void MAU_SqrtDeInit(CM_MAU_TypeDef *MAUx);
+
+void MAU_SqrtResultLShiftConfig(CM_MAU_TypeDef *MAUx, uint8_t u8ShiftNum);
+void MAU_SqrtIntCmd(CM_MAU_TypeDef *MAUx, en_functional_state_t enNewState);
+void MAU_SqrtWriteData(CM_MAU_TypeDef *MAUx, uint32_t u32Radicand);
+en_flag_status_t MAU_SqrtGetStatus(const CM_MAU_TypeDef *MAUx);
+uint32_t MAU_SqrtReadData(const CM_MAU_TypeDef *MAUx);
+void MAU_SqrtStart(CM_MAU_TypeDef *MAUx);
+
+int32_t MAU_Sqrt(CM_MAU_TypeDef *MAUx, uint32_t u32Radicand, uint32_t *pu32Result);
+
+int16_t MAU_Sin(CM_MAU_TypeDef *MAUx, uint16_t u16AngleIdx);
+
+int32_t MAU_DeInit(void);
+
+/**
+ * @}
+ */
+
+#endif /* LL_MAU_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_MAU_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_mdio.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_mdio.h
new file mode 100644
index 0000000000..32c80a564c
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_mdio.h
@@ -0,0 +1,269 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_mdio.h
+ * @brief This file contains all the functions prototypes of the MDIO driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_MDIO_H__
+#define __HC32_LL_MDIO_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_MDIO
+ * @{
+ */
+
+#if (LL_MDIO_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup MDIO_Global_Types MDIO Global Types
+ * @{
+ */
+
+/**
+ * @brief Structure definition of MDIO initialization.
+ * @note The parameter 'u32PhyAddr' is valid when the 'u32PhyAddrMode' is equal to MDIO_PHY_ADDR_MD_SW.
+ */
+typedef struct {
+ uint32_t u32PhyAddrBitWidth; /*!< Specifies the bit width of the PHY address.
+ This parameter can be a value of @ref MDIO_PHY_Addr_Bit_Width */
+ uint32_t u32PhyAddrMode; /*!< Specifies the mode of the PHY address.
+ This parameter can be a value of @ref MDIO_PHY_Addr_Mode */
+ uint32_t u32PhyAddr; /*!< Specifies the value of the PHY address.
+ This parameter can be a number between 0UL and 0x1FUL */
+ uint32_t u32DevAddrMask; /*!< Specifies the mask of the device address.
+ This parameter can be a value of @ref MDIO_DEV_Addr_Mask */
+ uint32_t u32DevAddr; /*!< Specifies the value of the device address.
+ This parameter can be a number between 0UL and 0x1FUL */
+} stc_mdio_init_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup MDIO_Global_Macros MDIO Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup MDIO_PHY_Addr_Bit_Width MDIO PHY Addr Bit Width
+ * @{
+ */
+#define MDIO_PHY_ADDR_5BIT (0UL) /* Use 5bits address */
+#define MDIO_PHY_ADDR_3BIT (MDIO_MDCON_MD_PHYB) /* Use 3bits address */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup MDIO_MDC_Detect_Level MDIO MDC Detect Level
+ * @{
+ */
+#define MDIO_MDC_DETECT_LVL_LOW (0UL) /*!< Detect low level */
+#define MDIO_MDC_DETECT_LVL_HIGH (MDIO_MDCON1_SEL_EDGE) /*!< Detect high level */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup MDIO_DEV_Addr_Mask MDIO Device Addr Mask
+ * @{
+ */
+#define MDIO_DEV_ADDR_MASK_DISABLE (0UL) /*!< Don't mask the result of the device address */
+#define MDIO_DEV_ADDR_MASK_ENABLE (MDIO_MDCON1_MD_MSDEV) /*!< Masking the result of the device address */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup MDIO_PHY_Addr_Mode MDIO PHY Address Mode
+ * @{
+ */
+#define MDIO_PHY_ADDR_MD_HW (0UL) /*!< Hardware address mode */
+#define MDIO_PHY_ADDR_MD_SW (MDIO_MDPHY_MD_PHYSEL) /*!< Software address mode */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup MDIO_RX_OPERA_CODE MDIO Receive Operation Code
+ * @{
+ */
+#define MDIO_RX_OPERA_ADDR_FRAME (0UL) /*!< Address frame */
+#define MDIO_RX_OPERA_WR_FRAME (MDIO_MDFRM_MD_ROP_0) /*!< Write frame */
+#define MDIO_RX_OPERA_RD_INC_FRAME (MDIO_MDFRM_MD_ROP_1) /*!< Address increase frame after reading */
+#define MDIO_RX_OPERA_RD_FRAME (MDIO_MDFRM_MD_ROP) /*!< Read frame */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup MDIO_RX_Convert_Bit MDIO Receive Convert Bit
+ * @{
+ */
+#define MDIO_RX_CONV_WR (MDIO_MDFRM_MD_RTA_1) /*!< Write operation */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup MDIO_Interrupt MDIO Interrupt
+ * @{
+ */
+#define MDIO_INT_WR_FRAME_MATCH (MDIO_MDIEN_MD_WRFIE) /*WP, MPU_REG_UNLOCK_KEY);
+}
+
+/**
+ * @brief MPU write protect lock.
+ * @param None
+ * @retval None
+ */
+__STATIC_INLINE void MPU_REG_Lock(void)
+{
+ WRITE_REG32(CM_MPU->WP, MPU_REG_LOCK_KEY);
+}
+
+void MPU_REG_Unlock(void);
+void MPU_REG_Lock(void);
+
+void MPU_DeInit(void);
+int32_t MPU_Init(const stc_mpu_init_t *pstcMpuInit);
+int32_t MPU_StructInit(stc_mpu_init_t *pstcMpuInit);
+int32_t MPU_UnitInit(uint32_t u32Unit, stc_mpu_unit_init_t *pstcUnitInit);
+int32_t MPU_UnitStructInit(stc_mpu_unit_init_t *pstcUnitInit);
+void MPU_SetExceptionType(uint32_t u32Unit, uint32_t u32Type);
+void MPU_BackgroundWriteCmd(uint32_t u32Unit, en_functional_state_t enNewState);
+void MPU_BackgroundReadCmd(uint32_t u32Unit, en_functional_state_t enNewState);
+void MPU_UnitCmd(uint32_t u32Unit, en_functional_state_t enNewState);
+en_flag_status_t MPU_GetStatus(uint32_t u32Flag);
+void MPU_ClearStatus(uint32_t u32Flag);
+
+int32_t MPU_RegionInit(uint32_t u32Num, const stc_mpu_region_init_t *pstcRegionInit);
+int32_t MPU_RegionStructInit(stc_mpu_region_init_t *pstcRegionInit);
+void MPU_SetRegionBaseAddr(uint32_t u32Num, uint32_t u32Addr);
+void MPU_SetRegionSize(uint32_t u32Num, uint32_t u32Size);
+void MPU_RegionWriteCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState);
+void MPU_RegionReadCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState);
+void MPU_RegionCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState);
+
+int32_t MPU_SPInit(uint32_t u32Unit, const stc_mpu_sp_init_t *pstcSpInit);
+int32_t MPU_SPStructInit(stc_mpu_sp_init_t *pstcSpInit);
+void MPU_SetSPStartAddr(uint32_t u32Unit, uint32_t u32Addr);
+void MPU_SetSPSize(uint32_t u32Unit, uint32_t u32Size);
+void MPU_SetSPExceptionType(uint32_t u32Unit, uint32_t u32Type);
+void MPU_SPCmd(uint32_t u32Unit, en_functional_state_t enNewState);
+
+void MPU_IP_SetExceptionType(uint32_t u32Type);
+void MPU_IP_WriteCmd(uint32_t u32Periph, en_functional_state_t enNewState);
+void MPU_IP_ReadCmd(uint32_t u32Periph, en_functional_state_t enNewState);
+
+/**
+ * @}
+ */
+
+#endif /* LL_MPU_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_MPU_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_ots.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_ots.h
new file mode 100644
index 0000000000..40c83305fa
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_ots.h
@@ -0,0 +1,204 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_ots.h
+ * @brief This file contains all the functions prototypes of the OTS driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Modify typo
+ Modify API OTS_DeInit()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_OTS_H__
+#define __HC32_LL_OTS_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_OTS
+ * @{
+ */
+
+#if (LL_OTS_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup OTS_Global_Types OTS Global Types
+ * @{
+ */
+
+/**
+ * @brief Conditions of default parameters(slope K and offset M).
+ * @note Parameter 'u8T1' CANNOT equal to parameter 'u8T2'.
+ */
+typedef struct {
+ uint16_t u16ClockFreq; /*!< Frequency(MHz) of clock sources that OTS is going to use. */
+ uint8_t u8T1; /*!< Temperature value T1 for the default parameter.
+ This parameter can be a value of @ref OTS_Param_Temp_Cond */
+ uint8_t u8T2; /*!< Temperature value T2 for the default parameter.
+ This parameter can be a value of @ref OTS_Param_Temp_Cond */
+} stc_para_temp_cond_t;
+
+/**
+ * @brief OTS initialization structure.
+ */
+typedef struct {
+ uint16_t u16ClockSrc; /*!< Specifies clock source for OTS.
+ This parameter can be a value of @ref OTS_Clock_Source */
+ uint16_t u16AutoOffEn; /*!< Enable or disable OTS automatic-off(after sampled temperature).
+ This parameter can be a value of @ref OTS_Auto_Off_En */
+ float32_t f32SlopeK; /*!< K: Temperature slope (calculated by calibration experiment).
+ If you want to use the default parameters(slope K and offset M),
+ specify both 'f32SlopeK' and 'f32OffsetM' as ZERO. */
+ float32_t f32OffsetM; /*!< M: Temperature offset (calculated by calibration experiment).
+ If you want to use the default parameters(slope K and offset M),
+ specify both 'f32SlopeK' and 'f32OffsetM' as ZERO. */
+ stc_para_temp_cond_t stcParaCond; /*!< Specifies the temperature conditions of the default parameters(slope K and offset M) if you
+ want to use the default parameters. */
+} stc_ots_init_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup OTS_Global_Macros OTS Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup OTS_Clock_Source OTS Clock Source
+ * @{
+ */
+#define OTS_CLK_XTAL (0x0U) /*!< Select XTAL as OTS clock. */
+#define OTS_CLK_HRC (OTS_CTL_OTSCK) /*!< Select HRC as OTS clock */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup OTS_Auto_Off_En OTS Automatic Off Function Control
+ * @{
+ */
+#define OTS_AUTO_OFF_DISABLE (0x0U) /*!< OTS automatically turned off when sampled done. */
+#define OTS_AUTO_OFF_ENABLE (OTS_CTL_TSSTP) /*!< OTS is still on when sampled done. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup OTS_Param_Temp_Cond OTS Parameter Temperature Condition
+ * @{
+ */
+#define OTS_PARAM_TEMP_COND_TN40 (0U) /*!< -40 degrees Celsius. */
+#define OTS_PARAM_TEMP_COND_T25 (1U) /*!< 25 degrees Celsius. */
+#define OTS_PARAM_TEMP_COND_T125 (2U) /*!< 125 degrees Celsius. */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup OTS_Global_Functions
+ * @{
+ */
+
+/**
+ * @brief Start OTS.
+ * @param None
+ * @retval None
+ */
+__STATIC_INLINE void OTS_Start(void)
+{
+ WRITE_REG32(bCM_OTS->CTL_b.OTSST, 1U);
+}
+
+/**
+ * @brief Stop OTS.
+ * @param None
+ * @retval None
+ */
+__STATIC_INLINE void OTS_Stop(void)
+{
+ WRITE_REG32(bCM_OTS->CTL_b.OTSST, 0U);
+}
+
+int32_t OTS_Init(const stc_ots_init_t *pstcOTSInit);
+int32_t OTS_StructInit(stc_ots_init_t *pstcOTSInit);
+int32_t OTS_DeInit(void);
+
+int32_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout);
+
+void OTS_IntCmd(en_functional_state_t enNewState);
+
+int32_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2,
+ uint16_t *pu16Ecr, float32_t *pf32A,
+ uint32_t u32Timeout);
+
+float32_t OTS_CalculateTemp(void);
+
+/**
+ * @}
+ */
+
+#endif /* LL_OTS_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_OTS_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_pla.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_pla.h
new file mode 100644
index 0000000000..8ec59c0c8d
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_pla.h
@@ -0,0 +1,214 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_pla.h
+ * @brief This file contains all the functions prototypes of the PLA driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-09-30 CDT Modify API for Reference Manual Rev1.0
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_PLA_H__
+#define __HC32_LL_PLA_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_PLA
+ * @{
+ */
+
+#if (LL_PLA_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup PLA_Global_Types PLA Global Types
+ * @{
+ */
+
+/**
+ * @brief PLA Init structure definition
+ */
+typedef struct {
+ uint32_t u32Mux0Src; /*!< Specifies the input signal source of MUX0.
+ This parameter can be a value of @ref PLA_MUX_Source */
+ uint32_t u32Mux1Src; /*!< Specifies the input signal source of MUX1.
+ This parameter can be a value of @ref PLA_MUX_Source */
+ uint32_t u32CombLogic; /*!< Specifies the combinatorial logic for input signals.
+ This parameter can be a number between 0UL and 0xFFUL */
+ uint32_t u32OutputSrc; /*!< Specifies the output signal source of PLA.
+ This parameter can be a value of @ref PLA_Output_Source */
+} stc_pla_init_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup PLA_Global_Macros PLA Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup PLA_Unit PLA Unit
+ * @{
+ */
+#define PLA_UNIT0 (0x0001UL)
+#define PLA_UNIT1 (0x0002UL)
+#define PLA_UNIT2 (0x0004UL)
+#define PLA_UNIT3 (0x0008UL)
+#define PLA_UNIT4 (0x0010UL)
+#define PLA_UNIT5 (0x0020UL)
+#define PLA_UNIT6 (0x0040UL)
+#define PLA_UNIT7 (0x0080UL)
+#define PLA_UNIT8 (0x0100UL)
+#define PLA_UNIT9 (0x0200UL)
+#define PLA_UNIT10 (0x0400UL)
+#define PLA_UNIT11 (0x0800UL)
+#define PLA_UNIT12 (0x1000UL)
+#define PLA_UNIT13 (0x2000UL)
+#define PLA_UNIT14 (0x4000UL)
+#define PLA_UNIT15 (0x8000UL)
+#define PLA_UNIT_ALL (0xFFFFUL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PLA_MUX_Channel PLA MUX Channel
+ * @{
+ */
+#define PLA_MUX_CH0 (1UL)
+#define PLA_MUX_CH1 (0UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PLA_MUX_Source PLA MUX Source
+ * @{
+ */
+#define PLA_MUX_SRC_SIGNAL0 (0U)
+#define PLA_MUX_SRC_SIGNAL1 (1U)
+#define PLA_MUX_SRC_SIGNAL2 (2U)
+#define PLA_MUX_SRC_SIGNAL3 (3U)
+#define PLA_MUX_SRC_SIGNAL4 (4U)
+#define PLA_MUX_SRC_SIGNAL5 (5U)
+#define PLA_MUX_SRC_SIGNAL6 (6U)
+#define PLA_MUX_SRC_SIGNAL7 (7U)
+#define PLA_MUX_SRC_SIGNAL8 (8U)
+#define PLA_MUX_SRC_SIGNAL9 (9U)
+#define PLA_MUX_SRC_SIGNAL10 (10U)
+#define PLA_MUX_SRC_SIGNAL11 (11U)
+#define PLA_MUX_SRC_SIGNAL12 (12U)
+#define PLA_MUX_SRC_SIGNAL13 (13U)
+#define PLA_MUX_SRC_SIGNAL14 (14U)
+#define PLA_MUX_SRC_SIGNAL15 (15U)
+#define PLA_MUX_SRC_SIGNAL16 (16U)
+#define PLA_MUX_SRC_SIGNAL17 (17U)
+#define PLA_MUX_SRC_SIGNAL18 (18U)
+#define PLA_MUX_SRC_SIGNAL19 (19U)
+#define PLA_MUX_SRC_SIGNAL20 (20U)
+#define PLA_MUX_SRC_SIGNAL21 (21U)
+#define PLA_MUX_SRC_SIGNAL22 (22U)
+#define PLA_MUX_SRC_SIGNAL23 (23U)
+#define PLA_MUX_SRC_SIGNAL24 (24U)
+#define PLA_MUX_SRC_SIGNAL25 (25U)
+#define PLA_MUX_SRC_SIGNAL26 (26U)
+#define PLA_MUX_SRC_SIGNAL27 (27U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PLA_Output_Source PLA Output Source
+ * @{
+ */
+#define PLA_OUTPUT_SRC_NONE (0UL) /*!< The LUT result isn't the output of PLA */
+#define PLA_OUTPUT_SRC_LUT (PLA_CTL_OSEL) /*!< The LUT result is the output of PLA */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup PLA_Global_Functions
+ * @{
+ */
+
+/* Initialization and configuration functions */
+int32_t PLA_DeInit(CM_PLA_TypeDef *PLAx);
+int32_t PLA_Init(CM_PLA_TypeDef *PLAx, uint32_t u32Unit, const stc_pla_init_t *pstcPlaInit);
+int32_t PLA_StructInit(stc_pla_init_t *pstcPlaInit);
+en_functional_state_t PLA_GetOutputLevel(CM_PLA_TypeDef *PLAx, uint32_t u32Unit);
+void PLA_SetMuxSrc(CM_PLA_TypeDef *PLAx, uint32_t u32Unit, uint32_t u32Ch, uint32_t u32Src);
+void PLA_SetCombLogic(CM_PLA_TypeDef *PLAx, uint32_t u32Unit, uint32_t u32Value);
+void PLA_OutputCmd(CM_PLA_TypeDef *PLAx, uint32_t u32Unit, en_functional_state_t enNewState);
+void PLA_Cmd(CM_PLA_TypeDef *PLAx, uint32_t u32Unit, en_functional_state_t enNewState);
+
+/**
+ * @}
+ */
+
+#endif /* LL_PLA_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_PLA_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_pwc.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_pwc.h
new file mode 100644
index 0000000000..b819393e5a
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_pwc.h
@@ -0,0 +1,653 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_pwc.h
+ * @brief This file contains all the functions prototypes of the PWC driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Modify group PWC_Stop_Type
+ 2023-09-30 CDT Remove redundant macro definition
+ Modify the PWC_LVD_Detection_Voltage_Sel comment
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_PWC_H__
+#define __HC32_LL_PWC_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_PWC
+ * @{
+ */
+
+#if (LL_PWC_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup PWC_Global_Types PWC Global Types
+ * @{
+ */
+/**
+ * @brief PWC LVD Init
+ */
+typedef struct {
+ uint32_t u32State; /*!< LVD function setting, @ref PWC_LVD_Config for details */
+ uint32_t u32CompareOutputState; /*!< LVD compare output function setting, @ref PWC_LVD_CMP_Config for details */
+ uint32_t u32ExceptionType; /*!< LVD interrupt or reset selection, @ref PWC_LVD_Exception_Type_Sel for details */
+ uint32_t u32Filter; /*!< LVD digital filter function setting, @ref PWC_LVD_DF_Config for details */
+ uint32_t u32FilterClock; /*!< LVD digital filter clock setting, @ref PWC_LVD_DFS_Clk_Sel for details */
+ uint32_t u32ThresholdVoltage; /*!< LVD detect voltage setting, @ref PWC_LVD_Detection_Voltage_Sel for details */
+ uint32_t u32TriggerEdge; /*!< LVD trigger setting, @ref PWC_LVD_TRIG_Sel for details */
+} stc_pwc_lvd_init_t;
+
+/**
+ * @brief PWC power down mode innit
+ */
+typedef struct {
+ uint8_t u8Mode; /*!< Power down mode, @ref PWC_PDMode_Sel for details. */
+ uint8_t u8IOState; /*!< IO state in power down mode, @ref PWC_PDMode_IO_Sel for details. */
+} stc_pwc_pd_mode_config_t;
+
+/**
+ * @brief PWC Stop mode Init
+ */
+typedef struct {
+ uint16_t u16Clock; /*!< System clock setting after wake-up from stop mode,
+ @ref PWC_STOP_CLK_Sel for details. */
+ uint16_t u16ExBusHold; /*!< Expos status in stop mode,
+ @ref PWC_STOP_EXBUS_Sel for details. */
+ uint16_t u16FlashWait; /*!< Waiting flash stable after wake-up from stop mode,
+ @ref PWC_STOP_Flash_Wait_Sel for details. */
+} stc_pwc_stop_mode_config_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup PWC_Global_Macros PWC Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup PWC_PDMode_Sel Power down mode selection
+ * @{
+ */
+#define PWC_PD_MD1 (0x00U) /*!< Power down mode 1 */
+#define PWC_PD_MD2 (0x01U) /*!< Power down mode 2 */
+#define PWC_PD_MD3 (0x02U) /*!< Power down mode 3 */
+#define PWC_PD_MD4 (0x03U) /*!< Power down mode 4 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_PDMode_IO_Sel IO state config in Power down mode
+ * @{
+ */
+#define PWC_PD_IO_KEEP1 (0x00U) /*!< IO state retain in PD mode and configurable after wakeup */
+#define PWC_PD_IO_KEEP2 (PWC_PWRC0_IORTN_0) /*!< IO state retain in PD mode and configurable after wakeup & set IORTN[1:0]=00b */
+#define PWC_PD_IO_HIZ (PWC_PWRC0_IORTN_1) /*!< IO state switch to HiZ */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_STOP_EXBUS_Sel ExBus status while enter stop mode
+ * @{
+ */
+#define PWC_STOP_EXBUS_HIZ (0x00U) /*!< Ex-Bus Hiz in stop mode */
+#define PWC_STOP_EXBUS_HOLD (PWC_STPMCR_EXBUSOE) /*!< Ex-Bus keep in stop mode */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_STOP_CLK_Sel System clock setting after wake-up from stop mode
+ * @{
+ */
+#define PWC_STOP_CLK_KEEP (0x00U) /*!< Keep System clock setting after wake-up from stop mode */
+#define PWC_STOP_CLK_MRC (PWC_STPMCR_CKSMRC) /*!< System clock switch to MRC after wake-up from stop mode */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_STOP_Flash_Wait_Sel Whether wait flash stable or not after wake-up from stop mode
+ * @{
+ */
+#define PWC_STOP_FLASH_WAIT_ON (0x00U) /*!< Wait flash stable after wake-up from stop mode */
+#define PWC_STOP_FLASH_WAIT_OFF (PWC_STPMCR_FLNWT) /*!< Don't wait flash stable after wake-up from stop mode */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_Stop_Type PWC stop mode type.
+ * @{
+ */
+#define PWC_STOP_WFI (0x00U) /*!< Enter stop mode by WFI, and wake-up by interrupt handle. */
+#define PWC_STOP_WFE_INT (0x01U) /*!< Enter stop mode by WFE, and wake-up by interrupt request. */
+#define PWC_STOP_WFE_EVT (0x02U) /*!< Enter stop mode by WFE, and wake-up by event. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_Stop_Type PWC stop mode type.
+ * @{
+ */
+#define PWC_SLEEP_WFI (0x00U) /*!< Enter sleep mode by WFI, and wake-up by interrupt handle. */
+#define PWC_SLEEP_WFE_INT (0x01U) /*!< Enter sleep mode by WFE, and wake-up by interrupt request. */
+#define PWC_SLEEP_WFE_EVT (0x02U) /*!< Enter sleep mode by WFE, and wake-up by event. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_PD_Periph_Ram Peripheral ram to power down
+ * @{
+ */
+#define PWC_RAM_PD_CAN1 (PWC_PRAMLPC_PRAMPDC0)
+#define PWC_RAM_PD_CAN2_3 (PWC_PRAMLPC_PRAMPDC1)
+#define PWC_RAM_PD_CACHE (PWC_PRAMLPC_PRAMPDC2)
+#define PWC_RAM_PD_USBFS (PWC_PRAMLPC_PRAMPDC3)
+#define PWC_RAM_PD_ALL (PWC_PRAMLPC_PRAMPDC0 | PWC_PRAMLPC_PRAMPDC1 | \
+ PWC_PRAMLPC_PRAMPDC2 | PWC_PRAMLPC_PRAMPDC3)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_PD_Ram Peripheral ram to power down
+ * @{
+ */
+#define PWC_RAM_PD_SRAM0 (PWC_RAMPC0_RAMPDC0) /*!< 0x20000000 ~ 0x20007FFF */
+#define PWC_RAM_PD_SRAMH (PWC_RAMPC0_RAMPDC10) /*!< 0x1FFF8000 ~ 0x1FFFFFFF */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_LVD_Channel PWC LVD channel
+ * @{
+ */
+#define PWC_LVD_CH1 (0x00U)
+#define PWC_LVD_CH2 (0x01U)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_LVD_Config PWC LVD Config
+ * @{
+ */
+#define PWC_LVD_ON (PWC_PVDCR0_PVD1EN)
+#define PWC_LVD_OFF (0x00U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_LVD_Exception_Type_Sel PWC LVD Exception Type Select
+ * @{
+ */
+#define PWC_LVD_EXP_TYPE_NONE (0x00U)
+#define PWC_LVD_EXP_TYPE_INT (0x0101U)
+#define PWC_LVD_EXP_TYPE_NMI (0x0001U)
+#define PWC_LVD_EXP_TYPE_RST (PWC_PVDCR1_PVD1IRE | PWC_PVDCR1_PVD1IRS)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_LVD_CMP_Config PWC LVD Compare Config
+ * @{
+ */
+#define PWC_LVD_CMP_OFF (0x00U)
+#define PWC_LVD_CMP_ON (PWC_PVDCR1_PVD1CMPOE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_LVD_DF_Config LVD digital filter ON or OFF
+ * @{
+ */
+#define PWC_LVD_FILTER_ON (0x00U)
+#define PWC_LVD_FILTER_OFF (0x01U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_LVD_DFS_Clk_Sel LVD digital filter sample ability
+ * @note modified this value must when PWC_LVD_FILTER_OFF
+ * @{
+ */
+#define PWC_LVD_FILTER_LRC_DIV4 (0x00UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 0.25 LRC cycle */
+#define PWC_LVD_FILTER_LRC_DIV2 (0x01UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 0.5 LRC cycle */
+#define PWC_LVD_FILTER_LRC_DIV1 (0x02UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 1 LRC cycle */
+#define PWC_LVD_FILTER_LRC_MUL2 (0x03UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 2 LRC cycles */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_LVD_Detection_Voltage_Sel PWC LVD Detection voltage
+ * @{
+ * @note
+ * @verbatim
+ * | LVL0 | LVL1 | LVL2 | LVL3 | LVL4 | LVL5 | LVL6 | LVL7 | EXVCC |
+ * LVD1 | 2.00V | 2.10V | 2.30V | 2.55V | 2.65V | 2.75V | 2.85V | 2.95V | -- |
+ * LVD2 | 2.10V | 2.30V | 2.55V | 2.65V | 2.75V | 2.85V | 2.95V | 1.10V | EXVCC |
+ * @endverbatim
+ */
+#define PWC_LVD_THRESHOLD_LVL0 (0x00U)
+#define PWC_LVD_THRESHOLD_LVL1 (0x01U)
+#define PWC_LVD_THRESHOLD_LVL2 (0x02U)
+#define PWC_LVD_THRESHOLD_LVL3 (0x03U)
+#define PWC_LVD_THRESHOLD_LVL4 (0x04U)
+#define PWC_LVD_THRESHOLD_LVL5 (0x05U)
+#define PWC_LVD_THRESHOLD_LVL6 (0x06U)
+#define PWC_LVD_THRESHOLD_LVL7 (0x07U)
+#define PWC_LVD_EXTVCC (0x07U)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_LVD_TRIG_Sel LVD trigger setting
+ * @{
+ */
+#define PWC_LVD_TRIG_FALLING (0x00UL << PWC_PVDICR_PVD1EDGS_POS)
+#define PWC_LVD_TRIG_RISING (0x01UL << PWC_PVDICR_PVD1EDGS_POS)
+#define PWC_LVD_TRIG_BOTH (0x02UL << PWC_PVDICR_PVD1EDGS_POS)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_LVD_Flag LVD flag
+ * @{
+ */
+#define PWC_LVD1_FLAG_DETECT (PWC_PVDDSR_PVD1DETFLG) /*!< VCC across VLVD1 */
+#define PWC_LVD2_FLAG_DETECT (PWC_PVDDSR_PVD2DETFLG) /*!< VCC across VLVD2 */
+#define PWC_LVD1_FLAG_MON (PWC_PVDDSR_PVD1MON) /*!< VCC > VLVD1 */
+#define PWC_LVD2_FLAG_MON (PWC_PVDDSR_PVD2MON) /*!< VCC > VLVD2 */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_WKUP_Event_Sel Power down mode wakeup event selection
+ * @{
+ */
+#define PWC_PD_WKUP0_POS (0U)
+#define PWC_PD_WKUP1_POS (8U)
+#define PWC_PD_WKUP2_POS (16U)
+#define PWC_PD_WKUP_WKUP00 (PWC_PDWKE0_WKE00 << PWC_PD_WKUP0_POS)
+#define PWC_PD_WKUP_WKUP01 (PWC_PDWKE0_WKE01 << PWC_PD_WKUP0_POS)
+#define PWC_PD_WKUP_WKUP02 (PWC_PDWKE0_WKE02 << PWC_PD_WKUP0_POS)
+#define PWC_PD_WKUP_WKUP03 (PWC_PDWKE0_WKE03 << PWC_PD_WKUP0_POS)
+#define PWC_PD_WKUP_WKUP10 (PWC_PDWKE0_WKE10 << PWC_PD_WKUP0_POS)
+#define PWC_PD_WKUP_WKUP11 (PWC_PDWKE0_WKE11 << PWC_PD_WKUP0_POS)
+#define PWC_PD_WKUP_WKUP12 (PWC_PDWKE0_WKE12 << PWC_PD_WKUP0_POS)
+#define PWC_PD_WKUP_WKUP13 (PWC_PDWKE0_WKE13 << PWC_PD_WKUP0_POS)
+#define PWC_PD_WKUP_WKUP20 (PWC_PDWKE1_WKE20 << PWC_PD_WKUP1_POS)
+#define PWC_PD_WKUP_WKUP21 (PWC_PDWKE1_WKE21 << PWC_PD_WKUP1_POS)
+#define PWC_PD_WKUP_WKUP22 (PWC_PDWKE1_WKE22 << PWC_PD_WKUP1_POS)
+#define PWC_PD_WKUP_WKUP23 (PWC_PDWKE1_WKE23 << PWC_PD_WKUP1_POS)
+#define PWC_PD_WKUP_WKUP30 (PWC_PDWKE1_WKE30 << PWC_PD_WKUP1_POS)
+#define PWC_PD_WKUP_WKUP31 (PWC_PDWKE1_WKE31 << PWC_PD_WKUP1_POS)
+#define PWC_PD_WKUP_WKUP32 (PWC_PDWKE1_WKE32 << PWC_PD_WKUP1_POS)
+#define PWC_PD_WKUP_WKUP33 (PWC_PDWKE1_WKE33 << PWC_PD_WKUP1_POS)
+#define PWC_PD_WKUP_LVD1 (PWC_PDWKE2_VD1WKE << PWC_PD_WKUP2_POS)
+#define PWC_PD_WKUP_LVD2 (PWC_PDWKE2_VD2WKE << PWC_PD_WKUP2_POS)
+#define PWC_PD_WKUP_RTCPRD (PWC_PDWKE2_RTCPRDWKE << PWC_PD_WKUP2_POS)
+#define PWC_PD_WKUP_RTCALM (PWC_PDWKE2_RTCALMWKE << PWC_PD_WKUP2_POS)
+#define PWC_PD_WKUP_WKTM (PWC_PDWKE2_WKTMWKE << PWC_PD_WKUP2_POS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_WKUP_Trigger_Event_Sel Power down mode wakeup event selection to set trigger edge.
+ * @{
+ */
+#define PWC_PD_WKUP_TRIG_LVD1 (PWC_PDWKES_VD1EGS)
+#define PWC_PD_WKUP_TRIG_LVD2 (PWC_PDWKES_VD2EGS)
+#define PWC_PD_WKUP_TRIG_WKUP0 (PWC_PDWKES_WK0EGS)
+#define PWC_PD_WKUP_TRIG_WKUP1 (PWC_PDWKES_WK1EGS)
+#define PWC_PD_WKUP_TRIG_WKUP2 (PWC_PDWKES_WK2EGS)
+#define PWC_PD_WKUP_TRIG_WKUP3 (PWC_PDWKES_WK3EGS)
+
+#define PWC_PD_WKUP_TRIG_ALL (PWC_PD_WKUP_TRIG_LVD1 | PWC_PD_WKUP_TRIG_LVD2 | PWC_PD_WKUP_TRIG_WKUP0 | \
+ PWC_PD_WKUP_TRIG_WKUP1 | PWC_PD_WKUP_TRIG_WKUP2 | PWC_PD_WKUP_TRIG_WKUP3)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_WKUP_Trigger_Edge_Sel Power down mode wakeup trigger edge selection
+ * @{
+ */
+#define PWC_PD_WKUP_TRIG_FALLING (0x00U)
+#define PWC_PD_WKUP_TRIG_RISING (0x01U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_WKUP_Event_Flag_Sel Power down mode wakeup Event status selection
+ * @{
+ */
+#define PWC_PD_WKUP_FLAG0_POS (0U)
+#define PWC_PD_WKUP_FLAG1_POS (8U)
+#define PWC_PD_WKUP_FLAG_WKUP0 (PWC_PDWKF0_PTWK0F << PWC_PD_WKUP_FLAG0_POS)
+#define PWC_PD_WKUP_FLAG_WKUP1 (PWC_PDWKF0_PTWK1F << PWC_PD_WKUP_FLAG0_POS)
+#define PWC_PD_WKUP_FLAG_WKUP2 (PWC_PDWKF0_PTWK2F << PWC_PD_WKUP_FLAG0_POS)
+#define PWC_PD_WKUP_FLAG_WKUP3 (PWC_PDWKF0_PTWK3F << PWC_PD_WKUP_FLAG0_POS)
+#define PWC_PD_WKUP_FLAG_LVD1 (PWC_PDWKF0_VD1WKF << PWC_PD_WKUP_FLAG0_POS)
+#define PWC_PD_WKUP_FLAG_LVD2 (PWC_PDWKF0_VD2WKF << PWC_PD_WKUP_FLAG0_POS)
+#define PWC_PD_WKUP_FLAG_RTCPRD (PWC_PDWKF1_RTCPRDWKF << PWC_PD_WKUP_FLAG1_POS)
+#define PWC_PD_WKUP_FLAG_RTCALM (PWC_PDWKF1_RTCALMWKF << PWC_PD_WKUP_FLAG1_POS)
+#define PWC_PD_WKUP_FLAG_WKTM (PWC_PDWKF1_WKTMWKF << PWC_PD_WKUP_FLAG1_POS)
+
+#define PWC_PD_WKUP_FLAG_ALL (PWC_PD_WKUP_FLAG_WKUP0 | PWC_PD_WKUP_FLAG_WKUP1 | PWC_PD_WKUP_FLAG_WKUP2 | \
+ PWC_PD_WKUP_FLAG_WKUP3 | PWC_PD_WKUP_FLAG_LVD1 | PWC_PD_WKUP_FLAG_LVD2 | \
+ PWC_PD_WKUP_FLAG_RTCPRD | PWC_PD_WKUP_FLAG_RTCALM | PWC_PD_WKUP_FLAG_WKTM)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_WKT_State PWC WKT State
+ * @{
+ */
+#define PWC_WKT_OFF (0x00U)
+#define PWC_WKT_ON (PWC_WKTCR_WKTCE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_WKT_Clock_Source PWC WKT Clock Source
+ * @{
+ */
+#define PWC_WKT_CLK_SRC_64HZ ((0x00U << PWC_WKTCR_WKCKS_POS)) /*!< 64Hz Clock */
+#define PWC_WKT_CLK_SRC_XTAL32 ((0x01U << PWC_WKTCR_WKCKS_POS)) /*!< XTAL32 Clock */
+#define PWC_WKT_CLK_SRC_LRC ((0x02U << PWC_WKTCR_WKCKS_POS)) /*!< LRC Clock */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_Ldo_Sel PWC LDO Selection
+ * @{
+ */
+#define PWC_LDO_HRC (PWC_PWRC1_VHRCSD)
+#define PWC_LDO_PLL (PWC_PWRC1_VPLLSD)
+#define PWC_LDO_MASK (PWC_LDO_HRC | PWC_LDO_PLL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_Rtc_Clock_Sel PWC RTC clock selection
+ * @{
+ */
+#define PWC_RTC_CLK_LRC (0x00U) /*!< Rtc clock selects LRC */
+#define PWC_RTC_CLK_XTAL_DIV (0x01U) /*!< Rtc clock selects XTAL div as 32.768KHz */
+#define PWC_RTC_CLK_PIN (0x02U) /*!< Rtc clock selects PIN input */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_Port_Reset_Sel PWC Port reset selection
+ * @{
+ */
+#define PWC_PORT_RST_WDT (PWC_PWRC6_WDRTNE)
+#define PWC_PORT_RST_SW (PWC_PWRC6_SWRTNE)
+#define PWC_PORT_RST_ALL (PWC_PORT_RST_WDT | PWC_PORT_RST_SW)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_Dac_Reset_Sel PWC Port reset selection
+ * @{
+ */
+#define PWC_DAC_RST_WDT (PWC_PWRC6_WDRDAC)
+#define PWC_DAC_RST_SW (PWC_PWRC6_SWRDAC)
+#define PWC_DAC_RST_ALL (PWC_DAC_RST_WDT | PWC_DAC_RST_SW)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PWC_REG_Write_Unlock_Code PWC register unlock code.
+ * @brief Lock/unlock Code for each module
+ * PWC_UNLOCK_CODE0:
+ * Below registers are locked in CLK module.
+ * XTALCFGR, XTALSTBCR, XTALCR, XTALSTDCR, XTALSTDSR, HRCTRM, HRCCR,
+ * MRCTRM, MRCCR, PLLCFGR, PLLCR, UPLLCFGR, UPLLCR, OSCSTBSR, CKSWR,
+ * SCFGR, USBCKCFGR, TPIUCKCFGR, MCO1CFGR, MCO2CFGR, XTAL32CR,
+ * XTALC32CFGR, XTAL32NFR, LRCCR, LRCTRM.
+ * PWC_UNLOCK_CODE1:
+ * Below registers are locked in PWC module.
+ * PWRC0, PWRC1, PWRC2, PWRC3, PDWKE0, PDWKE1, PDWKE2, PDWKES, PDWKF0,
+ * PDWKF1, PWCMR, PWR_STPMCR, RAMPC0, RAMOPM.
+ * Below registers are locked in CLK module.
+ * PERICKSEL, I2SCKSEL,
+ * Below register is locked in RMU module.
+ * RSTF0
+ * PWC_UNLOCK_CODE2:
+ * Below registers are locked in PWC module.
+ * PVDCR0, PVDCR1, PVDFCR, PVDLCR, PVDICR, PVDDSR
+ * @{
+ */
+#define PWC_WRITE_ENABLE (0xA500U)
+#define PWC_UNLOCK_CODE0 (0xA501U)
+#define PWC_UNLOCK_CODE1 (0xA502U)
+#define PWC_UNLOCK_CODE2 (0xA508U)
+
+/**
+ * @brief PWC FCG0 Unlock/Lock code
+ */
+#define PWC_FCG0_REG_UNLOCK_KEY (0xA5A50001UL)
+#define PWC_FCG0_REG_LOCK_KEY (0xA5A50000UL)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup PWC_Global_Functions
+ * @{
+ */
+/**
+ * @brief Lock PWC, CLK, RMU register.
+ * @param [in] u16Module Lock code for each module.
+ * @arg PWC_UNLOCK_CODE0
+ * @arg PWC_UNLOCK_CODE1
+ * @arg PWC_UNLOCK_CODE2
+ * @retval None
+ */
+__STATIC_INLINE void PWC_REG_Lock(uint16_t u16Module)
+{
+ CM_PWC->FPRC = (PWC_WRITE_ENABLE | (uint16_t)((uint16_t)(~u16Module) & (CM_PWC->FPRC)));
+}
+
+/**
+ * @brief Unlock PWC, CLK, RMU register.
+ * @param [in] u16Module Unlock code for each module.
+ * @arg PWC_UNLOCK_CODE0
+ * @arg PWC_UNLOCK_CODE1
+ * @arg PWC_UNLOCK_CODE2
+ * @retval None
+ */
+__STATIC_INLINE void PWC_REG_Unlock(uint16_t u16Module)
+{
+ SET_REG16_BIT(CM_PWC->FPRC, u16Module);
+}
+
+/**
+ * @brief Lock PWC_FCG0 register .
+ * @param None
+ * @retval None
+ */
+__STATIC_INLINE void PWC_FCG0_REG_Lock(void)
+{
+ WRITE_REG32(CM_PWC->FCG0PC, PWC_FCG0_REG_LOCK_KEY);
+}
+
+/**
+ * @brief Unlock PWR_FCG0 register.
+ * @param None
+ * @retval None
+ * @note Call this function before FCG_Fcg0PeriphClockCmd()
+ */
+__STATIC_INLINE void PWC_FCG0_REG_Unlock(void)
+{
+ WRITE_REG32(CM_PWC->FCG0PC, PWC_FCG0_REG_UNLOCK_KEY);
+}
+
+/* PWC PD Function */
+int32_t PWC_PD_Enter(void);
+int32_t PWC_PD_StructInit(stc_pwc_pd_mode_config_t *pstcPDModeConfig);
+int32_t PWC_PD_Config(const stc_pwc_pd_mode_config_t *pstcPDModeConfig);
+void PWC_PD_SetIoState(uint8_t u8IoState);
+void PWC_PD_SetMode(uint8_t u8PdMode);
+void PWC_PD_WakeupCmd(uint32_t u32Event, en_functional_state_t enNewState);
+void PWC_PD_SetWakeupTriggerEdge(uint8_t u8Event, uint8_t u8TrigEdge);
+en_flag_status_t PWC_PD_GetWakeupStatus(uint16_t u16Flag);
+void PWC_PD_ClearWakeupStatus(uint16_t u16Flag);
+void PWC_PD_PeriphRamCmd(uint32_t u32PeriphRam, en_functional_state_t enNewState);
+void PWC_PD_RamCmd(uint32_t u32Ram, en_functional_state_t enNewState);
+void PWC_PD_VdrCmd(en_functional_state_t enNewState);
+
+/* PWC WKTM Function */
+void PWC_WKT_Config(uint16_t u16ClkSrc, uint16_t u16CmpVal);
+void PWC_WKT_SetCompareValue(uint16_t u16CmpVal);
+uint16_t PWC_WKT_GetCompareValue(void);
+void PWC_WKT_Cmd(en_functional_state_t enNewState);
+en_flag_status_t PWC_WKT_GetStatus(void);
+void PWC_WKT_ClearStatus(void);
+
+/* PWC Sleep Function */
+void PWC_SLEEP_Enter(uint8_t u8SleepType);
+
+/* PWC Stop Function */
+void PWC_STOP_Enter(uint8_t u8StopType);
+int32_t PWC_STOP_StructInit(stc_pwc_stop_mode_config_t *pstcStopConfig);
+int32_t PWC_STOP_Config(const stc_pwc_stop_mode_config_t *pstcStopConfig);
+void PWC_STOP_ClockSelect(uint8_t u8Clock);
+void PWC_STOP_FlashWaitCmd(en_functional_state_t enNewState);
+
+void PWC_STOP_ExBusHoldConfig(uint16_t u16ExBusHold);
+
+/* PWC LDO Function */
+void PWC_LDO_Cmd(uint16_t u16Ldo, en_functional_state_t enNewState);
+
+/* PWC LVD/PVD Function */
+int32_t PWC_LVD_Init(uint8_t u8Ch, const stc_pwc_lvd_init_t *pstcLvdInit);
+void PWC_LVD_DeInit(uint8_t u8Ch);
+int32_t PWC_LVD_StructInit(stc_pwc_lvd_init_t *pstcLvdInit);
+void PWC_LVD_Cmd(uint8_t u8Ch, en_functional_state_t enNewState);
+void PWC_LVD_ExtInputCmd(en_functional_state_t enNewState);
+void PWC_LVD_CompareOutputCmd(uint8_t u8Ch, en_functional_state_t enNewState);
+void PWC_LVD_DigitalFilterCmd(uint8_t u8Ch, en_functional_state_t enNewState);
+void PWC_LVD_SetFilterClock(uint8_t u8Ch, uint32_t u32Clock);
+void PWC_LVD_SetThresholdVoltage(uint8_t u8Ch, uint32_t u32Voltage);
+void PWC_LVD_ClearStatus(uint8_t u8Flag);
+en_flag_status_t PWC_LVD_GetStatus(uint8_t u8Flag);
+
+/* PWC Power Monitor Function */
+void PWC_PowerMonitorCmd(en_functional_state_t enNewState);
+
+/* PWC RAM Function */
+
+void PWC_XTAL32_PowerCmd(en_functional_state_t enNewState);
+void PWC_RetSram_PowerCmd(en_functional_state_t enNewState);
+
+void PWC_PortResetCmd(uint8_t u8Event, en_functional_state_t enNewState);
+void PWC_DacResetCmd(uint8_t u8Event, en_functional_state_t enNewState);
+void PWC_ReleasePort(void);
+void PWC_SetRtcClock(uint8_t u8Clock);
+/**
+ * @}
+ */
+
+#endif /* LL_PWC_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_PWC_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_qspi.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_qspi.h
new file mode 100644
index 0000000000..8988d7a247
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_qspi.h
@@ -0,0 +1,445 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_qspi.h
+ * @brief This file contains all the functions prototypes of the QSPI driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_QSPI_H__
+#define __HC32_LL_QSPI_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_QSPI
+ * @{
+ */
+
+#if (LL_QSPI_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup QSPI_Global_Types QSPI Global Types
+ * @{
+ */
+
+/**
+ * @brief QSPI initialization structure definition
+ */
+typedef struct {
+ uint32_t u32ClockDiv; /*!< Specifies the clock division.
+ This parameter can be a value of @ref QSPI_Clock_Division */
+ uint32_t u32SpiMode; /*!< Specifies the SPI mode.
+ This parameter can be a value of @ref QSPI_SPI_Mode */
+ uint32_t u32PrefetchMode; /*!< Specifies the prefetch mode.
+ This parameter can be a value of @ref QSPI_Prefetch_Mode */
+ uint32_t u32ReadMode; /*!< Specifies the read mode.
+ This parameter can be a value of @ref QSPI_Read_Mode */
+ uint32_t u32DummyCycle; /*!< Specifies the number of dummy cycles.
+ This parameter can be a value of @ref QSPI_Dummy_Cycle */
+ uint32_t u32AddrWidth; /*!< Specifies the address width.
+ This parameter can be a value of @ref QSPI_Addr_Width */
+ uint32_t u32SetupTime; /*!< Specifies the advance time of QSSN setup.
+ This parameter can be a value of @ref QSPI_QSSN_Setup_Time */
+ uint32_t u32ReleaseTime; /*!< Specifies the delay time of QSSN release.
+ This parameter can be a value of @ref QSPI_QSSN_Release_Time */
+ uint32_t u32IntervalTime; /*!< Specifies the minimum interval time of QSSN.
+ This parameter can be a value of @ref QSPI_QSSN_Interval_Time */
+} stc_qspi_init_t;
+
+/**
+ * @brief QSPI Custom read mode structure definition
+ */
+typedef struct {
+ uint32_t u32InstrProtocol; /*!< Specifies the instruction stage protocol.
+ This parameter can be a value of @ref QSPI_Instruction_Protocol */
+ uint32_t u32AddrProtocol; /*!< Specifies the address stage protocol.
+ This parameter can be a value of @ref QSPI_Addr_Protocol */
+ uint32_t u32DataProtocol; /*!< Specifies the data stage protocol.
+ This parameter can be a value of @ref QSPI_Data_Protocol */
+ uint8_t u8InstrCode; /*!< Specifies the instruction code in custom read mode.
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFF */
+} stc_qspi_custom_mode_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup QSPI_Global_Macros QSPI Global Macros
+ * @{
+ */
+
+/* QSPI memory mapping base and end address */
+#define QSPI_ROM_BASE (0x98000000UL)
+#define QSPI_ROM_END (0x9BFFFFFFUL)
+
+/**
+ * @defgroup QSPI_Clock_Division QSPI Clock Division
+ * @{
+ */
+#define QSPI_CLK_DIV2 (0x01UL << QSPI_CR_DIV_POS) /*!< Clock division by 2 */
+#define QSPI_CLK_DIV3 (0x02UL << QSPI_CR_DIV_POS) /*!< Clock division by 3 */
+#define QSPI_CLK_DIV4 (0x03UL << QSPI_CR_DIV_POS) /*!< Clock division by 4 */
+#define QSPI_CLK_DIV5 (0x04UL << QSPI_CR_DIV_POS) /*!< Clock division by 5 */
+#define QSPI_CLK_DIV6 (0x05UL << QSPI_CR_DIV_POS) /*!< Clock division by 6 */
+#define QSPI_CLK_DIV7 (0x06UL << QSPI_CR_DIV_POS) /*!< Clock division by 7 */
+#define QSPI_CLK_DIV8 (0x07UL << QSPI_CR_DIV_POS) /*!< Clock division by 8 */
+#define QSPI_CLK_DIV9 (0x08UL << QSPI_CR_DIV_POS) /*!< Clock division by 9 */
+#define QSPI_CLK_DIV10 (0x09UL << QSPI_CR_DIV_POS) /*!< Clock division by 10 */
+#define QSPI_CLK_DIV11 (0x0AUL << QSPI_CR_DIV_POS) /*!< Clock division by 11 */
+#define QSPI_CLK_DIV12 (0x0BUL << QSPI_CR_DIV_POS) /*!< Clock division by 12 */
+#define QSPI_CLK_DIV13 (0x0CUL << QSPI_CR_DIV_POS) /*!< Clock division by 13 */
+#define QSPI_CLK_DIV14 (0x0DUL << QSPI_CR_DIV_POS) /*!< Clock division by 14 */
+#define QSPI_CLK_DIV15 (0x0EUL << QSPI_CR_DIV_POS) /*!< Clock division by 15 */
+#define QSPI_CLK_DIV16 (0x0FUL << QSPI_CR_DIV_POS) /*!< Clock division by 16 */
+#define QSPI_CLK_DIV17 (0x10UL << QSPI_CR_DIV_POS) /*!< Clock division by 17 */
+#define QSPI_CLK_DIV18 (0x11UL << QSPI_CR_DIV_POS) /*!< Clock division by 18 */
+#define QSPI_CLK_DIV19 (0x12UL << QSPI_CR_DIV_POS) /*!< Clock division by 19 */
+#define QSPI_CLK_DIV20 (0x13UL << QSPI_CR_DIV_POS) /*!< Clock division by 20 */
+#define QSPI_CLK_DIV21 (0x14UL << QSPI_CR_DIV_POS) /*!< Clock division by 21 */
+#define QSPI_CLK_DIV22 (0x15UL << QSPI_CR_DIV_POS) /*!< Clock division by 22 */
+#define QSPI_CLK_DIV23 (0x16UL << QSPI_CR_DIV_POS) /*!< Clock division by 23 */
+#define QSPI_CLK_DIV24 (0x17UL << QSPI_CR_DIV_POS) /*!< Clock division by 24 */
+#define QSPI_CLK_DIV25 (0x18UL << QSPI_CR_DIV_POS) /*!< Clock division by 25 */
+#define QSPI_CLK_DIV26 (0x19UL << QSPI_CR_DIV_POS) /*!< Clock division by 26 */
+#define QSPI_CLK_DIV27 (0x1AUL << QSPI_CR_DIV_POS) /*!< Clock division by 27 */
+#define QSPI_CLK_DIV28 (0x1BUL << QSPI_CR_DIV_POS) /*!< Clock division by 28 */
+#define QSPI_CLK_DIV29 (0x1CUL << QSPI_CR_DIV_POS) /*!< Clock division by 29 */
+#define QSPI_CLK_DIV30 (0x1DUL << QSPI_CR_DIV_POS) /*!< Clock division by 30 */
+#define QSPI_CLK_DIV31 (0x1EUL << QSPI_CR_DIV_POS) /*!< Clock division by 31 */
+#define QSPI_CLK_DIV32 (0x1FUL << QSPI_CR_DIV_POS) /*!< Clock division by 32 */
+#define QSPI_CLK_DIV33 (0x20UL << QSPI_CR_DIV_POS) /*!< Clock division by 33 */
+#define QSPI_CLK_DIV34 (0x21UL << QSPI_CR_DIV_POS) /*!< Clock division by 34 */
+#define QSPI_CLK_DIV35 (0x22UL << QSPI_CR_DIV_POS) /*!< Clock division by 35 */
+#define QSPI_CLK_DIV36 (0x23UL << QSPI_CR_DIV_POS) /*!< Clock division by 36 */
+#define QSPI_CLK_DIV37 (0x24UL << QSPI_CR_DIV_POS) /*!< Clock division by 37 */
+#define QSPI_CLK_DIV38 (0x25UL << QSPI_CR_DIV_POS) /*!< Clock division by 38 */
+#define QSPI_CLK_DIV39 (0x26UL << QSPI_CR_DIV_POS) /*!< Clock division by 39 */
+#define QSPI_CLK_DIV40 (0x27UL << QSPI_CR_DIV_POS) /*!< Clock division by 40 */
+#define QSPI_CLK_DIV41 (0x28UL << QSPI_CR_DIV_POS) /*!< Clock division by 41 */
+#define QSPI_CLK_DIV42 (0x29UL << QSPI_CR_DIV_POS) /*!< Clock division by 42 */
+#define QSPI_CLK_DIV43 (0x2AUL << QSPI_CR_DIV_POS) /*!< Clock division by 43 */
+#define QSPI_CLK_DIV44 (0x2BUL << QSPI_CR_DIV_POS) /*!< Clock division by 44 */
+#define QSPI_CLK_DIV45 (0x2CUL << QSPI_CR_DIV_POS) /*!< Clock division by 45 */
+#define QSPI_CLK_DIV46 (0x2DUL << QSPI_CR_DIV_POS) /*!< Clock division by 46 */
+#define QSPI_CLK_DIV47 (0x2EUL << QSPI_CR_DIV_POS) /*!< Clock division by 47 */
+#define QSPI_CLK_DIV48 (0x2FUL << QSPI_CR_DIV_POS) /*!< Clock division by 48 */
+#define QSPI_CLK_DIV49 (0x30UL << QSPI_CR_DIV_POS) /*!< Clock division by 49 */
+#define QSPI_CLK_DIV50 (0x31UL << QSPI_CR_DIV_POS) /*!< Clock division by 50 */
+#define QSPI_CLK_DIV51 (0x32UL << QSPI_CR_DIV_POS) /*!< Clock division by 51 */
+#define QSPI_CLK_DIV52 (0x33UL << QSPI_CR_DIV_POS) /*!< Clock division by 52 */
+#define QSPI_CLK_DIV53 (0x34UL << QSPI_CR_DIV_POS) /*!< Clock division by 53 */
+#define QSPI_CLK_DIV54 (0x35UL << QSPI_CR_DIV_POS) /*!< Clock division by 54 */
+#define QSPI_CLK_DIV55 (0x36UL << QSPI_CR_DIV_POS) /*!< Clock division by 55 */
+#define QSPI_CLK_DIV56 (0x37UL << QSPI_CR_DIV_POS) /*!< Clock division by 56 */
+#define QSPI_CLK_DIV57 (0x38UL << QSPI_CR_DIV_POS) /*!< Clock division by 57 */
+#define QSPI_CLK_DIV58 (0x39UL << QSPI_CR_DIV_POS) /*!< Clock division by 58 */
+#define QSPI_CLK_DIV59 (0x3AUL << QSPI_CR_DIV_POS) /*!< Clock division by 59 */
+#define QSPI_CLK_DIV60 (0x3BUL << QSPI_CR_DIV_POS) /*!< Clock division by 60 */
+#define QSPI_CLK_DIV61 (0x3CUL << QSPI_CR_DIV_POS) /*!< Clock division by 61 */
+#define QSPI_CLK_DIV62 (0x3DUL << QSPI_CR_DIV_POS) /*!< Clock division by 62 */
+#define QSPI_CLK_DIV63 (0x3EUL << QSPI_CR_DIV_POS) /*!< Clock division by 63 */
+#define QSPI_CLK_DIV64 (0x3FUL << QSPI_CR_DIV_POS) /*!< Clock division by 64 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup QSPI_SPI_Mode QSPI SPI Mode
+ * @{
+ */
+#define QSPI_SPI_MD0 (0UL) /*!< Selects SPI mode 0 */
+#define QSPI_SPI_MD3 (QSPI_CR_SPIMD3) /*!< Selects SPI mode 3 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup QSPI_Prefetch_Mode QSPI Prefetch Mode
+ * @{
+ */
+#define QSPI_PREFETCH_MD_INVD (0UL) /*!< Disable prefetch */
+#define QSPI_PREFETCH_MD_EDGE_STOP (QSPI_CR_PFE) /*!< Stop prefetch at the edge of byte */
+#define QSPI_PREFETCH_MD_IMMED_STOP (QSPI_CR_PFE | QSPI_CR_PFSAE) /*!< Stop prefetch at current position immediately */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup QSPI_Read_Mode QSPI Read Mode
+ * @{
+ */
+#define QSPI_RD_MD_STD_RD (0UL) /*!< Standard read mode (no dummy cycles) */
+#define QSPI_RD_MD_FAST_RD (0x01UL << QSPI_CR_MDSEL_POS) /*!< Fast read mode (dummy cycles between address and data) */
+#define QSPI_RD_MD_DUAL_OUTPUT_FAST_RD (0x02UL << QSPI_CR_MDSEL_POS) /*!< Fast read dual output mode (data on 2 lines) */
+#define QSPI_RD_MD_DUAL_IO_FAST_RD (0x03UL << QSPI_CR_MDSEL_POS) /*!< Fast read dual I/O mode (address and data on 2 lines) */
+#define QSPI_RD_MD_QUAD_OUTPUT_FAST_RD (0x04UL << QSPI_CR_MDSEL_POS) /*!< Fast read quad output mode (data on 4 lines) */
+#define QSPI_RD_MD_QUAD_IO_FAST_RD (0x05UL << QSPI_CR_MDSEL_POS) /*!< Fast read quad I/O mode (address and data on 4 lines) */
+#define QSPI_RD_MD_CUSTOM_STANDARD_RD (0x06UL << QSPI_CR_MDSEL_POS) /*!< Custom standard read mode */
+#define QSPI_RD_MD_CUSTOM_FAST_RD (0x07UL << QSPI_CR_MDSEL_POS) /*!< Custom fast read mode */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup QSPI_Dummy_Cycle QSPI Dummy Cycle
+ * @{
+ */
+#define QSPI_DUMMY_CYCLE3 (0UL) /*!< Dummy cycle is 3 */
+#define QSPI_DUMMY_CYCLE4 (0x01UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 4 */
+#define QSPI_DUMMY_CYCLE5 (0x02UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 5 */
+#define QSPI_DUMMY_CYCLE6 (0x03UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 6 */
+#define QSPI_DUMMY_CYCLE7 (0x04UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 7 */
+#define QSPI_DUMMY_CYCLE8 (0x05UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 8 */
+#define QSPI_DUMMY_CYCLE9 (0x06UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 9 */
+#define QSPI_DUMMY_CYCLE10 (0x07UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 10 */
+#define QSPI_DUMMY_CYCLE11 (0x08UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 11 */
+#define QSPI_DUMMY_CYCLE12 (0x09UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 12 */
+#define QSPI_DUMMY_CYCLE13 (0x0AUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 13 */
+#define QSPI_DUMMY_CYCLE14 (0x0BUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 14 */
+#define QSPI_DUMMY_CYCLE15 (0x0CUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 15 */
+#define QSPI_DUMMY_CYCLE16 (0x0DUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 16 */
+#define QSPI_DUMMY_CYCLE17 (0x0EUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 15 */
+#define QSPI_DUMMY_CYCLE18 (0x0FUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 16 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup QSPI_Addr_Width QSPI Address Width
+ * @{
+ */
+#define QSPI_ADDR_WIDTH_8BIT (0x0U) /*!< QSPI address width is 8 bits */
+#define QSPI_ADDR_WIDTH_16BIT (QSPI_FCR_AWSL_0) /*!< QSPI address width is 16 bits */
+#define QSPI_ADDR_WIDTH_24BIT (QSPI_FCR_AWSL_1) /*!< QSPI address width is 24 bits */
+#define QSPI_ADDR_WIDTH_32BIT_INSTR_24BIT (QSPI_FCR_AWSL) /*!< QSPI address width is 32 bits and don't use 4-byte address read instruction code */
+#define QSPI_ADDR_WIDTH_32BIT_INSTR_32BIT (QSPI_FCR_AWSL | QSPI_FCR_FOUR_BIC) /*!< QSPI address width is 32 bits and use 4-byte address read instruction code */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup QSPI_QSSN_Setup_Time QSPI QSSN Setup Time
+ * @{
+ */
+#define QSPI_QSSN_SETUP_ADVANCE_QSCK0P5 (0UL) /*!< Output QSSN signal 0.5 QSCK before the first rising edge of QSCK */
+#define QSPI_QSSN_SETUP_ADVANCE_QSCK1P5 (QSPI_FCR_SSNLD) /*!< Output QSSN signal 1.5 QSCK before the first rising edge of QSCK */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup QSPI_QSSN_Release_Time QSPI QSSN Release Time
+ * @{
+ */
+#define QSPI_QSSN_RELEASE_DELAY_QSCK0P5 (0UL) /*!< Release QSSN signal 0.5 QSCK after the last rising edge of QSCK */
+#define QSPI_QSSN_RELEASE_DELAY_QSCK1P5 (QSPI_FCR_SSNHD) /*!< Release QSSN signal 1.5 QSCK after the last rising edge of QSCK */
+#define QSPI_QSSN_RELEASE_DELAY_QSCK32 (QSPI_CSCR_SSNW_0 << 8U) /*!< Release QSSN signal 32 QSCK after the last rising edge of QSCK */
+#define QSPI_QSSN_RELEASE_DELAY_QSCK128 (QSPI_CSCR_SSNW_1 << 8U) /*!< Release QSSN signal 128 QSCK after the last rising edge of QSCK */
+#define QSPI_QSSN_RELEASE_DELAY_INFINITE (QSPI_CSCR_SSNW << 8U) /*!< Never release QSSN signal after the last rising edge of QSCK */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup QSPI_QSSN_Interval_Time QSPI QSSN Interval Time
+ * @{
+ */
+#define QSPI_QSSN_INTERVAL_QSCK1 (0UL) /*!< Minimum interval time is 1 QSCK */
+#define QSPI_QSSN_INTERVAL_QSCK2 (0x01UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 2 QSCK */
+#define QSPI_QSSN_INTERVAL_QSCK3 (0x02UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 3 QSCK */
+#define QSPI_QSSN_INTERVAL_QSCK4 (0x03UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 4 QSCK */
+#define QSPI_QSSN_INTERVAL_QSCK5 (0x04UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 5 QSCK */
+#define QSPI_QSSN_INTERVAL_QSCK6 (0x05UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 6 QSCK */
+#define QSPI_QSSN_INTERVAL_QSCK7 (0x06UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 7 QSCK */
+#define QSPI_QSSN_INTERVAL_QSCK8 (0x07UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 8 QSCK */
+#define QSPI_QSSN_INTERVAL_QSCK9 (0x08UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 9 QSCK */
+#define QSPI_QSSN_INTERVAL_QSCK10 (0x09UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 10 QSCK */
+#define QSPI_QSSN_INTERVAL_QSCK11 (0x0AUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 11 QSCK */
+#define QSPI_QSSN_INTERVAL_QSCK12 (0x0BUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 12 QSCK */
+#define QSPI_QSSN_INTERVAL_QSCK13 (0x0CUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 13 QSCK */
+#define QSPI_QSSN_INTERVAL_QSCK14 (0x0DUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 14 QSCK */
+#define QSPI_QSSN_INTERVAL_QSCK15 (0x0EUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 15 QSCK */
+#define QSPI_QSSN_INTERVAL_QSCK16 (0x0FUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 16 QSCK */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup QSPI_Instruction_Protocol QSPI Instruction Protocol
+ * @{
+ */
+#define QSPI_INSTR_PROTOCOL_1LINE (0x0U) /*!< Instruction on 1 line */
+#define QSPI_INSTR_PROTOCOL_2LINE (QSPI_CR_IPRSL_0) /*!< Instruction on 2 lines */
+#define QSPI_INSTR_PROTOCOL_4LINE (QSPI_CR_IPRSL_1) /*!< Instruction on 4 lines */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup QSPI_Addr_Protocol QSPI Address Protocol
+ * @{
+ */
+#define QSPI_ADDR_PROTOCOL_1LINE (0x0U) /*!< Address on 1 line */
+#define QSPI_ADDR_PROTOCOL_2LINE (QSPI_CR_APRSL_0) /*!< Address on 2 lines */
+#define QSPI_ADDR_PROTOCOL_4LINE (QSPI_CR_APRSL_1) /*!< Address on 4 lines */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup QSPI_Data_Protocol QSPI Data Protocol
+ * @{
+ */
+#define QSPI_DATA_PROTOCOL_1LINE (0x0U) /*!< Data on 1 line */
+#define QSPI_DATA_PROTOCOL_2LINE (QSPI_CR_DPRSL_0) /*!< Data on 2 lines */
+#define QSPI_DATA_PROTOCOL_4LINE (QSPI_CR_DPRSL_1) /*!< Data on 4 lines */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup QSPI_WP_Pin_Level QSPI WP Pin Level
+ * @{
+ */
+#define QSPI_WP_PIN_LOW (0x0U) /*!< WP(QSIO2) pin output low */
+#define QSPI_WP_PIN_HIGH (QSPI_FCR_WPOL) /*!< WP(QSIO2) pin output high */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup QSPI_Status_Flag QSPI Status Flag
+ * @{
+ */
+#define QSPI_FLAG_DIRECT_COMM_BUSY (QSPI_SR_BUSY) /*!< Serial transfer being processed */
+#define QSPI_FLAG_XIP_MD (QSPI_SR_XIPF) /*!< XIP mode */
+#define QSPI_FLAG_ROM_ACCESS_ERR (QSPI_SR_RAER) /*!< ROM access detection status in direct communication mode */
+#define QSPI_FLAG_PREFETCH_BUF_FULL (QSPI_SR_PFFUL) /*!< Prefetch buffer is full */
+#define QSPI_FLAG_PREFETCH_STOP (QSPI_SR_PFAN) /*!< Prefetch function operating */
+
+#define QSPI_FLAG_ALL (QSPI_FLAG_DIRECT_COMM_BUSY | QSPI_FLAG_XIP_MD | \
+ QSPI_FLAG_ROM_ACCESS_ERR | QSPI_FLAG_PREFETCH_BUF_FULL | \
+ QSPI_FLAG_PREFETCH_STOP)
+#define QSPI_FLAG_CLR_ALL (QSPI_FLAG_ROM_ACCESS_ERR)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup QSPI_Global_Functions
+ * @{
+ */
+
+/**
+ * @brief Write data in direct communication mode.
+ * @param [in] u8Value Byte data.
+ * @retval None
+ */
+__STATIC_INLINE void QSPI_WriteDirectCommValue(uint8_t u8Value)
+{
+ WRITE_REG32(CM_QSPI->DCOM, u8Value);
+}
+
+/**
+ * @brief Read data in direct communication mode.
+ * @param None
+ * @retval uint8_t Byte data.
+ */
+__STATIC_INLINE uint8_t QSPI_ReadDirectCommValue(void)
+{
+ return (uint8_t)CM_QSPI->DCOM;
+}
+
+/* Initialization and configuration functions */
+int32_t QSPI_DeInit(void);
+int32_t QSPI_Init(const stc_qspi_init_t *pstcQspiInit);
+int32_t QSPI_StructInit(stc_qspi_init_t *pstcQspiInit);
+void QSPI_SetWpPinLevel(uint32_t u32Level);
+void QSPI_SetPrefetchMode(uint32_t u32Mode);
+void QSPI_SelectMemoryBlock(uint8_t u8Block);
+void QSPI_SetReadMode(uint32_t u32Mode);
+int32_t QSPI_CustomReadConfig(const stc_qspi_custom_mode_t *pstcCustomMode);
+void QSPI_XipModeCmd(uint8_t u8ModeCode, en_functional_state_t enNewState);
+
+/* Transfer and receive data functions */
+void QSPI_EnterDirectCommMode(void);
+void QSPI_ExitDirectCommMode(void);
+void QSPI_WriteDirectCommValue(uint8_t u8Value);
+uint8_t QSPI_ReadDirectCommValue(void);
+
+/* Interrupt and flag management functions */
+uint8_t QSPI_GetPrefetchBufSize(void);
+en_flag_status_t QSPI_GetStatus(uint32_t u32Flag);
+void QSPI_ClearStatus(uint32_t u32Flag);
+
+/**
+ * @}
+ */
+
+#endif /* LL_QSPI_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_QSPI_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_rmu.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_rmu.h
new file mode 100644
index 0000000000..bf34b1edcc
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_rmu.h
@@ -0,0 +1,224 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_rmu.h
+ * @brief This file contains all the functions prototypes of the RMU driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Refine RMU_FRST0 peripheral
+ 2023-09-30 CDT Modify RMU_FRST2_PERIPH_TMRx macro definition
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_RMU_H__
+#define __HC32_LL_RMU_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_RMU
+ * @{
+ */
+#if (LL_RMU_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup RMU_Global_Macros RMU Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup RMU_ResetCause Rmu reset cause
+ * @{
+ */
+#define RMU_FLAG_PWR_ON (RMU_RSTF0_PORF) /*!< Power on reset */
+#define RMU_FLAG_PIN (RMU_RSTF0_PINRF) /*!< Reset pin reset */
+#define RMU_FLAG_BROWN_OUT (RMU_RSTF0_BORF) /*!< Brown-out reset */
+#define RMU_FLAG_PVD1 (RMU_RSTF0_PVD1RF) /*!< Program voltage Detection 1 reset */
+#define RMU_FLAG_PVD2 (RMU_RSTF0_PVD2RF) /*!< Program voltage Detection 2 reset */
+#define RMU_FLAG_WDT (RMU_RSTF0_WDRF) /*!< Watchdog timer reset */
+#define RMU_FLAG_SWDT (RMU_RSTF0_SWDRF) /*!< Special watchdog timer reset */
+#define RMU_FLAG_PWR_DOWN (RMU_RSTF0_PDRF) /*!< Power down reset */
+#define RMU_FLAG_SW (RMU_RSTF0_SWRF) /*!< Software reset */
+#define RMU_FLAG_MPU_ERR (RMU_RSTF0_MPUERF) /*!< Mpu error reset */
+#define RMU_FLAG_RAM_PARITY_ERR (RMU_RSTF0_RAPERF) /*!< Ram parity error reset */
+#define RMU_FLAG_RAM_ECC (RMU_RSTF0_RAECRF) /*!< Ram ECC reset */
+#define RMU_FLAG_CLK_ERR (RMU_RSTF0_CKFERF) /*!< Clk frequency error reset */
+#define RMU_FLAG_XTAL_ERR (RMU_RSTF0_XTALERF) /*!< Xtal error reset */
+#define RMU_FLAG_CPU_LOCKUP (RMU_RSTF0_LKUPRF) /*!< M4 Lockup reset */
+#define RMU_FLAG_MX (RMU_RSTF0_MULTIRF) /*!< Multiply reset cause */
+#define RMU_FLAG_ALL (RMU_FLAG_PWR_ON | RMU_FLAG_PIN | RMU_FLAG_BROWN_OUT | RMU_FLAG_PVD1 | \
+ RMU_FLAG_PVD2 | RMU_FLAG_WDT | RMU_FLAG_SWDT | RMU_FLAG_PWR_DOWN | \
+ RMU_FLAG_SW | RMU_FLAG_MPU_ERR | RMU_FLAG_RAM_PARITY_ERR | RMU_FLAG_RAM_ECC | \
+ RMU_FLAG_CLK_ERR | RMU_FLAG_XTAL_ERR | RMU_FLAG_CPU_LOCKUP | RMU_FLAG_MX)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup RMU_FRST0_Peripheral RMU FRST0 peripheral
+ * @{
+ */
+#define RMU_FRST0_PERIPH_PLA (RMU_FRST0_PLA)
+#define RMU_FRST0_PERIPH_KEY (RMU_FRST0_KEY)
+#define RMU_FRST0_PERIPH_DMA1 (RMU_FRST0_DMA1)
+#define RMU_FRST0_PERIPH_DMA2 (RMU_FRST0_DMA2)
+#define RMU_FRST0_PERIPH_FCM (RMU_FRST0_FCM)
+#define RMU_FRST0_PERIPH_AOS (RMU_FRST0_AOS)
+#define RMU_FRST0_PERIPH_CTC (RMU_FRST0_CTC)
+#define RMU_FRST0_PERIPH_MAU (RMU_FRST0_MAU)
+#define RMU_FRST0_PERIPH_AES (RMU_FRST0_AES)
+#define RMU_FRST0_PERIPH_HASH (RMU_FRST0_HASH)
+#define RMU_FRST0_PERIPH_TRNG (RMU_FRST0_TRNG)
+#define RMU_FRST0_PERIPH_CRC (RMU_FRST0_CRC)
+#define RMU_FRST0_PERIPH_DCU1 (RMU_FRST0_DCU1)
+#define RMU_FRST0_PERIPH_DCU2 (RMU_FRST0_DCU2)
+#define RMU_FRST0_PERIPH_DCU3 (RMU_FRST0_DCU3)
+#define RMU_FRST0_PERIPH_ALL (0x07FFE800UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup RMU_FRST1_Peripheral RMU FRST1 peripheral
+ * @{
+ */
+#define RMU_FRST1_PERIPH_QSPI (RMU_FRST1_QSPI)
+#define RMU_FRST1_PERIPH_MDIO (RMU_FRST1_MDIO)
+#define RMU_FRST1_PERIPH_SPI1 (RMU_FRST1_SPI1)
+#define RMU_FRST1_PERIPH_SPI2 (RMU_FRST1_SPI2)
+#define RMU_FRST1_PERIPH_SPI3 (RMU_FRST1_SPI3)
+#define RMU_FRST1_PERIPH_SPI4 (RMU_FRST1_SPI4)
+#define RMU_FRST1_PERIPH_USBFS (RMU_FRST1_USBFS)
+#define RMU_FRST1_PERIPH_FMAC1 (RMU_FRST1_FMAC1)
+#define RMU_FRST1_PERIPH_FMAC2 (RMU_FRST1_FMAC2)
+#define RMU_FRST1_PERIPH_FMAC3 (RMU_FRST1_FMAC3)
+#define RMU_FRST1_PERIPH_FMAC4 (RMU_FRST1_FMAC4)
+#define RMU_FRST1_PERIPH_ALL (0x0F4F0108UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup RMU_FRST2_Peripheral RMU FRST2 peripheral
+ * @{
+ */
+#define RMU_FRST2_PERIPH_TMR6 (RMU_FRST2_TMR6)
+#define RMU_FRST2_PERIPH_TMR4 (RMU_FRST2_TMR4)
+#define RMU_FRST2_PERIPH_TMR0 (RMU_FRST2_TMR0)
+#define RMU_FRST2_PERIPH_EMB (RMU_FRST2_EMB)
+#define RMU_FRST2_PERIPH_TMR2 (RMU_FRST2_TMR2)
+#define RMU_FRST2_PERIPH_TMRA (RMU_FRST2_TMRA)
+#define RMU_FRST2_PERIPH_ALL (0x00119C01UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup RMU_FRST3_Peripheral RMU FRST3 peripheral
+ * @{
+ */
+#define RMU_FRST3_PERIPH_ADC1 (RMU_FRST3_ADC1)
+#define RMU_FRST3_PERIPH_ADC2 (RMU_FRST3_ADC2)
+#define RMU_FRST3_PERIPH_ADC3 (RMU_FRST3_ADC3)
+#define RMU_FRST3_PERIPH_DAC1 (RMU_FRST3_DAC1)
+#define RMU_FRST3_PERIPH_DAC2 (RMU_FRST3_DAC2)
+#define RMU_FRST3_PERIPH_DAC3 (RMU_FRST3_DAC3)
+#define RMU_FRST3_PERIPH_DAC4 (RMU_FRST3_DAC4)
+#define RMU_FRST3_PERIPH_CMP1_2 (RMU_FRST3_CMP12)
+#define RMU_FRST3_PERIPH_CMP3_4 (RMU_FRST3_CMP34)
+#define RMU_FRST3_PERIPH_OTS (RMU_FRST3_OTS)
+#define RMU_FRST3_PERIPH_VREF (RMU_FRST3_VREF)
+#define RMU_FRST3_PERIPH_SMC (RMU_FRST3_EXMC_SMC)
+#define RMU_FRST3_PERIPH_USART1 (RMU_FRST3_USART1)
+#define RMU_FRST3_PERIPH_USART2 (RMU_FRST3_USART2)
+#define RMU_FRST3_PERIPH_USART3 (RMU_FRST3_USART3)
+#define RMU_FRST3_PERIPH_USART4 (RMU_FRST3_USART4)
+#define RMU_FRST3_PERIPH_USART5 (RMU_FRST3_USART5)
+#define RMU_FRST3_PERIPH_USART6 (RMU_FRST3_USART6)
+#define RMU_FRST3_PERIPH_ALL (0x03F133F7UL)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup RMU_Global_Functions
+ * @{
+ */
+
+en_flag_status_t RMU_GetStatus(uint32_t u32RmuResetCause);
+void RMU_ClearStatus(void);
+
+void RMU_CPULockUpCmd(en_functional_state_t enNewState);
+
+int32_t RMU_Frst0PeriphReset(uint32_t u32Frst0Periph);
+int32_t RMU_Frst1PeriphReset(uint32_t u32Frst1Periph);
+int32_t RMU_Frst2PeriphReset(uint32_t u32Frst2Periph);
+int32_t RMU_Frst3PeriphReset(uint32_t u32Frst3Periph);
+
+/**
+ * @}
+ */
+
+#endif /* LL_RMU_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_RMU_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
+
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_rtc.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_rtc.h
new file mode 100644
index 0000000000..c12b2cdc3f
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_rtc.h
@@ -0,0 +1,368 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_rtc.h
+ * @brief This file contains all the functions prototypes of the RTC driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Delete intrusion function
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_RTC_H__
+#define __HC32_LL_RTC_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_RTC
+ * @{
+ */
+
+#if (LL_RTC_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup RTC_Global_Types RTC Global Types
+ * @{
+ */
+
+/**
+ * @brief RTC Init structure definition
+ */
+typedef struct {
+ uint8_t u8ClockSrc; /*!< Specifies the RTC clock source.
+ This parameter can be a value of @ref RTC_Clock_Source */
+ uint8_t u8HourFormat; /*!< Specifies the RTC hour format.
+ This parameter can be a value of @ref RTC_Hour_Format */
+ uint8_t u8IntPeriod; /*!< Specifies the RTC interrupt period.
+ This parameter can be a value of @ref RTC_Interrupt_Period */
+ uint8_t u8ClockCompen; /*!< Specifies the validity of RTC clock compensation.
+ This parameter can be a value of @ref RTC_Clock_Compensation */
+ uint8_t u8CompenMode; /*!< Specifies the mode of RTC clock compensation.
+ This parameter can be a value of @ref RTC_Clock_Compensation_Mode */
+ uint16_t u16CompenValue; /*!< Specifies the value of RTC clock compensation.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 0x1FF */
+} stc_rtc_init_t;
+
+/**
+ * @brief RTC Date structure definition
+ */
+typedef struct {
+ uint8_t u8Year; /*!< Specifies the RTC Year.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 99 */
+ uint8_t u8Month; /*!< Specifies the RTC Month (in Decimal format).
+ This parameter can be a value of @ref RTC_Month */
+ uint8_t u8Day; /*!< Specifies the RTC Day.
+ This parameter can be a number between Min_Data = 1 and Max_Data = 31 */
+ uint8_t u8Weekday; /*!< Specifies the RTC Weekday.
+ This parameter can be a value of @ref RTC_Weekday */
+} stc_rtc_date_t;
+
+/**
+ * @brief RTC Time structure definition
+ */
+typedef struct {
+ uint8_t u8Hour; /*!< Specifies the RTC Hour.
+ This parameter can be a number between Min_Data = 1 and Max_Data = 12 if the RTC_HOUR_FMT_12H is selected.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HOUR_FMT_24H is selected */
+ uint8_t u8Minute; /*!< Specifies the RTC Minute.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 59 */
+ uint8_t u8Second; /*!< Specifies the RTC Second.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 59 */
+ uint8_t u8AmPm; /*!< Specifies the RTC Am/Pm Time (in RTC_HOUR_FMT_12H mode).
+ This parameter can be a value of @ref RTC_Hour12_AM_PM */
+} stc_rtc_time_t;
+
+/**
+ * @brief RTC Alarm structure definition
+ */
+typedef struct {
+ uint8_t u8AlarmHour; /*!< Specifies the RTC Alarm Hour.
+ This parameter can be a number between Min_Data = 1 and Max_Data = 12 if the RTC_HOUR_FMT_12H is selected.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HOUR_FMT_24H is selected */
+ uint8_t u8AlarmMinute; /*!< Specifies the RTC Alarm Minute.
+ This parameter can be a number between Min_Data = 0 and Max_Data = 59 */
+ uint8_t u8AlarmWeekday; /*!< Specifies the RTC Alarm Weekday.
+ This parameter can be a value of @ref RTC_Alarm_Weekday */
+ uint8_t u8AlarmAmPm; /*!< Specifies the RTC Alarm Am/Pm Time (in RTC_HOUR_FMT_12H mode).
+ This parameter can be a value of @ref RTC_Hour12_AM_PM */
+} stc_rtc_alarm_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup RTC_Global_Macros RTC Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup RTC_Data_Format RTC Data Format
+ * @{
+ */
+#define RTC_DATA_FMT_DEC (0x00U) /*!< Decimal data format */
+#define RTC_DATA_FMT_BCD (0x01U) /*!< BCD data format */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup RTC_Decimal_BCD_Conversion RTC Decimal BCD Conversion
+ * @{
+ */
+#define RTC_DEC2BCD(__DATA__) ((((__DATA__) / 10U) << 4U) + ((__DATA__) % 10U))
+#define RTC_BCD2DEC(__DATA__) ((((__DATA__) >> 4U) * 10U) + ((__DATA__) & 0x0FU))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup RTC_Clock_Source RTC Clock Source
+ * @{
+ */
+#define RTC_CLK_SRC_XTAL32 (0U) /*!< XTAL32 Clock */
+#define RTC_CLK_SRC_LRC (RTC_CR3_RCKSEL | RTC_CR3_LRCEN) /*!< RTC LRC Clock */
+#define RTC_CLK_SRC_XTAL_DIV (RTC_CR3_RCKSEL | PWC_PWRC6_RTCCKSEL_0) /*!< XTAL Fractional Divider */
+#define RTC_CLK_SRC_EXTCLK (RTC_CR3_RCKSEL | PWC_PWRC6_RTCCKSEL_1) /*!< External Clock */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup RTC_Hour_Format RTC Hour Format
+ * @{
+ */
+#define RTC_HOUR_FMT_12H (0U) /*!< 12 hour time system */
+#define RTC_HOUR_FMT_24H (RTC_CR1_AMPM) /*!< 24 hour time system */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup RTC_Interrupt_Period RTC Interrupt Period
+ * @{
+ */
+#define RTC_INT_PERIOD_INVD (0U) /*!< Interrupt period invalid */
+#define RTC_INT_PERIOD_PER_HALF_SEC (0x01U << RTC_CR1_PRDS_POS) /*!< Interrupt period per half second */
+#define RTC_INT_PERIOD_PER_SEC (0x02U << RTC_CR1_PRDS_POS) /*!< Interrupt period per second */
+#define RTC_INT_PERIOD_PER_MINUTE (0x03U << RTC_CR1_PRDS_POS) /*!< Interrupt period per minute */
+#define RTC_INT_PERIOD_PER_HOUR (0x04U << RTC_CR1_PRDS_POS) /*!< Interrupt period per hour */
+#define RTC_INT_PERIOD_PER_DAY (0x05U << RTC_CR1_PRDS_POS) /*!< Interrupt period per day */
+#define RTC_INT_PERIOD_PER_MONTH (0x06U << RTC_CR1_PRDS_POS) /*!< Interrupt period per month */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup RTC_Clock_Compensation RTC Clock Compensation
+ * @{
+ */
+#define RTC_CLK_COMPEN_DISABLE (0U)
+#define RTC_CLK_COMPEN_ENABLE (RTC_ERRCRH_COMPEN)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup RTC_Clock_Compensation_Mode RTC Clock Compensation Mode
+ * @{
+ */
+#define RTC_CLK_COMPEN_MD_DISTRIBUTED (0U) /*!< Distributed compensation 1Hz output */
+#define RTC_CLK_COMPEN_MD_UNIFORM (RTC_CR1_ONEHZSEL) /*!< Uniform compensation 1Hz output */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup RTC_Hour12_AM_PM RTC Hour12 AM/PM
+ * @{
+ */
+#define RTC_HOUR_24H (0U) /*!< 24-hour format */
+#define RTC_HOUR_12H_AM (0U) /*!< AM in 12-hour */
+#define RTC_HOUR_12H_PM (RTC_HOUR_HOURD_1) /*!< PM in 12-hour */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup RTC_Month RTC Month
+ * @{
+ */
+#define RTC_MONTH_JANUARY (0x01U)
+#define RTC_MONTH_FEBRUARY (0x02U)
+#define RTC_MONTH_MARCH (0x03U)
+#define RTC_MONTH_APRIL (0x04U)
+#define RTC_MONTH_MAY (0x05U)
+#define RTC_MONTH_JUNE (0x06U)
+#define RTC_MONTH_JULY (0x07U)
+#define RTC_MONTH_AUGUST (0x08U)
+#define RTC_MONTH_SEPTEMBER (0x09U)
+#define RTC_MONTH_OCTOBER (0x0AU)
+#define RTC_MONTH_NOVEMBER (0x0BU)
+#define RTC_MONTH_DECEMBER (0x0CU)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup RTC_Weekday RTC Weekday
+ * @{
+ */
+#define RTC_WEEKDAY_SUNDAY (0x00U)
+#define RTC_WEEKDAY_MONDAY (0x01U)
+#define RTC_WEEKDAY_TUESDAY (0x02U)
+#define RTC_WEEKDAY_WEDNESDAY (0x03U)
+#define RTC_WEEKDAY_THURSDAY (0x04U)
+#define RTC_WEEKDAY_FRIDAY (0x05U)
+#define RTC_WEEKDAY_SATURDAY (0x06U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup RTC_Alarm_Weekday RTC Alarm Weekday
+ * @{
+ */
+#define RTC_ALARM_WEEKDAY_SUNDAY (0x01U)
+#define RTC_ALARM_WEEKDAY_MONDAY (0x02U)
+#define RTC_ALARM_WEEKDAY_TUESDAY (0x04U)
+#define RTC_ALARM_WEEKDAY_WEDNESDAY (0x08U)
+#define RTC_ALARM_WEEKDAY_THURSDAY (0x10U)
+#define RTC_ALARM_WEEKDAY_FRIDAY (0x20U)
+#define RTC_ALARM_WEEKDAY_SATURDAY (0x40U)
+#define RTC_ALARM_WEEKDAY_EVERYDAY (0x7FU)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup RTC_Flag RTC Flag
+ * @{
+ */
+#define RTC_FLAG_RD_WR (RTC_CR2_RWEN) /*!< Read and write permission flag */
+#define RTC_FLAG_ALARM (RTC_CR2_ALMF) /*!< Alarm flag */
+#define RTC_FLAG_PERIOD (RTC_CR2_PRDF) /*!< Period flag */
+#define RTC_FLAG_ALL (RTC_FLAG_RD_WR | RTC_FLAG_ALARM | RTC_FLAG_PERIOD)
+#define RTC_FLAG_CLR_ALL (RTC_FLAG_ALARM | RTC_FLAG_PERIOD)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup RTC_Interrupt RTC Interrupt
+ * @{
+ */
+#define RTC_INT_PERIOD (RTC_CR2_PRDIE) /*!< Period interrupt */
+#define RTC_INT_ALARM (RTC_CR2_ALMIE) /*!< Alarm interrupt */
+#define RTC_INT_ALL (RTC_INT_PERIOD | RTC_INT_ALARM)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup RTC_Global_Functions
+ * @{
+ */
+
+/* Initialization and configuration functions */
+int32_t RTC_DeInit(void);
+int32_t RTC_Init(const stc_rtc_init_t *pstcRtcInit);
+int32_t RTC_StructInit(stc_rtc_init_t *pstcRtcInit);
+int32_t RTC_EnterRwMode(void);
+int32_t RTC_ExitRwMode(void);
+
+/* Control configuration */
+int32_t RTC_ConfirmLPMCond(void);
+void RTC_SetIntPeriod(uint8_t u8Period);
+void RTC_SetClockSrc(uint8_t u8Src);
+void RTC_SetClockCompenValue(uint16_t u16Value);
+en_functional_state_t RTC_GetCounterState(void);
+void RTC_Cmd(en_functional_state_t enNewState);
+void RTC_LrcCmd(en_functional_state_t enNewState);
+void RTC_OneHzOutputCmd(en_functional_state_t enNewState);
+void RTC_ClockCompenCmd(en_functional_state_t enNewState);
+
+/* Date and time functions */
+int32_t RTC_SetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate);
+int32_t RTC_GetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate);
+int32_t RTC_SetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime);
+int32_t RTC_GetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime);
+
+/* Alarm configuration functions */
+int32_t RTC_SetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm);
+int32_t RTC_GetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm);
+void RTC_AlarmCmd(en_functional_state_t enNewState);
+
+/* Interrupt and flag management functions */
+void RTC_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState);
+en_flag_status_t RTC_GetStatus(uint32_t u32Flag);
+void RTC_ClearStatus(uint32_t u32Flag);
+
+/**
+ * @}
+ */
+
+#endif /* LL_RTC_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_RTC_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_smc.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_smc.h
new file mode 100644
index 0000000000..5563815ee7
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_smc.h
@@ -0,0 +1,365 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_smc.h
+ * @brief This file contains all the functions prototypes of the EXMC_SMC
+ * (External Memory Controller: Static Memory Controller) driver library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT API EXMC_SMC_DeInit add return value
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_SMC_H__
+#define __HC32_LL_SMC_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_EXMC
+ * @{
+ */
+
+/**
+ * @addtogroup LL_SMC
+ * @{
+ */
+
+#if (LL_SMC_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup EXMC_SMC_Global_Types EXMC_SMC Global Types
+ * @{
+ */
+
+/**
+ * @brief EXMC_SMC Chip Configuration Structure definition
+ */
+typedef struct {
+ uint32_t u32ReadMode; /*!< Defines the read sync enable.
+ This parameter can be a value of @ref EXMC_SMC_Memory_Read_Mode */
+ uint32_t u32WriteMode; /*!< Defines the write sync enable.
+ This parameter can be a value of @ref EXMC_SMC_Memory_Write_Mode */
+ uint32_t u32MemoryWidth; /*!< Defines the SMC memory width.
+ This parameter can be a value of @ref EXMC_SMC_Memory_Width. */
+ uint32_t u32BAA; /*!< Defines the SMC BAA signal enable.
+ This parameter can be a value of @ref EXMC_SMC_BAA_Port_Selection. */
+ uint32_t u32ADV; /*!< Defines the SMC ADVS signal enable.
+ This parameter can be a value of @ref EXMC_SMC_ADV_Port_Selection. */
+ uint32_t u32BLS; /*!< Defines the SMC BLS signal selection.
+ This parameter can be a value of @ref EXMC_SMC_BLS_Synchronization_Selection. */
+ uint32_t u32AddrMatch; /*!< Defines the address match.
+ This parameter can be a value between Min_Data = 0x60 and Max_Data = 0x7F */
+ uint32_t u32AddrMask; /*!< Defines the address mask.
+ This parameter can be a value of @ref EXMC_SMC_Mask_Address. */
+} stc_exmc_smc_chip_config_t;
+
+/**
+ * @brief EXMC_SMC Timing Configuration Structure definition
+ */
+typedef struct {
+ uint8_t u8RC; /*!< Defines the RC in memory clock cycles.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */
+ uint8_t u8WC; /*!< Defines the WC in memory clock cycles.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */
+ uint8_t u8CEOE; /*!< Defines the CEOE in memory clock cycles.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
+ uint8_t u8WP; /*!< Defines the WP in memory clock cycles.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
+ uint8_t u8PC; /*!< Defines the PC in memory clock cycles.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
+ uint8_t u8TR; /*!< Defines the TR in memory clock cycles.
+ This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
+} stc_exmc_smc_timing_config_t;
+
+/**
+ * @brief EXMC_SMC Initialization Structure definition
+ */
+typedef struct {
+ stc_exmc_smc_chip_config_t stcChipConfig; /*!< SMC memory chip configure.
+ This structure details refer @ref stc_exmc_smc_chip_config_t. */
+ stc_exmc_smc_timing_config_t stcTimingConfig; /*!< SMC memory timing configure.
+ This structure details refer @ref stc_exmc_smc_timing_config_t. */
+} stc_exmc_smc_init_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup EXMC_SMC_Global_Macros EXMC_SMC Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup EXMC_SMC_Chip EXMC_SMC Chip
+ * @{
+ */
+#define EXMC_SMC_CHIP0 (0UL) /*!< Chip 0 */
+#define EXMC_SMC_CHIP1 (1UL) /*!< Chip 1 */
+#define EXMC_SMC_CHIP2 (2UL) /*!< Chip 2 */
+#define EXMC_SMC_CHIP3 (3UL) /*!< Chip 3 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EXMC_SMC_Memory_Read_Mode EXMC_SMC Memory Read Mode
+ * @{
+ */
+#define EXMC_SMC_READ_ASYNC (0UL)
+#define EXMC_SMC_READ_SYNC (SMC_CPCR_RSYN)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EXMC_SMC_Memory_Write_Mode EXMC_SMC Memory Write Mode
+ * @{
+ */
+#define EXMC_SMC_WRITE_ASYNC (0UL)
+#define EXMC_SMC_WRITE_SYNC (SMC_CPCR_WSYN)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EXMC_SMC_Memory_Width EXMC_SMC Memory Width
+ * @{
+ */
+#define EXMC_SMC_MEMORY_WIDTH_16BIT (SMC_CPCR_MW_0)
+#define EXMC_SMC_MEMORY_WIDTH_32BIT (SMC_CPCR_MW_1)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EXMC_SMC_BAA_Port_Selection EXMC_SMC BAA Port Selection
+ * @{
+ */
+#define EXMC_SMC_BAA_PORT_DISABLE (0UL)
+#define EXMC_SMC_BAA_PORT_ENABLE (SMC_CPCR_BAAS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EXMC_SMC_ADV_Port_Selection EXMC_SMC ADV Port Selection
+ * @{
+ */
+#define EXMC_SMC_ADV_PORT_DISABLE (0UL)
+#define EXMC_SMC_ADV_PORT_ENABLE (SMC_CPCR_ADVS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EXMC_SMC_BLS_Synchronization_Selection EXMC_SMC BLS Synchronization Selection
+ * @{
+ */
+#define EXMC_SMC_BLS_SYNC_CS (0UL)
+#define EXMC_SMC_BLS_SYNC_WE (SMC_CPCR_BLSS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EXMC_SMC_Command EXMC_SMC Command
+ * @{
+ */
+#define EXMC_SMC_CMD_MDREGCONFIG (SMC_CMDR_CMD_0) /*!< Command: MdRetConfig */
+#define EXMC_SMC_CMD_UPDATEREGS (SMC_CMDR_CMD_1) /*!< Command: UpdateRegs */
+#define EXMC_SMC_CMD_MDREGCONFIG_AND_UPDATEREGS (SMC_CMDR_CMD) /*!< Command: MdRetConfig & UpdateRegs */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EXMC_SMC_CRE_Polarity EXMC_SMC CRE Polarity
+ * @{
+ */
+#define EXMC_SMC_CRE_POLARITY_LOW (0UL) /*!< CRE is LOW */
+#define EXMC_SMC_CRE_POLARITY_HIGH (SMC_CMDR_CRES) /*!< CRE is HIGH when ModeReg write occurs */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EXMC_SMC_Status EXMC_SMC Status
+ * @{
+ */
+#define EXMC_SMC_READY (0UL) /*!< SMC is ready */
+#define EXMC_SMC_LOWPOWER (SMC_STSR_STATUS) /*!< SMC is low power */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EXMC_SMC_Sample_Clock EXMC_SMC Sample Clock
+ * @{
+ */
+#define EXMC_SMC_SAMPLE_CLK_INTERNCLK (0UL) /*!< Internal EXCLK */
+#define EXMC_SMC_SAMPLE_CLK_INTERNCLK_INVT (SMC_BACR_CKSEL_0) /*!< Invert internal EXCLK */
+#define EXMC_SMC_SAMPLE_CLK_EXTCLK (SMC_BACR_CKSEL_1) /*!< External clock from EXMC_CLK port */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EXMC_SMC_Mask_Address EXMC_SMC Mask Address
+ * @{
+ */
+#define EXMC_SMC_ADDR_MASK_16MB (0xFFUL)
+#define EXMC_SMC_ADDR_MASK_32MB (0xFEUL)
+#define EXMC_SMC_ADDR_MASK_64MB (0xFCUL)
+#define EXMC_SMC_ADDR_MASK_128MB (0xF8UL)
+#define EXMC_SMC_ADDR_MASK_256MB (0xF0UL)
+#define EXMC_SMC_ADDR_MASK_512MB (0xE0UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EXMC_SMC_Address_Space EXMC_SMC Address Space
+ * @{
+ */
+#define EXMC_SMC_ADDR_MIN (0x60000000UL)
+#define EXMC_SMC_ADDR_MAX (0x7FFFFFFFUL)
+/**
+ * @}
+ */
+
+/**
+ * @brief SMC device memory address shifting.
+ * @param [in] mem_base_addr SMC base address
+ * @param [in] mem_width SMC memory width
+ * @param [in] addr SMC device memory address
+ * @retval SMC device shifted address value
+ */
+#define SMC_ADDR_SHIFT(mem_base_addr, mem_width, addr) \
+( ((EXMC_SMC_MEMORY_WIDTH_16BIT == (mem_width))? (((mem_base_addr) + ((addr) << 1U))) : \
+ (((mem_base_addr) + ((addr) << 2U)))))
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup EXMC_SMC_Global_Functions
+ * @{
+ */
+
+/**
+ * @brief SMC entry low power state
+ * @param None
+ * @retval None
+ */
+__STATIC_INLINE void EXMC_SMC_EntryLowPower(void)
+{
+ WRITE_REG32(CM_SMC->STCR0, SMC_STCR0_LPWIR);
+}
+
+/**
+ * @brief SMC exit low power state
+ * @param None
+ * @retval None
+ */
+__STATIC_INLINE void EXMC_SMC_ExitLowPower(void)
+{
+ WRITE_REG32(CM_SMC->STCR1, SMC_STCR1_LPWOR);
+}
+
+/**
+ * @brief Get SMC status
+ * @param None
+ * @retval Returned value can be one of the macros group @ref EXMC_SMC_Status
+ * - EXMC_SMC_READY: SMC is ready
+ * - EXMC_SMC_LOWPOWER: SMC is low power
+ */
+__STATIC_INLINE uint32_t EXMC_SMC_GetStatus(void)
+{
+ return READ_REG32_BIT(CM_SMC->STSR, SMC_STSR_STATUS);
+}
+
+/* Initialization and configuration EXMC_SMC functions */
+int32_t EXMC_SMC_StructInit(stc_exmc_smc_init_t *pstcSmcInit);
+int32_t EXMC_SMC_Init(uint32_t u32Chip, const stc_exmc_smc_init_t *pstcSmcInit);
+int32_t EXMC_SMC_DeInit(void);
+
+void EXMC_SMC_Cmd(en_functional_state_t enNewState);
+void EXMC_SMC_PinMuxCmd(en_functional_state_t enNewState);
+void EXMC_SMC_SetSampleClock(uint32_t u32SampleClock);
+void EXMC_SMC_SetRefreshPeriod(uint8_t u8PeriodVal);
+
+void EXMC_SMC_SetCommand(uint32_t u32Chip, uint32_t u32Cmd, uint32_t u32CrePolarity, uint32_t u32Addr);
+uint32_t EXMC_SMC_GetChipStartAddr(uint32_t u32Chip);
+uint32_t EXMC_SMC_GetChipEndAddr(uint32_t u32Chip);
+int32_t EXMC_SMC_GetChipConfig(uint32_t u32Chip, stc_exmc_smc_chip_config_t *pstcChipConfig);
+int32_t EXMC_SMC_GetTimingConfig(uint32_t u32Chip, stc_exmc_smc_timing_config_t *pstcTimingConfig);
+
+/**
+ * @}
+ */
+
+#endif /* LL_SMC_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_SMC_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_spi.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_spi.h
new file mode 100644
index 0000000000..7011ff4e45
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_spi.h
@@ -0,0 +1,509 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_spi.h
+ * @brief This file contains all the functions prototypes of the SPI driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-12-15 CDT Rename SPI_FLAG_OVERLOAD as SPI_FLAG_OVERRUN, SPI_FLAG_UNDERLOAD as SPI_FLAG_UNDERRUN
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_SPI_H__
+#define __HC32_LL_SPI_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_SPI
+ * @{
+ */
+
+#if (LL_SPI_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup SPI_Global_Types SPI Global Types
+ * @{
+ */
+
+/**
+ * @brief Structure definition of SPI initialization.
+ * @note The parameter u32BaudRatePrescaler is invalid while slave mode
+ */
+typedef struct {
+ uint32_t u32WireMode; /*!< SPI wire mode, 3 wire mode or 4 wire mode.
+ This parameter can be a value of @ref SPI_Wire_Mode_Define */
+ uint32_t u32TransMode; /*!< SPI transfer mode, send only or full duplex.
+ This parameter can be a value of @ref SPI_Trans_Mode_Define */
+ uint32_t u32MasterSlave; /*!< SPI master/slave mode.
+ This parameter can be a value of @ref SPI_Master_Slave_Mode_Define */
+ uint32_t u32ModeFaultDetect; /*!< SPI mode fault detect command.
+ This parameter can be a value of @ref SPI_Mode_Fault_Detect_Command_Define */
+ uint32_t u32Parity; /*!< SPI parity check selection.
+ This parameter can be a value of @ref SPI_Parity_Check_Define */
+ uint32_t u32SpiMode; /*!< SPI mode.
+ This parameter can be a value of @ref SPI_Mode_Define */
+ uint32_t u32BaudRatePrescaler; /*!< SPI baud rate prescaler.
+ This parameter can be a value of @ref SPI_Baud_Rate_Prescaler_Define */
+ uint32_t u32DataBits; /*!< SPI data bits, 4 bits ~ 32 bits.
+ This parameter can be a value of @ref SPI_Data_Size_Define */
+ uint32_t u32FirstBit; /*!< MSB first or LSB first.
+ This parameter can be a value of @ref SPI_First_Bit_Define */
+ uint32_t u32SuspendMode; /*!< SPI communication suspend function.
+ This parameter can be a value of @ref SPI_Com_Suspend_Func_Define */
+ uint32_t u32FrameLevel; /*!< SPI frame level, SPI_1_FRAME ~ SPI_4_FRAME.
+ This parameter can be a value of @ref SPI_Frame_Level_Define */
+} stc_spi_init_t;
+
+/**
+ * @brief Structure definition of SPI delay time configuration.
+ */
+typedef struct {
+ uint32_t u32IntervalDelay; /*!< SPI interval time delay (Next access delay time)
+ This parameter can be a value of @ref SPI_Interval_Delay_Time_define */
+ uint32_t u32ReleaseDelay; /*!< SPI release time delay (SCK invalid delay time)
+ This parameter can be a value of @ref SPI_Release_Delay_Time_define */
+ uint32_t u32SetupDelay; /*!< SPI Setup time delay (SCK valid delay time) define
+ This parameter can be a value of @ref SPI_Setup_Delay_Time_define */
+} stc_spi_delay_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup SPI_Global_Macros SPI Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup SPI_Wire_Mode_Define SPI Wire Mode Define
+ * @{
+ */
+#define SPI_4_WIRE (0UL)
+#define SPI_3_WIRE (SPI_CR_SPIMDS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_Trans_Mode_Define SPI Transfer Mode Define
+ * @{
+ */
+#define SPI_FULL_DUPLEX (0UL) /*!< Full duplex. */
+#define SPI_SEND_ONLY (SPI_CR_TXMDS) /*!< Send only. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_Master_Slave_Mode_Define SPI Master Slave Mode Define
+ * @{
+ */
+#define SPI_SLAVE (0UL)
+#define SPI_MASTER (SPI_CR_MSTR)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_Loopback_Selection_Define SPI Loopback Selection Define
+ * @note Loopback mode is mainly used for parity self-diagnosis in 4-wire full-duplex mode.
+ * @{
+ */
+#define SPI_LOOPBACK_INVD (0UL)
+#define SPI_LOOPBACK_MOSI_INVT (SPI_CR_SPLPBK) /*!< MISO data is the inverse of the data output by MOSI. */
+#define SPI_LOOPBACK_MOSI (SPI_CR_SPLPBK2) /*!< MISO data is the data output by MOSI. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_Int_Type_Define SPI Interrupt Type Define
+ * @{
+ */
+#define SPI_INT_ERR (SPI_CR_EIE) /*!< Including overload, underload and parity error. */
+#define SPI_INT_TX_BUF_EMPTY (SPI_CR_TXIE)
+#define SPI_INT_RX_BUF_FULL (SPI_CR_RXIE)
+#define SPI_INT_IDLE (SPI_CR_IDIE)
+#define SPI_INT_ALL (SPI_INT_ERR | SPI_INT_TX_BUF_EMPTY | SPI_INT_RX_BUF_FULL | SPI_INT_IDLE )
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_Mode_Fault_Detect_Command_Define SPI Mode Fault Detect Command Define
+ * @{
+ */
+#define SPI_MD_FAULT_DETECT_DISABLE (0UL) /*!< Disable mode fault detection. */
+#define SPI_MD_FAULT_DETECT_ENABLE (SPI_CR_MODFE) /*!< Enable mode fault detection. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_Parity_Check_Define SPI Parity Check Mode Define
+ * @{
+ */
+#define SPI_PARITY_INVD (0UL) /*!< Parity check invalid. */
+#define SPI_PARITY_EVEN (SPI_CR_PAE) /*!< Parity check selection even parity. */
+#define SPI_PARITY_ODD (SPI_CR_PAE | SPI_CR_PAOE) /*!< Parity check selection odd parity. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_SS_Pin_Define SPI SSx Define
+ * @{
+ */
+#define SPI_PIN_SS0 (SPI_CFG1_SS0PV)
+#define SPI_PIN_SS1 (SPI_CFG1_SS1PV)
+#define SPI_PIN_SS2 (SPI_CFG1_SS2PV)
+#define SPI_PIN_SS3 (SPI_CFG1_SS3PV)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_SS_Level SPI SS pin valid level
+ * @{
+ */
+#define SPI_SS_VALID_LVL_HIGH (1UL)
+#define SPI_SS_VALID_LVL_LOW (0UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_Read_Target_Buf_Define SPI Read Data Register Target Buffer Define
+ * @{
+ */
+#define SPI_RD_TARGET_RD_BUF (0UL) /*!< Read RX buffer. */
+#define SPI_RD_TARGET_WR_BUF (SPI_CFG1_SPRDTD) /*!< Read TX buffer. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_Frame_Level_Define SPI data frame level define, The Data in the SPI_DR register will be send to TX_BUFF
+ * after enough data frame write to the SPI_DR
+ * @{
+ */
+#define SPI_1_FRAME (0UL) /*!< Data 1 frame */
+#define SPI_2_FRAME (SPI_CFG1_FTHLV_0) /*!< Data 2 frame.*/
+#define SPI_3_FRAME (SPI_CFG1_FTHLV_1) /*!< Data 3 frame.*/
+#define SPI_4_FRAME (SPI_CFG1_FTHLV) /*!< Data 4 frame.*/
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_Interval_Delay_Time_define SPI Interval Time Delay (Next Access Delay Time) define
+ * @{
+ */
+#define SPI_INTERVAL_TIME_1SCK (0UL << SPI_CFG1_MIDI_POS) /*!< 1 SCK + 2 PCLK1 */
+#define SPI_INTERVAL_TIME_2SCK (1UL << SPI_CFG1_MIDI_POS) /*!< 2 SCK + 2 PCLK1 */
+#define SPI_INTERVAL_TIME_3SCK (2UL << SPI_CFG1_MIDI_POS) /*!< 3 SCK + 2 PCLK1 */
+#define SPI_INTERVAL_TIME_4SCK (3UL << SPI_CFG1_MIDI_POS) /*!< 4 SCK + 2 PCLK1 */
+#define SPI_INTERVAL_TIME_5SCK (4UL << SPI_CFG1_MIDI_POS) /*!< 5 SCK + 2 PCLK1 */
+#define SPI_INTERVAL_TIME_6SCK (5UL << SPI_CFG1_MIDI_POS) /*!< 6 SCK + 2 PCLK1 */
+#define SPI_INTERVAL_TIME_7SCK (6UL << SPI_CFG1_MIDI_POS) /*!< 7 SCK + 2 PCLK1 */
+#define SPI_INTERVAL_TIME_8SCK (7UL << SPI_CFG1_MIDI_POS) /*!< 8 SCK + 2 PCLK1 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_Release_Delay_Time_define SPI Release Time Delay (SCK Invalid Delay Time) Define
+ * @{
+ */
+#define SPI_RELEASE_TIME_1SCK (0UL << SPI_CFG1_MSSDL_POS)
+#define SPI_RELEASE_TIME_2SCK (1UL << SPI_CFG1_MSSDL_POS)
+#define SPI_RELEASE_TIME_3SCK (2UL << SPI_CFG1_MSSDL_POS)
+#define SPI_RELEASE_TIME_4SCK (3UL << SPI_CFG1_MSSDL_POS)
+#define SPI_RELEASE_TIME_5SCK (4UL << SPI_CFG1_MSSDL_POS)
+#define SPI_RELEASE_TIME_6SCK (5UL << SPI_CFG1_MSSDL_POS)
+#define SPI_RELEASE_TIME_7SCK (6UL << SPI_CFG1_MSSDL_POS)
+#define SPI_RELEASE_TIME_8SCK (7UL << SPI_CFG1_MSSDL_POS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_Setup_Delay_Time_define SPI Setup Time Delay (SCK Valid Delay Time) Define
+ * @{
+ */
+#define SPI_SETUP_TIME_1SCK (0UL << SPI_CFG1_MSSI_POS)
+#define SPI_SETUP_TIME_2SCK (1UL << SPI_CFG1_MSSI_POS)
+#define SPI_SETUP_TIME_3SCK (2UL << SPI_CFG1_MSSI_POS)
+#define SPI_SETUP_TIME_4SCK (3UL << SPI_CFG1_MSSI_POS)
+#define SPI_SETUP_TIME_5SCK (4UL << SPI_CFG1_MSSI_POS)
+#define SPI_SETUP_TIME_6SCK (5UL << SPI_CFG1_MSSI_POS)
+#define SPI_SETUP_TIME_7SCK (6UL << SPI_CFG1_MSSI_POS)
+#define SPI_SETUP_TIME_8SCK (7UL << SPI_CFG1_MSSI_POS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_Com_Suspend_Func_Define SPI Communication Suspend Function Define
+ * @{
+ */
+#define SPI_COM_SUSP_FUNC_OFF (0UL)
+#define SPI_COM_SUSP_FUNC_ON (SPI_CR_CSUSPE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_Mode_Define SPI Mode Define
+ * @{
+ */
+#define SPI_MD_0 (0UL) /*!< SCK pin output low in idle state; \
+ MOSI/MISO pin data valid in odd edge, \
+ MOSI/MISO pin data change in even edge */
+#define SPI_MD_1 (SPI_CFG2_CPHA) /*!< SCK pin output low in idle state; \
+ MOSI/MISO pin data valid in even edge, \
+ MOSI/MISO pin data change in odd edge */
+#define SPI_MD_2 (SPI_CFG2_CPOL) /*!< SCK pin output high in idle state; \
+ MOSI/MISO pin data valid in odd edge, \
+ MOSI/MISO pin data change in even edge */
+#define SPI_MD_3 (SPI_CFG2_CPOL | SPI_CFG2_CPHA) /*!< SCK pin output high in idle state; \
+ MOSI/MISO pin data valid in even edge, \
+ MOSI/MISO pin data change in odd edge */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_SCK_Polarity_Define SPI SCK Polarity Define
+ * @{
+ */
+#define SPI_SCK_POLARITY_LOW (0UL) /*!< SCK pin output low in idle state */
+#define SPI_SCK_POLARITY_HIGH (SPI_CFG2_CPOL) /*!< SCK pin output high in idle state */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_SCK_Phase_Define SPI SCK Phase Define
+ * @{
+ */
+#define SPI_SCK_PHASE_ODD_EDGE_SAMPLE (0UL) /*!< MOSI/MISO pin data sample in odd edge, MOSI/MISO pin data change in even edge */
+#define SPI_SCK_PHASE_EVEN_EDGE_SAMPLE (SPI_CFG2_CPHA) /*!< MOSI/MISO pin data sample in even edge, MOSI/MISO pin data change in odd edge */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_Baud_Rate_Prescaler_Define SPI Baudrate Prescaler Define
+ * @{
+ */
+#define SPI_BR_CLK_DIV2 (0UL) /*!< PCLK1 / 2 */
+#define SPI_BR_CLK_DIV4 (1UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 4 */
+#define SPI_BR_CLK_DIV6 (2UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 6 */
+#define SPI_BR_CLK_DIV8 (3UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 8 */
+#define SPI_BR_CLK_DIV10 (4UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 10 */
+#define SPI_BR_CLK_DIV12 (5UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 12 */
+#define SPI_BR_CLK_DIV14 (6UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 14 */
+#define SPI_BR_CLK_DIV16 (7UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 16 */
+#define SPI_BR_CLK_DIV18 (8UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 18 */
+#define SPI_BR_CLK_DIV20 (9UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 20 */
+#define SPI_BR_CLK_DIV22 (10UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 22 */
+#define SPI_BR_CLK_DIV24 (11UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 24 */
+#define SPI_BR_CLK_DIV26 (12UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 26 */
+#define SPI_BR_CLK_DIV28 (13UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 28 */
+#define SPI_BR_CLK_DIV30 (14UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 30 */
+#define SPI_BR_CLK_DIV32 (15UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 32 */
+#define SPI_BR_CLK_DIV36 ((8UL << SPI_CFG1_CLKDIV_POS) | (1UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 36 */
+#define SPI_BR_CLK_DIV40 ((9UL << SPI_CFG1_CLKDIV_POS) | (1UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 40 */
+#define SPI_BR_CLK_DIV44 ((10UL << SPI_CFG1_CLKDIV_POS) | (1UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 44 */
+#define SPI_BR_CLK_DIV48 ((11UL << SPI_CFG1_CLKDIV_POS) | (1UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 48 */
+#define SPI_BR_CLK_DIV52 ((12UL << SPI_CFG1_CLKDIV_POS) | (1UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 52 */
+#define SPI_BR_CLK_DIV56 ((13UL << SPI_CFG1_CLKDIV_POS) | (1UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 56 */
+#define SPI_BR_CLK_DIV60 ((14UL << SPI_CFG1_CLKDIV_POS) | (1UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 60 */
+#define SPI_BR_CLK_DIV64 ((15UL << SPI_CFG1_CLKDIV_POS) | (1UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 64 */
+#define SPI_BR_CLK_DIV72 ((8UL << SPI_CFG1_CLKDIV_POS) | (2UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 72 */
+#define SPI_BR_CLK_DIV80 ((9UL << SPI_CFG1_CLKDIV_POS) | (2UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 80 */
+#define SPI_BR_CLK_DIV88 ((10UL << SPI_CFG1_CLKDIV_POS) | (2UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 88 */
+#define SPI_BR_CLK_DIV96 ((11UL << SPI_CFG1_CLKDIV_POS) | (2UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 96 */
+#define SPI_BR_CLK_DIV104 ((12UL << SPI_CFG1_CLKDIV_POS) | (2UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 104 */
+#define SPI_BR_CLK_DIV112 ((13UL << SPI_CFG1_CLKDIV_POS) | (2UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 112 */
+#define SPI_BR_CLK_DIV120 ((14UL << SPI_CFG1_CLKDIV_POS) | (2UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 120 */
+#define SPI_BR_CLK_DIV128 ((15UL << SPI_CFG1_CLKDIV_POS) | (2UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 128 */
+#define SPI_BR_CLK_DIV144 ((8UL << SPI_CFG1_CLKDIV_POS) | (3UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 144 */
+#define SPI_BR_CLK_DIV160 ((9UL << SPI_CFG1_CLKDIV_POS) | (3UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 160 */
+#define SPI_BR_CLK_DIV176 ((10UL << SPI_CFG1_CLKDIV_POS) | (3UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 176 */
+#define SPI_BR_CLK_DIV192 ((11UL << SPI_CFG1_CLKDIV_POS) | (3UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 192 */
+#define SPI_BR_CLK_DIV208 ((12UL << SPI_CFG1_CLKDIV_POS) | (3UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 208 */
+#define SPI_BR_CLK_DIV224 ((13UL << SPI_CFG1_CLKDIV_POS) | (3UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 224 */
+#define SPI_BR_CLK_DIV240 ((14UL << SPI_CFG1_CLKDIV_POS) | (3UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 240 */
+#define SPI_BR_CLK_DIV256 ((15UL << SPI_CFG1_CLKDIV_POS) | (3UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 256 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_Data_Size_Define SPI Data Size Define
+ * @{
+ */
+#define SPI_DATA_SIZE_4BIT (0UL << SPI_CFG2_DSIZE_POS)
+#define SPI_DATA_SIZE_5BIT (1UL << SPI_CFG2_DSIZE_POS)
+#define SPI_DATA_SIZE_6BIT (2UL << SPI_CFG2_DSIZE_POS)
+#define SPI_DATA_SIZE_7BIT (3UL << SPI_CFG2_DSIZE_POS)
+#define SPI_DATA_SIZE_8BIT (4UL << SPI_CFG2_DSIZE_POS)
+#define SPI_DATA_SIZE_9BIT (5UL << SPI_CFG2_DSIZE_POS)
+#define SPI_DATA_SIZE_10BIT (6UL << SPI_CFG2_DSIZE_POS)
+#define SPI_DATA_SIZE_11BIT (7UL << SPI_CFG2_DSIZE_POS)
+#define SPI_DATA_SIZE_12BIT (8UL << SPI_CFG2_DSIZE_POS)
+#define SPI_DATA_SIZE_13BIT (9UL << SPI_CFG2_DSIZE_POS)
+#define SPI_DATA_SIZE_14BIT (10UL << SPI_CFG2_DSIZE_POS)
+#define SPI_DATA_SIZE_15BIT (11UL << SPI_CFG2_DSIZE_POS)
+#define SPI_DATA_SIZE_16BIT (12UL << SPI_CFG2_DSIZE_POS)
+#define SPI_DATA_SIZE_20BIT (13UL << SPI_CFG2_DSIZE_POS)
+#define SPI_DATA_SIZE_24BIT (14UL << SPI_CFG2_DSIZE_POS)
+#define SPI_DATA_SIZE_32BIT (15UL << SPI_CFG2_DSIZE_POS)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_First_Bit_Define SPI First Bit Define
+ * @{
+ */
+#define SPI_FIRST_MSB (0UL)
+#define SPI_FIRST_LSB (SPI_CFG2_LSBF)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_Comm_Mode_Define SPI communication mode Define
+ * @{
+ */
+#define SPI_COMM_MD_NORMAL (0UL) /*!< Normal communication mode */
+#define SPI_COMM_MD_CONT (SPI_CFG1_CTMDS) /*!< Continuous communication mode */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_State_Flag_Define SPI State Flag Define
+ * @{
+ */
+#define SPI_FLAG_OVERRUN (SPI_SR_OVRERF)
+#define SPI_FLAG_IDLE (SPI_SR_IDLNF)
+#define SPI_FLAG_MD_FAULT (SPI_SR_MODFERF)
+#define SPI_FLAG_PARITY_ERR (SPI_SR_PERF)
+#define SPI_FLAG_UNDERRUN (SPI_SR_UDRERF)
+#define SPI_FLAG_TX_BUF_EMPTY (SPI_SR_TDEF) /*!< This flag is set when the data in the data register \
+ is copied into the shift register, but the transmission \
+ of the data bit may not have been completed. */
+#define SPI_FLAG_RX_BUF_FULL (SPI_SR_RDFF) /*!< Indicates that a data was received. */
+#define SPI_FLAG_CLR_ALL (SPI_FLAG_OVERRUN | SPI_FLAG_MD_FAULT | SPI_FLAG_PARITY_ERR | SPI_FLAG_UNDERRUN)
+#define SPI_FLAG_ALL (SPI_FLAG_OVERRUN | SPI_FLAG_IDLE | SPI_FLAG_MD_FAULT | SPI_FLAG_PARITY_ERR | \
+ SPI_FLAG_UNDERRUN | SPI_FLAG_TX_BUF_EMPTY | SPI_FLAG_RX_BUF_FULL)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup SPI_Global_Functions
+ * @{
+ */
+int32_t SPI_StructInit(stc_spi_init_t *pstcSpiInit);
+int32_t SPI_Init(CM_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcSpiInit);
+int32_t SPI_DeInit(CM_SPI_TypeDef *SPIx);
+
+void SPI_IntCmd(CM_SPI_TypeDef *SPIx, uint32_t u32IntType, en_functional_state_t enNewState);
+void SPI_Cmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState);
+void SPI_WriteData(CM_SPI_TypeDef *SPIx, uint32_t u32Data);
+uint32_t SPI_ReadData(const CM_SPI_TypeDef *SPIx);
+
+en_flag_status_t SPI_GetStatus(const CM_SPI_TypeDef *SPIx, uint32_t u32Flag);
+void SPI_ClearStatus(CM_SPI_TypeDef *SPIx, uint32_t u32Flag);
+void SPI_SetLoopbackMode(CM_SPI_TypeDef *SPIx, uint32_t u32Mode);
+void SPI_ParityCheckCmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState);
+void SPI_SetSSValidLevel(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin, uint32_t u32SSLevel);
+void SPI_SetSckPolarity(CM_SPI_TypeDef *SPIx, uint32_t u32Polarity);
+void SPI_SetSckPhase(CM_SPI_TypeDef *SPIx, uint32_t u32Phase);
+
+int32_t SPI_DelayTimeConfig(CM_SPI_TypeDef *SPIx, const stc_spi_delay_t *pstcDelayConfig);
+void SPI_SSPinSelect(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin);
+void SPI_SetReadBuf(CM_SPI_TypeDef *SPIx, uint32_t u32ReadBuf);
+int32_t SPI_DelayStructInit(stc_spi_delay_t *pstcDelayConfig);
+
+void SPI_SetCommMode(CM_SPI_TypeDef *SPIx, uint32_t u32Mode);
+
+int32_t SPI_Trans(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32TxLen, uint32_t u32Timeout);
+int32_t SPI_Receive(CM_SPI_TypeDef *SPIx, void *pvRxBuf, uint32_t u32RxLen, uint32_t u32Timeout);
+int32_t SPI_TransReceive(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout);
+
+/**
+ * @}
+ */
+
+#endif /* LL_SPI_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_SPI_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_sram.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_sram.h
new file mode 100644
index 0000000000..76d415e76e
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_sram.h
@@ -0,0 +1,234 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_sram.h
+ * @brief This file contains all the functions prototypes of the SRAM driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Modify typo
+ 2023-12-15 CDT Refine def group SRAM_ECC_Mode, and refine def group SRAM_Err_Mode as SRAM_Exception_Type
+ Remove wait cycle relevant code
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_SRAM_H__
+#define __HC32_LL_SRAM_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_SRAM
+ * @{
+ */
+
+#if (LL_SRAM_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup SRAM_Global_Macros SRAM Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup SRAM_Sel SRAM Selection
+ * @{
+ */
+#define SRAM_SRAMH (1UL << 1U) /*!< SRAMH: 0x1FFF8000~0x1FFFFFFF, 32KB */
+#define SRAM_SRAM0 (1UL << 0U) /*!< SRAM0: 0x20000000~0x20007FFF, 32KB */
+#define SRAM_SRAMB (1UL << 2U) /*!< SRAMB: 0x200F0000~0x200F0FFF, 4KB */
+#define SRAM_SRAM_ALL (SRAM_SRAMH | SRAM_SRAM0 | SRAM_SRAMB)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SRAM_ECC_SRAM ECC SRAM Definition
+ * @{
+ */
+#define SRAM_ECC_SRAM0 (1UL << 0U)
+#define SRAM_ECC_SRAMB (1UL << 1U)
+#define SRAM_ECC_SRAM_ALL (SRAM_ECC_SRAM0 | SRAM_ECC_SRAMB)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SRAM_Exception_Type SRAM exception type
+ * @note Even-parity check error, ECC check error.
+ * @{
+ */
+#define SRAM_EXP_TYPE_NMI (0UL)
+#define SRAM_EXP_TYPE_RST (1UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SRAM_Check_SRAM SRAM check sram
+ * @{
+ */
+#define SRAM_CHECK_SRAM0 (SRAMC_CKCR_ECCOAD)
+#define SRAM_CHECK_SRAMB (SRAMC_CKCR_BECCOAD)
+#define SRAM_CHECK_SRAMH (SRAMC_CKCR_PYOAD)
+#define SRAM_CHECK_SRAM_ALL (SRAM_CHECK_SRAM0 | SRAM_CHECK_SRAMB | SRAM_CHECK_SRAMH)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SRAM_ECC_Mode SRAM ECC Mode
+ * @note XX_INVD: The ECC mode is invalid
+ * XX_MD1: When 1-bit error occurs, ECC error corrects. No 1-bit-error status flag setting, no interrupt or reset.
+ * When 2-bit error occurs, ECC error detects. 2-bit-error status flag sets and interrupt or reset occurs.
+ * XX_MD2: When 1-bit error occurs, ECC error corrects. 1-bit-error status flag sets, no interrupt or reset.
+ * When 2-bit error occurs, ECC error detects. 2-bit-error status flag sets and interrupt or reset occurs.
+ * XX_MD3: When 1-bit error occurs, ECC error corrects. 1-bit-error status flag sets and interrupt or reset occurs.
+ * When 2-bit error occurs, ECC error detects. 2-bit-error status flag sets and interrupt or reset occurs.
+ * @{
+ */
+#define SRAM_SRAM0_ECC_INVD (0xFCFFFFFFUL) /*!< ~SRAMC_CKCR_ECCMOD */
+#define SRAM_SRAM0_ECC_MD1 (SRAMC_CKCR_ECCMOD_0)
+#define SRAM_SRAM0_ECC_MD2 (SRAMC_CKCR_ECCMOD_1)
+#define SRAM_SRAM0_ECC_MD3 (SRAMC_CKCR_ECCMOD)
+#define SRAM_SRAMB_ECC_INVD (0xF3FFFFFFUL) /*!< ~SRAMC_CKCR_BECCMOD */
+#define SRAM_SRAMB_ECC_MD1 (SRAMC_CKCR_BECCMOD_0)
+#define SRAM_SRAMB_ECC_MD2 (SRAMC_CKCR_BECCMOD_1)
+#define SRAM_SRAMB_ECC_MD3 (SRAMC_CKCR_BECCMOD)
+#define SRAM_ECC_MD_INVD (SRAM_SRAM0_ECC_INVD & SRAM_SRAMB_ECC_INVD)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SRAM_Err_Status_Flag SRAM Error Status Flag
+ * @{
+ */
+#define SRAM_FLAG_SRAMH_PYERR (SRAMC_CKSR_SRAMH_PYERR) /*!< SRAMH parity error. */
+#define SRAM_FLAG_SRAM0_1ERR (SRAMC_CKSR_SRAM0_1ERR) /*!< SRAM0 ECC 1-bit error. */
+#define SRAM_FLAG_SRAM0_2ERR (SRAMC_CKSR_SRAM0_2ERR) /*!< SRAM0 ECC 2-bit error. */
+#define SRAM_FLAG_SRAMB_1ERR (SRAMC_CKSR_SRAMB_1ERR) /*!< SRAMB ECC 1-bit error. */
+#define SRAM_FLAG_SRAMB_2ERR (SRAMC_CKSR_SRAMB_2ERR) /*!< SRAMB ECC 2-bit error. */
+#define SRAM_FLAG_CACHE_PYERR (SRAMC_CKSR_CACHE_PYERR) /*!< Cache RAM parity error. */
+#define SRAM_FLAG_ALL (0x1F8UL)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SRAM_Reg_Protect_Key SRAM Register Protect Key
+ * @{
+ */
+#define SRAM_REG_LOCK_KEY (0x76U)
+#define SRAM_REG_UNLOCK_KEY (0x77U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup SRAM_Global_Functions
+ * @{
+ */
+
+/**
+ * @brief Lock SRAM registers, write protect.
+ * @param None
+ * @retval None
+ */
+__STATIC_INLINE void SRAM_REG_Lock(void)
+{
+ WRITE_REG32(CM_SRAMC->CKPR, SRAM_REG_LOCK_KEY);
+}
+
+/**
+ * @brief Unlock SRAM registers, write enable.
+ * @param None
+ * @retval None
+ */
+__STATIC_INLINE void SRAM_REG_Unlock(void)
+{
+ WRITE_REG32(CM_SRAMC->CKPR, SRAM_REG_UNLOCK_KEY);
+}
+
+void SRAM_Init(void);
+void SRAM_DeInit(void);
+
+void SRAM_REG_Lock(void);
+void SRAM_REG_Unlock(void);
+
+void SRAM_SetEccMode(uint32_t u32EccSram, uint32_t u32EccMode);
+void SRAM_SetExceptionType(uint32_t u32CheckSram, uint32_t u32ExceptionType);
+
+en_flag_status_t SRAM_GetStatus(uint32_t u32Flag);
+void SRAM_ClearStatus(uint32_t u32Flag);
+
+void SRAM_ErrorInjectCmd(uint32_t u32EccSram, en_functional_state_t enNewState);
+void SRAM_ErrorInjectBitCmd(uint32_t u32EccSram, uint64_t u64BitSel, en_functional_state_t enNewState);
+uint32_t SRAM_GetEccErrorAddr(uint32_t u32EccSram);
+
+/**
+ * @}
+ */
+
+#endif /* LL_SRAM_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_SRAM_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_swdt.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_swdt.h
new file mode 100644
index 0000000000..15c4d4c4d3
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_swdt.h
@@ -0,0 +1,227 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_swdt.h
+ * @brief This file contains all the functions prototypes of the SWDT driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-12-15 CDT Modify macro define: SWDT_LPM_CNT_CONTINUE -> SWDT_LPM_CNT_CONT
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_SWDT_H__
+#define __HC32_LL_SWDT_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_SWDT
+ * @{
+ */
+
+#if (LL_SWDT_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup SWDT_Global_Types SWDT Global Types
+ * @{
+ */
+
+/**
+ * @brief SWDT Init structure definition
+ */
+typedef struct {
+ uint32_t u32CountPeriod; /*!< Specifies the counting period of SWDT.
+ This parameter can be a value of @ref SWDT_Count_Period */
+ uint32_t u32ClockDiv; /*!< Specifies the clock division factor of SWDT.
+ This parameter can be a value of @ref SWDT_Clock_Division */
+ uint32_t u32RefreshRange; /*!< Specifies the allow refresh range of SWDT.
+ This parameter can be a value of @ref SWDT_Refresh_Range */
+ uint32_t u32LPMCount; /*!< Specifies the count state in Low Power Mode (Sleep/Stop Mode).
+ This parameter can be a value of @ref SWDT_LPM_Count */
+ uint32_t u32ExceptionType; /*!< Specifies the type of exception response for SWDT.
+ This parameter can be a value of @ref SWDT_Exception_Type */
+} stc_swdt_init_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup SWDT_Global_Macros SWDT Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup SWDT_Count_Period SWDT Count Period
+ * @{
+ */
+#define SWDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */
+#define SWDT_CNT_PERIOD4096 (SWDT_CR_PERI_0) /*!< 4096 clock cycle */
+#define SWDT_CNT_PERIOD16384 (SWDT_CR_PERI_1) /*!< 16384 clock cycle */
+#define SWDT_CNT_PERIOD65536 (SWDT_CR_PERI) /*!< 65536 clock cycle */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SWDT_Clock_Division SWDT Clock Division
+ * @{
+ */
+#define SWDT_CLK_DIV1 (0UL) /*!< SWDTCLK/1 */
+#define SWDT_CLK_DIV16 (0x04UL << SWDT_CR_CKS_POS) /*!< SWDTCLK/16 */
+#define SWDT_CLK_DIV32 (0x05UL << SWDT_CR_CKS_POS) /*!< SWDTCLK/32 */
+#define SWDT_CLK_DIV64 (0x06UL << SWDT_CR_CKS_POS) /*!< SWDTCLK/64 */
+#define SWDT_CLK_DIV128 (0x07UL << SWDT_CR_CKS_POS) /*!< SWDTCLK/128 */
+#define SWDT_CLK_DIV256 (0x08UL << SWDT_CR_CKS_POS) /*!< SWDTCLK/256 */
+#define SWDT_CLK_DIV2048 (0x0BUL << SWDT_CR_CKS_POS) /*!< SWDTCLK/2048 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SWDT_Refresh_Range SWDT Refresh Range
+ * @{
+ */
+#define SWDT_RANGE_0TO25PCT (0x01UL << SWDT_CR_WDPT_POS) /*!< 0%~25% */
+#define SWDT_RANGE_25TO50PCT (0x02UL << SWDT_CR_WDPT_POS) /*!< 25%~50% */
+#define SWDT_RANGE_0TO50PCT (0x03UL << SWDT_CR_WDPT_POS) /*!< 0%~50% */
+#define SWDT_RANGE_50TO75PCT (0x04UL << SWDT_CR_WDPT_POS) /*!< 50%~75% */
+#define SWDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << SWDT_CR_WDPT_POS) /*!< 0%~25% & 50%~75% */
+#define SWDT_RANGE_25TO75PCT (0x06UL << SWDT_CR_WDPT_POS) /*!< 25%~75% */
+#define SWDT_RANGE_0TO75PCT (0x07UL << SWDT_CR_WDPT_POS) /*!< 0%~75% */
+#define SWDT_RANGE_75TO100PCT (0x08UL << SWDT_CR_WDPT_POS) /*!< 75%~100% */
+#define SWDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << SWDT_CR_WDPT_POS) /*!< 0%~25% & 75%~100% */
+#define SWDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << SWDT_CR_WDPT_POS) /*!< 25%~50% & 75%~100% */
+#define SWDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << SWDT_CR_WDPT_POS) /*!< 0%~50% & 75%~100% */
+#define SWDT_RANGE_50TO100PCT (0x0CUL << SWDT_CR_WDPT_POS) /*!< 50%~100% */
+#define SWDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << SWDT_CR_WDPT_POS) /*!< 0%~25% & 50%~100% */
+#define SWDT_RANGE_25TO100PCT (0x0EUL << SWDT_CR_WDPT_POS) /*!< 25%~100% */
+#define SWDT_RANGE_0TO100PCT (0x0FUL << SWDT_CR_WDPT_POS) /*!< 0%~100% */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SWDT_LPM_Count SWDT Low Power Mode Count
+ * @brief Counting control of SWDT in sleep/stop mode.
+ * @{
+ */
+#define SWDT_LPM_CNT_CONT (0UL) /*!< Continue counting in sleep/stop mode */
+#define SWDT_LPM_CNT_STOP (SWDT_CR_SLPOFF) /*!< Stop counting in sleep/stop mode */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SWDT_Exception_Type SWDT Exception Type
+ * @brief Specifies the exception response when a refresh error or count overflow occurs.
+ * @{
+ */
+#define SWDT_EXP_TYPE_INT (0UL) /*!< SWDT trigger interrupt */
+#define SWDT_EXP_TYPE_RST (SWDT_CR_ITS) /*!< SWDT trigger reset */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SWDT_Flag SWDT Flag
+ * @{
+ */
+#define SWDT_FLAG_UDF (SWDT_SR_UDF) /*!< Count underflow flag */
+#define SWDT_FLAG_REFRESH (SWDT_SR_REF) /*!< Refresh error flag */
+#define SWDT_FLAG_ALL (SWDT_SR_UDF | SWDT_SR_REF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup SWDT_Global_Functions
+ * @{
+ */
+
+/**
+ * @brief Get SWDT count value.
+ * @param None
+ * @retval uint16_t Count value
+ */
+__STATIC_INLINE uint16_t SWDT_GetCountValue(void)
+{
+ return (uint16_t)(READ_REG32(CM_SWDT->SR) & SWDT_SR_CNT);
+}
+
+/* Initialization and configuration functions */
+int32_t SWDT_Init(const stc_swdt_init_t *pstcSwdtInit);
+void SWDT_FeedDog(void);
+uint16_t SWDT_GetCountValue(void);
+
+/* Flags management functions */
+en_flag_status_t SWDT_GetStatus(uint32_t u32Flag);
+int32_t SWDT_ClearStatus(uint32_t u32Flag);
+
+/**
+ * @}
+ */
+
+#endif /* LL_SWDT_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_SWDT_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_tmr0.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_tmr0.h
new file mode 100644
index 0000000000..91c468175e
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_tmr0.h
@@ -0,0 +1,228 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_tmr0.h
+ * @brief This file contains all the functions prototypes of the TMR0 driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Modify typo
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_TMR0_H__
+#define __HC32_LL_TMR0_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_TMR0
+ * @{
+ */
+
+#if (LL_TMR0_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup TMR0_Global_Types TMR0 Global Types
+ * @{
+ */
+
+/**
+ * @brief TMR0 initialization structure definition
+ * @note The 'u32ClockDiv' is invalid when the value of 'u32ClockSrc' is "TMR0_CLK_SRC_SPEC_EVT".
+ */
+typedef struct {
+ uint32_t u32ClockSrc; /*!< Specifies the clock source of TMR0 channel.
+ This parameter can be a value of @ref TMR0_Clock_Source */
+ uint32_t u32ClockDiv; /*!< Specifies the clock division of TMR0 channel.
+ This parameter can be a value of @ref TMR0_Clock_Division */
+ uint32_t u32Func; /*!< Specifies the function of TMR0 channel.
+ This parameter can be a value of @ref TMR0_Function */
+ uint16_t u16CompareValue; /*!< Specifies the compare value of TMR0 channel.
+ This parameter can be a value of half-word */
+} stc_tmr0_init_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup TMR0_Global_Macros TMR0 Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup TMR0_Channel TMR0 Channel
+ * @{
+ */
+#define TMR0_CH_A (0UL)
+#define TMR0_CH_B (1UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR0_Clock_Source TMR0 Clock Source
+ * @note In asynchronous clock, continuous operation of the BCONR register requires waiting for 3 asynchronous clocks.
+ * @{
+ */
+#define TMR0_CLK_SRC_INTERN_CLK (0UL) /*!< Internal clock (Synchronous clock) */
+#define TMR0_CLK_SRC_SPEC_EVT (TMR0_BCONR_SYNCLKA) /*!< Specified event (Synchronous clock) */
+#define TMR0_CLK_SRC_LRC (TMR0_BCONR_SYNSA) /*!< LRC (Asynchronous clock) */
+#define TMR0_CLK_SRC_XTAL32 (TMR0_BCONR_ASYNCLKA | TMR0_BCONR_SYNSA) /*!< XTAL32 (Asynchronous clock) */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR0_Clock_Division TMR0 Clock Division
+ * @{
+ */
+#define TMR0_CLK_DIV1 (0UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK */
+#define TMR0_CLK_DIV2 (1UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/2 */
+#define TMR0_CLK_DIV4 (2UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/4 */
+#define TMR0_CLK_DIV8 (3UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/8 */
+#define TMR0_CLK_DIV16 (4UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/16 */
+#define TMR0_CLK_DIV32 (5UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/32 */
+#define TMR0_CLK_DIV64 (6UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/64 */
+#define TMR0_CLK_DIV128 (7UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/128 */
+#define TMR0_CLK_DIV256 (8UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/256 */
+#define TMR0_CLK_DIV512 (9UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/512 */
+#define TMR0_CLK_DIV1024 (10UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/1024 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR0_Function TMR0 Function
+ * @{
+ */
+#define TMR0_FUNC_CMP (0UL) /*!< Output compare function */
+#define TMR0_FUNC_CAPT (TMR0_BCONR_CAPMDA | TMR0_BCONR_HICPA) /*!< Input capture function */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR0_Interrupt TMR0 Interrupt
+ * @{
+ */
+#define TMR0_INT_CMP_A (TMR0_BCONR_INTENA)
+#define TMR0_INT_CMP_B (TMR0_BCONR_INTENB)
+#define TMR0_INT_ALL (TMR0_INT_CMP_A | TMR0_INT_CMP_B)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR0_FLAG TMR0 Flag
+ * @{
+ */
+#define TMR0_FLAG_CMP_A (TMR0_STFLR_CMFA)
+#define TMR0_FLAG_CMP_B (TMR0_STFLR_CMFB)
+#define TMR0_FLAG_REPEAT_CAPT_A (TMR0_STFLR_ICPA)
+#define TMR0_FLAG_REPEAT_CAPT_B (TMR0_STFLR_ICPB)
+#define TMR0_FLAG_ALL (TMR0_FLAG_CMP_A | TMR0_FLAG_CMP_B | TMR0_FLAG_REPEAT_CAPT_A | \
+ TMR0_FLAG_REPEAT_CAPT_B)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup TMR0_Global_Functions
+ * @{
+ */
+
+/* Initialization functions */
+void TMR0_DeInit(CM_TMR0_TypeDef *TMR0x);
+int32_t TMR0_Init(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, const stc_tmr0_init_t *pstcTmr0Init);
+int32_t TMR0_StructInit(stc_tmr0_init_t *pstcTmr0Init);
+void TMR0_Start(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch);
+void TMR0_Stop(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch);
+
+/* Control configuration functions */
+void TMR0_SetCountValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value);
+uint16_t TMR0_GetCountValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch);
+void TMR0_SetCompareValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value);
+uint16_t TMR0_GetCompareValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch);
+void TMR0_SetClockSrc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Src);
+void TMR0_SetClockDiv(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Div);
+void TMR0_SetFunc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Func);
+
+/* Hardware trigger Functions */
+void TMR0_HWCaptureCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState);
+void TMR0_HWStartCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState);
+void TMR0_HWStopCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState);
+void TMR0_HWClearCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState);
+
+/* Interrupt and flag management functions */
+void TMR0_IntCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32IntType, en_functional_state_t enNewState);
+en_flag_status_t TMR0_GetStatus(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag);
+void TMR0_ClearStatus(CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag);
+
+/**
+ * @}
+ */
+
+#endif /* LL_TMR0_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_TMR0_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_tmr2.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_tmr2.h
new file mode 100644
index 0000000000..54d571027f
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_tmr2.h
@@ -0,0 +1,356 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_tmr2.h
+ * @brief This file contains all the functions prototypes of the TMR2(Timer2)
+ * driver library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Modify typo
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_TMR2_H__
+#define __HC32_LL_TMR2_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_TMR2
+ * @{
+ */
+#if (LL_TMR2_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup TMR2_Global_Types TMR2 Global Types
+ * @{
+ */
+
+/**
+ * @brief TMR2 PWM configuration structure.
+ */
+typedef struct {
+ uint32_t u32StartPolarity; /*!< Specifies the polarity of PWM output when TMR2 counting start.
+ This parameter can be a value of @ref TMR2_PWM_Polarity */
+ uint32_t u32StopPolarity; /*!< Specifies the polarity of PWM output when TMR2 counting stop.
+ This parameter can be a value of @ref TMR2_PWM_Polarity */
+ uint32_t u32CompareMatchPolarity; /*!< Specifies the polarity of PWM output when TMR2 counter matches the compare value.
+ This parameter can be a value of @ref TMR2_PWM_Polarity */
+} stc_tmr2_pwm_init_t;
+
+/**
+ * @brief TMR2 initialization structure.
+ */
+typedef struct {
+ uint32_t u32ClockSrc; /*!< Specifies the clock source for TMR2 channel.
+ This parameter can be a value of @ref TMR2_Clock_Source */
+ uint32_t u32ClockDiv; /*!< Specifies the division of the clock source.
+ This parameter can be a value of @ref TMR2_Clock_Divider */
+ uint32_t u32Func; /*!< Specifies the function mode for TMR2 channel.
+ This parameter can be a value of @ref TMR2_Function */
+ uint32_t u32CompareValue; /*!< Specifies the compare value.
+ This parameter can be a number between 0U and 0xFFFFU, inclusive. */
+} stc_tmr2_init_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup TMR2_Global_Macros TMR2 Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup TMR2_Channel TMR2 Channel
+ * @{
+ */
+#define TMR2_CH_A (0U) /*!< Channel A of TMR2. */
+#define TMR2_CH_B (1U) /*!< Channel B of TMR2. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR2_Function TMR2 Function
+ * @{
+ */
+#define TMR2_FUNC_CMP (0x0U) /*!< The function of TMR2 channel is ouput compare. */
+#define TMR2_FUNC_CAPT (TMR2_BCONR_CAPMDA) /*!< The function of TMR2 channel is input capture. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR2_Clock_Source TMR2 Clock Source
+ * @{
+ */
+#define TMR2_CLK_PCLK1 (0x0U) /*!< Synchronous clock source, PCLK1. */
+#define TMR2_CLK_TRIG_RISING (TMR2_BCONR_SYNCLKA_0) /*!< Synchronous clock source, rising edge of TIM2__TRIGA/B.
+ One rising edge causes one count. */
+#define TMR2_CLK_TRIG_FALLING (TMR2_BCONR_SYNCLKA_1) /*!< Synchronous clock source, falling edge of TIM2__TRIGA/B.
+ One falling edge causes one count. */
+#define TMR2_CLK_EVT (TMR2_BCONR_SYNCLKA) /*!< Synchronous clock source, peripheral event. The event is specified by register TMR2_HTSSR.
+ One event causes one count. */
+#define TMR2_CLK_TMR6_OVF (TMR2_BCONR_SYNCLKAT_0) /*!< Synchronous clock source, the event of counting overflow of TIMER6.
+ It is NOT need to set register TMR2_HTSSR. */
+#define TMR2_CLK_TMR6_UDF (TMR2_BCONR_SYNCLKAT_1) /*!< Synchronous clock source, the event of counting underflow of TIMER6.
+ It is NOT need to set register TMR2_HTSSR. */
+#define TMR2_CLK_TMR6_OVF_UDF (TMR2_BCONR_SYNCLKAT_0 | \
+ TMR2_BCONR_SYNCLKAT_1) /*!< Synchronous clock source, both overflow and underflow of TIMER6. */
+#define TMR2_CLK_LRC (TMR2_BCONR_SYNSA) /*!< Asynchronous clock source, LRC(32.768KHz). */
+#define TMR2_CLK_XTAL32 (TMR2_BCONR_ASYNCLKA_0 | \
+ TMR2_BCONR_SYNSA) /*!< Asynchronous clock source, XTAL32(32.768KHz). */
+#define TMR2_CLK_PIN_CLK (TMR2_BCONR_ASYNCLKA_1 | \
+ TMR2_BCONR_SYNSA) /*!< Asynchronous clock source, input from pin TIM2__CLKA/B. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR2_Clock_Divider TMR2 Clock Divider
+ * @{
+ */
+#define TMR2_CLK_DIV1 (0x0U) /*!< Clock source. */
+#define TMR2_CLK_DIV2 (0x1UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 2. */
+#define TMR2_CLK_DIV4 (0x2UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 4. */
+#define TMR2_CLK_DIV8 (0x3UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 8. */
+#define TMR2_CLK_DIV16 (0x4UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 16. */
+#define TMR2_CLK_DIV32 (0x5UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 32. */
+#define TMR2_CLK_DIV64 (0x6UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 64. */
+#define TMR2_CLK_DIV128 (0x7UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 128. */
+#define TMR2_CLK_DIV256 (0x8UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 256. */
+#define TMR2_CLK_DIV512 (0x9UL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 512. */
+#define TMR2_CLK_DIV1024 (0xAUL << TMR2_BCONR_CKDIVA_POS) /*!< Clock source / 1024. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR2_Interrupt_Type TMR2 Interrupt Type
+ * @{
+ */
+#define TMR2_INT_MATCH_CH_A (TMR2_ICONR_CMENA) /*!< TMR2 count match interrupt. */
+#define TMR2_INT_OVF_CH_A (TMR2_ICONR_OVENA) /*!< TMR2 count overflow interrupt. */
+#define TMR2_INT_MATCH_CH_B (TMR2_ICONR_CMENB) /*!< TMR2 count match interrupt. */
+#define TMR2_INT_OVF_CH_B (TMR2_ICONR_OVENB) /*!< TMR2 count overflow interrupt. */
+#define TMR2_INT_ALL (TMR2_INT_MATCH_CH_A | TMR2_INT_OVF_CH_A | \
+ TMR2_INT_MATCH_CH_B | TMR2_INT_OVF_CH_B)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR2_Status_Flag TMR2 Status Flag
+ * @{
+ */
+#define TMR2_FLAG_MATCH_CH_A (TMR2_STFLR_CMFA) /*!< Counter match flag of channel A. */
+#define TMR2_FLAG_OVF_CH_A (TMR2_STFLR_OVFA) /*!< Counter overflow flag channel A. */
+#define TMR2_FLAG_MATCH_CH_B (TMR2_STFLR_CMFB) /*!< Counter match flag channel B. */
+#define TMR2_FLAG_OVF_CH_B (TMR2_STFLR_OVFB) /*!< Counter overflow flag channel B. */
+#define TMR2_FLAG_CAPT_AGAIN_CH_A (TMR2_STFLR_ICPA) /*!< Capture occurs again after successful capture of channel A */
+#define TMR2_FLAG_CAPT_AGAIN_CH_B (TMR2_STFLR_ICPB) /*!< Capture occurs again after successful capture of channel B */
+#define TMR2_FLAG_ALL (TMR2_FLAG_MATCH_CH_A | TMR2_FLAG_OVF_CH_A | \
+ TMR2_FLAG_MATCH_CH_B | TMR2_FLAG_OVF_CH_B | \
+ TMR2_FLAG_CAPT_AGAIN_CH_A | TMR2_FLAG_CAPT_AGAIN_CH_B)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR2_Counter_State TMR2 Counter State
+ * @{
+ */
+#define TMR2_CNT_STAT_START (0U) /*!< Counter start counting. */
+#define TMR2_CNT_STAT_STOP (1U) /*!< Counter stop counting. */
+#define TMR2_CNT_STAT_MATCH_CMP (2U) /*!< Counter value matches the compare value. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR2_PWM_Polarity TMR2 PWM Polarity
+ * @{
+ */
+#define TMR2_PWM_LOW (0x0U) /*!< PWM output low. */
+#define TMR2_PWM_HIGH (0x1U) /*!< PWM output high. */
+#define TMR2_PWM_HOLD (0x2U) /*!< PWM output keeps the current polarity. */
+#define TMR2_PWM_INVT (0x3U) /*!< PWM output reverses the current polarity. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR2_Start_Condition TMR2 Start Condition
+ * @{
+ */
+#define TMR2_START_COND_INVD (0x0U) /*!< The start condition of TMR2 is INVALID. */
+#define TMR2_START_COND_TRIG_RISING (TMR2_HCONR_HSTAA0) /*!< The start condition of TMR2 is the rising edge of TIM2_x_PWMA/B. */
+#define TMR2_START_COND_TRIG_FALLING (TMR2_HCONR_HSTAA1) /*!< The start condition of TMR2 is the falling edge of TIM2_x_PWMA/B. */
+#define TMR2_START_COND_EVT (TMR2_HCONR_HSTAA2) /*!< The start condition of TMR2 is the specified event occurred. */
+#define TMR2_START_COND_ALL (TMR2_START_COND_TRIG_RISING | TMR2_START_COND_TRIG_FALLING | \
+ TMR2_START_COND_EVT)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR2_Stop_Condition TMR2 Stop Condition
+ * @{
+ */
+#define TMR2_STOP_COND_INVD (0x0U) /*!< The stop condition of TMR2 is INVALID. */
+#define TMR2_STOP_COND_TRIG_RISING (TMR2_HCONR_HSTPA0) /*!< The stop condition of TMR2 is the rising edge of TIM2_x_PWMA/B. */
+#define TMR2_STOP_COND_TRIG_FALLING (TMR2_HCONR_HSTPA1) /*!< The stop condition of TMR2 is the falling edge of TIM2_x_PWMA/B. */
+#define TMR2_STOP_COND_EVT (TMR2_HCONR_HSTPA2) /*!< The stop condition of TMR2 is the specified event occurred. */
+#define TMR2_STOP_COND_ALL (TMR2_STOP_COND_TRIG_RISING | TMR2_STOP_COND_TRIG_FALLING | \
+ TMR2_STOP_COND_EVT)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR2_Clear_Condition TMR2 Clear Condition
+ * @{
+ */
+#define TMR2_CLR_COND_INVD (0x0U) /*!< The clear condition of TMR2 is INVALID. */
+#define TMR2_CLR_COND_TRIG_RISING (TMR2_HCONR_HCLEA0) /*!< The clear(clear CNTAR/CNTBR) condition of TMR2 is the rising edge of TIM2_x_PWMA/B. */
+#define TMR2_CLR_COND_TRIG_FALLING (TMR2_HCONR_HCLEA1) /*!< The clear(clear CNTAR/CNTBR) condition of TMR2 is the falling edge of TIM2_x_PWMA/B. */
+#define TMR2_CLR_COND_EVT (TMR2_HCONR_HCLEA2) /*!< The clear(clear CNTAR/CNTBR) condition of TMR2 is the specified event occurred. */
+#define TMR2_CLR_COND_ALL (TMR2_CLR_COND_TRIG_RISING | TMR2_CLR_COND_TRIG_FALLING | \
+ TMR2_CLR_COND_EVT)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR2_Capture_Condition TMR2 Capture Condition
+ * @{
+ */
+#define TMR2_CAPT_COND_INVD (0x0U) /*!< The capture condition of TMR2 is INVALID. */
+#define TMR2_CAPT_COND_TRIG_RISING (TMR2_HCONR_HICPA0) /*!< The capture condition of TMR2 is the rising edge of TIM2_x_PWMA/B. */
+#define TMR2_CAPT_COND_TRIG_FALLING (TMR2_HCONR_HICPA1) /*!< The capture condition of TMR2 is the falling edge of TIM2_x_PWMA/B. */
+#define TMR2_CAPT_COND_EVT (TMR2_HCONR_HICPA2) /*!< The capture condition of TMR2 is the specified event occurred. */
+#define TMR2_CAPT_COND_ALL (TMR2_CAPT_COND_TRIG_RISING | TMR2_CAPT_COND_TRIG_FALLING | \
+ TMR2_CAPT_COND_EVT)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR2_Filter_Clock_Divider TMR2 Filter Clock Divider
+ * @{
+ */
+#define TMR2_FILTER_CLK_DIV1 (0x0U) /*!< The filter clock is the clock of timer2 / 1 */
+#define TMR2_FILTER_CLK_DIV4 (TMR2_PCONR_NOFICKA_0) /*!< The filter clock is the clock of timer2 / 4 */
+#define TMR2_FILTER_CLK_DIV16 (TMR2_PCONR_NOFICKA_1) /*!< The filter clock is the clock of timer2 / 16 */
+#define TMR2_FILTER_CLK_DIV64 (TMR2_PCONR_NOFICKA) /*!< The filter clock is the clock of timer2 / 64 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup TMR2_Global_Functions
+ * @{
+ */
+int32_t TMR2_Init(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, const stc_tmr2_init_t *pstcTmr2Init);
+int32_t TMR2_StructInit(stc_tmr2_init_t *pstcTmr2Init);
+void TMR2_DeInit(CM_TMR2_TypeDef *TMR2x);
+
+void TMR2_SetFunc(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Func);
+void TMR2_SetClockSrc(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Src);
+void TMR2_SetClockDiv(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Div);
+
+int32_t TMR2_PWM_StructInit(stc_tmr2_pwm_init_t *pstPwmInit);
+int32_t TMR2_PWM_Init(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, const stc_tmr2_pwm_init_t *pstPwmInit);
+void TMR2_PWM_OutputCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, en_functional_state_t enNewState);
+
+void TMR2_HWCaptureCondCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState);
+
+void TMR2_HWStartCondCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState);
+void TMR2_HWStopCondCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState);
+void TMR2_HWClearCondCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState);
+
+void TMR2_SetFilterClockDiv(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Div);
+void TMR2_FilterCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, en_functional_state_t enNewState);
+
+void TMR2_IntCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32IntType, en_functional_state_t enNewState);
+
+void TMR2_Start(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch);
+void TMR2_Stop(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch);
+
+en_flag_status_t TMR2_GetStatus(const CM_TMR2_TypeDef *TMR2x, uint32_t u32Flag);
+void TMR2_ClearStatus(CM_TMR2_TypeDef *TMR2x, uint32_t u32Flag);
+
+void TMR2_SetCompareValue(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Value);
+uint32_t TMR2_GetCompareValue(const CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch);
+
+void TMR2_SetCountValue(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Value);
+uint32_t TMR2_GetCountValue(const CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch);
+
+void TMR2_PWM_SetPolarity(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint8_t u8CountState, uint32_t u32Polarity);
+
+/**
+ * @}
+ */
+
+#endif /* LL_TMR2_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_TMR2_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_tmr4.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_tmr4.h
new file mode 100644
index 0000000000..48ec16c215
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_tmr4.h
@@ -0,0 +1,828 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_tmr4.h
+ * @brief This file contains all the functions prototypes of the TMR4
+ * driver library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Add the macros group @ref TMR4_OC_Output_Polarity
+ Modify typo
+ TMR4_OC_Buffer_Object group add macro-definition: TMR4_OC_BUF_NONE
+ 2023-09-30 CDT Rename macro-define: TMR4_INT_EVT_CMP_xx -> TMR4_INT_SCMP_EVTx
+ Rename macro-define: TMR4_FLAG_EVT_CMP_xx -> TMR4_FLAG_SCMP_EVTx
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_TMR4_H__
+#define __HC32_LL_TMR4_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_TMR4
+ * @{
+ */
+
+#if (LL_TMR4_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup TMR4_Global_Types TMR4 Global Types
+ * @{
+ */
+
+/**
+ * @brief TMR4 Counter function initialization configuration
+ * @note The TMR4 division(u16ClockDiv) is valid when clock source is the internal clock.
+ */
+typedef struct {
+ uint16_t u16ClockSrc; /*!< TMR4 counter clock source.
+ This parameter can be a value of @ref TMR4_Count_Clock_Source */
+ uint16_t u16ClockDiv; /*!< TMR4 counter internal clock division.
+ This parameter can be a value of @ref TMR4_Count_Clock_Division. */
+ uint16_t u16CountMode; /*!< TMR4 counter mode.
+ This parameter can be a value of @ref TMR4_Count_Mode */
+ uint16_t u16PeriodValue; /*!< TMR4 counter period value.
+ This parameter can be a value of half-word */
+} stc_tmr4_init_t;
+
+/**
+ * @brief The configuration of Output-Compare high channel(OUH/OVH/OWH)
+ */
+typedef union {
+ uint16_t OCMRx; /*!< OCMRxH(x=U/V/W) register */
+
+ struct { /*!< OCMRxH(x=U/V/W) register struct field bit */
+ uint16_t OCFDCH : 1; /*!< OCMRxh b0 High channel's OCF status when high channel match occurs at the condition that counter is counting down
+ This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
+ uint16_t OCFPKH : 1; /*!< OCMRxh b1 High channel's OCF status when high channel match occurs at the condition that counter count=Peak
+ This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
+ uint16_t OCFUCH : 1; /*!< OCMRxh b2 High channel's OCF status when high channel match occurs at the condition that counter is counting up
+ This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
+ uint16_t OCFZRH : 1; /*!< OCMRxh b3 High channel's OCF status when high channel match occurs at the condition that counter count=0x0000
+ This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
+ uint16_t OPDCH : 2; /*!< OCMRxh b5~b4 High channel's OP output status when high channel match occurs at the condition that counter is counting down
+ This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
+ uint16_t OPPKH : 2; /*!< OCMRxh b7~b6 High channel's OP output status when high channel match occurs at the condition that counter count=Peak
+ This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
+ uint16_t OPUCH : 2; /*!< OCMRxh b9~b8 High channel's OP output status when high channel match occurs at the condition that counter is counting up
+ This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
+ uint16_t OPZRH : 2; /*!< OCMRxh b11~b10 High channel's OP output status when high channel match occurs at the condition that counter count=0x0000
+ This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
+ uint16_t OPNPKH : 2; /*!< OCMRxh b13~b12 High channel's OP output status when high channel match doesn't occur at the condition that counter count=Peak
+ This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
+ uint16_t OPNZRH : 2; /*!< OCMRxh b15~b14 High channel's OP output status when high channel match doesn't occur at the condition that counter count=0x0000
+ This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
+ } OCMRx_f;
+} un_tmr4_oc_ocmrh_t;
+
+/**
+ * @brief The configuration of Output-Compare low channel(OUL/OVL/OWL)
+ */
+typedef union {
+ uint32_t OCMRx; /*!< OCMRxL(x=U/V/W) register */
+
+ struct { /*!< OCMRxL(x=U/V/W) register struct field bit*/
+ uint32_t OCFDCL : 1; /*!< OCMRxl b0 Low channel's OCF status when low channel match occurs at the condition that counter is counting down
+ This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
+ uint32_t OCFPKL : 1; /*!< OCMRxl b1 Low channel's OCF status when low channel match occurs at the condition that counter count=Peak
+ This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
+ uint32_t OCFUCL : 1; /*!< OCMRxl b2 Low channel's OCF status when low channel match occurs at the condition that counter is counting up
+ This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
+ uint32_t OCFZRL : 1; /*!< OCMRxl b3 Low channel's OCF status when low channel match occurs at the condition that counter count=0x0000
+ This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */
+ uint32_t OPDCL : 2; /*!< OCMRxl b5~b4 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter is counting down
+ This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
+ uint32_t OPPKL : 2; /*!< OCMRxl b7~b6 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter count=Peak
+ This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
+ uint32_t OPUCL : 2; /*!< OCMRxl b9~b8 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter is counting up
+ This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
+ uint32_t OPZRL : 2; /*!< OCMRxl b11~b10 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter count=0x0000
+ This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
+ uint32_t OPNPKL : 2; /*!< OCMRxl b13~b12 Low channel's OP output status when high channel not match and low channel not match occurs at the condition that counter count=Peak
+ This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
+ uint32_t OPNZRL : 2; /*!< OCMRxl b15~b14 Low channel's OP output status when high channel not match and low channel not match occurs at the condition that counter count=0x0000
+ This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
+ uint32_t EOPNDCL : 2; /*!< OCMRxl b17~b16 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter is counting down
+ This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
+ uint32_t EOPNUCL : 2; /*!< OCMRxl b19~b18 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter is counting up
+ This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
+ uint32_t EOPDCL : 2; /*!< OCMRxl b21~b20 Low channel's OP output status when high channel and low channel match occurs at the condition that counter is counting down
+ This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
+ uint32_t EOPPKL : 2; /*!< OCMRxl b23~b22 Low channel's OP output status when high channel and low channel match occurs at the condition that counter count=Peak
+ This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
+ uint32_t EOPUCL : 2; /*!< OCMRxl b25~b24 Low channel's OP output status when high channel and low channel match occurs at the condition that counter is counting up
+ This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
+ uint32_t EOPZRL : 2; /*!< OCMRxl b27~b26 Low channel's OP output status when high channel and low channel match occurs at the condition that counter count=0x0000
+ This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
+ uint32_t EOPNPKL : 2; /*!< OCMRxl b29~b28 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter count=Peak
+ This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
+ uint32_t EOPNZRL : 2; /*!< OCMRxl b31~b30 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter count=0x0000
+ This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */
+ } OCMRx_f;
+} un_tmr4_oc_ocmrl_t;
+
+/**
+ * @brief TMR4 Output-Compare(OC) initialization configuration
+ */
+typedef struct {
+ uint16_t u16CompareValue; /*!< TMR4 OC compare match value.
+ This parameter can be a value of half-word. */
+ uint16_t u16OcInvalidPolarity; /*!< Port output polarity when OC is disabled.
+ This parameter can be a value of @ref TMR4_OC_Invalid_Output_Polarity. */
+ uint16_t u16CompareModeBufCond; /*!< Register OCMR buffer transfer condition.
+ This parameter can be a value of @ref TMR4_OC_Buffer_Transfer_Condition. */
+ uint16_t u16CompareValueBufCond; /*!< Register OCCR buffer transfer condition.
+ This parameter can be a value of @ref TMR4_OC_Buffer_Transfer_Condition. */
+ uint16_t u16BufLinkTransObject; /*!< Enable the specified object(OCMR/OCCR) register buffer linked transfer with the counter interrupt mask.
+ This parameter can be a value of @ref TMR4_OC_Buffer_Object. */
+} stc_tmr4_oc_init_t;
+
+/**
+ * @brief TMR4 PWM initialization configuration
+ * @note The clock division(u16ClockDiv) is valid when TMR4 clock source is the internal clock.
+ */
+typedef struct {
+ uint16_t u16Mode; /*!< Select PWM mode
+ This parameter can be a value of @ref TMR4_PWM_Mode */
+ uint16_t u16ClockDiv; /*!< The internal clock division of PWM timer.
+ This parameter can be a value of @ref TMR4_PWM_Clock_Division. */
+ uint16_t u16Polarity; /*!< TMR4 PWM polarity
+ This parameter can be a value of @ref TMR4_PWM_Polarity */
+} stc_tmr4_pwm_init_t;
+
+/**
+ * @brief TMR4 Special-Event(EVT) initialization configuration
+ */
+typedef struct {
+ uint16_t u16Mode; /*!< TMR4 event mode
+ This parameter can be a value of @ref TMR4_Event_Mode */
+ uint16_t u16CompareValue; /*!< TMR4 event compare match value.
+ This parameter can be a value of half-word */
+ uint16_t u16OutputEvent; /*!< TMR4 event output event when match count compare condition.
+ This parameter can be a value of @ref TMR4_Event_Output_Event */
+ uint16_t u16MatchCond; /*!< Enable the specified count compare type with counter count to generate event.
+ This parameter can be a value of @ref TMR4_Event_Match_Condition */
+} stc_tmr4_evt_init_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup TMR4_Global_Macros TMR4 Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup TMR4_Counter_Macros TMR4 Counter Macros
+ * @{
+ */
+
+/**
+ * @defgroup TMR4_Count_Clock_Source TMR4 Count Clock Source
+ * @{
+ */
+#define TMR4_CLK_SRC_INTERNCLK (0U)
+#define TMR4_CLK_SRC_EXTCLK (TMR4_CCSR_ECKEN)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_Count_Clock_Division TMR4 Count Clock Division
+ * @{
+ */
+#define TMR4_CLK_DIV1 (0U << TMR4_CCSR_CKDIV_POS) /*!< CLK */
+#define TMR4_CLK_DIV2 (1U << TMR4_CCSR_CKDIV_POS) /*!< CLK/2 */
+#define TMR4_CLK_DIV4 (2U << TMR4_CCSR_CKDIV_POS) /*!< CLK/4 */
+#define TMR4_CLK_DIV8 (3U << TMR4_CCSR_CKDIV_POS) /*!< CLK/8 */
+#define TMR4_CLK_DIV16 (4U << TMR4_CCSR_CKDIV_POS) /*!< CLK/16 */
+#define TMR4_CLK_DIV32 (5U << TMR4_CCSR_CKDIV_POS) /*!< CLK/32 */
+#define TMR4_CLK_DIV64 (6U << TMR4_CCSR_CKDIV_POS) /*!< CLK/64 */
+#define TMR4_CLK_DIV128 (7U << TMR4_CCSR_CKDIV_POS) /*!< CLK/128 */
+#define TMR4_CLK_DIV256 (8U << TMR4_CCSR_CKDIV_POS) /*!< CLK/256 */
+#define TMR4_CLK_DIV512 (9U << TMR4_CCSR_CKDIV_POS) /*!< CLK/512 */
+#define TMR4_CLK_DIV1024 (10U << TMR4_CCSR_CKDIV_POS) /*!< CLK/1024 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_Count_Mode TMR4 Count Mode
+ * @{
+ */
+#define TMR4_MD_SAWTOOTH (0U)
+#define TMR4_MD_TRIANGLE (TMR4_CCSR_MODE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_Flag TMR4 Flag
+ * @{
+ */
+#define TMR4_FLAG_CNT_PEAK ((uint32_t)TMR4_CCSR_IRQPF) /*!< Count peak flag */
+#define TMR4_FLAG_CNT_VALLEY ((uint32_t)TMR4_CCSR_IRQZF) /*!< Count valley flag */
+#define TMR4_FLAG_RELOAD_TMR_U (1UL << 0U) /*!< TMR4 PWM reload-timer flag - channel U */
+#define TMR4_FLAG_RELOAD_TMR_V (1UL << 4U) /*!< TMR4 PWM reload-timer flag - channel V */
+#define TMR4_FLAG_RELOAD_TMR_W (1UL << 8U) /*!< TMR4 PWM reload-timer flag - channel W */
+#define TMR4_FLAG_OC_CMP_UH (1UL << 16U) /*!< TMR4 output-compare compare flag - channel UH */
+#define TMR4_FLAG_OC_CMP_UL (1UL << 17U) /*!< TMR4 output-compare compare flag - channel UL */
+#define TMR4_FLAG_OC_CMP_VH (1UL << 18U) /*!< TMR4 output-compare compare flag - channel VH */
+#define TMR4_FLAG_OC_CMP_VL (1UL << 19U) /*!< TMR4 output-compare compare flag - channel VL */
+#define TMR4_FLAG_OC_CMP_WH (1UL << 20U) /*!< TMR4 output-compare compare flag - channel WH */
+#define TMR4_FLAG_OC_CMP_WL (1UL << 21U) /*!< TMR4 output-compare compare flag - channel WL */
+#define TMR4_FLAG_SCMP_EVT0 (1UL << 24U) /*!< TMR4 event-compare compare flag - event 0 */
+#define TMR4_FLAG_SCMP_EVT1 (1UL << 25U) /*!< TMR4 event-compare compare flag - event 1 */
+#define TMR4_FLAG_SCMP_EVT2 (1UL << 26U) /*!< TMR4 event-compare compare flag - event 2 */
+#define TMR4_FLAG_SCMP_EVT3 (1UL << 27U) /*!< TMR4 event-compare compare flag - event 3 */
+#define TMR4_FLAG_SCMP_EVT4 (1UL << 28U) /*!< TMR4 event-compare compare flag - event 4 */
+#define TMR4_FLAG_SCMP_EVT5 (1UL << 29U) /*!< TMR4 event-compare compare flag - event 5 */
+#define TMR4_FLAG_ALL (TMR4_FLAG_CNT_PEAK | TMR4_FLAG_CNT_VALLEY | TMR4_FLAG_RELOAD_TMR_U | \
+ TMR4_FLAG_RELOAD_TMR_V | TMR4_FLAG_RELOAD_TMR_W | TMR4_FLAG_OC_CMP_UH | \
+ TMR4_FLAG_OC_CMP_UL | TMR4_FLAG_OC_CMP_VH | TMR4_FLAG_OC_CMP_VL | \
+ TMR4_FLAG_OC_CMP_WH | TMR4_FLAG_OC_CMP_WL | TMR4_FLAG_SCMP_EVT0 | \
+ TMR4_FLAG_SCMP_EVT1 | TMR4_FLAG_SCMP_EVT2 | TMR4_FLAG_SCMP_EVT3 | \
+ TMR4_FLAG_SCMP_EVT4 | TMR4_FLAG_SCMP_EVT5)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_Interrupt TMR4 Interrupt
+ * @{
+ */
+#define TMR4_INT_CNT_PEAK ((uint32_t)TMR4_CCSR_IRQPEN) /*!< Count peak interrupt */
+#define TMR4_INT_CNT_VALLEY ((uint32_t)TMR4_CCSR_IRQZEN) /*!< Count valley interrupt */
+#define TMR4_INT_RELOAD_TMR_U (1UL << 0U) /*!< TMR4 PWM reload-timer interrupt - channel U */
+#define TMR4_INT_RELOAD_TMR_V (1UL << 1U) /*!< TMR4 PWM reload-timer interrupt - channel W */
+#define TMR4_INT_RELOAD_TMR_W (1UL << 2U) /*!< TMR4 PWM reload-timer interrupt - channel V */
+#define TMR4_INT_OC_CMP_UH (1UL << 16U) /*!< TMR4 output-compare compare interrupt - channel UH */
+#define TMR4_INT_OC_CMP_UL (1UL << 17U) /*!< TMR4 output-compare compare interrupt - channel UL */
+#define TMR4_INT_OC_CMP_VH (1UL << 18U) /*!< TMR4 output-compare compare interrupt - channel VH */
+#define TMR4_INT_OC_CMP_VL (1UL << 19U) /*!< TMR4 output-compare compare interrupt - channel VL */
+#define TMR4_INT_OC_CMP_WH (1UL << 20U) /*!< TMR4 output-compare compare interrupt - channel WH */
+#define TMR4_INT_OC_CMP_WL (1UL << 21U) /*!< TMR4 output-compare compare interrupt - channel WL */
+#define TMR4_INT_SCMP_EVT0 (1UL << 24U) /*!< TMR4 event-compare compare interrupt - event 0 */
+#define TMR4_INT_SCMP_EVT1 (1UL << 25U) /*!< TMR4 event-compare compare interrupt - event 1 */
+#define TMR4_INT_SCMP_EVT2 (1UL << 26U) /*!< TMR4 event-compare compare interrupt - event 2 */
+#define TMR4_INT_SCMP_EVT3 (1UL << 27U) /*!< TMR4 event-compare compare interrupt - event 3 */
+#define TMR4_INT_SCMP_EVT4 (1UL << 28U) /*!< TMR4 event-compare compare interrupt - event 4 */
+#define TMR4_INT_SCMP_EVT5 (1UL << 29U) /*!< TMR4 event-compare compare interrupt - event 5 */
+
+#define TMR4_INT_ALL (TMR4_INT_CNT_PEAK | TMR4_INT_CNT_VALLEY | TMR4_INT_RELOAD_TMR_U | \
+ TMR4_INT_RELOAD_TMR_V | TMR4_INT_RELOAD_TMR_W | TMR4_INT_OC_CMP_UH | \
+ TMR4_INT_OC_CMP_UL | TMR4_INT_OC_CMP_VH | TMR4_INT_OC_CMP_VL | \
+ TMR4_INT_OC_CMP_WH | TMR4_INT_OC_CMP_WL | TMR4_INT_SCMP_EVT0 | \
+ TMR4_INT_SCMP_EVT1 | TMR4_INT_SCMP_EVT2 | TMR4_INT_SCMP_EVT3 | \
+ TMR4_INT_SCMP_EVT4 | TMR4_INT_SCMP_EVT5)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_Count_Interrupt_Mask_Time TMR4 Count Interrupt Mask Time
+ * @{
+ */
+#define TMR4_INT_CNT_MASK0 (0U) /*!< Counter interrupt flag is always set(not masked) for counter count every time at "0x0000" or peak */
+#define TMR4_INT_CNT_MASK1 (1U) /*!< Counter interrupt flag is set once when counter counts 2 times at "0x0000" or peak (skipping 1 count) */
+#define TMR4_INT_CNT_MASK2 (2U) /*!< Counter interrupt flag is set once when counter counts 3 times at "0x0000" or peak (skipping 2 count) */
+#define TMR4_INT_CNT_MASK3 (3U) /*!< Counter interrupt flag is set once when counter counts 4 times at "0x0000" or peak (skipping 3 count) */
+#define TMR4_INT_CNT_MASK4 (4U) /*!< Counter interrupt flag is set once when counter counts 5 times at "0x0000" or peak (skipping 4 count) */
+#define TMR4_INT_CNT_MASK5 (5U) /*!< Counter interrupt flag is set once when counter counts 6 times at "0x0000" or peak (skipping 5 count) */
+#define TMR4_INT_CNT_MASK6 (6U) /*!< Counter interrupt flag is set once when counter counts 7 times at "0x0000" or peak (skipping 6 count) */
+#define TMR4_INT_CNT_MASK7 (7U) /*!< Counter interrupt flag is set once when counter counts 8 times at "0x0000" or peak (skipping 7 count) */
+#define TMR4_INT_CNT_MASK8 (8U) /*!< Counter interrupt flag is set once when counter counts 9 times at "0x0000" or peak (skipping 8 count) */
+#define TMR4_INT_CNT_MASK9 (9U) /*!< Counter interrupt flag is set once when counter counts 10 times at "0x0000" or peak (skipping 9 count) */
+#define TMR4_INT_CNT_MASK10 (10U) /*!< Counter interrupt flag is set once when counter counts 11 times at "0x0000" or peak (skipping 10 count) */
+#define TMR4_INT_CNT_MASK11 (11U) /*!< Counter interrupt flag is set once when counter counts 12 times at "0x0000" or peak (skipping 11 count) */
+#define TMR4_INT_CNT_MASK12 (12U) /*!< Counter interrupt flag is set once when counter counts 13 times at "0x0000" or peak (skipping 12 count) */
+#define TMR4_INT_CNT_MASK13 (13U) /*!< Counter interrupt flag is set once when counter counts 14 times at "0x0000" or peak (skipping 13 count) */
+#define TMR4_INT_CNT_MASK14 (14U) /*!< Counter interrupt flag is set once when counter counts 15 times at "0x0000" or peak (skipping 14 count) */
+#define TMR4_INT_CNT_MASK15 (15U) /*!< Counter interrupt flag is set once when counter counts 16 times at "0x0000" or peak (skipping 15 count) */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_Output_Compare_Macros TMR4 Output-Compare Macros
+ * @{
+ */
+
+/**
+ * @defgroup TMR4_OC_Channel TMR4 OC Channel
+ * @{
+ */
+#define TMR4_OC_CH_UH (0UL) /*!< TMR4 OC channel:UH */
+#define TMR4_OC_CH_UL (1UL) /*!< TMR4 OC channel:UL */
+#define TMR4_OC_CH_VH (2UL) /*!< TMR4 OC channel:VH */
+#define TMR4_OC_CH_VL (3UL) /*!< TMR4 OC channel:VL */
+#define TMR4_OC_CH_WH (4UL) /*!< TMR4 OC channel:WH */
+#define TMR4_OC_CH_WL (5UL) /*!< TMR4 OC channel:WL */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_OC_Invalid_Output_Polarity TMR4 OC Invalid Output Polarity
+ * @{
+ */
+#define TMR4_OC_INVD_LOW (0U) /*!< TMR4 OC Output low level when OC is invalid */
+#define TMR4_OC_INVD_HIGH (TMR4_OCSR_OCPH) /*!< TMR4 OC Output high level when OC is invalid */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_OC_Output_Polarity TMR4 OC Output Polarity
+ * @{
+ */
+#define TMR4_OC_PORT_LOW (0U) /*!< TMR4 OC Output low level */
+#define TMR4_OC_PORT_HIGH (TMR4_OCSR_OCPH) /*!< TMR4 OC Output high level */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_OC_Buffer_Object TMR4 OC Buffer Object
+ * @{
+ */
+#define TMR4_OC_BUF_NONE (0x00U) /*!< Disable the buffer function of OCCR/OCMR */
+#define TMR4_OC_BUF_CMP_VALUE (0x01U) /*!< The register OCCR buffer function */
+#define TMR4_OC_BUF_CMP_MD (0x02U) /*!< The register OCMR buffer function */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_OC_Buffer_Transfer_Condition TMR4 OC OCCR Buffer Transfer Condition
+ * @{
+ */
+#define TMR4_OC_BUF_COND_IMMED (0U) /*!< Buffer transfer is made when writing to the OCCR/OCMR register. */
+#define TMR4_OC_BUF_COND_VALLEY (1U) /*!< Buffer transfer is made when counter count valley */
+#define TMR4_OC_BUF_COND_PEAK (2U) /*!< Buffer transfer is made when counter count peak */
+#define TMR4_OC_BUF_COND_PEAK_VALLEY (3U) /*!< Buffer transfer is made when counter count peak or valley */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_OC_Count_Match_OCF_State TMR4 OC Count Match OCF State
+ * @{
+ */
+#define TMR4_OC_OCF_HOLD (0U) /*!< Hold OCF when the TMR4 OC count match */
+#define TMR4_OC_OCF_SET (TMR4_OCMRH_OCFDCH) /*!< Set OCF when the TMR4 OC count match */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_OC_Count_Match_Output_Polarity TMR4 OC Count Match Output Polarity
+ * @{
+ */
+#define TMR4_OC_HOLD (0U) /*!< Hold output when the TMR4 OC count match */
+#define TMR4_OC_HIGH (1U) /*!< Output high when the TMR4 OC count match */
+#define TMR4_OC_LOW (2U) /*!< Output low when the TMR4 OC count match */
+#define TMR4_OC_INVT (3U) /*!< Invert output when the TMR4 OC count match */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_PWM_Macros TMR4 PWM Macros
+ * @{
+ */
+
+/**
+ * @defgroup TMR4_PWM_Channel TMR4 PWM Channel
+ * @{
+ */
+#define TMR4_PWM_CH_U (0UL) /*!< TMR4 PWM couple channel: U */
+#define TMR4_PWM_CH_V (1UL) /*!< TMR4 PWM couple channel: V */
+#define TMR4_PWM_CH_W (2UL) /*!< TMR4 PWM couple channel: W */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_PWM_Pin TMR4 PWM Pin
+ * @{
+ */
+#define TMR4_PWM_PIN_OUH (0UL) /*!< TMR4 PWM port: TIM4__OUH */
+#define TMR4_PWM_PIN_OUL (1UL) /*!< TMR4 PWM port: TIM4__OUL */
+#define TMR4_PWM_PIN_OVH (2UL) /*!< TMR4 PWM port: TIM4__OVH */
+#define TMR4_PWM_PIN_OVL (3UL) /*!< TMR4 PWM port: TIM4__OVL */
+#define TMR4_PWM_PIN_OWH (4UL) /*!< TMR4 PWM port: TIM4__OWH */
+#define TMR4_PWM_PIN_OWL (5UL) /*!< TMR4 PWM port: TIM4__OWL */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_PWM_Clock_Division TMR4 PWM Clock Division
+ * @{
+ */
+#define TMR4_PWM_CLK_DIV1 (0U) /*!< CLK */
+#define TMR4_PWM_CLK_DIV2 (1U << TMR4_POCR_DIVCK_POS) /*!< CLK/2 */
+#define TMR4_PWM_CLK_DIV4 (2U << TMR4_POCR_DIVCK_POS) /*!< CLK/8 */
+#define TMR4_PWM_CLK_DIV8 (3U << TMR4_POCR_DIVCK_POS) /*!< CLK/8 */
+#define TMR4_PWM_CLK_DIV16 (4U << TMR4_POCR_DIVCK_POS) /*!< CLK/16 */
+#define TMR4_PWM_CLK_DIV32 (5U << TMR4_POCR_DIVCK_POS) /*!< CLK/32 */
+#define TMR4_PWM_CLK_DIV64 (6U << TMR4_POCR_DIVCK_POS) /*!< CLK/64 */
+#define TMR4_PWM_CLK_DIV128 (7U << TMR4_POCR_DIVCK_POS) /*!< CLK/128 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_PWM_Mode TMR4 PWM Mode
+ * @{
+ */
+#define TMR4_PWM_MD_THROUGH (0U) /*!< Through mode */
+#define TMR4_PWM_MD_DEAD_TMR (TMR4_POCR_PWMMD_0) /*!< Dead timer mode */
+#define TMR4_PWM_MD_DEAD_TMR_FILTER (TMR4_POCR_PWMMD_1) /*!< Dead timer filter mode */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_PWM_Polarity TMR4 PWM Polarity
+ * @{
+ */
+#define TMR4_PWM_OXH_HOLD_OXL_HOLD (0U) /*!< Output PWML and PWMH signals without changing the level */
+#define TMR4_PWM_OXH_INVT_OXL_INVT (TMR4_POCR_LVLS_0) /*!< Output both PWML and PWMH signals reversed */
+#define TMR4_PWM_OXH_INVT_OXL_HOLD (TMR4_POCR_LVLS_1) /*!< Output the PWMH signal reversed, outputs the PWML signal without changing the level. */
+#define TMR4_PWM_OXH_HOLD_OXL_INVT (TMR4_POCR_LVLS) /*!< Output the PWMH signal without changing the level, Outputs the PWML signal reversed. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_PWM_Dead_Time_Register_Index TMR4 PWM Dead Time Register Index
+ * @{
+ */
+#define TMR4_PWM_PDAR_IDX (0UL) /*!< TMR4_PDARn(n=U/V/W) */
+#define TMR4_PWM_PDBR_IDX (1UL) /*!< TMR4_PDBRn(n=U/V/W) */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_PWM_Abnormal_Pin_Status TMR4 PWM Abnormal Pin Status
+ * @{
+ */
+#define TMR4_PWM_ABNORMAL_PIN_NORMAL (0UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) output normal */
+#define TMR4_PWM_ABNORMAL_PIN_HIZ (1UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) to Hi-z */
+#define TMR4_PWM_ABNORMAL_PIN_LOW (2UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) output low level */
+#define TMR4_PWM_ABNORMAL_PIN_HIGH (3UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) output high level */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_PWM_Pin_Output_Mode TMR4 PWM Pin Mode
+ * @{
+ */
+#define TMR4_PWM_PIN_OUTPUT_OS (0UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) output polarity by specified register TMR4_PSCR.OSxy */
+#define TMR4_PWM_PIN_OUTPUT_NORMAL (TMR4_PSCR_OEUH) /*!< TIM4__Oxy(x=U/V/W, y=H/L) output normal PWM */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_PWM_OE_Bit_Effect_Time TMR4 PWM Register TMR4_PSCR.OE Bit Effect Time
+ * @{
+ */
+#define TMR4_PWM_OE_EFFECT_IMMED (TMR4_PSCR_ODT_0) /*!< TMR4 PWM register TMR4_PSCR.OE bit immediate effect. */
+#define TMR4_PWM_OE_EFFECT_COUNT_PEAK (TMR4_PSCR_ODT) /*!< TMR4 PWM register TMR4_PSCR.OE bit effect when TMR4 counter count peak. */
+#define TMR4_PWM_OE_EFFECT_COUNT_VALLEY (TMR4_PSCR_ODT_1) /*!< TMR4 PWM register TMR4_PSCR.OE bit effect when TMR4 counter count valley. */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_Event_Macros TMR4 Event Macros
+ * @{
+ */
+
+/**
+ * @defgroup TMR4_Event_Channel TMR4 Event Channel
+ * @{
+ */
+#define TMR4_EVT_CH_UH (0UL) /*!< TMR4 EVT channel:UH */
+#define TMR4_EVT_CH_UL (1UL) /*!< TMR4 EVT channel:UL */
+#define TMR4_EVT_CH_VH (2UL) /*!< TMR4 EVT channel:VH */
+#define TMR4_EVT_CH_VL (3UL) /*!< TMR4 EVT channel:VL */
+#define TMR4_EVT_CH_WH (4UL) /*!< TMR4 EVT channel:WH */
+#define TMR4_EVT_CH_WL (5UL) /*!< TMR4 EVT channel:WL */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_Event_Match_Condition TMR4 Event Match Condition
+ * @{
+ */
+#define TMR4_EVT_MATCH_CNT_UP (TMR4_SCSR_UEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count up */
+#define TMR4_EVT_MATCH_CNT_DOWN (TMR4_SCSR_DEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count down */
+#define TMR4_EVT_MATCH_CNT_PEAK (TMR4_SCSR_PEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count peak */
+#define TMR4_EVT_MATCH_CNT_VALLEY (TMR4_SCSR_ZEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count valley */
+#define TMR4_EVT_MATCH_CNT_ALL (TMR4_EVT_MATCH_CNT_DOWN | TMR4_EVT_MATCH_CNT_UP | \
+ TMR4_EVT_MATCH_CNT_PEAK | TMR4_EVT_MATCH_CNT_VALLEY)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_Event_Mask TMR4 Event Mask
+ * @{
+ */
+#define TMR4_EVT_MASK_PEAK (TMR4_SCMR_MPCE) /*!< Match with the count peak interrupt mask of the counter */
+#define TMR4_EVT_MASK_VALLEY (TMR4_SCMR_MZCE) /*!< Match with the count valley interrupt mask of the counter */
+#define TMR4_EVT_MASK_TYPE_ALL (TMR4_EVT_MASK_PEAK | TMR4_EVT_MASK_VALLEY)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_Event_Buffer_Transfer_Condition TMR4 Event Buffer Transfer Condition
+ * @{
+ */
+#define TMR4_EVT_BUF_COND_IMMED (0U) /*!< Register SCCR&SCMR buffer transfer when writing to the SCCR&SCMR register */
+#define TMR4_EVT_BUF_COND_VALLEY (TMR4_SCSR_BUFEN_0) /*!< Register SCCR&SCMR buffer transfer when counter count valley */
+#define TMR4_EVT_BUF_COND_PEAK (TMR4_SCSR_BUFEN_1) /*!< Register SCCR&SCMR buffer transfer when counter count peak */
+#define TMR4_EVT_BUF_COND_PEAK_VALLEY (TMR4_SCSR_BUFEN) /*!< Register SCCR&SCMR buffer transfer when counter count peak or valley */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_Event_Mode TMR4 Event Mode
+ * @{
+ */
+#define TMR4_EVT_MD_CMP (0U) /*!< TMR4 EVT compare mode */
+#define TMR4_EVT_MD_DELAY (TMR4_SCSR_EVTMS) /*!< TMR4 EVT delay mode */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_Event_Delay_Object TMR4 Event Delay Object
+ * @{
+ */
+#define TMR4_EVT_DELAY_OCCRXH (0U) /*!< TMR4 EVT delay object: OCCRxh(x=u/v/w) */
+#define TMR4_EVT_DELAY_OCCRXL (TMR4_SCSR_EVTDS) /*!< TMR4 EVT delay object: OCCRxl(x=u/v/w) */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_Event_Mask_Times TMR4 Event Mask Times
+ * @{
+ */
+#define TMR4_EVT_MASK0 (0U << TMR4_SCMR_AMC_POS) /*!< Mask 0 time */
+#define TMR4_EVT_MASK1 (1U << TMR4_SCMR_AMC_POS) /*!< Mask 1 times */
+#define TMR4_EVT_MASK2 (2U << TMR4_SCMR_AMC_POS) /*!< Mask 2 times */
+#define TMR4_EVT_MASK3 (3U << TMR4_SCMR_AMC_POS) /*!< Mask 3 times */
+#define TMR4_EVT_MASK4 (4U << TMR4_SCMR_AMC_POS) /*!< Mask 4 times */
+#define TMR4_EVT_MASK5 (5U << TMR4_SCMR_AMC_POS) /*!< Mask 5 times */
+#define TMR4_EVT_MASK6 (6U << TMR4_SCMR_AMC_POS) /*!< Mask 6 times */
+#define TMR4_EVT_MASK7 (7U << TMR4_SCMR_AMC_POS) /*!< Mask 7 times */
+#define TMR4_EVT_MASK8 (8U << TMR4_SCMR_AMC_POS) /*!< Mask 8 times */
+#define TMR4_EVT_MASK9 (9U << TMR4_SCMR_AMC_POS) /*!< Mask 9 times */
+#define TMR4_EVT_MASK10 (10U << TMR4_SCMR_AMC_POS) /*!< Mask 10 times */
+#define TMR4_EVT_MASK11 (11U << TMR4_SCMR_AMC_POS) /*!< Mask 11 times */
+#define TMR4_EVT_MASK12 (12U << TMR4_SCMR_AMC_POS) /*!< Mask 12 times */
+#define TMR4_EVT_MASK13 (13U << TMR4_SCMR_AMC_POS) /*!< Mask 13 times */
+#define TMR4_EVT_MASK14 (14U << TMR4_SCMR_AMC_POS) /*!< Mask 14 times */
+#define TMR4_EVT_MASK15 (15U << TMR4_SCMR_AMC_POS) /*!< Mask 15 times */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_Event_Output_Event TMR4 Event Output Event
+ * @{
+ */
+#define TMR4_EVT_OUTPUT_EVT0 (0U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 0 */
+#define TMR4_EVT_OUTPUT_EVT1 (1U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 1 */
+#define TMR4_EVT_OUTPUT_EVT2 (2U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 2 */
+#define TMR4_EVT_OUTPUT_EVT3 (3U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 3 */
+#define TMR4_EVT_OUTPUT_EVT4 (4U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 4 */
+#define TMR4_EVT_OUTPUT_EVT5 (5U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 5 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_Event_Output_Signal TMR4 Event Output Signal
+ * @{
+ */
+#define TMR4_EVT_OUTPUT_NONE (0U) /*!< Disable output event signal of TMR4 Special-EVT */
+#define TMR4_EVT_OUTPUT_EVT0_SIGNAL (1U) /*!< Output the specified event 0 signal of TMR4 Special-EVT */
+#define TMR4_EVT_OUTPUT_EVT1_SIGNAL (2U) /*!< Output the specified event 1 signal of TMR4 Special-EVT */
+#define TMR4_EVT_OUTPUT_EVT2_SIGNAL (3U) /*!< Output the specified event 2 signal of TMR4 Special-EVT */
+#define TMR4_EVT_OUTPUT_EVT3_SIGNAL (4U) /*!< Output the specified event 3 signal of TMR4 Special-EVT */
+#define TMR4_EVT_OUTPUT_EVT4_SIGNAL (5U) /*!< Output the specified event 4 signal of TMR4 Special-EVT */
+#define TMR4_EVT_OUTPUT_EVT5_SIGNAL (6U) /*!< Output the specified event 5 signal of TMR4 Special-EVT */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup TMR4_Global_Functions
+ * @{
+ */
+
+/**
+ * @addtogroup TMR4_Counter_Global_Functions
+ * @{
+ */
+
+/* Initialization and configuration TMR4 counter functions */
+int32_t TMR4_StructInit(stc_tmr4_init_t *pstcTmr4Init);
+int32_t TMR4_Init(CM_TMR4_TypeDef *TMR4x, const stc_tmr4_init_t *pstcTmr4Init);
+int32_t TMR4_DeInit(CM_TMR4_TypeDef *TMR4x);
+void TMR4_SetClockSrc(CM_TMR4_TypeDef *TMR4x, uint16_t u16Src);
+void TMR4_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint16_t u16Div);
+void TMR4_SetCountMode(CM_TMR4_TypeDef *TMR4x, uint16_t u16Mode);
+uint16_t TMR4_GetPeriodValue(const CM_TMR4_TypeDef *TMR4x);
+void TMR4_SetPeriodValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value);
+uint16_t TMR4_GetCountValue(const CM_TMR4_TypeDef *TMR4x);
+void TMR4_SetCountValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value);
+void TMR4_ClearCountValue(CM_TMR4_TypeDef *TMR4x);
+void TMR4_Start(CM_TMR4_TypeDef *TMR4x);
+void TMR4_Stop(CM_TMR4_TypeDef *TMR4x);
+void TMR4_ClearStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag);
+en_flag_status_t TMR4_GetStatus(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag);
+void TMR4_IntCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, en_functional_state_t enNewState);
+void TMR4_PeriodBufCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState);
+uint16_t TMR4_GetCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType);
+void TMR4_SetCountIntMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, uint16_t u16MaskTime);
+uint16_t TMR4_GetCurrentCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType);
+void TMR4_PortOutputCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState);
+void TMR4_HWStartCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState);
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup TMR4_Output_Compare_Global_Functions
+ * @{
+ */
+
+/* Initialization and configuration TMR4 Output-Compare functions */
+int32_t TMR4_OC_StructInit(stc_tmr4_oc_init_t *pstcTmr4OcInit);
+int32_t TMR4_OC_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_oc_init_t *pstcTmr4OcInit);
+void TMR4_OC_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
+uint16_t TMR4_OC_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
+void TMR4_OC_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value);
+void TMR4_OC_Cmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState);
+void TMR4_OC_ExtendControlCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState);
+void TMR4_OC_BufIntervalResponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch,
+ uint16_t u16Object, en_functional_state_t enNewState);
+uint16_t TMR4_OC_GetPolarity(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
+void TMR4_OC_SetOcInvalidPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity);
+void TMR4_OC_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object, uint16_t u16BufCond);
+uint16_t TMR4_OC_GetHighChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
+void TMR4_OC_SetHighChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrh_t unTmr4Ocmrh);
+uint32_t TMR4_OC_GetLowChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
+void TMR4_OC_SetLowChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrl_t unTmr4Ocmrl);
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup TMR4_PWM_Global_Functions
+ * @{
+ */
+
+/* Initialization and configuration TMR4 PWM functions */
+int32_t TMR4_PWM_StructInit(stc_tmr4_pwm_init_t *pstcTmr4PwmInit);
+int32_t TMR4_PWM_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_pwm_init_t *pstcTmr4PwmInit);
+void TMR4_PWM_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
+void TMR4_PWM_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Div);
+void TMR4_PWM_SetPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity);
+void TMR4_PWM_StartReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
+void TMR4_PWM_StopReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
+void TMR4_PWM_SetFilterCountValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value);
+void TMR4_PWM_SetDeadTimeValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex, uint16_t u16Value);
+uint16_t TMR4_PWM_GetDeadTimeValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex);
+void TMR4_PWM_SetAbnormalPinStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32PwmPin, uint32_t u32PinStatus);
+void TMR4_PWM_SetOEEffectTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32Time);
+void TMR4_PWM_EmbHWMainOutputCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState);
+void TMR4_PWM_MainOutputCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState);
+void TMR4_PWM_SetPortOutputMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32PwmPin, uint32_t u32Mode);
+
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup TMR4_Event_Global_Functions
+ * @{
+ */
+
+/* Initialization and configuration TMR4 event functions */
+int32_t TMR4_EVT_StructInit(stc_tmr4_evt_init_t *pstcTmr4EventInit);
+int32_t TMR4_EVT_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_evt_init_t *pstcTmr4EventInit);
+void TMR4_EVT_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
+void TMR4_EVT_SetDelayObject(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object);
+void TMR4_EVT_SetMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16MaskTime);
+uint16_t TMR4_EVT_GetMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
+void TMR4_EVT_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value);
+uint16_t TMR4_EVT_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch);
+void TMR4_EVT_SetOutputEvent(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Event);
+void TMR4_EVT_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16BufCond);
+void TMR4_EVT_BufIntervalResponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState);
+void TMR4_EVT_EventIntervalResponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch,
+ uint16_t u16MaskType, en_functional_state_t enNewState);
+void TMR4_EVT_MatchCondCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState);
+void TMR4_EVT_SetOutputEventSignal(CM_TMR4_TypeDef *TMR4x, uint16_t u16Signal);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* LL_TMR4_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_TMR4_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_tmr6.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_tmr6.h
new file mode 100644
index 0000000000..80d40ebcd7
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_tmr6.h
@@ -0,0 +1,935 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_tmr6.h
+ * @brief This file contains all the functions prototypes of the TMR6 driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Delete union in stc_tmr6_init_t structure
+ 2023-09-30 CDT Modify macro define for group TMR6_Emb_Ch_Define
+ 2023-12-15 CDT Modify for headfile update: CM_TMR6CR -> CM_TMR6_COMMON
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_TMR6_H__
+#define __HC32_LL_TMR6_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_TMR6
+ * @{
+ */
+
+#if (LL_TMR6_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup TMR6_Global_Types TMR6 Global Types
+ * @{
+ */
+
+/**
+ * @brief Timer6 count function structure definition
+ */
+typedef struct {
+ uint8_t u8CountSrc; /*!< Specifies the count source @ref TMR6_Count_Src_Define */
+ struct {
+ uint32_t u32ClockDiv; /*!< Count clock division select, @ref TMR6_Count_Clock_Define */
+ uint32_t u32CountMode; /*!< Count mode, @ref TMR6_Count_Mode_Define */
+ uint32_t u32CountDir; /*!< Count direction, @ref TMR6_Count_Dir_Define */
+ } sw_count;
+ struct {
+ uint32_t u32CountUpCond; /*!< Hardware count up condition. @ref TMR6_HW_Count_Up_Cond_Define */
+ uint32_t u32CountDownCond; /*!< Hardware count down condition. @ref TMR6_HW_Count_Down_Cond_Define */
+ } hw_count;
+ uint32_t u32PeriodValue; /*!< The period reference value. (0x00 ~ 0xFFFF) or (0x00 ~ 0xFFFFFFFF) */
+ uint32_t u32CountReload; /*!< Count reload after overflow @ref TMR6_Count_Reload_Define */
+} stc_tmr6_init_t;
+
+/**
+ * @brief Timer6 pwm output function structure definition
+ */
+typedef struct {
+ uint32_t u32CompareValue; /*!< Range (0 ~ 0xFFFF) or (0 ~ 0xFFFFFFFF) */
+ uint32_t u32StartPolarity; /*!< Pin polarity when count start @ref TMR6_Pin_Polarity_Define */
+ uint32_t u32StopPolarity; /*!< Pin polarity when count stop @ref TMR6_Pin_Polarity_Define */
+ uint32_t u32CountUpMatchAPolarity; /*!< Port state when match compare register A(GCMAR) at count-up mode \
+ @ref TMR6_Pin_Polarity_Define */
+ uint32_t u32CountDownMatchAPolarity; /*!< Port state when match compare register A(GCMAR) at count-down mode \
+ @ref TMR6_Pin_Polarity_Define */
+ uint32_t u32CountUpMatchBPolarity; /*!< Port state when match compare register B(GCMBR) at count-up mode \
+ @ref TMR6_Pin_Polarity_Define*/
+ uint32_t u32CountDownMatchBPolarity; /*!< Port state when match compare register B(GCMBR) at count-down mode\
+ @ref TMR6_Pin_Polarity_Define */
+ uint32_t u32UdfPolarity; /*!< Pin polarity when underflow @ref TMR6_Pin_Polarity_Define */
+ uint32_t u32OvfPolarity; /*!< Pin polarity when overflow @ref TMR6_Pin_Polarity_Define */
+} stc_tmr6_pwm_init_t;
+
+/**
+ * @brief Timer6 buffer function configuration structure definition
+ */
+typedef struct {
+ uint32_t u32BufNum; /*!< The buffer number, and this parameter can be a value of \
+ @ref TMR6_Buf_Num_Define */
+ uint32_t u32BufTransCond; /*!< The buffer send time, and this parameter can be a value of \
+ @ref TMR6_Buf_Trans_Cond_Define */
+} stc_tmr6_buf_config_t;
+
+/**
+ * @brief Timer6 Valid period function configuration structure definition
+ */
+typedef struct {
+ uint32_t u32CountCond; /*!< The count condition, and this parameter can be a value of \
+ @ref TMR6_Valid_Period_Count_Cond_Define */
+ uint32_t u32PeriodInterval; /*!< The interval of the valid period @ref TMR6_Valid_Period_Count_Define */
+} stc_tmr6_valid_period_config_t;
+
+/**
+ * @brief Timer6 EMB configuration structure definition
+ */
+typedef struct {
+ uint32_t u32ValidCh; /*!< Valid EMB event channel @ref TMR6_Emb_Ch_Define */
+ uint32_t u32ReleaseMode; /*!< Pin release mode when EMB event invalid @ref TMR6_Emb_Release_Mode_Define */
+ uint32_t u32PinStatus; /*!< Pin output status when EMB event valid @ref TMR6_Emb_Pin_Status_Define */
+} stc_tmr6_emb_config_t;
+
+/**
+ * @brief Timer6 Dead time function configuration structure definition
+ */
+typedef struct {
+ uint32_t u32EqualUpDown; /*!< Enable down count dead time register equal to up count DT register \
+ @ref TMR6_Deadtime_Reg_Equal_Func_Define */
+ uint32_t u32BufUp; /*!< Enable buffer transfer for up count dead time register (DTUBR-->DTUAR) \
+ @ref TMR6_Deadtime_CountUp_Buf_Func_Define*/
+ uint32_t u32BufDown; /*!< Enable buffer transfer for down count dead time register (DTDBR-->DTDAR) \
+ @ref TMR6_Deadtime_CountDown_Buf_Func_Define*/
+ uint32_t u32BufTransCond; /*!< Buffer transfer condition for triangular wave mode \
+ @ref TMR6_Deadtime_Buf_Trans_Cond_Define */
+} stc_tmr6_deadtime_config_t;
+
+/**
+ * @brief Timer6 Dead time function configuration structure definition
+ */
+typedef struct {
+ uint32_t u32ZMaskCycle; /*!< Z phase input mask periods selection @ref TMR6_Zmask_Cycle_Define */
+ uint32_t u32PosCountMaskFunc; /*!< As position count timer, clear function enable(TRUE) or disable(FALSE) during \
+ the time of Z phase input mask @ref TMR6_Zmask_Pos_Unit_Clear_Func_Define */
+ uint32_t u32RevoCountMaskFunc; /*!< As revolution count timer, the counter function enable(TRUE) or disable(FALSE) \
+ during the time of Z phase input mask \
+ @ref TMR6_Zmask_Revo_Unit_Count_Func_Define*/
+} stc_tmr6_zmask_config_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup TMR6_Global_Macros TMR6 Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup TMR6_Count_Src_Define TMR6 Count Source Define
+ * @{
+ */
+#define TMR6_CNT_SRC_SW (0U) /*!< Timer6 normal count function */
+#define TMR6_CNT_SRC_HW (1U) /*!< Timer6 hardware count function */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Stat_Flag_Define TMR6 Status Flag Define
+ * @{
+ */
+#define TMR6_FLAG_MATCH_A (TMR6_STFLR_CMAF) /*!< GCMAR match counter */
+#define TMR6_FLAG_MATCH_B (TMR6_STFLR_CMBF) /*!< GCMBR match counter */
+#define TMR6_FLAG_MATCH_C (TMR6_STFLR_CMCF) /*!< GCMCR match counter */
+#define TMR6_FLAG_MATCH_D (TMR6_STFLR_CMDF) /*!< GCMDR match counter */
+#define TMR6_FLAG_MATCH_E (TMR6_STFLR_CMEF) /*!< GCMER match counter */
+#define TMR6_FLAG_MATCH_F (TMR6_STFLR_CMFF) /*!< GCMFR match counter */
+#define TMR6_FLAG_OVF (TMR6_STFLR_OVFF) /*!< Sawtooth wave counter overflow, \
+ Triangular wave peak point */
+#define TMR6_FLAG_UDF (TMR6_STFLR_UDFF) /*!< Sawtooth wave counter underflow, \
+ Triangular wave valley point */
+#define TMR6_FLAG_DEAD_TIME_ERR (TMR6_STFLR_DTEF) /*!< Dead time error */
+#define TMR6_FLAG_UP_CNT_SPECIAL_MATCH_A (TMR6_STFLR_CMSAUF) /*!< SCMAR match counter when count-up */
+#define TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_A (TMR6_STFLR_CMSADF) /*!< SCMAR match counter when count-down */
+#define TMR6_FLAG_UP_CNT_SPECIAL_MATCH_B (TMR6_STFLR_CMSBUF) /*!< SCMBR match counter when count-up */
+#define TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_B (TMR6_STFLR_CMSBDF) /*!< SCMBR match counter when count-down */
+#define TMR6_FLAG_CNT_DIR (TMR6_STFLR_DIRF) /*!< Count direction flag */
+#define TMR6_FLAG_CAPT_AGAIN_A (TMR6_STFLR_CMAF2) /*!< Capture A again flag */
+#define TMR6_FLAG_CAPT_AGAIN_B (TMR6_STFLR_CMBF2) /*!< Capture B again flag */
+
+#define TMR6_FLAG_CLR_ALL (0x0C001EFFUL) /*!< Clear all flag */
+#define TMR6_FLAG_ALL (TMR6_FLAG_MATCH_A | TMR6_FLAG_MATCH_B | TMR6_FLAG_MATCH_C | \
+ TMR6_FLAG_MATCH_D | TMR6_FLAG_MATCH_E | TMR6_FLAG_MATCH_F | \
+ TMR6_FLAG_OVF | TMR6_FLAG_UDF | TMR6_FLAG_DEAD_TIME_ERR | \
+ TMR6_FLAG_UP_CNT_SPECIAL_MATCH_A | TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_A | \
+ TMR6_FLAG_UP_CNT_SPECIAL_MATCH_B | TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_B | \
+ TMR6_FLAG_CNT_DIR | TMR6_FLAG_CAPT_AGAIN_A | TMR6_FLAG_CAPT_AGAIN_B)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Int_Flag_Define TMR6 Interrupt Flag Define
+ * @{
+ */
+#define TMR6_INT_MATCH_A (TMR6_ICONR_INTENA) /*!< GCMAR register matched */
+#define TMR6_INT_MATCH_B (TMR6_ICONR_INTENB) /*!< GCMBR register matched */
+#define TMR6_INT_MATCH_C (TMR6_ICONR_INTENC) /*!< GCMCR register matched */
+#define TMR6_INT_MATCH_D (TMR6_ICONR_INTEND) /*!< GCMDR register matched */
+#define TMR6_INT_MATCH_E (TMR6_ICONR_INTENE) /*!< GCMER register matched */
+#define TMR6_INT_MATCH_F (TMR6_ICONR_INTENF) /*!< GCMFR register matched */
+#define TMR6_INT_OVF (TMR6_ICONR_INTENOVF) /*!< Counter register overflow */
+#define TMR6_INT_UDF (TMR6_ICONR_INTENUDF) /*!< Counter register underflow */
+#define TMR6_INT_DEAD_TIME_ERR (TMR6_ICONR_INTENDTE) /*!< Dead time error */
+#define TMR6_INT_UP_CNT_SPECIAL_MATCH_A (TMR6_ICONR_INTENSAU) /*!< SCMAR register matched when count-up */
+#define TMR6_INT_DOWN_CNT_SPECIAL_MATCH_A (TMR6_ICONR_INTENSAD) /*!< SCMAR register matched when count-down */
+#define TMR6_INT_UP_CNT_SPECIAL_MATCH_B (TMR6_ICONR_INTENSBU) /*!< SCMBR register matched when count-up */
+#define TMR6_INT_DOWN_CNT_SPECIAL_MATCH_B (TMR6_ICONR_INTENSBD) /*!< SCMBR register matched when count-down */
+#define TMR6_INT_ALL (TMR6_INT_MATCH_A | TMR6_INT_MATCH_B | TMR6_INT_MATCH_C | TMR6_INT_MATCH_D |\
+ TMR6_INT_MATCH_E | TMR6_INT_MATCH_F | TMR6_INT_OVF | TMR6_INT_UDF | \
+ TMR6_INT_DEAD_TIME_ERR | TMR6_INT_UP_CNT_SPECIAL_MATCH_A | \
+ TMR6_INT_DOWN_CNT_SPECIAL_MATCH_A | TMR6_INT_UP_CNT_SPECIAL_MATCH_B | \
+ TMR6_INT_DOWN_CNT_SPECIAL_MATCH_B)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Period_Reg_Index_Define TMR6 Period Register Index Define
+ * @{
+ */
+#define TMR6_PERIOD_REG_A (0x00UL)
+#define TMR6_PERIOD_REG_B (0x01UL)
+#define TMR6_PERIOD_REG_C (0x02UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Compare_Reg_Index_Define TMR6 Compare Register Index Define
+ * @{
+ */
+#define TMR6_CMP_REG_A (0x00UL)
+#define TMR6_CMP_REG_B (0x01UL)
+#define TMR6_CMP_REG_C (0x02UL)
+#define TMR6_CMP_REG_D (0x03UL)
+#define TMR6_CMP_REG_E (0x04UL)
+#define TMR6_CMP_REG_F (0x05UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Count_Ch_Define TMR6 General/Special Compare Channel Define
+ * @{
+ */
+#define TMR6_CH_A (0x00UL)
+#define TMR6_CH_B (0x01UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Buf_Num_Define TMR6 Buffer Number Define
+ * @{
+ */
+#define TMR6_BUF_SINGLE (0x00UL)
+#define TMR6_BUF_DUAL (TMR6_BCONR_BSEA)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Buf_Trans_Cond_Define TMR6 Buffer Transfer Time Configuration Define
+ * @{
+ */
+#define TMR6_BUF_TRANS_INVD (0x00UL)
+#define TMR6_BUF_TRANS_OVF (0x00000004UL)
+#define TMR6_BUF_TRANS_UDF (0x00000008UL)
+#define TMR6_BUF_TRANS_OVF_UDF (0x0000000CUL)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Valid_Period_Count_Cond_Define TMR6 Valid Period Function Count Condition Define
+ * @{
+ */
+#define TMR6_VALID_PERIOD_INVD (0x00UL) /*!< Valid period function off */
+#define TMR6_VALID_PERIOD_CNT_COND_VALLEY (TMR6_VPERR_PCNTE_0) /*!< Count when Sawtooth waveform overflow and underflow, \
+ triangular wave valley */
+#define TMR6_VALID_PERIOD_CNT_COND_PEAK (TMR6_VPERR_PCNTE_1) /*!< Count when Sawtooth waveform overflow and underflow, \
+ triangular wave peak */
+#define TMR6_VALID_PERIOD_CNT_COND_VALLEY_PEAK (TMR6_VPERR_PCNTE) /*!< Count when Sawtooth waveform overflow and underflow, \
+ triangular wave valley and peak */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Valid_Period_Count_Define TMR6 Valid Period Function Count Define
+ * @{
+ */
+#define TMR6_VALID_PERIOD_CNT_INVD (0x00UL)
+#define TMR6_VALID_PERIOD_CNT1 (1UL << TMR6_VPERR_PCNTS_POS)
+#define TMR6_VALID_PERIOD_CNT2 (2UL << TMR6_VPERR_PCNTS_POS)
+#define TMR6_VALID_PERIOD_CNT3 (3UL << TMR6_VPERR_PCNTS_POS)
+#define TMR6_VALID_PERIOD_CNT4 (4UL << TMR6_VPERR_PCNTS_POS)
+#define TMR6_VALID_PERIOD_CNT5 (5UL << TMR6_VPERR_PCNTS_POS)
+#define TMR6_VALID_PERIOD_CNT6 (6UL << TMR6_VPERR_PCNTS_POS)
+#define TMR6_VALID_PERIOD_CNT7 (7UL << TMR6_VPERR_PCNTS_POS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_DeadTime_Reg_Define TMR6 Dead Time Register Define
+ * @{
+ */
+#define TMR6_DEADTIME_REG_UP_A (0x00U) /*!< Register DTUAR */
+#define TMR6_DEADTIME_REG_DOWN_A (0x01U) /*!< Register DTDAR */
+#define TMR6_DEADTIME_REG_UP_B (0x02U) /*!< Register DTUBR */
+#define TMR6_DEADTIME_REG_DOWN_B (0x03U) /*!< Register DTDBR */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Pin_Define TMR6 Input And Output Pin Define
+ * @{
+ */
+#define TMR6_IO_PWMA (0x00U) /*!< Pin TIM6__PWMA */
+#define TMR6_IO_PWMB (0x01U) /*!< Pin TIM6__PWMB */
+#define TMR6_INPUT_TRIGA (0x02U) /*!< Input pin TIM6_TRIGA */
+#define TMR6_INPUT_TRIGB (0x03U) /*!< Input pin TIM6_TRIGB */
+#define TMR6_INPUT_TRIGC (0x04U) /*!< Input pin TIM6_TRIGC */
+#define TMR6_INPUT_TRIGD (0x05U) /*!< Input pin TIM6_TRIGD */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Input_Filter_Clock TMR6 Input Pin Filter Clock Divider Define
+ * @{
+ */
+#define TMR6_FILTER_CLK_DIV1 (0x00U)
+#define TMR6_FILTER_CLK_DIV4 (0x01U)
+#define TMR6_FILTER_CLK_DIV16 (0x02U)
+#define TMR6_FILTER_CLK_DIV64 (0x03U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Pin_Mode_Define TMR6 Pin Function Mode Selection
+ * @{
+ */
+#define TMR6_PIN_CMP_OUTPUT (0x00UL)
+#define TMR6_PIN_CAPT_INPUT (TMR6_PCNAR_CAPMDA)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Count_State_Define TMR6 Count State
+ * @{
+ */
+#define TMR6_STAT_START (0U) /*!< Count start */
+#define TMR6_STAT_STOP (1U) /*!< Count stop */
+#define TMR6_STAT_OVF (2U) /*!< Count overflow */
+#define TMR6_STAT_UDF (3U) /*!< Count underflow */
+#define TMR6_STAT_UP_CNT_MATCH_A (4U) /*!< Count up match compare register A */
+#define TMR6_STAT_DOWN_CNT_MATCH_A (5U) /*!< Count down match compare register A */
+#define TMR6_STAT_UP_CNT_MATCH_B (6U) /*!< Count up match compare register B */
+#define TMR6_STAT_DOWN_CNT_MATCH_B (7U) /*!< Count down match compare register B */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Pin_Polarity_Define TMR6 Pin Output Polarity
+ * @{
+ */
+
+#define TMR6_PWM_LOW (0x00U)
+#define TMR6_PWM_HIGH (0x01U)
+#define TMR6_PWM_HOLD (0x02U)
+#define TMR6_PWM_INVT (0x03U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Force_Output_Polarity_Define TMR6 Force Output Polarity Next Period
+ * @{
+ */
+#define TMR6_PWM_FORCE_INVD (0x00U)
+#define TMR6_PWM_FORCE_LOW (0x02U)
+#define TMR6_PWM_FORCE_HIGH (0x03U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Emb_Ch_Define TMR6 EMB Event Channel
+ * @{
+ */
+#define TMR6_EMB_EVT_CH0 (0x00UL)
+#define TMR6_EMB_EVT_CH1 (0x01UL << TMR6_PCNAR_EMBSA_POS)
+#define TMR6_EMB_EVT_CH2 (0x02UL << TMR6_PCNAR_EMBSA_POS)
+#define TMR6_EMB_EVT_CH3 (0x03UL << TMR6_PCNAR_EMBSA_POS)
+#define TMR6_EMB_EVT_CH4 (0x04UL << TMR6_PCNAR_EMBSA_POS)
+#define TMR6_EMB_EVT_CH5 (0x05UL << TMR6_PCNAR_EMBSA_POS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Emb_Release_Mode_Define TMR6 EMB Function Release Mode When EMB Event Invalid
+ * @{
+ */
+#define TMR6_EMB_RELEASE_IMMED (0x00UL)
+#define TMR6_EMB_RELEASE_OVF (TMR6_PCNAR_EMBRA_0)
+#define TMR6_EMB_RELEASE_UDF (TMR6_PCNAR_EMBRA_1)
+#define TMR6_EMB_RELEASE_OVF_UDF (TMR6_PCNAR_EMBRA)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Emb_Pin_Status_Define TMR6 Pin Output Status When EMB Event Valid
+ * @{
+ */
+#define TMR6_EMB_PIN_NORMAL (0x00UL)
+#define TMR6_EMB_PIN_HIZ (TMR6_PCNAR_EMBCA_0)
+#define TMR6_EMB_PIN_LOW (TMR6_PCNAR_EMBCA_1)
+#define TMR6_EMB_PIN_HIGH (TMR6_PCNAR_EMBCA)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Deadtime_CountUp_Buf_Func_Define TMR6 Dead Time Buffer Function For Count Up Stage
+ * @{
+ */
+#define TMR6_DEADTIME_CNT_UP_BUF_OFF (0x00UL)
+#define TMR6_DEADTIME_CNT_UP_BUF_ON (TMR6_DCONR_DTBENU)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Deadtime_CountDown_Buf_Func_Define TMR6 Dead Time Buffer Function For Count Down Stage
+ * @{
+ */
+#define TMR6_DEADTIME_CNT_DOWN_BUF_OFF (0x00UL)
+#define TMR6_DEADTIME_CNT_DOWN_BUF_ON (TMR6_DCONR_DTBEND)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Deadtime_Buf_Trans_Cond_Define TMR6 Dead Time Buffer Transfer Condition Define For Triangular Count Mode
+ * @{
+ */
+#define TMR6_DEADTIME_BUF_COND_INVD (0x00U)
+#define TMR6_DEADTIME_BUF_COND_OVF (TMR6_DCONR_DTBTRU)
+#define TMR6_DEADTIME_BUF_COND_UDF (TMR6_DCONR_DTBTRD)
+#define TMR6_DEADTIME_BUF_COND_OVF_UDF (TMR6_DCONR_DTBTRU | TMR6_DCONR_DTBTRD)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Deadtime_Reg_Equal_Func_Define TMR6 Dead Time Function DTDAR Equal DTUAR
+ * @{
+ */
+#define TMR6_DEADTIME_EQUAL_OFF (0x00UL)
+#define TMR6_DEADTIME_EQUAL_ON (TMR6_DCONR_SEPA)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_SW_Sync_Unit_define TMR6 Software Synchronization Start/Stop/Clear/Update Unit Number Define
+ * @{
+ */
+#define TMR6_SW_SYNC_U1 (TMR6_COMMON_SSTAR_SSTA1)
+#define TMR6_SW_SYNC_U2 (TMR6_COMMON_SSTAR_SSTA2)
+#define TMR6_SW_SYNC_U3 (TMR6_COMMON_SSTAR_SSTA3)
+#define TMR6_SW_SYNC_U4 (TMR6_COMMON_SSTAR_SSTA4)
+#define TMR6_SW_SYNC_U5 (TMR6_COMMON_SSTAR_SSTA5)
+#define TMR6_SW_SYNC_U6 (TMR6_COMMON_SSTAR_SSTA6)
+#define TMR6_SW_SYNC_U7 (TMR6_COMMON_SSTAR_SSTA7)
+#define TMR6_SW_SYNC_U8 (TMR6_COMMON_SSTAR_SSTA8)
+#define TMR6_SW_SYNC_U9 (TMR6_COMMON_SSTAR_SSTA9)
+#define TMR6_SW_SYNC_U10 (TMR6_COMMON_SSTAR_SSTA10)
+#define TMR6_SW_SYNC_ALL (0x3FFUL)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_hardware_start_condition_Define TMR6 Hardware Start Condition Define
+ * @{
+ */
+#define TMR6_START_COND_PWMA_RISING (TMR6_HSTAR_HSTA0)
+#define TMR6_START_COND_PWMA_FALLING (TMR6_HSTAR_HSTA1)
+#define TMR6_START_COND_PWMB_RISING (TMR6_HSTAR_HSTA2)
+#define TMR6_START_COND_PWMB_FALLING (TMR6_HSTAR_HSTA3)
+#define TMR6_START_COND_EVT0 (TMR6_HSTAR_HSTA8)
+#define TMR6_START_COND_EVT1 (TMR6_HSTAR_HSTA9)
+#define TMR6_START_COND_EVT2 (TMR6_HSTAR_HSTA10)
+#define TMR6_START_COND_EVT3 (TMR6_HSTAR_HSTA11)
+#define TMR6_START_COND_TRIGA_RISING (TMR6_HSTAR_HSTA16)
+#define TMR6_START_COND_TRIGA_FALLING (TMR6_HSTAR_HSTA17)
+#define TMR6_START_COND_TRIGB_RISING (TMR6_HSTAR_HSTA18)
+#define TMR6_START_COND_TRIGB_FALLING (TMR6_HSTAR_HSTA19)
+#define TMR6_START_COND_TRIGC_RISING (TMR6_HSTAR_HSTA20)
+#define TMR6_START_COND_TRIGC_FALLING (TMR6_HSTAR_HSTA21)
+#define TMR6_START_COND_TRIGD_RISING (TMR6_HSTAR_HSTA22)
+#define TMR6_START_COND_TRIGD_FALLING (TMR6_HSTAR_HSTA23)
+#define TMR6_START_COND_ALL (0x00FF0F0FUL)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_hardware_stop_condition_Define TMR6 Hardware Stop Condition Define
+ * @{
+ */
+#define TMR6_STOP_COND_PWMA_RISING (TMR6_HSTPR_HSTP0)
+#define TMR6_STOP_COND_PWMA_FALLING (TMR6_HSTPR_HSTP1)
+#define TMR6_STOP_COND_PWMB_RISING (TMR6_HSTPR_HSTP2)
+#define TMR6_STOP_COND_PWMB_FALLING (TMR6_HSTPR_HSTP3)
+#define TMR6_STOP_COND_EVT0 (TMR6_HSTPR_HSTP8)
+#define TMR6_STOP_COND_EVT1 (TMR6_HSTPR_HSTP9)
+#define TMR6_STOP_COND_EVT2 (TMR6_HSTPR_HSTP10)
+#define TMR6_STOP_COND_EVT3 (TMR6_HSTPR_HSTP11)
+#define TMR6_STOP_COND_TRIGA_RISING (TMR6_HSTPR_HSTP16)
+#define TMR6_STOP_COND_TRIGA_FALLING (TMR6_HSTPR_HSTP17)
+#define TMR6_STOP_COND_TRIGB_RISING (TMR6_HSTPR_HSTP18)
+#define TMR6_STOP_COND_TRIGB_FALLING (TMR6_HSTPR_HSTP19)
+#define TMR6_STOP_COND_TRIGC_RISING (TMR6_HSTPR_HSTP20)
+#define TMR6_STOP_COND_TRIGC_FALLING (TMR6_HSTPR_HSTP21)
+#define TMR6_STOP_COND_TRIGD_RISING (TMR6_HSTPR_HSTP22)
+#define TMR6_STOP_COND_TRIGD_FALLING (TMR6_HSTPR_HSTP23)
+#define TMR6_STOP_COND_ALL (0x00FF0F0FUL)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_hardware_clear_condition_Define TMR6 Hardware Clear Condition Define
+ * @{
+ */
+#define TMR6_CLR_COND_PWMA_RISING (TMR6_HCLRR_HCLE0)
+#define TMR6_CLR_COND_PWMA_FALLING (TMR6_HCLRR_HCLE1)
+#define TMR6_CLR_COND_PWMB_RISING (TMR6_HCLRR_HCLE2)
+#define TMR6_CLR_COND_PWMB_FALLING (TMR6_HCLRR_HCLE3)
+#define TMR6_CLR_COND_EVT0 (TMR6_HCLRR_HCLE8)
+#define TMR6_CLR_COND_EVT1 (TMR6_HCLRR_HCLE9)
+#define TMR6_CLR_COND_EVT2 (TMR6_HCLRR_HCLE10)
+#define TMR6_CLR_COND_EVT3 (TMR6_HCLRR_HCLE11)
+#define TMR6_CLR_COND_TRIGA_RISING (TMR6_HCLRR_HCLE16)
+#define TMR6_CLR_COND_TRIGA_FALLING (TMR6_HCLRR_HCLE17)
+#define TMR6_CLR_COND_TRIGB_RISING (TMR6_HCLRR_HCLE18)
+#define TMR6_CLR_COND_TRIGB_FALLING (TMR6_HCLRR_HCLE19)
+#define TMR6_CLR_COND_TRIGC_RISING (TMR6_HCLRR_HCLE20)
+#define TMR6_CLR_COND_TRIGC_FALLING (TMR6_HCLRR_HCLE21)
+#define TMR6_CLR_COND_TRIGD_RISING (TMR6_HCLRR_HCLE22)
+#define TMR6_CLR_COND_TRIGD_FALLING (TMR6_HCLRR_HCLE23)
+#define TMR6_CLR_COND_ALL (0x00FF0F0FUL)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_hardware_update_condition_Define TMR6 Hardware Update Condition Define
+ * @{
+ */
+#define TMR6_UPD_COND_PWMA_RISING (TMR6_HUPDR_HUPD0)
+#define TMR6_UPD_COND_PWMA_FALLING (TMR6_HUPDR_HUPD1)
+#define TMR6_UPD_COND_PWMB_RISING (TMR6_HUPDR_HUPD2)
+#define TMR6_UPD_COND_PWMB_FALLING (TMR6_HUPDR_HUPD3)
+#define TMR6_UPD_COND_EVT0 (TMR6_HUPDR_HUPD8)
+#define TMR6_UPD_COND_EVT1 (TMR6_HUPDR_HUPD9)
+#define TMR6_UPD_COND_EVT2 (TMR6_HUPDR_HUPD10)
+#define TMR6_UPD_COND_EVT3 (TMR6_HUPDR_HUPD11)
+#define TMR6_UPD_COND_TRIGA_RISING (TMR6_HUPDR_HUPD16)
+#define TMR6_UPD_COND_TRIGA_FALLING (TMR6_HUPDR_HUPD17)
+#define TMR6_UPD_COND_TRIGB_RISING (TMR6_HUPDR_HUPD18)
+#define TMR6_UPD_COND_TRIGB_FALLING (TMR6_HUPDR_HUPD19)
+#define TMR6_UPD_COND_TRIGC_RISING (TMR6_HUPDR_HUPD20)
+#define TMR6_UPD_COND_TRIGC_FALLING (TMR6_HUPDR_HUPD21)
+#define TMR6_UPD_COND_TRIGD_RISING (TMR6_HUPDR_HUPD22)
+#define TMR6_UPD_COND_TRIGD_FALLING (TMR6_HUPDR_HUPD23)
+#define TMR6_UPD_COND_ALL (0x00FF0F0FUL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_hardware_capture_condition_Define TMR6 Hardware Capture Condition Define
+ * @{
+ */
+#define TMR6_CAPT_COND_PWMA_RISING (TMR6_HCPAR_HCPA0)
+#define TMR6_CAPT_COND_PWMA_FALLING (TMR6_HCPAR_HCPA1)
+#define TMR6_CAPT_COND_PWMB_RISING (TMR6_HCPAR_HCPA2)
+#define TMR6_CAPT_COND_PWMB_FALLING (TMR6_HCPAR_HCPA3)
+#define TMR6_CAPT_COND_EVT0 (TMR6_HCPAR_HCPA8)
+#define TMR6_CAPT_COND_EVT1 (TMR6_HCPAR_HCPA9)
+#define TMR6_CAPT_COND_EVT2 (TMR6_HCPAR_HCPA10)
+#define TMR6_CAPT_COND_EVT3 (TMR6_HCPAR_HCPA11)
+#define TMR6_CAPT_COND_TRIGA_RISING (TMR6_HCPAR_HCPA16)
+#define TMR6_CAPT_COND_TRIGA_FALLING (TMR6_HCPAR_HCPA17)
+#define TMR6_CAPT_COND_TRIGB_RISING (TMR6_HCPAR_HCPA18)
+#define TMR6_CAPT_COND_TRIGB_FALLING (TMR6_HCPAR_HCPA19)
+#define TMR6_CAPT_COND_TRIGC_RISING (TMR6_HCPAR_HCPA20)
+#define TMR6_CAPT_COND_TRIGC_FALLING (TMR6_HCPAR_HCPA21)
+#define TMR6_CAPT_COND_TRIGD_RISING (TMR6_HCPAR_HCPA22)
+#define TMR6_CAPT_COND_TRIGD_FALLING (TMR6_HCPAR_HCPA23)
+#define TMR6_CAPT_COND_ALL (0x00FF0F0FUL)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_HW_Count_Up_Cond_Define TMR6 Hardware Count Up Condition Define
+ * @{
+ */
+#define TMR6_CNT_UP_COND_INVD (0U)
+#define TMR6_CNT_UP_COND_PWMA_LOW_PWMB_RISING (TMR6_HCUPR_HCUP0)
+#define TMR6_CNT_UP_COND_PWMA_LOW_PWMB_FALLING (TMR6_HCUPR_HCUP1)
+#define TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING (TMR6_HCUPR_HCUP2)
+#define TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_FALLING (TMR6_HCUPR_HCUP3)
+#define TMR6_CNT_UP_COND_PWMB_LOW_PWMA_RISING (TMR6_HCUPR_HCUP4)
+#define TMR6_CNT_UP_COND_PWMB_LOW_PWMA_FALLING (TMR6_HCUPR_HCUP5)
+#define TMR6_CNT_UP_COND_PWMB_HIGH_PWMA_RISING (TMR6_HCUPR_HCUP6)
+#define TMR6_CNT_UP_COND_PWMB_HIGH_PWMA_FALLING (TMR6_HCUPR_HCUP7)
+#define TMR6_CNT_UP_COND_EVT0 (TMR6_HCUPR_HCUP8)
+#define TMR6_CNT_UP_COND_EVT1 (TMR6_HCUPR_HCUP9)
+#define TMR6_CNT_UP_COND_EVT2 (TMR6_HCUPR_HCUP10)
+#define TMR6_CNT_UP_COND_EVT3 (TMR6_HCUPR_HCUP11)
+#define TMR6_CNT_UP_COND_TRIGA_RISING (TMR6_HCUPR_HCUP16)
+#define TMR6_CNT_UP_COND_TRIGA_FALLING (TMR6_HCUPR_HCUP17)
+#define TMR6_CNT_UP_COND_TRIGB_RISING (TMR6_HCUPR_HCUP18)
+#define TMR6_CNT_UP_COND_TRIGB_FALLING (TMR6_HCUPR_HCUP19)
+#define TMR6_CNT_UP_COND_TRIGC_RISING (TMR6_HCUPR_HCUP20)
+#define TMR6_CNT_UP_COND_TRIGC_FALLING (TMR6_HCUPR_HCUP21)
+#define TMR6_CNT_UP_COND_TRIGD_RISING (TMR6_HCUPR_HCUP22)
+#define TMR6_CNT_UP_COND_TRIGD_FALLING (TMR6_HCUPR_HCUP23)
+#define TMR6_CNT_UP_COND_ALL (0x00FF0FFFUL)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_HW_Count_Down_Cond_Define TMR6 Hardware Count Down Condition Define
+ * @{
+ */
+#define TMR6_CNT_DOWN_COND_INVD (0U)
+#define TMR6_CNT_DOWN_COND_PWMA_LOW_PWMB_RISING (TMR6_HCDOR_HCDO0)
+#define TMR6_CNT_DOWN_COND_PWMA_LOW_PWMB_FALLING (TMR6_HCDOR_HCDO1)
+#define TMR6_CNT_DOWN_COND_PWMA_HIGH_PWMB_RISING (TMR6_HCDOR_HCDO2)
+#define TMR6_CNT_DOWN_COND_PWMA_HIGH_PWMB_FALLING (TMR6_HCDOR_HCDO3)
+#define TMR6_CNT_DOWN_COND_PWMB_LOW_PWMA_RISING (TMR6_HCDOR_HCDO4)
+#define TMR6_CNT_DOWN_COND_PWMB_LOW_PWMA_FALLING (TMR6_HCDOR_HCDO5)
+#define TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING (TMR6_HCDOR_HCDO6)
+#define TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_FALLING (TMR6_HCDOR_HCDO7)
+#define TMR6_CNT_DOWN_COND_EVT0 (TMR6_HCDOR_HCDO8)
+#define TMR6_CNT_DOWN_COND_EVT1 (TMR6_HCDOR_HCDO9)
+#define TMR6_CNT_DOWN_COND_EVT2 (TMR6_HCDOR_HCDO10)
+#define TMR6_CNT_DOWN_COND_EVT3 (TMR6_HCDOR_HCDO11)
+#define TMR6_CNT_DOWN_COND_TRIGA_RISING (TMR6_HCDOR_HCDO16)
+#define TMR6_CNT_DOWN_COND_TRIGA_FALLING (TMR6_HCDOR_HCDO17)
+#define TMR6_CNT_DOWN_COND_TRIGB_RISING (TMR6_HCDOR_HCDO18)
+#define TMR6_CNT_DOWN_COND_TRIGB_FALLING (TMR6_HCDOR_HCDO19)
+#define TMR6_CNT_DOWN_COND_TRIGC_RISING (TMR6_HCDOR_HCDO20)
+#define TMR6_CNT_DOWN_COND_TRIGC_FALLING (TMR6_HCDOR_HCDO21)
+#define TMR6_CNT_DOWN_COND_TRIGD_RISING (TMR6_HCDOR_HCDO22)
+#define TMR6_CNT_DOWN_COND_TRIGD_FALLING (TMR6_HCDOR_HCDO23)
+#define TMR6_CNT_DOWN_COND_ALL (0x00FF0FFFUL)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Count_Dir_Define TMR6 Base Counter Function Direction Define
+ * @{
+ */
+#define TMR6_CNT_UP (TMR6_GCONR_DIR)
+#define TMR6_CNT_DOWN (0x00UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Count_Dir_Status_Define TMR6 Count Direction Status Define
+ * @{
+ */
+#define TMR6_STAT_CNT_UP (TMR6_STFLR_DIRF)
+#define TMR6_STAT_CNT_DOWN (0x00UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Count_Mode_Define TMR6 Base Counter Function Mode Define
+ * @{
+ */
+#define TMR6_MD_SAWTOOTH (0x00UL)
+#define TMR6_MD_TRIANGLE (TMR6_GCONR_MODE)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Count_Clock_Define TMR6 Base Counter Clock Source Define
+ * @{
+ */
+#define TMR6_CLK_DIV1 (0x00UL)
+#define TMR6_CLK_DIV2 (0x01UL << TMR6_GCONR_CKDIV_POS)
+#define TMR6_CLK_DIV4 (0x02UL << TMR6_GCONR_CKDIV_POS)
+#define TMR6_CLK_DIV8 (0x03UL << TMR6_GCONR_CKDIV_POS)
+#define TMR6_CLK_DIV16 (0x04UL << TMR6_GCONR_CKDIV_POS)
+#define TMR6_CLK_DIV32 (0x05UL << TMR6_GCONR_CKDIV_POS)
+#define TMR6_CLK_DIV64 (0x06UL << TMR6_GCONR_CKDIV_POS)
+#define TMR6_CLK_DIV128 (0x07UL << TMR6_GCONR_CKDIV_POS)
+#define TMR6_CLK_DIV256 (0x08UL << TMR6_GCONR_CKDIV_POS)
+#define TMR6_CLK_DIV512 (0x09UL << TMR6_GCONR_CKDIV_POS)
+#define TMR6_CLK_DIV1024 (0x0AUL << TMR6_GCONR_CKDIV_POS)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Count_Reload_Define TMR6 Count Stop After Overflow Function Define
+ * @{
+ */
+#define TMR6_CNT_RELOAD_ON (0x00UL)
+#define TMR6_CNT_RELOAD_OFF (TMR6_GCONR_OVSTP)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Zmask_Cycle_Define TMR6 Z Mask Input Function Mask Cycles Number Define
+ * @{
+ */
+#define TMR6_ZMASK_FUNC_INVD (0x00UL)
+#define TMR6_ZMASK_CYCLE_4 (TMR6_GCONR_ZMSKVAL_0)
+#define TMR6_ZMASK_CYCLE_8 (TMR6_GCONR_ZMSKVAL_1)
+#define TMR6_ZMASK_CYCLE_16 (TMR6_GCONR_ZMSKVAL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Zmask_Pos_Unit_Clear_Func_Define TMR6 Unit As Position Timer, Z Phase Input Mask Function Define For Clear Action
+ * @{
+ */
+#define TMR6_POS_CLR_ZMASK_FUNC_OFF (0x00UL)
+#define TMR6_POS_CLR_ZMASK_FUNC_ON (TMR6_GCONR_ZMSKPOS)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR6_Zmask_Revo_Unit_Count_Func_Define TMR6 Unit As Revolution Timer, Z Phase Input Mask Function Define For Count Action
+ * @{
+ */
+#define TMR6_REVO_CNT_ZMASK_FUNC_OFF (0x00UL)
+#define TMR6_REVO_CNT_ZMASK_FUNC_ON (TMR6_GCONR_ZMSKREV)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup TMR6_Global_Functions
+ * @{
+ */
+/**
+ * @brief Get Software Sync start status
+ * @param None
+ * @retval uint32_t Data indicate the read status.
+ */
+__STATIC_INLINE uint32_t TMR6_GetSWSyncStartStatus(void)
+{
+ return READ_REG32(CM_TMR6_COMMON->SSTAR);
+}
+
+/* Base count */
+int32_t TMR6_StructInit(stc_tmr6_init_t *pstcTmr6Init);
+int32_t TMR6_Init(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_init_t *pstcTmr6Init);
+
+void TMR6_SetCountMode(CM_TMR6_TypeDef *TMR6x, uint32_t u32Mode);
+void TMR6_SetCountDir(CM_TMR6_TypeDef *TMR6x, uint32_t u32Dir);
+uint32_t TMR6_GetCountDir(CM_TMR6_TypeDef *TMR6x);
+void TMR6_SetClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Div);
+void TMR6_CountReloadCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
+
+/* Hardware count */
+void TMR6_HWCountUpCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState);
+void TMR6_HWCountDownCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState);
+
+/* PWM output */
+int32_t TMR6_PWM_StructInit(stc_tmr6_pwm_init_t *pstcPwmInit);
+int32_t TMR6_PWM_Init(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_pwm_init_t *pstcPwmInit);
+void TMR6_PWM_OutputCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState);
+void TMR6_PWM_SetPolarity(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32CountState, uint32_t u32Polarity);
+void TMR6_PWM_SetForcePolarity(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Polarity);
+
+/* Input capture */
+void TMR6_HWCaptureCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState);
+
+/* Pin config */
+void TMR6_SetFilterClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, uint32_t u32Div);
+void TMR6_FilterCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, en_functional_state_t enNewState);
+void TMR6_SetFunc(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Func);
+
+/* Universal */
+void TMR6_IntCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32IntType, en_functional_state_t enNewState);
+en_flag_status_t TMR6_GetStatus(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag);
+void TMR6_ClearStatus(CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag);
+uint32_t TMR6_GetPeriodNum(const CM_TMR6_TypeDef *TMR6x);
+void TMR6_DeInit(CM_TMR6_TypeDef *TMR6x);
+void TMR6_Start(CM_TMR6_TypeDef *TMR6x);
+void TMR6_Stop(CM_TMR6_TypeDef *TMR6x);
+
+/* Register write */
+void TMR6_SetCountValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Value);
+void TMR6_SetUpdateValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Value);
+void TMR6_SetPeriodValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value);
+void TMR6_SetCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value);
+void TMR6_SetSpecialCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value);
+void TMR6_SetDeadTimeValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value);
+
+/* Register read */
+uint32_t TMR6_GetCountValue(const CM_TMR6_TypeDef *TMR6x);
+uint32_t TMR6_GetUpdateValue(const CM_TMR6_TypeDef *TMR6x);
+uint32_t TMR6_GetPeriodValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index);
+uint32_t TMR6_GetCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index);
+uint32_t TMR6_GetSpecialCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index);
+uint32_t TMR6_GetDeadTimeValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index);
+
+/* Buffer function */
+int32_t TMR6_GeneralBufConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_buf_config_t *pstcBufConfig);
+int32_t TMR6_PeriodBufConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_buf_config_t *pstcBufConfig);
+
+int32_t TMR6_SpecialBufConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_buf_config_t *pstcBufConfig);
+void TMR6_GeneralBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState);
+void TMR6_SpecialBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState);
+void TMR6_PeriodBufCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
+
+/* Extend function */
+int32_t TMR6_ValidPeriodConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_valid_period_config_t *pstcValidperiodConfig);
+void TMR6_ValidPeriodCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState);
+void TMR6_DeadTimeFuncCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
+int32_t TMR6_DeadTimeConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_deadtime_config_t *pstcDeadTimeConfig);
+int32_t TMR6_ZMaskConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_zmask_config_t *pstcZMaskConfig);
+int32_t TMR6_EMBConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_emb_config_t *pstcEmbConfig);
+int32_t TMR6_BufFuncStructInit(stc_tmr6_buf_config_t *pstcBufConfig);
+int32_t TMR6_ValidPeriodStructInit(stc_tmr6_valid_period_config_t *pstcValidperiodConfig);
+int32_t TMR6_EMBConfigStructInit(stc_tmr6_emb_config_t *pstcEmbConfig);
+int32_t TMR6_DeadTimeStructInit(stc_tmr6_deadtime_config_t *pstcDeadTimeConfig);
+int32_t TMR6_ZMaskConfigStructInit(stc_tmr6_zmask_config_t *pstcZMaskConfig);
+
+/* Software synchronous control */
+void TMR6_SWSyncStart(uint32_t u32Unit);
+void TMR6_SWSyncStop(uint32_t u32Unit);
+void TMR6_SWSyncClear(uint32_t u32Unit);
+void TMR6_SWSyncUpdate(uint32_t u32Unit);
+
+/* Hardware control */
+void TMR6_HWStartCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState);
+void TMR6_HWStartCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
+void TMR6_HWStopCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState);
+void TMR6_HWStopCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
+void TMR6_HWClearCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState);
+void TMR6_HWClearCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
+void TMR6_HWUpdateCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState);
+void TMR6_HWUpdateCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState);
+/**
+ * @}
+ */
+
+#endif /* LL_TMR6_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_TMR6_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_tmra.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_tmra.h
new file mode 100644
index 0000000000..9a35ca256f
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_tmra.h
@@ -0,0 +1,545 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_tmra.h
+ * @brief This file contains all the functions prototypes of the TMRA(TimerA)
+ * driver library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Modify typo
+ Delete union in stc_tmra_init_t structure
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_TMRA_H__
+#define __HC32_LL_TMRA_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_TMRA
+ * @{
+ */
+
+#if (LL_TMRA_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup TMRA_Global_Types TMRA Global Types
+ * @{
+ */
+/**
+ * @brief TMRA initialization structure.
+ */
+typedef struct {
+ uint8_t u8CountSrc; /*!< Specifies the count source of TMRA.
+ This parameter can be a value of @ref TMRA_Count_Src */
+ struct {
+ uint8_t u8ClockDiv; /*!< Specifies the divider of software clock source.
+ This parameter can be a value of @ref TMRA_Clock_Divider */
+ uint8_t u8CountMode; /*!< Specifies count mode.
+ This parameter can be a value of @ref TMRA_Count_Mode */
+ uint8_t u8CountDir; /*!< Specifies count direction.
+ This parameter can be a value of @ref TMRA_Count_Dir */
+ } sw_count;
+ struct {
+ uint16_t u16CountUpCond; /*!< Hardware count up condition.
+ This parameter can be a value of @ref TMRA_Hard_Count_Up_Condition */
+ uint16_t u16CountDownCond; /*!< Hardware count down condition.
+ This parameter can be a value of @ref TMRA_Hard_Count_Down_Condition */
+ } hw_count;
+ uint32_t u32PeriodValue; /*!< Specifies the period reference value.
+ This parameter can be a number between 0U and 0xFFFFU, inclusive. */
+ uint8_t u8CountReload; /*!< Continue counting or stop when counter overflow/underflow.
+ This parameter can be a value of @ref TMRA_Count_Reload_En */
+} stc_tmra_init_t;
+
+/**
+ * @brief TMRA PWM configuration structure.
+ */
+typedef struct {
+ uint32_t u32CompareValue; /*!< Specifies compare value of the TMRA channel.
+ This parameter can be a number between:
+ 0UL and 0xFFFFFFFFUL for 32-bit TimerA units.
+ 0UL and 0xFFFFUL for 16-bit TimerA units. */
+ uint16_t u16StartPolarity; /*!< Specifies the polarity when the counter start counting.
+ This parameter can be a value of @ref TMRA_PWM_Polarity
+ NOTE: CAN NOT be specified as TMRA_PWM_LOW or TMRA_PWM_HIGH when
+ sw_count.u16ClockDiv of @ref stc_tmra_init_t is NOT specified
+ as @ref TMRA_CLK_DIV1 */
+ uint16_t u16StopPolarity; /*!< Specifies the polarity when the counter stop counting.
+ This parameter can be a value of @ref TMRA_PWM_Polarity */
+ uint16_t u16CompareMatchPolarity; /*!< Specifies the polarity when the counter matches the compare register.
+ This parameter can be a value of @ref TMRA_PWM_Polarity */
+ uint16_t u16PeriodMatchPolarity; /*!< Specifies the polarity when the counter matches the period register.
+ This parameter can be a value of @ref TMRA_PWM_Polarity */
+} stc_tmra_pwm_init_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup TMRA_Global_Macros TMRA Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup TMRA_Count_Src TMRA Count Source
+ * @{
+ */
+#define TMRA_CNT_SRC_SW (0U) /*!< Clock source is PCLK. */
+#define TMRA_CNT_SRC_HW (1U) /*!< Clock source is from external pin or peripheral event. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_Channel TMRA Channel
+ * @{
+ */
+#define TMRA_CH1 (0U) /*!< Channel 1 of TMRA. */
+#define TMRA_CH2 (1U) /*!< Channel 2 of TMRA. */
+#define TMRA_CH3 (2U) /*!< Channel 3 of TMRA. */
+#define TMRA_CH4 (3U) /*!< Channel 4 of TMRA. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_Count_Dir TMRA Count Direction
+ * @{
+ */
+#define TMRA_DIR_DOWN (0x0U) /*!< TMRA count down. */
+#define TMRA_DIR_UP (TMRA_BCSTRL_DIR) /*!< TMRA count up. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_Count_Mode TMRA Count Mode
+ * @{
+ */
+#define TMRA_MD_SAWTOOTH (0x0U) /*!< Count mode is sawtooth wave. */
+#define TMRA_MD_TRIANGLE (TMRA_BCSTRL_MODE) /*!< Count mode is triangle wave. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_Function_Mode TMRA TMRA Function Mode
+ * @{
+ */
+#define TMRA_FUNC_CMP (0x0U) /*!< Function mode of TMRA channel is ouput compare. */
+#define TMRA_FUNC_CAPT (TMRA_CCONR_CAPMD) /*!< Function mode of TMRA channel is input capture. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_Count_Reload_En TMRA Count Reload
+ * @{
+ */
+#define TMRA_CNT_RELOAD_DISABLE (TMRA_BCSTRH_OVSTP) /*!< Stop when counter overflow/underflow. */
+#define TMRA_CNT_RELOAD_ENABLE (0U) /*!< When counter overflow/underflow, counter reload to continue counting. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_Clock_Divider TMRA Clock Divider
+ * @{
+ */
+#define TMRA_CLK_DIV1 (0x0U) /*!< The clock source of TMRA is PCLK. */
+#define TMRA_CLK_DIV2 (0x1U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 2. */
+#define TMRA_CLK_DIV4 (0x2U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 4. */
+#define TMRA_CLK_DIV8 (0x3U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 8. */
+#define TMRA_CLK_DIV16 (0x4U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 16. */
+#define TMRA_CLK_DIV32 (0x5U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 32. */
+#define TMRA_CLK_DIV64 (0x6U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 64. */
+#define TMRA_CLK_DIV128 (0x7U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 128. */
+#define TMRA_CLK_DIV256 (0x8U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 256. */
+#define TMRA_CLK_DIV512 (0x9U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 512. */
+#define TMRA_CLK_DIV1024 (0xAU << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 1024. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_Filter_Pin TMRA Pin With Filter
+ * @{
+ */
+#define TMRA_PIN_TRIG (0U) /*!< Pin TIMA__TRIG. */
+#define TMRA_PIN_CLKA (1U) /*!< Pin TIMA__CLKA. */
+#define TMRA_PIN_CLKB (2U) /*!< Pin TIMA__CLKB. */
+#define TMRA_PIN_PWM1 (3U) /*!< Pin TIMA__PWM1. */
+#define TMRA_PIN_PWM2 (4U) /*!< Pin TIMA__PWM2. */
+#define TMRA_PIN_PWM3 (5U) /*!< Pin TIMA__PWM3. */
+#define TMRA_PIN_PWM4 (6U) /*!< Pin TIMA__PWM4. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_Hard_Count_Up_Condition TMRA Hardware Count Up Condition
+ * @note Symmetric units: unit 1 and 2; unit 3 and 4; ...; unit 11 and 12.
+ * @{
+ */
+#define TMRA_CNT_UP_COND_INVD (0U) /*!< TMRA hardware count up condition is INVALID. */
+#define TMRA_CNT_UP_COND_CLKA_LOW_CLKB_RISING (TMRA_HCUPR_HCUP0) /*!< When CLKA is low, a rising edge is sampled on CLKB, the counter register counts up. */
+#define TMRA_CNT_UP_COND_CLKA_LOW_CLKB_FALLING (TMRA_HCUPR_HCUP1) /*!< When CLKA is low, a falling edge is sampled on CLKB, the counter register counts up. */
+#define TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING (TMRA_HCUPR_HCUP2) /*!< When CLKA is high, a rising edge is sampled on CLKB, the counter register counts up. */
+#define TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_FALLING (TMRA_HCUPR_HCUP3) /*!< When CLKA is high, a falling edge is sampled on CLKB, the counter register counts up. */
+#define TMRA_CNT_UP_COND_CLKB_LOW_CLKA_RISING (TMRA_HCUPR_HCUP4) /*!< When CLKB is low, a rising edge is sampled on CLKA, the counter register counts up. */
+#define TMRA_CNT_UP_COND_CLKB_LOW_CLKA_FALLING (TMRA_HCUPR_HCUP5) /*!< When CLKB is low, a falling edge is sampled on CLKA, the counter register counts up. */
+#define TMRA_CNT_UP_COND_CLKB_HIGH_CLKA_RISING (TMRA_HCUPR_HCUP6) /*!< When CLKB is high, a rising edge is sampled on CLKA, the counter register counts up. */
+#define TMRA_CNT_UP_COND_CLKB_HIGH_CLKA_FALLING (TMRA_HCUPR_HCUP7) /*!< When CLKB is high, a falling edge is sampled on CLKA, the counter register counts up. */
+#define TMRA_CNT_UP_COND_TRIG_RISING (TMRA_HCUPR_HCUP8) /*!< When a rising edge occurred on TRIG, the counter register counts up. */
+#define TMRA_CNT_UP_COND_TRIG_FALLING (TMRA_HCUPR_HCUP9) /*!< When a falling edge occurred on TRIG, the counter register counts up. */
+#define TMRA_CNT_UP_COND_EVT (TMRA_HCUPR_HCUP10) /*!< When the TMRA common trigger event occurred, the counter register counts up. */
+#define TMRA_CNT_UP_COND_SYM_OVF (TMRA_HCUPR_HCUP11) /*!< When the symmetric unit overflow, the counter register counts up. */
+#define TMRA_CNT_UP_COND_SYM_UDF (TMRA_HCUPR_HCUP12) /*!< When the symmetric unit underflow, the counter register counts up. */
+#define TMRA_CNT_UP_COND_ALL (0x1FFFU)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_Hard_Count_Down_Condition TMRA Hardware Count Down Condition
+ * @note Symmetric units: unit 1 and 2; unit 3 and 4; ...; unit 11 and 12.
+ * @{
+ */
+#define TMRA_CNT_DOWN_COND_INVD (0U) /*!< TMRA hardware count down condition is INVALID. */
+#define TMRA_CNT_DOWN_COND_CLKA_LOW_CLKB_RISING (TMRA_HCDOR_HCDO0) /*!< When CLKA is low, a rising edge is sampled on CLKB, the counter register counts down. */
+#define TMRA_CNT_DOWN_COND_CLKA_LOW_CLKB_FALLING (TMRA_HCDOR_HCDO1) /*!< When CLKA is low, a falling edge is sampled on CLKB, the counter register counts down. */
+#define TMRA_CNT_DOWN_COND_CLKA_HIGH_CLKB_RISING (TMRA_HCDOR_HCDO2) /*!< When CLKA is high, a rising edge is sampled on CLKB, the counter register counts down. */
+#define TMRA_CNT_DOWN_COND_CLKA_HIGH_CLKB_FALLING (TMRA_HCDOR_HCDO3) /*!< When CLKA is high, a falling edge is sampled on CLKB, the counter register counts down. */
+#define TMRA_CNT_DOWN_COND_CLKB_LOW_CLKA_RISING (TMRA_HCDOR_HCDO4) /*!< When CLKB is low, a rising edge is sampled on CLKA, the counter register counts down. */
+#define TMRA_CNT_DOWN_COND_CLKB_LOW_CLKA_FALLING (TMRA_HCDOR_HCDO5) /*!< When CLKB is low, a falling edge is sampled on CLKA, the counter register counts down. */
+#define TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING (TMRA_HCDOR_HCDO6) /*!< When CLKB is high, a rising edge is sampled on CLKA, the counter register counts down. */
+#define TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_FALLING (TMRA_HCDOR_HCDO7) /*!< When CLKB is high, a falling edge is sampled on CLKA, the counter register counts down. */
+#define TMRA_CNT_DOWN_COND_TRIG_RISING (TMRA_HCDOR_HCDO8) /*!< When a rising edge occurred on TRIG, the counter register counts down. */
+#define TMRA_CNT_DOWN_COND_TRIG_FALLING (TMRA_HCDOR_HCDO9) /*!< When a falling edge occurred on TRIG, the counter register counts down. */
+#define TMRA_CNT_DOWN_COND_EVT (TMRA_HCDOR_HCDO10) /*!< When the TMRA common trigger event occurred, the counter register counts down. */
+#define TMRA_CNT_DOWN_COND_SYM_OVF (TMRA_HCDOR_HCDO11) /*!< When the symmetric unit overflow, the counter register counts down. */
+#define TMRA_CNT_DOWN_COND_SYM_UDF (TMRA_HCDOR_HCDO12) /*!< When the symmetric unit underflow, the counter register counts down. */
+#define TMRA_CNT_DOWN_COND_ALL (0x1FFFU)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_Interrupt_Type TMRA Interrupt Type
+ * @{
+ */
+#define TMRA_INT_OVF (1UL << 4U) /*!< The interrupt of counting overflow. */
+#define TMRA_INT_UDF (1UL << 5U) /*!< The interrupt of counting underflow. */
+#define TMRA_INT_CMP_CH1 (1UL << 16U) /*!< The interrupt of compare-match of channel 1. */
+#define TMRA_INT_CMP_CH2 (1UL << 17U) /*!< The interrupt of compare-match of channel 2. */
+#define TMRA_INT_CMP_CH3 (1UL << 18U) /*!< The interrupt of compare-match of channel 3. */
+#define TMRA_INT_CMP_CH4 (1UL << 19U) /*!< The interrupt of compare-match of channel 4. */
+#define TMRA_INT_ALL (0xF0030UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_Event_Type TMRA Event Type
+ * @{
+ */
+#define TMRA_EVT_CMP_CH1 (TMRA_ECONR_ETEN1) /*!< The event of compare-match of channel 1. */
+#define TMRA_EVT_CMP_CH2 (TMRA_ECONR_ETEN2) /*!< The event of compare-match of channel 2. */
+#define TMRA_EVT_CMP_CH3 (TMRA_ECONR_ETEN3) /*!< The event of compare-match of channel 3. */
+#define TMRA_EVT_CMP_CH4 (TMRA_ECONR_ETEN4) /*!< The event of compare-match of channel 4. */
+#define TMRA_EVT_ALL (TMRA_EVT_CMP_CH1 | TMRA_EVT_CMP_CH2 | \
+ TMRA_EVT_CMP_CH3 | TMRA_EVT_CMP_CH4)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_Status_Flag TMRA Status Flag
+ * @{
+ */
+#define TMRA_FLAG_OVF (1UL << 6U) /*!< The flag of counting overflow. */
+#define TMRA_FLAG_UDF (1UL << 7U) /*!< The flag of counting underflow. */
+#define TMRA_FLAG_CMP_CH1 (1UL << 16U) /*!< The flag of compare-match of channel 1. */
+#define TMRA_FLAG_CMP_CH2 (1UL << 17U) /*!< The flag of compare-match of channel 2. */
+#define TMRA_FLAG_CMP_CH3 (1UL << 18U) /*!< The flag of compare-match of channel 3. */
+#define TMRA_FLAG_CMP_CH4 (1UL << 19U) /*!< The flag of compare-match of channel 4. */
+#define TMRA_FLAG_CAPT_AGAIN_CH1 (1UL << 24U) /*!< The flag of capture occurs again after successful capture of channel 1. */
+#define TMRA_FLAG_CAPT_AGAIN_CH2 (1UL << 25U) /*!< The flag of capture occurs again after successful capture of channel 2. */
+#define TMRA_FLAG_CAPT_AGAIN_CH3 (1UL << 26U) /*!< The flag of capture occurs again after successful capture of channel 3. */
+#define TMRA_FLAG_CAPT_AGAIN_CH4 (1UL << 27U) /*!< The flag of capture occurs again after successful capture of channel 4. */
+#define TMRA_FLAG_ALL (0xF0F00C0UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_Capture_Cond TMRA Capture Condition
+ * @note 'TMRA_CAPT_COND_TRIG_RISING' and 'TMRA_CAPT_COND_TRIG_FALLING' are only valid for channel 4.
+ * @{
+ */
+#define TMRA_CAPT_COND_INVD (0x0U) /*!< The condition of capture is INVALID. */
+#define TMRA_CAPT_COND_PWM_RISING (TMRA_CCONR_HICP0) /*!< The condition of capture is a rising edge is sampled on pin TIMA__PWMn. */
+#define TMRA_CAPT_COND_PWM_FALLING (TMRA_CCONR_HICP1) /*!< The condition of capture is a falling edge is sampled on pin TIMA__PWMn. */
+#define TMRA_CAPT_COND_EVT (TMRA_CCONR_HICP2) /*!< The condition of capture is the specified event occurred. */
+#define TMRA_CAPT_COND_TRIG_RISING (TMRA_CCONR_HICP3) /*!< The condition of capture is a rising edge is sampled on pin TIMA__TRIG.
+ This condition is only valid for channel 4. */
+#define TMRA_CAPT_COND_TRIG_FALLING (TMRA_CCONR_HICP4) /*!< The condition of capture is a falling edge is sampled on pin TIMA__TRIG.
+ This condition is only valid for channel 4. */
+#define TMRA_CAPT_COND_ALL (TMRA_CAPT_COND_PWM_RISING | TMRA_CAPT_COND_PWM_FALLING | \
+ TMRA_CAPT_COND_EVT | TMRA_CAPT_COND_TRIG_RISING | \
+ TMRA_CAPT_COND_TRIG_FALLING)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_Cmp_Value_Buf_Trans_Cond TMRA Compare Value Buffer Transmission Condition
+ * @{
+ */
+#define TMRA_BUF_TRANS_COND_OVF_UDF_CLR (0x0U) /*!< This configuration value applies to non-triangular wave counting mode.
+ When counting overflow or underflow or counting register was cleared,
+ transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). */
+#define TMRA_BUF_TRANS_COND_PEAK (TMRA_BCONR_BSE0) /*!< In triangle wave count mode, when count reached peak,
+ transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). */
+#define TMRA_BUF_TRANS_COND_VALLEY (TMRA_BCONR_BSE1) /*!< In triangle wave count mode, when count reached valley,
+ transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,.... */
+#define TMRA_BUF_TRANS_COND_PEAK_VALLEY (TMRA_BCONR_BSE1 | \
+ TMRA_BCONR_BSE0) /*!< In triangle wave count mode, when count reached peak or valley,
+ transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_Filter_Clock_Divider TMRA Filter Clock Divider
+ * @{
+ */
+#define TMRA_FILTER_CLK_DIV1 (0x0U) /*!< The filter clock is the clock of TimerA / 1 */
+#define TMRA_FILTER_CLK_DIV4 (0x1U) /*!< The filter clock is the clock of TimerA / 4 */
+#define TMRA_FILTER_CLK_DIV16 (0x2U) /*!< The filter clock is the clock of TimerA / 16 */
+#define TMRA_FILTER_CLK_DIV64 (0x3U) /*!< The filter clock is the clock of TimerA / 64 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_Counter_State TMRA Counter State
+ * @{
+ */
+#define TMRA_CNT_STAT_START (0U) /*!< Counter start counting. */
+#define TMRA_CNT_STAT_STOP (1U) /*!< Counter stop counting. */
+#define TMRA_CNT_STAT_MATCH_CMP (2U) /*!< Counter value matches the compare value. */
+#define TMRA_CNT_STAT_MATCH_PERIOD (3U) /*!< Counter value matches the period value. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_PWM_Polarity TMRA PWM Polarity
+ * @{
+ */
+#define TMRA_PWM_LOW (0x0U) /*!< PWM output low. */
+#define TMRA_PWM_HIGH (0x1U) /*!< PWM output high. */
+#define TMRA_PWM_HOLD (0x2U) /*!< PWM output holds the current polarity. */
+#define TMRA_PWM_INVT (0x3U) /*!< PWM output reverses the current polarity. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_PWM_Force_Polarity TMRA PWM Force Polarity
+ * @{
+ */
+#define TMRA_PWM_FORCE_INVD (0x0U) /*!< Force polarity is invalid. */
+#define TMRA_PWM_FORCE_LOW (TMRA_PCONR_FORC_1) /*!< Force the PWM output low at the beginning of the next cycle.
+ The beginning of the next cycle: overflow position or underflow position
+ of sawtooth wave; valley position of triangle wave. */
+#define TMRA_PWM_FORCE_HIGH (TMRA_PCONR_FORC) /*!< Force the PWM output high at the beginning of the next cycle.
+ The beginning of the next cycle: overflow position or underflow position
+ of sawtooth wave; valley position of triangle wave. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_Hardware_Start_Condition TMRA Hardware Start Condition
+ * @{
+ */
+#define TMRA_START_COND_INVD (0x0U) /*!< The condition of start is INVALID. */
+#define TMRA_START_COND_TRIG_RISING (TMRA_HCONR_HSTA0) /*!< 1. Sync start is invalid: The condition is that a rising edge is sampled on TRIG of the current TMRA unit.
+ 2. Sync start is valid: The condition is that a rising edge is sampled on TRIG of the symmetric TMRA unit. */
+#define TMRA_START_COND_TRIG_FALLING (TMRA_HCONR_HSTA1) /*!< 1. Sync start is invalid: The condition is that a falling edge is sampled on TRIG of the current TMRA unit.
+ 2. Sync start is valid: The condition is that a falling edge is sampled on TRIG of the symmetric TMRA unit. */
+#define TMRA_START_COND_EVT (TMRA_HCONR_HSTA2) /*!< The condition is that the TMRA common trigger event has occurred. */
+#define TMRA_START_COND_ALL (TMRA_START_COND_TRIG_RISING | TMRA_START_COND_TRIG_FALLING | \
+ TMRA_START_COND_EVT)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_Hardware_Stop_Condition TMRA Hardware Stop Condition
+ * @{
+ */
+#define TMRA_STOP_COND_INVD (0x0U) /*!< The condition of stop is INVALID. */
+#define TMRA_STOP_COND_TRIG_RISING (TMRA_HCONR_HSTP0) /*!< The condition is that a rising edge is sampled on pin TRIG of the current TMRA unit. */
+#define TMRA_STOP_COND_TRIG_FALLING (TMRA_HCONR_HSTP1) /*!< The condition is that a falling edge is sampled on pin TRIG of the current TMRA unit. */
+#define TMRA_STOP_COND_EVT (TMRA_HCONR_HSTP2) /*!< The condition is that the TMRA common trigger event has occurred. */
+#define TMRA_STOP_COND_ALL (TMRA_STOP_COND_TRIG_RISING | TMRA_STOP_COND_TRIG_FALLING | \
+ TMRA_STOP_COND_EVT)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_Hardware_Clear_Condition TMRA Hardware Clear Condition
+ * @note Symmetric units: unit 1 and 2; unit 3 and 4; ... ; unit 11 and 12.
+ * @{
+ */
+#define TMRA_CLR_COND_INVD (0x0U) /*!< The condition of clear is INVALID. */
+#define TMRA_CLR_COND_TRIG_RISING (TMRA_HCONR_HCLE0) /*!< The condition is that a rising edge is sampled on TRIG of the current TMRA unit. */
+#define TMRA_CLR_COND_TRIG_FALLING (TMRA_HCONR_HCLE1) /*!< The condition is that a falling edge is sampled on TRIG of the current TMRA unit. */
+#define TMRA_CLR_COND_EVT (TMRA_HCONR_HCLE2) /*!< The condition is that the TMRA common trigger event has occurred. */
+#define TMRA_CLR_COND_SYM_TRIG_RISING (TMRA_HCONR_HCLE3) /*!< The condition is that a rising edge is sampled on TRIG of the symmetric unit. */
+#define TMRA_CLR_COND_SYM_TRIG_FALLING (TMRA_HCONR_HCLE4) /*!< The condition is that a falling edge is sampled on TRIG of the symmetric unit. */
+#define TMRA_CLR_COND_PWM3_RISING (TMRA_HCONR_HCLE5) /*!< The condition is that a rising edge is sampled on PWM3 of the current TMRA unit. */
+#define TMRA_CLR_COND_PWM3_FALLING (TMRA_HCONR_HCLE6) /*!< The condition is that a falling edge is sampled on PWM3 of the current TMRA unit. */
+#define TMRA_CLR_COND_ALL (TMRA_CLR_COND_TRIG_RISING | TMRA_CLR_COND_TRIG_FALLING | \
+ TMRA_CLR_COND_EVT| TMRA_CLR_COND_SYM_TRIG_RISING | \
+ TMRA_CLR_COND_SYM_TRIG_FALLING | TMRA_CLR_COND_PWM3_RISING| \
+ TMRA_CLR_COND_PWM3_FALLING)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup TMRA_Global_Functions
+ * @{
+ */
+/* Base count(use software clock PCLK/HCLK) */
+int32_t TMRA_Init(CM_TMRA_TypeDef *TMRAx, const stc_tmra_init_t *pstcTmraInit);
+int32_t TMRA_StructInit(stc_tmra_init_t *pstcTmraInit);
+void TMRA_SetCountMode(CM_TMRA_TypeDef *TMRAx, uint8_t u8Mode);
+void TMRA_SetCountDir(CM_TMRA_TypeDef *TMRAx, uint8_t u8Dir);
+void TMRA_SetClockDiv(CM_TMRA_TypeDef *TMRAx, uint8_t u8Div);
+
+/* Hardware count */
+void TMRA_HWCountUpCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState);
+void TMRA_HWCountDownCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState);
+/* Set function mode */
+void TMRA_SetFunc(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Func);
+
+/* Ouput compare */
+int32_t TMRA_PWM_Init(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, const stc_tmra_pwm_init_t *pstcPwmInit);
+int32_t TMRA_PWM_StructInit(stc_tmra_pwm_init_t *pstcPwmInit);
+void TMRA_PWM_OutputCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState);
+void TMRA_PWM_SetPolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint8_t u8CountState, uint16_t u16Polarity);
+void TMRA_PWM_SetForcePolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Polarity);
+/* Input capture */
+void TMRA_HWCaptureCondCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState);
+
+/* Trigger: hardware trigger to start/stop/clear the counter */
+void TMRA_HWStartCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState);
+void TMRA_HWStopCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState);
+void TMRA_HWClearCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState);
+
+/* Filter */
+void TMRA_SetFilterClockDiv(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, uint16_t u16Div);
+void TMRA_FilterCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, en_functional_state_t enNewState);
+
+/* Global */
+void TMRA_DeInit(CM_TMRA_TypeDef *TMRAx);
+/* Counting direction, period value, counter value, compare value */
+uint8_t TMRA_GetCountDir(const CM_TMRA_TypeDef *TMRAx);
+
+void TMRA_SetPeriodValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value);
+uint32_t TMRA_GetPeriodValue(const CM_TMRA_TypeDef *TMRAx);
+void TMRA_SetCountValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value);
+uint32_t TMRA_GetCountValue(const CM_TMRA_TypeDef *TMRAx);
+void TMRA_SetCompareValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint32_t u32Value);
+uint32_t TMRA_GetCompareValue(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch);
+
+/* Sync start */
+void TMRA_SyncStartCmd(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState);
+/* Reload and continue counting when overflow/underflow */
+void TMRA_CountReloadCmd(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState);
+
+void TMRA_SetCompareBufCond(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond);
+void TMRA_CompareBufCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState);
+
+en_flag_status_t TMRA_GetStatus(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag);
+void TMRA_ClearStatus(CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag);
+void TMRA_IntCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32IntType, en_functional_state_t enNewState);
+void TMRA_EventCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32EventType, en_functional_state_t enNewState);
+void TMRA_Start(CM_TMRA_TypeDef *TMRAx);
+void TMRA_Stop(CM_TMRA_TypeDef *TMRAx);
+
+/**
+ * @}
+ */
+
+#endif /* LL_TMRA_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_TMRA_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_trng.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_trng.h
new file mode 100644
index 0000000000..15360ce4ac
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_trng.h
@@ -0,0 +1,129 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_trng.h
+ * @brief This file contains all the functions prototypes of the TRNG driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Add TRNG_Cmd,TRNG_DeInit functions
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_TRNG_H__
+#define __HC32_LL_TRNG_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_TRNG
+ * @{
+ */
+
+#if (LL_TRNG_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/**
+ * @defgroup TRNG_Global_Macros TRNG Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup TRNG_Reload_Init_Value TRNG Reload Initial Value
+ * @{
+ */
+#define TRNG_RELOAD_INIT_VAL_ENABLE (TRNG_MR_LOAD) /* Enable reload new initial value. */
+#define TRNG_RELOAD_INIT_VAL_DISABLE (0x0U) /* Disable reload new initial value. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TRNG_Shift_Ctrl TRNG Shift Control
+ * @{
+ */
+#define TRNG_SHIFT_CNT32 (0x3UL << TRNG_MR_CNT_POS) /* Shift 32 times when capturing random noise. */
+#define TRNG_SHIFT_CNT64 (0x4UL << TRNG_MR_CNT_POS) /* Shift 64 times when capturing random noise. */
+#define TRNG_SHIFT_CNT128 (0x5UL << TRNG_MR_CNT_POS) /* Shift 128 times when capturing random noise. */
+#define TRNG_SHIFT_CNT256 (0x6UL << TRNG_MR_CNT_POS) /* Shift 256 times when capturing random noise. */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup TRNG_Global_Functions
+ * @{
+ */
+int32_t TRNG_DeInit(void);
+void TRNG_Init(uint32_t u32ShiftCount, uint32_t u32ReloadInitValueEn);
+int32_t TRNG_GenerateRandom(uint32_t *pu32Random, uint32_t u32RandomLen);
+
+void TRNG_Start(void);
+void TRNG_Cmd(en_functional_state_t enNewState);
+int32_t TRNG_GetRandom(uint32_t *pu32Random, uint8_t u8RandomLen);
+/**
+ * @}
+ */
+
+#endif /* LL_TRNG_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_TRNG_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_usart.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_usart.h
new file mode 100644
index 0000000000..a66c4b0f5a
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_usart.h
@@ -0,0 +1,543 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_usart.h
+ * @brief This file contains all the functions prototypes of the USART(Universal
+ * Synchronous/Asynchronous Receiver Transmitter) driver library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Modify typo
+ Change macro-definition: USART_DR_MPID -> USART_TDR_MPID
+ Modify USART_SetTransType parameter: u32Type -> u16Type
+ Modify USART_SC_ETU_CLK128/256 value
+ 2023-09-30 CDT Remove u32StopBit param from stc_usart_smartcard_init_t structure
+ 2023-12-15 CDT Add the declaration of API USART_GetFuncState()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_USART_H__
+#define __HC32_LL_USART_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_USART
+ * @{
+ */
+
+#if (LL_USART_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup USART_Global_Types USART Global Types
+ * @{
+ */
+
+/**
+ * @brief clock synchronization mode initialization structure definition
+ * @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock.
+ */
+typedef struct {
+ uint32_t u32ClockSrc; /*!< Clock Source.
+ This parameter can be a value of @ref USART_Clock_Source */
+ uint32_t u32ClockDiv; /*!< Clock division.
+ This parameter can be a value of @ref USART_Clock_Division. */
+ uint32_t u32Baudrate; /*!< USART baudrate.
+ This parameter is valid when clock source is the internal clock. */
+ uint32_t u32FirstBit; /*!< Significant bit.
+ This parameter can be a value of @ref USART_First_Bit */
+ uint32_t u32HWFlowControl; /*!< Hardware flow control.
+ This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} stc_usart_clocksync_init_t;
+
+/**
+ * @brief UART multiple-processor initialization structure definition
+ * @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock.
+ */
+typedef struct {
+ uint32_t u32ClockSrc; /*!< Clock Source.
+ This parameter can be a value of @ref USART_Clock_Source */
+ uint32_t u32ClockDiv; /*!< Clock division.
+ This parameter can be a value of @ref USART_Clock_Division. */
+ uint32_t u32CKOutput; /*!< USART_CK output selection.
+ This parameter can be a value of @ref USART_CK_Output_Selection. */
+ uint32_t u32Baudrate; /*!< USART baudrate.
+ This parameter is valid when clock source is the internal clock. */
+ uint32_t u32DataWidth; /*!< Data width.
+ This parameter can be a value of @ref USART_Data_Width_Bit */
+ uint32_t u32StopBit; /*!< Stop Bits.
+ This parameter can be a value of @ref USART_Stop_Bit */
+ uint32_t u32OverSampleBit; /*!< Oversampling Bits.
+ This parameter can be a value of @ref USART_Over_Sample_Bit */
+ uint32_t u32FirstBit; /*!< Significant bit.
+ This parameter can be a value of @ref USART_First_Bit */
+ uint32_t u32StartBitPolarity; /*!< Start Bit Detect Polarity.
+ This parameter can be a value of @ref USART_Start_Bit_Polarity */
+ uint32_t u32HWFlowControl; /*!< Hardware flow control.
+ This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} stc_usart_multiprocessor_init_t;
+
+/**
+ * @brief UART mode initialization structure definition
+ * @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock.
+ */
+typedef struct {
+ uint32_t u32ClockSrc; /*!< Clock Source.
+ This parameter can be a value of @ref USART_Clock_Source */
+ uint32_t u32ClockDiv; /*!< Clock division.
+ This parameter can be a value of @ref USART_Clock_Division. */
+ uint32_t u32CKOutput; /*!< USART_CK output selection.
+ This parameter can be a value of @ref USART_CK_Output_Selection. */
+ uint32_t u32Baudrate; /*!< USART baudrate.
+ This parameter is valid when clock source is the internal clock. */
+ uint32_t u32DataWidth; /*!< Data width.
+ This parameter can be a value of @ref USART_Data_Width_Bit */
+ uint32_t u32StopBit; /*!< Stop Bits.
+ This parameter can be a value of @ref USART_Stop_Bit */
+ uint32_t u32Parity; /*!< Parity format.
+ This parameter can be a value of @ref USART_Parity_Control */
+ uint32_t u32OverSampleBit; /*!< Oversampling Bits.
+ This parameter can be a value of @ref USART_Over_Sample_Bit */
+ uint32_t u32FirstBit; /*!< Significant bit.
+ This parameter can be a value of @ref USART_First_Bit */
+ uint32_t u32StartBitPolarity; /*!< Start Bit Detect Polarity.
+ This parameter can be a value of @ref USART_Start_Bit_Polarity */
+ uint32_t u32HWFlowControl; /*!< Hardware flow control.
+ This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} stc_usart_uart_init_t;
+
+/**
+ * @brief LIN mode initialization structure definition
+ * @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock.
+ */
+typedef struct {
+ uint32_t u32ClockSrc; /*!< Clock Source.
+ This parameter can be a value of @ref USART_Clock_Source */
+ uint32_t u32ClockDiv; /*!< Clock division.
+ This parameter can be a value of @ref USART_Clock_Division. */
+ uint32_t u32CKOutput; /*!< USART_CK output selection.
+ This parameter can be a value of @ref USART_CK_Output_Selection. */
+ uint32_t u32Baudrate; /*!< USART baudrate.
+ This parameter is valid when clock source is the internal clock. */
+ uint32_t u32OverSampleBit; /*!< Oversampling Bits.
+ This parameter can be a value of @ref USART_Over_Sample_Bit */
+ uint32_t u32BmcClockDiv; /*!< BMC clock division.
+ This parameter can be a value of @ref USART_LIN_BMC_Clock_Division.
+ @note The clock division is valid when clock source is the internal clock. */
+ uint32_t u32DetectBreakLen; /*!< Detect break length.
+ This parameter can be a value of @ref USART_LIN_Detect_Break_Length */
+ uint32_t u32SendBreakLen; /*!< Send break length.
+ This parameter can be a value of @ref USART_LIN_Send_Break_Length */
+ uint32_t u32SendBreakMode; /*!< Send break mode.
+ This parameter can be a value of @ref USART_LIN_Send_Break_Mode */
+} stc_usart_lin_init_t;
+
+/**
+ * @brief Smartcard mode initialization structure definition
+ */
+typedef struct {
+ uint32_t u32ClockDiv; /*!< Clock division. This parameter can be a value of @ref USART_Clock_Division.
+ @note This parameter is valid when clock source is the internal clock. */
+ uint32_t u32CKOutput; /*!< USART_CK output selection. This parameter can be a value of @ref USART_CK_Output_Selection.
+ @note This parameter is valid when clock source is the internal clock. */
+ uint32_t u32Baudrate; /*!< USART baudrate.
+ This parameter is calculated according with smartcard default ETU and clock. */
+ uint32_t u32FirstBit; /*!< Significant bit.
+ This parameter can be a value of @ref USART_First_Bit */
+} stc_usart_smartcard_init_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup USART_Global_Macros USART Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup USART_Flag USART Flag
+ * @{
+ */
+#define USART_FLAG_RX_FULL (USART_SR_RXNE) /*!< Receive data register not empty flag */
+#define USART_FLAG_OVERRUN (USART_SR_ORE) /*!< Overrun error flag */
+#define USART_FLAG_TX_CPLT (USART_SR_TC) /*!< Transmission complete flag */
+#define USART_FLAG_TX_EMPTY (USART_SR_TXE) /*!< Transmit data register empty flag */
+#define USART_FLAG_FRAME_ERR (USART_SR_FE) /*!< Framing error flag */
+#define USART_FLAG_PARITY_ERR (USART_SR_PE) /*!< Parity error flag */
+#define USART_FLAG_MX_PROCESSOR (USART_SR_MPB) /*!< Receive processor ID flag */
+#define USART_FLAG_RX_TIMEOUT (USART_SR_RTOF) /*!< Receive timeout flag */
+#define USART_FLAG_LIN_ERR (USART_SR_BE) /*!< LIN bus error flag */
+#define USART_FLAG_LIN_WKUP (USART_SR_WKUP) /*!< LIN wakeup signal detection flag */
+#define USART_FLAG_LIN_BREAK (USART_SR_LBD) /*!< LIN break signal detection flag */
+#define USART_FLAG_TX_END (USART_SR_TEND) /*!< Transmission complete flag (can be cleared) */
+
+#define USART_FLAG_ALL (USART_FLAG_RX_FULL | USART_FLAG_FRAME_ERR | USART_FLAG_TX_EMPTY | \
+ USART_FLAG_OVERRUN | USART_FLAG_PARITY_ERR | USART_FLAG_RX_TIMEOUT | \
+ USART_FLAG_TX_CPLT | USART_FLAG_LIN_BREAK | USART_FLAG_LIN_WKUP | \
+ USART_FLAG_LIN_ERR | USART_FLAG_MX_PROCESSOR | USART_FLAG_TX_END)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_Transmission_Type USART Transmission Type
+ * @{
+ */
+#define USART_TRANS_DATA (0UL)
+#define USART_TRANS_ID (USART_TDR_MPID)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_Function USART Function
+ * @{
+ */
+#define USART_TX (USART_CR1_TE) /*!< USART TX function */
+#define USART_RX (USART_CR1_RE) /*!< USART RX function */
+#define USART_INT_RX (USART_CR1_RIE) /*!< USART receive data register not empty && receive error interrupt */
+#define USART_INT_TX_CPLT (USART_CR1_TCIE) /*!< USART transmission complete interrupt */
+#define USART_INT_TX_EMPTY (USART_CR1_TXEIE) /*!< USART transmit data register empty interrupt */
+#define USART_RX_TIMEOUT (USART_CR1_RTOE) /*!< USART RX timeout function */
+#define USART_INT_RX_TIMEOUT (USART_CR1_RTOIE) /*!< USART RX timeout interrupt */
+#define USART_INT_TX_END (USART_CR1_TENDIE) /*!< USART transmission complete interrupt */
+#define USART_LIN (USART_CR2_LINEN << 16UL) /*!< USART LIN function */
+#define USART_LIN_WKUP (USART_CR2_WKUPE << 16UL) /*!< USART LIN wakeup signal detect function */
+#define USART_LIN_ERR (USART_CR2_BEE << 16UL) /*!< USART LIN bus error detect function */
+#define USART_LIN_BREAK (USART_CR2_LBDL << 16UL) /*!< USART LIN bus break field detect function */
+#define USART_LIN_INT_ERR (USART_CR2_BEIE << 16UL) /*!< USART LIN bus error detect interrupt function */
+#define USART_LIN_INT_BREAK (USART_CR2_LBDIE << 16UL) /*!< USART LIN bus break field detect interrupt function */
+#define USART_LIN_INT_WKUP (USART_CR2_WKUPIE << 16UL) /*!< USART LIN bus wakeup signal detect interrupt function */
+
+#define USART_FUNC_ALL (USART_TX | USART_RX | USART_INT_RX | USART_INT_TX_CPLT | USART_RX_TIMEOUT | \
+ USART_INT_RX_TIMEOUT | USART_INT_TX_EMPTY | USART_LIN | USART_LIN_WKUP | \
+ USART_LIN_ERR | USART_LIN_BREAK | USART_LIN_INT_ERR | USART_LIN_INT_BREAK | \
+ USART_LIN_INT_WKUP | USART_INT_TX_END)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_Parity_Control USART Parity Control
+ * @{
+ */
+#define USART_PARITY_NONE (0UL) /*!< Parity control disabled */
+#define USART_PARITY_EVEN (USART_CR1_PCE) /*!< Parity control enabled and Even Parity is selected */
+#define USART_PARITY_ODD (USART_CR1_PCE | \
+ USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_Data_Width_Bit USART Data Width Bit
+ * @{
+ */
+#define USART_DATA_WIDTH_8BIT (0UL) /*!< 8 bits */
+#define USART_DATA_WIDTH_9BIT (USART_CR1_M) /*!< 9 bits */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_Over_Sample_Bit USART Over Sample Bit
+ * @{
+ */
+#define USART_OVER_SAMPLE_16BIT (0UL) /*!< Oversampling by 16 bits */
+#define USART_OVER_SAMPLE_8BIT (USART_CR1_OVER8) /*!< Oversampling by 8 bits */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_First_Bit USART First Bit
+ * @{
+ */
+#define USART_FIRST_BIT_LSB (0UL) /*!< LSB(Least Significant Bit) */
+#define USART_FIRST_BIT_MSB (USART_CR1_ML) /*!< MSB(Most Significant Bit) */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_Start_Bit_Polarity USART Start Bit Polarity
+ * @{
+ */
+#define USART_START_BIT_LOW (0UL) /*!< Detect RX pin low level */
+#define USART_START_BIT_FALLING (USART_CR1_SBS) /*!< Detect RX pin falling edge */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_Clock_Source USART Clock Source
+ * @{
+ */
+#define USART_CLK_SRC_INTERNCLK (0UL) /*!< Select internal clock source and don't output clock */
+#define USART_CLK_SRC_EXTCLK (USART_CR2_CLKC_1) /*!< Select external clock source. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_CK_Output_Selection USART_CK Output Selection
+ * @{
+ */
+#define USART_CK_OUTPUT_DISABLE (0UL) /*!< Disable USART_CK output */
+#define USART_CK_OUTPUT_ENABLE (USART_CR2_CLKC_0) /*!< Enable USART_CK output. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_Stop_Bit USART Stop Bit
+ * @{
+ */
+#define USART_STOPBIT_1BIT (0UL) /*!< 1 stop bit */
+#define USART_STOPBIT_2BIT (USART_CR2_STOP) /*!< 2 stop bit */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_Hardware_Flow_Control USART Hardware Flow Control
+ * @{
+ */
+#define USART_HW_FLOWCTRL_CTS (USART_CR3_CTSE) /*!< USART hardware flow control CTS mode */
+#define USART_HW_FLOWCTRL_RTS (USART_CR3_CTSE >> 1U) /*!< USART hardware flow control RTS mode */
+#define USART_HW_FLOWCTRL_NONE (0UL) /*!< Disable USART hardware flow control */
+#define USART_HW_FLOWCTRL_RTS_CTS (USART_HW_FLOWCTRL_CTS | \
+ USART_HW_FLOWCTRL_RTS) /*!< USART hardware flow control RTS and CTS mode */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_Clock_Division USART Clock Division
+ * @{
+ */
+#define USART_CLK_DIV1 (0UL) /*!< CLK */
+#define USART_CLK_DIV4 (1UL) /*!< CLK/4 */
+#define USART_CLK_DIV16 (2UL) /*!< CLK/16 */
+#define USART_CLK_DIV64 (3UL) /*!< CLK/64 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_Max_Timeout USART Max Timeout
+ * @{
+ */
+#define USART_MAX_TIMEOUT (0xFFFFFFFFUL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_Smartcard_ETU_Clock USART Smartcard ETU Clock
+ * @{
+ */
+#define USART_SC_ETU_CLK32 (0UL << USART_CR3_BCN_POS) /*!< 1 etu = 32/f */
+#define USART_SC_ETU_CLK64 (1UL << USART_CR3_BCN_POS) /*!< 1 etu = 64/f */
+#define USART_SC_ETU_CLK128 (3UL << USART_CR3_BCN_POS) /*!< 1 etu = 128/f */
+#define USART_SC_ETU_CLK256 (5UL << USART_CR3_BCN_POS) /*!< 1 etu = 256/f */
+#define USART_SC_ETU_CLK372 (6UL << USART_CR3_BCN_POS) /*!< 1 etu = 372/f */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_Stop_Mode_Noise_Filter_Width_Level USART Stop Mode Noise Filter Width Level
+ * @{
+ */
+#define USART_STOP_MD_FILTER_LVL1 (0UL) /*!< Filter width level 1 */
+#define USART_STOP_MD_FILTER_LVL2 (PERIC_USART1_NFC_USASRT1_NFS_0) /*!< Filter width level 2 */
+#define USART_STOP_MD_FILTER_LVL3 (PERIC_USART1_NFC_USASRT1_NFS_1) /*!< Filter width level 3 */
+#define USART_STOP_MD_FILTER_LVL4 (PERIC_USART1_NFC_USASRT1_NFS) /*!< Filter width level 4 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_LIN_BMC_Clock_Division USART LIN Baudrate Measure Counter Clock Division
+ * @{
+ */
+#define USART_LIN_BMC_CLK_DIV1 (0UL) /*!< CLK */
+#define USART_LIN_BMC_CLK_DIV2 (USART_PR_LBMPSC_0) /*!< CLK/2 */
+#define USART_LIN_BMC_CLK_DIV4 (USART_PR_LBMPSC_1) /*!< CLK/4 */
+#define USART_LIN_BMC_CLK_DIV8 (USART_PR_LBMPSC) /*!< CLK/8 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_LIN_Send_Break_Mode USART LIN Send Break Mode
+ * @{
+ */
+#define USART_LIN_SEND_BREAK_MD_SBK (0UL) /*!< Start send break after USART_CR2 SBK bit set 1 value */
+#define USART_LIN_SEND_BREAK_MD_TDR (USART_CR2_SBKM) /*!< Start send break after USART_DR TDR write 0x00 value */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_LIN_Detect_Break_Length USART LIN Detect Break Length
+ * @{
+ */
+#define USART_LIN_DETECT_BREAK_10BIT (0UL) /*!< Detect break 10-bit */
+#define USART_LIN_DETECT_BREAK_11BIT (USART_CR2_LBDL) /*!< Detect break 11-bit */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_LIN_Send_Break_Length USART LIN Send Break Length
+ * @{
+ */
+#define USART_LIN_SEND_BREAK_10BIT (0UL) /*!< Send break 10-bit */
+#define USART_LIN_SEND_BREAK_11BIT (USART_CR2_SBKL_0) /*!< Send break 11-bit */
+#define USART_LIN_SEND_BREAK_13BIT (USART_CR2_SBKL_1) /*!< Send break 13-bit */
+#define USART_LIN_SEND_BREAK_14BIT (USART_CR2_SBKL) /*!< Send break 14-bit */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup USART_Global_Functions
+ * @{
+ */
+int32_t USART_ClockSync_StructInit(stc_usart_clocksync_init_t *pstcClockSyncInit);
+int32_t USART_ClockSync_Init(CM_USART_TypeDef *USARTx,
+ const stc_usart_clocksync_init_t *pstcClockSyncInit, float32_t *pf32Error);
+int32_t USART_MultiProcessor_StructInit(stc_usart_multiprocessor_init_t *pstcMultiProcessorInit);
+int32_t USART_MultiProcessor_Init(CM_USART_TypeDef *USARTx,
+ const stc_usart_multiprocessor_init_t *pstcMultiProcessorInit, float32_t *pf32Error);
+int32_t USART_UART_StructInit(stc_usart_uart_init_t *pstcUartInit);
+int32_t USART_UART_Init(CM_USART_TypeDef *USARTx, const stc_usart_uart_init_t *pstcUartInit, float32_t *pf32Error);
+
+int32_t USART_HalfDuplex_Init(CM_USART_TypeDef *USARTx,
+ const stc_usart_uart_init_t *pstcUartInit, float32_t *pf32Error);
+
+int32_t USART_LIN_StructInit(stc_usart_lin_init_t *pstcLinInit);
+int32_t USART_LIN_Init(CM_USART_TypeDef *USARTx, const stc_usart_lin_init_t *pstcLinInit, float32_t *pf32Error);
+
+int32_t USART_SmartCard_StructInit(stc_usart_smartcard_init_t *pstcSmartCardInit);
+int32_t USART_SmartCard_Init(CM_USART_TypeDef *USARTx,
+ const stc_usart_smartcard_init_t *pstcSmartCardInit, float32_t *pf32Error);
+
+int32_t USART_DeInit(CM_USART_TypeDef *USARTx);
+void USART_FuncCmd(CM_USART_TypeDef *USARTx, uint32_t u32Func, en_functional_state_t enNewState);
+en_functional_state_t USART_GetFuncState(CM_USART_TypeDef *USARTx, uint32_t u32Func);
+en_flag_status_t USART_GetStatus(const CM_USART_TypeDef *USARTx, uint32_t u32Flag);
+void USART_ClearStatus(CM_USART_TypeDef *USARTx, uint32_t u32Flag);
+void USART_SetParity(CM_USART_TypeDef *USARTx, uint32_t u32Parity);
+void USART_SetFirstBit(CM_USART_TypeDef *USARTx, uint32_t u32FirstBit);
+void USART_SetStopBit(CM_USART_TypeDef *USARTx, uint32_t u32StopBit);
+void USART_SetDataWidth(CM_USART_TypeDef *USARTx, uint32_t u32DataWidth);
+void USART_SetOverSampleBit(CM_USART_TypeDef *USARTx, uint32_t u32OverSampleBit);
+void USART_SetStartBitPolarity(CM_USART_TypeDef *USARTx, uint32_t u32Polarity);
+void USART_SetTransType(CM_USART_TypeDef *USARTx, uint16_t u16Type);
+void USART_SetClockDiv(CM_USART_TypeDef *USARTx, uint32_t u32ClockDiv);
+uint32_t USART_GetClockDiv(const CM_USART_TypeDef *USARTx);
+void USART_SetClockSrc(CM_USART_TypeDef *USARTx, uint32_t u32ClockSrc);
+uint32_t USART_GetClockSrc(const CM_USART_TypeDef *USARTx);
+void USART_FilterCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState);
+void USART_SilenceCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState);
+void USART_SetHWFlowControl(CM_USART_TypeDef *USARTx, uint32_t u32HWFlowControl);
+uint16_t USART_ReadData(const CM_USART_TypeDef *USARTx);
+void USART_WriteData(CM_USART_TypeDef *USARTx, uint16_t u16Data);
+void USART_WriteID(CM_USART_TypeDef *USARTx, uint16_t u16ID);
+
+int32_t USART_SetBaudrate(CM_USART_TypeDef *USARTx, uint32_t u32Baudrate, float32_t *pf32Error);
+
+void USART_SmartCard_SetEtuClock(CM_USART_TypeDef *USARTx, uint32_t u32EtuClock);
+
+void USART_StopModeNoiseFilterCmd(const CM_USART_TypeDef *USARTx, en_functional_state_t enNewState);
+void USART_SetStopModeNoiseFilter(const CM_USART_TypeDef *USARTx, uint32_t u32Level);
+
+void USART_LIN_LoopbackCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState);
+void USART_LIN_SetBmcClockDiv(CM_USART_TypeDef *USARTx, uint32_t u32ClockDiv);
+void USART_LIN_RequestBreakSending(CM_USART_TypeDef *USARTx);
+en_flag_status_t USART_LIN_GetRequestBreakStatus(const CM_USART_TypeDef *USARTx);
+void USART_LIN_SetBreakMode(CM_USART_TypeDef *USARTx, uint32_t u32Mode);
+uint32_t USART_LIN_GetBreakMode(const CM_USART_TypeDef *USARTx);
+uint32_t USART_LIN_GetMeasureCount(const CM_USART_TypeDef *USARTx);
+uint32_t USART_LIN_GetMeasureBaudrate(const CM_USART_TypeDef *USARTx);
+void USART_LIN_SetDetectBreakLen(CM_USART_TypeDef *USARTx, uint32_t u32Len);
+void USART_LIN_SetSendBreakLen(CM_USART_TypeDef *USARTx, uint32_t u32Len);
+
+int32_t USART_UART_Trans(CM_USART_TypeDef *USARTx, const void *pvBuf, uint32_t u32Len, uint32_t u32Timeout);
+int32_t USART_UART_Receive(const CM_USART_TypeDef *USARTx, void *pvBuf, uint32_t u32Len, uint32_t u32Timeout);
+int32_t USART_ClockSync_Trans(CM_USART_TypeDef *USARTx, const uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout);
+int32_t USART_ClockSync_Receive(CM_USART_TypeDef *USARTx, uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout);
+int32_t USART_ClockSync_TransReceive(CM_USART_TypeDef *USARTx, const uint8_t au8TxBuf[], uint8_t au8RxBuf[],
+ uint32_t u32Len, uint32_t u32Timeout);
+
+/**
+ * @}
+ */
+
+#endif /* LL_USART_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_USART_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_usb.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_usb.h
new file mode 100644
index 0000000000..26b7bf88fc
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_usb.h
@@ -0,0 +1,688 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_usb.h
+ * @brief A detailed description is available at hardware registers.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Add API USB_DeInit()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_USB_H__
+#define __HC32_LL_USB_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+#include "usb_app_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_USB
+ * @{
+ */
+
+#if (LL_USB_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+#define USB_MAX_TX_FIFOS (12U)
+#define USB_MAX_CH_NUM (USB_MAX_TX_FIFOS)
+#define USB_MAX_EP_NUM (6U)
+
+/* USB Core ID define */
+#define USBFS_CORE_ID (0U)
+#define USBHS_CORE_ID (1U)
+
+/* USB PHY type define for USBHS core */
+#define USBHS_PHY_EMBED (0U)
+#define USBHS_PHY_EXT (1U)
+
+#define USB_MAX_EP0_SIZE (64U)
+/* working mode of the USB core */
+#define DEVICE_MODE (0U)
+#define HOST_MODE (1U)
+
+/* Macro definations for device mode*/
+#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << USBFS_DSTS_ENUMSPD_POS)
+#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << USBFS_DSTS_ENUMSPD_POS)
+#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << USBFS_DSTS_ENUMSPD_POS)
+#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << USBFS_DSTS_ENUMSPD_POS)
+
+/* EP type */
+#define EP_TYPE_CTRL (0U)
+#define EP_TYPE_ISOC (1U)
+#define EP_TYPE_BULK (2U)
+#define EP_TYPE_INTR (3U)
+#define EP_TYPE_MSK (3U)
+
+/* USB port speed */
+#define PRTSPD_FULL_SPEED (1U)
+#define PRTSPD_LOW_SPEED (2U)
+
+/* PHY clock */
+#define HCFG_30_60_MHZ (0U)
+#define HCFG_48_MHZ (1U)
+#define HCFG_6_MHZ (2U)
+
+#define USB_EP_TX_DIS (0x0000U)
+#define USB_EP_TX_STALL (0x0010U)
+#define USB_EP_TX_NAK (0x0020U)
+#define USB_EP_TX_VALID (0x0030U)
+
+#define USB_EP_RX_DIS (0x0000U)
+#define USB_EP_RX_STALL (0x1000U)
+#define USB_EP_RX_NAK (0x2000U)
+#define USB_EP_RX_VALID (0x3000U)
+
+#define USB_OK (0U)
+#define USB_ERROR (1U)
+
+#define USB_FRAME_INTERVAL_80 (0UL << USBFS_DCFG_PFIVL_POS)
+#define USB_FRAME_INTERVAL_85 (1UL << USBFS_DCFG_PFIVL_POS)
+#define USB_FRAME_INTERVAL_90 (2UL << USBFS_DCFG_PFIVL_POS)
+#define USB_FRAME_INTERVAL_95 (3UL << USBFS_DCFG_PFIVL_POS)
+
+#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \
+ (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U))
+#define LOBYTE(x) ((uint8_t)((uint16_t)(x) & 0x00FFU))
+#define HIBYTE(x) ((uint8_t)(((uint16_t)(x) & 0xFF00U) >>8U))
+
+#ifdef USB_INTERNAL_DMA_ENABLED
+#define __USB_ALIGN_END
+#if defined (__GNUC__) /* GNU Compiler */
+#define __USB_ALIGN_BEGIN __attribute__ ((aligned (4)))
+#elif defined (__CC_ARM) /* ARM Compiler */
+#define __USB_ALIGN_BEGIN __align(4)
+#elif defined (__ICCARM__) /* IAR Compiler */
+#define __USB_ALIGN_BEGIN
+#elif defined (__TASKING__) /* TASKING Compiler */
+#define __USB_ALIGN_BEGIN __align(4)
+#endif
+#else
+#define __USB_ALIGN_BEGIN
+#define __USB_ALIGN_END
+#endif
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+typedef struct {
+ __IO uint32_t GVBUSCFG; /* VBUS Configuration Register 000h */
+ uint32_t Reserved04; /* Reserved 004h */
+ __IO uint32_t GAHBCFG; /* AHB Configuration Register 008h */
+ __IO uint32_t GUSBCFG; /* USB Configuration Register 00Ch */
+ __IO uint32_t GRSTCTL; /* Reset Register 010h */
+ __IO uint32_t GINTSTS; /* Interrupt Register 014h */
+ __IO uint32_t GINTMSK; /* Interrupt Mask Register 018h */
+ __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch */
+ __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h */
+ __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h */
+ __IO uint32_t HNPTXFSIZ; /* HNPTXFSIZ: Host Non-Periodic Transmit FIFO Size Register 028h
+ DIEPTXF0: Device IN EP0 Transmit FIFO size register 028h */
+ __IO uint32_t HNPTXSTS; /* Host Non Periodic Transmit FIFO/Queue Status Register 02Ch */
+ uint32_t Reserved30[3]; /* Reserved 030h-038h */
+ __IO uint32_t CID; /* User ID Register 03Ch */
+ uint32_t Reserved40[5]; /* Reserved 040h-050h */
+ __IO uint32_t GLPMCFG; /* Low Power Mode Configuration Register 054h */
+ uint32_t Reserved58[42]; /* Reserved 058h-0FCh */
+ __IO uint32_t HPTXFSIZ; /* Host Periodic Transmit FIFO Size Register 100h */
+ __IO uint32_t DIEPTXF[USB_MAX_TX_FIFOS]; /* Device Periodic Transmit FIFO Size Register */
+} USB_CORE_GREGS;
+
+typedef struct {
+ __IO uint32_t DCFG; /* Device Configuration Register 800h */
+ __IO uint32_t DCTL; /* Device Control Register 804h */
+ __IO uint32_t DSTS; /* Device Status Register (RO) 808h */
+ uint32_t Reserved0C; /* Reserved 80Ch */
+ __IO uint32_t DIEPMSK; /* Device IN EP Common Interrupt Mask Register 810h */
+ __IO uint32_t DOEPMSK; /* Device OUT EP Common Interrupt Mask Register 814h */
+ __IO uint32_t DAINT; /* Device All EP Interrupt Register 818h */
+ __IO uint32_t DAINTMSK; /* Device All EP Interrupt Mask Register 81Ch */
+ uint32_t Reserved20[4]; /* Reserved 820h-82Ch */
+ __IO uint32_t DTHRCTL; /* Device Threshold Control Register 830h */
+ __IO uint32_t DIEPEMPMSK; /* Device IN EP FIFO Empty Interrupt Mask Register 834h */
+ __IO uint32_t DEACHINT; /* Device Each EP Interrupt Register 838h */
+ __IO uint32_t DEACHINTMSK; /* Device Each EP Interrupt Mask Register 83Ch */
+ uint32_t Reserved40; /* Reserved 840h */
+ __IO uint32_t DIEPEACHMSK1; /* Device IN EP1 Interrupt Mask Register 844h */
+ uint32_t Reserved48[15]; /* Reserved 848-880h */
+ __IO uint32_t DOEPEACHMSK1; /* Device OUT EP1 Interrupt Mask Register 884h */
+} USB_CORE_DREGS;
+
+typedef struct {
+ __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS; /* IN Endpoint Tx FIFO Status 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+} USB_CORE_INEPREGS;
+
+typedef struct {
+ __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_CORE_OUTEPREGS;
+
+typedef struct {
+ __IO uint32_t HCFG; /* Host Configuration Register 400h*/
+ __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
+ __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
+ uint32_t Reserved40C; /* Reserved 40Ch*/
+ __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
+ __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
+ __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
+} USB_CORE_HREGS;
+
+typedef struct {
+ __IO uint32_t HCCHAR;
+ __IO uint32_t HCSPLT;
+ __IO uint32_t HCINT;
+ __IO uint32_t HCINTMSK;
+ __IO uint32_t HCTSIZ;
+ __IO uint32_t HCDMA;
+ uint32_t Reserved[2];
+} USB_CORE_HC_REGS;
+
+typedef struct { /* 000h */
+ USB_CORE_GREGS *GREGS;
+ USB_CORE_DREGS *DREGS;
+ USB_CORE_HREGS *HREGS;
+ USB_CORE_INEPREGS *INEP_REGS[USB_MAX_TX_FIFOS];
+ USB_CORE_OUTEPREGS *OUTEP_REGS[USB_MAX_TX_FIFOS];
+ USB_CORE_HC_REGS *HC_REGS[USB_MAX_TX_FIFOS];
+ __IO uint32_t *HPRT;
+ __IO uint32_t *DFIFO[USB_MAX_TX_FIFOS];
+ __IO uint32_t *GCCTL;
+} LL_USB_TypeDef;
+
+typedef struct {
+ uint8_t host_chnum;
+ uint8_t dev_epnum;
+ uint8_t dmaen;
+ uint8_t low_power;
+ uint8_t phy_type;
+ uint8_t core_type;
+} USB_CORE_BASIC_CFGS;
+
+typedef struct {
+ uint8_t dev_addr;
+ uint8_t ep_idx;
+ uint8_t is_epin;
+ uint8_t ch_speed;
+ uint8_t do_ping;
+ uint8_t ep_type;
+ uint16_t max_packet;
+ uint8_t pid_type;
+ uint8_t in_toggle;
+ uint8_t out_toggle;
+ /* transaction level variables*/
+ uint32_t dma_addr;
+ uint32_t xfer_len;
+ uint32_t xfer_count;
+ uint8_t *xfer_buff;
+} USB_HOST_CH;
+
+typedef struct {
+ uint8_t epidx;
+ uint8_t ep_dir;
+ uint8_t trans_type;
+ uint8_t ep_stall;
+ uint8_t data_pid_start;
+ uint8_t datax_pid;
+ uint16_t tx_fifo_num;
+ uint32_t maxpacket;
+ /* Transfer level variables */
+ uint32_t rem_data_len;
+ uint32_t total_data_len;
+ uint32_t ctl_data_len;
+ /* transaction level variables*/
+ uint32_t dma_addr;
+ uint32_t xfer_len;
+ uint32_t xfer_count;
+ uint8_t *xfer_buff;
+} USB_DEV_EP;
+
+typedef struct {
+ uint8_t u8CoreID; /* USBFS_CORE_ID or USBHS_CORE_ID */
+} stc_usb_port_identify;
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+
+/**
+ * @addtogroup USB_Global_Functions
+ * @{
+ */
+
+/**
+ * @brief get the current mode of the usb core from the corresponding register
+ * @param [in] USBx usb instance
+ * @retval current mode 1: host mode 0: device mode
+ */
+__STATIC_INLINE uint8_t usb_getcurmod(LL_USB_TypeDef *USBx)
+{
+ if (0UL != READ_REG32_BIT(USBx->GREGS->GINTSTS, USBFS_GINTSTS_CMOD)) {
+ return 1U;
+ } else {
+ return 0U;
+ }
+}
+
+/**
+ * @brief Initializes the normal interrupts
+ * @param [in] USBx usb instance
+ * @retval None
+ */
+__STATIC_INLINE void usb_normalinten(LL_USB_TypeDef *USBx)
+{
+ WRITE_REG32(USBx->GREGS->GINTSTS, 0xBFFFFFFFUL);
+ WRITE_REG32(USBx->GREGS->GINTMSK, USBFS_GINTMSK_WKUIM | USBFS_GINTMSK_USBSUSPM);
+}
+
+/**
+ * @brief clear all the pending device interrupt bits and mask the IN and OUT
+ * endpoint interrupts.
+ * @param [in] USBx usb instance
+ * @retval None
+ */
+__STATIC_INLINE void usb_clrandmskepint(LL_USB_TypeDef *USBx)
+{
+ WRITE_REG32(USBx->DREGS->DIEPMSK, 0UL);
+ WRITE_REG32(USBx->DREGS->DOEPMSK, 0UL);
+ WRITE_REG32(USBx->DREGS->DAINT, 0xFFFFFFFFUL);
+ WRITE_REG32(USBx->DREGS->DAINTMSK, 0UL);
+}
+
+/**
+ * @brief generate a device connect signal to the USB host
+ * @param [in] USBx usb instance
+ * @retval None
+ */
+__STATIC_INLINE void usb_coreconn(LL_USB_TypeDef *USBx)
+{
+ CLR_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_SDIS);
+}
+
+/**
+ * @brief test of mode processing
+ * @param [in] USBx usb instance
+ * @param [in] reg Register write
+ * @retval None
+ */
+__STATIC_INLINE void usb_runtestmode(LL_USB_TypeDef *USBx, uint32_t reg)
+{
+ WRITE_REG32(USBx->DREGS->DCTL, reg);
+}
+
+/**
+ * @brief Enables the controller's Global interrupts in the AHB Configuration
+ * registers.
+ * @param [in] USBx usb instance
+ * @retval None
+ */
+__STATIC_INLINE void usb_ginten(LL_USB_TypeDef *USBx)
+{
+ SET_REG32_BIT(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_GINTMSK);
+}
+
+/**
+ * @brief Disable the controller's Global interrupt in the AHB Configuration
+ * register.
+ * @param [in] USBx usb instance
+ * @retval None
+ */
+__STATIC_INLINE void usb_gintdis(LL_USB_TypeDef *USBx)
+{
+ CLR_REG32_BIT(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_GINTMSK);
+}
+
+/**
+ * @brief Get the Core Interrupt bits from the interrupt register not including
+ * the bits that are masked.
+ * @param [in] USBx usb instance
+ * @retval status[32bits]
+ */
+__STATIC_INLINE uint32_t usb_getcoreintr(LL_USB_TypeDef *USBx)
+{
+ uint32_t v;
+ v = READ_REG32(USBx->GREGS->GINTSTS);
+ v &= READ_REG32(USBx->GREGS->GINTMSK);
+ return v;
+}
+
+/**
+ * @brief Get the out endpoint interrupt bits from the all endpoint interrupt
+ * register not including the bits masked.
+ * @param [in] USBx usb instance
+ * @retval The status that shows which OUT EP have interrupted.
+ */
+__STATIC_INLINE uint32_t usb_getalloepintr(LL_USB_TypeDef *USBx)
+{
+ uint32_t v;
+ v = READ_REG32(USBx->DREGS->DAINT);
+ v &= READ_REG32(USBx->DREGS->DAINTMSK);
+ return ((v & 0xFFFF0000UL) >> 16U);
+}
+
+/**
+ * @brief Get the Device OUT EP Interrupt register(DOEPINT) not including the
+ * interrupt bits that are masked.
+ * @param [in] USBx usb instance
+ * @param [in] epnum end point index
+ * @retval all the interrupt bits on DOEPINTn while n = epnum
+ */
+__STATIC_INLINE uint32_t usb_getoepintbit(LL_USB_TypeDef *USBx, uint8_t epnum)
+{
+ uint32_t v;
+ v = READ_REG32(USBx->OUTEP_REGS[epnum]->DOEPINT);
+ v &= READ_REG32(USBx->DREGS->DOEPMSK);
+ return v;
+}
+
+/**
+ * @brief Get the IN endpoint interrupt bits from the all endpoint interrupt
+ * register not including the bits masked.
+ * @param [in] USBx usb instance
+ * @retval The status that shows which IN EP have interrupted.
+ */
+__STATIC_INLINE uint32_t usb_getalliepintr(LL_USB_TypeDef *USBx)
+{
+ uint32_t v;
+ v = READ_REG32(USBx->DREGS->DAINT);
+ v &= READ_REG32(USBx->DREGS->DAINTMSK);
+ return (v & 0xFFFFUL);
+}
+
+/**
+ * @brief Set the device a new address.
+ * @param [in] USBx usb instance
+ * @param [in] address device address which will be set to the corresponding register.
+ * @retval None
+ */
+__STATIC_INLINE void usb_devaddrset(LL_USB_TypeDef *USBx, uint8_t address)
+{
+ MODIFY_REG32(USBx->DREGS->DCFG, USBFS_DCFG_DAD, (uint32_t)address << USBFS_DCFG_DAD_POS);
+}
+
+/**
+ * @brief Select the USB PHY.
+ * @param [in] USBx usb instance
+ * @param [in] PhyType USB phy, 1 select external ULPI PHY, 0 select internal FS PHY
+ * @retval None
+ */
+__STATIC_INLINE void usb_PhySelect(LL_USB_TypeDef *USBx, uint8_t PhyType)
+{
+ if (USBHS_PHY_EXT == PhyType) {
+ CLR_REG32_BIT(USBx->GREGS->GUSBCFG, USBFS_GUSBCFG_PHYSEL);
+ //SET_REG32_BIT(USBx->GREGS->GUSBCFG, 1UL<<4);
+ } else {
+ SET_REG32_BIT(USBx->GREGS->GUSBCFG, USBFS_GUSBCFG_PHYSEL);
+ }
+}
+
+/**
+ * @brief Select the USB device PHY.
+ * @param [in] USBx usb instance
+ * @param [in] PhyType USB phy, 1 select external ULPI PHY, 0 select internal FS PHY
+ * @retval None
+ */
+__STATIC_INLINE void usb_DevPhySelect(LL_USB_TypeDef *USBx, uint8_t PhyType)
+{
+ if (1U == PhyType) {
+ CLR_REG32_BIT(USBx->DREGS->DCFG, USBFS_DCFG_DSPD);
+ } else {
+ SET_REG32_BIT(USBx->DREGS->DCFG, USBFS_DCFG_DSPD);
+ }
+
+}
+
+/**
+ * @brief USB DMA function command.
+ * @param [in] USBx usb instance
+ * @param [in] DmaCmd USB DMA command status, 0 disable, 1 enable
+ * @retval None
+ */
+__STATIC_INLINE void usb_DmaCmd(LL_USB_TypeDef *USBx, uint8_t DmaCmd)
+{
+ MODIFY_REG32(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_DMAEN, (uint32_t)DmaCmd << USBFS_GAHBCFG_DMAEN_POS);
+}
+
+/**
+ * @brief USB burst length config.
+ * @param [in] USBx usb instance
+ * @param [in] len Burst length
+ * @retval None
+ */
+__STATIC_INLINE void usb_BurstLenConfig(LL_USB_TypeDef *USBx, uint8_t len)
+{
+ MODIFY_REG32(USBx->GREGS->GAHBCFG, USBFS_GAHBCFG_HBSTLEN, (uint32_t)len << USBFS_GAHBCFG_HBSTLEN_POS);
+}
+
+/**
+ * @brief USB frame interval config
+ * @param [in] USBx usb instance
+ * @param [in] interval Frame interval
+ * @retval None
+ */
+__STATIC_INLINE void usb_FrameIntervalConfig(LL_USB_TypeDef *USBx, uint8_t interval)
+{
+ MODIFY_REG32(USBx->DREGS->DCFG, USBFS_DCFG_PFIVL, interval);
+}
+
+#ifdef USE_HOST_MODE
+/**
+ * @brief Read the register HPRT and reset the following bits.
+ * @param [in] USBx usb instance
+ * @retval value of HPRT
+ */
+//#define USBFS_HPRT_PRTOVRCURRCHNG (0x00000020UL)
+__STATIC_INLINE uint32_t usb_rdhprt(LL_USB_TypeDef *USBx)
+{
+ return (READ_REG32(*USBx->HPRT) & ~(USBFS_HPRT_PENA | USBFS_HPRT_PCDET | USBFS_HPRT_PENCHNG));
+}
+
+/**
+ * @brief Issues a ping token
+ * @param [in] USBx usb instance
+ * @param [in] hc_num the host channel index
+ * @retval None
+ */
+//#define USBFS_HCTSIZ_DOPNG (0x80000000UL)
+__STATIC_INLINE void usb_pingtokenissue(LL_USB_TypeDef *USBx, uint8_t hc_num)
+{
+ WRITE_REG32(USBx->HC_REGS[hc_num]->HCTSIZ, 1UL << USBFS_HCTSIZ_PKTCNT_POS);
+ MODIFY_REG32(USBx->HC_REGS[hc_num]->HCCHAR, USBFS_HCCHAR_CHENA | USBFS_HCCHAR_CHDIS, USBFS_HCCHAR_CHENA);
+}
+
+/**
+ * @brief This function returns the frame number for sof packet
+ * @param [in] USBx usb instance
+ * @retval Frame number
+ */
+__STATIC_INLINE uint32_t usb_ifevenframe(LL_USB_TypeDef *USBx)
+{
+ return ((READ_REG32(USBx->HREGS->HFNUM) + 1UL) & 0x1UL);
+}
+
+/**
+ * @brief Initializes the FSLSPClkSel field of the HCFG register on the PHY type
+ * @param [in] USBx usb instance
+ * @param [in] freq clock frequency
+ * @retval None
+ */
+__STATIC_INLINE void usb_fslspclkselset(LL_USB_TypeDef *USBx, uint8_t freq)
+{
+ MODIFY_REG32(USBx->HREGS->HCFG, USBFS_HCFG_FSLSPCS, (uint32_t)freq << USBFS_HCFG_FSLSPCS_POS);
+}
+
+/**
+ * @brief suspend the port
+ * @param [in] USBx usb instance
+ * @retval None
+ */
+__STATIC_INLINE void usb_prtsusp(LL_USB_TypeDef *USBx)
+{
+ uint32_t u32hprt;
+ u32hprt = usb_rdhprt(USBx);
+ u32hprt |= USBFS_HPRT_PSUSP;
+ u32hprt &= ~USBFS_HPRT_PRES;
+ WRITE_REG32(*USBx->HPRT, u32hprt);
+}
+
+/**
+ * @brief control the enumeration speed of the core, this function make sure that
+ * the maximum speed supperted by the connected device.
+ * @param [in] USBx usb instance
+ * @retval None
+ */
+__STATIC_INLINE void usb_enumspeed(LL_USB_TypeDef *USBx)
+{
+ CLR_REG32_BIT(USBx->HREGS->HCFG, USBFS_HCFG_FSLSS);
+}
+
+/**
+ * @brief set the TXFIFO and depth for non-periodic and periodic and RXFIFO size
+ * @param [in] USBx usb instance
+ * @retval None
+ */
+__STATIC_INLINE void usb_sethostfifo(LL_USB_TypeDef *USBx, uint8_t u8CoreID)
+{
+ if (USBFS_CORE_ID == u8CoreID) {
+#ifdef USB_FS_MODE
+ /* USBFS Core*/
+ WRITE_REG32(USBx->GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); /* set the RxFIFO Depth */
+ /* non-periodic transmit RAM start address, set the non-periodic TxFIFO depth */
+ WRITE_REG32(USBx->GREGS->HNPTXFSIZ,
+ (RX_FIFO_FS_SIZE << USBFS_HNPTXFSIZ_NPTXFSA_POS)
+ | (TXH_NP_FS_FIFOSIZ << USBFS_HNPTXFSIZ_NPTXFD_POS));
+ /* set the host periodic TxFIFO start address, set the host periodic TxFIFO depth */
+ WRITE_REG32(USBx->GREGS->HPTXFSIZ,
+ ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ) << USBFS_HPTXFSIZ_PTXSA_POS)
+ | (TXH_P_FS_FIFOSIZ << USBFS_HPTXFSIZ_PTXFD_POS));
+#endif
+ } else {
+#ifdef USB_HS_MODE
+ /* USBHS Core */
+ WRITE_REG32(USBx->GREGS->GRXFSIZ, RX_FIFO_HS_SIZE);
+ WRITE_REG32(USBx->GREGS->HNPTXFSIZ,
+ (RX_FIFO_HS_SIZE << USBFS_HNPTXFSIZ_NPTXFSA_POS)
+ | (TXH_NP_HS_FIFOSIZ << USBFS_HNPTXFSIZ_NPTXFD_POS));
+ WRITE_REG32(USBx->GREGS->HPTXFSIZ,
+ ((RX_FIFO_HS_SIZE + TXH_NP_HS_FIFOSIZ) << USBFS_HPTXFSIZ_PTXSA_POS)
+ | (TXH_P_HS_FIFOSIZ << USBFS_HPTXFSIZ_PTXFD_POS));
+#endif
+ }
+}
+
+/**
+ * @brief reset the channel whose channel number is ch_idx
+ * @param [in] USBx usb instance
+ * @param [in] ch_idx channel number
+ * @retval None
+ */
+__STATIC_INLINE void usb_chrst(LL_USB_TypeDef *USBx, uint8_t ch_idx)
+{
+ MODIFY_REG32(USBx->HC_REGS[ch_idx]->HCCHAR,
+ USBFS_HCCHAR_CHENA | USBFS_HCCHAR_CHDIS | USBFS_HCCHAR_EPDIR,
+ USBFS_HCCHAR_CHDIS);
+}
+#endif /* end of USE_HOST_MODE */
+
+extern void usb_initusbcore(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs);
+extern void usb_setregaddr(LL_USB_TypeDef *USBx, stc_usb_port_identify *pstcPortIdentify, USB_CORE_BASIC_CFGS *basic_cfgs);
+extern void usb_rdpkt(LL_USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
+extern void usb_wrpkt(LL_USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t u8DmaEn);
+extern void usb_txfifoflush(LL_USB_TypeDef *USBx, uint32_t num);
+extern void usb_rxfifoflush(LL_USB_TypeDef *USBx);
+extern void usb_modeset(LL_USB_TypeDef *USBx, uint8_t mode);
+extern void usb_coresoftrst(LL_USB_TypeDef *USBx);
+extern int32_t USB_DeInit(LL_USB_TypeDef *USBx);
+
+#ifdef USE_HOST_MODE
+extern void usb_hostmodeinit(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs);
+extern void usb_hostinten(LL_USB_TypeDef *USBx, uint8_t u8DmaEn);
+extern uint8_t usb_inithch(LL_USB_TypeDef *USBx, uint8_t hc_num, USB_HOST_CH *pCh, uint8_t u8DmaEn);
+extern void usb_hoststop(LL_USB_TypeDef *USBx, uint8_t u8ChNum);
+extern void usb_hchstop(LL_USB_TypeDef *USBx, uint8_t hc_num);
+extern uint8_t usb_hchtransbegin(LL_USB_TypeDef *USBx, uint8_t hc_num, USB_HOST_CH *pCh, uint8_t u8DmaEn);
+extern void usb_hprtrst(LL_USB_TypeDef *USBx);
+extern void usb_vbusctrl(LL_USB_TypeDef *USBx, uint8_t u8State);
+#endif
+
+#ifdef USE_DEVICE_MODE
+extern void usb_devmodeinit(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs);
+extern void usb_devinten(LL_USB_TypeDef *USBx, uint8_t u8DmaEn);
+extern void usb_ep0activate(LL_USB_TypeDef *USBx);
+extern void usb_epactive(LL_USB_TypeDef *USBx, USB_DEV_EP *ep);
+extern void usb_epdeactive(LL_USB_TypeDef *USBx, USB_DEV_EP *ep);
+extern void usb_epntransbegin(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint8_t u8DmaEn);
+extern void usb_ep0transbegin(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint8_t u8DmaEn);
+extern void usb_setepstall(LL_USB_TypeDef *USBx, USB_DEV_EP *ep);
+extern void usb_clearepstall(LL_USB_TypeDef *USBx, USB_DEV_EP *ep);
+extern void usb_ep0revcfg(LL_USB_TypeDef *USBx, uint8_t u8DmaEn, uint8_t *u8RevBuf);
+extern void usb_remotewakeupen(LL_USB_TypeDef *USBx);
+extern void usb_epstatusset(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint32_t Status);
+extern uint32_t usb_epstatusget(LL_USB_TypeDef *USBx, USB_DEV_EP *ep);
+extern void usb_devepdis(LL_USB_TypeDef *USBx, uint8_t u8EpNum);
+extern void usb_ctrldevconnect(LL_USB_TypeDef *USBx, uint8_t link);
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* LL_USB_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_USB_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_utility.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_utility.h
new file mode 100644
index 0000000000..5c58e9c6aa
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_utility.h
@@ -0,0 +1,131 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_utility.h
+ * @brief This file contains all the functions prototypes of the DDL utility.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_UTILITY_H__
+#define __HC32_LL_UTILITY_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_UTILITY
+ * @{
+ */
+
+#if (LL_UTILITY_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup UTILITY_Global_Functions
+ * @{
+ */
+
+/* Imprecise delay */
+void DDL_DelayMS(uint32_t u32Count);
+void DDL_DelayUS(uint32_t u32Count);
+
+/* Systick functions */
+int32_t SysTick_Init(uint32_t u32Freq);
+void SysTick_Delay(uint32_t u32Delay);
+void SysTick_IncTick(void);
+uint32_t SysTick_GetTick(void);
+void SysTick_Suspend(void);
+void SysTick_Resume(void);
+
+#if (LL_PRINT_ENABLE == DDL_ON)
+int32_t LL_PrintfInit(void *vpDevice, uint32_t u32Param, int32_t (*pfnPreinit)(void *vpDevice, uint32_t u32Param));
+#endif
+
+/* You can add your own assert functions by implement the function DDL_AssertHandler
+ definition follow the function DDL_AssertHandler declaration */
+#ifdef __DEBUG
+#define DDL_ASSERT(x) \
+do { \
+ ((x) ? (void)0 : DDL_AssertHandler(__FILE__, __LINE__)); \
+} while (0)
+/* Exported function */
+void DDL_AssertHandler(const char *file, int line);
+#else
+#define DDL_ASSERT(x) ((void)0U)
+#endif /* __DEBUG */
+
+#if (LL_PRINT_ENABLE == DDL_ON)
+#include
+__WEAKDEF int32_t DDL_ConsoleOutputChar(char cData);
+
+#define DDL_PrintfInit (void)LL_PrintfInit
+#define DDL_Printf (void)printf
+#else
+#define DDL_PrintfInit(vpDevice, u32Param, pfnPreinit)
+#define DDL_Printf(...)
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* LL_UTILITY_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_UTILITY_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_vref.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_vref.h
new file mode 100644
index 0000000000..dc79e6e9b7
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_vref.h
@@ -0,0 +1,138 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_vref.h
+ * @brief This file contains all the functions prototypes of the VREF driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Add API VREF_DeInit()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_VREF_H__
+#define __HC32_LL_VREF_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_VREF
+ * @{
+ */
+
+#if (LL_VREF_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/**
+ * @defgroup VREF_Global_Macros VREF Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup VREF_Intern_Vref_Mode VREF Operating Mode
+ * @{
+ */
+#define VREF_EXT_REF_MD (0x0UL) /*!< External reference voltage mode, use external VREFH as
+ reference voltage. Internal reference voltage is OFF. */
+#define VREF_SHORT_MD (VREF_CR_HIZ) /*!< External VREFH is short to VSS.
+ Internal reference voltage is OFF. */
+#define VREF_INTERN_REF_MD (VREF_CR_IVREFEN) /*!< Use internal reference voltage.
+ External VREFH is short to VREF circuit. */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup VREF_Avcc_Div_Config VREF AVCC Divider configure
+ * @{
+ */
+#define VREF_AVCC_DIV_QUARTER (0x0UL) /*!< AVCC*1/4 */
+#define VREF_AVCC_DIV_ONE_THIRD (VREF_CR_AVCCMONS_0) /*!< AVCC*1/3 */
+#define VREF_AVCC_DIV_TWO_FIFTHS (VREF_CR_AVCCMONS_1) /*!< AVCC*2/5 */
+#define VREF_AVCC_DIV_HALF (VREF_CR_AVCCMONS_1 | VREF_CR_AVCCMONS_0) /*!< AVCC*1/2 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup VREF_Global_Functions
+ * @{
+ */
+void VREF_BandGapRefCmd(en_functional_state_t enNewState);
+void VREF_CurrentSrcCmd(en_functional_state_t enNewState);
+
+void VREF_AvccDivCmd(en_functional_state_t enNewState);
+void VREF_AvccDivConfig(uint32_t u32Div);
+
+void VREF_VrefintCmd(en_functional_state_t enNewState);
+
+void VREF_IvrefCmd(en_functional_state_t enNewState);
+void VREF_SetIvrefMode(uint32_t u32Mode);
+
+int32_t VREF_DeInit(void);
+/**
+ * @}
+ */
+
+#endif /* LL_VREF_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_VREF_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_wdt.h b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_wdt.h
new file mode 100644
index 0000000000..331a8f7bb5
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_wdt.h
@@ -0,0 +1,228 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_wdt.h
+ * @brief This file contains all the functions prototypes of the WDT driver
+ * library.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-12-15 CDT Modify macro define: WDT_LPM_CNT_CONTINUE -> WDT_LPM_CNT_CONT
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32_LL_WDT_H__
+#define __HC32_LL_WDT_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_def.h"
+
+#include "hc32f4xx.h"
+#include "hc32f4xx_conf.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @addtogroup LL_WDT
+ * @{
+ */
+
+#if (LL_WDT_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup WDT_Global_Types WDT Global Types
+ * @{
+ */
+
+/**
+ * @brief WDT Init structure definition
+ */
+typedef struct {
+ uint32_t u32CountPeriod; /*!< Specifies the counting period of WDT.
+ This parameter can be a value of @ref WDT_Count_Period */
+ uint32_t u32ClockDiv; /*!< Specifies the clock division factor of WDT.
+ This parameter can be a value of @ref WDT_Clock_Division */
+ uint32_t u32RefreshRange; /*!< Specifies the allow refresh range of WDT.
+ This parameter can be a value of @ref WDT_Refresh_Range */
+ uint32_t u32LPMCount; /*!< Specifies the count state in Low Power Mode (Sleep Mode).
+ This parameter can be a value of @ref WDT_LPM_Count */
+ uint32_t u32ExceptionType; /*!< Specifies the type of exception response for WDT.
+ This parameter can be a value of @ref WDT_Exception_Type */
+} stc_wdt_init_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup WDT_Global_Macros WDT Global Macros
+ * @{
+ */
+
+/**
+ * @defgroup WDT_Count_Period WDT Count Period
+ * @{
+ */
+#define WDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */
+#define WDT_CNT_PERIOD4096 (WDT_CR_PERI_0) /*!< 4096 clock cycle */
+#define WDT_CNT_PERIOD16384 (WDT_CR_PERI_1) /*!< 16384 clock cycle */
+#define WDT_CNT_PERIOD65536 (WDT_CR_PERI) /*!< 65536 clock cycle */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup WDT_Clock_Division WDT Clock Division
+ * @{
+ */
+#define WDT_CLK_DIV4 (0x02UL << WDT_CR_CKS_POS) /*!< PLCKx/4 */
+#define WDT_CLK_DIV64 (0x06UL << WDT_CR_CKS_POS) /*!< PLCKx/64 */
+#define WDT_CLK_DIV128 (0x07UL << WDT_CR_CKS_POS) /*!< PLCKx/128 */
+#define WDT_CLK_DIV256 (0x08UL << WDT_CR_CKS_POS) /*!< PLCKx/256 */
+#define WDT_CLK_DIV512 (0x09UL << WDT_CR_CKS_POS) /*!< PLCKx/512 */
+#define WDT_CLK_DIV1024 (0x0AUL << WDT_CR_CKS_POS) /*!< PLCKx/1024 */
+#define WDT_CLK_DIV2048 (0x0BUL << WDT_CR_CKS_POS) /*!< PLCKx/2048 */
+#define WDT_CLK_DIV8192 (0x0DUL << WDT_CR_CKS_POS) /*!< PLCKx/8192 */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup WDT_Refresh_Range WDT Refresh Range
+ * @{
+ */
+#define WDT_RANGE_0TO25PCT (0x01UL << WDT_CR_WDPT_POS) /*!< 0%~25% */
+#define WDT_RANGE_25TO50PCT (0x02UL << WDT_CR_WDPT_POS) /*!< 25%~50% */
+#define WDT_RANGE_0TO50PCT (0x03UL << WDT_CR_WDPT_POS) /*!< 0%~50% */
+#define WDT_RANGE_50TO75PCT (0x04UL << WDT_CR_WDPT_POS) /*!< 50%~75% */
+#define WDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << WDT_CR_WDPT_POS) /*!< 0%~25% & 50%~75% */
+#define WDT_RANGE_25TO75PCT (0x06UL << WDT_CR_WDPT_POS) /*!< 25%~75% */
+#define WDT_RANGE_0TO75PCT (0x07UL << WDT_CR_WDPT_POS) /*!< 0%~75% */
+#define WDT_RANGE_75TO100PCT (0x08UL << WDT_CR_WDPT_POS) /*!< 75%~100% */
+#define WDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << WDT_CR_WDPT_POS) /*!< 0%~25% & 75%~100% */
+#define WDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << WDT_CR_WDPT_POS) /*!< 25%~50% & 75%~100% */
+#define WDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << WDT_CR_WDPT_POS) /*!< 0%~50% & 75%~100% */
+#define WDT_RANGE_50TO100PCT (0x0CUL << WDT_CR_WDPT_POS) /*!< 50%~100% */
+#define WDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << WDT_CR_WDPT_POS) /*!< 0%~25% & 50%~100% */
+#define WDT_RANGE_25TO100PCT (0x0EUL << WDT_CR_WDPT_POS) /*!< 25%~100% */
+#define WDT_RANGE_0TO100PCT (0x0FUL << WDT_CR_WDPT_POS) /*!< 0%~100% */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup WDT_LPM_Count WDT Low Power Mode Count
+ * @brief Counting control of WDT in sleep mode.
+ * @{
+ */
+#define WDT_LPM_CNT_CONT (0UL) /*!< Continue counting in sleep mode */
+#define WDT_LPM_CNT_STOP (WDT_CR_SLPOFF) /*!< Stop counting in sleep mode */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup WDT_Exception_Type WDT Exception Type
+ * @brief Specifies the exception response when a refresh error or count overflow occurs.
+ * @{
+ */
+#define WDT_EXP_TYPE_INT (0UL) /*!< WDT trigger interrupt */
+#define WDT_EXP_TYPE_RST (WDT_CR_ITS) /*!< WDT trigger reset */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup WDT_Flag WDT Flag
+ * @{
+ */
+#define WDT_FLAG_UDF (WDT_SR_UDF) /*!< Count underflow flag */
+#define WDT_FLAG_REFRESH (WDT_SR_REF) /*!< Refresh error flag */
+#define WDT_FLAG_ALL (WDT_SR_UDF | WDT_SR_REF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ Global function prototypes (definition in C source)
+ ******************************************************************************/
+/**
+ * @addtogroup WDT_Global_Functions
+ * @{
+ */
+
+/**
+ * @brief Get WDT count value.
+ * @param None
+ * @retval uint16_t Count value
+ */
+__STATIC_INLINE uint16_t WDT_GetCountValue(void)
+{
+ return (uint16_t)(READ_REG32(CM_WDT->SR) & WDT_SR_CNT);
+}
+
+/* Initialization and configuration functions */
+int32_t WDT_Init(const stc_wdt_init_t *pstcWdtInit);
+void WDT_FeedDog(void);
+uint16_t WDT_GetCountValue(void);
+
+/* Flags management functions */
+en_flag_status_t WDT_GetStatus(uint32_t u32Flag);
+int32_t WDT_ClearStatus(uint32_t u32Flag);
+
+/**
+ * @}
+ */
+
+#endif /* LL_WDT_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32_LL_WDT_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll.c
new file mode 100644
index 0000000000..959880561f
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll.c
@@ -0,0 +1,170 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll.c
+ * @brief This file provides firmware functions to low-level drivers (LL).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_Global Global
+ * @{
+ */
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup LL_Global_Functions LL Global Functions
+ * @{
+ */
+void LL_PERIPH_WE(uint32_t u32Peripheral)
+{
+#if (LL_EFM_ENABLE == DDL_ON)
+ if ((u32Peripheral & LL_PERIPH_EFM) != 0UL) {
+ /* Unlock all EFM registers */
+ EFM_REG_Unlock();
+ }
+#endif
+#if (LL_FCG_ENABLE == DDL_ON)
+ if ((u32Peripheral & LL_PERIPH_FCG) != 0UL) {
+ /* Unlock FCG register */
+ PWC_FCG0_REG_Unlock();
+ }
+#endif
+#if (LL_GPIO_ENABLE == DDL_ON)
+ if ((u32Peripheral & LL_PERIPH_GPIO) != 0UL) {
+ /* Unlock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */
+ GPIO_REG_Unlock();
+ }
+#endif
+#if (LL_MPU_ENABLE == DDL_ON)
+ if ((u32Peripheral & LL_PERIPH_MPU) != 0UL) {
+ /* Unlock all MPU registers */
+ MPU_REG_Unlock();
+ }
+#endif
+#if (LL_PWC_ENABLE == DDL_ON)
+ if ((u32Peripheral & LL_PERIPH_LVD) != 0UL) {
+ /* Unlock LVD registers, @ref PWC_REG_Write_Unlock_Code for details */
+ PWC_REG_Unlock(PWC_UNLOCK_CODE2);
+ }
+#endif
+#if (LL_PWC_ENABLE == DDL_ON)
+ if ((u32Peripheral & LL_PERIPH_PWC_CLK_RMU) != 0UL) {
+ /* Unlock PWC, CLK, RMU registers, @ref PWC_REG_Write_Unlock_Code for details */
+ PWC_REG_Unlock(PWC_UNLOCK_CODE0 | PWC_UNLOCK_CODE1);
+ }
+#endif
+#if (LL_SRAM_ENABLE == DDL_ON)
+ if ((u32Peripheral & LL_PERIPH_SRAM) != 0UL) {
+ /* Unlock SRAM register: WTCR, CKCR */
+ SRAM_REG_Unlock();
+ }
+#endif
+}
+
+void LL_PERIPH_WP(uint32_t u32Peripheral)
+{
+#if (LL_EFM_ENABLE == DDL_ON)
+ if ((u32Peripheral & LL_PERIPH_EFM) != 0UL) {
+ /* Lock all EFM registers */
+ EFM_REG_Lock();
+ }
+#endif
+#if (LL_FCG_ENABLE == DDL_ON)
+ if ((u32Peripheral & LL_PERIPH_FCG) != 0UL) {
+ /* Lock FCG register */
+ PWC_FCG0_REG_Lock();
+ }
+#endif
+#if (LL_GPIO_ENABLE == DDL_ON)
+ if ((u32Peripheral & LL_PERIPH_GPIO) != 0UL) {
+ /* Unlock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */
+ GPIO_REG_Lock();
+ }
+#endif
+#if (LL_MPU_ENABLE == DDL_ON)
+ if ((u32Peripheral & LL_PERIPH_MPU) != 0UL) {
+ /* Lock all MPU registers */
+ MPU_REG_Lock();
+ }
+#endif
+#if (LL_PWC_ENABLE == DDL_ON)
+ if ((u32Peripheral & LL_PERIPH_LVD) != 0UL) {
+ /* Lock LVD registers, @ref PWC_REG_Write_Unlock_Code for details */
+ PWC_REG_Lock(PWC_UNLOCK_CODE2);
+ }
+#endif
+#if (LL_PWC_ENABLE == DDL_ON)
+ if ((u32Peripheral & LL_PERIPH_PWC_CLK_RMU) != 0UL) {
+ /* Lock PWC, CLK, RMU registers, @ref PWC_REG_Write_Unlock_Code for details */
+ PWC_REG_Lock(PWC_UNLOCK_CODE0 | PWC_UNLOCK_CODE1);
+ }
+#endif
+#if (LL_SRAM_ENABLE == DDL_ON)
+ if ((u32Peripheral & LL_PERIPH_SRAM) != 0UL) {
+ /* Lock SRAM register: WTCR, CKCR */
+ SRAM_REG_Lock();
+ }
+#endif
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_adc.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_adc.c
new file mode 100644
index 0000000000..c28e375348
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_adc.c
@@ -0,0 +1,1143 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_adc.c
+ * @brief This file provides firmware functions to manage the Analog-to-Digital
+ * Converter(ADC).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Modify typo
+ API fixed: ADC_DeInit()
+ 2023-12-15 CDT Add API ADC_MxChCmd(),ADC_ConvDataAverageMxChCmd
+ Add API ADC_GetResolution()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_adc.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_ADC ADC
+ * @brief Analog-to-Digital Converter Driver Library
+ * @{
+ */
+
+#if (LL_ADC_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup ADC_Local_Macros ADC Local Macros
+ * @{
+ */
+
+#define ADC_RMU_TIMEOUT (100U)
+
+/**
+ * @defgroup ADC_PGA_En ADC PGA Function Control
+ * @{
+ */
+#define ADC_PGA_DISABLE (0x0U)
+#define ADC_PGA_ENABLE (0xEU)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_AWD_DR_CHSR ADC AWD DR CHSR
+ * @{
+ */
+#define ADC_AWDx_DR(awd, reg_base) (*(__IO uint16_t *)((uint32_t)(reg_base) + ((uint32_t)(awd) * 8U)))
+#define ADC_AWDx_CHSR(awd, reg_base) (*(__IO uint8_t *)((uint32_t)(reg_base) + ((uint32_t)(awd) * 8U)))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_Channel_Max ADC Channel Max
+ * @{
+ */
+#define ADC1_CH_MAX (ADC_CH23)
+#define ADC2_CH_MAX (ADC_CH23)
+#define ADC3_CH_MAX (ADC_CH24)
+#define ADC_REMAP_CH_MAX (ADC_CH15)
+#define ADC_REMAP_PIN_MAX (ADC12_PIN_PC5)
+#define ADC_SSTR_NUM (16U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup ADC_Check_Parameters_Validity ADC check parameters validity
+ * @{
+ */
+#define IS_ADC_1BIT_MASK(x) (((x) != 0U) && (((x) & ((x) - 1U)) == 0U))
+#define IS_ADC_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask)))
+
+/* ADC unit check */
+#define IS_ADC_UNIT(x) \
+( ((x) == CM_ADC1) || \
+ ((x) == CM_ADC2) || \
+ ((x) == CM_ADC3))
+
+/* ADC sequence check */
+#define IS_ADC_SEQ(x) (((x) == ADC_SEQ_A) || ((x) == ADC_SEQ_B))
+
+/* ADC channel check */
+#define IS_ADC_CH(adc, ch) \
+( (((adc) == CM_ADC1) && ((ch) <= ADC1_CH_MAX)) || \
+ (((adc) == CM_ADC2) && ((ch) <= ADC2_CH_MAX)) || \
+ (((adc) == CM_ADC3) && ((ch) <= ADC3_CH_MAX)))
+
+/* ADC MX channel check */
+#define IS_ADC_MX_CH(adc, ch) \
+( (((adc) == CM_ADC1) && IS_ADC_BIT_MASK(ch, ADC1_MX_CH_ALL)) || \
+ (((adc) == CM_ADC2) && IS_ADC_BIT_MASK(ch, ADC2_MX_CH_ALL)) || \
+ (((adc) == CM_ADC3) && IS_ADC_BIT_MASK(ch, ADC3_MX_CH_ALL)))
+
+#define IS_ADC_SCAN_MD(x) \
+( ((x) == ADC_MD_SEQA_SINGLESHOT) || \
+ ((x) == ADC_MD_SEQA_CONT) || \
+ ((x) == ADC_MD_SEQA_SEQB_SINGLESHOT) || \
+ ((x) == ADC_MD_SEQA_CONT_SEQB_SINGLESHOT))
+
+#define IS_ADC_RESOLUTION(x) \
+( ((x) == ADC_RESOLUTION_8BIT) || \
+ ((x) == ADC_RESOLUTION_10BIT) || \
+ ((x) == ADC_RESOLUTION_12BIT))
+
+#define IS_ADC_HARDTRIG(x) \
+( ((x) == ADC_HARDTRIG_ADTRG_PIN) || \
+ ((x) == ADC_HARDTRIG_EVT0) || \
+ ((x) == ADC_HARDTRIG_EVT1) || \
+ ((x) == ADC_HARDTRIG_EVT0_EVT1))
+
+#define IS_ADC_DATAALIGN(x) \
+( ((x) == ADC_DATAALIGN_RIGHT) || \
+ ((x) == ADC_DATAALIGN_LEFT))
+
+#define IS_ADC_SEQA_RESUME_MD(x) \
+( ((x) == ADC_SEQA_RESUME_SCAN_CONT) || \
+ ((x) == ADC_SEQA_RESUME_SCAN_RESTART))
+
+#define IS_ADC_SAMPLE_TIME(x) ((x) >= 5U)
+
+#define IS_ADC_INT(x) IS_ADC_BIT_MASK(x, ADC_INT_ALL)
+#define IS_ADC_FLAG(x) IS_ADC_BIT_MASK(x, ADC_FLAG_ALL)
+
+/* Scan-average. */
+#define IS_ADC_AVG_CNT(x) (((x) | ADC_AVG_CNT256) == ADC_AVG_CNT256)
+
+/* Channel remapping. */
+#define IS_ADC_REMAP_PIN(adc, pin) (IS_ADC_UNIT(adc) && ((pin) <= ADC_REMAP_PIN_MAX))
+#define IS_ADC_REMAP_CH(adc, ch) (IS_ADC_UNIT(adc) && ((ch) <= ADC_REMAP_CH_MAX))
+
+/* Sync mode. */
+#define IS_ADC_SYNC_MD(x) \
+( ((x) == ADC_SYNC_SINGLE_DELAY_TRIG) || \
+ ((x) == ADC_SYNC_SINGLE_PARALLEL_TRIG) || \
+ ((x) == ADC_SYNC_CYCLIC_DELAY_TRIG) || \
+ ((x) == ADC_SYNC_CYCLIC_PARALLEL_TRIG))
+
+#define IS_ADC_SYNC(x) \
+( ((x) == ADC_SYNC_ADC1_ADC2) || \
+ ((x) == ADC_SYNC_ADC1_ADC2_ADC3))
+
+/* Analog watchdog. */
+#define IS_ADC_AWD_MD(x) \
+( ((x) == ADC_AWD_MD_CMP_OUT) || \
+ ((x) == ADC_AWD_MD_CMP_IN))
+
+#define IS_ADC_AWD(x) ((x) <= ADC_AWD1)
+
+/* AWD flag check */
+#define IS_ADC_AWD_FLAG(x) IS_ADC_BIT_MASK(x, ADC_AWD_FLAG_ALL)
+
+/* Two AWD units */
+#define IS_ADC_AWD_COMB_MD(x) \
+( ((x) == ADC_AWD_COMB_INVD) || \
+ ((x) == ADC_AWD_COMB_OR) || \
+ ((x) == ADC_AWD_COMB_AND) || \
+ ((x) == ADC_AWD_COMB_XOR))
+
+#define IS_ADC_AWD_INT(x) IS_ADC_BIT_MASK(x, ADC_AWD_INT_ALL)
+
+/* PGA */
+#define IS_ADC_PGA_GAIN(x) ((x) <= ADC_PGA_GAIN_32)
+
+#define IS_ADC_PGA_VSS(x) (((x) == ADC_PGA_VSS_PGAVSS) || ((x) == ADC_PGA_VSS_AVSS))
+
+/* PGA unit */
+#define IS_ADC_PGA(adc, pga) \
+( (((adc) == CM_ADC1) && ((pga) == ADC_PGA1)) || \
+ (((adc) == CM_ADC2) && ((pga) == ADC_PGA2)))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup ADC_Global_Functions ADC Global Functions
+ * @{
+ */
+
+/**
+ * @brief Initializes the specified ADC peripheral according to the specified parameters
+ * in the structure pstcAdcInit.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] pstcAdcInit Pointer to a @ref stc_adc_init_t structure that contains the
+ * configuration information for the specified ADC.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_INVD_PARAM: pstcAdcInit == NULL.
+ */
+int32_t ADC_Init(CM_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcAdcInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ DDL_ASSERT(IS_ADC_UNIT(ADCx));
+
+ if (pstcAdcInit != NULL) {
+ DDL_ASSERT(IS_ADC_SCAN_MD(pstcAdcInit->u16ScanMode));
+ DDL_ASSERT(IS_ADC_RESOLUTION(pstcAdcInit->u16Resolution));
+ DDL_ASSERT(IS_ADC_DATAALIGN(pstcAdcInit->u16DataAlign));
+ /* Configures scan mode, resolution, data align. */
+ WRITE_REG16(ADCx->CR0, pstcAdcInit->u16ScanMode | pstcAdcInit->u16Resolution | pstcAdcInit->u16DataAlign);
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Deinitialize the specified ADC peripheral registers to their default reset values.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @retval int32_t:
+ * - LL_OK: De-Initialize success.
+ * - LL_ERR_TIMEOUT: Timeout.
+ */
+int32_t ADC_DeInit(CM_ADC_TypeDef *ADCx)
+{
+ int32_t i32Ret = LL_OK;
+ uint32_t u32UnitShift;
+ uint32_t u32UnitBase;
+ __IO uint8_t u8TimeOut = 0U;
+
+ DDL_ASSERT(IS_ADC_UNIT(ADCx));
+ /* Check FRST register protect */
+ DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1);
+
+ /* Reset ADC */
+ u32UnitBase = (uint32_t)ADCx;
+ u32UnitShift = (u32UnitBase - CM_ADC1_BASE) / (CM_ADC2_BASE - CM_ADC1_BASE);
+ CLR_REG32_BIT(CM_RMU->FRST3, RMU_FRST3_ADC1 << u32UnitShift);
+ /* Ensure reset procedure is completed */
+ while (0UL == READ_REG32_BIT(CM_RMU->FRST3, RMU_FRST3_ADC1 << u32UnitShift)) {
+ u8TimeOut++;
+ if (u8TimeOut > ADC_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Set each @ref stc_adc_init_t field to default value.
+ * @param [in] pstcAdcInit Pointer to a @ref stc_adc_init_t structure
+ * whose fields will be set to default values.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_INVD_PARAM: pstcAdcInit == NULL.
+ */
+int32_t ADC_StructInit(stc_adc_init_t *pstcAdcInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (pstcAdcInit != NULL) {
+ pstcAdcInit->u16ScanMode = ADC_MD_SEQA_SINGLESHOT;
+ pstcAdcInit->u16Resolution = ADC_RESOLUTION_12BIT;
+ pstcAdcInit->u16DataAlign = ADC_DATAALIGN_RIGHT;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Enable or disable the specified ADC channel.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u8Seq The sequence whose channel specified by 'u8Ch' will be enabled or disabled.
+ * This parameter can be a value of @ref ADC_Sequence
+ * @arg ADC_SEQ_A: ADC sequence A.
+ * @arg ADC_SEQ_B: ADC sequence B.
+ * @param [in] u8Ch The ADC channel.
+ * This parameter can be values of @ref ADC_Channel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @note Sequence A and Sequence B CAN NOT include the same channel!
+ * @note Sequence A can always started by software(by calling @ref ADC_Start()),
+ * regardless of whether the hardware trigger source is valid or not.
+ * @note Sequence B must be specified a valid hard trigger by calling functions @ref ADC_TriggerConfig()
+ * and @ref ADC_TriggerCmd().
+ */
+void ADC_ChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint8_t u8Ch, en_functional_state_t enNewState)
+{
+ uint32_t u32CHSELAddr;
+
+ DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch));
+ DDL_ASSERT(IS_ADC_SEQ(u8Seq));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u32CHSELAddr = (uint32_t)&ADCx->CHSELRA + (u8Seq * 4UL);
+ if (enNewState == ENABLE) {
+ /* Enable the specified channel. */
+ SET_REG32_BIT(RW_MEM32(u32CHSELAddr), 1UL << u8Ch);
+ } else {
+ /* Disable the specified channel. */
+ CLR_REG32_BIT(RW_MEM32(u32CHSELAddr), 1UL << u8Ch);
+ }
+}
+
+/**
+ * @brief Enable or disable the specified ADC channel.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u8Seq The sequence whose channel specified by 'u32MxCh' will be enabled or disabled.
+ * This parameter can be a value of @ref ADC_Sequence
+ * @arg ADC_SEQ_A: ADC sequence A.
+ * @arg ADC_SEQ_B: ADC sequence B.
+ * @param [in] u32MxCh The ADC channel.
+ * This parameter can be any component of @ref ADC_Mx_Channel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @note Sequence A and Sequence B CAN NOT include the same channel!
+ * @note Sequence A can always started by software(by calling @ref ADC_Start()),
+ * regardless of whether the hardware trigger source is valid or not.
+ * @note Sequence B must be specified a valid hard trigger by calling functions @ref ADC_TriggerConfig()
+ * and @ref ADC_TriggerCmd().
+ */
+void ADC_MxChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint32_t u32MxCh, en_functional_state_t enNewState)
+{
+ uint32_t u32CHSELAddr;
+
+ DDL_ASSERT(IS_ADC_MX_CH(ADCx, u32MxCh));
+ DDL_ASSERT(IS_ADC_SEQ(u8Seq));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u32CHSELAddr = (uint32_t)&ADCx->CHSELRA + (u8Seq * 4UL);
+ if (enNewState == ENABLE) {
+ /* Enable the specified channel. */
+ SET_REG32_BIT(RW_MEM32(u32CHSELAddr), u32MxCh);
+ } else {
+ /* Disable the specified channel. */
+ CLR_REG32_BIT(RW_MEM32(u32CHSELAddr), u32MxCh);
+ }
+}
+
+/**
+ * @brief Set sampling time for the specified channel.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u8Ch The channel to be set sampling time.
+ * This parameter can be values of @ref ADC_Channel
+ * @param [in] u8SampleTime Sampling time for the channel that specified by 'u8Ch'.
+ * @retval None
+ */
+void ADC_SetSampleTime(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8SampleTime)
+{
+ uint32_t u32Addr;
+
+ DDL_ASSERT(IS_ADC_SAMPLE_TIME(u8SampleTime));
+
+ DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch));
+ if (u8Ch < ADC_SSTR_NUM) {
+ u32Addr = (uint32_t)&ADCx->SSTR0 + u8Ch;
+ WRITE_REG8(RW_MEM8(u32Addr), u8SampleTime);
+ } else {
+ WRITE_REG8(ADCx->SSTRL, u8SampleTime);
+ }
+}
+
+/**
+ * @brief Set scan-average count.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u16AverageCount Scan-average count.
+ * This parameter can be a value of @ref ADC_Average_Count
+ * @arg ADC_AVG_CNT2: 2 consecutive average conversions.
+ * @arg ADC_AVG_CNT4: 4 consecutive average conversions.
+ * @arg ADC_AVG_CNT8: 8 consecutive average conversions.
+ * @arg ADC_AVG_CNT16: 16 consecutive average conversions.
+ * @arg ADC_AVG_CNT32: 32 consecutive average conversions.
+ * @arg ADC_AVG_CNT64: 64 consecutive average conversions.
+ * @arg ADC_AVG_CNT128: 128 consecutive average conversions.
+ * @arg ADC_AVG_CNT256: 256 consecutive average conversions.
+ * @retval None
+ */
+void ADC_ConvDataAverageConfig(CM_ADC_TypeDef *ADCx, uint16_t u16AverageCount)
+{
+ DDL_ASSERT(IS_ADC_UNIT(ADCx));
+ DDL_ASSERT(IS_ADC_AVG_CNT(u16AverageCount));
+ MODIFY_REG16(ADCx->CR0, ADC_CR0_AVCNT, u16AverageCount);
+}
+
+/**
+ * @brief Enable or disable conversion data average calculation channel.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u8Ch The ADC channel.
+ * This parameter can be values of @ref ADC_Channel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void ADC_ConvDataAverageChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (enNewState == ENABLE) {
+ SET_REG32_BIT(ADCx->AVCHSELR, 1UL << u8Ch);
+ } else {
+ CLR_REG32_BIT(ADCx->AVCHSELR, 1UL << u8Ch);
+ }
+}
+
+/**
+ * @brief Enable or disable conversion data average calculation channel.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u32MxCh The ADC channel.
+ * This parameter can be any component of @ref ADC_Mx_Channel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void ADC_ConvDataAverageMxChCmd(CM_ADC_TypeDef *ADCx, uint32_t u32MxCh, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_ADC_MX_CH(ADCx, u32MxCh));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (enNewState == ENABLE) {
+ SET_REG32_BIT(ADCx->AVCHSELR, u32MxCh);
+ } else {
+ CLR_REG32_BIT(ADCx->AVCHSELR, u32MxCh);
+ }
+}
+
+/**
+ * @brief Specifies the hard trigger for the specified ADC sequence.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADCx or CM_ADC
+ * @param [in] u8Seq The sequence to be configured.
+ * This parameter can be a value of @ref ADC_Sequence
+ * @arg ADC_SEQ_A: Sequence A.
+ * @arg ADC_SEQ_B: Sequence B.
+ * @param [in] u16TriggerSel Hard trigger selection. This parameter can be a value of @ref ADC_Hard_Trigger_Sel
+ * @arg ADC_HARDTRIG_ADTRG_PIN: Selects the following edge of pin ADTRG as the trigger of ADC sequence.
+ * @arg ADC_HARDTRIG_EVT0: Selects an internal event as the trigger of ADC sequence.
+ This event is specified by register ADCx_TRGSEL0(x=(null), 1, 2, 3).
+ * @arg ADC_HARDTRIG_EVT1: Selects an internal event as the trigger of ADC sequence.
+ This event is specified by register ADCx_TRGSEL1(x=(null), 1, 2, 3).
+ * @arg ADC_HARDTRIG_EVT0_EVT1: Selects two internal events as the trigger of ADC sequence.
+ The two events are specified by register ADCx_TRGSEL0 and register ADCx_TRGSEL1.
+ * @retval None
+ * @note ADC must be stopped while calling this function.
+ * @note The trigger source CANNOT be an event that generated by the sequence itself.
+ */
+void ADC_TriggerConfig(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint16_t u16TriggerSel)
+{
+ DDL_ASSERT(IS_ADC_UNIT(ADCx));
+ DDL_ASSERT(IS_ADC_SEQ(u8Seq));
+ DDL_ASSERT(IS_ADC_HARDTRIG(u16TriggerSel));
+
+ u8Seq *= ADC_TRGSR_TRGSELB_POS;
+ MODIFY_REG16(ADCx->TRGSR, (uint32_t)ADC_TRGSR_TRGSELA << u8Seq, (uint32_t)u16TriggerSel << u8Seq);
+}
+
+/**
+ * @brief Enable or disable the hard trigger of the specified ADC sequence.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADCx or CM_ADC
+ * @param [in] u8Seq The sequence to be configured.
+ * This parameter can be a value of @ref ADC_Sequence
+ * @arg ADC_SEQ_A: Sequence A.
+ * @arg ADC_SEQ_B: Sequence B.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ * @note ADC must be stopped while calling this function.
+ */
+void ADC_TriggerCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_ADC_UNIT(ADCx));
+ DDL_ASSERT(IS_ADC_SEQ(u8Seq));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (enNewState == ENABLE) {
+ SET_REG16_BIT(ADCx->TRGSR, (uint32_t)ADC_TRGSR_TRGENA << (u8Seq * ADC_TRGSR_TRGSELB_POS));
+ } else {
+ CLR_REG16_BIT(ADCx->TRGSR, (uint32_t)ADC_TRGSR_TRGENA << (u8Seq * ADC_TRGSR_TRGSELB_POS));
+ }
+}
+
+/**
+ * @brief Enable or disable ADC interrupts.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u8IntType ADC interrupt.
+ * This parameter can be values of @ref ADC_Int_Type
+ * @arg ADC_INT_EOCA: Interrupt of the end of conversion of sequence A.
+ * @arg ADC_INT_EOCB: Interrupt of the end of conversion of sequence B.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void ADC_IntCmd(CM_ADC_TypeDef *ADCx, uint8_t u8IntType, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_ADC_UNIT(ADCx));
+ DDL_ASSERT(IS_ADC_INT(u8IntType));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (enNewState == ENABLE) {
+ SET_REG8_BIT(ADCx->ICR, u8IntType);
+ } else {
+ CLR_REG8_BIT(ADCx->ICR, u8IntType);
+ }
+}
+
+/**
+ * @brief Start sequence A conversion.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @retval int32_t
+ * - LL_OK: Start success.
+ * - LL_ERR_BUSY: ADC is busy.
+ */
+int32_t ADC_Start(CM_ADC_TypeDef *ADCx)
+{
+ int32_t i32Ret = LL_OK;
+
+ DDL_ASSERT(IS_ADC_UNIT(ADCx));
+
+ if (1U == READ_REG8(ADCx->STR)) {
+ i32Ret = LL_ERR_BUSY;
+ } else {
+ WRITE_REG8(ADCx->STR, ADC_STR_STRT);
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Stop ADC conversion, both sequence A and sequence B.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @retval None
+ */
+void ADC_Stop(CM_ADC_TypeDef *ADCx)
+{
+ DDL_ASSERT(IS_ADC_UNIT(ADCx));
+ WRITE_REG8(ADCx->STR, 0U);
+}
+
+/**
+ * @brief Get the ADC value of the specified channel.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u8Ch The ADC channel.
+ * This parameter can be values of @ref ADC_Channel
+ * @retval An uint16_t type value of ADC value.
+ */
+uint16_t ADC_GetValue(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch)
+{
+ DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch));
+
+ return RW_MEM16((uint32_t)&ADCx->DR0 + u8Ch * 2UL);
+}
+
+/**
+ * @brief Get the ADC resolution.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @retval An uint16_t type value of ADC resolution. @ref ADC_Resolution
+ */
+uint16_t ADC_GetResolution(const CM_ADC_TypeDef *ADCx)
+{
+ DDL_ASSERT(IS_ADC_UNIT(ADCx));
+
+ return READ_REG16_BIT(ADCx->CR0, ADC_CR0_ACCSEL);
+}
+
+/**
+ * @brief Get the status of the specified ADC flag.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u8Flag ADC status flag.
+ * This parameter can be a value of @ref ADC_Status_Flag
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t ADC_GetStatus(const CM_ADC_TypeDef *ADCx, uint8_t u8Flag)
+{
+ en_flag_status_t enStatus = RESET;
+
+ DDL_ASSERT(IS_ADC_UNIT(ADCx));
+ DDL_ASSERT(IS_ADC_FLAG(u8Flag));
+
+ if (READ_REG8_BIT(ADCx->ISR, u8Flag) != 0U) {
+ enStatus = SET;
+ }
+
+ return enStatus;
+}
+
+/**
+ * @brief Clear the status of the specified ADC flag.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u8Flag ADC status flag.
+ * This parameter can be valueS of @ref ADC_Status_Flag
+ * @retval None
+ */
+void ADC_ClearStatus(CM_ADC_TypeDef *ADCx, uint8_t u8Flag)
+{
+ DDL_ASSERT(IS_ADC_UNIT(ADCx));
+ DDL_ASSERT(IS_ADC_FLAG(u8Flag));
+
+ WRITE_REG8(ADCx->ISCLRR, u8Flag);
+}
+
+/**
+ * @brief Remap the correspondence between ADC channel and analog input pins.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u8Ch This parameter can be values of @ref ADC_Channel
+ * @param [in] u8AdcPin This parameter can be a value of @ref ADC_Remap_Pin
+ * @retval None
+ */
+void ADC_ChRemap(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8AdcPin)
+{
+ uint8_t u8FieldOfs;
+ uint8_t u8RegIdx;
+ __IO uint16_t *regCHMUXR;
+
+ DDL_ASSERT(IS_ADC_REMAP_CH(ADCx, u8Ch));
+ DDL_ASSERT(IS_ADC_REMAP_PIN(ADCx, u8AdcPin));
+
+ regCHMUXR = (__IO uint16_t *)((uint32_t)&ADCx->CHMUXR0);
+ u8RegIdx = u8Ch / 4U;
+ u8FieldOfs = (u8Ch % 4U) * 4U;
+ MODIFY_REG16(regCHMUXR[u8RegIdx], ((uint32_t)ADC_CHMUXR0_CH00MUX << u8FieldOfs), ((uint32_t)u8AdcPin << u8FieldOfs));
+}
+
+/**
+ * @brief Get the ADC pin corresponding to the specified ADC channel.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u8Ch ADC channel.
+ * This parameter can be one of the following values of @ref ADC_Channel
+ * @retval An uint8_t type value of ADC pin. @ref ADC_Remap_Pin
+ */
+uint8_t ADC_GetChPin(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch)
+{
+ uint8_t u8RetPin;
+ uint8_t u8FieldOfs;
+ uint8_t u8RegIdx;
+ __IO uint16_t *regCHMUXR;
+
+ DDL_ASSERT(IS_ADC_REMAP_CH(ADCx, u8Ch));
+
+ regCHMUXR = (__IO uint16_t *)((uint32_t)&ADCx->CHMUXR0);
+ u8RegIdx = u8Ch / 4U;
+ u8FieldOfs = (u8Ch % 4U) * 4U;
+ u8RetPin = ((uint8_t)(regCHMUXR[u8RegIdx] >> u8FieldOfs)) & 0xFU;
+
+ return u8RetPin;
+}
+
+/**
+ * @brief Reset channel-pin mapping.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @retval None
+ */
+void ADC_ResetChMapping(CM_ADC_TypeDef *ADCx)
+{
+ DDL_ASSERT(IS_ADC_UNIT(ADCx));
+
+ WRITE_REG16(ADCx->CHMUXR0, 0x3210U);
+ WRITE_REG16(ADCx->CHMUXR1, 0x7654U);
+ WRITE_REG16(ADCx->CHMUXR2, 0xBA98U);
+ WRITE_REG16(ADCx->CHMUXR3, 0xFEDCU);
+}
+
+/**
+ * @brief Configures synchronous mode.
+ * @param [in] u16SyncUnit Specify the ADC units which work synchronously.
+ * This parameter can be a value of @ref ADC_Sync_Unit
+ * @param [in] u16SyncMode Synchronous mode.
+ * This parameter can be a value of @ref ADC_Sync_Mode
+ * @arg ADC_SYNC_SINGLE_DELAY_TRIG: Single shot delayed trigger mode.
+ * When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has).
+ * All ADCs scan once.
+ * @arg ADC_SYNC_SINGLE_PARALLEL_TRIG: Single shot parallel trigger mode.
+ * When the trigger condition occurs, all ADCs start at the same time.
+ * All ADCs scan once.
+ * @arg ADC_SYNC_CYCLIC_DELAY_TRIG: Cyclic delayed trigger mode.
+ * When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has).
+ * All ADCs scan cyclicly(keep scanning till you stop them).
+ * @arg ADC_SYNC_CYCLIC_PARALLEL_TRIG: Single shot parallel trigger mode.
+ * When the trigger condition occurs, all ADCs start at the same time.
+ * All ADCs scan cyclicly(keep scanning till you stop them).
+ * @param [in] u8TriggerDelay Trigger delay time(ADCLK cycle), range is [1, 255].
+ * @retval None
+ */
+void ADC_SyncModeConfig(uint16_t u16SyncUnit, uint16_t u16SyncMode, uint8_t u8TriggerDelay)
+{
+ DDL_ASSERT(IS_ADC_SYNC(u16SyncUnit));
+ DDL_ASSERT(IS_ADC_SYNC_MD(u16SyncMode));
+
+ u16SyncMode |= ((uint16_t)((uint32_t)u8TriggerDelay << ADC_SYNCCR_SYNCDLY_POS)) | u16SyncUnit;
+ MODIFY_REG16(CM_ADC1->SYNCCR, ADC_SYNCCR_SYNCMD | ADC_SYNCCR_SYNCDLY, u16SyncMode);
+}
+
+/**
+ * @brief Enable or disable synchronous mode.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void ADC_SyncModeCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ WRITE_REG32(bCM_ADC1->SYNCCR_b.SYNCEN, enNewState);
+}
+
+/**
+ * @brief Configures analog watchdog.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u8AwdUnit AWD unit that is going to be configured.
+ * This parameter can be a value of @ref ADC_AWD_Unit
+ * @param [in] u8Ch The channel that to be used as an analog watchdog channel.
+ * This parameter can be a value of @ref ADC_Channel
+ * @param [in] pstcAwd Pointer to a @ref stc_adc_awd_config_t structure value that
+ * contains the configuration information of the AWD.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_INVD_PARAM: pstcAwd == NULL.
+ */
+int32_t ADC_AWD_Config(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch, const stc_adc_awd_config_t *pstcAwd)
+{
+ uint32_t u32AwdDr0;
+ uint32_t u32AwdDr1;
+ uint32_t u32AwdChsr;
+ uint32_t u32Addr;
+ uint8_t u8Pos;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch));
+ DDL_ASSERT(IS_ADC_AWD(u8AwdUnit));
+
+ if (pstcAwd != NULL) {
+ DDL_ASSERT(IS_ADC_AWD_MD(pstcAwd->u16WatchdogMode));
+
+ u8Pos = (u8AwdUnit * 4U) + ADC_AWDCR_AWD0MD_POS;
+ u32Addr = (uint32_t)&ADCx->AWDCR;
+ u32AwdDr0 = (uint32_t)&ADCx->AWD0DR0;
+ u32AwdDr1 = (uint32_t)&ADCx->AWD0DR1;
+ u32AwdChsr = (uint32_t)&ADCx->AWD0CHSR;
+
+ WRITE_REG32(PERIPH_BIT_BAND(u32Addr, u8Pos), pstcAwd->u16WatchdogMode);
+ WRITE_REG16(ADC_AWDx_DR(u8AwdUnit, u32AwdDr0), pstcAwd->u16LowThreshold);
+ WRITE_REG16(ADC_AWDx_DR(u8AwdUnit, u32AwdDr1), pstcAwd->u16HighThreshold);
+ WRITE_REG8(ADC_AWDx_CHSR(u8AwdUnit, u32AwdChsr), u8Ch);
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Specifies combination mode of analog watchdog.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u16CombMode Combination mode of analog watchdog.
+ * This parameter can be a value of @ref ADC_AWD_Comb_Mode
+ * @arg ADC_AWD_COMB_INVD Combination mode is invalid.
+ * @arg ADC_AWD_COMB_OR: The status of AWD0 is set or the status of AWD1 is set, the status of combination mode is set.
+ * @arg ADC_AWD_COMB_AND: The status of AWD0 is set and the status of AWD1 is set, the status of combination mode is set.
+ * @arg ADC_AWD_COMB_XOR: Only one of the status of AWD0 and AWD1 is set, the status of combination mode is set.
+ * @retval None
+ */
+void ADC_AWD_SetCombMode(CM_ADC_TypeDef *ADCx, uint16_t u16CombMode)
+{
+ DDL_ASSERT(IS_ADC_UNIT(ADCx));
+ DDL_ASSERT(IS_ADC_AWD_COMB_MD(u16CombMode));
+ MODIFY_REG16(ADCx->AWDCR, ADC_AWDCR_AWDCM, u16CombMode);
+}
+
+/**
+ * @brief Specifies the compare mode of analog watchdog.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u8AwdUnit AWD unit that is going to be configured.
+ * This parameter can be a value of @ref ADC_AWD_Unit
+ * @param [in] u16WatchdogMode Analog watchdog compare mode.
+ * This parameter can be a value of @ref ADC_AWD_Mode
+ * @arg ADC_AWD_MD_CMP_OUT: ADCValue > HighThreshold or ADCValue < LowThreshold
+ * @arg ADC_AWD_MD_CMP_IN: LowThreshold < ADCValue < HighThreshold
+ * @retval None
+ */
+void ADC_AWD_SetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16WatchdogMode)
+{
+ uint8_t u8Pos;
+ uint32_t u32Addr;
+
+ DDL_ASSERT(IS_ADC_UNIT(ADCx));
+ DDL_ASSERT(IS_ADC_AWD(u8AwdUnit));
+ DDL_ASSERT(IS_ADC_AWD_MD(u16WatchdogMode));
+
+ u8Pos = (u8AwdUnit * 4U) + ADC_AWDCR_AWD0MD_POS;
+ u32Addr = (uint32_t)&ADCx->AWDCR;
+ WRITE_REG32(PERIPH_BIT_BAND(u32Addr, u8Pos), u16WatchdogMode);
+}
+
+/**
+ * @brief Get the compare mode of analog watchdog.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u8AwdUnit AWD unit that is going to be configured.
+ * This parameter can be a value of @ref ADC_AWD_Unit
+ * @retval Analog watchdog compare mode. A value of @ref ADC_AWD_Mode
+ * - ADC_AWD_MD_CMP_OUT: ADCValue > HighThreshold or ADCValue < LowThreshold
+ * - ADC_AWD_MD_CMP_IN: LowThreshold < ADCValue < HighThreshold
+ */
+uint16_t ADC_AWD_GetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit)
+{
+ uint16_t u16RetMode;
+
+ uint8_t u8Pos;
+ uint32_t u32Addr;
+
+ DDL_ASSERT(IS_ADC_UNIT(ADCx));
+ DDL_ASSERT(IS_ADC_AWD(u8AwdUnit));
+
+ u8Pos = (u8AwdUnit * 4U) + ADC_AWDCR_AWD0MD_POS;
+ u32Addr = (uint32_t)&ADCx->AWDCR;
+ u16RetMode = (uint16_t)PERIPH_BIT_BAND(u32Addr, u8Pos);
+
+ return u16RetMode;
+}
+
+/**
+ * @brief Specifies the low threshold and high threshold of analog watchdog.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u8AwdUnit AWD unit that is going to be configured.
+ * This parameter can be a value of @ref ADC_AWD_Unit
+ * @param [in] u16LowThreshold Low threshold of analog watchdog.
+ * @param [in] u16HighThreshold High threshold of analog watchdog.
+ * @retval None
+ */
+void ADC_AWD_SetThreshold(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16LowThreshold, uint16_t u16HighThreshold)
+{
+ uint32_t u32AwdDr0;
+ uint32_t u32AwdDr1;
+
+ DDL_ASSERT(IS_ADC_UNIT(ADCx));
+ DDL_ASSERT(IS_ADC_AWD(u8AwdUnit));
+
+ u32AwdDr0 = (uint32_t)&ADCx->AWD0DR0;
+ u32AwdDr1 = (uint32_t)&ADCx->AWD0DR1;
+ WRITE_REG16(ADC_AWDx_DR(u8AwdUnit, u32AwdDr0), u16LowThreshold);
+ WRITE_REG16(ADC_AWDx_DR(u8AwdUnit, u32AwdDr1), u16HighThreshold);
+}
+
+/**
+ * @brief Select the specified ADC channel as an analog watchdog channel.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u8AwdUnit AWD unit that is going to be configured.
+ * This parameter can be a value of @ref ADC_AWD_Unit
+ * @param [in] u8Ch The channel that to be used as an analog watchdog channel.
+ * This parameter can be a value of @ref ADC_Channel
+ * @retval None
+ */
+void ADC_AWD_SelectCh(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch)
+{
+ uint32_t u32AwdChsr;
+ DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch));
+ DDL_ASSERT(IS_ADC_AWD(u8AwdUnit));
+
+ u32AwdChsr = (uint32_t)&ADCx->AWD0CHSR;
+ WRITE_REG8(ADC_AWDx_CHSR(u8AwdUnit, u32AwdChsr), u8Ch);
+}
+
+/**
+ * @brief Enable or disable the specified analog watchdog.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u8AwdUnit AWD unit that is going to be enabled or disabled.
+ * This parameter can be a value of @ref ADC_AWD_Unit
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void ADC_AWD_Cmd(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, en_functional_state_t enNewState)
+{
+ uint32_t u32Addr;
+
+ DDL_ASSERT(IS_ADC_UNIT(ADCx));
+ DDL_ASSERT(IS_ADC_AWD(u8AwdUnit));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u32Addr = (uint32_t)&ADCx->AWDCR;
+ /* Enable bit position: u8AwdUnit * 4 */
+ WRITE_REG32(PERIPH_BIT_BAND(u32Addr, (u8AwdUnit * 4UL)), enNewState);
+}
+
+/**
+ * @brief Enable or disable the specified analog watchdog interrupts.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u16IntType Interrupt of AWD.
+ * This parameter can be a value of @ref ADC_AWD_Int_Type
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void ADC_AWD_IntCmd(CM_ADC_TypeDef *ADCx, uint16_t u16IntType, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_ADC_UNIT(ADCx));
+ DDL_ASSERT(IS_ADC_AWD_INT(u16IntType));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (enNewState == ENABLE) {
+ SET_REG16_BIT(ADCx->AWDCR, u16IntType);
+ } else {
+ CLR_REG16_BIT(ADCx->AWDCR, u16IntType);
+ }
+}
+
+/**
+ * @brief Get the status of the specified analog watchdog flag.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u32Flag AWD status flag.
+ * This parameter can be values of @ref ADC_AWD_Status_Flag
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t ADC_AWD_GetStatus(const CM_ADC_TypeDef *ADCx, uint32_t u32Flag)
+{
+ en_flag_status_t enStatus = RESET;
+
+ DDL_ASSERT(IS_ADC_UNIT(ADCx));
+ DDL_ASSERT(IS_ADC_AWD_FLAG(u32Flag));
+ if (READ_REG8_BIT(ADCx->AWDSR, u32Flag) != 0U) {
+ enStatus = SET;
+ }
+
+ return enStatus;
+}
+
+/**
+ * @brief Clear the status of the specified analog watchdog flag.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u32Flag AWD status flag.
+ * This parameter can be values of @ref ADC_AWD_Status_Flag
+ * @retval None
+ */
+void ADC_AWD_ClearStatus(CM_ADC_TypeDef *ADCx, uint32_t u32Flag)
+{
+ DDL_ASSERT(IS_ADC_UNIT(ADCx));
+ DDL_ASSERT(IS_ADC_AWD_FLAG(u32Flag));
+ WRITE_REG8(ADCx->AWDSCLRR, u32Flag);
+}
+
+/**
+ * @brief Configures the specified programmable gain amplifier.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u8PgaUnit The PGA unit.
+ * This parameter can be a value of @ref ADC_PGA_Unit
+ * @param [in] u8Gain Gain of the specified PGA.
+ * This parameter can be a value of @ref ADC_PGA_Gain
+ * @arg ADC_PGA_GAIN_2: PGA gain factor is 2.
+ * @arg ADC_PGA_GAIN_2P133: PGA gain factor is 2.133.
+ * @arg ADC_PGA_GAIN_2P286: PGA gain factor is 2.286.
+ * @arg ADC_PGA_GAIN_2P667: PGA gain factor is 2.667.
+ * @arg ADC_PGA_GAIN_2P909: PGA gain factor is 2.909.
+ * @arg ADC_PGA_GAIN_3P2: PGA gain factor is 3.2.
+ * @arg ADC_PGA_GAIN_3P556: PGA gain factor is 2.556.
+ * @arg ADC_PGA_GAIN_4: PGA gain factor is 4.
+ * @arg ADC_PGA_GAIN_4P571: PGA gain factor is 4.571.
+ * @arg ADC_PGA_GAIN_5P333: PGA gain factor is 5.333.
+ * @arg ADC_PGA_GAIN_6P4: PGA gain factor is 6.4.
+ * @arg ADC_PGA_GAIN_8: PGA gain factor is 8.
+ * @arg ADC_PGA_GAIN_10P667: PGA gain factor is 10.667.
+ * @arg ADC_PGA_GAIN_16: PGA gain factor is 16.
+ * @arg ADC_PGA_GAIN_32: PGA gain factor is 32.
+ * @param [in] u8PgaVss VSS for the specified PGA.
+ * This parameter can be a value of @ref ADC_PGA_VSS
+ * @arg ADC_PGA_VSS_PGAVSS: Use pin PGAx_VSS as the reference GND of PGAx
+ * @arg ADC_PGA_VSS_AVSS: Use AVSS as the reference GND of PGAx.
+ * @retval None
+ */
+void ADC_PGA_Config(CM_ADC_TypeDef *ADCx, uint8_t u8PgaUnit, uint8_t u8Gain, uint8_t u8PgaVss)
+{
+ DDL_ASSERT(IS_ADC_PGA(ADCx, u8PgaUnit));
+ DDL_ASSERT(IS_ADC_PGA_GAIN(u8Gain));
+ DDL_ASSERT(IS_ADC_PGA_VSS(u8PgaVss));
+
+ (void)(u8PgaUnit);
+ MODIFY_REG8(ADCx->PGACR, ADC_PGACR_PGAGAIN, u8Gain << ADC_PGACR_PGAGAIN_POS);
+ WRITE_REG8(ADCx->PGAVSSENR, u8PgaVss);
+}
+
+/**
+ * @brief Enable the specified programmable gain amplifier.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u8PgaUnit The PGA unit.
+ * This parameter can be a value of @ref ADC_PGA_Unit
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void ADC_PGA_Cmd(CM_ADC_TypeDef *ADCx, uint8_t u8PgaUnit, en_functional_state_t enNewState)
+{
+ const uint8_t au8Cmd[] = {ADC_PGA_DISABLE, ADC_PGA_ENABLE};
+
+ DDL_ASSERT(IS_ADC_PGA(ADCx, u8PgaUnit));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ (void)(u8PgaUnit);
+ MODIFY_REG8(ADCx->PGACR, ADC_PGACR_PGACTL, au8Cmd[(uint8_t)enNewState]);
+}
+
+/**
+ * @brief Enable or disable automatically clear data register.
+ * The automatic clearing function is mainly used to detect whether the data register is updated.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void ADC_DataRegAutoClearCmd(CM_ADC_TypeDef *ADCx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_ADC_UNIT(ADCx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (enNewState == ENABLE) {
+ SET_REG16_BIT(ADCx->CR0, ADC_CR0_CLREN);
+ } else {
+ CLR_REG16_BIT(ADCx->CR0, ADC_CR0_CLREN);
+ }
+}
+
+/**
+ * @brief Sequence A restart channel selection.
+ * @param [in] ADCx Pointer to ADC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_ADC or CM_ADCx: ADC instance register base.
+ * @param [in] u16SeqAResumeMode Sequence A resume mode.
+ * This parameter can be a value of @ref ADC_SeqA_Resume_Mode
+ * @arg ADC_SEQA_RESUME_SCAN_CONT: Scanning will continue from the interrupted channel.
+ * @arg ADC_SEQA_RESUME_SCAN_RESTART: Scanning will start from the first channel.
+ * @retval None
+ */
+void ADC_SetSeqAResumeMode(CM_ADC_TypeDef *ADCx, uint16_t u16SeqAResumeMode)
+{
+ DDL_ASSERT(IS_ADC_UNIT(ADCx));
+ DDL_ASSERT(IS_ADC_SEQA_RESUME_MD(u16SeqAResumeMode));
+ WRITE_REG16(ADCx->CR1, u16SeqAResumeMode);
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_ADC_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_aes.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_aes.c
new file mode 100644
index 0000000000..6982a936af
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_aes.c
@@ -0,0 +1,316 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_aes.c
+ * @brief This file provides firmware functions to manage the Advanced Encryption
+ * Standard(AES).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Add API AES_DeInit()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_aes.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_AES AES
+ * @brief AES Driver Library
+ * @{
+ */
+
+#if (LL_AES_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup AES_Local_Macros AES Local Macros
+ * @{
+ */
+/* Delay count for timeout */
+#define AES_TIMEOUT (30000UL)
+#define AES_RMU_TIMEOUT (100UL)
+
+/* AES block size */
+#define AES_BLOCK_SIZE (16U)
+
+/**
+ * @defgroup AES_Check_Parameters_Validity AES Check Parameters Validity
+ * @{
+ */
+#define IS_AES_KEY_SIZE(x) \
+( ((x) == AES_KEY_SIZE_16BYTE) || \
+ ((x) == AES_KEY_SIZE_24BYTE) || \
+ ((x) == AES_KEY_SIZE_32BYTE))
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup AES_Local_Functions AES Local Functions
+ * @{
+ */
+/**
+ * @brief Write the input buffer in data register.
+ * @param [in] pu8SrcData Point to the source data buffer.
+ * @retval None
+ */
+static void AES_WriteData(const uint8_t *pu8SrcData)
+{
+ uint8_t i;
+ __IO uint32_t *regDR = &CM_AES->DR0;
+ const uint32_t *pu32Data = (const uint32_t *)((uint32_t)pu8SrcData);
+
+ for (i = 0U; i < 4U; i++) {
+ regDR[i] = pu32Data[i];
+ }
+}
+
+/**
+ * @brief Read the from data register.
+ * @param [out] pu8Result Point to the result buffer.
+ * @retval None
+ */
+static void AES_ReadData(uint8_t *pu8Result)
+{
+ uint8_t i;
+ __IO uint32_t *regDR = &CM_AES->DR0;
+ uint32_t *pu32Result = (uint32_t *)((uint32_t)pu8Result);
+
+ for (i = 0U; i < 4U; i++) {
+ pu32Result[i] = regDR[i];
+ }
+}
+
+/**
+ * @brief Write the input buffer in key register.
+ * @param [in] pu8Key Pointer to the key buffer.
+ * @param [in] u8KeySize AES key size. This parameter can be a value of @ref AES_Key_Size
+ * @retval None
+ */
+static void AES_WriteKey(const uint8_t *pu8Key, uint8_t u8KeySize)
+{
+ uint8_t i;
+ uint8_t u8KeyWordSize = u8KeySize / 4U;
+ __IO uint32_t *regKR = &CM_AES->KR0;
+ const uint32_t *pu32Key = (const uint32_t *)((uint32_t)pu8Key);
+
+ for (i = 0U; i < u8KeyWordSize; i++) {
+ regKR[i] = pu32Key[i];
+ }
+ switch (u8KeySize) {
+ case 16U:
+ u8KeySize = 0U;
+ break;
+ case 24U:
+ u8KeySize = 1U;
+ break;
+ case 32U:
+ u8KeySize = 2U;
+ break;
+ default:
+ break;
+ }
+ MODIFY_REG32(CM_AES->CR, AES_CR_KEYSIZE, ((uint32_t)u8KeySize << AES_CR_KEYSIZE_POS));
+}
+
+/**
+ * @brief Wait AES operation done.
+ * @param None
+ * @retval None
+ */
+static int32_t AES_WaitDone(void)
+{
+ __IO uint32_t u32TimeCount = 0UL;
+ int32_t i32Ret = LL_OK;
+
+ while (bCM_AES->CR_b.START != 0UL) {
+ if (u32TimeCount++ >= AES_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+
+ return i32Ret;
+}
+/**
+ * @}
+ */
+
+/**
+ * @defgroup AES_Global_Functions AES Global Functions
+ * @{
+ */
+
+/**
+ * @brief AES encryption.
+ * @param [in] pu8Plaintext Buffer of the plaintext(the source data which will be encrypted).
+ * @param [in] u32PlaintextSize Length of plaintext in bytes.
+ * @param [in] pu8Key Pointer to the AES key.
+ * @param [in] u8KeySize AES key size. This parameter can be a value of @ref AES_Key_Size
+ * @param [out] pu8Ciphertext Buffer of the ciphertext.
+ * @retval int32_t:
+ * - LL_OK: Encrypt successfully.
+ * - LL_ERR_INVD_PARAM: Invalid parameter.
+ * - LL_TIMEOUT: Encrypt timeout.
+ */
+int32_t AES_Encrypt(const uint8_t *pu8Plaintext, uint32_t u32PlaintextSize,
+ const uint8_t *pu8Key, uint8_t u8KeySize,
+ uint8_t *pu8Ciphertext)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ uint32_t u32Index = 0UL;
+
+ DDL_ASSERT(IS_AES_KEY_SIZE(u8KeySize));
+ DDL_ASSERT((u32PlaintextSize % AES_BLOCK_SIZE) == 0U);
+
+ if ((pu8Plaintext != NULL) && (u32PlaintextSize > 0UL) && \
+ (pu8Key != NULL) && (pu8Ciphertext != NULL)) {
+ AES_WriteKey(pu8Key, u8KeySize);
+ /* Set AES encrypt. */
+ WRITE_REG32(bCM_AES->CR_b.MODE, 0UL);
+ while (u32Index < u32PlaintextSize) {
+ AES_WriteData(&pu8Plaintext[u32Index]);
+ /* Start AES calculating. */
+ WRITE_REG32(bCM_AES->CR_b.START, 1UL);
+ /* Wait for AES to stop */
+ i32Ret = AES_WaitDone();
+ if (i32Ret != LL_OK) {
+ break;
+ }
+ AES_ReadData(&pu8Ciphertext[u32Index]);
+ u32Index += AES_BLOCK_SIZE;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief AES decryption.
+ * @param [in] pu8Ciphertext Buffer of the Ciphertext(the source data which will be decrypted).
+ * @param [in] u32CiphertextSize Length of ciphertext in bytes.
+ * @param [in] pu8Key Pointer to the AES key.
+ * @param [in] u8KeySize AES key size. This parameter can be a value of @ref AES_Key_Size
+ * @param [out] pu8Plaintext Buffer of the plaintext.
+ * @retval int32_t:
+ * - LL_OK: Decrypt successfully.
+ * - LL_ERR_INVD_PARAM: Invalid parameter.
+ * - LL_TIMEOUT: Decrypt timeout.
+ */
+int32_t AES_Decrypt(const uint8_t *pu8Ciphertext, uint32_t u32CiphertextSize,
+ const uint8_t *pu8Key, uint8_t u8KeySize,
+ uint8_t *pu8Plaintext)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ uint32_t u32Index = 0UL;
+
+ DDL_ASSERT(IS_AES_KEY_SIZE(u8KeySize));
+ DDL_ASSERT((u32CiphertextSize % AES_BLOCK_SIZE) == 0U);
+
+ if ((pu8Plaintext != NULL) && (u32CiphertextSize > 0UL) && \
+ (pu8Key != NULL) && (pu8Ciphertext != NULL)) {
+ AES_WriteKey(pu8Key, u8KeySize);
+ /* Set AES decrypt. */
+ WRITE_REG32(bCM_AES->CR_b.MODE, 1UL);
+ while (u32Index < u32CiphertextSize) {
+ AES_WriteData(&pu8Ciphertext[u32Index]);
+ /* Start AES calculating. */
+ WRITE_REG32(bCM_AES->CR_b.START, 1UL);
+ /* Wait for AES to stop */
+ i32Ret = AES_WaitDone();
+ if (i32Ret != LL_OK) {
+ break;
+ }
+ AES_ReadData(&pu8Plaintext[u32Index]);
+ u32Index += AES_BLOCK_SIZE;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief De-Initialize AES function.
+ * @param None
+ * @retval int32_t:
+ * - LL_OK: De-Initialize success.
+ * - LL_ERR_TIMEOUT: Timeout.
+ */
+int32_t AES_DeInit(void)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t u32TimeOut = 0U;
+ /* Check FRST register protect */
+ DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1);
+
+ /* Reset */
+ WRITE_REG32(bCM_RMU->FRST0_b.AES, 0UL);
+ /* Ensure reset procedure is completed */
+ while (0UL == READ_REG32(bCM_RMU->FRST0_b.AES)) {
+ u32TimeOut++;
+ if (u32TimeOut > AES_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+ return i32Ret;
+}
+/**
+ * @}
+ */
+
+#endif /* LL_AES_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
+
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_aos.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_aos.c
new file mode 100644
index 0000000000..f754feff22
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_aos.c
@@ -0,0 +1,230 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_aos.c
+ * @brief This file provides firmware functions to manage the AOS.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-01-15 CDT Macro name modified: from IS_AOS_TRIG_SEL to IS_AOS_TARGET
+ Modified parameters name and comments of AOS_CommonTriggerCmd() and AOS_SetTriggerEventSrc()
+ 2023-06-30 CDT Add AOS_DeInit function
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_aos.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_AOS AOS
+ * @brief AOS Driver Library
+ * @{
+ */
+
+#if (LL_AOS_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup AOS_Local_Macros AOS Local Macros
+ * @{
+ */
+
+/**
+ * @defgroup AOS_Common_Trigger_ID_Validity AOS Common Trigger ID Validity
+ * @{
+ */
+#define IS_AOS_COMM_TRIG(x) \
+( ((x) != 0UL) && \
+ ((x) | AOS_COMM_TRIG_MASK) == AOS_COMM_TRIG_MASK)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup AOS_Target_Select_Validity AOS Target Select Validity
+ * @{
+ */
+#define IS_AOS_TARGET(x) \
+( ((x) == AOS_DCU1) || \
+ ((x) == AOS_DCU2) || \
+ ((x) == AOS_DCU3) || \
+ ((x) == AOS_DMA1_0) || \
+ ((x) == AOS_DMA1_1) || \
+ ((x) == AOS_DMA1_2) || \
+ ((x) == AOS_DMA1_3) || \
+ ((x) == AOS_DMA1_4) || \
+ ((x) == AOS_DMA1_5) || \
+ ((x) == AOS_DMA1_6) || \
+ ((x) == AOS_DMA1_7) || \
+ ((x) == AOS_DMA2_0) || \
+ ((x) == AOS_DMA2_1) || \
+ ((x) == AOS_DMA2_2) || \
+ ((x) == AOS_DMA2_3) || \
+ ((x) == AOS_DMA2_4) || \
+ ((x) == AOS_DMA2_5) || \
+ ((x) == AOS_DMA2_6) || \
+ ((x) == AOS_DMA2_7) || \
+ ((x) == AOS_DMA_RC) || \
+ ((x) == AOS_TMR6_0) || \
+ ((x) == AOS_TMR6_1) || \
+ ((x) == AOS_TMR6_2) || \
+ ((x) == AOS_TMR6_3) || \
+ ((x) == AOS_TMR4) || \
+ ((x) == AOS_EVTPORT12) || \
+ ((x) == AOS_EVTPORT34) || \
+ ((x) == AOS_TMR0) || \
+ ((x) == AOS_TMR2) || \
+ ((x) == AOS_HASH_A) || \
+ ((x) == AOS_HASH_B) || \
+ ((x) == AOS_TMRA_0) || \
+ ((x) == AOS_TMRA_1) || \
+ ((x) == AOS_TMRA_2) || \
+ ((x) == AOS_TMRA_3) || \
+ ((x) == AOS_OTS) || \
+ ((x) == AOS_ADC1_0) || \
+ ((x) == AOS_ADC1_1) || \
+ ((x) == AOS_ADC2_0) || \
+ ((x) == AOS_ADC2_1) || \
+ ((x) == AOS_ADC3_0) || \
+ ((x) == AOS_ADC3_1) || \
+ ((x) == AOS_COMM_1) || \
+ ((x) == AOS_COMM_2))
+
+/**
+ * @}
+ */
+
+#define IS_AOS_PWC_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1)
+
+/* AOS reset timeout */
+#define AOS_RMU_TIMEOUT (100UL)
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup AOS_Global_Functions AOS Global Functions
+ * @{
+ */
+
+/**
+ * @brief De-Initialize AOS.
+ * @param None
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_TIMEOUT: Works timeout.
+ */
+int32_t AOS_DeInit(void)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t u32TimeOut = 0U;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_AOS_PWC_UNLOCKED());
+
+ CLR_REG32_BIT(CM_RMU->FRST0, RMU_FRST0_AOS);
+ /* Ensure reset procedure is completed */
+ while (RMU_FRST0_AOS != READ_REG32_BIT(CM_RMU->FRST0, RMU_FRST0_AOS)) {
+ u32TimeOut++;
+ if (u32TimeOut > AOS_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Common trigger function command
+ * @param [in] u32Target AOS target that need to be triggered by common trigger @ref AOS_Target_Select in details
+ * @param [in] u32CommonTrigger Common trigger ID
+ * This parameter can be one of the following values:
+ * @arg AOS_COMM_TRIG1: Common trigger 1.
+ * @arg AOS_COMM_TRIG2: Common trigger 2.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void AOS_CommonTriggerCmd(uint32_t u32Target, uint32_t u32CommonTrigger, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_AOS_TARGET(u32Target));
+ DDL_ASSERT(IS_AOS_COMM_TRIG(u32CommonTrigger));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(*(__IO uint32_t *)u32Target, u32CommonTrigger);
+ } else {
+ CLR_REG32_BIT(*(__IO uint32_t *)u32Target, u32CommonTrigger);
+ }
+}
+
+/**
+ * @brief Set trigger event source
+ * @param [in] u32Target AOS target that need to be triggered by AOS source @ref AOS_Target_Select in details
+ * @param [in] enSource AOS source that trigger the AOS target @ref en_event_src_t in details
+ * @retval None
+ */
+void AOS_SetTriggerEventSrc(uint32_t u32Target, en_event_src_t enSource)
+{
+ DDL_ASSERT(IS_AOS_TARGET(u32Target));
+
+ MODIFY_REG32(*(__IO uint32_t *)u32Target, AOS_TRIG_SEL_MASK, enSource);
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_AOS_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_can.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_can.c
new file mode 100644
index 0000000000..55e6cc0aae
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_can.c
@@ -0,0 +1,1564 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_can.c
+ * @brief This file provides firmware functions to manage the CAN.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2022-10-31 CDT Deleted redundant comments
+ API fixed: CAN_FillTxFrame(), CAN_GetStatus(), CAN_ClearStatus()
+ 2023-06-30 CDT Added 3 APIs for local-reset.Refine local function CAN_ReadRxBuf(), CAN_WriteTxBuf()
+ Modify typo
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_can.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_CAN CAN
+ * @brief CAN Driver Library
+ * @{
+ */
+
+#if (LL_CAN_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup CAN_Local_Macros CAN Local Macros
+ * @{
+ */
+
+/**
+ * @defgroup CAN_Check_Parameters_Validity CAN Check Parameters Validity
+ * @{
+ */
+#define IS_CAN_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask)))
+
+#define IS_CAN_FUNC_EN(x, en) (((x) == 0U) || ((x) == (en)))
+
+#define IS_CAN_UNIT(x) (((x) == CM_CAN1) || ((x) == CM_CAN2) || ((x) == CM_CAN3))
+#define IS_CAN_FD_UNIT(x) (((x) == CM_CAN1) || ((x) == CM_CAN2) || ((x) == CM_CAN3))
+
+#define IS_CAN_BIT_TIME_PRESC(x) (((x) >= 1U) && ((x) <= 256U))
+
+#define IS_CAN_WORK_MD(x) ((x) <= CAN_WORK_MD_ELB_SILENT)
+
+#define IS_CAN_TX_BUF_TYPE(x) (((x) == CAN_TX_BUF_PTB) || ((x) == CAN_TX_BUF_STB))
+
+#define IS_CAN_PTB_SINGLESHOT_TX(x) IS_CAN_FUNC_EN(x, CAN_PTB_SINGLESHOT_TX_ENABLE)
+
+#define IS_CAN_STB_SINGLESHOT_TX(x) IS_CAN_FUNC_EN(x, CAN_STB_SINGLESHOT_TX_ENABLE)
+
+#define IS_CAN_STB_PRIO_MD(x) IS_CAN_FUNC_EN(x, CAN_STB_PRIO_MD_ENABLE)
+
+#define IS_CAN_TX_REQ(x) IS_CAN_BIT_MASK(x, CAN_TX_REQ_STB_ONE|CAN_TX_REQ_STB_ALL|CAN_TX_REQ_PTB)
+
+#define IS_CAN_RX_ALL_FRAME(x) IS_CAN_FUNC_EN(x, CAN_RX_ALL_FRAME_ENABLE)
+
+#define IS_CAN_RX_OVF_MD(x) (((x) == CAN_RX_OVF_SAVE_NEW) || ((x) == CAN_RX_OVF_DISCARD_NEW))
+
+#define IS_CAN_SELF_ACK(x) IS_CAN_FUNC_EN(x, CAN_SELF_ACK_ENABLE)
+
+#define IS_CAN_INT(x) IS_CAN_BIT_MASK(x, CAN_INT_ALL)
+
+#define IS_CAN_FLAG(x) IS_CAN_BIT_MASK(x, CAN_FLAG_ALL)
+
+#define IS_CAN_ID(ide, x) \
+( (((ide) == 1U) && (((x) | 0x1FFFFFFFUL) == 0x1FFFFFFFUL)) || \
+ (((ide) == 0U) && (((x) | 0x7FFUL) == 0x7FFUL)))
+
+#define IS_CAN_ID_MASK(x) (((x) | 0x1FFFFFFFUL) == 0x1FFFFFFFUL)
+
+#define IS_CAN_IDE(x) (((x) == 0U) || ((x) == 1U))
+
+#define IS_CAN_FILTER(x) IS_CAN_BIT_MASK(x, CAN_FILTER_ALL)
+
+#define IS_CAN_RX_WARN(x) (((x) >= CAN_RX_WARN_MIN) && ((x) <= CAN_RX_WARN_MAX))
+
+#define IS_CAN_ERR_WARN(x) ((x) < 16U)
+
+#define IS_CAN_FD_MD(x) (((x) == CAN_FD_MD_BOSCH) || ((x) == CAN_FD_MD_ISO))
+
+#define IS_CAN_FD_TDC(x) IS_CAN_FUNC_EN(x, CAN_FD_TDC_ENABLE)
+
+#define IS_CAN_FD_SSP(x) ((x) < 128U)
+
+#define IS_TTCAN_TX_BUF_MD(x) (((x) == CAN_TTC_TX_BUF_MD_CAN) || ((x) == CAN_TTC_TX_BUF_MD_TTCAN))
+
+#define IS_TTCAN_TX_BUF_SEL(x) ((x) <= CAN_TTC_TX_BUF_STB3)
+
+#define IS_TTCAN_INT(x) IS_CAN_BIT_MASK(x, CAN_TTC_INT_ALL)
+
+#define IS_TTCAN_FLAG(x) IS_CAN_BIT_MASK(x, CAN_TTC_FLAG_ALL)
+
+#define IS_TTCAN_TX_EN_WINDOW(x) (((x) > 0U) && ((x) <= 16U))
+
+#define IS_TTCAN_NTU_PRESCALER(x) \
+( ((x) == CAN_TTC_NTU_PRESCALER1) || \
+ ((x) == CAN_TTC_NTU_PRESCALER2) || \
+ ((x) == CAN_TTC_NTU_PRESCALER4) || \
+ ((x) == CAN_TTC_NTU_PRESCALER8))
+
+#define IS_TTCAN_TRIG_TYPE(x) \
+( ((x) == CAN_TTC_TRIG_IMMED_TRIG) || \
+ ((x) == CAN_TTC_TRIG_TIME_TRIG) || \
+ ((x) == CAN_TTC_TRIG_SINGLESHOT_TX_TRIG) || \
+ ((x) == CAN_TTC_TRIG_TX_START_TRIG) || \
+ ((x) == CAN_TTC_TRIG_TX_STOP_TRIG))
+
+#define IS_CAN_ID_TYPE(x) \
+( ((x) == CAN_ID_STD_EXT) || \
+ ((x) == CAN_ID_STD) || \
+ ((x) == CAN_ID_EXT))
+
+#define IS_CAN_SBT(seg1, seg2, sjw) \
+( (((seg1) >= 2U) && ((seg1) <= 65U)) && \
+ (((seg2) >= 1U) && ((seg2) <= 8U)) && \
+ (((sjw) >= 1U) && ((sjw) <= 16U)) && \
+ ((seg1) >= ((seg2) + 1U)) && \
+ ((seg2) >= (sjw)))
+
+#define IS_CAN_FD_SBT(seg1, seg2, sjw) \
+( (((seg1) >= 2U) && ((seg1) <= 65U)) && \
+ (((seg2) >= 1U) && ((seg2) <= 32U)) && \
+ (((sjw) >= 1U) && ((sjw) <= 16U)) && \
+ ((seg1) >= ((seg2) + 1U)) && \
+ ((seg2) >= (sjw)))
+
+#define IS_CAN_FD_FBT(seg1, seg2, sjw) \
+( (((seg1) >= 2U) && ((seg1) <= 17U)) && \
+ (((seg2) >= 1U) && ((seg2) <= 8U)) && \
+ (((sjw) >= 1U) && ((sjw) <= 8U)) && \
+ ((seg1) >= ((seg2) + 1U)) && \
+ ((seg2) >= (sjw)))
+
+/* FDF bit check */
+#define IS_CAN20_FDF(x) ((x) == 0U)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_Miscellaneous_Macros CAN Miscellaneous Macros
+ * @{
+ */
+#define CAN_RX_BUF_NUM (8U)
+
+#define CAN_RX_WARN_MIN (1U)
+#define CAN_RX_WARN_MAX (CAN_RX_BUF_NUM)
+
+#define CAN_ERRINT_FLAG_MASK (CAN_ERRINT_BEIF | CAN_ERRINT_ALIF | CAN_ERRINT_EPIF)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/**
+ * @defgroup CAN_Local_Variables CAN Local Variables
+ * @{
+ */
+const static uint8_t m_au8DLC2WordSize[16U] = {
+ 0U, 1U, 1U, 1U, 1U, 2U, 2U, 2U, 2U, 3U, 4U, 5U, 6U, 8U, 12U, 16U
+};
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup CAN_Local_Functions CAN Local Functions
+ * @{
+ */
+
+#if defined __DEBUG
+/**
+ * @brief Initialization parameter check.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] pstcCanInit Pointer to a stc_can_init_t structure value that
+ * contains the configuration information for the CAN.
+ * @retval None
+ */
+static void CAN_InitParameterCheck(CM_CAN_TypeDef *CANx, const stc_can_init_t *pstcCanInit)
+{
+ stc_canfd_config_t *pstcCanFd = pstcCanInit->pstcCanFd;
+
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ DDL_ASSERT(IS_CAN_WORK_MD(pstcCanInit->u8WorkMode));
+ DDL_ASSERT(IS_CAN_PTB_SINGLESHOT_TX(pstcCanInit->u8PTBSingleShotTx));
+ DDL_ASSERT(IS_CAN_STB_SINGLESHOT_TX(pstcCanInit->u8STBSingleShotTx));
+ DDL_ASSERT(IS_CAN_STB_PRIO_MD(pstcCanInit->u8STBPrioMode));
+ DDL_ASSERT(IS_CAN_RX_WARN(pstcCanInit->u8RxWarnLimit));
+ DDL_ASSERT(IS_CAN_ERR_WARN(pstcCanInit->u8ErrorWarnLimit));
+ DDL_ASSERT(IS_CAN_FILTER(pstcCanInit->u16FilterSelect));
+ DDL_ASSERT(IS_CAN_RX_ALL_FRAME(pstcCanInit->u8RxAllFrame));
+ DDL_ASSERT(IS_CAN_RX_OVF_MD(pstcCanInit->u8RxOvfMode));
+ DDL_ASSERT(IS_CAN_SELF_ACK(pstcCanInit->u8SelfAck));
+
+ if (pstcCanFd != NULL) {
+ DDL_ASSERT(IS_CAN_FD_UNIT(CANx));
+ DDL_ASSERT(IS_CAN_BIT_TIME_PRESC(pstcCanInit->stcBitCfg.u32Prescaler));
+ DDL_ASSERT(IS_CAN_FD_SBT(pstcCanInit->stcBitCfg.u32TimeSeg1,
+ pstcCanInit->stcBitCfg.u32TimeSeg2,
+ pstcCanInit->stcBitCfg.u32SJW));
+
+ DDL_ASSERT(IS_CAN_BIT_TIME_PRESC(pstcCanFd->stcBitCfg.u32Prescaler));
+ DDL_ASSERT(IS_CAN_FD_FBT(pstcCanFd->stcBitCfg.u32TimeSeg1,
+ pstcCanFd->stcBitCfg.u32TimeSeg2,
+ pstcCanFd->stcBitCfg.u32SJW));
+
+ DDL_ASSERT(IS_CAN_FD_MD(pstcCanFd->u8Mode));
+ DDL_ASSERT(IS_CAN_FD_TDC(pstcCanFd->u8TDC));
+ DDL_ASSERT(IS_CAN_FD_SSP(pstcCanFd->u8SSPOffset));
+ } else {
+ DDL_ASSERT(IS_CAN_BIT_TIME_PRESC(pstcCanInit->stcBitCfg.u32Prescaler));
+ DDL_ASSERT(IS_CAN_SBT(pstcCanInit->stcBitCfg.u32TimeSeg1,
+ pstcCanInit->stcBitCfg.u32TimeSeg2,
+ pstcCanInit->stcBitCfg.u32SJW));
+ }
+}
+#endif
+
+/**
+ * @brief Specifies work mode for the specified CAN unit.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] u8WorkMode Work mode of CAN.
+ * This parameter can be a value of @ref CAN_Work_Mode
+ * @arg CAN_WORK_MD_NORMAL: Normal work mode.
+ * @arg CAN_WORK_MD_SILENT: Silent work mode. Prohibit data transmission.
+ * @arg CAN_WORK_MD_ILB: Internal loop back mode, just for self-test while developing.
+ * @arg CAN_WORK_MD_ELB: External loop back mode, just for self-test while developing.
+ * @arg CAN_WORK_MD_ELB_SILENT: External loop back silent mode, just for self-test while developing.
+ * It is forbidden to respond to received frames and error frames,
+ * but data can be transmitted.
+ * @retval None
+ * @note Call this function when CFG_STAT.RESET is 0.
+ */
+static void CAN_SetWorkMode(CM_CAN_TypeDef *CANx, uint8_t u8WorkMode)
+{
+ uint8_t u8CFGSTAT = 0U;
+ uint8_t u8TCMD = 0U;
+
+ switch (u8WorkMode) {
+ case CAN_WORK_MD_SILENT:
+ u8TCMD = CAN_TCMD_LOM;
+ break;
+ case CAN_WORK_MD_ILB:
+ u8CFGSTAT = CAN_CFG_STAT_LBMI;
+ break;
+ case CAN_WORK_MD_ELB:
+ u8CFGSTAT = CAN_CFG_STAT_LBME;
+ break;
+ case CAN_WORK_MD_ELB_SILENT:
+ u8TCMD = CAN_TCMD_LOM;
+ u8CFGSTAT = CAN_CFG_STAT_LBME;
+ break;
+ case CAN_WORK_MD_NORMAL:
+ default:
+ break;
+ }
+
+ MODIFY_REG8(CANx->CFG_STAT, CAN_CFG_STAT_LBMI | CAN_CFG_STAT_LBME, u8CFGSTAT);
+ MODIFY_REG8(CANx->TCMD, CAN_TCMD_LOM, u8TCMD);
+}
+
+/**
+ * @brief Configures acceptance filter. Set ID and ID mask for the specified acceptance filters.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] u16FilterSelect Acceptance filters selection.
+ * This parameter can be values of @ref CAN_Acceptance_Filter
+ * @param [in] pstcFilter Pointer to a stc_can_filter_config_t structure type array which contains ID and ID mask
+ * values for the acceptance filters specified by parameter u16FilterSelect.
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_INVD_PARAM: If one the following cases matches:
+ * - u16FilterSelect == 0U.
+ * - pstcFilter == NULL.
+ * @note Call this function when CFG_STAT.RESET is 1.
+ */
+static int32_t CAN_FilterConfig(CM_CAN_TypeDef *CANx, uint16_t u16FilterSelect,
+ const stc_can_filter_config_t *pstcFilter)
+{
+ uint8_t u8FilterAddr = 0U;
+ uint8_t i = 0U;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+
+ if ((u16FilterSelect != 0U) && (pstcFilter != NULL)) {
+ while (u16FilterSelect != 0U) {
+ if ((u16FilterSelect & 0x1U) != 0U) {
+ DDL_ASSERT(IS_CAN_ID_TYPE(pstcFilter[i].u32IDType));
+ DDL_ASSERT(IS_CAN_ID_MASK(pstcFilter[i].u32IDMask));
+ WRITE_REG8(CANx->ACFCTRL, u8FilterAddr);
+ WRITE_REG32(CANx->ACF, pstcFilter[i].u32ID);
+ SET_REG8_BIT(CANx->ACFCTRL, CAN_ACFCTRL_SELMASK);
+ WRITE_REG32(CANx->ACF, pstcFilter[i].u32IDMask | pstcFilter[i].u32IDType);
+ i++;
+ }
+ u16FilterSelect >>= 1U;
+ u8FilterAddr++;
+ }
+
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Configures the specified CAN FD according to the specified parameters
+ * in a @ref stc_canfd_config_t structure.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] pstcCanFd Pointer to a @ref stc_canfd_config_t structure.
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_INVD_PARAM: pstcCanFd == NULL.
+ * @note Call this function when CFG_STAT.RESET is 1.
+ */
+static int32_t CAN_FD_Config(CM_CAN_TypeDef *CANx, const stc_canfd_config_t *pstcCanFd)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (pstcCanFd != NULL) {
+ /* Specifies CAN FD ISO mode. */
+ MODIFY_REG8(CANx->TCTRL, CAN_TCTRL_FD_ISO, pstcCanFd->u8Mode);
+ /**
+ * Configures fast bit time.
+ * Restrictions: u32TimeSeg1 >= u32TimeSeg2 + 1, u32TimeSeg2 >= u32SJW.
+ * TQ = u32Prescaler / CANClock.
+ * Fast bit time = (u32TimeSeg1 + u32TimeSeg2) * TQ.
+ */
+ WRITE_REG32(CANx->FBT, ((pstcCanFd->stcBitCfg.u32TimeSeg1 - 2U) | \
+ ((pstcCanFd->stcBitCfg.u32TimeSeg2 - 1U) << CAN_FBT_F_SEG_2_POS) | \
+ ((pstcCanFd->stcBitCfg.u32SJW - 1U) << CAN_FBT_F_SJW_POS) | \
+ ((pstcCanFd->stcBitCfg.u32Prescaler - 1U) << CAN_FBT_F_PRESC_POS)));
+
+ /* Specifies the secondary sample point. Number of TQ.
+ Enable or disable TDC. */
+ WRITE_REG8(CANx->TDC, pstcCanFd->u8TDC | pstcCanFd->u8SSPOffset);
+
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Write TX buffer register in bytes.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] pstcTx Pointer to a @ref stc_can_tx_frame_t structure.
+ * @retval None
+ */
+static void CAN_WriteTxBuf(CM_CAN_TypeDef *CANx, const stc_can_tx_frame_t *pstcTx)
+{
+ uint8_t i;
+ uint8_t u8WordLen;
+ __IO uint32_t *reg32TBUF;
+ uint32_t *pu32TxData = (uint32_t *)((uint32_t)(&pstcTx->au8Data[0U]));
+
+ reg32TBUF = (__IO uint32_t *)((uint32_t)&CANx->TBUF);
+ reg32TBUF[0U] = pstcTx->u32ID;
+ reg32TBUF[1U] = pstcTx->u32Ctrl;
+
+ u8WordLen = m_au8DLC2WordSize[pstcTx->DLC];
+ if ((pstcTx->FDF == 0U) && (u8WordLen > 2U)) {
+ /* Maximum size of data payload is 8 bytes(2words) for classical CAN frame. */
+ u8WordLen = 2U;
+ }
+
+ for (i = 0U; i < u8WordLen; i++) {
+ reg32TBUF[2U + i] = pu32TxData[i];
+ }
+}
+
+/**
+ * @brief Read RX buffer register in bytes.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] pstcRx Pointer to a @ref stc_can_rx_frame_t structure.
+ * @retval None
+ */
+static void CAN_ReadRxBuf(const CM_CAN_TypeDef *CANx, stc_can_rx_frame_t *pstcRx)
+{
+ __I uint32_t *reg32RBUF;
+ uint8_t i;
+ uint8_t u8WordLen;
+ uint32_t *pu32RxData = (uint32_t *)((uint32_t)(&pstcRx->au8Data[0U]));
+
+ reg32RBUF = (__I uint32_t *)((uint32_t)&CANx->RBUF);
+ pstcRx->u32ID = reg32RBUF[0U];
+ pstcRx->u32Ctrl = reg32RBUF[1U];
+
+ if (pstcRx->IDE == 0U) {
+ pstcRx->u32ID &= 0x7FFUL;
+ } else {
+ pstcRx->u32ID &= 0x1FFFFFFFUL;
+ }
+
+ u8WordLen = m_au8DLC2WordSize[pstcRx->DLC];
+ if ((pstcRx->FDF == 0U) && (u8WordLen > 2U)) {
+ /* Maximum size of data payload is 8 bytes(2words) for classical CAN frame. */
+ u8WordLen = 2U;
+ }
+
+ for (i = 0U; i < u8WordLen; i++) {
+ pu32RxData[i] = reg32RBUF[2U + i];
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_Global_Functions CAN Global Functions
+ * @{
+ */
+
+/**
+ * @brief Initializes the specified CAN peripheral according to the specified parameters
+ * in the structure pstcCanInit.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] pstcCanInit Pointer to a @ref stc_can_init_t structure value that
+ * contains the configuration information for the CAN.
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_INVD_PARAM: pstcCanInit == NULL
+ */
+int32_t CAN_Init(CM_CAN_TypeDef *CANx, const stc_can_init_t *pstcCanInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (pstcCanInit != NULL) {
+#if defined __DEBUG
+ CAN_InitParameterCheck(CANx, pstcCanInit);
+#endif
+ /* Local reset. */
+ SET_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET);
+ /* Configures nominal bit time. */
+ WRITE_REG32(CANx->SBT, ((pstcCanInit->stcBitCfg.u32TimeSeg1 - 2U) | \
+ ((pstcCanInit->stcBitCfg.u32TimeSeg2 - 1U) << CAN_SBT_S_SEG_2_POS) | \
+ ((pstcCanInit->stcBitCfg.u32SJW - 1U) << CAN_SBT_S_SJW_POS) | \
+ ((pstcCanInit->stcBitCfg.u32Prescaler - 1U) << CAN_SBT_S_PRESC_POS)));
+ /* Enable or disable STB priority mode. */
+ MODIFY_REG8(CANx->TCTRL, CAN_TCTRL_TSMODE, pstcCanInit->u8STBPrioMode);
+ /* Configures acceptance filters. */
+ (void)CAN_FilterConfig(CANx, pstcCanInit->u16FilterSelect, pstcCanInit->pstcFilter);
+
+ /* Configures CAN-FD if needed. */
+ if (pstcCanInit->pstcCanFd != NULL) {
+ (void)CAN_FD_Config(CANx, pstcCanInit->pstcCanFd);
+ }
+
+ /* CAN enters normal communication mode. */
+ CLR_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET);
+ /* Specifies CAN work mode. */
+ CAN_SetWorkMode(CANx, pstcCanInit->u8WorkMode);
+ /* Enable or disable single shot transmission mode of PTB and STB. */
+ MODIFY_REG8(CANx->CFG_STAT, \
+ (CAN_CFG_STAT_TPSS | CAN_CFG_STAT_TSSS), \
+ (pstcCanInit->u8PTBSingleShotTx | pstcCanInit->u8STBSingleShotTx));
+ /* Specifies receive buffer almost full warning limit. Specifies error warning limit. */
+ WRITE_REG8(CANx->LIMIT, ((pstcCanInit->u8RxWarnLimit << CAN_LIMIT_AFWL_POS) | pstcCanInit->u8ErrorWarnLimit));
+
+ /* Enable or disable RX all frames(include frames with error).
+ Specifies receive overflow mode. In case of a full rx buffer when a new message is received.
+ Enable or disable self-acknowledge. */
+ WRITE_REG8(CANx->RCTRL, pstcCanInit->u8RxAllFrame | \
+ pstcCanInit->u8RxOvfMode | \
+ pstcCanInit->u8SelfAck);
+ /* Enable acceptance filters that configured before. */
+ WRITE_REG16(CANx->ACFEN, pstcCanInit->u16FilterSelect);
+ /* Configures TTCAN if needed. */
+ if (pstcCanInit->pstcCanTtc != NULL) {
+ (void)CAN_TTC_Config(CANx, pstcCanInit->pstcCanTtc);
+ }
+
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set each @ref stc_can_init_t field to a default value.
+ * Classical CAN bit time configuration:
+ * Based on 40MHz CAN clock, TQ clock is CAN clock divided by 4.
+ * Bit rate 500Kbps, 1 bit time is 20TQs, sample point is 80%.
+ * CAN-FD bit time configuration:
+ * Based on 40MHz CAN clock, TQ clock is CAN clock divided by 1.
+ * Bit rate 2Mbps, 1 bit time is 20TQs, primary sample point is 80%,
+ * secondary sample point is 80%.
+ * @param [in] pstcCanInit Pointer to a @ref stc_can_init_t structure
+ * whose fields will be set to default values.
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_INVD_PARAM: pstcCanInit == NULL.
+ */
+int32_t CAN_StructInit(stc_can_init_t *pstcCanInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (pstcCanInit != NULL) {
+ /**
+ * Synchronization Segment(SS): Fixed as 1TQ
+ * Propagation Time Segment(PTS) and Phase Buffer Segment 1(PBS1): 15TQs
+ * Phase Buffer Segment 2(PBS2): 4TQs
+ *
+ * Field 'S_SEG_1' in register CAN_SBT contains SS, PTS and PBS1.
+ * Field 'S_SEG_2' in register CAN_SBT only contains PBS2.
+ * Sample point = (SS + PTS + PBS1) / (SS + PTS + PBS1 + PBS2)
+ * = (1 + 15) / (1 + 15 + 4)
+ * = 80%.
+ */
+ pstcCanInit->stcBitCfg.u32Prescaler = 4U;
+ pstcCanInit->stcBitCfg.u32TimeSeg1 = 16U;
+ pstcCanInit->stcBitCfg.u32TimeSeg2 = 4U;
+ pstcCanInit->stcBitCfg.u32SJW = 2U;
+ pstcCanInit->pstcFilter = NULL;
+ pstcCanInit->u16FilterSelect = 0U;
+ pstcCanInit->u8WorkMode = CAN_WORK_MD_NORMAL;
+ pstcCanInit->u8PTBSingleShotTx = CAN_PTB_SINGLESHOT_TX_DISABLE;
+ pstcCanInit->u8STBSingleShotTx = CAN_STB_SINGLESHOT_TX_DISABLE;
+ pstcCanInit->u8STBPrioMode = CAN_STB_PRIO_MD_DISABLE;
+ pstcCanInit->u8RxWarnLimit = CAN_RX_WARN_MAX;
+ pstcCanInit->u8ErrorWarnLimit = 7U;
+ pstcCanInit->u8RxAllFrame = CAN_RX_ALL_FRAME_DISABLE;
+ pstcCanInit->u8RxOvfMode = CAN_RX_OVF_DISCARD_NEW;
+ pstcCanInit->u8SelfAck = CAN_SELF_ACK_DISABLE;
+ pstcCanInit->pstcCanTtc = NULL;
+ pstcCanInit->pstcCanFd = NULL;
+
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Deinitialize the specified CAN peripheral registers to their default reset values.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @retval None
+ */
+void CAN_DeInit(CM_CAN_TypeDef *CANx)
+{
+ uint8_t i;
+
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+
+ CLR_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET);
+ for (i = 0U; i < 2U; i++) {
+ WRITE_REG8(CANx->CFG_STAT, 0x80U);
+ WRITE_REG8(CANx->TCMD, 0x00U);
+ WRITE_REG8(CANx->TCTRL, 0x90U);
+ WRITE_REG8(CANx->RCTRL, 0x10U);
+ WRITE_REG8(CANx->RTIE, 0xFEU);
+ WRITE_REG8(CANx->RTIF, 0xFFU);
+ WRITE_REG8(CANx->ERRINT, 0xD5U);
+ WRITE_REG8(CANx->LIMIT, 0x1BU);
+ WRITE_REG32(CANx->SBT, 0x01020203UL);
+ WRITE_REG8(CANx->RECNT, 0x00U);
+ WRITE_REG8(CANx->TECNT, 0x00U);
+ WRITE_REG8(CANx->ACFCTRL, 0x00U);
+ WRITE_REG8(CANx->TBSLOT, 0x00U);
+ WRITE_REG8(CANx->TTCFG, 0xD8U);
+ WRITE_REG16(CANx->TRG_CFG, 0x00U);
+ WRITE_REG16(CANx->TT_TRIG, 0x00U);
+ WRITE_REG16(CANx->TT_WTRIG, 0x00U);
+ WRITE_REG16(CANx->ACFEN, 0x01U);
+ WRITE_REG32(CANx->FBT, 0x01020203UL);
+ WRITE_REG8(CANx->TDC, 0x00U);
+
+ SET_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET);
+ }
+}
+
+/**
+ * @brief Enable or disable specified interrupts.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] u32IntType Interrupt of CAN.
+ * This parameter can be values of @ref CAN_Interrupt_Type
+ * @arg CAN_INT_ERR_INT: Register bit RTIE.EIE. Error interrupt.
+ * @arg CAN_INT_STB_TX: Register bit RTIE.TSIE. STB was transmitted successfully.
+ * @arg CAN_INT_PTB_TX: Register bit RTIE.TPIE. PTB was transmitted successfully.
+ * @arg CAN_INT_RX_BUF_WARN: Register bit RTIE.RAFIE. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value.
+ * @arg CAN_INT_RX_BUF_FULL: Register bit RTIE.RFIE. The FIFO of receive buffer is full.
+ * @arg CAN_INT_RX_OVERRUN: Register bit RTIE.ROIE. Receive buffers are full and there is a further message to be stored.
+ * @arg CAN_INT_RX: Register bit RTIE.RIE. Received a valid data frame or remote frame.
+ * @arg CAN_INT_BUS_ERR: Register bit ERRINT.BEIE. Arbitration lost caused bus error
+ * @arg CAN_INT_ARBITR_LOST: Register bit ERRINT.ALIE. Arbitration lost.
+ * @arg CAN_INT_ERR_PASSIVE: Register bit ERRINT.EPIE. A change from error-passive to error-active or error-active to error-passive has occurred.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void CAN_IntCmd(CM_CAN_TypeDef *CANx, uint32_t u32IntType, en_functional_state_t enNewState)
+{
+ uint8_t u8RTIE;
+ uint8_t u8ERRINT;
+
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ DDL_ASSERT(IS_CAN_INT(u32IntType));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u8RTIE = (uint8_t)u32IntType;
+ u8ERRINT = (uint8_t)(u32IntType >> 8U);
+
+ if (enNewState == ENABLE) {
+ SET_REG8_BIT(CANx->RTIE, u8RTIE);
+ SET_REG8_BIT(CANx->ERRINT, u8ERRINT);
+ } else {
+ CLR_REG8_BIT(CANx->RTIE, u8RTIE);
+ CLR_REG8_BIT(CANx->ERRINT, u8ERRINT);
+ }
+}
+
+/**
+ * @brief Fills transmit frame.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] u8TxBufType CAN transmit buffer type.
+ * This parameter can be a value of @ref CAN_Tx_Buf_Type
+ * @param [in] pstcTx Pointer to a @ref stc_can_tx_frame_t structure.
+ * @arg CAN_TX_BUF_PTB: Primary transmit buffer.
+ * @arg CAN_TX_BUF_STB: Secondary transmit buffer.
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_INVD_PARAM: pstcTx == NULL.
+ * - LL_ERR_BUF_FULL: The specified transmit buffer is full.
+ * - LL_ERR_BUSY: The specified transmit buffer is being transmitted.
+ */
+int32_t CAN_FillTxFrame(CM_CAN_TypeDef *CANx, uint8_t u8TxBufType, const stc_can_tx_frame_t *pstcTx)
+{
+ uint8_t u8RTIE;
+ uint8_t u8TCTRL;
+ uint32_t u32RegAddr;
+ int32_t i32Ret = LL_OK;
+
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ DDL_ASSERT(IS_CAN_TX_BUF_TYPE(u8TxBufType));
+
+ if (pstcTx != NULL) {
+ if ((CANx == CM_CAN1) || (CANx == CM_CAN3)) {
+ DDL_ASSERT(IS_CAN20_FDF(pstcTx->FDF));
+ }
+ if (u8TxBufType == CAN_TX_BUF_PTB) {
+ if (READ_REG8_BIT(CANx->TCMD, CAN_TCMD_TPE) != 0U) {
+ /* PTB is being transmitted. */
+ i32Ret = LL_ERR_BUSY;
+ }
+ } else {
+ if (READ_REG8_BIT(CANx->TCMD, (CAN_TCMD_TSONE | CAN_TCMD_TSALL)) != 0U) {
+ /* STB is being transmitted. */
+ i32Ret = LL_ERR_BUSY;
+ } else {
+ u8RTIE = READ_REG8(CANx->RTIE);
+ u8TCTRL = READ_REG8(CANx->TCTRL);
+ if (((u8RTIE & CAN_RTIE_TSFF) == CAN_RTIE_TSFF) || \
+ ((u8TCTRL & CAN_TCTRL_TSSTAT) == CAN_TCTRL_TSSTAT)) {
+ /* All STBs are filled. */
+ i32Ret = LL_ERR_BUF_FULL;
+ }
+ }
+ }
+
+ if (i32Ret == LL_OK) {
+ /* Assert ID */
+ DDL_ASSERT(IS_CAN_ID(pstcTx->IDE, pstcTx->u32ID));
+
+ /* Specifies the transmit buffer, PTB or STB. */
+ u32RegAddr = (uint32_t)&CANx->TCMD;
+ WRITE_REG32(PERIPH_BIT_BAND(u32RegAddr, CAN_TCMD_TBSEL_POS), u8TxBufType);
+
+ CAN_WriteTxBuf(CANx, pstcTx);
+
+ if (u8TxBufType == CAN_TX_BUF_STB) {
+ /* After writes the data in transmit buffer(TB), sets the TSNEXT bit to indicate that the current
+ STB slot has been filled, so that the hardware will point TB to the next STB slot. */
+ SET_REG8_BIT(CANx->TCTRL, CAN_TCTRL_TSNEXT);
+ }
+ }
+ } else {
+ i32Ret = LL_ERR_INVD_PARAM;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Starts transmission.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] u8TxRequest The transmit buffer to be transmitted.
+ * This parameter can be values of @ref CAN_Tx_Request
+ * @arg CAN_TX_REQ_STB_ONE: Transmit one STB frame.
+ * @arg CAN_TX_REQ_STB_ALL: Transmit all STB frames.
+ * @arg CAN_TX_REQ_PTB: Transmit PTB frame.
+ * @retval None
+ * @note Call this function when CFG_STAT.RESET is 0.
+ */
+void CAN_StartTx(CM_CAN_TypeDef *CANx, uint8_t u8TxRequest)
+{
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ DDL_ASSERT(IS_CAN_TX_REQ(u8TxRequest));
+ SET_REG8_BIT(CANx->TCMD, u8TxRequest);
+}
+
+/**
+ * @brief Abort the transmission of the specified transmit buffer.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] u8TxBufType The transmit buffer to be aborted.
+ * This parameter can be a value of @ref CAN_Tx_Buf_Type
+ * @arg CAN_TX_BUF_PTB: Abort PTB transmission.
+ * @arg CAN_TX_BUF_STB: Abort STB transmission.
+ * @retval None
+ * @note Call this function when CFG_STAT.RESET is 0.
+ */
+void CAN_AbortTx(CM_CAN_TypeDef *CANx, uint8_t u8TxBufType)
+{
+ uint8_t au8Abort[] = {CAN_TCMD_TPA, CAN_TCMD_TSA};
+
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ DDL_ASSERT(IS_CAN_TX_BUF_TYPE(u8TxBufType));
+ SET_REG8_BIT(CANx->TCMD, au8Abort[u8TxBufType]);
+}
+
+/**
+ * @brief Get one received frame.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [out] pstcRx Pointer to a @ref stc_can_rx_frame_t structure.
+ * @retval int32_t:
+ * - LL_OK: Get one received frame successfully.
+ * - LL_ERR_BUF_EMPTY: Receive buffer is empty, and no frame has been read.
+ * - LL_ERR_INVD_PARAM: pstcRx == NULL.
+ */
+int32_t CAN_GetRxFrame(CM_CAN_TypeDef *CANx, stc_can_rx_frame_t *pstcRx)
+{
+ int32_t i32Ret = LL_ERR_BUF_EMPTY;
+
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+
+ if (pstcRx == NULL) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ if (READ_REG8_BIT(CANx->RCTRL, CAN_RCTRL_RSTAT) != CAN_RX_BUF_EMPTY) {
+ CAN_ReadRxBuf(CANx, pstcRx);
+ /* Set RB to point to the next RB slot. */
+ SET_REG8_BIT(CANx->RCTRL, CAN_RCTRL_RREL);
+
+ i32Ret = LL_OK;
+ }
+ }
+
+ return i32Ret;
+}
+
+/** Request a local-reset. The some register (e.g for node configuration) can only be modified if RESET=1.
+ * Bit RESET forces several components to a reset state, see the reference manual for details.
+ * @brief
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @retval None
+ */
+void CAN_EnterLocalReset(CM_CAN_TypeDef *CANx)
+{
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ SET_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET);
+}
+
+/** Exit the local-reset state. A CAN node will participate in CAN communication after RESET is switched to 0 after 11 CAN bit times.
+ * @brief
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @retval None
+ */
+void CAN_ExitLocalReset(CM_CAN_TypeDef *CANx)
+{
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ CLR_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET);
+}
+
+/** Check whether CAN is in the local-reset state.
+ * @brief
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t CAN_GetLocalResetStatus(CM_CAN_TypeDef *CANx)
+{
+ en_flag_status_t enStatus = RESET;
+
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+
+ if (READ_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET) != 0U) {
+ /* The CAN is in local-reset state */
+ enStatus = SET;
+ }
+
+ return enStatus;
+}
+
+/**
+ * @brief Get the status of specified flag.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] u32Flag CAN status flag.
+ * This parameter can be a value of @ref CAN_Status_Flag
+ * @arg CAN_FLAG_BUS_OFF: Register bit CFG_STAT.BUSOFF. CAN bus off.
+ * @arg CAN_FLAG_TX_GOING: Register bit CFG_STAT.TACTIVE. CAN bus is transmitting.
+ * @arg CAN_FLAG_RX_GOING: Register bit CFG_STAT.RACTIVE. CAN bus is receiving.
+ * @arg CAN_FLAG_RX_BUF_OVF: Register bit RCTRL.ROV. Receive buffer is full and there is a further bit to be stored. At least one data is lost.
+ * @arg CAN_FLAG_TX_BUF_FULL: Register bit RTIE.TSFF. Transmit buffers are all full:
+ * TTCFG.TTEN == 0 or TCTRL.TTTEM == 0: ALL STB slots are filled.
+ * TTCFG.TTEN == 1 and TCTRL.TTTEM == 1: Transmit buffer that pointed by TBSLOT.TBPTR is filled.
+ * @arg CAN_FLAG_TX_ABORTED: Register bit RTIF.AIF. Transmit messages requested via TCMD.TPA and TCMD.TSA were successfully canceled.
+ * @arg CAN_FLAG_ERR_INT: Register bit RTIF.EIF. The CFG_STAT.BUSOFF bit changes, or the relative relationship between the value of the error counter and the
+ * set value of the ERROR warning limit changes. For example, the value of the error counter changes from less than
+ * the set value to greater than the set value, or from greater than the set value to less than the set value.
+ * @arg CAN_FLAG_STB_TX: Register bit RTIF.TSIF. STB was transmitted successfully.
+ * @arg CAN_FLAG_PTB_TX: Register bit RTIF.TPIF. PTB was transmitted successfully.
+ * @arg CAN_FLAG_RX_BUF_WARN: Register bit RTIF.RAFIF. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value.
+ * @arg CAN_FLAG_RX_BUF_FULL: Register bit RTIF.RFIF. The FIFO of receive buffer is full.
+ * @arg CAN_FLAG_RX_OVERRUN: Register bit RTIF.ROIF. Receive buffers are all full and there is a further message to be stored.
+ * @arg CAN_FLAG_RX: Register bit RTIF.RIF. Received a valid data frame or remote frame.
+ * @arg CAN_FLAG_BUS_ERR: Register bit ERRINT.BEIF. In case of an error, KOER and the error counters get updated. BEIF gets set if BEIE is enabled
+ * and the other error interrupt flags will act accordingly.
+ * @arg CAN_FLAG_ARBITR_LOST: Register bit ERRINT.ALIF. Arbitration lost.
+ * @arg CAN_FLAG_ERR_PASSIVE: Register bit ERRINT.EPIF. A change from error-passive to error-active or error-active to error-passive has occurred.
+ * @arg CAN_FLAG_ERR_PASSIVE_NODE: Register bit ERRINT.EPASS. The node is an error-passive node.
+ * @arg CAN_FLAG_TEC_REC_WARN: Register bit ERRINT.EWARN. REC or TEC is greater than or equal to the LIMIT.EWL setting value.
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t CAN_GetStatus(const CM_CAN_TypeDef *CANx, uint32_t u32Flag)
+{
+ uint8_t u8CFGSTAT;
+ uint8_t u8RCTRL;
+ uint8_t u8RTIE;
+ uint8_t u8RTIF;
+ uint8_t u8ERRINT;
+ en_flag_status_t enStatus = RESET;
+
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ DDL_ASSERT(IS_CAN_FLAG(u32Flag));
+
+ u8CFGSTAT = (uint8_t)(u32Flag & 0x7UL);
+ u8RCTRL = (uint8_t)(u32Flag & CAN_FLAG_RX_BUF_OVF);
+ u8RTIE = (uint8_t)(u32Flag >> 8U);
+ u8RTIF = (uint8_t)(u32Flag >> 16U);
+ u8ERRINT = (uint8_t)(u32Flag >> 24U);
+
+ u8CFGSTAT = READ_REG8_BIT(CANx->CFG_STAT, u8CFGSTAT);
+ u8RCTRL = READ_REG8_BIT(CANx->RCTRL, u8RCTRL);
+ u8RTIE = READ_REG8_BIT(CANx->RTIE, u8RTIE);
+ u8RTIF = READ_REG8_BIT(CANx->RTIF, u8RTIF);
+ u8ERRINT = READ_REG8_BIT(CANx->ERRINT, u8ERRINT);
+
+ if ((u8CFGSTAT != 0U) || (u8RCTRL != 0U) || \
+ (u8RTIE != 0U) || (u8RTIF != 0U) || (u8ERRINT != 0U)) {
+ enStatus = SET;
+ }
+
+ return enStatus;
+}
+
+/**
+ * @brief Clear the status of specified flags.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] u32Flag CAN status flag.
+ * This parameter can be values of @ref CAN_Status_Flag
+ * @arg CAN_FLAG_TX_ABORTED: Register bit RTIF.AIF. Transmit messages requested via TCMD.TPA and TCMD.TSA were successfully canceled.
+ * @arg CAN_FLAG_ERR_INT: Register bit RTIF.EIF. The CFG_STAT.BUSOFF bit changes, or the relative relationship between the value of the error counter
+ * and the set value of the ERROR warning limit changes. For example, the value of the error counter changes from less than
+ * the set value to greater than the set value, or from greater than the set value to less than the set value.
+ * @arg CAN_FLAG_STB_TX: Register bit RTIF.TSIF. STB was transmitted successfully.
+ * @arg CAN_FLAG_PTB_TX: Register bit RTIF.TPIF. PTB was transmitted successfully.
+ * @arg CAN_FLAG_RX_BUF_WARN: Register bit RTIF.RAFIF. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value.
+ * @arg CAN_FLAG_RX_BUF_FULL: Register bit RTIF.RFIF. The FIFO of receive buffer is full.
+ * @arg CAN_FLAG_RX_OVERRUN: Register bit RTIF.ROIF. Receive buffers are all full and there is a further message to be stored.
+ * @arg CAN_FLAG_RX: Register bit RTIF.RIF. Received a valid data frame or remote frame.
+ * @arg CAN_FLAG_BUS_ERR: Register bit ERRINT.BEIF. In case of an error, KOER and the error counters get updated. BEIF gets set if BEIE is enabled
+ * and the other error interrupt flags will act accordingly.
+ * @arg CAN_FLAG_ARBITR_LOST: Register bit ERRINT.ALIF. Arbitration lost.
+ * @arg CAN_FLAG_ERR_PASSIVE: Register bit ERRINT.EPIF. A change from error-passive to error-active or error-active to error-passive has occurred.
+ * @arg CAN_FLAG_ERR_PASSIVE_NODE: Register bit ERRINT.EPASS. The node is an error-passive node.
+ * @arg CAN_FLAG_TEC_REC_WARN: Register bit ERRINT.EWARN. REC or TEC is greater than or equal to the LIMIT.EWL setting value.
+ * @retval None
+ */
+void CAN_ClearStatus(CM_CAN_TypeDef *CANx, uint32_t u32Flag)
+{
+ uint8_t u8RTIF;
+ uint8_t u8ERRINT;
+ uint8_t u8Reg;
+
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ DDL_ASSERT(IS_CAN_FLAG(u32Flag));
+
+ u32Flag &= CAN_FLAG_CLR_ALL;
+ u8RTIF = (uint8_t)(u32Flag >> 16U);
+ u8ERRINT = (uint8_t)(u32Flag >> 24U);
+
+ WRITE_REG8(CANx->RTIF, u8RTIF);
+
+ u8Reg = READ_REG8(CANx->ERRINT);
+ u8Reg &= (uint8_t)(~CAN_ERRINT_FLAG_MASK);
+ u8Reg |= u8ERRINT;
+ WRITE_REG8(CANx->ERRINT, u8Reg);
+}
+
+/**
+ * @brief Get the value of CAN status.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @retval An uint32_t type value that includes the flowing status flags.
+ * - CAN_FLAG_BUS_OFF: Register bit CFG_STAT.BUSOFF. CAN bus off.
+ * - CAN_FLAG_TX_GOING: Register bit CFG_STAT.TACTIVE. CAN bus is transmitting.
+ * - CAN_FLAG_RX_GOING: Register bit CFG_STAT.RACTIVE. CAN bus is receiving.
+ * - CAN_FLAG_RX_BUF_OVF: Register bit RCTRL.ROV. Receive buffer is full and there is a further bit to be stored. At least one data is lost.
+ * - CAN_FLAG_TX_BUF_FULL: Register bit RTIE.TSFF. Transmit buffers are all full:
+ * TTCFG.TTEN == 0 or TCTRL.TTTEM == 0: ALL STB slots are filled.
+ * TTCFG.TTEN == 1 and TCTRL.TTTEM == 1: Transmit buffer that pointed by TBSLOT.TBPTR is filled.
+ * - CAN_FLAG_TX_ABORTED: Register bit RTIF.AIF. Transmit messages requested via TCMD.TPA and TCMD.TSA were successfully canceled.
+ * - CAN_FLAG_ERR_INT: Register bit RTIF.EIF. The CFG_STAT.BUSOFF bit changes, or the relative relationship between the value of the error counter and the
+ * set value of the ERROR warning limit changes. For example, the value of the error counter changes from less than
+ * the set value to greater than the set value, or from greater than the set value to less than the set value.
+ * - CAN_FLAG_STB_TX: Register bit RTIF.TSIF. STB was transmitted successfully.
+ * - CAN_FLAG_PTB_TX: Register bit RTIF.TPIF. PTB was transmitted successfully.
+ * - CAN_FLAG_RX_BUF_WARN: Register bit RTIF.RAFIF. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value.
+ * - CAN_FLAG_RX_BUF_FULL: Register bit RTIF.RFIF. The FIFO of receive buffer is full.
+ * - CAN_FLAG_RX_OVERRUN: Register bit RTIF.ROIF. Receive buffers are all full and there is a further message to be stored.
+ * - CAN_FLAG_RX: Register bit RTIF.RIF. Received a valid data frame or remote frame.
+ * - CAN_FLAG_BUS_ERR: Register bit ERRINT.BEIF. In case of an error, KOER and the error counters get updated. BEIF gets set if BEIE is enabled
+ * and the other error interrupt flags will act accordingly.
+ * - CAN_FLAG_ARBITR_LOST: Register bit ERRINT.ALIF. Arbitration lost.
+ * - CAN_FLAG_ERR_PASSIVE: Register bit ERRINT.EPIF. A change from error-passive to error-active or error-active to error-passive has occurred.
+ * - CAN_FLAG_ERR_PASSIVE_NODE: Register bit ERRINT.EPASS. The node is an error-passive node.
+ * - CAN_FLAG_TEC_REC_WARN: Register bit ERRINT.EWARN. REC or TEC is greater than or equal to the LIMIT.EWL setting value.
+ */
+uint32_t CAN_GetStatusValue(const CM_CAN_TypeDef *CANx)
+{
+ uint32_t u32RCTRL;
+ uint32_t u32RTIE;
+ uint32_t u32RTIF;
+ uint32_t u32ERRINT;
+ uint32_t u32RetVal;
+
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+
+ u32RetVal = CANx->CFG_STAT;
+ u32RCTRL = CANx->RCTRL;
+ u32RCTRL &= CAN_FLAG_RX_BUF_OVF;
+ u32RTIE = CANx->RTIE;
+ u32RTIF = CANx->RTIF;
+ u32ERRINT = CANx->ERRINT;
+
+ u32RetVal |= (u32RCTRL | (u32RTIE << 8U) | (u32RTIF << 16U) | (u32ERRINT << 24U));
+ u32RetVal &= CAN_FLAG_ALL;
+
+ return u32RetVal;
+}
+
+/**
+ * @brief Get the information of CAN errors.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [out] pstcErr Pointer to a @ref stc_can_error_info_t structure.
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_INVD_PARAM: pstcErr == NULL.
+ */
+int32_t CAN_GetErrorInfo(const CM_CAN_TypeDef *CANx, stc_can_error_info_t *pstcErr)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+
+ if (pstcErr != NULL) {
+ pstcErr->u8ArbitrLostPos = READ_REG8_BIT(CANx->EALCAP, CAN_EALCAP_ALC);
+ pstcErr->u8ErrorType = READ_REG8_BIT(CANx->EALCAP, CAN_EALCAP_KOER) >> CAN_EALCAP_KOER_POS;
+ pstcErr->u8RxErrorCount = READ_REG8(CANx->RECNT);
+ pstcErr->u8TxErrorCount = READ_REG8(CANx->TECNT);
+
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Get status(full or empty) of transmit buffer.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @retval An uint8_t type value of status of transmit buffer. It can be a value of @ref CAN_Tx_Buf_Status
+ * - CAN_TX_BUF_EMPTY: TTCAN is disabled(TTEN == 0): STB is empty.
+ * TTCAN is disabled(TTEN == 1) and transmit buffer is specified by TBPTR and TTPTR(TTTBM == 1):
+ * PTB and STB are both empty.
+ * - CAN_TX_BUF_NOT_MORE_THAN_HALF: TTEN == 0: STB is not less than half full;
+ * TTEN == 1 && TTTBM == 1: PTB and STB are neither empty.
+ * - CAN_TX_BUF_MORE_THAN_HALF: TTEN == 0: STB is more than half full;
+ * TTEN == 1 && TTTBM == 1: reserved value.
+ * - CAN_TX_BUF_FULL: TTEN == 0: STB is full;
+ * TTEN == 1 && TTTBM == 1: PTB and STB are both full.
+ */
+uint8_t CAN_GetTxBufStatus(const CM_CAN_TypeDef *CANx)
+{
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ return (READ_REG8_BIT(CANx->TCTRL, CAN_TCTRL_TSSTAT));
+}
+
+/**
+ * @brief Get status(full or empty) of receive buffer.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @retval An uint8_t type value of status of receive buffer. It can be a value of @ref CAN_Rx_Buf_Status
+ * - CAN_RX_BUF_EMPTY: Receive buffer is empty.
+ * - CAN_RX_BUF_NOT_WARN: Receive buffer is not empty, but is less than almost full warning limit.
+ * - CAN_RX_BUF_WARN: Receive buffer is not full, but is more than or equal to almost full warning limit.
+ * - CAN_RX_BUF_FULL: Receive buffer is full.
+ */
+uint8_t CAN_GetRxBufStatus(const CM_CAN_TypeDef *CANx)
+{
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ return (READ_REG8_BIT(CANx->RCTRL, CAN_RCTRL_RSTAT));
+}
+
+/**
+ * @brief Enable or disable the specified acceptance filters.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] u16FilterSelect Acceptance filters selection.
+ * This parameter can be values of @ref CAN_Acceptance_Filter
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void CAN_FilterCmd(CM_CAN_TypeDef *CANx, uint16_t u16FilterSelect, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ DDL_ASSERT(IS_CAN_FILTER(u16FilterSelect));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (enNewState == ENABLE) {
+ SET_REG16_BIT(CANx->ACFEN, u16FilterSelect);
+ } else {
+ CLR_REG16_BIT(CANx->ACFEN, u16FilterSelect);
+ }
+}
+
+/**
+ * @brief Set receive buffer full warning limit.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] u8RxWarnLimit: Receive buffer full warning limit.
+ * When the number of received frames reaches the value specified by
+ * parameter 'u8RxWarnLimit', register bit RTIF.RAFIF set and the
+ * interrupt occurred if it was enabled.
+ * @retval None
+ */
+void CAN_SetRxWarnLimit(CM_CAN_TypeDef *CANx, uint8_t u8RxWarnLimit)
+{
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ DDL_ASSERT(IS_CAN_RX_WARN(u8RxWarnLimit));
+ MODIFY_REG8(CANx->LIMIT, CAN_LIMIT_AFWL, u8RxWarnLimit << CAN_LIMIT_AFWL_POS);
+}
+
+/**
+ * @brief Set error warning limit.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] u8ErrorWarnLimit Programmable error warning limit. Range is [0, 15].
+ * Error warning limit = (u8ErrorWarnLimit + 1) * 8.
+ * @retval None
+ */
+void CAN_SetErrorWarnLimit(CM_CAN_TypeDef *CANx, uint8_t u8ErrorWarnLimit)
+{
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ DDL_ASSERT(IS_CAN_ERR_WARN(u8ErrorWarnLimit));
+ MODIFY_REG8(CANx->LIMIT, CAN_LIMIT_EWL, u8ErrorWarnLimit);
+}
+
+/**
+ * @brief Set each @ref stc_canfd_config_t field to a default value.
+ * Based on 40MHz CAN clock, TQ clock is CAN clock divided by 1.
+ * Bit rate 2Mbps, 1 bit time is 20TQs, primary sample point is 80%,
+ * secondary sample point is 80%.
+ * @param [in] pstcCanFd Pointer to a @ref stc_canfd_config_t structure.
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_INVD_PARAM: pstcCanFd == NULL.
+ * @note 2. CAN2 supports CAN-FD.
+ */
+int32_t CAN_FD_StructInit(stc_canfd_config_t *pstcCanFd)
+{
+ /**
+ * u8TDC: Enable(CAN_FD_TDC_ENABLE) or disable(CAN_FD_TDC_DISABLE) transmitter delay compensation.
+ * u8SSPOffset: The position(TQs) of secondary sample point.
+ *
+ * Primary sample point: u32TimeSeg1 / (u32TimeSeg1 + u32TimeSeg2) = 80%
+ * Secondary sample point: u8SSPOffset / (u32TimeSeg1 + u32TimeSeg2) = 80%
+ *
+ * u32TimeSeg1: TQs of segment 1. Contains synchronization segment,
+ * propagation time segment and phase buffer segment 1.
+ * u32TimeSeg2: TQs of segment 2(Phase buffer segment 2).
+ * u32SJW: TQs of synchronization jump width.
+ * u32Prescaler: Range [1, 256].
+ */
+
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (pstcCanFd != NULL) {
+ pstcCanFd->stcBitCfg.u32Prescaler = 1U;
+ pstcCanFd->stcBitCfg.u32TimeSeg1 = 16U;
+ pstcCanFd->stcBitCfg.u32TimeSeg2 = 4U;
+ pstcCanFd->stcBitCfg.u32SJW = 4U;
+ pstcCanFd->u8Mode = CAN_FD_MD_ISO;
+ pstcCanFd->u8TDC = CAN_FD_TDC_ENABLE;
+ pstcCanFd->u8SSPOffset = 16U;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Enable or disable the FD function of the specified CAN controller.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void CAN_FD_Cmd(const CM_CAN_TypeDef *CANx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_CAN_FD_UNIT(CANx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (CANx == CM_CAN1) {
+ WRITE_REG32(bCM_PERIC->CAN_SYCTLREG_b.CAN1FDE, enNewState);
+ } else if (CANx == CM_CAN2) {
+ WRITE_REG32(bCM_PERIC->CAN_SYCTLREG_b.CAN2FDE, enNewState);
+ } else {
+ WRITE_REG32(bCM_PERIC->CAN_SYCTLREG_b.CAN3FDE, enNewState);
+ }
+}
+
+/**
+ * @brief Set each @ref stc_can_ttc_config_t field to a default value.
+ * @param [in] pstcCanTtc Pointer to a @ref stc_can_ttc_config_t structure value that
+ * contains the configuration information for TTCAN.
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_INVD_PARAM: pstcCanTtc == NULL.
+ */
+int32_t CAN_TTC_StructInit(stc_can_ttc_config_t *pstcCanTtc)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (pstcCanTtc != NULL) {
+ pstcCanTtc->u8NTUPrescaler = CAN_TTC_NTU_PRESCALER1;
+ pstcCanTtc->u32RefMsgID = 0x0UL;
+ pstcCanTtc->u32RefMsgIDE = 0U;
+ pstcCanTtc->u8TxBufMode = CAN_TTC_TX_BUF_MD_TTCAN;
+ pstcCanTtc->u16TriggerType = CAN_TTC_TRIG_SINGLESHOT_TX_TRIG;
+ pstcCanTtc->u16TxEnableWindow = 16U;
+ pstcCanTtc->u16TxTriggerTime = 0xFFFFU;
+ pstcCanTtc->u16WatchTriggerTime = 0xFFFFU;
+
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Configures the specified TTCAN according to the specified parameters
+ * in @ref stc_can_ttc_config_t type structure.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] pstcCanTtc Pointer to a @ref stc_can_ttc_config_t structure value that
+ * contains the configuration information for TTCAN.
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_INVD_PARAM: pstcCanTtc == NULL.
+ */
+int32_t CAN_TTC_Config(CM_CAN_TypeDef *CANx, const stc_can_ttc_config_t *pstcCanTtc)
+{
+ uint32_t u32RefMsgID;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+
+ if (pstcCanTtc != NULL) {
+ DDL_ASSERT(IS_TTCAN_TX_BUF_MD(pstcCanTtc->u8TxBufMode));
+ DDL_ASSERT(IS_TTCAN_NTU_PRESCALER(pstcCanTtc->u8NTUPrescaler));
+ DDL_ASSERT(IS_CAN_ID(pstcCanTtc->u32RefMsgIDE, pstcCanTtc->u32RefMsgID));
+ DDL_ASSERT(IS_TTCAN_TRIG_TYPE(pstcCanTtc->u16TriggerType));
+ DDL_ASSERT(IS_TTCAN_TX_EN_WINDOW(pstcCanTtc->u16TxEnableWindow));
+
+ u32RefMsgID = pstcCanTtc->u32RefMsgID & ((uint32_t)(~CAN_REF_MSG_REF_IDE));
+ /* Specifies transmission buffer mode. */
+ MODIFY_REG8(CANx->TCTRL, CAN_TCTRL_TTTBM, pstcCanTtc->u8TxBufMode);
+ /* Specifies Tx_Enable window and trigger type. */
+ WRITE_REG16(CANx->TRG_CFG, pstcCanTtc->u16TriggerType |
+ ((pstcCanTtc->u16TxEnableWindow - 1U) << CAN_TRG_CFG_TEW_POS));
+ /* Specifies ID of reference message and its extension bit. */
+ WRITE_REG32(CANx->REF_MSG, (((pstcCanTtc->u32RefMsgIDE << CAN_REF_MSG_REF_IDE_POS) | u32RefMsgID)));
+ /* Specifies transmission trigger time. */
+ WRITE_REG16(CANx->TT_TRIG, pstcCanTtc->u16TxTriggerTime);
+ /* Specifies watch trigger time. */
+ WRITE_REG16(CANx->TT_WTRIG, pstcCanTtc->u16WatchTriggerTime);
+ /* Specifies NTU prescaler. */
+ MODIFY_REG8(CANx->TTCFG, CAN_TTCFG_T_PRESC, pstcCanTtc->u8NTUPrescaler);
+
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Enable or disable the specified interrupts of TTCAN.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] u8IntType Interrupt of TTCAN.
+ * This parameter can be values of @ref TTCAN_Interrupt_Type
+ * @arg CAN_TTC_INT_TIME_TRIG: Time trigger interrupt.
+ * @arg CAN_TTC_INT_WATCH_TRIG: Watch trigger interrupt.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void CAN_TTC_IntCmd(CM_CAN_TypeDef *CANx, uint8_t u8IntType, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ DDL_ASSERT(IS_TTCAN_INT(u8IntType));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (enNewState == ENABLE) {
+ SET_REG8_BIT(CANx->TTCFG, u8IntType);
+ } else {
+ CLR_REG8_BIT(CANx->TTCFG, u8IntType);
+ }
+}
+
+/**
+ * @brief Enable or disable TTCAN of the specified CAN unit.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ * @note Call this function when CFG_STAT.RESET is 0.
+ */
+void CAN_TTC_Cmd(CM_CAN_TypeDef *CANx, en_functional_state_t enNewState)
+{
+ uint32_t u32Addr;
+
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u32Addr = (uint32_t)&CANx->TTCFG;
+ WRITE_REG32(PERIPH_BIT_BAND(u32Addr, CAN_TTCFG_TTEN_POS), enNewState);
+}
+
+/**
+ * @brief Get status of the specified TTCAN flag.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] u8Flag Status flag of TTCAN.
+ * This parameter can be values of @ref TTCAN_Status_Flag
+ * @arg CAN_TTC_FLAG_TIME_TRIG: Time trigger interrupt flag.
+ * @arg CAN_TTC_FLAG_TRIG_ERR: Trigger error interrupt flag.
+ * @arg CAN_TTC_FLAG_WATCH_TRIG: Watch trigger interrupt flag.
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t CAN_TTC_GetStatus(const CM_CAN_TypeDef *CANx, uint8_t u8Flag)
+{
+ en_flag_status_t enStatus = RESET;
+
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ DDL_ASSERT(IS_TTCAN_FLAG(u8Flag));
+
+ if (READ_REG8_BIT(CANx->TTCFG, (u8Flag & CAN_TTC_FLAG_ALL)) != 0U) {
+ enStatus = SET;
+ }
+
+ return enStatus;
+}
+
+/**
+ * @brief Clear the status of TTCAN flags.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] u8Flag Status flag of TTCAN.
+ * This parameter can be a value of @ref TTCAN_Status_Flag except CAN_TTC_FLAG_TRIG_ERR.
+ * @arg CAN_TTC_FLAG_TIME_TRIG: Time trigger interrupt flag.
+ * @arg CAN_TTC_FLAG_WATCH_TRIG: Watch trigger interrupt flag.
+ * @retval None
+ */
+void CAN_TTC_ClearStatus(CM_CAN_TypeDef *CANx, uint8_t u8Flag)
+{
+ uint8_t u8Reg;
+
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ DDL_ASSERT(IS_TTCAN_FLAG(u8Flag));
+
+ u8Reg = READ_REG8(CANx->TTCFG);
+ u8Reg &= (uint8_t)(~CAN_TTC_FLAG_ALL);
+ u8Reg |= u8Flag;
+ WRITE_REG8(CANx->TTCFG, u8Reg);
+}
+
+/**
+ * @brief Get the status value of TTCAN.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @retval An uint8_t type value that includes the flowing status flags.
+ * - CAN_TTC_FLAG_TIME_TRIG: Time trigger interrupt flag.
+ * - CAN_TTC_FLAG_TRIG_ERR: Trigger error interrupt flag.
+ * - CAN_TTC_FLAG_WATCH_TRIG: Watch trigger interrupt flag.
+ */
+uint8_t CAN_TTC_GetStatusValue(const CM_CAN_TypeDef *CANx)
+{
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ return READ_REG8_BIT(CANx->TTCFG, CAN_TTC_FLAG_ALL);
+}
+
+/**
+ * @brief Specifies trigger type of TTCAN.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] u16TriggerType TTCAN trigger type.
+ * This parameter can be a value of @ref TTCAN_Trigger_Type
+ * @arg CAN_TTC_TRIG_IMMED_TRIG: Immediate trigger for immediate transmission.
+ * @arg CAN_TTC_TRIG_TIME_TRIG: Time trigger for receive triggers.
+ * @arg CAN_TTC_TRIG_SINGLESHOT_TX_TRIG: Single shot transmit trigger for exclusive time windows.
+ * @arg CAN_TTC_TRIG_TX_START_TRIG: Transmit start trigger for merged arbitrating time windows.
+ * @arg CAN_TTC_TRIG_TX_STOP_TRIG: Transmit stop trigger for merged arbitrating time windows.
+ * @retval None
+ */
+void CAN_TTC_SetTriggerType(CM_CAN_TypeDef *CANx, uint16_t u16TriggerType)
+{
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ DDL_ASSERT(IS_TTCAN_TRIG_TYPE(u16TriggerType));
+ MODIFY_REG16(CANx->TRG_CFG, CAN_TRG_CFG_TTYPE, u16TriggerType);
+}
+
+/**
+ * @brief Specifies transmit enable window time of TTCAN.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] u16TxEnableWindow Number of NTU. Time period within which the transmit of a message may be started.
+ * @retval None
+ */
+void CAN_TTC_SetTxEnableWindow(CM_CAN_TypeDef *CANx, uint16_t u16TxEnableWindow)
+{
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ DDL_ASSERT(IS_TTCAN_TX_EN_WINDOW(u16TxEnableWindow));
+ MODIFY_REG16(CANx->TRG_CFG, CAN_TRG_CFG_TEW, (u16TxEnableWindow - 1U) << CAN_TRG_CFG_TEW_POS);
+}
+
+/**
+ * @brief Specifies transmit trigger time of TTCAN.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] u16TxTriggerTime Transmit trigger time(number of NTU).
+ * @retval None
+ */
+void CAN_TTC_SetTxTriggerTime(CM_CAN_TypeDef *CANx, uint16_t u16TxTriggerTime)
+{
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ WRITE_REG16(CANx->TT_TRIG, u16TxTriggerTime);
+}
+
+/**
+ * @brief TTCAN specifies watch-trigger time.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] u16WatchTriggerTime Watch trigger time(number of NTU).
+ * @retval None
+ */
+void CAN_TTC_SetWatchTriggerTime(CM_CAN_TypeDef *CANx, uint16_t u16WatchTriggerTime)
+{
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ WRITE_REG16(CANx->TT_WTRIG, u16WatchTriggerTime);
+}
+
+/**
+ * @brief TTCAN fill transmit frame.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [in] u8CANTTCTxBuf TTCAN transmit buffer selection.
+ * This parameter can be a value of @ref TTCAN_Tx_Buf_Sel
+ * @param [in] pstcTx Pointer to a @ref stc_can_tx_frame_t structure.
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_INVD_PARAM: pstcTx == NULL.
+ * - LL_ERR_BUF_FULL: The target transmit buffer is full.
+ */
+int32_t CAN_TTC_FillTxFrame(CM_CAN_TypeDef *CANx, uint8_t u8CANTTCTxBuf, const stc_can_tx_frame_t *pstcTx)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ DDL_ASSERT(IS_CAN_UNIT(CANx));
+ DDL_ASSERT(IS_TTCAN_TX_BUF_SEL(u8CANTTCTxBuf));
+
+ if (pstcTx != NULL) {
+ DDL_ASSERT(IS_CAN20_FDF(pstcTx->FDF));
+
+ if (READ_REG8_BIT(CANx->TCTRL, CAN_TX_BUF_FULL) == CAN_TX_BUF_FULL) {
+ i32Ret = LL_ERR_BUF_FULL;
+ } else {
+ WRITE_REG8(CANx->TBSLOT, u8CANTTCTxBuf);
+ MODIFY_REG16(CANx->TRG_CFG, CAN_TRG_CFG_TTPTR, u8CANTTCTxBuf);
+ CAN_WriteTxBuf(CANx, pstcTx);
+
+ /* Set buffer as filled. */
+ SET_REG8_BIT(CANx->TBSLOT, CAN_TBSLOT_TBF);
+
+ /* Write MSB of TT_TRIG to transmit. */
+ WRITE_REG16(CANx->TT_TRIG, CANx->TT_TRIG);
+
+ i32Ret = LL_OK;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Get the configuration of TTCAN.
+ * @param [in] CANx Pointer to CAN instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_CAN or CM_CANx: CAN instance register base.
+ * @param [out] pstcCanTtc Pointer to a @ref stc_can_ttc_config_t structure.
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_INVD_PARAM: pstcCanTtc == NULL.
+ */
+int32_t CAN_TTC_GetConfig(const CM_CAN_TypeDef *CANx, stc_can_ttc_config_t *pstcCanTtc)
+{
+ uint32_t u32Tmp;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (pstcCanTtc != NULL) {
+ u32Tmp = READ_REG32(CANx->REF_MSG);
+ pstcCanTtc->u8TxBufMode = READ_REG8_BIT(CANx->TCTRL, CAN_TCTRL_TTTBM);
+ pstcCanTtc->u8NTUPrescaler = READ_REG8_BIT(CANx->TTCFG, CAN_TTCFG_T_PRESC);
+ pstcCanTtc->u32RefMsgIDE = (u32Tmp >> CAN_REF_MSG_REF_IDE_POS) & 0x1UL;
+ pstcCanTtc->u32RefMsgID = u32Tmp & 0x7FFFFFFFUL;
+ pstcCanTtc->u16TriggerType = READ_REG16_BIT(CANx->TRG_CFG, CAN_TRG_CFG_TTYPE);
+ pstcCanTtc->u16TxEnableWindow = (READ_REG16_BIT(CANx->TRG_CFG, CAN_TRG_CFG_TEW) >> CAN_TRG_CFG_TEW_POS) + 1U;
+ pstcCanTtc->u16TxTriggerTime = READ_REG16(CANx->TT_TRIG);
+ pstcCanTtc->u16WatchTriggerTime = READ_REG16(CANx->TT_WTRIG);
+
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_CAN_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_clk.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_clk.c
new file mode 100644
index 0000000000..fdc67d1e4c
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_clk.c
@@ -0,0 +1,1537 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_clk.c
+ * @brief This file provides firmware functions to manage the Clock(CLK).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Modify typo
+ Modify CLK_SetUSBClockSrc(), add delay after configure USB clock
+ 2023-09-30 CDT Modify API CLK_Xtal32Cmd(), CLK_MrcCmd() and CLK_LrcCmd(), use DDL_DelayUS() to replace CLK_Delay()
+ 2023-12-15 CDT Refine API CLK_XtalStdInit. and add API CLK_XtalStdCmd, CLK_SetXtalStdExceptionType
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_clk.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_CLK CLK
+ * @brief Clock Driver Library
+ * @{
+ */
+
+#if (LL_CLK_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup CLK_Local_Macros CLK Local Macros
+ * @{
+ */
+
+/**
+ * @brief CLK_FREQ Clock frequency definition
+ */
+#define CLK_FREQ_48M (48UL*1000UL*1000UL)
+#define CLK_FREQ_64M (64UL*1000UL*1000UL)
+#define CLK_FREQ_32M (32UL*1000UL*1000UL)
+
+/**
+ * @brief Be able to modify TIMEOUT according to board condition.
+ */
+#define CLK_TIMEOUT ((uint32_t)0x1000UL)
+#define CLK_LRC_TIMEOUT (160U)
+#define CLK_MRC_TIMEOUT (1U)
+#define CLK_XTAL32_TIMEOUT (160U)
+
+/**
+ * @brief XTALSTD exception type mask
+ */
+#define CLK_XTALSTD_EXP_TYPE_MASK (CMU_XTALSTDCR_XTALSTDIE | CMU_XTALSTDCR_XTALSTDRE | CMU_XTALSTDCR_XTALSTDRIS)
+
+/**
+ * @brief LRC State ON or OFF
+ */
+#define CLK_LRC_OFF (CMU_LRCCR_LRCSTP)
+#define CLK_LRC_ON (0x00U)
+
+/**
+ * @brief MRC State ON or OFF
+ */
+#define CLK_MRC_OFF (CMU_MRCCR_MRCSTP)
+#define CLK_MRC_ON (0x80U)
+
+/**
+ * @brief Clk PLL Relevant Parameter Range Definition
+ */
+#define CLK_PLLP_DEFAULT (0x01UL)
+#define CLK_PLLQ_DEFAULT (0x01UL)
+#define CLK_PLLR_DEFAULT (0x01UL)
+#define CLK_PLLN_DEFAULT (0x13UL)
+#define CLK_PLLM_DEFAULT (0x00UL)
+
+#define CLK_PLLR_DIV_MIN (2UL)
+#define CLK_PLLR_DIV_MAX (16UL)
+#define CLK_PLLQ_DIV_MIN (2UL)
+#define CLK_PLLQ_DIV_MAX (16UL)
+#define CLK_PLLP_DIV_MIN (2UL)
+#define CLK_PLLP_DIV_MAX (16UL)
+
+#define CLK_PLL_FREQ_MIN (15UL*1000UL*1000UL)
+#define CLK_PLL_VCO_IN_MIN (1UL*1000UL*1000UL)
+#define CLK_PLL_VCO_IN_MAX (25UL*1000UL*1000UL)
+#define CLK_PLL_VCO_OUT_MIN (240UL*1000UL*1000UL)
+#define CLK_PLL_VCO_OUT_MAX (480UL*1000UL*1000UL)
+#define CLK_PLLM_DIV_MIN (1UL)
+#define CLK_PLLM_DIV_MAX (24UL)
+#define CLK_PLLN_MULTI_MIN (20UL)
+#define CLK_PLLN_MULTI_MAX (480UL)
+#define CLK_PLL_FREQ_MAX (120UL*1000UL*1000UL)
+
+/**
+ * @brief Clk PLL Register Redefinition
+ */
+#define PLL_SRC_REG (CM_CMU->PLLHCFGR)
+#define PLL_SRC_BIT (CMU_PLLHCFGR_PLLSRC)
+#define PLL_SRC_POS (CMU_PLLHCFGR_PLLSRC_POS)
+#define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS)
+#define PLL_EN_REG (CM_CMU->PLLHCR)
+
+/**
+ * @brief Switch clock stable time
+ * @note Approx. 30us
+ */
+#define CLK_SYSCLK_SW_STB (30U)
+
+/**
+ * @brief Clk FCG Default Value
+ */
+#define CLK_FCG0_DEFAULT (0xFFFFFA0EUL)
+#define CLK_FCG1_DEFAULT (0xFFFFFFFFUL)
+#define CLK_FCG2_DEFAULT (0xFFFFFFFFUL)
+#define CLK_FCG3_DEFAULT (0xFFFFFFFFUL)
+
+/**
+ * @defgroup CLK_Check_Parameters_Validity CLK Check Parameters Validity
+ * @{
+ */
+/* Check CLK register lock status. */
+#define IS_CLK_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB0) == PWC_FPRC_FPRCB0)
+#define IS_PWC_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1)
+
+/* Parameter valid check for XTAL state */
+#define IS_CLK_XTAL_STATE(x) \
+( ((x) == CLK_XTAL_OFF) || \
+ ((x) == CLK_XTAL_ON))
+
+/* Parameter valid check for XTAL mode */
+#define IS_CLK_XTAL_MD(x) \
+( ((x) == CLK_XTAL_MD_OSC) || \
+ ((x) == CLK_XTAL_MD_EXCLK))
+
+/* Parameter valid check for XTAL driver ability mode */
+#define IS_CLK_XTAL_DRV_MD(x) \
+( ((x) == CLK_XTAL_DRV_HIGH) || \
+ ((x) == CLK_XTAL_DRV_MID) || \
+ ((x) == CLK_XTAL_DRV_LOW) || \
+ ((x) == CLK_XTAL_DRV_ULOW))
+
+/* Parameter valid check for XTAL stable time selection */
+#define IS_CLK_XTAL_STB_SEL(x) \
+( ((x) == CLK_XTAL_STB_133US) || \
+ ((x) == CLK_XTAL_STB_255US) || \
+ ((x) == CLK_XTAL_STB_499US) || \
+ ((x) == CLK_XTAL_STB_988US) || \
+ ((x) == CLK_XTAL_STB_2MS) || \
+ ((x) == CLK_XTAL_STB_4MS) || \
+ ((x) == CLK_XTAL_STB_8MS) || \
+ ((x) == CLK_XTAL_STB_16MS) || \
+ ((x) == CLK_XTAL_STB_31MS))
+
+/* Parameter valid check for XTALDIV state */
+#define IS_CLK_XTALDIV_STATE(x) \
+( ((x) == CLK_XTALDIV_OFF) || \
+ ((x) == CLK_XTALDIV_ON))
+
+/* Parameter valid check for XTALSTD state */
+#define IS_CLK_XTALSTD_STATE(x) \
+( ((x) == CLK_XTALSTD_OFF) || \
+ ((x) == CLK_XTALSTD_ON))
+
+/* Parameter valid check for XTALSTD exception type */
+#define IS_CLK_XTALSTD_EXP_TYPE(x) \
+( ((x) == CLK_XTALSTD_EXP_TYPE_NONE) || \
+ ((x) == CLK_XTALSTD_EXP_TYPE_RST) || \
+ ((x) == CLK_XTALSTD_EXP_TYPE_INT))
+
+/* Parameter valid check for PLL state */
+#define IS_CLK_PLL_STATE(x) \
+( ((x) == CLK_PLL_OFF) || \
+ ((x) == CLK_PLL_ON))
+
+/* Parameter validity check for PLL input source */
+#define IS_CLK_PLL_SRC(x) \
+( ((x) == CLK_PLL_SRC_XTAL) || \
+ ((x) == CLK_PLL_SRC_HRC))
+
+/* Parameter validity check for PLL frequency range */
+#define IS_CLK_PLL_FREQ(x) \
+( ((x) <= CLK_PLL_FREQ_MAX) && \
+ ((x) >= CLK_PLL_FREQ_MIN))
+
+/* Parameter validity check for PLL M divide */
+#define IS_CLK_PLLM_DIV(x) \
+( ((x) <= CLK_PLLM_DIV_MAX) && \
+ ((x) >= CLK_PLLM_DIV_MIN))
+
+/* Parameter validity check for PLL N multi- */
+#define IS_CLK_PLLN_MULTI(x) \
+( ((x) <= CLK_PLLN_MULTI_MAX) && \
+ ((x) >= CLK_PLLN_MULTI_MIN))
+
+/* Parameter validity check for PLL P divide */
+#define IS_CLK_PLLP_DIV(x) \
+( ((x) <= CLK_PLLP_DIV_MAX) && \
+ ((x) >= CLK_PLLP_DIV_MIN))
+
+/* Parameter validity check for PLL_input freq./PLLM(vco_in) */
+#define IS_CLK_PLL_VCO_IN(x) \
+( ((x) <= CLK_PLL_VCO_IN_MAX) && \
+ ((x) >= CLK_PLL_VCO_IN_MIN))
+
+/* Parameter validity check for PLL vco_in*PLLN(vco_out) */
+#define IS_CLK_PLL_VCO_OUT(x) \
+( ((x) <= CLK_PLL_VCO_OUT_MAX) && \
+ ((x) >= CLK_PLL_VCO_OUT_MIN))
+
+/* Parameter validity check for PLL R divide */
+#define IS_CLK_PLLR_DIV(x) \
+( ((x) <= CLK_PLLR_DIV_MAX) && \
+ ((x) >= CLK_PLLR_DIV_MIN))
+
+/* Parameter validity check for PLL Q divide */
+#define IS_CLK_PLLQ_DIV(x) \
+( ((x) <= CLK_PLLQ_DIV_MAX) && \
+ ((x) >= CLK_PLLQ_DIV_MIN))
+
+/* Parameter valid check for XTAL32 state */
+#define IS_CLK_XTAL32_STATE(x) \
+( ((x) == CLK_XTAL32_OFF) || \
+ ((x) == CLK_XTAL32_ON))
+
+/* Parameter valid check for XTAL32 driver ability mode */
+#define IS_CLK_XTAL32_DRV_MD(x) \
+( ((x) == CLK_XTAL32_DRV_MID) || \
+ ((x) == CLK_XTAL32_DRV_HIGH))
+
+/* Parameter valid check for XTAL32 filtering selection */
+#define IS_CLK_XTAL32_FILT_SEL(x) \
+( ((x) == CLK_XTAL32_FILTER_ALL_MD) || \
+ ((x) == CLK_XTAL32_FILTER_RUN_MD) || \
+ ((x) == CLK_XTAL32_FILTER_OFF))
+
+/* Parameter valid check for system clock source */
+#define IS_CLK_SYSCLK_SRC(x) \
+( ((x) == CLK_SYSCLK_SRC_HRC) || \
+ ((x) == CLK_SYSCLK_SRC_MRC) || \
+ ((x) == CLK_SYSCLK_SRC_LRC) || \
+ ((x) == CLK_SYSCLK_SRC_XTAL) || \
+ ((x) == CLK_SYSCLK_SRC_XTAL32) || \
+ ((x) == CLK_SYSCLK_SRC_PLL))
+
+/* Parameter valid check for CLK stable flag. */
+#define IS_CLK_STB_FLAG(x) \
+( ((x) != 0x00U) && \
+ (((x) | CLK_STB_FLAG_MASK) == CLK_STB_FLAG_MASK))
+
+/* Parameter valid check for bus clock category */
+#define IS_CLK_BUS_CLK_CATE(x) (((x) & CLK_BUS_CLK_ALL) != (0x00U))
+
+/* Parameter valid check for HCLK divider */
+#define IS_CLK_HCLK_DIV(x) \
+( ((x) == CLK_HCLK_DIV1) || \
+ ((x) == CLK_HCLK_DIV2) || \
+ ((x) == CLK_HCLK_DIV4) || \
+ ((x) == CLK_HCLK_DIV8) || \
+ ((x) == CLK_HCLK_DIV16) || \
+ ((x) == CLK_HCLK_DIV32) || \
+ ((x) == CLK_HCLK_DIV64))
+
+/* Parameter valid check for PCLK1 divider */
+#define IS_CLK_PCLK1_DIV(x) \
+( ((x) == CLK_PCLK1_DIV1) || \
+ ((x) == CLK_PCLK1_DIV2) || \
+ ((x) == CLK_PCLK1_DIV4) || \
+ ((x) == CLK_PCLK1_DIV8) || \
+ ((x) == CLK_PCLK1_DIV16) || \
+ ((x) == CLK_PCLK1_DIV32) || \
+ ((x) == CLK_PCLK1_DIV64))
+
+/* Parameter valid check for PCLK4 divider */
+#define IS_CLK_PCLK4_DIV(x) \
+( ((x) == CLK_PCLK4_DIV1) || \
+ ((x) == CLK_PCLK4_DIV2) || \
+ ((x) == CLK_PCLK4_DIV4) || \
+ ((x) == CLK_PCLK4_DIV8) || \
+ ((x) == CLK_PCLK4_DIV16) || \
+ ((x) == CLK_PCLK4_DIV32) || \
+ ((x) == CLK_PCLK4_DIV64))
+
+/* Parameter valid check for PCLK3 divider */
+#define IS_CLK_PCLK3_DIV(x) \
+( ((x) == CLK_PCLK3_DIV1) || \
+ ((x) == CLK_PCLK3_DIV2) || \
+ ((x) == CLK_PCLK3_DIV4) || \
+ ((x) == CLK_PCLK3_DIV8) || \
+ ((x) == CLK_PCLK3_DIV16) || \
+ ((x) == CLK_PCLK3_DIV32) || \
+ ((x) == CLK_PCLK3_DIV64))
+
+/* Parameter valid check for EXCLK divider */
+#define IS_CLK_EXCLK_DIV(x) \
+( ((x) == CLK_EXCLK_DIV1) || \
+ ((x) == CLK_EXCLK_DIV2) || \
+ ((x) == CLK_EXCLK_DIV4) || \
+ ((x) == CLK_EXCLK_DIV8) || \
+ ((x) == CLK_EXCLK_DIV16) || \
+ ((x) == CLK_EXCLK_DIV32) || \
+ ((x) == CLK_EXCLK_DIV64))
+
+/* Parameter valid check for PCLK0 divider */
+#define IS_CLK_PCLK0_DIV(x) \
+( ((x) == CLK_PCLK0_DIV1) || \
+ ((x) == CLK_PCLK0_DIV2) || \
+ ((x) == CLK_PCLK0_DIV4) || \
+ ((x) == CLK_PCLK0_DIV8) || \
+ ((x) == CLK_PCLK0_DIV16) || \
+ ((x) == CLK_PCLK0_DIV32) || \
+ ((x) == CLK_PCLK0_DIV64))
+
+/* Parameter valid check for PCLK2 divider */
+#define IS_CLK_PCLK2_DIV(x) \
+( ((x) == CLK_PCLK2_DIV1) || \
+ ((x) == CLK_PCLK2_DIV2) || \
+ ((x) == CLK_PCLK2_DIV4) || \
+ ((x) == CLK_PCLK2_DIV8) || \
+ ((x) == CLK_PCLK2_DIV16) || \
+ ((x) == CLK_PCLK2_DIV32) || \
+ ((x) == CLK_PCLK2_DIV64))
+
+/* Parameter valid check for bus clock */
+#define IS_CLK_BUS_CLK(x) \
+( ((x) == CLK_BUS_HCLK) || \
+ ((x) == CLK_BUS_EXCLK) || \
+ ((x) == CLK_BUS_PCLK0) || \
+ ((x) == CLK_BUS_PCLK1) || \
+ ((x) == CLK_BUS_PCLK2) || \
+ ((x) == CLK_BUS_PCLK3) || \
+ ((x) == CLK_BUS_PCLK4))
+
+/* Parameter valid check for USB clock source */
+#define IS_CLK_USBCLK_SRC(x) \
+( ((x) == CLK_USBCLK_SYSCLK_DIV2) || \
+ ((x) == CLK_USBCLK_SYSCLK_DIV3) || \
+ ((x) == CLK_USBCLK_SYSCLK_DIV4) || \
+ ((x) == CLK_USBCLK_SYSCLK_DIV5) || \
+ ((x) == CLK_USBCLK_SYSCLK_DIV6) || \
+ ((x) == CLK_USBCLK_SYSCLK_DIV7) || \
+ ((x) == CLK_USBCLK_SYSCLK_DIV8) || \
+ ((x) == CLK_USBCLK_PLLQ) || \
+ ((x) == CLK_USBCLK_PLLR))
+
+/* Parameter valid check for CAN clock source */
+#define IS_CLK_CANCLK(x) \
+( ((x) == CLK_CANCLK_SYSCLK_DIV2) || \
+ ((x) == CLK_CANCLK_SYSCLK_DIV3) || \
+ ((x) == CLK_CANCLK_SYSCLK_DIV4) || \
+ ((x) == CLK_CANCLK_SYSCLK_DIV5) || \
+ ((x) == CLK_CANCLK_SYSCLK_DIV6) || \
+ ((x) == CLK_CANCLK_SYSCLK_DIV7) || \
+ ((x) == CLK_CANCLK_SYSCLK_DIV8) || \
+ ((x) == CLK_CANCLK_PLLQ) || \
+ ((x) == CLK_CANCLK_PLLR) || \
+ ((x) == CLK_CANCLK_XTAL ))
+
+/* Parameter valid check for CAN channel for clock source config */
+#define IS_CLK_CAN_UNIT(x) \
+( ((x) == CLK_CAN1) || \
+ ((x) == CLK_CAN2) || \
+ ((x) == CLK_CAN3))
+
+/* Parameter valid check for peripheral source */
+#define IS_CLK_PERIPHCLK_SRC(x) \
+( ((x) == CLK_PERIPHCLK_PCLK) || \
+ ((x) == CLK_PERIPHCLK_PLLQ) || \
+ ((x) == CLK_PERIPHCLK_PLLR))
+
+/* Parameter valid check for TPIU clock divider */
+#define IS_CLK_TPIUCLK_DIV(x) \
+( ((x) == CLK_TPIUCLK_DIV1) || \
+ ((x) == CLK_TPIUCLK_DIV2) || \
+ ((x) == CLK_TPIUCLK_DIV4))
+
+/* Parameter valid check for CLK MCO clock source . */
+#define IS_CLK_MCO_SRC(x) \
+( ((x) == CLK_MCO_SRC_HRC) || \
+ ((x) == CLK_MCO_SRC_MRC) || \
+ ((x) == CLK_MCO_SRC_LRC) || \
+ ((x) == CLK_MCO_SRC_XTAL) || \
+ ((x) == CLK_MCO_SRC_XTAL32) || \
+ ((x) == CLK_MCO_SRC_PLLP) || \
+ ((x) == CLK_MCO_SRC_PLLQ) || \
+ ((x) == CLK_MCO_SRC_HCLK))
+
+/* Parameter valid check for CLK MCO clock divide. */
+#define IS_CLK_MCO_DIV(x) \
+( ((x) == CLK_MCO_DIV1) || \
+ ((x) == CLK_MCO_DIV2) || \
+ ((x) == CLK_MCO_DIV4) || \
+ ((x) == CLK_MCO_DIV8) || \
+ ((x) == CLK_MCO_DIV16) || \
+ ((x) == CLK_MCO_DIV32) || \
+ ((x) == CLK_MCO_DIV64) || \
+ ((x) == CLK_MCO_DIV128))
+
+/* Parameter valid check for CLK MCO channel. */
+#define IS_CLK_MCO_CH(x) \
+( ((x) == CLK_MCO1) || \
+ ((x) == CLK_MCO2))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup CLK_Local_Functions CLK Local Functions
+ * @{
+ */
+/**
+ * @brief Wait clock stable flag.
+ * @param [in] u8Flag Specifies the stable flag to be wait. @ref CLK_STB_Flag
+ * @param [in] u32Time Specifies the time to wait while the flag not be set.
+ * @retval int32_t
+ */
+static int32_t CLK_WaitStable(uint8_t u8Flag, uint32_t u32Time)
+{
+ __IO uint32_t u32Timeout = 0UL;
+ int32_t i32Ret = LL_ERR_TIMEOUT;
+
+ while (u32Timeout <= u32Time) {
+ if (SET == CLK_GetStableStatus(u8Flag)) {
+ i32Ret = LL_OK;
+ break;
+ }
+ u32Timeout++;
+ }
+ return i32Ret;
+}
+
+static void SetSysClockSrc(uint8_t u8Src)
+{
+ uint8_t u8TmpFlag = 0U;
+ /* backup FCGx setting */
+ __IO uint32_t fcg0 = CM_PWC->FCG0;
+ __IO uint32_t fcg1 = CM_PWC->FCG1;
+ __IO uint32_t fcg2 = CM_PWC->FCG2;
+ __IO uint32_t fcg3 = CM_PWC->FCG3;
+
+ DDL_ASSERT(IS_CLK_SYSCLK_SRC(u8Src));
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ /* Only current system clock source or target system clock source is PLLH
+ need to close fcg0~fcg3 and open fcg0~fcg3 during switch system clock source.
+ We need to backup fcg0~fcg3 before close them. */
+ if (CLK_SYSCLK_SRC_PLL == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW) || (CLK_SYSCLK_SRC_PLL == u8Src)) {
+ u8TmpFlag = 1U;
+ /* FCG0 protect judgment */
+ DDL_ASSERT((CM_PWC->FCG0PC & PWC_FCG0PC_PRT0) == PWC_FCG0PC_PRT0);
+ /* Close FCGx. */
+ WRITE_REG32(CM_PWC->FCG0, CLK_FCG0_DEFAULT);
+ WRITE_REG32(CM_PWC->FCG1, CLK_FCG1_DEFAULT);
+ WRITE_REG32(CM_PWC->FCG2, CLK_FCG2_DEFAULT);
+ WRITE_REG32(CM_PWC->FCG3, CLK_FCG3_DEFAULT);
+ /* Wait stable after close FCGx. */
+ DDL_DelayUS(CLK_SYSCLK_SW_STB);
+ }
+ /* Set system clock source */
+ WRITE_REG8(CM_CMU->CKSWR, u8Src);
+ /* Wait stable after setting system clock source */
+ DDL_DelayUS(CLK_SYSCLK_SW_STB);
+ if (1U == u8TmpFlag) {
+ WRITE_REG32(CM_PWC->FCG0, fcg0);
+ WRITE_REG32(CM_PWC->FCG1, fcg1);
+ WRITE_REG32(CM_PWC->FCG2, fcg2);
+ WRITE_REG32(CM_PWC->FCG3, fcg3);
+ /* Wait stable after open fcg. */
+ DDL_DelayUS(CLK_SYSCLK_SW_STB);
+ }
+}
+
+static void GetClockFreq(stc_clock_freq_t *pstcClockFreq)
+{
+ stc_clock_scale_t *pstcClockScale;
+ uint32_t u32HrcValue;
+ uint8_t plln;
+ uint8_t pllp;
+ uint8_t pllm;
+
+ switch (READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) {
+ case CLK_SYSCLK_SRC_HRC:
+ /* HRC is used to system clock */
+ pstcClockFreq->u32SysclkFreq = HRC_VALUE;
+ break;
+ case CLK_SYSCLK_SRC_MRC:
+ /* MRC is used to system clock */
+ pstcClockFreq->u32SysclkFreq = MRC_VALUE;
+ break;
+ case CLK_SYSCLK_SRC_LRC:
+ /* LRC is used to system clock */
+ pstcClockFreq->u32SysclkFreq = LRC_VALUE;
+ break;
+ case CLK_SYSCLK_SRC_XTAL:
+ /* XTAL is used to system clock */
+ pstcClockFreq->u32SysclkFreq = XTAL_VALUE;
+ break;
+ case CLK_SYSCLK_SRC_XTAL32:
+ /* XTAL32 is used to system clock */
+ pstcClockFreq->u32SysclkFreq = XTAL32_VALUE;
+ break;
+ case CLK_SYSCLK_SRC_PLL:
+ /* PLLHP is used as system clock. */
+ pllp = (uint8_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHP) >> CMU_PLLHCFGR_PLLHP_POS);
+ plln = (uint8_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHN) >> CMU_PLLHCFGR_PLLHN_POS);
+ pllm = (uint8_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHM) >> CMU_PLLHCFGR_PLLHM_POS);
+ /* pll = ((pllin / pllm) * plln) / pllp */
+ if (CLK_PLL_SRC_XTAL == PLL_SRC) {
+ pstcClockFreq->u32SysclkFreq = ((XTAL_VALUE / (pllm + 1UL)) * (plln + 1UL)) / (pllp + 1UL);
+ } else {
+ u32HrcValue = HRC_VALUE;
+ pstcClockFreq->u32SysclkFreq = ((u32HrcValue / (pllm + 1UL)) * (plln + 1UL)) / (pllp + 1UL);
+ }
+ break;
+ default:
+ break;
+ }
+
+ pstcClockScale = (stc_clock_scale_t *)((uint32_t)&CM_CMU->SCFGR);
+ pstcClockScale->SCFGR = READ_REG32(CM_CMU->SCFGR);
+ /* Get hclk. */
+ pstcClockFreq->u32HclkFreq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.HCLKS;
+ /* Get pclk1. */
+ pstcClockFreq->u32Pclk1Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK1S;
+ /* Get pclk4. */
+ pstcClockFreq->u32Pclk4Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK4S;
+ /* Get pclk3. */
+ pstcClockFreq->u32Pclk3Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK3S;
+ /* Get exclk. */
+ pstcClockFreq->u32ExclkFreq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.EXCKS;
+ /* Get pclk0. */
+ pstcClockFreq->u32Pclk0Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK0S;
+ /* Get pclk2. */
+ pstcClockFreq->u32Pclk2Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK2S;
+}
+
+static void SetSysClockDiv(uint32_t u32Clock, uint32_t u32Div)
+{
+ uint8_t u8TmpFlag = 0U;
+
+ /* backup FCGx setting */
+ __IO uint32_t fcg0 = CM_PWC->FCG0;
+ __IO uint32_t fcg1 = CM_PWC->FCG1;
+ __IO uint32_t fcg2 = CM_PWC->FCG2;
+ __IO uint32_t fcg3 = CM_PWC->FCG3;
+
+ DDL_ASSERT(IS_CLK_HCLK_DIV(u32Div & CMU_SCFGR_HCLKS));
+ DDL_ASSERT(IS_CLK_PCLK1_DIV(u32Div & CMU_SCFGR_PCLK1S));
+ DDL_ASSERT(IS_CLK_PCLK4_DIV(u32Div & CMU_SCFGR_PCLK4S));
+ DDL_ASSERT(IS_CLK_EXCLK_DIV(u32Div & CMU_SCFGR_EXCKS));
+ DDL_ASSERT(IS_CLK_PCLK0_DIV(u32Div & CMU_SCFGR_PCLK0S));
+ DDL_ASSERT(IS_CLK_PCLK2_DIV(u32Div & CMU_SCFGR_PCLK2S));
+ DDL_ASSERT(IS_CLK_PCLK3_DIV(u32Div & CMU_SCFGR_PCLK3S));
+ DDL_ASSERT(IS_CLK_BUS_CLK_CATE(u32Clock));
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ /* Only current system clock source or target system clock source is PLLH
+ need to close fcg0~fcg3 and open fcg0~fcg3 during switch system clock source.
+ We need to backup fcg0~fcg3 before close them. */
+ if (CLK_SYSCLK_SRC_PLL == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) {
+ u8TmpFlag = 1U;
+ DDL_ASSERT((CM_PWC->FCG0PC & PWC_FCG0PC_PRT0) == PWC_FCG0PC_PRT0);
+ /* Close FCGx. */
+ WRITE_REG32(CM_PWC->FCG0, CLK_FCG0_DEFAULT);
+ WRITE_REG32(CM_PWC->FCG1, CLK_FCG1_DEFAULT);
+ WRITE_REG32(CM_PWC->FCG2, CLK_FCG2_DEFAULT);
+ WRITE_REG32(CM_PWC->FCG3, CLK_FCG3_DEFAULT);
+ /* Wait stable after close FCGx. */
+ DDL_DelayUS(CLK_SYSCLK_SW_STB);
+ }
+ MODIFY_REG32(CM_CMU->SCFGR, u32Clock, u32Div);
+ DDL_DelayUS(CLK_SYSCLK_SW_STB);
+ if (1U == u8TmpFlag) {
+ WRITE_REG32(CM_PWC->FCG0, fcg0);
+ WRITE_REG32(CM_PWC->FCG1, fcg1);
+ WRITE_REG32(CM_PWC->FCG2, fcg2);
+ WRITE_REG32(CM_PWC->FCG3, fcg3);
+ /* Wait stable after open fcg. */
+ DDL_DelayUS(CLK_SYSCLK_SW_STB);
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CLK_Global_Functions CLK Global Functions
+ * @{
+ */
+/**
+ * @brief LRC function enable/disable.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval int32_t:
+ * - LL_OK: LRC operate successfully
+ * - LL_ERR_BUSY: LRC is the system clock, CANNOT stop it.
+ * @note DO NOT STOP LRC while using it as system clock.
+ */
+int32_t CLK_LrcCmd(en_functional_state_t enNewState)
+{
+ int32_t i32Ret = LL_OK;
+
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ if (DISABLE == enNewState) {
+ if (CLK_SYSCLK_SRC_LRC == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) {
+ i32Ret = LL_ERR_BUSY;
+ } else {
+ WRITE_REG8(CM_CMU->LRCCR, CLK_LRC_OFF);
+ }
+ } else {
+ WRITE_REG8(CM_CMU->LRCCR, CLK_LRC_ON);
+ }
+ /* wait approx, 5 * LRC cycle */
+ DDL_DelayUS(CLK_LRC_TIMEOUT);
+
+ return i32Ret;
+}
+
+/**
+ * @brief MRC function enable/disable.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval int32_t:
+ * - LL_OK: MRC operate successfully
+ * - LL_ERR_BUSY: MRC is the system clock, CANNOT stop it.
+ * @note DO NOT STOP MRC while using it as system clock.
+ */
+int32_t CLK_MrcCmd(en_functional_state_t enNewState)
+{
+ int32_t i32Ret = LL_OK;
+
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ if (DISABLE == enNewState) {
+ if (CLK_SYSCLK_SRC_MRC == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) {
+ i32Ret = LL_ERR_BUSY;
+ } else {
+ WRITE_REG8(CM_CMU->MRCCR, CLK_MRC_OFF);
+ }
+ } else {
+ WRITE_REG8(CM_CMU->MRCCR, CLK_MRC_ON);
+ }
+ /* Wait approx. 5 * MRC cycle */
+ DDL_DelayUS(CLK_MRC_TIMEOUT);
+
+ return i32Ret;
+}
+
+/**
+ * @brief HRC function enable/disable.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval int32_t:
+ * - LL_OK: HRC operate successfully
+ * - LL_ERR_BUSY: HRC is the system clock or as the PLL source clock, CANNOT stop it.
+ * - LL_ERR_TIMEOUT: HRC operate Timeout
+ * @note DO NOT STOP HRC while using it as system clock or as the PLL source clock.
+ */
+int32_t CLK_HrcCmd(en_functional_state_t enNewState)
+{
+ int32_t i32Ret = LL_OK;
+
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ if (DISABLE == enNewState) {
+ if (CLK_SYSCLK_SRC_HRC == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) {
+ i32Ret = LL_ERR_BUSY;
+ } else if (CLK_PLL_SRC_HRC == PLL_SRC) {
+ /* HRC as PLL clock source and PLL is working */
+ if (0UL == PLL_EN_REG) {
+ i32Ret = LL_ERR_BUSY;
+ } else {
+ WRITE_REG8(CM_CMU->HRCCR, CLK_HRC_OFF);
+ }
+ } else {
+ WRITE_REG8(CM_CMU->HRCCR, CLK_HRC_OFF);
+ }
+ } else {
+ WRITE_REG8(CM_CMU->HRCCR, CLK_HRC_ON);
+ i32Ret = CLK_WaitStable(CLK_STB_FLAG_HRC, CLK_TIMEOUT);
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set HRC trimming value.
+ * @param [in] i8TrimVal specifies the trimming value for HRC.
+ * @retval None
+ */
+void CLK_HrcTrim(int8_t i8TrimVal)
+{
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ WRITE_REG8(CM_CMU->HRCTRM, i8TrimVal);
+}
+
+/**
+ * @brief Set MRC trimming value.
+ * @param [in] i8TrimVal specifies the trimming value for MRC.
+ * @retval None
+ */
+void CLK_MrcTrim(int8_t i8TrimVal)
+{
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ WRITE_REG8(CM_CMU->MRCTRM, i8TrimVal);
+}
+
+/**
+ * @brief Set LRC trimming value.
+ * @param [in] i8TrimVal specifies the trimming value for LRC.
+ * @retval None
+ */
+void CLK_LrcTrim(int8_t i8TrimVal)
+{
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ WRITE_REG8(CM_CMU->LRCTRM, i8TrimVal);
+}
+
+/**
+ * @brief Init Xtal initial structure with default value.
+ * @param [in] pstcXtalInit specifies the Parameter of XTAL.
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t CLK_XtalStructInit(stc_clock_xtal_init_t *pstcXtalInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ /* Check if pointer is NULL */
+ if (NULL == pstcXtalInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Configure to default value */
+ pstcXtalInit->u8State = CLK_XTAL_OFF;
+ pstcXtalInit->u8Mode = CLK_XTAL_MD_OSC;
+ pstcXtalInit->u8Drv = CLK_XTAL_DRV_HIGH;
+ pstcXtalInit->u8StableTime = CLK_XTAL_STB_2MS;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief XTAL initialize.
+ * @param [in] pstcXtalInit specifies the XTAL initial config.
+ * @retval int32_t:
+ * - LL_OK: XTAL initial successfully.
+ * - LL_ERR_TIMEOUT: XTAL operate timeout.
+ * - LL_ERR_BUSY: XTAL is the system clock, CANNOT stop it.
+ * - LL_ERR_INVD_PARAM: NULL pointer.
+ * @note DO NOT STOP XTAL while using it as system clock.
+ */
+int32_t CLK_XtalInit(const stc_clock_xtal_init_t *pstcXtalInit)
+{
+ int32_t i32Ret;
+
+ if (NULL == pstcXtalInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ DDL_ASSERT(IS_CLK_XTAL_STATE(pstcXtalInit->u8State));
+ DDL_ASSERT(IS_CLK_XTAL_DRV_MD(pstcXtalInit->u8Drv));
+ DDL_ASSERT(IS_CLK_XTAL_MD(pstcXtalInit->u8Mode));
+ DDL_ASSERT(IS_CLK_XTAL_STB_SEL(pstcXtalInit->u8StableTime));
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ WRITE_REG8(CM_CMU->XTALSTBCR, pstcXtalInit->u8StableTime);
+ WRITE_REG8(CM_CMU->XTALCFGR, (0x80U | pstcXtalInit->u8Drv | pstcXtalInit->u8Mode));
+ if (CLK_XTAL_ON == pstcXtalInit->u8State) {
+ i32Ret = CLK_XtalCmd(ENABLE);
+ } else {
+ i32Ret = CLK_XtalCmd(DISABLE);
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief XTAL function enable/disable.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval int32_t:
+ * - LL_OK: XTAL operate successfully
+ * - LL_ERR_BUSY: XTAL is the system clock or as the PLL source clock, CANNOT stop it.
+ * - LL_ERR_TIMEOUT: XTAL operate timeout.
+ * @note DO NOT STOP XTAL while using it as system clock or as the PLL source clock.
+ */
+int32_t CLK_XtalCmd(en_functional_state_t enNewState)
+{
+ int32_t i32Ret = LL_OK;
+
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ if (DISABLE == enNewState) {
+ if (CLK_SYSCLK_SRC_XTAL == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) {
+ i32Ret = LL_ERR_BUSY;
+ } else if (CLK_PLL_SRC_XTAL == PLL_SRC) {
+ /* XTAL as PLL clock source and PLL is working */
+ if (0UL == PLL_EN_REG) {
+ i32Ret = LL_ERR_BUSY;
+ } else {
+ WRITE_REG8(CM_CMU->XTALCR, CLK_XTAL_OFF);
+ }
+ } else {
+ WRITE_REG8(CM_CMU->XTALCR, CLK_XTAL_OFF);
+ }
+ } else {
+ WRITE_REG8(CM_CMU->XTALCR, CLK_XTAL_ON);
+ i32Ret = CLK_WaitStable(CLK_STB_FLAG_XTAL, CLK_TIMEOUT);
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief XTAL divide function enable/disable.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void CLK_XtalDivCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ if (DISABLE == enNewState) {
+ CLR_REG32_BIT(CM_CMU->XTALDIVCR, CMU_XTALDIVCR_FRADIVEN);
+ } else {
+ SET_REG32_BIT(CM_CMU->XTALDIVCR, CMU_XTALDIVCR_FRADIVEN);
+ }
+}
+
+/**
+ * @brief Init Xtal divide initial structure with default value.
+ * @param [in] pstcXtalDivInit specifies the Parameter of XTAL.
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t CLK_XtalDivStructInit(stc_clock_xtaldiv_init_t *pstcXtalDivInit)
+{
+ int32_t i32Ret = LL_OK;;
+
+ if (NULL == pstcXtalDivInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ pstcXtalDivInit->u32State = CLK_XTALDIV_OFF;
+ pstcXtalDivInit->u32Num = 0x3D09U;
+ pstcXtalDivInit->u32Den = 0x40U;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief XTAL divide initialize.
+ * @param [in] pstcXtalDivInit specifies the XTAL initial config.
+ * @arg u32State : The new state of the XTAL divide.
+ * @arg u32Num : The numerator of XTAL divide.
+ * @arg u32Den : The denominator of XTAL divide.
+ * @retval int32_t:
+ * - LL_OK: XTAL divide initial successfully.
+ * - LL_ERR_INVD_PARAM: NULL pointer.
+ */
+int32_t CLK_XtalDivInit(const stc_clock_xtaldiv_init_t *pstcXtalDivInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcXtalDivInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+ DDL_ASSERT(IS_CLK_XTALDIV_STATE(pstcXtalDivInit->u32State));
+
+ WRITE_REG32(CM_CMU->XTALDIVR, (uint32_t)pstcXtalDivInit->u32Num << CMU_XTALDIVR_NUMERATOR_POS | pstcXtalDivInit->u32Den);
+ WRITE_REG32(CM_CMU->XTALDIVCR, pstcXtalDivInit->u32State);
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief XTAL status detection function enable/disable.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void CLK_XtalStdCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ if (DISABLE == enNewState) {
+ CLR_REG8_BIT(CM_CMU->XTALSTDCR, CMU_XTALSTDCR_XTALSTDE);
+ } else {
+ SET_REG8_BIT(CM_CMU->XTALSTDCR, CMU_XTALSTDCR_XTALSTDE);
+ }
+}
+
+/**
+ * @brief Initialise the XTAL status detection.
+ * @param [in] u8State specifies the Parameter of XTALSTD.
+ * @param [in] u8ExceptionType specifies the Parameter of XTALSTD.
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t CLK_XtalStdInit(uint8_t u8State, uint8_t u8ExceptionType)
+{
+ int32_t i32Ret = LL_OK;
+
+ /* Parameter valid check */
+ DDL_ASSERT(IS_CLK_XTALSTD_STATE(u8State));
+ DDL_ASSERT(IS_CLK_XTALSTD_EXP_TYPE(u8ExceptionType));
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ if ((CLK_PLL_SRC_XTAL == PLL_SRC) && (u8ExceptionType == CLK_XTALSTD_EXP_TYPE_INT)) {
+ if (0UL == PLL_EN_REG) {
+ /* while xtal used as PLL clock source, XTALSTD only choose reset exception */
+ i32Ret = LL_ERR_INVD_PARAM;
+ }
+ }
+ if (LL_OK == i32Ret) {
+ /* Initialize XTALSTD */
+ WRITE_REG8(CM_CMU->XTALSTDCR, u8State | u8ExceptionType);
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set XTALSTD exception type.
+ * @param [in] u8ExceptionType specifies the XTALSTD exception type.
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t CLK_SetXtalStdExceptionType(uint8_t u8ExceptionType)
+{
+ int32_t i32Ret = LL_OK;
+
+ /* Parameter valid check */
+ DDL_ASSERT(IS_CLK_XTALSTD_EXP_TYPE(u8ExceptionType));
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ if ((CLK_PLL_SRC_XTAL == PLL_SRC) && (u8ExceptionType == CLK_XTALSTD_EXP_TYPE_INT)) {
+ if (0UL == PLL_EN_REG) {
+ /* while xtal used as PLL clock source, XTALSTD only choose reset exception */
+ i32Ret = LL_ERR_INVD_PARAM;
+ }
+ }
+ if (LL_OK == i32Ret) {
+ /* Set exception type */
+ MODIFY_REG8(CM_CMU->XTALSTDCR, CLK_XTALSTD_EXP_TYPE_MASK, u8ExceptionType);
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Clear the XTAL error flag.
+ * @param None
+ * @retval None
+ * @note The system clock should not be XTAL before call this function.
+ */
+void CLK_ClearXtalStdStatus(void)
+{
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ if (0x01U == READ_REG8(CM_CMU->XTALSTDSR)) {
+ /* Clear the XTAL STD flag */
+ WRITE_REG8(CM_CMU->XTALSTDSR, 0x00U);
+ }
+}
+
+/**
+ * @brief Get the XTAL error flag.
+ * @param None
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t CLK_GetXtalStdStatus(void)
+{
+ return ((0x00U != READ_REG8(CM_CMU->XTALSTDSR)) ? SET : RESET);
+}
+
+/**
+ * @brief Init Xtal32 initial structure with default value.
+ * @param [in] pstcXtal32Init specifies the Parameter of XTAL32.
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t CLK_Xtal32StructInit(stc_clock_xtal32_init_t *pstcXtal32Init)
+{
+ int32_t i32Ret = LL_OK;
+
+ /* Check if pointer is NULL */
+ if (NULL == pstcXtal32Init) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Configure to default value */
+ pstcXtal32Init->u8State = CLK_XTAL32_ON;
+ pstcXtal32Init->u8Drv = CLK_XTAL32_DRV_MID;
+ pstcXtal32Init->u8Filter = CLK_XTAL32_FILTER_ALL_MD;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief XTAL32 initialize.
+ * @param [in] pstcXtal32Init specifies the XTAL32 initial config.
+ * @arg u8State : The new state of the XTAL32.
+ * @arg u8Drv : The XTAL32 drive capacity.
+ * @arg u8Filter : The XTAL32 noise filter on or off.
+ * @retval int32_t:
+ * - LL_OK: XTAL32 initial successfully.
+ * - LL_ERR_BUSY: XTAL32 is the system clock, CANNOT stop it.
+ * - LL_ERR_INVD_PARAM: NULL pointer.
+ * @note DO NOT STOP XTAL32 while using it as system clock.
+ */
+int32_t CLK_Xtal32Init(const stc_clock_xtal32_init_t *pstcXtal32Init)
+{
+ int32_t i32Ret;
+
+ if (NULL == pstcXtal32Init) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Parameters check */
+ DDL_ASSERT(IS_CLK_XTAL32_STATE(pstcXtal32Init->u8State));
+ DDL_ASSERT(IS_CLK_XTAL32_DRV_MD(pstcXtal32Init->u8Drv));
+ DDL_ASSERT(IS_CLK_XTAL32_FILT_SEL(pstcXtal32Init->u8Filter));
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ WRITE_REG8(CM_CMU->XTAL32CFGR, pstcXtal32Init->u8Drv);
+ WRITE_REG8(CM_CMU->XTAL32NFR, pstcXtal32Init->u8Filter);
+ if (CLK_XTAL32_ON == pstcXtal32Init->u8State) {
+ i32Ret = CLK_Xtal32Cmd(ENABLE);
+ } else {
+ i32Ret = CLK_Xtal32Cmd(DISABLE);
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief XTAL32 function enable/disable.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval int32_t:
+ * - LL_OK: XTAL32 operate successfully
+ * - LL_ERR_BUSY: XTAL32 is the system clock, CANNOT stop it.
+ * @note DO NOT STOP XTAL32 while using it as system clock.
+ */
+int32_t CLK_Xtal32Cmd(en_functional_state_t enNewState)
+{
+ int32_t i32Ret = LL_OK;
+
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ if (DISABLE == enNewState) {
+ if (CLK_SYSCLK_SRC_XTAL32 == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) {
+ i32Ret = LL_ERR_BUSY;
+ } else {
+ WRITE_REG8(CM_CMU->XTAL32CR, CLK_XTAL32_OFF);
+ }
+ } else {
+ WRITE_REG8(CM_CMU->XTAL32CR, CLK_XTAL32_ON);
+ /* wait stable*/
+ }
+ /* wait approx. 5 * xtal32 cycle */
+ DDL_DelayUS(CLK_XTAL32_TIMEOUT);
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set PLL source clock.
+ * @param [in] u32PllSrc PLL source clock.
+ * @arg CLK_PLL_SRC_XTAL
+ * @arg CLK_PLL_SRC_HRC
+ * @retval None
+ */
+void CLK_SetPLLSrc(uint32_t u32PllSrc)
+{
+ DDL_ASSERT(IS_CLK_PLL_SRC(u32PllSrc));
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ MODIFY_REG32(PLL_SRC_REG, PLL_SRC_BIT, u32PllSrc << PLL_SRC_POS);
+}
+
+/**
+ * @brief Init PLL initial structure with default value.
+ * @param [in] pstcPLLInit specifies the Parameter of PLL.
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t CLK_PLLStructInit(stc_clock_pll_init_t *pstcPLLInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ /* Check if pointer is NULL */
+ if (NULL == pstcPLLInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Configure to default value */
+ pstcPLLInit->PLLCFGR = 0UL;
+ pstcPLLInit->PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
+ pstcPLLInit->PLLCFGR_f.PLLM = CLK_PLLM_DEFAULT;
+ pstcPLLInit->PLLCFGR_f.PLLN = CLK_PLLN_DEFAULT;
+ pstcPLLInit->PLLCFGR_f.PLLP = CLK_PLLP_DEFAULT;
+ pstcPLLInit->PLLCFGR_f.PLLQ = CLK_PLLQ_DEFAULT;
+ pstcPLLInit->PLLCFGR_f.PLLR = CLK_PLLR_DEFAULT;
+ pstcPLLInit->u8PLLState = CLK_PLL_OFF;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief PLL initialize.
+ * @param [in] pstcPLLInit specifies the structure of PLLH initial config.
+ * @arg u8PLLState : The new state of the PLLH.
+ * @arg PLLCFGR : PLLH config.
+ * @retval int32_t:
+ * - LL_OK: PLLH initial successfully
+ * - LL_ERR_TIMEOUT: PLLH initial timeout
+ * - LL_ERR_BUSY: PLLH is the source clock, CANNOT stop it.
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ * @note The pll_input/PLLM (VCOIN) must between 8 ~ 24MHz.
+ * The VCOIN*PLLN (VCOOUT) is between 600 ~ 1200MHz.
+ * The PLLH frequency (VCOOUT/PLLHP_Q_R) is between 40 ~ 240MHz.
+ */
+int32_t CLK_PLLInit(const stc_clock_pll_init_t *pstcPLLInit)
+{
+ int32_t i32Ret;
+#ifdef __DEBUG
+ uint32_t vcoIn;
+ uint32_t vcoOut;
+#endif
+
+ if (NULL == pstcPLLInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ DDL_ASSERT(IS_CLK_PLL_SRC(pstcPLLInit->PLLCFGR_f.PLLSRC));
+ DDL_ASSERT(IS_CLK_PLLM_DIV(pstcPLLInit->PLLCFGR_f.PLLM + 1UL));
+ DDL_ASSERT(IS_CLK_PLLN_MULTI(pstcPLLInit->PLLCFGR_f.PLLN + 1UL));
+ DDL_ASSERT(IS_CLK_PLLP_DIV(pstcPLLInit->PLLCFGR_f.PLLP + 1UL));
+#ifdef __DEBUG
+ vcoIn = ((CLK_PLL_SRC_XTAL == pstcPLLInit->PLLCFGR_f.PLLSRC ?
+ XTAL_VALUE : HRC_VALUE) / (pstcPLLInit->PLLCFGR_f.PLLM + 1UL));
+ vcoOut = vcoIn * (pstcPLLInit->PLLCFGR_f.PLLN + 1UL);
+ DDL_ASSERT(IS_CLK_PLL_VCO_IN(vcoIn));
+ DDL_ASSERT(IS_CLK_PLL_VCO_OUT(vcoOut));
+ DDL_ASSERT(IS_CLK_PLL_FREQ(vcoOut / (pstcPLLInit->PLLCFGR_f.PLLP + 1UL)));
+ DDL_ASSERT(IS_CLK_PLLQ_DIV(pstcPLLInit->PLLCFGR_f.PLLQ + 1UL));
+ DDL_ASSERT(IS_CLK_PLLR_DIV(pstcPLLInit->PLLCFGR_f.PLLR + 1UL));
+ DDL_ASSERT(IS_CLK_PLL_FREQ(vcoOut / (pstcPLLInit->PLLCFGR_f.PLLR + 1UL)));
+ DDL_ASSERT(IS_CLK_PLL_FREQ(vcoOut / (pstcPLLInit->PLLCFGR_f.PLLQ + 1UL)));
+#endif /* __DEBUG */
+ DDL_ASSERT(IS_CLK_PLL_STATE(pstcPLLInit->u8PLLState));
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ /* set PLL source in advance */
+ MODIFY_REG32(PLL_SRC_REG, PLL_SRC_BIT, pstcPLLInit->PLLCFGR_f.PLLSRC << PLL_SRC_POS);
+ WRITE_REG32(CM_CMU->PLLHCFGR, pstcPLLInit->PLLCFGR);
+ if (CLK_PLL_ON == pstcPLLInit->u8PLLState) {
+ i32Ret = CLK_PLLCmd(ENABLE);
+ } else {
+ i32Ret = CLK_PLLCmd(DISABLE);
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief PLL function enable/disable.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval int32_t:
+ * - LL_OK: PLL operate successfully
+ * - LL_ERR_BUSY: PLL is the system clock, CANNOT stop it.
+ * - LL_ERR_TIMEOUT: PLL operate timeout
+ * @note DO NOT STOP PLL while using it as system clock.
+ */
+int32_t CLK_PLLCmd(en_functional_state_t enNewState)
+{
+ int32_t i32Ret = LL_OK;
+
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ if (DISABLE == enNewState) {
+ if (CLK_SYSCLK_SRC_PLL == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) {
+ i32Ret = LL_ERR_BUSY;
+ } else {
+ WRITE_REG8(PLL_EN_REG, CLK_PLL_OFF);
+ }
+ } else {
+ if (CLK_PLL_SRC_XTAL == PLL_SRC) {
+ i32Ret = CLK_WaitStable(CLK_STB_FLAG_XTAL, CLK_TIMEOUT);
+ } else {
+ i32Ret = CLK_WaitStable(CLK_STB_FLAG_HRC, CLK_TIMEOUT);
+ }
+ if (LL_OK == i32Ret) {
+ WRITE_REG8(PLL_EN_REG, CLK_PLL_ON);
+ i32Ret = CLK_WaitStable(CLK_STB_FLAG_PLL, CLK_TIMEOUT);
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Selects the clock source to output on MCO pin.
+ * @param [in] u8Ch Specifies the MCO channel. @ref CLK_MCO_Channel_Sel
+ * @param [in] u8Src Specifies the clock source to output. @ref CLK_MCO_Clock_Source
+ * @param [in] u8Div Specifies the MCOx prescaler. @ref CLK_MCO_Clock_Prescaler
+ * @retval None
+ * @note MCO pin should be configured in alternate function 1 mode.
+ */
+void CLK_MCOConfig(uint8_t u8Ch, uint8_t u8Src, uint8_t u8Div)
+{
+ __IO uint8_t *MCOCFGRx;
+
+ /* Check the parameters. */
+ DDL_ASSERT(IS_CLK_MCO_SRC(u8Src));
+ DDL_ASSERT(IS_CLK_MCO_DIV(u8Div));
+ DDL_ASSERT(IS_CLK_MCO_CH(u8Ch));
+ /* enable register write. */
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ MCOCFGRx = &(*(__IO uint8_t *)((uint32_t)&CM_CMU->MCO1CFGR + u8Ch));
+ /* Config the MCO */
+ MODIFY_REG8(*MCOCFGRx, (CMU_MCOCFGR_MCOSEL | CMU_MCOCFGR_MCODIV), (u8Src | u8Div));
+}
+
+/**
+ * @brief Enable or disable the MCO1 output.
+ * @param [in] u8Ch Specifies the MCO channel. @ref CLK_MCO_Channel_Sel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void CLK_MCOCmd(uint8_t u8Ch, en_functional_state_t enNewState)
+{
+ __IO uint8_t *MCOCFGRx;
+
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+ DDL_ASSERT(IS_CLK_MCO_CH(u8Ch));
+
+ MCOCFGRx = &(*(__IO uint8_t *)((uint32_t)&CM_CMU->MCO1CFGR + u8Ch));
+ /* Enable or disable clock output. */
+ MODIFY_REG8(*MCOCFGRx, CMU_MCOCFGR_MCOEN, (uint8_t)enNewState << CMU_MCOCFGR_MCOEN_POS);
+}
+
+/**
+ * @brief PLL/XTAL/HRC stable flag read.
+ * @param [in] u8Flag specifies the stable flag to be read. @ref CLK_STB_Flag
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t CLK_GetStableStatus(uint8_t u8Flag)
+{
+ DDL_ASSERT(IS_CLK_STB_FLAG(u8Flag));
+
+ return ((0x00U != READ_REG8_BIT(CM_CMU->OSCSTBSR, u8Flag)) ? SET : RESET);
+}
+
+/**
+ * @brief Set the system clock source.
+ * @param [in] u8Src specifies the source of system clock. @ref CLK_System_Clock_Source
+ * @retval None
+ */
+void CLK_SetSysClockSrc(uint8_t u8Src)
+{
+ /* Set system clock source */
+ SetSysClockSrc(u8Src);
+ /* Update system clock */
+ SystemCoreClockUpdate();
+}
+
+/**
+ * @brief Get bus clock frequency.
+ * @param [out] pstcClockFreq specifies the pointer to get bus frequency.
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t CLK_GetClockFreq(stc_clock_freq_t *pstcClockFreq)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcClockFreq) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ GetClockFreq(pstcClockFreq);
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Get bus clock frequency.
+ * @param [in] u32Clock specifies the bus clock to get frequency. @ref CLK_Bus_Clock_Sel
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+uint32_t CLK_GetBusClockFreq(uint32_t u32Clock)
+{
+ uint32_t u32ClockFreq;
+ DDL_ASSERT(IS_CLK_BUS_CLK(u32Clock));
+
+ switch (u32Clock) {
+ case CLK_BUS_HCLK:
+ u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS);
+ break;
+ case CLK_BUS_PCLK1:
+ u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS);
+ break;
+ case CLK_BUS_PCLK4:
+ u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK4S) >> CMU_SCFGR_PCLK4S_POS);
+ break;
+ case CLK_BUS_PCLK3:
+ u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK3S) >> CMU_SCFGR_PCLK3S_POS);
+ break;
+ case CLK_BUS_EXCLK:
+ u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_EXCKS) >> CMU_SCFGR_EXCKS_POS);
+ break;
+ case CLK_BUS_PCLK0:
+ u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK0S) >> CMU_SCFGR_PCLK0S_POS);
+ break;
+ case CLK_BUS_PCLK2:
+ u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK2S) >> CMU_SCFGR_PCLK2S_POS);
+ break;
+ default:
+ u32ClockFreq = SystemCoreClock;
+ break;
+ }
+ return u32ClockFreq;
+}
+
+/**
+ * @brief Get PLL clock frequency.
+ * @param [out] pstcPllClkFreq specifies the pointer to get PLL frequency.
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t CLK_GetPLLClockFreq(stc_pll_clock_freq_t *pstcPllClkFreq)
+{
+ int32_t i32Ret = LL_OK;
+ uint32_t pllin;
+ uint32_t plln;
+ uint32_t pllm;
+ uint32_t pllp;
+ uint32_t pllq;
+ uint32_t pllr;
+
+ if (NULL == pstcPllClkFreq) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ pllp = (uint32_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHP) >> CMU_PLLHCFGR_PLLHP_POS);
+ pllq = (uint32_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHQ) >> CMU_PLLHCFGR_PLLHQ_POS);
+ pllr = (uint32_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHR) >> CMU_PLLHCFGR_PLLHR_POS);
+ plln = (uint32_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHN) >> CMU_PLLHCFGR_PLLHN_POS);
+ pllm = (uint32_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHM) >> CMU_PLLHCFGR_PLLHM_POS);
+
+ /* PLLHP is used as system clock. */
+ if (CLK_PLL_SRC_XTAL == PLL_SRC) {
+ pllin = XTAL_VALUE;
+ } else {
+ pllin = HRC_VALUE;
+ }
+ pstcPllClkFreq->u32PllVcin = (pllin / (pllm + 1UL));
+ pstcPllClkFreq->u32PllVco = ((pllin / (pllm + 1UL)) * (plln + 1UL));
+ pstcPllClkFreq->u32PllP = ((pllin / (pllm + 1UL)) * (plln + 1UL)) / (pllp + 1UL);
+ pstcPllClkFreq->u32PllQ = ((pllin / (pllm + 1UL)) * (plln + 1UL)) / (pllq + 1UL);
+ pstcPllClkFreq->u32PllR = ((pllin / (pllm + 1UL)) * (plln + 1UL)) / (pllr + 1UL);
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief HCLK/PCLK divide setting.
+ * @param [in] u32Clock specifies the clock to be divided. @ref CLK_Bus_Clock_Sel
+ * @param [in] u32Div specifies the clock divide factor. @ref CLK_Clock_Divider
+ * @retval None
+ * @note u32Div could choose CLK_HCLK_Divider, CLK_PCLK0_Divider, CLK_PCLK1_Divider,
+ * CLK_PCLK2_Divider, CLK_PCLK3_Divider, CLK_PCLK4_Divider, CLK_EXCLK_Divider, according to the MCU
+ */
+void CLK_SetClockDiv(uint32_t u32Clock, uint32_t u32Div)
+{
+ /* Set clock divider */
+ SetSysClockDiv(u32Clock, u32Div);
+ /* Update system clock */
+ SystemCoreClockUpdate();
+}
+
+/**
+ * @brief Set peripheral clock source.
+ * @param [in] u16Src specifies the peripheral clock source. @ref CLK_PERIPH_Sel
+ * @retval None
+ */
+void CLK_SetPeriClockSrc(uint16_t u16Src)
+{
+ DDL_ASSERT(IS_CLK_PERIPHCLK_SRC(u16Src));
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+
+ WRITE_REG8(CM_CMU->PERICKSEL, u16Src);
+}
+
+/**
+ * @brief USB clock source config.
+ * @param [in] u8Src specifies the USB clock source. @ref CLK_USBCLK_Sel
+ * @retval None
+ */
+void CLK_SetUSBClockSrc(uint8_t u8Src)
+{
+ DDL_ASSERT(IS_CLK_USBCLK_SRC(u8Src));
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ WRITE_REG8(CM_CMU->USBCKCFGR, u8Src);
+
+ DDL_DelayUS(CLK_SYSCLK_SW_STB);
+}
+
+/**
+ * @brief CAN clock source config.
+ * @param [in] u8Unit specifies the CAN channel for clock source. @ref CLK_CAN_Sel
+ * @param [in] u8Src specifies the CAN clock source. @ref CLK_CANCLK_Sel
+ * @retval None
+ */
+void CLK_SetCANClockSrc(uint8_t u8Unit, uint8_t u8Src)
+{
+ uint32_t u32UnitPos = 0UL;
+
+ DDL_ASSERT(IS_CLK_CAN_UNIT(u8Unit));
+ DDL_ASSERT(IS_CLK_CANCLK(u8Src));
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ while (0UL != u8Unit) {
+ if (0UL != (u8Unit & 0x1UL)) {
+ MODIFY_REG16(CM_CMU->CANCKCFGR, (uint32_t)CMU_CANCKCFGR_CAN1CKS << u32UnitPos, (uint32_t)u8Src << u32UnitPos);
+ }
+ u8Unit >>= 1UL;
+ u32UnitPos += 4U;
+ }
+}
+
+/**
+ * @brief Enable or disable the TPIU clock.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void CLK_TpiuClockCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ MODIFY_REG8(CM_CMU->TPIUCKCFGR, CMU_TPIUCKCFGR_TPIUCKOE, (uint8_t)enNewState << CMU_TPIUCKCFGR_TPIUCKOE_POS);
+}
+
+/**
+ * @brief TPIU clock divider config.
+ * @param [in] u8Div specifies the TPIU clock divide factor. @ref CLK_TPIU_Divider
+ * @arg CLK_TPIUCLK_DIV1: TPIU clock no divide
+ * @arg CLK_TPIUCLK_DIV2: TPIU clock divide by 2
+ * @arg CLK_TPIUCLK_DIV4: TPIU clock divide by 4
+ * @retval None
+ */
+void CLK_SetTpiuClockDiv(uint8_t u8Div)
+{
+ DDL_ASSERT(IS_CLK_TPIUCLK_DIV(u8Div));
+ DDL_ASSERT(IS_CLK_UNLOCKED());
+
+ MODIFY_REG8(CM_CMU->TPIUCKCFGR, CMU_TPIUCKCFGR_TPIUCKS, u8Div);
+}
+/**
+ * @}
+ */
+
+#endif /* LL_CLK_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_cmp.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_cmp.c
new file mode 100644
index 0000000000..4238498f47
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_cmp.c
@@ -0,0 +1,852 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_cmp.c
+ * @brief This file provides firmware functions to manage the Comparator(CMP).
+ *
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Modify typo
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_cmp.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_CMP CMP
+ * @brief CMP Driver Library
+ * @{
+ */
+
+#if (LL_CMP_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup CMP_Local_Macros CMP Local Macros
+ * @{
+ */
+
+/**
+ * @defgroup CMP_Check_Parameters_Validity CMP Check Parameters Validity
+ * @{
+ */
+#define IS_CMP_UNIT(x) \
+( ((x) == CM_CMP1) || \
+ ((x) == CM_CMP2) || \
+ ((x) == CM_CMP3) || \
+ ((x) == CM_CMP4))
+
+#define IS_CMP_WIN_MD_UNIT(x) \
+( ((x) == CMP_WIN_CMP12) || \
+ ((x) == CMP_WIN_CMP34))
+
+#define IS_CMP_POSITIVE_IN(x) \
+( ((x) == CMP_POSITIVE_NONE) || \
+ ((x) == CMP_POSITIVE_INP1) || \
+ ((x) == CMP_POSITIVE_INP2) || \
+ ((x) == CMP_POSITIVE_INP3) || \
+ ((x) == CMP_POSITIVE_INP4))
+
+#define IS_CMP_NEGATIVE_IN(x) \
+( ((x) == CMP_NEGATIVE_NONE) || \
+ ((x) == CMP_NEGATIVE_INM1) || \
+ ((x) == CMP_NEGATIVE_INM2) || \
+ ((x) == CMP_NEGATIVE_INM3) || \
+ ((x) == CMP_NEGATIVE_INM4) || \
+ ((x) == CMP_NEGATIVE_INM5) || \
+ ((x) == CMP_NEGATIVE_INM6) || \
+ ((x) == CMP_NEGATIVE_INM7) || \
+ ((x) == CMP_NEGATIVE_INM8) || \
+ ((x) == CMP_NEGATIVE_INM9) || \
+ ((x) == CMP_NEGATIVE_INM10))
+
+#define IS_CMP_WIN_LOW_IN(x) \
+( ((x) == CMP_WIN_LOW_NONE) || \
+ ((x) == CMP_WIN_LOW_INM1) || \
+ ((x) == CMP_WIN_LOW_INM2) || \
+ ((x) == CMP_WIN_LOW_INM3) || \
+ ((x) == CMP_WIN_LOW_INM4) || \
+ ((x) == CMP_WIN_LOW_INM5) || \
+ ((x) == CMP_WIN_LOW_INM6) || \
+ ((x) == CMP_WIN_LOW_INM7) || \
+ ((x) == CMP_WIN_LOW_INM8) || \
+ ((x) == CMP_WIN_LOW_INM9) || \
+ ((x) == CMP_WIN_LOW_INM10))
+
+#define IS_CMP_WIN_HIGH_IN(x) \
+( ((x) == CMP_WIN_HIGH_NONE) || \
+ ((x) == CMP_WIN_HIGH_INM1) || \
+ ((x) == CMP_WIN_HIGH_INM2) || \
+ ((x) == CMP_WIN_HIGH_INM3) || \
+ ((x) == CMP_WIN_HIGH_INM4) || \
+ ((x) == CMP_WIN_HIGH_INM5) || \
+ ((x) == CMP_WIN_HIGH_INM6) || \
+ ((x) == CMP_WIN_HIGH_INM7) || \
+ ((x) == CMP_WIN_HIGH_INM8) || \
+ ((x) == CMP_WIN_HIGH_INM9) || \
+ ((x) == CMP_WIN_HIGH_INM10))
+
+#define IS_CMP_WIN_POSITIVE_IN(x) \
+( ((x) == CMP_WIN_POSITIVE_NONE) || \
+ ((x) == CMP_WIN_POSITIVE_INP1) || \
+ ((x) == CMP_WIN_POSITIVE_INP2) || \
+ ((x) == CMP_WIN_POSITIVE_INP3) || \
+ ((x) == CMP_WIN_POSITIVE_INP4))
+
+#define IS_CMP_HYST_VOLT(x) \
+( ((x) == CMP_HYST_VOLT_NONE) || \
+ ((x) == CMP_HYST_VOLT_10MV) || \
+ ((x) == CMP_HYST_VOLT_20MV) || \
+ ((x) == CMP_HYST_VOLT_30MV) || \
+ ((x) == CMP_HYST_VOLT_40MV) || \
+ ((x) == CMP_HYST_VOLT_50MV) || \
+ ((x) == CMP_HYST_VOLT_60MV) || \
+ ((x) == CMP_HYST_VOLT_70MV))
+
+#define IS_CMP_OUT_POLARITY(x) \
+( ((x) == CMP_OUT_INVT_OFF) || \
+ ((x) == CMP_OUT_INVT_ON))
+
+#define IS_CMP_OUT_FILTER(x) \
+( ((x) == CMP_OUT_FILTER_NONE) || \
+ ((x) == CMP_OUT_FILTER_CLK) || \
+ ((x) == CMP_OUT_FILTER_CLK_DIV2) || \
+ ((x) == CMP_OUT_FILTER_CLK_DIV4) || \
+ ((x) == CMP_OUT_FILTER_CLK_DIV8) || \
+ ((x) == CMP_OUT_FILTER_CLK_DIV16) || \
+ ((x) == CMP_OUT_FILTER_CLK_DIV32) || \
+ ((x) == CMP_OUT_FILTER_CLK_DIV64))
+
+#define IS_CMP_OUT_DETECT_EDGE(x) \
+( ((x) == CMP_DETECT_EDGS_NONE) || \
+ ((x) == CMP_DETECT_EDGS_RISING) || \
+ ((x) == CMP_DETECT_EDGS_FALLING) || \
+ ((x) == CMP_DETECT_EDGS_BOTH))
+
+#define IS_CMP_OUT_DETECT_EDGE_FLAG(x) \
+( ((x) == CMP_DETECT_EDGS_RISING) || \
+ ((x) == CMP_DETECT_EDGS_FALLING) || \
+ ((x) == CMP_DETECT_EDGS_BOTH))
+
+#define IS_CMP_BLANKWIN_VALID_LVL(x) \
+( ((x) == CMP_BLANKWIN_VALID_LVL_LOW) || \
+ ((x) == CMP_BLANKWIN_VALID_LVL_HIGH))
+
+#define IS_CMP_BLANKWIN_OUT_LVL(x) \
+( ((x) == CMP_BLANKWIN_OUTPUT_LVL_LOW) || \
+ ((x) == CMP_BLANKWIN_OUTPUT_LVL_HIGH) || \
+ ((x) == CMP_BLANKWIN_OUTPUT_LVL_HOLD))
+
+#define IS_CMP_BLANKWIN_MD(x) \
+( ((x) == CMP_BLANKWIN_MD_LVL) || \
+ ((x) == CMP_BLANKWIN_MD_EDGE))
+
+#define IS_CMP_BLANKWIN_EDGE(x) \
+( ((x) == CMP_BLANKWIN_VALID_EDGE_NONE) || \
+ ((x) == CMP_BLANKWIN_VALID_EDGE_RISING) || \
+ ((x) == CMP_BLANKWIN_VALID_EDGE_FALLING) || \
+ ((x) == CMP_BLANKWIN_VALID_EDGE_ALL))
+
+#define IS_CMP_BLANKWIN_MASK_WIDTH(x) \
+( (x) <= 255U)
+
+/**
+ * @}
+ */
+
+#define CMP_MDR_CENB (CMP_MDR_CENA)
+#define CMP_MDR_CWDE (CMP_MDR_WDEN)
+#define CMP_OCR_TWOE (CMP_OCR_BWEN)
+#define CMP_OCR_TWOL (CMP_OCR_BWOL)
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup CMP_Local_Functions CMP Local Functions
+ * @{
+ */
+
+/**
+ * @brief Delay function, delay us approximately
+ * @param [in] u32Count us
+ * @retval None
+ */
+static void CMP_DelayUS(uint32_t u32Count)
+{
+ __IO uint32_t i;
+ const uint32_t u32Cyc = HCLK_VALUE / 10000000UL;
+
+ while (u32Count-- > 0UL) {
+ i = u32Cyc;
+ while (i-- > 0UL) {
+ ;
+ }
+ }
+}
+
+/**
+ * @brief Get CMP function status and disable CMP
+ * @param [in] CMPx Pointer to CMP instance register base
+ * @arg CM_CMPx
+ * @retval uint16_t The register value
+ */
+static uint16_t GetCmpFuncStatusAndDisFunc(CM_CMP_TypeDef *CMPx)
+{
+ uint16_t u16temp;
+ /* It is possible that the interrupt may occurs after CMP status switch. */
+ DDL_ASSERT(READ_REG8_BIT(CMPx->FIR, CMP_FIR_CIEN) == 0U);
+
+ /* Read CMP status */
+ u16temp = (uint16_t)(uint8_t)READ_REG8_BIT(CMPx->MDR, CMP_MDR_CENB);
+ /* Stop CMP function */
+ CLR_REG8_BIT(CMPx->MDR, CMP_MDR_CENB);
+ return u16temp;
+}
+
+/**
+ * @brief Recover CMP function status
+ * @param [in] CMPx Pointer to CMP instance register base
+ * @arg CM_CMPx
+ * @param [in] u16CmpFuncStatus CMP function status backup value
+ * @retval None
+ */
+static void RecoverCmpFuncStatus(CM_CMP_TypeDef *CMPx, uint16_t u16CmpFuncStatus)
+{
+ if (u16CmpFuncStatus != 0U) {
+ /* Recover CMP status */
+ MODIFY_REG8(CMPx->MDR, CMP_MDR_CENB, u16CmpFuncStatus);
+ /* Delay 1us */
+ CMP_DelayUS(1U);
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CMP_Global_Functions CMP Global Functions
+ * @{
+ */
+
+/**
+ * @brief Initialize structure stc_cmp_init_t variable with default value.
+ * @param [in] pstcCmpInit Pointer to a structure variable which will be initialized. @ref stc_cmp_init_t
+ * @retval int32_t
+ * - LL_OK: Success
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t CMP_StructInit(stc_cmp_init_t *pstcCmpInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ if (pstcCmpInit != NULL) {
+ pstcCmpInit->u16PositiveInput = CMP_POSITIVE_NONE;
+ pstcCmpInit->u16NegativeInput = CMP_NEGATIVE_NONE;
+ pstcCmpInit->u16OutPolarity = CMP_OUT_INVT_OFF;
+ pstcCmpInit->u16OutDetectEdge = CMP_DETECT_EDGS_NONE;
+ pstcCmpInit->u16OutFilter = CMP_OUT_FILTER_NONE;
+ pstcCmpInit->u16HystVoltage = CMP_HYST_VOLT_NONE;
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize structure stc_cmp_window_init_t variable with default value.
+ * @param [in] pstcCmpWindowInit Pointer to a structure variable. @ref stc_cmp_window_init_t
+ * @retval int32_t
+ * - LL_OK: Success
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t CMP_WindowStructInit(stc_cmp_window_init_t *pstcCmpWindowInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ if (pstcCmpWindowInit != NULL) {
+ pstcCmpWindowInit->u16PositiveInput = CMP_WIN_POSITIVE_NONE;
+ pstcCmpWindowInit->u16WinVolLow = CMP_NEGATIVE_NONE;
+ pstcCmpWindowInit->u16WinVolHigh = CMP_NEGATIVE_NONE;
+ pstcCmpWindowInit->u16OutPolarity = CMP_OUT_INVT_OFF;
+ pstcCmpWindowInit->u16OutDetectEdge = CMP_DETECT_EDGS_NONE;
+ pstcCmpWindowInit->u16OutFilter = CMP_OUT_FILTER_NONE;
+ pstcCmpWindowInit->u16HystVoltage = CMP_HYST_VOLT_NONE;
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize structure stc_cmp_blankwindow_t variable with default value.
+ * @param [in] pstcBlankWindowConfig Pointer to a structure variable. @ref stc_cmp_blankwindow_t
+ * @retval int32_t
+ * - LL_OK: Success
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t CMP_BlankWindowStructInit(stc_cmp_blankwindow_t *pstcBlankWindowConfig)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ if (pstcBlankWindowConfig != NULL) {
+ pstcBlankWindowConfig->u8Mode = CMP_BLANKWIN_MD_LVL;
+ pstcBlankWindowConfig->u16ValidLevelEdge = CMP_BLANKWIN_VALID_LVL_LOW;
+ pstcBlankWindowConfig->u16MaskWidth = 0U;
+ pstcBlankWindowConfig->u8OutLevel = CMP_BLANKWIN_OUTPUT_LVL_LOW;
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief De-initialize CMP unit
+ * @param [in] CMPx Pointer to CMP instance register base
+ * @arg CM_CMPx
+ * @retval None
+ */
+void CMP_DeInit(CM_CMP_TypeDef *CMPx)
+{
+ DDL_ASSERT(IS_CMP_UNIT(CMPx));
+
+ CLR_REG8(CMPx->MDR);
+ CLR_REG8(CMPx->FIR);
+ CLR_REG8(CMPx->OCR);
+ CLR_REG32(CMPx->PMSR);
+ CLR_REG32(CMPx->BWSR1);
+ CLR_REG16(CMPx->BWSR2);
+}
+
+/**
+ * @brief CMP normal mode initialize
+ * @param [in] CMPx Pointer to CMP instance register base
+ * @arg CM_CMPx
+ * @param [in] pstcCmpInit CMP function base parameter structure
+ * @arg pstcCmpInit->u16PositiveInput: @ref CMP_Positive_Input_Select
+ * @arg pstcCmpInit->u16NegativeInput: @ref CMP_Negative_Input_Select
+ * @arg pstcCmpInit->u16OutPolarity: @ref CMP_Out_Polarity_Select
+ * @arg pstcCmpInit->u16OutDetectEdge: @ref CMP_Out_Detect_Edge_Select
+ * @arg pstcCmpInit->u16OutFilter: @ref CMP_Out_Filter
+ * @retval int32_t
+ * - LL_OK: Success
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t CMP_NormalModeInit(CM_CMP_TypeDef *CMPx, const stc_cmp_init_t *pstcCmpInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ /* Check CMPx instance and configuration structure*/
+ if (NULL != pstcCmpInit) {
+ /* Check parameters */
+ DDL_ASSERT(IS_CMP_UNIT(CMPx));
+ DDL_ASSERT(IS_CMP_OUT_POLARITY(pstcCmpInit->u16OutPolarity));
+ DDL_ASSERT(IS_CMP_OUT_DETECT_EDGE(pstcCmpInit->u16OutDetectEdge));
+ DDL_ASSERT(IS_CMP_OUT_FILTER(pstcCmpInit->u16OutFilter));
+ DDL_ASSERT(IS_CMP_POSITIVE_IN(pstcCmpInit->u16PositiveInput));
+ DDL_ASSERT(IS_CMP_NEGATIVE_IN(pstcCmpInit->u16NegativeInput));
+ DDL_ASSERT(IS_CMP_HYST_VOLT(pstcCmpInit->u16HystVoltage));
+
+ /* Stop CMP compare */
+ CLR_REG8_BIT(CMPx->MDR, CMP_MDR_CENB);
+
+ /* Set voltage in */
+ WRITE_REG32(CMPx->PMSR, ((uint32_t)pstcCmpInit->u16PositiveInput << CMP_PMSR_CVSL_POS) | (uint32_t)pstcCmpInit->u16NegativeInput);
+ /* Set hysteresis voltage */
+ MODIFY_REG8(CMPx->MDR, CMP_MDR_HYST, pstcCmpInit->u16HystVoltage);
+
+ /* Delay 1us*/
+ CMP_DelayUS(1U);
+ /* Start CMP compare */
+ SET_REG8_BIT(CMPx->MDR, CMP_MDR_CENB);
+ /* Delay 1us*/
+ CMP_DelayUS(1U);
+ /* Set output filter and output detect edge and output polarity */
+ WRITE_REG8(CMPx->FIR, (pstcCmpInit->u16OutFilter | pstcCmpInit->u16OutDetectEdge));
+ WRITE_REG8(CMPx->OCR, pstcCmpInit->u16OutPolarity);
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Voltage compare function command
+ * @param [in] CMPx Pointer to CMP instance register base
+ * @arg CM_CMPx
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void CMP_FuncCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState)
+{
+ /* Check CMPx instance */
+ DDL_ASSERT(IS_CMP_UNIT(CMPx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG8_BIT(CMPx->MDR, CMP_MDR_CENB);
+ /* Delay 1us*/
+ CMP_DelayUS(1U);
+ } else {
+ CLR_REG8_BIT(CMPx->MDR, CMP_MDR_CENB);
+ }
+
+}
+
+/**
+ * @brief Voltage compare interrupt function command
+ * @param [in] CMPx Pointer to CMP instance register base
+ * @arg CM_CMPx
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void CMP_IntCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_CMP_UNIT(CMPx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG8_BIT(CMPx->FIR, CMP_FIR_CIEN);
+ } else {
+ CLR_REG8_BIT(CMPx->FIR, CMP_FIR_CIEN);
+ }
+}
+
+/**
+ * @brief Voltage compare output command
+ * @param [in] CMPx Pointer to CMP instance register base
+ * @arg CM_CMPx
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void CMP_CompareOutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_CMP_UNIT(CMPx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG8_BIT(CMPx->OCR, CMP_OCR_COEN);
+ } else {
+ CLR_REG8_BIT(CMPx->OCR, CMP_OCR_COEN);
+ }
+}
+
+/**
+ * @brief Voltage compare output port VCOUT function command
+ * @param [in] CMPx Pointer to CMP instance register base
+ * @arg CM_CMPx
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void CMP_PinVcoutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_CMP_UNIT(CMPx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG8_BIT(CMPx->OCR, CMP_OCR_CPOE);
+ } else {
+ CLR_REG8_BIT(CMPx->OCR, CMP_OCR_CPOE);
+ }
+
+}
+
+/**
+ * @brief Voltage compare result flag read
+ * @param [in] CMPx Pointer to CMP instance register base
+ * @arg CM_CMPx
+ * @retval An @ref en_flag_status_t enumeration type value.
+ * In normal mode
+ * - RESET: compare voltage < reference voltage
+ * - SET: compare voltage > reference voltage
+ * In Window mode
+ * - RESET: compare voltage < reference low voltage or compare voltage > reference high voltage
+ * - SET: reference low voltage < compare voltage < reference high voltage
+ */
+en_flag_status_t CMP_GetStatus(const CM_CMP_TypeDef *CMPx)
+{
+ en_flag_status_t enRet;
+ /* Check CMPx instance */
+ DDL_ASSERT(IS_CMP_UNIT(CMPx));
+ enRet = (READ_REG8_BIT(CMPx->OMR, CMP_OMR_CMON) != 0U) ? SET : RESET;
+ return enRet;
+}
+
+/**
+ * @brief Set output detect edge
+ * @param [in] CMPx Pointer to CMP instance register base
+ * @arg CM_CMPx
+ * @param [in] u8CmpEdges CMP output detect edge selection. @ref CMP_Out_Detect_Edge_Select
+ * @retval None
+ */
+void CMP_SetOutDetectEdge(CM_CMP_TypeDef *CMPx, uint8_t u8CmpEdges)
+{
+ uint16_t u16temp;
+ /* Check parameters */
+ DDL_ASSERT(IS_CMP_UNIT(CMPx));
+ DDL_ASSERT(IS_CMP_OUT_DETECT_EDGE(u8CmpEdges));
+ /* Read CMP status */
+ u16temp = GetCmpFuncStatusAndDisFunc(CMPx);
+
+ /* CMP output detect edge selection */
+ MODIFY_REG8(CMPx->FIR, CMP_FIR_EDGS, u8CmpEdges);
+ /* Recover CMP function */
+ RecoverCmpFuncStatus(CMPx, u16temp);
+}
+
+/**
+ * @brief Set output filter
+ * @param [in] CMPx Pointer to CMP instance register base
+ * @arg CM_CMPx
+ * @param [in] u8CmpFilter CMP output filter selection. @ref CMP_Out_Filter
+ * @retval None
+ */
+void CMP_SetOutFilter(CM_CMP_TypeDef *CMPx, uint8_t u8CmpFilter)
+{
+ uint16_t u16temp;
+ /* Check parameters */
+ DDL_ASSERT(IS_CMP_UNIT(CMPx));
+ DDL_ASSERT(IS_CMP_OUT_FILTER(u8CmpFilter));
+ /* Read CMP status */
+ u16temp = GetCmpFuncStatusAndDisFunc(CMPx);
+ /* CMP output filter selection */
+ MODIFY_REG8(CMPx->FIR, CMP_FIR_FCKS, u8CmpFilter);
+ /* Recover CMP function */
+ RecoverCmpFuncStatus(CMPx, u16temp);
+}
+
+/**
+ * @brief Clear output detect edge flag
+ * @param [in] CMPx Pointer to CMP instance register base
+ * @arg CM_CMPx
+ * @param [in] u8CmpEdges CMP output detect edge selection.
+ * @arg CMP_DETECT_EDGS_RISING
+ * @arg CMP_DETECT_EDGS_FALLING
+ * @arg CMP_DETECT_EDGS_BOTH
+ * @retval None
+ */
+void CMP_ClearOutDetectFlag(CM_CMP_TypeDef *CMPx, uint8_t u8CmpEdges)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_CMP_UNIT(CMPx));
+ DDL_ASSERT(IS_CMP_OUT_DETECT_EDGE_FLAG(u8CmpEdges));
+ MODIFY_REG8(CMPx->FIR, CMP_FIR_CFF | CMP_FIR_CRF, u8CmpEdges << (CMP_FIR_CFF_POS - CMP_FIR_EDGS_POS));
+}
+
+/**
+ * @brief Get output detect edge flags
+ * @param [in] CMPx Pointer to CMP instance register base
+ * @arg CM_CMPx
+ * @param [in] u8CmpEdges CMP output detect edge selection.
+ * @arg CMP_DETECT_EDGS_RISING
+ * @arg CMP_DETECT_EDGS_FALLING
+ * @arg CMP_DETECT_EDGS_BOTH
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t CMP_GetOutDetectFlag(const CM_CMP_TypeDef *CMPx, uint8_t u8CmpEdges)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_CMP_UNIT(CMPx));
+ DDL_ASSERT(IS_CMP_OUT_DETECT_EDGE_FLAG(u8CmpEdges));
+ return ((0U != READ_REG8_BIT(CMPx->FIR, u8CmpEdges << (CMP_FIR_CFF_POS - CMP_FIR_EDGS_POS))) ? SET : RESET);
+}
+
+/**
+ * @brief Set output polarity
+ * @param [in] CMPx Pointer to CMP instance register base
+ * @arg CM_CMPx
+ * @param [in] u16CmpPolarity CMP output polarity selection. @ref CMP_Out_Polarity_Select
+ * @retval None
+ */
+void CMP_SetOutPolarity(CM_CMP_TypeDef *CMPx, uint16_t u16CmpPolarity)
+{
+ uint16_t u16temp;
+ /* Check parameters */
+ DDL_ASSERT(IS_CMP_UNIT(CMPx));
+ DDL_ASSERT(IS_CMP_OUT_POLARITY(u16CmpPolarity));
+ /* Read CMP status */
+ u16temp = GetCmpFuncStatusAndDisFunc(CMPx);
+
+ /* CMP output polarity selection */
+ MODIFY_REG8(CMPx->OCR, CMP_OCR_COPS, u16CmpPolarity);
+ /* Recover CMP function */
+ RecoverCmpFuncStatus(CMPx, u16temp);
+}
+
+/**
+ * @brief Set positive in(compare voltage)
+ * @param [in] CMPx Pointer to CMP instance register base
+ * @arg CM_CMPx
+ * @param [in] u16PositiveInput @ref CMP_Positive_Input_Select
+ * @retval None
+ */
+void CMP_SetPositiveInput(CM_CMP_TypeDef *CMPx, uint16_t u16PositiveInput)
+{
+ uint16_t u16temp;
+ /* Check parameters */
+ DDL_ASSERT(IS_CMP_UNIT(CMPx));
+ DDL_ASSERT(IS_CMP_POSITIVE_IN(u16PositiveInput));
+
+ /* Read CMP status */
+ u16temp = GetCmpFuncStatusAndDisFunc(CMPx);
+
+ /* Set voltage in */
+ MODIFY_REG32(CMPx->PMSR, CMP_PMSR_CVSL, (uint32_t)u16PositiveInput << CMP_PMSR_CVSL_POS);
+
+ /* Recover CMP function */
+ RecoverCmpFuncStatus(CMPx, u16temp);
+}
+
+/**
+ * @brief Set negative in(reference voltage)
+ * @param [in] CMPx Pointer to CMP instance register base
+ * @arg CM_CMPx
+ * @param [in] u16NegativeInput @ref CMP_Negative_Input_Select
+ * @retval None
+ */
+void CMP_SetNegativeInput(CM_CMP_TypeDef *CMPx, uint16_t u16NegativeInput)
+{
+ uint16_t u16temp;
+ /* Check parameters */
+ DDL_ASSERT(IS_CMP_UNIT(CMPx));
+ DDL_ASSERT(IS_CMP_NEGATIVE_IN(u16NegativeInput));
+ /* Read CMP status */
+ u16temp = GetCmpFuncStatusAndDisFunc(CMPx);
+
+ /* Set voltage in */
+ MODIFY_REG32(CMPx->PMSR, CMP_PMSR_RVSL, u16NegativeInput);
+
+ /* Recover CMP function */
+ RecoverCmpFuncStatus(CMPx, u16temp);
+}
+
+/**
+ * @brief Set CMP hysteresis voltage
+ * @param [in] CMPx Pointer to CMP instance register base
+ * @arg CM_CMPx
+ * @param [in] u16HystVoltage @ref CMP_Hyst_Voltage
+ * @retval None
+ */
+void CMP_SetHystVoltage(CM_CMP_TypeDef *CMPx, uint16_t u16HystVoltage)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_CMP_UNIT(CMPx));
+ DDL_ASSERT(IS_CMP_HYST_VOLT(u16HystVoltage));
+
+ MODIFY_REG8(CMPx->MDR, CMP_MDR_HYST, u16HystVoltage);
+}
+
+/**
+ * @brief CMP window mode initialize
+ * @param [in] u8WinCMPx @ref CMP_Window_Mode_Unit
+ * @param [in] pstcCmpWindowInit CMP function base parameter structure @ref stc_cmp_window_init_t
+ * @retval int32_t
+ * - LL_OK: Success
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t CMP_WindowModeInit(uint8_t u8WinCMPx, const stc_cmp_window_init_t *pstcCmpWindowInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ /* Check configuration structure */
+ if (NULL != pstcCmpWindowInit) {
+ /* Check parameters */
+ DDL_ASSERT(IS_CMP_WIN_MD_UNIT(u8WinCMPx));
+ DDL_ASSERT(IS_CMP_OUT_POLARITY(pstcCmpWindowInit->u16OutPolarity));
+ DDL_ASSERT(IS_CMP_OUT_DETECT_EDGE(pstcCmpWindowInit->u16OutDetectEdge));
+ DDL_ASSERT(IS_CMP_OUT_FILTER(pstcCmpWindowInit->u16OutFilter));
+ DDL_ASSERT(IS_CMP_WIN_LOW_IN(pstcCmpWindowInit->u16WinVolLow));
+ DDL_ASSERT(IS_CMP_WIN_HIGH_IN(pstcCmpWindowInit->u16WinVolHigh));
+ DDL_ASSERT(IS_CMP_WIN_POSITIVE_IN(pstcCmpWindowInit->u16PositiveInput));
+ DDL_ASSERT(IS_CMP_HYST_VOLT(pstcCmpWindowInit->u16HystVoltage));
+
+ CM_CMP_TypeDef *pCMP_MAIN;
+ CM_CMP_TypeDef *pCMP_MINOR;
+
+ if (u8WinCMPx == CMP_WIN_CMP12) {
+ pCMP_MAIN = CM_CMP2;
+ pCMP_MINOR = CM_CMP1;
+ } else {
+ pCMP_MAIN = CM_CMP4;
+ pCMP_MINOR = CM_CMP3;
+ }
+ /* Stop CMP compare */
+ CLR_REG8_BIT(pCMP_MINOR->MDR, CMP_MDR_CENB);
+ CLR_REG8_BIT(pCMP_MAIN->MDR, CMP_MDR_CENB);
+
+ /* Set positive in(compare voltage), window voltage */
+ WRITE_REG32(pCMP_MINOR->PMSR,
+ ((uint32_t)pstcCmpWindowInit->u16PositiveInput << CMP_PMSR_CVSL_POS)
+ | (uint32_t)pstcCmpWindowInit->u16WinVolLow);
+ WRITE_REG32(pCMP_MAIN->PMSR,
+ ((uint32_t)pstcCmpWindowInit->u16PositiveInput << CMP_PMSR_CVSL_POS)
+ | (uint32_t)pstcCmpWindowInit->u16WinVolHigh);
+ /* Set hysteresis voltage */
+ MODIFY_REG8(pCMP_MAIN->MDR, CMP_MDR_HYST, pstcCmpWindowInit->u16HystVoltage);
+ /* Select window compare mode */
+ SET_REG8_BIT(pCMP_MAIN->MDR, CMP_MDR_CWDE);
+ /* Start CMP compare function */
+ SET_REG8_BIT(pCMP_MINOR->MDR, CMP_MDR_CENB);
+ SET_REG8_BIT(pCMP_MAIN->MDR, CMP_MDR_CENB);
+ /* Delay 1us*/
+ CMP_DelayUS(1U);
+ /* Set output filter and output detect edge and output polarity */
+ WRITE_REG8(pCMP_MAIN->FIR, pstcCmpWindowInit->u16OutFilter | pstcCmpWindowInit->u16OutDetectEdge);
+ WRITE_REG8(pCMP_MAIN->OCR, pstcCmpWindowInit->u16OutPolarity);
+
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Blank window function disable specified window source
+ * @param [in] CMPx Pointer to CMP instance register base
+ * @arg CM_CMPx
+ * @param [in] u16BlankWindowSrc Blank window source. can be any combination of @ref CMP_BlankWindow_Src
+ * @retval None
+ */
+void CMP_BlankWindowSrcDisable(CM_CMP_TypeDef *CMPx, uint16_t u16BlankWindowSrc)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_CMP_UNIT(CMPx));
+
+ /* Set blank window valid level high */
+ CLR_REG32_BIT(CMPx->BWSR1, (uint32_t)u16BlankWindowSrc << CMP_BWSR1_CTWP0_POS);
+ /* Disable blank window source */
+ CLR_REG32_BIT(CMPx->BWSR1, u16BlankWindowSrc);
+}
+
+/**
+ * @brief Voltage compare blank window function configuration
+ * @param [in] CMPx Pointer to CMP instance register base
+ * @arg CM_CMPx
+ * @param [in] pstcBlankWindowConfig Configuration structure for blank window mode.
+ * @retval int32_t
+ * - LL_OK: Success
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t CMP_BlankWindowConfig(CM_CMP_TypeDef *CMPx, const stc_cmp_blankwindow_t *pstcBlankWindowConfig)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ /* Check CMPx instance and configuration structure*/
+ if (NULL != pstcBlankWindowConfig) {
+ i32Ret = LL_OK;
+ /* Check parameters */
+ DDL_ASSERT(IS_CMP_UNIT(CMPx));
+ DDL_ASSERT(IS_CMP_BLANKWIN_MD(pstcBlankWindowConfig->u8Mode));
+ if (CMP_BLANKWIN_MD_LVL == pstcBlankWindowConfig->u8Mode) {
+ DDL_ASSERT(IS_CMP_BLANKWIN_VALID_LVL(pstcBlankWindowConfig->u16ValidLevelEdge));
+ } else {
+ DDL_ASSERT(IS_CMP_BLANKWIN_EDGE(pstcBlankWindowConfig->u16ValidLevelEdge));
+ DDL_ASSERT(IS_CMP_BLANKWIN_MASK_WIDTH(pstcBlankWindowConfig->u16MaskWidth));
+ }
+ DDL_ASSERT(IS_CMP_BLANKWIN_OUT_LVL(pstcBlankWindowConfig->u8OutLevel));
+
+ /* Select blank window mode and output level when blank window valid */
+ MODIFY_REG8(CMPx->OCR, CMP_OCR_TWOL | CMP_OCR_BWMD,
+ pstcBlankWindowConfig->u8OutLevel | pstcBlankWindowConfig->u8Mode);
+ if (CMP_BLANKWIN_MD_LVL == pstcBlankWindowConfig->u8Mode) {
+ /* Select blank window valid level */
+ if (CMP_BLANKWIN_VALID_LVL_LOW == pstcBlankWindowConfig->u16ValidLevelEdge) {
+ SET_REG32_BIT(CMPx->BWSR1, (uint32_t)pstcBlankWindowConfig->u16Src << CMP_BWSR1_CTWP0_POS);
+ } else {
+ CLR_REG32_BIT(CMPx->BWSR1, (uint32_t)pstcBlankWindowConfig->u16Src << CMP_BWSR1_CTWP0_POS);
+ }
+ } else {
+ WRITE_REG16(CMPx->BWSR2,
+ pstcBlankWindowConfig->u16ValidLevelEdge | pstcBlankWindowConfig->u16MaskWidth);
+ }
+ /* Select blank window source */
+ SET_REG32_BIT(CMPx->BWSR1, pstcBlankWindowConfig->u16Src);
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief CMP out blank window function command
+ * @param [in] CMPx Pointer to CMP instance register base
+ * @arg CM_CMPx
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void CMP_BlankWindowCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_CMP_UNIT(CMPx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG8_BIT(CMPx->OCR, CMP_OCR_TWOE);
+ } else {
+ CLR_REG8_BIT(CMPx->OCR, CMP_OCR_TWOE);
+ }
+}
+/**
+ * @brief CMP blank window mode set
+ * @param [in] CMPx Pointer to CMP instance register base
+ * @arg CM_CMPx
+ * @param [in] u8Mode Blank window mode @ref CMP_BlankWindow_Mode.
+ * @retval None
+ */
+void CMP_BlankWindowMode(CM_CMP_TypeDef *CMPx, uint8_t u8Mode)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_CMP_UNIT(CMPx));
+ DDL_ASSERT(IS_CMP_BLANKWIN_MD(u8Mode));
+ MODIFY_REG8(CMPx->OCR, CMP_OCR_BWMD, u8Mode);
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_CMP_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_crc.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_crc.c
new file mode 100644
index 0000000000..c2dc8ec12e
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_crc.c
@@ -0,0 +1,567 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_crc.c
+ * @brief This file provides firmware functions to manage the Cyclic Redundancy
+ * Check(CRC).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Reconstruct interface function relate to calculate CRC
+ Optimize CRC_DeInit function
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_crc.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_CRC CRC
+ * @brief Cyclic Redundancy Check Driver Library
+ * @{
+ */
+
+#if (LL_CRC_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup CRC_Local_Macros CRC Local Macros
+ * @{
+ */
+
+/**
+ * @defgroup CRC_Check_Parameters_Validity CRC Check Parameters Validity
+ * @{
+ */
+/*! Parameter validity check for CRC protocol. */
+#define IS_CRC_PROTOCOL(x) \
+( ((x) == CRC_CRC16) || \
+ ((x) == CRC_CRC32))
+
+/*! Parameter validity check for CRC data width. */
+#define IS_CRC_DATA_WIDTH(x) \
+( ((x) == CRC_DATA_WIDTH_8BIT) || \
+ ((x) == CRC_DATA_WIDTH_16BIT) || \
+ ((x) == CRC_DATA_WIDTH_32BIT))
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CRC_Registers_Reset_Value_definition CRC Registers Reset Value
+ * @{
+ */
+#define CRC_CR_RST_VALUE (0x0001UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CRC_DATA_Register_Address CRC Data Register Address
+ * @{
+ */
+#define CRC_DATA_ADDR ((uint32_t)(&CM_CRC->DAT0))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CRC_Calculate_Clock_Count CRC Calculate Clock Count
+ * @{
+ */
+#define CRC_CALC_CLK_COUNT (10UL)
+/**
+ * @}
+ */
+
+#define CRC_RMU_TIMEOUT (100U)
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup CRC_Local_Functions CRC Local Functions
+ * @{
+ */
+
+/**
+ * @brief Calculate the CRC value of a 8-bit data buffer.
+ * @param [in] au8Data Pointer to the input data buffer.
+ * @param [in] u32Len The length(counted in byte) of the data to be calculated.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_INVD_PARAM: The au8Data value is NULL or u32Len value is 0.
+ */
+static int32_t CRC_WriteData8(const uint8_t au8Data[], uint32_t u32Len)
+{
+ uint32_t i;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ const uint32_t u32DataAddr = CRC_DATA_ADDR;
+
+ if ((au8Data != NULL) && (u32Len != 0UL)) {
+ for (i = 0UL; i < u32Len; i++) {
+ RW_MEM8(u32DataAddr) = au8Data[i];
+ }
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Calculate the CRC value of a 16-bit data buffer.
+ * @param [in] au16Data Pointer to the input data buffer.
+ * @param [in] u32Len The length(counted in half-word) of the data to be calculated.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_INVD_PARAM: The au16Data value is NULL or u32Len value is 0.
+ */
+static int32_t CRC_WriteData16(const uint16_t au16Data[], uint32_t u32Len)
+{
+ uint32_t i;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ const uint32_t u32DataAddr = CRC_DATA_ADDR;
+
+ if ((au16Data != NULL) && (u32Len != 0UL)) {
+ for (i = 0UL; i < u32Len; i++) {
+ RW_MEM16(u32DataAddr) = au16Data[i];
+ }
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Calculate the CRC value of a 32-bit data buffer.
+ * @param [in] au32Data Pointer to the input data buffer.
+ * @param [in] u32Len The length(counted in word) of the data to be calculated.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_INVD_PARAM: The au32Data value is NULL or u32Len value is 0.
+ */
+static int32_t CRC_WriteData32(const uint32_t au32Data[], uint32_t u32Len)
+{
+ uint32_t i;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ const uint32_t u32DataAddr = CRC_DATA_ADDR;
+
+ if ((au32Data != NULL) && (u32Len != 0UL)) {
+ for (i = 0UL; i < u32Len; i++) {
+ RW_MEM32(u32DataAddr) = au32Data[i];
+ }
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CRC_Global_Functions CRC Global Functions
+ * @{
+ */
+
+/**
+ * @brief Set the fields of structure stc_crc_init_t to default values.
+ * @param [out] pstcCrcInit Pointer to a @ref stc_crc_init_t structure.
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcCrcInit value is NULL.
+ */
+int32_t CRC_StructInit(stc_crc_init_t *pstcCrcInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcCrcInit) {
+ pstcCrcInit->u32Protocol = CRC_CRC16;
+ pstcCrcInit->u32InitValue = CRC_INIT_VALUE_DEFAULT;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize the CRC.
+ * @param [in] pstcCrcInit Pointer to a @ref stc_crc_init_t structure.
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcCrcInit value is NULL.
+ */
+int32_t CRC_Init(const stc_crc_init_t *pstcCrcInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcCrcInit) {
+ DDL_ASSERT(IS_CRC_PROTOCOL(pstcCrcInit->u32Protocol));
+
+ MODIFY_REG32(CM_CRC->CR, CRC_CRC32, pstcCrcInit->u32Protocol);
+
+ /* Set initial value */
+ if (CRC_CRC16 == (pstcCrcInit->u32Protocol & CRC_CRC32)) {
+ WRITE_REG16(CM_CRC->RESLT, (uint16_t)pstcCrcInit->u32InitValue);
+ } else {
+ WRITE_REG32(CM_CRC->RESLT, pstcCrcInit->u32InitValue);
+ }
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief De-initialize the CRC.
+ * @param None
+ * @retval int32_t:
+ * - LL_OK: Reset success.
+ * - LL_ERR_TIMEOUT: Reset time out.
+ * @note Call LL_PERIPH_WE(LL_PERIPH_PWC_CLK_RMU) unlock RMU_FRSTx register first.
+ */
+int32_t CRC_DeInit(void)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint8_t u8TimeOut = 0U;
+
+ DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1);
+
+ /* Reset CRC */
+ WRITE_REG32(bCM_RMU->FRST0_b.CRC, 0UL);
+
+ /* Ensure reset procedure is completed */
+ while (READ_REG32(bCM_RMU->FRST0_b.CRC) != 1UL) {
+ u8TimeOut++;
+ if (u8TimeOut > CRC_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Get status of the CRC operation result.
+ * @param None
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t CRC_GetResultStatus(void)
+{
+ uint32_t u32Status;
+
+ u32Status = READ_REG32_BIT(CM_CRC->CR, CRC_CR_FLAG);
+
+ return (u32Status > 0UL) ? SET : RESET;
+}
+
+/**
+ * @brief Calculate the CRC16 value and start with the previously calculated CRC as initial value.
+ * @param [in] u8DataWidth Bit width of the data.
+ * This parameter can be one of the macros group @ref CRC_DATA_Bit_Width
+ * @arg CRC_DATA_WIDTH_8BIT: 8 Bit
+ * @arg CRC_DATA_WIDTH_16BIT: 16 Bit
+ * @arg CRC_DATA_WIDTH_32BIT: 32 Bit
+ * @param [in] pvData Pointer to the buffer containing the data to be calculated.
+ * @param [in] u32Len The length(counted in bytes or half word or word, depending on
+ * the bit width) of the data to be calculated.
+ * @retval The CRC16 value.
+ * @note The function fetch data in byte or half word or word depending on the data bit width(the parameter u8DataWidth).
+ */
+uint16_t CRC_CRC16_AccumulateData(uint8_t u8DataWidth, const void *pvData, uint32_t u32Len)
+{
+ uint16_t u16CrcValue = 0U;
+
+ if ((pvData != NULL) && (u32Len != 0UL)) {
+ DDL_ASSERT(IS_CRC_DATA_WIDTH(u8DataWidth));
+
+ /* Write data */
+ if (CRC_DATA_WIDTH_32BIT == u8DataWidth) {
+ (void)CRC_WriteData32((const uint32_t *)pvData, u32Len);
+ } else if (CRC_DATA_WIDTH_16BIT == u8DataWidth) {
+ (void)CRC_WriteData16((const uint16_t *)pvData, u32Len);
+ } else {
+ (void)CRC_WriteData8((const uint8_t *)pvData, u32Len);
+ }
+
+ /* Get checksum */
+ u16CrcValue = (uint16_t)READ_REG16(CM_CRC->RESLT);
+ }
+
+ return u16CrcValue;
+}
+
+/**
+ * @brief Calculate the CRC32 value and start with the previously calculated CRC as initial value.
+ * @param [in] u8DataWidth Bit width of the data.
+ * This parameter can be one of the macros group @ref CRC_DATA_Bit_Width
+ * @arg CRC_DATA_WIDTH_8BIT: 8 Bit
+ * @arg CRC_DATA_WIDTH_16BIT: 16 Bit
+ * @arg CRC_DATA_WIDTH_32BIT: 32 Bit
+ * @param [in] pvData Pointer to the buffer containing the data to be calculated.
+ * @param [in] u32Len The length(counted in bytes or half word or word, depending on
+ * the bit width) of the data to be calculated.
+ * @retval The CRC32 value.
+ * @note The function fetch data in byte or half word or word depending on the data bit width(the parameter u8DataWidth).
+ */
+uint32_t CRC_CRC32_AccumulateData(uint8_t u8DataWidth, const void *pvData, uint32_t u32Len)
+{
+ uint32_t u32CrcValue = 0UL;
+
+ if ((pvData != NULL) && (u32Len != 0UL)) {
+ DDL_ASSERT(IS_CRC_DATA_WIDTH(u8DataWidth));
+
+ /* Write data */
+ if (CRC_DATA_WIDTH_32BIT == u8DataWidth) {
+ (void)CRC_WriteData32((const uint32_t *)pvData, u32Len);
+ } else if (CRC_DATA_WIDTH_16BIT == u8DataWidth) {
+ (void)CRC_WriteData16((const uint16_t *)pvData, u32Len);
+ } else {
+ (void)CRC_WriteData8((const uint8_t *)pvData, u32Len);
+ }
+
+ /* Get checksum */
+ u32CrcValue = READ_REG32(CM_CRC->RESLT);
+ }
+
+ return u32CrcValue;
+}
+
+/**
+ * @brief Calculate the CRC16 value and start with the specified initial value.
+ * @param [in] u16InitValue The CRC initialization value which is the valid bits same as
+ * the bits of CRC Protocol.
+ * @param [in] u8DataWidth Bit width of the data.
+ * This parameter can be one of the macros group @ref CRC_DATA_Bit_Width
+ * @arg CRC_DATA_WIDTH_8BIT: 8 Bit
+ * @arg CRC_DATA_WIDTH_16BIT: 16 Bit
+ * @arg CRC_DATA_WIDTH_32BIT: 32 Bit
+ * @param [in] pvData Pointer to the buffer containing the data to be computed.
+ * @param [in] u32Len The length(counted in bytes or half word or word, depending on
+ * the bit width) of the data to be computed.
+ * @retval The CRC16 value.
+ * @note The function fetch data in byte or half word or word depending on the data bit width(the parameter u8DataWidth).
+ */
+uint16_t CRC_CRC16_Calculate(uint16_t u16InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len)
+{
+ uint16_t u16CrcValue = 0U;
+
+ if ((pvData != NULL) && (u32Len != 0UL)) {
+ /* Set initial value */
+ WRITE_REG16(CM_CRC->RESLT, u16InitValue);
+
+ u16CrcValue = CRC_CRC16_AccumulateData(u8DataWidth, pvData, u32Len);
+ }
+
+ return u16CrcValue;
+}
+
+/**
+ * @brief Calculate the CRC32 value and start with the specified initial value.
+ * @param [in] u32InitValue The CRC initialization value which is the valid bits same as
+ * the bits of CRC Protocol.
+ * @param [in] u8DataWidth Bit width of the data.
+ * This parameter can be one of the macros group @ref CRC_DATA_Bit_Width
+ * @arg CRC_DATA_WIDTH_8BIT: 8 Bit
+ * @arg CRC_DATA_WIDTH_16BIT: 16 Bit
+ * @arg CRC_DATA_WIDTH_32BIT: 32 Bit
+ * @param [in] pvData Pointer to the buffer containing the data to be computed.
+ * @param [in] u32Len The length(counted in bytes or half word or word, depending on
+ * the bit width) of the data to be computed.
+ * @retval The CRC32 value.
+ * @note The function fetch data in byte or half word or word depending on the data bit width(the parameter u8DataWidth).
+ */
+uint32_t CRC_CRC32_Calculate(uint32_t u32InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len)
+{
+ uint32_t u32CrcValue = 0UL;
+
+ if ((pvData != NULL) && (u32Len != 0UL)) {
+ /* Set initial value */
+ WRITE_REG32(CM_CRC->RESLT, u32InitValue);
+
+ u32CrcValue = CRC_CRC32_AccumulateData(u8DataWidth, pvData, u32Len);
+ }
+
+ return u32CrcValue;
+}
+
+/**
+ * @brief Check the CRC16 calculating result with the expected value.
+ * @param [in] u16InitValue The CRC initialization value which is the valid bits same as
+ * the bits of CRC Protocol.
+ * @param [in] u8DataWidth Bit width of the data.
+ * This parameter can be one of the following values:
+ * @arg CRC_DATA_WIDTH_8BIT: 8 Bit
+ * @arg CRC_DATA_WIDTH_16BIT: 16 Bit
+ * @arg CRC_DATA_WIDTH_32BIT: 32 Bit
+ * @param [in] pvData Pointer to the buffer containing the data to be computed.
+ * @param [in] u32Len The length(counted in byte) of the data to be calculated.
+ * @param [in] u16ExpectValue The expected CRC value to be checked.
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t CRC_CRC16_CheckData(uint16_t u16InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len, uint16_t u16ExpectValue)
+{
+ __IO uint32_t u32Count = CRC_CALC_CLK_COUNT;
+ en_flag_status_t enStatus = RESET;
+ uint32_t u32Expect_Value = u16ExpectValue;
+
+ if ((pvData != NULL) && (u32Len != 0UL)) {
+ (void)CRC_CRC16_Calculate(u16InitValue, u8DataWidth, pvData, u32Len);
+
+ /* Writes the expected CRC value to be checked */
+ (void)CRC_WriteData16((uint16_t *)((void *)&u32Expect_Value), 1UL);
+
+ /* Delay for waiting CRC result flag */
+ while (u32Count-- != 0UL) {
+ __NOP();
+ }
+
+ enStatus = CRC_GetResultStatus();
+ }
+
+ return enStatus;
+}
+
+/**
+ * @brief Check the CRC32 calculating result with the expected value.
+ * @param [in] u32InitValue The CRC initialization value which is the valid bits same as
+ * the bits of CRC Protocol.
+ * @param [in] u8DataWidth Bit width of the data.
+ * This parameter can be one of the following values:
+ * @arg CRC_DATA_WIDTH_8BIT: 8 Bit
+ * @arg CRC_DATA_WIDTH_16BIT: 16 Bit
+ * @arg CRC_DATA_WIDTH_32BIT: 32 Bit
+ * @param [in] pvData Pointer to the buffer containing the data to be computed.
+ * @param [in] u32Len The length(counted in byte) of the data to be calculated.
+ * @param [in] u32ExpectValue The expected CRC value to be checked.
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t CRC_CRC32_CheckData(uint32_t u32InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len, uint32_t u32ExpectValue)
+{
+ __IO uint32_t u32Count = CRC_CALC_CLK_COUNT;
+ en_flag_status_t enStatus = RESET;
+ uint32_t u32Expect_Value = u32ExpectValue;
+
+ if ((pvData != NULL) && (u32Len != 0UL)) {
+ (void)CRC_CRC32_Calculate(u32InitValue, u8DataWidth, pvData, u32Len);
+
+ /* Writes the expected CRC value to be checked */
+ (void)CRC_WriteData32(&u32Expect_Value, 1UL);
+
+ /* Delay for waiting CRC result flag */
+ while (u32Count-- != 0UL) {
+ __NOP();
+ }
+
+ enStatus = CRC_GetResultStatus();
+ }
+
+ return enStatus;
+}
+
+/**
+ * @brief Get the CRC16 check result with the expected value.
+ * @param [in] u16ExpectValue The expected CRC value to be checked.
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t CRC_CRC16_GetCheckResult(uint16_t u16ExpectValue)
+{
+ __IO uint32_t u32Count = CRC_CALC_CLK_COUNT;
+ en_flag_status_t enStatus;
+ uint32_t u32Expect_Value = u16ExpectValue;
+
+ /* Writes the expected CRC value to be checked */
+ (void)CRC_WriteData16((uint16_t *)((void *)&u32Expect_Value), 1UL);
+
+ /* Delay for waiting CRC result flag */
+ while (u32Count-- != 0UL) {
+ __NOP();
+ }
+
+ enStatus = CRC_GetResultStatus();
+
+ return enStatus;
+}
+
+/**
+ * @brief Get the CRC32 check result with the expected value.
+ * @param [in] u32ExpectValue The expected CRC value to be checked.
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t CRC_CRC32_GetCheckResult(uint32_t u32ExpectValue)
+{
+ __IO uint32_t u32Count = CRC_CALC_CLK_COUNT;
+ en_flag_status_t enStatus;
+ uint32_t u32Expect_Value = u32ExpectValue;
+
+ /* Writes the expected CRC value to be checked */
+ (void)CRC_WriteData32(&u32Expect_Value, 1UL);
+
+ /* Delay for waiting CRC result flag */
+ while (u32Count-- != 0UL) {
+ __NOP();
+ }
+
+ enStatus = CRC_GetResultStatus();
+
+ return enStatus;
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_CRC_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_ctc.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_ctc.c
new file mode 100644
index 0000000000..2e289e105d
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_ctc.c
@@ -0,0 +1,525 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_ctc.c
+ * @brief This file provides firmware functions to manage the Clock Trimming
+ * Controller(CTC).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Modify typo
+ Modify CTC_DeInit() to use RMU function reset
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_ctc.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_CTC CTC
+ * @brief CTC Driver Library
+ * @{
+ */
+
+#if (LL_CTC_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup CTC_Local_Macros CTC Local Macros
+ * @{
+ */
+
+/**
+ * @defgroup CTC_Check_Parameters_Validity CTC Check Parameters Validity
+ * @{
+ */
+#define IS_CTC_REF_CLK_SRC(x) \
+( ((x) == CTC_REF_CLK_SRC_XTAL) || \
+ ((x) == CTC_REF_CLK_SRC_XTAL32) || \
+ ((x) == CTC_REF_CLK_SRC_CTCREF))
+
+#define IS_CTC_REF_CLK_DIV(x) \
+( ((x) == CTC_REF_CLK_DIV2) || \
+ ((x) == CTC_REF_CLK_DIV4) || \
+ ((x) == CTC_REF_CLK_DIV8) || \
+ ((x) == CTC_REF_CLK_DIV16) || \
+ ((x) == CTC_REF_CLK_DIV64) || \
+ ((x) == CTC_REF_CLK_DIV256) || \
+ ((x) == CTC_REF_CLK_DIV1024) || \
+ ((x) == CTC_REF_CLK_DIV4096))
+
+#define IS_CTC_OFFSET_VALUE(x) ((x) <= 0xFFUL)
+
+#define IS_CTC_RELOAD_VALUE(x) ((x) <= 0xFFFFUL)
+
+#define IS_CTC_TRIM_VALUE(x) ((x) <= 0x3FUL)
+
+#define IS_CTC_TOLERANT_ERR(x) \
+( ((x) >= 0.0F) && \
+ ((x) <= CTC_TOLERANT_ERR_MAX))
+
+#define IS_CTC_FLAG(x) \
+( ((x) != 0UL) && \
+ (((x) | CTC_FLAG_ALL) == CTC_FLAG_ALL))
+
+#define IS_CTC_HRC_CLK_DIV(x) \
+( ((x) == CTC_HRC_CLK_DIV1) || \
+ ((x) == CTC_HRC_CLK_DIV2) || \
+ ((x) == CTC_HRC_CLK_DIV4) || \
+ ((x) == CTC_HRC_CLK_DIV8) || \
+ ((x) == CTC_HRC_CLK_DIV32) || \
+ ((x) == CTC_HRC_CLK_DIV128) || \
+ ((x) == CTC_HRC_CLK_DIV512) || \
+ ((x) == CTC_HRC_CLK_DIV2048))
+
+#define IS_CTC_CTCREF_EDGE(x) \
+( ((x) == CTC_CTCREF_RISING_RISING) || \
+ ((x) == CTC_CTCREF_RISING_FALLING) || \
+ ((x) == CTC_CTCREF_FALLING_RISING) || \
+ ((x) == CTC_CTCREF_FALLING_FALLING))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CTC_Tolerant_Error_Max CTC Tolerant Error Max
+ * @{
+ */
+#define CTC_TOLERANT_ERR_MAX (1.0F)
+/**
+ * @}
+ */
+
+#define CTC_RMU_TIMEOUT (100UL)
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ * @defgroup CTC_Local_Functions CTC Local Functions
+ * @{
+ */
+
+/**
+ * @brief Get HRC clock frequency.
+ * @param None
+ * @retval HRC clock frequency.
+ */
+static uint32_t CTC_GetHrcClockFreq(void)
+{
+ return HRC_VALUE;
+}
+
+/**
+ * @brief Get reference clock division.
+ * @param [in] u32Cr1RefPsc CTC CR1 REFPSC bits value.
+ * This parameter can be between Min_Data=0 and Max_Data=7
+ * @retval Reference clock division.
+ */
+static uint32_t CTC_GetRefClockDiv(uint32_t u32Cr1RefPsc)
+{
+ uint32_t u32RefclkDiv;
+
+ if (u32Cr1RefPsc < CTC_REF_CLK_DIV64) {
+ u32RefclkDiv = (2UL << u32Cr1RefPsc);
+ } else {
+ u32RefclkDiv = (64UL << (2UL * (u32Cr1RefPsc - CTC_REF_CLK_DIV64)));
+ }
+
+ return u32RefclkDiv;
+}
+
+/**
+ * @brief Get CTC HRC clock division.
+ * @param [in] u32Cr1HrcPsc CTC CR1 REFPSC bits value.
+ * This parameter can be between Min_Data=0 and Max_Data=7
+ * @retval CTC HRC clock division.
+ */
+static uint32_t CTC_GetCtcHrcClockDiv(uint32_t u32Cr1HrcPsc)
+{
+ uint32_t u32CtcHrcDiv;
+
+ if (u32Cr1HrcPsc < CTC_HRC_CLK_DIV32) {
+ u32CtcHrcDiv = (1UL << u32Cr1HrcPsc);
+ } else {
+ u32CtcHrcDiv = (32UL << (2UL * (u32Cr1HrcPsc - CTC_HRC_CLK_DIV32)));
+ }
+
+ return u32CtcHrcDiv;
+}
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CTC_Global_Functions CTC Global Functions
+ * @{
+ */
+
+/**
+ * @brief Set the fields of structure stc_ctc_ct_init_t to default values.
+ * @param [out] pstcCtcInit Pointer to a @ref stc_ctc_ct_init_t structure.
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcCtcInit value is NULL.
+ */
+int32_t CTC_CT_StructInit(stc_ctc_ct_init_t *pstcCtcInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcCtcInit) {
+ pstcCtcInit->u32HrcClockDiv = CTC_HRC_CLK_DIV1;
+ pstcCtcInit->u32RefClockFreq = 0UL;
+ pstcCtcInit->u32RefClockSrc = CTC_REF_CLK_SRC_CTCREF;
+ pstcCtcInit->u32RefClockDiv = CTC_REF_CLK_DIV8;
+ pstcCtcInit->f32TolerantErrRate = 0.0F;
+ pstcCtcInit->u8TrimValue = 0U;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize CTC continuous trim function.
+ * @param [in] pstcCtcInit Pointer to a @ref stc_ctc_ct_init_t structure.
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_BUSY: CTC state is busy.
+ * - LL_ERR_INVD_PARAM: If one of following cases matches:
+ * - The pointer pstcCtcInit value is NULL.
+ * - Reference frequency is out of range.
+ * - Calculate reload & offset value out of range.
+ */
+int32_t CTC_CT_Init(const stc_ctc_ct_init_t *pstcCtcInit)
+{
+ float32_t f32OffsetValue;
+ uint32_t u32RegValue;
+ uint32_t u32ReloadValue;
+ uint32_t u32OffsetValue;
+ uint32_t u32RefClockDiv;
+ uint32_t u32CtcHrcFreq;
+ uint32_t u32Multiplier;
+ uint64_t u64InterClock;
+ int32_t i32Ret = LL_ERR_BUSY;
+
+ /* Check CTC status */
+ if (CTC_FLAG_BUSY != (READ_REG32_BIT(CM_CTC->STR, CTC_FLAG_BUSY))) {
+ if ((NULL == pstcCtcInit) || (0UL == pstcCtcInit->u32RefClockFreq)) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ DDL_ASSERT(IS_CTC_REF_CLK_SRC(pstcCtcInit->u32RefClockSrc));
+ DDL_ASSERT(IS_CTC_REF_CLK_DIV(pstcCtcInit->u32RefClockDiv));
+ DDL_ASSERT(IS_CTC_TRIM_VALUE(pstcCtcInit->u8TrimValue));
+ DDL_ASSERT(IS_CTC_TOLERANT_ERR(pstcCtcInit->f32TolerantErrRate));
+ DDL_ASSERT(IS_CTC_HRC_CLK_DIV(pstcCtcInit->u32HrcClockDiv));
+
+ u32CtcHrcFreq = (CTC_GetHrcClockFreq() / CTC_GetCtcHrcClockDiv(pstcCtcInit->u32HrcClockDiv));
+
+ u32RefClockDiv = CTC_GetRefClockDiv(pstcCtcInit->u32RefClockDiv);
+ u64InterClock = ((uint64_t)u32CtcHrcFreq) * ((uint64_t)(u32RefClockDiv));
+ u32Multiplier = (uint32_t)(u64InterClock / pstcCtcInit->u32RefClockFreq);
+
+ /* Calculate offset value formula: OFSVAL = (Fhrc / (Fref * Fref_division)) * TA */
+ f32OffsetValue = ((float32_t)u32Multiplier) * (pstcCtcInit->f32TolerantErrRate);
+ u32OffsetValue = (uint32_t)(f32OffsetValue);
+
+ /* Calculate reload value formula: RLDVAL = (Fhrc / (Fref * Fref_division)) + OFSVAL */
+ u32ReloadValue = u32Multiplier + u32OffsetValue;
+
+ /* Check reload and offset value */
+ if ((IS_CTC_OFFSET_VALUE(u32OffsetValue)) && (IS_CTC_RELOAD_VALUE(u32ReloadValue))) {
+ /* Set CR1 */
+ u32RegValue = (pstcCtcInit->u32RefClockDiv | pstcCtcInit->u32RefClockSrc | \
+ ((uint32_t)pstcCtcInit->u8TrimValue << CTC_CR1_TRMVAL_POS));
+ u32RegValue |= pstcCtcInit->u32HrcClockDiv;
+ WRITE_REG32(CM_CTC->CR1, u32RegValue);
+
+ /* Set CR2 */
+ u32RegValue = ((u32ReloadValue << CTC_CR2_RLDVAL_POS) | u32OffsetValue);
+ WRITE_REG32(CM_CTC->CR2, u32RegValue);
+ i32Ret = LL_OK;
+ }
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set the fields of structure stc_ctc_st_init_t to default values.
+ * @param [out] pstcCtcInit Pointer to a @ref stc_ctc_st_init_t structure.
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcCtcInit value is NULL.
+ */
+int32_t CTC_ST_StructInit(stc_ctc_st_init_t *pstcCtcInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcCtcInit) {
+ pstcCtcInit->u32HrcClockDiv = CTC_HRC_CLK_DIV1;
+ pstcCtcInit->f32CtcRefEdgeTime = 0.0F;
+ pstcCtcInit->f32TolerantErrRate = 0.0F;
+ pstcCtcInit->u32CtcRefEdge = CTC_CTCREF_RISING_RISING;
+ pstcCtcInit->u8TrimValue = 0U;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize CTC single trim function.
+ * @param [in] pstcCtcInit Pointer to a @ref stc_ctc_st_init_t structure.
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_BUSY: CTC state is busy
+ * - LL_ERR_INVD_PARAM: If one of following cases matches:
+ * - pstcCtcInit is NULL.
+ * - Reference frequency is out of range.
+ * - Calculate reload & offset value out of range
+ */
+int32_t CTC_ST_Init(const stc_ctc_st_init_t *pstcCtcInit)
+{
+ float32_t f32OffsetValue;
+ uint32_t u32RegValue;
+ uint32_t u32ReloadValue;
+ uint32_t u32OffsetValue;
+ uint32_t u32CtcHrcFreq;
+ uint32_t u32Multiplier;
+ int32_t i32Ret = LL_ERR_BUSY;
+
+ /* Check CTC status */
+ if (CTC_FLAG_BUSY != (READ_REG32_BIT(CM_CTC->STR, CTC_FLAG_BUSY))) {
+ if (NULL == pstcCtcInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ DDL_ASSERT(IS_CTC_HRC_CLK_DIV(pstcCtcInit->u32HrcClockDiv));
+ DDL_ASSERT(IS_CTC_TOLERANT_ERR(pstcCtcInit->f32TolerantErrRate));
+ DDL_ASSERT(IS_CTC_CTCREF_EDGE(pstcCtcInit->u32CtcRefEdge));
+ DDL_ASSERT(IS_CTC_TRIM_VALUE(pstcCtcInit->u8TrimValue));
+
+ /* CTC trim HRC clock frequency */
+ u32CtcHrcFreq = (CTC_GetHrcClockFreq() / CTC_GetCtcHrcClockDiv(pstcCtcInit->u32HrcClockDiv));
+
+ f32OffsetValue = ((float32_t)u32CtcHrcFreq * pstcCtcInit->f32CtcRefEdgeTime);
+ u32Multiplier = (uint32_t)(f32OffsetValue);
+
+ /* Calculate offset value formula: OFSVAL = ( Fhrc x Ttrim ) x TA */
+ f32OffsetValue = ((float32_t)u32Multiplier) * (pstcCtcInit->f32TolerantErrRate);
+ u32OffsetValue = (uint32_t)(f32OffsetValue);
+
+ /* Calculate reload value formula: RLDVAL = ( Fhrc x Ttrim ) + OFSVAL */
+ u32ReloadValue = u32Multiplier + u32OffsetValue;
+
+ /* Check reload and offset value */
+ if ((IS_CTC_OFFSET_VALUE(u32OffsetValue)) && (IS_CTC_RELOAD_VALUE(u32ReloadValue))) {
+ /* Set CR1 */
+ u32RegValue = (CTC_CR1_REFCKS_0 | pstcCtcInit->u32HrcClockDiv | pstcCtcInit->u32CtcRefEdge | \
+ ((uint32_t)pstcCtcInit->u8TrimValue << CTC_CR1_TRMVAL_POS));
+ WRITE_REG32(CM_CTC->CR1, u32RegValue);
+
+ /* Set CR2 */
+ u32RegValue = ((u32ReloadValue << CTC_CR2_RLDVAL_POS) | u32OffsetValue);
+ WRITE_REG32(CM_CTC->CR2, u32RegValue);
+ i32Ret = LL_OK;
+ }
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief De-Initialize CTC function.
+ * @param None
+ * @retval int32_t:
+ * - LL_OK: De-Initialize success
+ * - LL_ERR_TIMEOUT: Reset time out
+ */
+int32_t CTC_DeInit(void)
+{
+ __IO uint32_t u32TimeOut = 0U;
+ int32_t i32Ret = LL_OK;
+
+ DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1);
+
+ CLR_REG32_BIT(CM_RMU->FRST0, RMU_FRST0_CTC);
+ /* Ensure reset procedure is completed */
+ while (RMU_FRST0_CTC != READ_REG32_BIT(CM_RMU->FRST0, RMU_FRST0_CTC)) {
+ u32TimeOut++;
+ if (u32TimeOut > CTC_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Enable or disable CTC error interrupt function.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void CTC_IntCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(CM_CTC->CR1, CTC_CR1_ERRIE);
+ } else {
+ CLR_REG32_BIT(CM_CTC->CR1, CTC_CR1_ERRIE);
+ }
+}
+
+/**
+ * @brief Get CTC flag status.
+ * @param [in] u32Flag CTC flag
+ * This parameter can be any composed value of the macros group @ref CTC_Flag
+ * @arg CTC_FLAG_TRIM_OK: Trimming OK flag
+ * @arg CTC_FLAG_TRIM_OVF: Trimming overflow flag
+ * @arg CTC_FLAG_TRIM_UDF: Trimming underflow flag
+ * @arg CTC_FLAG_BUSY: CTC busy flag
+ * @retval Returned value can be one of the following values:
+ */
+en_flag_status_t CTC_GetStatus(uint32_t u32Flag)
+{
+ DDL_ASSERT(IS_CTC_FLAG(u32Flag));
+
+ return ((0UL == READ_REG32_BIT(CM_CTC->STR, u32Flag)) ? RESET : SET);
+}
+
+/**
+ * @brief Set CTC trimming value.
+ * @param [in] u8TrimValue CTC trimming value
+ * This parameter can be Min_Data=0 && Max_Data=0x3F
+ * @retval None
+ */
+void CTC_SetTrimValue(uint8_t u8TrimValue)
+{
+ DDL_ASSERT(IS_CTC_TRIM_VALUE(u8TrimValue));
+
+ MODIFY_REG32(CM_CTC->CR1, CTC_CR1_TRMVAL, ((uint32_t)u8TrimValue << CTC_CR1_TRMVAL_POS));
+}
+
+/**
+ * @brief Get CTC trimming value.
+ * @param None
+ * @retval CTC trimming value(between Min_Data=0 and Max_Data=0x3F)
+ */
+uint8_t CTC_GetTrimValue(void)
+{
+ return (uint8_t)(READ_REG32_BIT(CM_CTC->CR1, CTC_CR1_TRMVAL) >> CTC_CR1_TRMVAL_POS);
+}
+
+/**
+ * @brief Set CTC reload value.
+ * @param [in] u16ReloadValue CTC reload value
+ * This parameter can be between Min_Data=0 and Max_Data=0xFFFF
+ * @retval None
+ */
+void CTC_SetReloadValue(uint16_t u16ReloadValue)
+{
+ MODIFY_REG32(CM_CTC->CR2, CTC_CR2_RLDVAL, ((uint32_t)u16ReloadValue << CTC_CR2_RLDVAL_POS));
+}
+
+/**
+ * @brief Get CTC reload value.
+ * @param None
+ * @retval CTC reload value (between Min_Data=0 and Max_Data=0xFFFF)
+ */
+uint16_t CTC_GetReloadValue(void)
+{
+ return (uint16_t)(READ_REG32_BIT(CM_CTC->CR2, CTC_CR2_RLDVAL) >> CTC_CR2_RLDVAL_POS);
+}
+
+/**
+ * @brief Set CTC offset value.
+ * @param [in] u8OffsetValue CTC offset value
+ * This parameter can be between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+void CTC_SetOffsetValue(uint8_t u8OffsetValue)
+{
+ MODIFY_REG32(CM_CTC->CR2, CTC_CR2_OFSVAL, ((uint32_t)u8OffsetValue << CTC_CR2_OFSVAL_POS));
+}
+
+/**
+ * @brief Get CTC offset value.
+ * @param None
+ * @retval CTC offset value (between Min_Data=0 and Max_Data=0xFF)
+ */
+uint8_t CTC_GetOffsetValue(void)
+{
+ return (uint8_t)(READ_REG32_BIT(CM_CTC->CR2, CTC_CR2_OFSVAL) >> CTC_CR2_OFSVAL_POS);
+}
+
+/**
+ * @brief Get CTC count value.
+ * @param None
+ * @retval CTC count value (between Min_Data=0 and Max_Data=0xFFFF)
+ */
+uint16_t CTC_GetCountValue(void)
+{
+ return READ_REG16(CM_CTC->CNT);
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_CTC_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_dac.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_dac.c
new file mode 100644
index 0000000000..7d2e3d4f6a
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_dac.c
@@ -0,0 +1,569 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_dac.c
+ * @brief This file provides firmware functions to manage the Digital-to-Analog
+ * Converter(DAC).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Refine data validation
+ Modify function:DAC_DeInit
+ 2023-09-30 CDT Modify API for Reference Manual Rev1.0
+ Fix register wrong and right brace position in assert
+ 2023-12-15 CDT Delete ASSERT IS_ADP_CTRL_ALLOWED() and IS_VALID_DATA_SRC() for Reference Manual Modified.
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_dac.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_DAC DAC
+ * @brief DAC Driver Library
+ * @{
+ */
+
+#if (LL_DAC_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup DAC_Local_Macros DAC Local Macros
+ * @{
+ */
+#define DAC_RESOLUTION (DAC_RESOLUTION_12BIT)
+#define DAC_DATA_REG_WIDTH (16U)
+#define DAC_DATA_RIGHT_ALIGN_MASK ((2U << DAC_RESOLUTION) - 1U)
+#define DAC_DATA_LEFT_ALIGN_MASK (DAC_DATA_RIGHT_ALIGN_MASK << (DAC_DATA_REG_WIDTH - DAC_RESOLUTION))
+
+#define DAC_RMU_TIMEOUT (100U)
+
+/**
+ * @defgroup DAC_Check_Parameters_Validity DAC Check Parameters Validity
+ * @{
+ */
+#define IS_VALID_UNIT(x) \
+( ((x) == CM_DAC1) || \
+ ((x) == CM_DAC2) || \
+ ((x) == CM_DAC3) || \
+ ((x) == CM_DAC4))
+
+#define IS_VALID_CH(x) (((x) == DAC_CH1) || ((x) == DAC_CH2))
+
+#define IS_VALID_DATA_ALIGN(x) (((x) == DAC_DATA_ALIGN_LEFT) || ((x) == DAC_DATA_ALIGN_RIGHT))
+
+#define IS_VALID_DATA_SRC(x) (((x) == DAC_DATA_SRC_DATAREG) || ((x) == DAC_DATA_SRC_DCU))
+
+#define IS_VALID_ADCPRIO_CONFIG(x) ((0U != (x)) && (DAC_ADP_SEL_ALL == ((x) | DAC_ADP_SEL_ALL)))
+
+#define IS_VALID_DATA_GAIN(x) (((x) == DAC_AMP_GAIN_1) || ((x) == DAC_AMP_GAIN_2))
+
+#define IS_VALID_RIGHT_ALIGNED_DATA(data) (((data) & ~DAC_DATA_RIGHT_ALIGN_MASK) == 0U)
+#define IS_VALID_LEFT_ALIGNED_DATA(data) (((data) & ~DAC_DATA_LEFT_ALIGN_MASK) == 0U)
+
+#define IS_OUTPUT_CTRL_ALLOWED(x,Ch) \
+( (READ_REG16_BIT(DACx->DACR, DAC_DACR_DAAMP1 << (Ch)) == 0U) || \
+ ((x) == ENABLE))
+
+#define IS_AMP_CTRL_ALLOWED(x,Ch) \
+( (READ_REG16_BIT(DACx->DAOCR, DAC_DAOCR_DAODIS1 << (Ch)) == 0U) || \
+ ((x) == DISABLE))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ * @defgroup DAC_Global_Functions DAC Global Functions
+ * @{
+ */
+
+/**
+ * @brief DAC data register's data alignment pattern configuration
+ * @param [in] DACx Pointer to the DAC peripheral register.
+ * This parameter can be a value of the following:
+ * @arg CM_DAC or CM_DACx
+ * @param [in] u16Align Specify the data alignment.
+ * This parameter can be a value of @ref DAC_DATAREG_ALIGN_PATTERN
+ * - DAC_DATA_ALIGN_LEFT: left alignment
+ * - DAC_DATA_ALIGN_RIGHT: right alignment
+ * @retval None
+ */
+void DAC_DataRegAlignConfig(CM_DAC_TypeDef *DACx, uint16_t u16Align)
+{
+ DDL_ASSERT(IS_VALID_UNIT(DACx));
+ DDL_ASSERT(IS_VALID_DATA_ALIGN(u16Align));
+
+ MODIFY_REG16(DACx->DACR, DAC_DACR_DPSEL, u16Align);
+}
+
+/**
+ * @brief DAC output function command
+ * @param [in] DACx Pointer to the DAC peripheral register.
+ * This parameter can be a value of the following:
+ * @arg CM_DAC or CM_DACx
+ * @param [in] u16Ch Specify DAC channel @ref DAC_CH.
+ * This parameter can be a value of the following:
+ * @arg DAC_CH1
+ * @arg DAC_CH2
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void DAC_OutputCmd(CM_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState)
+{
+ uint16_t u16Cmd;
+
+ DDL_ASSERT(IS_VALID_UNIT(DACx));
+ DDL_ASSERT(IS_VALID_CH(u16Ch));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_OUTPUT_CTRL_ALLOWED(enNewState, u16Ch));
+
+ u16Cmd = (uint16_t)(1UL << (DAC_DAOCR_DAODIS1_POS + u16Ch));
+
+ if (ENABLE == enNewState) {
+ CLR_REG16_BIT(DACx->DAOCR, u16Cmd);
+ } else {
+ SET_REG16_BIT(DACx->DAOCR, u16Cmd);
+ }
+}
+
+/**
+ * @brief DAC AMP function command
+ * @param [in] DACx Pointer to the DAC peripheral register.
+ * This parameter can be a value of the following:
+ * @arg CM_DAC or CM_DACx
+ * @param [in] u16Ch Specify DAC channel @ref DAC_CH.
+ * This parameter can be a value of the following:
+ * @arg DAC_CH1
+ * @arg DAC_CH2
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void DAC_AMPCmd(CM_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState)
+{
+ uint16_t u16Cmd;
+
+ DDL_ASSERT(IS_VALID_UNIT(DACx));
+ DDL_ASSERT(IS_VALID_CH(u16Ch));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_AMP_CTRL_ALLOWED(enNewState, u16Ch));
+ u16Cmd = (uint16_t)(1UL << (DAC_DACR_DAAMP1_POS + u16Ch));
+
+ if (ENABLE == enNewState) {
+ SET_REG16_BIT(DACx->DACR, u16Cmd);
+ } else {
+ CLR_REG16_BIT(DACx->DACR, u16Cmd);
+ }
+}
+
+/**
+ * @brief Set DAC amp gain for specified channel
+ * @param [in] DACx Pointer to the DAC peripheral register.
+ * This parameter can be a value of the following:
+ * @arg CM_DAC or CM_DACx
+ * @param [in] u16Ch Specify the DAC channel @ref DAC_CH.
+ * This parameter can be a value of the following:
+ * @arg DAC_CH1
+ * @arg DAC_CH2
+ * @param [in] u16Gain Specify the amp gain.
+ * This parameter can be a value of @ref DAC_AMP_GAIN
+ * - DAC_AMP_GAIN_1: AMP gain is 1
+ * - DAC_AMP_GAIN_2: AMP gain is 2
+ * @retval None
+ */
+void DAC_SetAmpGain(CM_DAC_TypeDef *DACx, uint16_t u16Ch, uint16_t u16Gain)
+{
+ DDL_ASSERT(IS_VALID_UNIT(DACx));
+ DDL_ASSERT(IS_VALID_CH(u16Ch));
+ DDL_ASSERT(IS_VALID_DATA_GAIN(u16Gain));
+
+ MODIFY_REG16(DACx->DACR, (uint16_t)DAC_DACR_DAOGS1 << u16Ch, u16Gain << u16Ch);
+}
+
+/**
+ * @brief DAC ADC priority function command
+ * @param [in] DACx Pointer to the DAC peripheral register.
+ * This parameter can be a value of the following:
+ * @arg CM_DAC or CM_DACx
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ * @note please make sure ADC is in stoped status before calling DAC_ADCPrioCmd
+ */
+void DAC_ADCPrioCmd(CM_DAC_TypeDef *DACx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_UNIT(DACx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG16_BIT(DACx->DAADPCR, DAC_DAADPCR_ADPEN);
+ } else {
+ CLR_REG16_BIT(DACx->DAADPCR, DAC_DAADPCR_ADPEN);
+ }
+}
+
+/**
+ * @brief Enable or Disable the ADC priority for the selected ADCx
+ * @param [in] DACx Pointer to the DAC peripheral register.
+ * This parameter can be a value of the following:
+ * @arg CM_DAC or CM_DACx
+ * @param [in] u16ADCxPrio ADCx priority to be enabled or disabled.
+ * This parameter can be one or any combination of the following values:
+ * @arg DAC_ADP_SEL_ADC1
+ * @arg DAC_ADP_SEL_ADC2
+ * @arg DAC_ADP_SEL_ADC3
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ * @note please make sure ADC is in stoped status before calling DAC_ADCPrioConfig
+ */
+void DAC_ADCPrioConfig(CM_DAC_TypeDef *DACx, uint16_t u16ADCxPrio, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_UNIT(DACx));
+ DDL_ASSERT(IS_VALID_ADCPRIO_CONFIG(u16ADCxPrio));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG16_BIT(DACx->DAADPCR, u16ADCxPrio);
+ } else {
+ CLR_REG16_BIT(DACx->DAADPCR, u16ADCxPrio);
+ }
+}
+
+/**
+ * @brief Start the specified DAC channel
+ * @param [in] DACx Pointer to the DAC peripheral register.
+ * This parameter can be a value of the following:
+ * @arg CM_DAC or CM_DACx
+ * @param [in] u16Ch Specify DAC channel @ref DAC_CH.
+ * This parameter can be a value of the following:
+ * @arg DAC_CH1
+ * @arg DAC_CH2
+ * @retval int32_t:
+ * - LL_OK: No errors occurred
+ * - LL_ERR_INVD_MD: cannot start single channel when \n
+ * this channel have already been started by \n
+ * @ref DAC_StartDualCh
+ */
+int32_t DAC_Start(CM_DAC_TypeDef *DACx, uint16_t u16Ch)
+{
+ int32_t i32Ret = LL_OK;
+ uint16_t u16Cmd;
+
+ DDL_ASSERT(IS_VALID_UNIT(DACx));
+ DDL_ASSERT(IS_VALID_CH(u16Ch));
+
+ if ((DACx->DACR & DAC_DACR_DAE) != 0U) {
+ i32Ret = LL_ERR_INVD_MD;
+ } else {
+ u16Cmd = (uint16_t)(1UL << (DAC_DACR_DA1E_POS + u16Ch));
+ SET_REG16_BIT(DACx->DACR, u16Cmd);
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Stop the specified DAC channel
+ * @param [in] DACx Pointer to the DAC peripheral register.
+ * This parameter can be a value of the following:
+ * @arg CM_DAC or CM_DACx
+ * @param [in] u16Ch Specify DAC channel @ref DAC_CH.
+ * This parameter can be a value of the following:
+ * @arg DAC_CH1
+ * @arg DAC_CH2
+ * @retval int32_t:
+ * - LL_OK: No errors occurred
+ * - LL_ERR_INVD_MD: cannot stop single channel when \n
+ * this channel is started by \n
+ * @ref DAC_StartDualCh
+ */
+int32_t DAC_Stop(CM_DAC_TypeDef *DACx, uint16_t u16Ch)
+{
+ int32_t i32Ret = LL_OK;
+ uint16_t u16Cmd;
+
+ DDL_ASSERT(IS_VALID_UNIT(DACx));
+ DDL_ASSERT(IS_VALID_CH(u16Ch));
+
+ if ((DACx->DACR & DAC_DACR_DAE) != 0U) {
+ i32Ret = LL_ERR_INVD_MD;
+ } else {
+ u16Cmd = (uint16_t)(1UL << (DAC_DACR_DA1E_POS + u16Ch));
+ CLR_REG16_BIT(DACx->DACR, u16Cmd);
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Start DAC channel 1 and channel 2
+ * @param [in] DACx Pointer to the DAC peripheral register.
+ * This parameter can be a value of the following:
+ * @arg CM_DAC or CM_DACx
+ * @retval None
+ */
+void DAC_StartDualCh(CM_DAC_TypeDef *DACx)
+{
+ DDL_ASSERT(IS_VALID_UNIT(DACx));
+
+ SET_REG16_BIT(DACx->DACR, DAC_DACR_DAE);
+}
+
+/**
+ * @brief Stop DAC channel 1 and channel 2
+ * @param [in] DACx Pointer to the DAC peripheral register.
+ * This parameter can be a value of the following:
+ * @arg CM_DAC or CM_DACx
+ * @retval None
+ */
+void DAC_StopDualCh(CM_DAC_TypeDef *DACx)
+{
+ DDL_ASSERT(IS_VALID_UNIT(DACx));
+
+ CLR_REG16_BIT(DACx->DACR, DAC_DACR_DAE);
+}
+
+/**
+ * @brief Set the specified data to the data holding register of specified DAC channel
+ * @param [in] DACx Pointer to the DAC peripheral register.
+ * This parameter can be a value of the following:
+ * @arg CM_DAC or CM_DACx
+ * @param [in] u16Ch Specify DAC channel @ref DAC_CH.
+ * This parameter can be a value of the following:
+ * @arg DAC_CH1
+ * @arg DAC_CH2
+ * @param [in] u16Data Data to be loaded into data holding register of specified channel
+ * @retval None
+ */
+void DAC_SetChData(CM_DAC_TypeDef *DACx, uint16_t u16Ch, uint16_t u16Data)
+{
+ __IO uint16_t *u16DADRx;
+
+ DDL_ASSERT(IS_VALID_UNIT(DACx));
+ DDL_ASSERT(IS_VALID_CH(u16Ch));
+
+ if (READ_REG16_BIT(DACx->DACR, DAC_DACR_DPSEL) == DAC_DATA_ALIGN_LEFT) {
+ DDL_ASSERT(IS_VALID_LEFT_ALIGNED_DATA(u16Data));
+ } else {
+ DDL_ASSERT(IS_VALID_RIGHT_ALIGNED_DATA(u16Data));
+ }
+
+ u16DADRx = (uint16_t *)((uint32_t) & (DACx->DADR1) + u16Ch * 2UL);
+ WRITE_REG16(*u16DADRx, u16Data);
+}
+
+/**
+ * @brief Set the specified data to the data holding register of DAC channel 1 and channel 2
+ * @param [in] DACx Pointer to the DAC peripheral register.
+ * This parameter can be a value of the following:
+ * @arg CM_DAC or CM_DACx
+ * @param u16Data1: Data to be loaded into data holding register of channel 1
+ * @param u16Data2: Data to be loaded into data holding register of channel 2
+ * @retval None
+ */
+void DAC_SetDualChData(CM_DAC_TypeDef *DACx, uint16_t u16Data1, uint16_t u16Data2)
+{
+ uint32_t u32Data;
+ __IO uint32_t *u32DADRx;
+
+ DDL_ASSERT(IS_VALID_UNIT(DACx));
+
+ if (READ_REG16_BIT(DACx->DACR, DAC_DACR_DPSEL) == DAC_DATA_ALIGN_LEFT) {
+ DDL_ASSERT(IS_VALID_LEFT_ALIGNED_DATA(u16Data1));
+ DDL_ASSERT(IS_VALID_LEFT_ALIGNED_DATA(u16Data2));
+ } else {
+ DDL_ASSERT(IS_VALID_RIGHT_ALIGNED_DATA(u16Data1));
+ DDL_ASSERT(IS_VALID_RIGHT_ALIGNED_DATA(u16Data2));
+ }
+
+ u32Data = ((uint32_t)u16Data2 << 16U) | u16Data1;
+ u32DADRx = (__IO uint32_t *)(uint32_t)(&DACx->DADR1);
+ WRITE_REG32(*u32DADRx, u32Data);
+}
+
+/**
+ * @brief Get convert status of specified channel in ADC priority mode
+ * @param [in] DACx Pointer to the DAC peripheral register.
+ * This parameter can be a value of the following:
+ * @arg CM_DAC or CM_DACx
+ * @param [in] u16Ch Specify DAC channel @ref DAC_CH.
+ * This parameter can be a value of the following:
+ * @arg DAC_CH1
+ * @arg DAC_CH2
+ * @retval int32_t:
+ * - LL_ERR_INVD_MD: Could not get convert status when adc priority is not enabled
+ * - LL_OK: Data convert completed
+ * - LL_ERR_BUSY: Data convert is ongoing
+ */
+int32_t DAC_GetChConvertState(const CM_DAC_TypeDef *DACx, uint16_t u16Ch)
+{
+ int32_t i32Ret = LL_ERR_INVD_MD;
+
+ DDL_ASSERT(IS_VALID_UNIT(DACx));
+ DDL_ASSERT(IS_VALID_CH(u16Ch));
+
+ if (0U != READ_REG16_BIT(DACx->DAADPCR, DAC_DAADPCR_ADPEN)) {
+ i32Ret = LL_ERR_BUSY;
+
+ if (READ_REG16_BIT(DACx->DAADPCR, (DAC_DAADPCR_DA1SF << u16Ch)) == 0U) {
+ i32Ret = LL_OK;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Fills each pstcDacInit member with its default value
+ * @param [in] pstcDacInit pointer to a stc_dac_init_t structure which will
+ * be initialized.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_INVD_PARAM: pstcDacInit is NULL
+ */
+int32_t DAC_StructInit(stc_dac_init_t *pstcDacInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (pstcDacInit != NULL) {
+ pstcDacInit->enOutput = ENABLE;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize the DAC peripheral according to the specified parameters
+ * in the stc_dac_init_t
+ * @param [in] DACx Pointer to the DAC peripheral register.
+ * This parameter can be a value of the following:
+ * @arg CM_DAC or CM_DACx
+ * @param [in] u16Ch Specify DAC channel @ref DAC_CH.
+ * This parameter can be a value of the following:
+ * @arg DAC_CH1
+ * @arg DAC_CH2
+ * @param [in] pstcDacInit pointer to a stc_dac_init_t structure that contains
+ * the configuration information for the specified DAC channel.
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully
+ * - LL_ERR_INVD_PARAM: pstcDacInit is NULL
+ */
+int32_t DAC_Init(CM_DAC_TypeDef *DACx, uint16_t u16Ch, const stc_dac_init_t *pstcDacInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (pstcDacInit != NULL) {
+ DDL_ASSERT(IS_VALID_UNIT(DACx));
+ DDL_ASSERT(IS_VALID_CH(u16Ch));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcDacInit->enOutput));
+ DAC_OutputCmd(DACx, u16Ch, pstcDacInit->enOutput);
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Deinitialize the DAC peripheral registers to their default reset values.
+ * @param [in] DACx Pointer to the DAC peripheral register.
+ * This parameter can be a value of the following:
+ * @arg CM_DAC or CM_DACx
+ * @retval int32_t:
+ * - LL_OK: Reset success.
+ * - LL_ERR_TIMEOUT: Reset time out.
+ * - LL_ERR_INVD_PARAM Invalid parameter.
+ * @retval None
+ */
+int32_t DAC_DeInit(CM_DAC_TypeDef *DACx)
+{
+ int32_t i32Ret = LL_OK;
+ const uint32_t au32DACx[] = {CM_DAC1_BASE, CM_DAC2_BASE, CM_DAC3_BASE, CM_DAC4_BASE};
+ __IO uint8_t u8TimeOut = 0U;
+ uint32_t RMU_FRST3_DACx = 0UL;
+ uint8_t i;
+ DDL_ASSERT(IS_VALID_UNIT(DACx));
+ DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1);
+
+ for (i = 0; i < ARRAY_SZ(au32DACx); i++) {
+ if ((uint32_t)DACx == au32DACx[i]) {
+ RMU_FRST3_DACx = (RMU_FRST3_DAC1 << i);
+ break;
+ }
+ }
+ if (i < ARRAY_SZ(au32DACx)) {
+ /* Reset DAC */
+ CLR_REG32_BIT(CM_RMU->FRST3, RMU_FRST3_DACx);
+ /* Ensure reset procedure is completed */
+ while (RMU_FRST3_DACx != READ_REG32_BIT(CM_RMU->FRST3, RMU_FRST3_DACx)) {
+ u8TimeOut++;
+ if (u8TimeOut > DAC_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+ } else {
+ i32Ret = LL_ERR_INVD_PARAM;
+ }
+ return i32Ret;
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_DAC_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_dbgc.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_dbgc.c
new file mode 100644
index 0000000000..9f2c762f02
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_dbgc.c
@@ -0,0 +1,175 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_dbgc.c
+ * @brief This file provides firmware functions to manage the DBGC.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2023-06-30 CDT First version
+ 2023-09-30 CDT Add assert to DBGC_PeriphCmd & DBGC_Periph2Cmd
+ Add assert IS_DGBC_TRACE_MD and add API DBGC_TraceIoCmd,DBGC_TraceModeConfig
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_dbgc.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_DBGC DBGC
+ * @brief DBGC Driver Library
+ * @{
+ */
+
+#if (LL_DBGC_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/**
+ * @defgroup DBGC_Local_Macros DBGC Local Macros
+ * @{
+ */
+
+/**
+ * @defgroup DBGC_Check_Parameters_Validity DBGC Check Parameters Validity
+ * @{
+ */
+#define IS_SECURITY_FLAG(x) \
+( ((x) != 0U) && \
+ (((x) | DBGC_SECURITY_ALL) == DBGC_SECURITY_ALL))
+
+/* Parameter valid check for debug trace mode */
+#define IS_DGBC_TRACE_MD(x) \
+( ((x) == DBGC_TRACE_ASYNC) || \
+ ((x) == DBGC_TRACE_SYNC_1BIT) || \
+ ((x) == DBGC_TRACE_SYNC_2BIT) || \
+ ((x) == DBGC_TRACE_SYNC_4BIT))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup DBGC_Global_Functions DBGC Global Functions
+ * @{
+ */
+
+/**
+ * @brief Whether to stop the peripheral while mcu core stop.
+ * @param [in] u32Periph Specifies the peripheral. @ref DBGC_Periph_Sel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void DBGC_PeriphCmd(uint32_t u32Periph, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ CLR_REG32_BIT(CM_DBGC->MCUSTPCTL, u32Periph);
+ } else {
+ SET_REG32_BIT(CM_DBGC->MCUSTPCTL, u32Periph);
+ }
+}
+
+/**
+ * @brief Whether to stop the peripheral2 while mcu core stop.
+ * @param [in] u32Periph Specifies the peripheral. @ref DBGC_Periph2_Sel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void DBGC_Periph2Cmd(uint32_t u32Periph, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ CLR_REG32_BIT(CM_DBGC->MCUSTPCTL2, u32Periph);
+ } else {
+ SET_REG32_BIT(CM_DBGC->MCUSTPCTL2, u32Periph);
+ }
+}
+
+/**
+ * @brief Enable or disable the trace pin output.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void DBGC_TraceIoCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(CM_DBGC->MCUTRACECTL, DBGC_MCUTRACECTL_TRACEIOEN);
+ } else {
+ CLR_REG32_BIT(CM_DBGC->MCUTRACECTL, DBGC_MCUTRACECTL_TRACEIOEN);
+ }
+}
+
+/**
+ * @brief Config trace mode.
+ * @param [in] u32TraceMode Specifies the trace mode. @ref DBGC_Trace_Mode
+ * @retval None
+ */
+void DBGC_TraceModeConfig(uint32_t u32TraceMode)
+{
+ DDL_ASSERT(IS_DGBC_TRACE_MD(u32TraceMode));
+
+ MODIFY_REG32(CM_DBGC->MCUTRACECTL, DBGC_MCUTRACECTL_TRACEMODE, u32TraceMode);
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_DBGC_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_dcu.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_dcu.c
new file mode 100644
index 0000000000..d5cdaa3080
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_dcu.c
@@ -0,0 +1,552 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_dcu.c
+ * @brief This file provides firmware functions to manage the DCU(Data Computing
+ * Unit).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Modify typo
+ Modify API DCU_DeInit()
+ Delete wave mode
+ Modify function DCU_IntCmd() for misra
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_dcu.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_DCU DCU
+ * @brief DCU Driver Library
+ * @{
+ */
+
+#if (LL_DCU_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup DCU_Local_Macros DCU Local Macros
+ * @{
+ */
+
+#define DCU_RMU_TIMEOUT (100U)
+
+/**
+ * @defgroup DCU_Check_Parameters_Validity DCU Check Parameters Validity
+ * @{
+ */
+
+#define IS_DCU_BASE_FUNC_UNIT(x) \
+( ((x) == CM_DCU1) || \
+ ((x) == CM_DCU2) || \
+ ((x) == CM_DCU3))
+
+#define IS_DCU_UNIT(x) (IS_DCU_BASE_FUNC_UNIT(x))
+
+#define IS_DCU_BASE_FUNC_UNIT_MD(x) \
+( ((x) == DCU_MD_CMP) || \
+ ((x) == DCU_MD_ADD) || \
+ ((x) == DCU_MD_SUB) || \
+ ((x) == DCU_MD_HW_ADD) || \
+ ((x) == DCU_MD_HW_SUB) || \
+ ((x) == DCU_MD_INVD))
+
+#define IS_DCU_BASE_FUNC_UNIT_FLAG(x) \
+( (0UL != (x)) && \
+ (0UL == ((x) & (~DCU_BASE_FUNC_UNIT_FLAG_MASK))))
+
+#define IS_DCU_CMP_COND(x) \
+( ((x) == DCU_CMP_TRIG_DATA0) || \
+ ((x) == DCU_CMP_TRIG_DATA0_DATA1_DATA2))
+
+#define IS_DCU_DATA_WIDTH(x) \
+( ((x) == DCU_DATA_WIDTH_8BIT) || \
+ ((x) == DCU_DATA_WIDTH_16BIT) || \
+ ((x) == DCU_DATA_WIDTH_32BIT))
+
+#define IS_DCU_INT_CATEGORY(x) \
+( ((x) == DCU_CATEGORY_OP) || \
+ ((x) == DCU_CATEGORY_CMP_WIN) || \
+ ((x) == DCU_CATEGORY_CMP_NON_WIN))
+
+#define IS_DCU_INT_OP(x) ((x) == DCU_INT_OP_CARRY)
+
+#define IS_DCU_INT_CMP_WIN(x) \
+( ((x) == DCU_INT_CMP_WIN_INSIDE) || \
+ ((x) == DCU_INT_CMP_WIN_OUTSIDE))
+
+#define IS_DCU_INT_CMP_NON_WIN(x) \
+( ((x) != 0UL) || \
+ (((x) | DCU_INT_CMP_NON_WIN_ALL) == DCU_INT_CMP_NON_WIN_ALL))
+
+#define IS_DCU_INT_WAVE_MD(x) \
+( ((x) != 0UL) && \
+ (((x) | DCU_INT_WAVE_MD_ALL) == DCU_INT_WAVE_MD_ALL))
+
+#define IS_DCU_DATA_REG(x) \
+( ((x) == DCU_DATA0_IDX) || \
+ ((x) == DCU_DATA1_IDX) || \
+ ((x) == DCU_DATA2_IDX))
+
+#define IS_DCU_WAVE_UPPER_LIMIT(x) ((x) <= 0xFFFUL)
+
+#define IS_DCU_WAVE_LOWER_LIMIT(x) ((x) <= 0xFFFUL)
+
+#define IS_DCU_WAVE_STEP(x) ((x) <= 0xFFFUL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DCU_Flag_Mask DCU Flag Mask
+ * @{
+ */
+#define DCU_BASE_FUNC_UNIT_FLAG_MASK (0x0E7FUL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup DCU_Register_Address DCU Register Address
+ * @{
+ */
+#define DCU_REG_ADDR(_REG_) ((uint32_t)(&(_REG_)))
+#define DCU_DATA_REG_ADDR(_UNITx_, _IDX_) (DCU_REG_ADDR((_UNITx_)->DATA0) + ((_IDX_) << 2UL))
+
+#define DCU_DATA_REG8(_UNITx_, _IDX_) (*(__IO uint8_t *)DCU_DATA_REG_ADDR(_UNITx_, _IDX_))
+#define DCU_DATA_REG16(_UNITx_, _IDX_) (*(__IO uint16_t *)DCU_DATA_REG_ADDR(_UNITx_, _IDX_))
+#define DCU_DATA_REG32(_UNITx_, _IDX_) (*(__IO uint32_t *)DCU_DATA_REG_ADDR(_UNITx_, _IDX_))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup DCU_Global_Functions DCU Global Functions
+ * @{
+ */
+
+/**
+ * @brief Set the fields of structure stc_dcu_init_t to default values.
+ * @param [out] pstcDcuInit Pointer to a @ref stc_dcu_init_t structure.
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcDcuInit value is NULL.
+ */
+int32_t DCU_StructInit(stc_dcu_init_t *pstcDcuInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcDcuInit) {
+ pstcDcuInit->u32Mode = DCU_MD_INVD;
+ pstcDcuInit->u32DataWidth = DCU_DATA_WIDTH_8BIT;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize DCU function.
+ * @param [in] DCUx Pointer to DCU instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_DCU or CM_DCUx: DCU instance register base
+ * @param [in] pstcDcuInit Pointer to a @ref stc_dcu_init_t structure.
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcDcuInit value is NULL.
+ */
+int32_t DCU_Init(CM_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcDcuInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcDcuInit) {
+ DDL_ASSERT(IS_DCU_UNIT(DCUx) && IS_DCU_BASE_FUNC_UNIT_MD(pstcDcuInit->u32Mode));
+ DDL_ASSERT(IS_DCU_DATA_WIDTH(pstcDcuInit->u32DataWidth));
+
+ /* Set register: CTL */
+ WRITE_REG32(DCUx->CTL, (pstcDcuInit->u32Mode | pstcDcuInit->u32DataWidth));
+
+ /* Disable interrupt */
+ WRITE_REG32(DCUx->INTEVTSEL, 0x00000000UL);
+
+ /* Clear Flag */
+ WRITE_REG32(DCUx->FLAGCLR, 0x0000007FUL);
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief De-Initialize DCU function.
+ * @param [in] DCUx Pointer to DCU instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_DCU or CM_DCUx: DCU instance register base
+ * @retval int32_t:
+ * - LL_OK: De-Initialize success.
+ * - LL_ERR_TIMEOUT: Timeout.
+ */
+int32_t DCU_DeInit(CM_DCU_TypeDef *DCUx)
+{
+ int32_t i32Ret = LL_OK;
+ uint32_t u32UnitShift;
+ uint32_t u32UnitBase;
+ __IO uint8_t u8TimeOut = 0U;
+
+ DDL_ASSERT(IS_DCU_UNIT(DCUx));
+ /* Check FRST register protect */
+ DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1);
+
+ /* Reset */
+ u32UnitBase = (uint32_t)DCUx;
+ u32UnitShift = (u32UnitBase - CM_DCU1_BASE) / (CM_DCU2_BASE - CM_DCU1_BASE);
+ CLR_REG32_BIT(CM_RMU->FRST0, RMU_FRST0_DCU1 << u32UnitShift);
+ /* Ensure reset procedure is completed */
+ while (0UL == READ_REG32_BIT(CM_RMU->FRST0, RMU_FRST0_DCU1 << u32UnitShift)) {
+ u8TimeOut++;
+ if (u8TimeOut > DCU_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Set DCU operation mode.
+ * @param [in] DCUx Pointer to DCU instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_DCU or CM_DCUx: DCU instance register base
+ * @param [in] u32Mode DCU mode
+ * This parameter can be one of the macros group @ref DCU_Mode.
+ * @retval None
+ */
+void DCU_SetMode(CM_DCU_TypeDef *DCUx, uint32_t u32Mode)
+{
+ DDL_ASSERT(IS_DCU_UNIT(DCUx) && IS_DCU_BASE_FUNC_UNIT_MD(u32Mode));
+
+ MODIFY_REG32(DCUx->CTL, DCU_CTL_MODE, u32Mode);
+}
+
+/**
+ * @brief Set DCU data size.
+ * @param [in] DCUx Pointer to DCU instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_DCU or CM_DCUx: DCU instance register base
+ * @param [in] u32DataWidth DCU data width
+ * This parameter can be one of the macros group @ref DCU_Data_Width
+ * @arg DCU_DATA_WIDTH_8BIT: DCU data size 8 bit
+ * @arg DCU_DATA_WIDTH_16BIT: DCU data size 16 bit
+ * @arg DCU_DATA_WIDTH_32BIT: DCU data size 32 bit
+ * @retval None
+ */
+void DCU_SetDataWidth(CM_DCU_TypeDef *DCUx, uint32_t u32DataWidth)
+{
+ DDL_ASSERT(IS_DCU_UNIT(DCUx));
+ DDL_ASSERT(IS_DCU_DATA_WIDTH(u32DataWidth));
+
+ MODIFY_REG32(DCUx->CTL, DCU_CTL_DATASIZE, u32DataWidth);
+}
+
+/**
+ * @brief Set DCU compare trigger condition.
+ * @param [in] DCUx Pointer to DCU instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_DCU or CM_DCUx: DCU instance register base
+ * @param [in] u32Cond DCU compare trigger condition
+ * This parameter can be one of the macros group @ref DCU_Compare_Trigger_Condition
+ * @arg DCU_CMP_TRIG_DATA0: DCU compare triggered by DATA0.
+ * @arg DCU_CMP_TRIG_DATA0_DATA1_DATA2: DCU compare triggered by DATA0 or DATA1 or DATA2.
+ * @retval None
+ */
+void DCU_SetCompareCond(CM_DCU_TypeDef *DCUx, uint32_t u32Cond)
+{
+ DDL_ASSERT(IS_DCU_UNIT(DCUx));
+ DDL_ASSERT(IS_DCU_CMP_COND(u32Cond));
+
+ MODIFY_REG32(DCUx->CTL, DCU_CTL_COMPTRG, u32Cond);
+}
+
+/**
+ * @brief Get DCU flag.
+ * @param [in] DCUx Pointer to DCU instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_DCU or CM_DCUx: DCU instance register base
+ * @param [in] u32Flag The specified DCU flag
+ * This parameter can be any composed value of the macros group @ref DCU_Flag.
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t DCU_GetStatus(const CM_DCU_TypeDef *DCUx, uint32_t u32Flag)
+{
+ DDL_ASSERT(IS_DCU_UNIT(DCUx) && IS_DCU_BASE_FUNC_UNIT_FLAG(u32Flag));
+
+ return (0UL == READ_REG32_BIT(DCUx->FLAG, u32Flag)) ? RESET : SET;
+}
+
+/**
+ * @brief Clear DCU flag.
+ * @param [in] DCUx Pointer to DCU instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_DCU or CM_DCUx: DCU instance register base
+ * @param [in] u32Flag The specified DCU flag
+ * This parameter can be any composed value of the macros group @ref DCU_Mode.
+ * @retval None
+ */
+void DCU_ClearStatus(CM_DCU_TypeDef *DCUx, uint32_t u32Flag)
+{
+ DDL_ASSERT(IS_DCU_UNIT(DCUx) && IS_DCU_BASE_FUNC_UNIT_FLAG(u32Flag));
+
+ WRITE_REG32(DCUx->FLAGCLR, u32Flag);
+}
+
+/**
+ * @brief Enable or disable DCU interrupt function.
+ * @param [in] DCUx Pointer to DCU instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_DCU or CM_DCUx: DCU instance register base
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void DCU_GlobalIntCmd(CM_DCU_TypeDef *DCUx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_DCU_UNIT(DCUx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(DCUx->CTL, DCU_CTL_INTEN);
+ } else {
+ CLR_REG32_BIT(DCUx->CTL, DCU_CTL_INTEN);
+ }
+}
+
+/**
+ * @brief Enable/disable DCU the specified interrupt source.
+ * @param [in] DCUx Pointer to DCU instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_DCU or CM_DCUx: DCU instance register base
+ * @param [in] u32IntCategory DCU interrupt category
+ * This parameter can be one of the macros group @ref DCU_Category.
+ * @param [in] u32IntType DCU interrupt type
+ * This parameter can be one of the macros group @ref DCU_Interrupt_Type.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void DCU_IntCmd(CM_DCU_TypeDef *DCUx, uint32_t u32IntCategory, uint32_t u32IntType, en_functional_state_t enNewState)
+{
+ uint32_t u32Type;
+
+ DDL_ASSERT(IS_DCU_UNIT(DCUx));
+ DDL_ASSERT(IS_DCU_INT_CATEGORY(u32IntCategory));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (DCU_CATEGORY_OP == u32IntCategory) {
+ DDL_ASSERT(IS_DCU_INT_OP(u32IntType));
+ u32Type = (u32IntType & DCU_INT_OP_CARRY);
+ } else if (DCU_CATEGORY_CMP_WIN == u32IntCategory) {
+ DDL_ASSERT(IS_DCU_INT_CMP_WIN(u32IntType));
+ u32Type = (u32IntType & DCU_INT_CMP_WIN_ALL);
+ } else {
+ DDL_ASSERT(IS_DCU_INT_CMP_NON_WIN(u32IntType));
+ u32Type = (u32IntType & DCU_INT_CMP_NON_WIN_ALL);
+ }
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(DCUx->INTEVTSEL, u32Type);
+ } else {
+ CLR_REG32_BIT(DCUx->INTEVTSEL, u32Type);
+ }
+}
+
+/**
+ * @brief Read DCU register DATA for byte.
+ * @param [in] DCUx Pointer to DCU instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_DCU or CM_DCUx: DCU instance register base
+ * @param [in] u32DataIndex DCU data register index
+ * This parameter can be one of the macros group @ref DCU_Data_Register_Index
+ * @arg DCU_DATA0_IDX: DCU DATA0
+ * @arg DCU_DATA1_IDX: DCU DATA1
+ * @arg DCU_DATA2_IDX: DCU DATA2
+ * @retval DCU register DATA value for byte
+ */
+uint8_t DCU_ReadData8(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex)
+{
+ DDL_ASSERT(IS_DCU_UNIT(DCUx));
+ DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex));
+
+ return READ_REG8(DCU_DATA_REG8(DCUx, u32DataIndex));
+}
+
+/**
+ * @brief Write DCU register DATA for byte.
+ * @param [in] DCUx Pointer to DCU instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_DCU or CM_DCUx: DCU instance register base
+ * @param [in] u32DataIndex DCU data register index
+ * This parameter can be one of the macros group @ref DCU_Data_Register_Index
+ * @arg DCU_DATA0_IDX: DCU DATA0
+ * @arg DCU_DATA1_IDX: DCU DATA1
+ * @arg DCU_DATA2_IDX: DCU DATA2
+ * @param [in] u8Data The data to write.
+ * @retval None
+ */
+void DCU_WriteData8(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint8_t u8Data)
+{
+ __IO uint8_t *DATA;
+
+ DDL_ASSERT(IS_DCU_UNIT(DCUx));
+ DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex));
+
+ DATA = &DCU_DATA_REG8(DCUx, u32DataIndex);
+ WRITE_REG8(*DATA, u8Data);
+}
+
+/**
+ * @brief Read DCU register DATA for half-word.
+ * @param [in] DCUx Pointer to DCU instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_DCU or CM_DCUx: DCU instance register base
+ * @param [in] u32DataIndex DCU data register index
+ * This parameter can be one of the macros group @ref DCU_Data_Register_Index
+ * @arg DCU_DATA0_IDX: DCU DATA0
+ * @arg DCU_DATA1_IDX: DCU DATA1
+ * @arg DCU_DATA2_IDX: DCU DATA2
+ * @retval DCU register DATA value for half-word
+ */
+uint16_t DCU_ReadData16(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex)
+{
+ DDL_ASSERT(IS_DCU_UNIT(DCUx));
+ DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex));
+
+ return READ_REG16(DCU_DATA_REG16(DCUx, u32DataIndex));
+}
+
+/**
+ * @brief Write DCU register DATA for half-word.
+ * @param [in] DCUx Pointer to DCU instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_DCU or CM_DCUx: DCU instance register base
+ * @param [in] u32DataIndex DCU data register index
+ * This parameter can be one of the macros group @ref DCU_Data_Register_Index
+ * @arg DCU_DATA0_IDX: DCU DATA0
+ * @arg DCU_DATA1_IDX: DCU DATA1
+ * @arg DCU_DATA2_IDX: DCU DATA2
+ * @param [in] u16Data The data to write.
+ * @retval None
+ */
+void DCU_WriteData16(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint16_t u16Data)
+{
+ __IO uint16_t *DATA;
+
+ DDL_ASSERT(IS_DCU_UNIT(DCUx));
+ DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex));
+
+ DATA = &DCU_DATA_REG16(DCUx, u32DataIndex);
+ WRITE_REG16(*DATA, u16Data);
+}
+
+/**
+ * @brief Read DCU register DATA for word.
+ * @param [in] DCUx Pointer to DCU instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_DCU or CM_DCUx: DCU instance register base
+ * @param [in] u32DataIndex DCU data register index
+ * This parameter can be one of the macros group @ref DCU_Data_Register_Index
+ * @arg DCU_DATA0_IDX: DCU DATA0
+ * @arg DCU_DATA1_IDX: DCU DATA1
+ * @arg DCU_DATA2_IDX: DCU DATA2
+ * @retval DCU register DATA value for word
+ */
+uint32_t DCU_ReadData32(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex)
+{
+ DDL_ASSERT(IS_DCU_UNIT(DCUx));
+ DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex));
+
+ return READ_REG32(DCU_DATA_REG32(DCUx, u32DataIndex));
+}
+
+/**
+ * @brief Write DCU register DATA0 for word.
+ * @param [in] DCUx Pointer to DCU instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_DCU or CM_DCUx: DCU instance register base
+ * @param [in] u32DataIndex DCU data register index
+ * This parameter can be one of the macros group @ref DCU_Data_Register_Index
+ * @arg DCU_DATA0_IDX: DCU DATA0
+ * @arg DCU_DATA1_IDX: DCU DATA1
+ * @arg DCU_DATA2_IDX: DCU DATA2
+ * @param [in] u32Data The data to write.
+ * @retval None
+ */
+void DCU_WriteData32(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint32_t u32Data)
+{
+ __IO uint32_t *DATA;
+
+ DDL_ASSERT(IS_DCU_UNIT(DCUx));
+ DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex));
+
+ DATA = &DCU_DATA_REG32(DCUx, u32DataIndex);
+ WRITE_REG32(*DATA, u32Data);
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_DCU_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_dma.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_dma.c
new file mode 100644
index 0000000000..c92e778f3a
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_dma.c
@@ -0,0 +1,1357 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_dma.c
+ * @brief This file provides firmware functions to manage the Direct Memory
+ * Access (DMA).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-01-15 CDT Modify API DMA_DeInit and add LLP address assert
+ 2023-06-30 CDT Modify typo
+ Add API DMA_UnitDeInit()
+ Modify blocksize assert, 1024U is valid
+ Add API DMA_SetDataWidth()
+ 2023-12-15 CDT Add DMA Repeat size assert
+ Modify API input param type:u16->u32
+ Use macros replace immediate data, modify IS_DMA_NON_SEQ_TRANS_CNT
+ Add API DMA_ReconfigNonSeqStructInit() & DMA_ReconfigNonSeqInit()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_dma.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_DMA DMA
+ * @brief Direct Memory Access Driver Library
+ * @{
+ */
+
+#if (LL_DMA_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup DMA_Local_Macros DMA Local Macros
+ * @{
+ */
+#define DMA_CH_REG(reg_base, ch) (*(__IO uint32_t *)((uint32_t)(&(reg_base)) + ((ch) * 0x40UL)))
+
+#define DMA_RMU_TIMEOUT (100U)
+
+/**
+ * @defgroup DMA_Check_Parameters_Validity DMA Check Parameters Validity
+ * @{
+ */
+/* Parameter valid check for DMA unit. */
+#define IS_DMA_UNIT(x) \
+( ((x) == CM_DMA1) || \
+ ((x) == CM_DMA2))
+
+/* Parameter valid check for DMA channel. */
+#define IS_DMA_CH(x) ((x) <= DMA_CH7)
+
+/* Parameter valid check for DMA multiplex channel. */
+#define IS_DMA_MX_CH(x) \
+( ((x) != 0x00UL) && \
+ (((x) | DMA_MX_CH_ALL) == DMA_MX_CH_ALL))
+
+/* Parameter valid check for DMA block size. */
+#define IS_DMA_BLOCK_SIZE(x) ((x) <= 1024UL)
+
+/* Parameter valid check for DMA repeat block size. */
+#define IS_DMA_REPEAT_SIZE(x) ((x) <= 1024UL)
+#define IS_DMA_RC_REPEAT_SIZE(x) (((x) > 0U) && ((x) < 1024U))
+
+/* Parameter valid check for DMA non-sequence transfer count. */
+#define IS_DMA_NON_SEQ_TRANS_CNT(x) ((x) <= 4096U)
+#define IS_DMA_RC_NON_SEQ_TRANS_CNT(x) (((x) > 0U) && ((x) < 4096U))
+
+/* Parameter valid check for DMA non-sequence offset. */
+#define IS_DMA_NON_SEQ_OFFSET(x) ((x) <= DMA_SNSEQCTL_SOFFSET)
+#define IS_DMA_RC_NON_SEQ_DIST(x) ((x) <= DMA_SNSEQCTLB_SNSDIST)
+
+/* Parameter valid check for DMA LLP function. */
+#define IS_DMA_LLP_EN(x) \
+( ((x) == DMA_LLP_ENABLE) || \
+ ((x) == DMA_LLP_DISABLE))
+
+/* Parameter valid check for DMA linked-list-pointer mode. */
+#define IS_DMA_LLP_MD(x) \
+( ((x) == DMA_LLP_RUN) || \
+ ((x) == DMA_LLP_WAIT))
+
+/* Parameter valid check for address alignment of DMA linked-list-pointer descriptor */
+#define IS_DMA_LLP_ADDR_ALIGN(x) IS_ADDR_ALIGN_WORD(x)
+
+/* Parameter valid check for DMA error flag. */
+#define IS_DMA_ERR_FLAG(x) \
+( ((x)!= 0x00000000UL) && \
+ (((x)| DMA_FLAG_ERR_MASK) == DMA_FLAG_ERR_MASK))
+
+/* Parameter valid check for DMA transfer flag. */
+#define IS_DMA_TRANS_FLAG(x) \
+( ((x)!= 0x00000000UL) && \
+ (((x)| DMA_FLAG_TRANS_MASK) == DMA_FLAG_TRANS_MASK))
+
+/* Parameter valid check for DMA error interrupt. */
+#define IS_DMA_ERR_INT(x) \
+( ((x)!= 0x00000000UL) && \
+ (((x)| DMA_INT_ERR_MASK) == DMA_INT_ERR_MASK))
+
+/* Parameter valid check for DMA transfer interrupt. */
+#define IS_DMA_TRANS_INT(x) \
+( ((x)!= 0x00000000UL) && \
+ (((x)| DMA_INT_TRANS_MASK) == DMA_INT_TRANS_MASK))
+
+/* Parameter valid check for DMA request status. */
+#define IS_DMA_REQ_STAT(x) \
+( ((x) != 0x00000000UL) && \
+ (((x) | DMA_STAT_REQ_MASK) == DMA_STAT_REQ_MASK))
+
+/* Parameter valid check for DMA transfer status. */
+#define IS_DMA_TRANS_STAT(x) \
+( ((x) != 0x00000000UL) && \
+ (((x) | DMA_STAT_TRANS_MASK) == DMA_STAT_TRANS_MASK))
+
+/* Parameter valid check for DMA transfer data width. */
+#define IS_DMA_DATA_WIDTH(x) \
+( ((x) == DMA_DATAWIDTH_8BIT) || \
+ ((x) == DMA_DATAWIDTH_16BIT) || \
+ ((x) == DMA_DATAWIDTH_32BIT))
+
+/* Parameter valid check for DMA source address mode. */
+#define IS_DMA_SADDR_MD(x) \
+( ((x) == DMA_SRC_ADDR_FIX) || \
+ ((x) == DMA_SRC_ADDR_INC) || \
+ ((x) == DMA_SRC_ADDR_DEC))
+
+/* Parameter valid check for DMA destination address mode. */
+#define IS_DMA_DADDR_MD(x) \
+( ((x) == DMA_DEST_ADDR_FIX) || \
+ ((x) == DMA_DEST_ADDR_INC) || \
+ ((x) == DMA_DEST_ADDR_DEC))
+
+/* Parameter valid check for DMA repeat mode. */
+#define IS_DMA_RPT_MD(x) \
+( ((x) == DMA_RPT_NONE) || \
+ ((x) == DMA_RPT_SRC) || \
+ ((x) == DMA_RPT_DEST) || \
+ ((x) == DMA_RPT_BOTH))
+
+/* Parameter valid check for DMA non_sequence mode. */
+#define IS_DMA_NON_SEQ_MD(x) \
+( ((x) == DMA_NON_SEQ_NONE) || \
+ ((x) == DMA_NON_SEQ_SRC) || \
+ ((x) == DMA_NON_SEQ_DEST) || \
+ ((x) == DMA_NON_SEQ_BOTH))
+
+/* Parameter valid check for DMA global interrupt function. */
+#define IS_DMA_INT_FUNC(x) \
+( ((x) == DMA_INT_ENABLE) || \
+ ((x) == DMA_INT_DISABLE))
+
+/* Parameter valid check for DMA reconfig count mode. */
+#define IS_DMA_RC_CNT_MD(x) \
+( ((x) == DMA_RC_CNT_KEEP) || \
+ ((x) == DMA_RC_CNT_SRC) || \
+ ((x) == DMA_RC_CNT_DEST))
+
+/* Parameter valid check for DMA reconfig destination address mode. */
+#define IS_DMA_RC_DA_MD(x) \
+( ((x) == DMA_RC_DEST_ADDR_KEEP) || \
+ ((x) == DMA_RC_DEST_ADDR_NS) || \
+ ((x) == DMA_RC_DEST_ADDR_RPT))
+
+/* Parameter valid check for DMA reconfig source address mode. */
+#define IS_DMA_RC_SA_MD(x) \
+( ((x) == DMA_RC_SRC_ADDR_KEEP) || \
+ ((x) == DMA_RC_SRC_ADDR_NS) || \
+ ((x) == DMA_RC_SRC_ADDR_RPT))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup DMA_Global_Functions DMA Global Functions
+ * @{
+ */
+
+/**
+ * @brief DMA global function config.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void DMA_Cmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ /* Global setting, ENABLE or DISABLE DMA */
+ WRITE_REG32(DMAx->EN, enNewState);
+}
+
+/**
+ * @brief DMA error IRQ function config.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u32ErrInt DMA error IRQ flag. @ref DMA_Int_Request_Err_Sel, @ref DMA_Int_Trans_Err_Sel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void DMA_ErrIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32ErrInt, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_ERR_INT(u32ErrInt));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (DISABLE == enNewState) {
+ SET_REG32_BIT(DMAx->INTMASK0, u32ErrInt);
+ } else {
+ CLR_REG32_BIT(DMAx->INTMASK0, u32ErrInt);
+ }
+}
+
+/**
+ * @brief Get DMA error flag.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u32Flag DMA error IRQ flag. @ref DMA_Flag_Trans_Err_Sel, @ref DMA_Flag_Request_Err_Sel
+ * @retval An @ref en_flag_status_t enumeration type value.
+ * @note Include transfer error flag & request error flag
+ */
+en_flag_status_t DMA_GetErrStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_ERR_FLAG(u32Flag));
+
+ return (0U != READ_REG32_BIT(DMAx->INTSTAT0, u32Flag) ? SET : RESET);
+}
+
+/**
+ * @brief Clear DMA error flag.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u32Flag DMA error IRQ flag. @ref DMA_Flag_Trans_Err_Sel, @ref DMA_Flag_Request_Err_Sel
+ * @retval None
+ * @note Include transfer error flag & request error flag
+ */
+void DMA_ClearErrStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_ERR_FLAG(u32Flag));
+
+ SET_REG32_BIT(DMAx->INTCLR0, u32Flag);
+}
+
+/**
+ * @brief DMA transfer IRQ function config.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u32TransCompleteInt DMA transfer complete IRQ flag. @ref DMA_Int_Btc_Sel, @ref DMA_Int_Tc_Sel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void DMA_TransCompleteIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32TransCompleteInt, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_TRANS_INT(u32TransCompleteInt));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (DISABLE == enNewState) {
+ SET_REG32_BIT(DMAx->INTMASK1, u32TransCompleteInt);
+ } else {
+ CLR_REG32_BIT(DMAx->INTMASK1, u32TransCompleteInt);
+ }
+}
+
+/**
+ * @brief Get DMA transfer flag.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u32Flag DMA transfer IRQ flag. @ref DMA_Flag_Btc_Sel, @ref DMA_Flag_Tc_Sel
+ * @retval An @ref en_flag_status_t enumeration type value.
+ * @note Include transfer complete flag & block transfer complete flag
+ */
+en_flag_status_t DMA_GetTransCompleteStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag)
+{
+ DDL_ASSERT(IS_DMA_TRANS_FLAG(u32Flag));
+ return ((0U != READ_REG32_BIT(DMAx->INTSTAT1, u32Flag)) ? SET : RESET);
+}
+
+/**
+ * @brief Clear DMA transfer flag.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u32Flag DMA transfer complete flag. @ref DMA_Flag_Btc_Sel, @ref DMA_Flag_Tc_Sel
+ * @retval None
+ * @note Include transfer complete flag & block transfer complete flag
+ */
+void DMA_ClearTransCompleteStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_TRANS_FLAG(u32Flag));
+
+ SET_REG32_BIT(DMAx->INTCLR1, u32Flag);
+}
+
+/**
+ * @brief DMA multiplex channel function config.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8MxCh DMA multiplex channel. @ref DMA_Mx_Channel_selection
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void DMA_MxChCmd(CM_DMA_TypeDef *DMAx, uint8_t u8MxCh, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_MX_CH(u8MxCh));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ WRITE_REG32(DMAx->CHEN, u8MxCh);
+ } else {
+ WRITE_REG32(DMAx->CHENCLR, u8MxCh);
+ }
+}
+
+/**
+ * @brief DMA channel function config.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval int32_t
+ */
+int32_t DMA_ChCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ WRITE_REG32(DMAx->CHEN, ((1UL << u8Ch) & DMA_CHEN_CHEN));
+ } else {
+ WRITE_REG32(DMAx->CHENCLR, ((1UL << u8Ch) & DMA_CHENCLR_CHENCLR));
+ }
+
+ return LL_OK;
+}
+
+/**
+ * @brief Get DMA transfer status.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u32Status DMA transfer status. @ref DMA_Trans_Status_Sel
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t DMA_GetTransStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_TRANS_STAT(u32Status));
+
+ return ((0U != READ_REG32_BIT(DMAx->CHSTAT, u32Status)) ? SET : RESET);
+}
+
+/**
+ * @brief Get DMA request status.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u32Status DMA request status. @ref DMA_Req_Status_Sel
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t DMA_GetRequestStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_REQ_STAT(u32Status));
+
+ return ((0U != READ_REG32_BIT(DMAx->REQSTAT, u32Status)) ? SET : RESET);
+}
+
+/**
+ * @brief Config DMA source address.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @param [in] u32Addr DMA source address.
+ * @retval int32_t
+ */
+int32_t DMA_SetSrcAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+
+ WRITE_REG32(DMA_CH_REG(DMAx->SAR0, u8Ch), u32Addr);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Config DMA destination address.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @param [in] u32Addr DMA destination address.
+ * @retval int32_t
+ */
+int32_t DMA_SetDestAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+
+ WRITE_REG32(DMA_CH_REG(DMAx->DAR0, u8Ch), u32Addr);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Config DMA transfer count.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @param [in] u16Count DMA transfer count (0: infinite, 1 ~ 65535).
+ * @retval int32_t
+ */
+int32_t DMA_SetTransCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Count)
+{
+ __IO uint32_t *DTCTLx;
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+
+ DTCTLx = &DMA_CH_REG(DMAx->DTCTL0, u8Ch);
+ MODIFY_REG32(*DTCTLx, DMA_DTCTL_CNT, ((uint32_t)(u16Count) << DMA_DTCTL_CNT_POS));
+ return LL_OK;
+}
+
+/**
+ * @brief Config DMA block size per transfer.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @param [in] u16Size DMA block size (range: 0~1024, 0 is for 1024).
+ * @retval int32_t
+ */
+int32_t DMA_SetBlockSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size)
+{
+ __IO uint32_t *DTCTLx;
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+ DDL_ASSERT(IS_DMA_BLOCK_SIZE(u16Size));
+
+ DTCTLx = &DMA_CH_REG(DMAx->DTCTL0, u8Ch);
+ MODIFY_REG32(*DTCTLx, DMA_DTCTL_BLKSIZE, u16Size);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Config DMA data width per transfer.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @param [in] u32DataWidth DMA data width. @ref DMA_DataWidth_Sel
+ * @retval int32_t
+ */
+int32_t DMA_SetDataWidth(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32DataWidth)
+{
+ __IO uint32_t *CHxCTL0;
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+ DDL_ASSERT(IS_DMA_DATA_WIDTH(u32DataWidth));
+
+ CHxCTL0 = &DMA_CH_REG(DMAx->CHCTL0, u8Ch);
+ MODIFY_REG32(*CHxCTL0, DMA_CHCTL_HSIZE, u32DataWidth);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Config DMA source repeat size.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @param [in] u32Size DMA source repeat size (0, 1024: 1024, 1 ~ 1023).
+ * @retval int32_t
+ */
+int32_t DMA_SetSrcRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Size)
+{
+ __IO uint32_t *RPTx;
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+ DDL_ASSERT(IS_DMA_REPEAT_SIZE(u32Size));
+
+ RPTx = &DMA_CH_REG(DMAx->RPT0, u8Ch);
+ MODIFY_REG32(*RPTx, DMA_RPT_SRPT, (u32Size << DMA_RPT_SRPT_POS));
+
+ return LL_OK;
+}
+
+/**
+ * @brief Config DMA destination repeat size.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @param [in] u32Size DMA destination repeat size (0, 1024: 1024, 1 ~ 1023).
+ * @retval int32_t
+ */
+int32_t DMA_SetDestRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Size)
+{
+ __IO uint32_t *RPTx;
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+ DDL_ASSERT(IS_DMA_REPEAT_SIZE(u32Size));
+
+ RPTx = &DMA_CH_REG(DMAx->RPT0, u8Ch);
+ MODIFY_REG32(*RPTx, DMA_RPT_DRPT, (u32Size << DMA_RPT_DRPT_POS));
+
+ return LL_OK;
+}
+
+/**
+ * @brief Config DMA source transfer count under non-sequence mode.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @param [in] u32Count DMA source transfer count (0, 4096: 4096, 1 ~ 4095).
+ * @retval int32_t
+ */
+int32_t DMA_SetNonSeqSrcCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count)
+{
+ __IO uint32_t *SNSEQCTLx;
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+ DDL_ASSERT(IS_DMA_NON_SEQ_TRANS_CNT(u32Count));
+
+ SNSEQCTLx = &DMA_CH_REG(DMAx->SNSEQCTL0, u8Ch);
+ MODIFY_REG32(*SNSEQCTLx, DMA_SNSEQCTL_SNSCNT, (u32Count << DMA_SNSEQCTL_SNSCNT_POS));
+
+ return LL_OK;
+}
+
+/**
+ * @brief Config DMA destination transfer count under non-sequence mode.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @param [in] u32Count DMA destination transfer count (0, 4096: 4096, 1 ~ 4095).
+ * @retval int32_t
+ */
+int32_t DMA_SetNonSeqDestCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count)
+{
+ __IO uint32_t *DNSEQCTLx;
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+ DDL_ASSERT(IS_DMA_NON_SEQ_TRANS_CNT(u32Count));
+
+ DNSEQCTLx = &DMA_CH_REG(DMAx->DNSEQCTL0, u8Ch);
+ MODIFY_REG32(*DNSEQCTLx, DMA_DNSEQCTL_DNSCNT, (u32Count << DMA_DNSEQCTL_DNSCNT_POS));
+
+ return LL_OK;
+}
+
+/**
+ * @brief Config DMA source offset number under non-sequence mode.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @param [in] u32Offset DMA source offset (0 ~ 2^20 - 1).
+ * @retval int32_t
+ */
+int32_t DMA_SetNonSeqSrcOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset)
+{
+ __IO uint32_t *SNSEQCTLx;
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+ DDL_ASSERT(IS_DMA_NON_SEQ_OFFSET(u32Offset));
+
+ SNSEQCTLx = &DMA_CH_REG(DMAx->SNSEQCTL0, u8Ch);
+ MODIFY_REG32(*SNSEQCTLx, DMA_SNSEQCTL_SOFFSET, u32Offset);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Config DMA destination offset number under non-sequence mode.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @param [in] u32Offset DMA destination offset (0 ~ 2^20 - 1).
+ * @retval int32_t
+ */
+int32_t DMA_SetNonSeqDestOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset)
+{
+ __IO uint32_t *DNSEQCTLx;
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+ DDL_ASSERT(IS_DMA_NON_SEQ_OFFSET(u32Offset));
+
+ DNSEQCTLx = &DMA_CH_REG(DMAx->DNSEQCTL0, u8Ch);
+ MODIFY_REG32(*DNSEQCTLx, DMA_DNSEQCTL_DOFFSET, u32Offset);
+
+ return LL_OK;
+}
+
+/**
+ * @brief De-Initialize DMA channel function.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @retval None
+ */
+void DMA_DeInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+
+ /* Disable */
+ SET_REG32_BIT(DMAx->CHENCLR, DMA_CHENCLR_CHENCLR_0 << u8Ch);
+
+ /* Set default value. */
+ WRITE_REG32(DMA_CH_REG(DMAx->SAR0, u8Ch), 0UL);
+ WRITE_REG32(DMA_CH_REG(DMAx->DAR0, u8Ch), 0UL);
+ CLR_REG32_BIT(DMAx->INTMASK0, (DMA_INTMASK0_MSKTRNERR_0 | DMA_INTMASK0_MSKREQERR_0) << u8Ch);
+ CLR_REG32_BIT(DMAx->INTMASK1, (DMA_INTMASK1_MSKTC_0 | DMA_INTMASK1_MSKBTC_0) << u8Ch);
+ SET_REG32_BIT(DMAx->INTCLR0, (DMA_INTCLR0_CLRTRNERR_0 | DMA_INTCLR0_CLRREQERR_0) << u8Ch);
+ SET_REG32_BIT(DMAx->INTCLR1, (DMA_INTCLR1_CLRTC_0 | DMA_INTCLR1_CLRBTC_0) << u8Ch);
+
+ WRITE_REG32(DMA_CH_REG(DMAx->DTCTL0, u8Ch), 1UL);
+ WRITE_REG32(DMA_CH_REG(DMAx->CHCTL0, u8Ch), 0x00001000UL);
+ WRITE_REG32(DMA_CH_REG(DMAx->RPT0, u8Ch), 0UL);
+ WRITE_REG32(DMA_CH_REG(DMAx->SNSEQCTL0, u8Ch), 0UL);
+ WRITE_REG32(DMA_CH_REG(DMAx->DNSEQCTL0, u8Ch), 0UL);
+ WRITE_REG32(DMA_CH_REG(DMAx->LLP0, u8Ch), 0UL);
+
+}
+
+/**
+ * @brief De-Initialize DMA function.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @retval int32_t:
+ * - LL_OK: Reset success.
+ * - LL_ERR_TIMEOUT: Reset time out.
+ */
+int32_t DMA_UnitDeInit(CM_DMA_TypeDef *DMAx)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint8_t u8TimeOut = 0U;
+ __IO uint32_t *bCM_RMU_FRST0_DMAx;
+
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1);
+
+ if (CM_DMA1 == DMAx) {
+ bCM_RMU_FRST0_DMAx = &bCM_RMU->FRST0_b.DMA1;
+ } else {
+ bCM_RMU_FRST0_DMAx = &bCM_RMU->FRST0_b.DMA2;
+ }
+ /* Reset DMA */
+ WRITE_REG32(*bCM_RMU_FRST0_DMAx, 0UL);
+ /* Ensure reset procedure is completed */
+ while (READ_REG32(*bCM_RMU_FRST0_DMAx) != 1UL) {
+ u8TimeOut++;
+ if (u8TimeOut > DMA_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize DMA config structure. Fill each pstcDmaInit with default value
+ * @param [in] pstcDmaInit Pointer to a stc_dma_init_t structure that
+ * contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: DMA structure initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t DMA_StructInit(stc_dma_init_t *pstcDmaInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcDmaInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ pstcDmaInit->u32IntEn = DMA_INT_DISABLE;
+ pstcDmaInit->u32SrcAddr = 0x00UL;
+ pstcDmaInit->u32DestAddr = 0x00UL;
+ pstcDmaInit->u32DataWidth = DMA_DATAWIDTH_8BIT;
+ pstcDmaInit->u32BlockSize = 0x01UL;
+ pstcDmaInit->u32TransCount = 0x00UL;
+ pstcDmaInit->u32SrcAddrInc = DMA_SRC_ADDR_FIX;
+ pstcDmaInit->u32DestAddrInc = DMA_DEST_ADDR_FIX;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief DMA basic function initialize.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @param [in] pstcDmaInit DMA config structure.
+ * @arg u32IntEn DMA interrupt ENABLE or DISABLE.
+ * @arg u32SrcAddr DMA source address.
+ * @arg u32DestAddr DMA destination address.
+ * @arg u32DataWidth DMA data width.
+ * @arg u32BlockSize DMA block size.
+ * @arg u32TransCount DMA transfer count.
+ * @arg u32SrcAddrInc DMA source address direction.
+ * @arg u32DestAddrInc DMA destination address direction.
+ * @retval int32_t:
+ * - LL_OK: DMA basic function initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t DMA_Init(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_init_t *pstcDmaInit)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t *CHCTLx;
+
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+
+ if (NULL == pstcDmaInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ DDL_ASSERT(IS_DMA_DATA_WIDTH(pstcDmaInit->u32DataWidth));
+ DDL_ASSERT(IS_DMA_SADDR_MD(pstcDmaInit->u32SrcAddrInc));
+ DDL_ASSERT(IS_DMA_DADDR_MD(pstcDmaInit->u32DestAddrInc));
+ DDL_ASSERT(IS_DMA_BLOCK_SIZE(pstcDmaInit->u32BlockSize));
+ DDL_ASSERT(IS_DMA_INT_FUNC(pstcDmaInit->u32IntEn));
+
+ WRITE_REG32(DMA_CH_REG(DMAx->SAR0, u8Ch), pstcDmaInit->u32SrcAddr);
+ WRITE_REG32(DMA_CH_REG(DMAx->DAR0, u8Ch), pstcDmaInit->u32DestAddr);
+
+ WRITE_REG32(DMA_CH_REG(DMAx->DTCTL0, u8Ch), ((pstcDmaInit->u32BlockSize & DMA_DTCTL_BLKSIZE) | \
+ (pstcDmaInit->u32TransCount << DMA_DTCTL_CNT_POS)));
+
+ CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch);
+ MODIFY_REG32(*CHCTLx, (DMA_CHCTL_SINC | DMA_CHCTL_DINC | DMA_CHCTL_HSIZE | DMA_CHCTL_IE), \
+ (pstcDmaInit->u32IntEn | pstcDmaInit->u32DataWidth | pstcDmaInit->u32SrcAddrInc | \
+ pstcDmaInit->u32DestAddrInc));
+
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize DMA repeat mode config structure.
+ * Fill each pstcDmaInit with default value
+ * @param [in] pstcDmaRepeatInit Pointer to a stc_dma_repeat_init_t structure that
+ * contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: DMA repeat mode config structure initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t DMA_RepeatStructInit(stc_dma_repeat_init_t *pstcDmaRepeatInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcDmaRepeatInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ pstcDmaRepeatInit->u32Mode = DMA_RPT_NONE;
+ pstcDmaRepeatInit->u32SrcCount = 0x00UL;
+ pstcDmaRepeatInit->u32DestCount = 0x00UL;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief DMA repeat mode initialize.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @param [in] pstcDmaRepeatInit DMA repeat mode config structure.
+ * @note Call this function after DMA_Init();
+ */
+int32_t DMA_RepeatInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_repeat_init_t *pstcDmaRepeatInit)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t *CHCTLx;
+
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+
+ if (NULL == pstcDmaRepeatInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ DDL_ASSERT(IS_DMA_RPT_MD(pstcDmaRepeatInit->u32Mode));
+ DDL_ASSERT(IS_DMA_REPEAT_SIZE(pstcDmaRepeatInit->u32DestCount));
+ DDL_ASSERT(IS_DMA_REPEAT_SIZE(pstcDmaRepeatInit->u32SrcCount));
+
+ CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch);
+ MODIFY_REG32(*CHCTLx, (DMA_CHCTL_SRPTEN | DMA_CHCTL_DRPTEN), pstcDmaRepeatInit->u32Mode);
+
+ WRITE_REG32(DMA_CH_REG(DMAx->RPT0, u8Ch), \
+ ((pstcDmaRepeatInit->u32DestCount << DMA_RPT_DRPT_POS) | pstcDmaRepeatInit->u32SrcCount) & \
+ (DMA_RPT_DRPT | DMA_RPT_SRPT));
+
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize DMA non-sequence mode config structure.
+ * Fill each pstcDmaInit with default value
+ * @param [in] pstcDmaNonSeqInit Pointer to a stc_dma_nonseq_init_t structure that
+ * contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: DMA non-sequence mode structure initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t DMA_NonSeqStructInit(stc_dma_nonseq_init_t *pstcDmaNonSeqInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcDmaNonSeqInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ pstcDmaNonSeqInit->u32Mode = DMA_NON_SEQ_NONE;
+ pstcDmaNonSeqInit->u32SrcCount = 0x00UL;
+ pstcDmaNonSeqInit->u32SrcOffset = 0x00UL;
+ pstcDmaNonSeqInit->u32DestCount = 0x00UL;
+ pstcDmaNonSeqInit->u32DestOffset = 0x00UL;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief DMA non-sequence mode initialize.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @param [in] pstcDmaNonSeqInit DMA non-sequence mode config structure.
+ * @retval int32_t:
+ * - LL_OK: DMA non-sequence function initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ * @note Call this function after DMA_Init();
+ */
+int32_t DMA_NonSeqInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_nonseq_init_t *pstcDmaNonSeqInit)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t *CHCTLx;
+
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+
+ if (NULL == pstcDmaNonSeqInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ DDL_ASSERT(IS_DMA_NON_SEQ_MD(pstcDmaNonSeqInit->u32Mode));
+
+ DDL_ASSERT(IS_DMA_NON_SEQ_TRANS_CNT(pstcDmaNonSeqInit->u32SrcCount));
+ DDL_ASSERT(IS_DMA_NON_SEQ_TRANS_CNT(pstcDmaNonSeqInit->u32DestCount));
+ DDL_ASSERT(IS_DMA_NON_SEQ_OFFSET(pstcDmaNonSeqInit->u32SrcOffset));
+ DDL_ASSERT(IS_DMA_NON_SEQ_OFFSET(pstcDmaNonSeqInit->u32DestOffset));
+
+ CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch);
+ MODIFY_REG32(*CHCTLx, (DMA_CHCTL_SNSEQEN | DMA_CHCTL_DNSEQEN), pstcDmaNonSeqInit->u32Mode);
+
+ WRITE_REG32(DMA_CH_REG(DMAx->SNSEQCTL0, u8Ch), ((pstcDmaNonSeqInit->u32SrcCount << DMA_SNSEQCTL_SNSCNT_POS) | \
+ pstcDmaNonSeqInit->u32SrcOffset));
+ WRITE_REG32(DMA_CH_REG(DMAx->DNSEQCTL0, u8Ch), ((pstcDmaNonSeqInit->u32DestCount << DMA_DNSEQCTL_DNSCNT_POS) | \
+ pstcDmaNonSeqInit->u32DestOffset));
+
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize DMA Linked List Pointer (hereafter, LLP) mode config structure.
+ * Fill each pstcDmaInit with default value
+ * @param [in] pstcDmaLlpInit Pointer to a stc_dma_llp_init_t structure that
+ * contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: DMA LLP mode config structure initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t DMA_LlpStructInit(stc_dma_llp_init_t *pstcDmaLlpInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcDmaLlpInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ pstcDmaLlpInit->u32State = DMA_LLP_DISABLE;
+ pstcDmaLlpInit->u32Mode = DMA_LLP_WAIT;
+ pstcDmaLlpInit->u32Addr = 0x00UL;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief DMA LLP mode initialize.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @param [in] pstcDmaLlpInit DMA LLP config structure.
+ * @arg u32State DMA LLP ENABLE or DISABLE.
+ * @arg u32Mode DMA LLP auto-run or wait request.
+ * @arg u32Addr DMA LLP next list pointer address.
+ * @arg u32AddrSelect DMA LLP address mode.
+ * @retval int32_t:
+ * - LL_OK: DMA LLP function initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ * @note Call this function after DMA_Init();
+ */
+int32_t DMA_LlpInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_llp_init_t *pstcDmaLlpInit)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t *CHCTLx;
+
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+
+ if (NULL == pstcDmaLlpInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ DDL_ASSERT(IS_DMA_LLP_EN(pstcDmaLlpInit->u32State));
+ DDL_ASSERT(IS_DMA_LLP_MD(pstcDmaLlpInit->u32Mode));
+ DDL_ASSERT(IS_DMA_LLP_ADDR_ALIGN(pstcDmaLlpInit->u32Addr));
+
+ CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch);
+ MODIFY_REG32(*CHCTLx, (DMA_CHCTL_LLPEN | DMA_CHCTL_LLPRUN), \
+ (pstcDmaLlpInit->u32State | pstcDmaLlpInit->u32Mode));
+
+ WRITE_REG32(DMA_CH_REG(DMAx->LLP0, u8Ch), pstcDmaLlpInit->u32Addr & DMA_LLP_LLP);
+
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Config DMA LLP value.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @param [in] u32Addr Next link pointer address for DMA LLP mode.
+ * @retval None
+ */
+void DMA_SetLlpAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr)
+{
+
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+ DDL_ASSERT(IS_DMA_LLP_ADDR_ALIGN(u32Addr));
+
+ WRITE_REG32(DMA_CH_REG(DMAx->LLP0, u8Ch), (u32Addr & DMA_LLP_LLP));
+}
+
+/**
+ * @brief DMA LLP ENABLE or DISABLE.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void DMA_LlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(DMA_CH_REG(DMAx->CHCTL0, u8Ch), DMA_CHCTL_LLPEN);
+
+ } else {
+ CLR_REG32_BIT(DMA_CH_REG(DMAx->CHCTL0, u8Ch), DMA_CHCTL_LLPEN);
+
+ }
+}
+
+/**
+ * @brief DMA reconfig function ENABLE or DISABLE.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void DMA_ReconfigCmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(DMAx->RCFGCTL, 1UL);
+ } else {
+ CLR_REG32_BIT(DMAx->RCFGCTL, 1UL);
+ }
+}
+
+/**
+ * @brief DMA LLP ENABLE or DISABLE for reconfig function.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void DMA_ReconfigLlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ MODIFY_REG32(DMAx->RCFGCTL, DMA_RCFGCTL_RCFGCHS | DMA_RCFGCTL_RCFGLLP, \
+ ((uint32_t)(u8Ch) << DMA_RCFGCTL_RCFGCHS_POS) | ((uint32_t)enNewState << DMA_RCFGCTL_RCFGLLP_POS));
+}
+
+/**
+ * @brief Initialize DMA re-config mode config structure.
+ * Fill each pstcDmaRCInit with default value
+ * @param [in] pstcDmaRCInit Pointer to a stc_dma_reconfig_init_t structure that
+ * contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: DMA reconfig mode config structure initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t DMA_ReconfigStructInit(stc_dma_reconfig_init_t *pstcDmaRCInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcDmaRCInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ pstcDmaRCInit->u32CountMode = DMA_RC_CNT_KEEP;
+ pstcDmaRCInit->u32DestAddrMode = DMA_RC_DEST_ADDR_KEEP;
+ pstcDmaRCInit->u32SrcAddrMode = DMA_RC_SRC_ADDR_KEEP;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief DMA reconfig mode initialize.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @param [in] pstcDmaRCInit DMA reconfig mode config structure
+ * @arg u32CountMode DMA reconfig count mode.
+ * @arg u32DestAddrMode DMA reconfig destination address mode.
+ * @arg u32SrcAddrMode DMA reconfig source address mode.
+ * @retval int32_t:
+ * - LL_OK: DMA reconfig function initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+*/
+int32_t DMA_ReconfigInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_reconfig_init_t *pstcDmaRCInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+
+ if (NULL == pstcDmaRCInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ DDL_ASSERT(IS_DMA_RC_CNT_MD(pstcDmaRCInit->u32CountMode));
+ DDL_ASSERT(IS_DMA_RC_DA_MD(pstcDmaRCInit->u32DestAddrMode));
+ DDL_ASSERT(IS_DMA_RC_SA_MD(pstcDmaRCInit->u32SrcAddrMode));
+
+ MODIFY_REG32(DMAx->RCFGCTL, \
+ (DMA_RCFGCTL_RCFGCHS | DMA_RCFGCTL_SARMD | DMA_RCFGCTL_DARMD | DMA_RCFGCTL_CNTMD), \
+ (pstcDmaRCInit->u32CountMode | pstcDmaRCInit->u32SrcAddrMode | \
+ pstcDmaRCInit->u32DestAddrMode | ((uint32_t)(u8Ch) << DMA_RCFGCTL_RCFGCHS_POS)));
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize DMA non-sequence mode config structure.
+ * Fill each pstcDmaInit with default value
+ * @param [in] pstcDmaRcNonSeqInit Pointer to a stc_dma_rc_nonseq_init_t structure that
+ * contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: DMA non-sequence mode structure initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t DMA_ReconfigNonSeqStructInit(stc_dma_rc_nonseq_init_t *pstcDmaRcNonSeqInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcDmaRcNonSeqInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ pstcDmaRcNonSeqInit->u32Mode = DMA_NON_SEQ_NONE;
+ pstcDmaRcNonSeqInit->u32SrcCount = 0x01UL;
+ pstcDmaRcNonSeqInit->u32SrcDist = 0x00UL;
+ pstcDmaRcNonSeqInit->u32DestCount = 0x01UL;
+ pstcDmaRcNonSeqInit->u32DestDist = 0x00UL;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief DMA non-sequence mode initialize.
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @param [in] pstcDmaRcNonSeqInit Pointer to a stc_dma_rc_nonseq_init_t structure that
+ * contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: DMA non-sequence function initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ * @note Call this function after DMA_Init();
+ */
+int32_t DMA_ReconfigNonSeqInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_rc_nonseq_init_t *pstcDmaRcNonSeqInit)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t *CHCTLx;
+
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+
+ if (NULL == pstcDmaRcNonSeqInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ DDL_ASSERT(IS_DMA_NON_SEQ_MD(pstcDmaRcNonSeqInit->u32Mode));
+ DDL_ASSERT(IS_DMA_RC_NON_SEQ_TRANS_CNT(pstcDmaRcNonSeqInit->u32SrcCount));
+ DDL_ASSERT(IS_DMA_RC_NON_SEQ_TRANS_CNT(pstcDmaRcNonSeqInit->u32DestCount));
+ DDL_ASSERT(IS_DMA_RC_NON_SEQ_DIST(pstcDmaRcNonSeqInit->u32SrcDist));
+ DDL_ASSERT(IS_DMA_RC_NON_SEQ_DIST(pstcDmaRcNonSeqInit->u32DestDist));
+
+ CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch);
+ MODIFY_REG32(*CHCTLx, (DMA_CHCTL_SNSEQEN | DMA_CHCTL_DNSEQEN), pstcDmaRcNonSeqInit->u32Mode);
+ WRITE_REG32(DMA_CH_REG(DMAx->SNSEQCTLB0, u8Ch),
+ ((pstcDmaRcNonSeqInit->u32SrcCount << DMA_SNSEQCTLB_SNSCNTB_POS) | pstcDmaRcNonSeqInit->u32SrcDist));
+ WRITE_REG32(DMA_CH_REG(DMAx->DNSEQCTLB0, u8Ch),
+ ((pstcDmaRcNonSeqInit->u32DestCount << DMA_DNSEQCTLB_DNSCNTB_POS) | pstcDmaRcNonSeqInit->u32DestDist));
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief DMA get current source address
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @retval Current source address.
+ */
+uint32_t DMA_GetSrcAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+
+ return READ_REG32(DMA_CH_REG(DMAx->MONSAR0, u8Ch));
+}
+
+/**
+ * @brief DMA get current destination address
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @retval Current destination address.
+ */
+uint32_t DMA_GetDestAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+
+ return READ_REG32(DMA_CH_REG(DMAx->MONDAR0, u8Ch));
+}
+
+/**
+ * @brief DMA get current transfer count
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @retval Current transfer count.
+ */
+uint32_t DMA_GetTransCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+
+ return ((READ_REG32(DMA_CH_REG(DMAx->MONDTCTL0, u8Ch)) >> DMA_DTCTL_CNT_POS) & 0xFFFFUL);
+}
+
+/**
+ * @brief DMA get current block size
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @retval Current block size.
+ */
+uint32_t DMA_GetBlockSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+
+ return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONDTCTL0, u8Ch), DMA_DTCTL_BLKSIZE));
+}
+
+/**
+ * @brief DMA get current source repeat size
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @retval Current source repeat size.
+ */
+uint32_t DMA_GetSrcRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+
+ return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONRPT0, u8Ch), DMA_RPT_SRPT));
+}
+
+/**
+ * @brief DMA get current destination repeat size
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @retval Current destination repeat size.
+ */
+uint32_t DMA_GetDestRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+
+ return ((READ_REG32(DMA_CH_REG(DMAx->MONRPT0, u8Ch)) >> DMA_RPT_DRPT_POS) & 0x3FFUL);
+}
+
+/**
+ * @brief DMA get current source count in non-sequence mode
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @retval Current source count in non-sequence mode.
+ */
+uint32_t DMA_GetNonSeqSrcCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+
+ return ((READ_REG32(DMA_CH_REG(DMAx->MONSNSEQCTL0, u8Ch)) >> DMA_SNSEQCTLB_SNSCNTB_POS) & 0xFFFUL);
+}
+
+/**
+ * @brief DMA get current destination count in non-sequence mode
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA,, x can be 0-1
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @retval Current destination count in non-sequence mode.
+ */
+uint32_t DMA_GetNonSeqDestCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+
+ return ((READ_REG32(DMA_CH_REG(DMAx->MONDNSEQCTL0, u8Ch)) >> DMA_DNSEQCTL_DNSCNT_POS) & 0xFFFUL);
+}
+
+/**
+ * @brief DMA get current source offset in non-sequence mode
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @retval Current source offset in non-sequence mode.
+ */
+uint32_t DMA_GetNonSeqSrcOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+
+ return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONSNSEQCTL0, u8Ch), DMA_SNSEQCTL_SOFFSET));
+}
+
+/**
+ * @brief DMA get current destination offset in non-sequence mode
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @retval Current destination offset in non-sequence mode.
+ */
+uint32_t DMA_GetNonSeqDestOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+
+ return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONDNSEQCTL0, u8Ch), DMA_DNSEQCTL_DOFFSET));
+}
+
+/**
+ * @brief Enable or disable AHB HPROT bufferable and cacheable transfer
+ * @param [in] DMAx DMA unit instance.
+ * @arg CM_DMAx or CM_DMA
+ * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ * @note This command can only be enabled when DMA accesses SMC, otherwise please disable it
+ */
+void DMA_AHB_HProtBufCacheCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_DMA_UNIT(DMAx));
+ DDL_ASSERT(IS_DMA_CH(u8Ch));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(DMA_CH_REG(DMAx->CHCTL0, u8Ch), DMA_CHCTL_HPROT);
+ } else {
+ CLR_REG32_BIT(DMA_CH_REG(DMAx->CHCTL0, u8Ch), DMA_CHCTL_HPROT);
+ }
+}
+/**
+ * @}
+ */
+
+#endif /* LL_DMA_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_efm.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_efm.c
new file mode 100644
index 0000000000..942234a9d6
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_efm.c
@@ -0,0 +1,1643 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_efm.c
+ * @brief This file provides firmware functions to manage the Embedded Flash
+ * Memory unit (EFM).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Modify typo
+ Use FNWPRT_REG to replace CM_EFM->F0NWPRT0
+ 2023-09-30 CDT Remove address assert from EFM_ReadByte()
+ Refine EFM_SequenceProgram() & EFM_ChipErase(), and put them in RAM
+ 2023-12-15 CDT Rename EFM_DataCacheResetCmd() as EFM_CacheRamReset() and modify comment
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_efm.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_EFM EFM
+ * @brief Embedded Flash Management Driver Library
+ * @{
+ */
+
+#if (LL_EFM_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup EFM_Local_Macros EFM Local Macros
+ * @{
+ */
+#ifndef __EFM_FUNC
+#define __EFM_FUNC __RAM_FUNC
+#endif
+
+/**
+ * @defgroup EFM_Timeout_Definition EFM timeout definition
+ * @{
+ */
+#define EFM_TIMEOUT (HCLK_VALUE / 20000UL) /* EFM wait read timeout */
+#define EFM_PGM_TIMEOUT (HCLK_VALUE / 20000UL) /* EFM Program timeout max 53us */
+#define EFM_ERASE_TIMEOUT (HCLK_VALUE / 50UL) /* EFM Erase timeout max 20ms */
+#define EFM_SEQ_PGM_TIMEOUT (HCLK_VALUE / 62500UL) /* EFM Sequence Program timeout max 16us */
+/**
+ * @}
+ */
+
+#define REMCR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_EFM->MMF_REMCR0) + (4UL * (x))))
+
+#define EFM_FLAG0_POS (0U)
+#define EFM_FLAG1_POS (16U)
+#define EFM_OTP_END_SECTOR_NUM (15U)
+
+#define EFM_FLASH1_START_SECTOR_NUM (32U)
+#define FNWPRT_REG (CM_EFM->F0NWPRT)
+
+#define REG_LEN (32U)
+#define EFM_SWAP_FLASH1_END_SECTOR_NUM (EFM_FLASH1_START_SECTOR_NUM + EFM_OTP_END_SECTOR_NUM)
+#define EFM_SWAP_FLASH1_END_ADDR (EFM_FLASH_1_START_ADDR + EFM_OTP_END_ADDR1)
+#define EFM_OTP_UNLOCK_KEY1 (0x10325476UL)
+#define EFM_OTP_UNLOCK_KEY2 (0xEFCDAB89UL)
+
+/**
+ * @defgroup EFM_Configuration_Bit_Mask EFM Configuration Bit Mask
+ * @{
+ */
+#define EFM_CACHE_ALL (EFM_FRMC_CRST | EFM_FRMC_PREFETE | EFM_FRMC_DCACHE | EFM_FRMC_ICACHE)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_SectorOperate EFM sector operate define
+ * @{
+ */
+#define EFM_FNWPRT_REG_OFFSET (4UL)
+#define EFM_FNWPRT_REG_NUM (2UL)
+#define EFM_FNWPRT_REG_END_ADDR (__IO uint32_t *)(uint32_t)(&CM_EFM->F1NWPRT)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_protect EFM protect define
+ * @{
+ */
+#define EFM_SECURITY_LEN (12UL)
+#define EFM_PROTECT1_KEY (0xAF180402UL)
+#define EFM_PROTECT2_KEY (0xA85173AEUL)
+
+#define EFM_PROTECT3_KEY (0x42545048UL)
+#define EFM_PROTECT1_ADDR (0x00000430UL)
+#define EFM_PROTECT2_ADDR (0x00000434UL)
+#define EFM_PROTECT3_ADDR1 (0x00000420UL)
+#define EFM_PROTECT3_ADDR2 (0x00000424UL)
+#define EFM_PROTECT3_ADDR3 (0x00000428UL)
+#define EFM_SECURITY_ADDR (0x03004000UL)
+
+#define EFM_SWAP_ON_PROTECT_SECTOR_NUM EFM_FLASH1_START_SECTOR_NUM
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_Check_Parameters_Validity EFM Check Parameters Validity
+ * @{
+ */
+/* Parameter validity check for efm chip . */
+#define IS_EFM_CHIP(x) \
+( ((x) == EFM_CHIP0) || \
+ ((x) == EFM_CHIP1) || \
+ ((x) == EFM_CHIP_ALL))
+
+/* Parameter validity check for flash latency. */
+#define IS_EFM_WAIT_CYCLE(x) ((x) <= EFM_WAIT_CYCLE15)
+
+/* Parameter validity check for operate mode. */
+#define IS_EFM_OPERATE_MD(x) \
+( ((x) == EFM_MD_PGM_SINGLE) || \
+ ((x) == EFM_MD_PGM_READBACK) || \
+ ((x) == EFM_MD_PGM_SEQ) || \
+ ((x) == EFM_MD_ERASE_SECTOR) || \
+ ((x) == EFM_MD_ERASE_ONE_CHIP) || \
+ ((x) == EFM_MD_ERASE_ALL_CHIP) || \
+ ((x) == EFM_MD_READONLY))
+
+/* Parameter validity check for efm status. */
+#define IS_EFM_STATUS(x) \
+( ((x) == EFM_FLASH0_ACT_FLASH1_ACT) || \
+ ((x) == EFM_FLASH0_STP_FLASH1_ACT) || \
+ ((x) == EFM_FLASH0_ACT_FLASH1_STP) || \
+ ((x) == EFM_FLASH0_STP_FLASH1_STP))
+
+/* Parameter validity check for flash interrupt select. */
+#define IS_EFM_INT_SEL(x) (((x) | EFM_INT_ALL) == EFM_INT_ALL)
+
+/* Parameter validity check for flash flag. */
+#define IS_EFM_FLAG(x) (((x) | EFM_FLAG_ALL) == EFM_FLAG_ALL)
+
+/* Parameter validity check for flash clear flag. */
+#define IS_EFM_CLRFLAG(x) (((x) | EFM_FLAG_ALL) == EFM_FLAG_ALL)
+
+/* Parameter validity check for bus status while flash program or erase. */
+#define IS_EFM_BUS_STATUS(x) \
+( ((x) == EFM_BUS_HOLD) || \
+ ((x) == EFM_BUS_RELEASE))
+
+/* Parameter validity check for efm address. */
+#define IS_EFM_ADDR(x) \
+( ((x) <= EFM_END_ADDR) || \
+ (((x) >= EFM_OTP_START_ADDR) && ((x) <= EFM_OTP_END_ADDR)) || \
+ (((x) >= EFM_SECURITY_START_ADDR) && ((x) <= EFM_SECURITY_END_ADDR)))
+
+/* Parameter validity check for efm erase address. */
+#define IS_EFM_ERASE_ADDR(x) \
+( ((x) <= EFM_END_ADDR) || \
+ (((x) >= EFM_OTP_START_ADDR) && ((x) <= EFM_OTP_END_ADDR)))
+
+/* Parameter validity check for efm erase mode . */
+#define IS_EFM_ERASE_MD(x) \
+( ((x) == EFM_MD_ERASE_ONE_CHIP) || \
+ ((x) == EFM_MD_ERASE_FULL))
+
+/* Parameter validity check for EFM lock status. */
+#define IS_EFM_REG_UNLOCK() (CM_EFM->FAPRT == 0x00000001UL)
+
+/* Parameter validity check for EFM_FWMC register lock status. */
+#define IS_EFM_FWMC_UNLOCK() (bCM_EFM->FWMC_b.KEY1LOCK == 0U)
+
+/* Parameter validity check for OTP lock status. */
+#define IS_EFM_OTP_UNLOCK() (bCM_EFM->FWMC_b.KEY2LOCK == 0U)
+
+/* Parameter validity check for sector protected register locking. */
+#define IS_EFM_SECTOR_PROTECT_REG_LOCK(x) (((x) & (EFM_WLOCK_WLOCK0 | EFM_WLOCK_WLOCK1)) != 0x00U)
+
+/* Parameter validity check for EFM sector number */
+#define IS_EFM_SECTOR_NUM(x) ((x) <= 64U)
+#define IS_EFM_SECTOR_IDX(x) ((x) < 64U)
+
+/* Parameter validity check for EFM remap lock status. */
+#define IS_EFM_REMAP_UNLOCK() (CM_EFM->MMF_REMPRT == 0x00000001UL)
+
+/* Parameter validity check for EFM remap index */
+#define IS_EFM_REMAP_IDX(x) \
+( ((x) == EFM_REMAP_IDX0) || \
+ ((x) == EFM_REMAP_IDX1))
+
+/* Parameter validity check for EFM remap size */
+#define IS_EFM_REMAP_SIZE(x) \
+( ((x) >= EFM_REMAP_4K) && \
+ ((x) <= EFM_REMAP_SIZE_MAX))
+
+/* Parameter validity check for EFM remap address */
+#define IS_EFM_REMAP_ADDR(x) \
+( ((x) <= EFM_REMAP_ROM_END_ADDR) || \
+ (((x) >= EFM_REMAP_RAM_START_ADDR) && \
+ ((x) <= EFM_REMAP_RAM_END_ADDR)))
+
+/* Parameter validity check for EFM remap state */
+#define IS_EFM_REMAP_STATE(x) \
+( ((x) == EFM_REMAP_OFF) || \
+ ((x) == EFM_REMAP_ON))
+
+/* Parameter validity check for EFM security code length */
+#define IS_EFM_SECURITY_CODE_LEN(x) ((x) <= EFM_SECURITY_LEN)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ * @defgroup EFM_Local_Functions EFM Local Functions
+ * @{
+ */
+/**
+ * @brief Wait EFM flag.
+ * @param [in] u32Flag Specifies the flag to be wait. @ref EFM_Flag_Sel
+ * @param [in] u32Time Specifies the time to wait while the flag not be set.
+ * @retval int32_t:
+ * - LL_OK: Flag was set.
+ * - LL_ERR_TIMEOUT: Flag was not set.
+ */
+static int32_t EFM_WaitFlag(uint32_t u32Flag, uint32_t u32Time)
+{
+ __IO uint32_t u32Timeout = 0UL;
+ int32_t i32Ret = LL_OK;
+
+ while (SET != EFM_GetStatus(u32Flag)) {
+ u32Timeout++;
+ if (u32Timeout > u32Time) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Wait EFM flag.
+ * @param [in] u32Addr Specifies the address to calculate.
+ * @retval uint8_t: The count that flag should shift.
+ */
+static uint8_t EFM_FlagShift(uint32_t u32Addr)
+{
+ uint8_t u8Shift;
+ uint8_t u8SwapState;
+ uint8_t u8OtpState;
+ uint8_t u8Flag;
+
+ u8SwapState = (uint8_t)READ_REG32(bCM_EFM->FSWP_b.FSWP);
+ u8OtpState = (0xFFFFFFFFUL == RW_MEM32(EFM_OTP_ENABLE_ADDR)) ? 0U : 1U;
+
+ /* To judge the addr belong to FLASH0 or FLASH1 */
+ if (u32Addr < EFM_OTP_END_ADDR1) {
+ u8Flag = (1U == u8OtpState) ? 0U : 1U;
+ u8Shift = (u8SwapState & u8Flag) * EFM_FLAG1_POS;
+ } else if (u32Addr < EFM_FLASH_1_START_ADDR) {
+ u8Shift = u8SwapState * EFM_FLAG1_POS;
+ } else if (u32Addr < EFM_SWAP_FLASH1_END_ADDR) {
+ u8Flag = (1U == u8SwapState) ? 0U : 1U;
+ u8Shift = (u8Flag | u8OtpState) * EFM_FLAG1_POS;
+ } else if (u32Addr < EFM_END_ADDR) {
+ u8Flag = (1U == u8SwapState) ? 0U : 1U;
+ u8Shift = u8Flag * EFM_FLAG1_POS;
+ } else {
+ u8Shift = EFM_FLAG0_POS;
+ }
+
+ return u8Shift;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EFM_Global_Functions EFM Global Functions
+ * @{
+ */
+
+/**
+ * @brief Enable or disable EFM.
+ * @param [in] u32Flash Specifies the FLASH. @ref EFM_Chip_Sel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void EFM_Cmd(uint32_t u32Flash, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_EFM_REG_UNLOCK());
+ DDL_ASSERT(IS_EFM_CHIP(u32Flash));
+
+ if (ENABLE == enNewState) {
+ CLR_REG32_BIT(CM_EFM->FSTP, u32Flash);
+ } else {
+ SET_REG32_BIT(CM_EFM->FSTP, u32Flash);
+ }
+}
+
+/**
+ * @brief Set the efm read wait cycles.
+ * @param [in] u32WaitCycle Specifies the efm read wait cycles.
+ * @arg This parameter can be of a value of @ref EFM_Wait_Cycle
+ * @retval int32_t:
+ * - LL_OK: Program successfully.
+ * - LL_ERR_TIMEOUT: EFM is not ready.
+ * @note Call EFM_REG_Unlock() unlock EFM register first.
+ */
+int32_t EFM_SetWaitCycle(uint32_t u32WaitCycle)
+{
+ uint32_t u32Timeout = 0UL;
+
+ /* Param valid check */
+ DDL_ASSERT(IS_EFM_REG_UNLOCK());
+ DDL_ASSERT(IS_EFM_WAIT_CYCLE(u32WaitCycle));
+
+ MODIFY_REG32(CM_EFM->FRMC, EFM_FRMC_FLWT, u32WaitCycle);
+ while (u32WaitCycle != READ_REG32_BIT(CM_EFM->FRMC, EFM_FRMC_FLWT)) {
+ u32Timeout++;
+ if (u32Timeout > EFM_TIMEOUT) {
+ return LL_ERR_TIMEOUT;
+ }
+ }
+ return LL_OK;
+}
+
+/**
+ * @brief Reset cache RAM or cache ram release reset.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void EFM_CacheRamReset(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_EFM_REG_UNLOCK());
+
+ WRITE_REG32(bCM_EFM->FRMC_b.CRST, enNewState);
+}
+
+/**
+ * @brief Enable or disable the flash prefetch.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ * @note Call EFM_REG_Unlock() unlock EFM register first.
+ */
+void EFM_PrefetchCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_EFM_REG_UNLOCK());
+
+ WRITE_REG32(bCM_EFM->FRMC_b.PREFETE, enNewState);
+}
+
+/**
+ * @brief Enable or disable the flash data cache.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ * @note Call EFM_REG_Unlock() unlock EFM register first.
+ */
+void EFM_DCacheCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_EFM_REG_UNLOCK());
+
+ WRITE_REG32(bCM_EFM->FRMC_b.DCACHE, enNewState);
+}
+
+/**
+ * @brief Enable or disable the flash instruction cache.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ * @note Call EFM_REG_Unlock() unlock EFM register first.
+ */
+void EFM_ICacheCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_EFM_REG_UNLOCK());
+
+ WRITE_REG32(bCM_EFM->FRMC_b.ICACHE, enNewState);
+}
+
+/**
+ * @brief Enable or disable the Read of low-voltage mode.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ * @note Call EFM_REG_Unlock() unlock EFM register first.
+ */
+void EFM_LowVoltageReadCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_EFM_REG_UNLOCK());
+
+ WRITE_REG32(bCM_EFM->FRMC_b.LVM, enNewState);
+}
+
+/**
+ * @brief Enable or disable the EFM swap function.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval int32_t:
+ * - LL_OK: Program successfully.
+ * - LL_ERR_NOT_RDY: EFM is not ready.
+ * @note Call EFM_REG_Unlock() unlock EFM register first.
+ */
+int32_t EFM_SwapCmd(en_functional_state_t enNewState)
+{
+ int32_t i32Ret = LL_OK;
+ uint32_t u32Tmp;
+
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_EFM_REG_UNLOCK());
+ DDL_ASSERT(IS_EFM_FWMC_UNLOCK());
+
+ /* Get CACHE status */
+ u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
+ /* Disable CACHE */
+ CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
+
+ if (enNewState == ENABLE) {
+ /* Set Program single mode. */
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE);
+ /* Enable flash swap function */
+ RW_MEM32(EFM_SWAP_ADDR) = EFM_SWAP_DATA;
+ /* Wait for ready flag. */
+ if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_PGM_TIMEOUT)) {
+ i32Ret = LL_ERR_NOT_RDY;
+ }
+ /* CLear the operation end flag. */
+ EFM_ClearStatus(EFM_FLAG_OPTEND);
+ } else {
+ /* Set Sector erase mode. */
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_SECTOR);
+ /* Disable flash switch function */
+ RW_MEM32(EFM_SWAP_ADDR) = 0x0UL;
+ /* Wait for ready flag. */
+ if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_ERASE_TIMEOUT)) {
+ i32Ret = LL_ERR_NOT_RDY;
+ }
+ /* CLear the operation end flag. */
+ EFM_ClearStatus(EFM_FLAG_OPTEND);
+ }
+ /* Set read only mode. */
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY);
+
+ /* recover CACHE */
+ MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp);
+
+ return i32Ret;
+}
+
+/**
+ * @brief Checks whether the swap function enable or disable.
+ * @param None
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t EFM_GetSwapStatus(void)
+{
+ return ((0UL == READ_REG32(bCM_EFM->FSWP_b.FSWP)) ? RESET : SET);
+}
+
+/**
+ * @brief Set the FLASH erase program mode .
+ * @param [in] u32Mode Specifies the FLASH erase program mode.
+ * @arg This parameter can be of a value of @ref EFM_OperateMode_Sel
+ * @retval int32_t:
+ * - LL_OK: Set mode successfully.
+ * - LL_ERR_NOT_RDY: EFM is not ready.
+ */
+int32_t EFM_SetOperateMode(uint32_t u32Mode)
+{
+ int32_t i32Ret = LL_OK;
+ DDL_ASSERT(IS_EFM_OPERATE_MD(u32Mode));
+ DDL_ASSERT(IS_EFM_REG_UNLOCK());
+ DDL_ASSERT(IS_EFM_FWMC_UNLOCK());
+
+ if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_SEQ_PGM_TIMEOUT)) {
+ i32Ret = LL_ERR_NOT_RDY;
+ }
+
+ if (i32Ret == LL_OK) {
+ /* Set the program or erase mode. */
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, u32Mode);
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Enable or Disable EFM interrupt.
+ * @param [in] u32EfmInt Specifies the FLASH interrupt source and status. @ref EFM_Interrupt_Sel
+ * @arg EFM_INT_OPTEND: End of EFM Operation Interrupt source
+ * @arg EFM_INT_PEERR: Program/erase error Interrupt source
+ * @arg EFM_INT_COLERR: Read collide error Interrupt source
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ * @note Call EFM_REG_Unlock() unlock EFM register first.
+ */
+void EFM_IntCmd(uint32_t u32EfmInt, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_EFM_REG_UNLOCK());
+ DDL_ASSERT(IS_EFM_INT_SEL(u32EfmInt));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(CM_EFM->FITE, u32EfmInt);
+ } else {
+ CLR_REG32_BIT(CM_EFM->FITE, u32EfmInt);
+ }
+}
+
+/**
+ * @brief Check any of the specified flag is set or not.
+ * @param [in] u32Flag Specifies the FLASH flag to check.
+ * @arg This parameter can be of a value of @ref EFM_Flag_Sel
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t EFM_GetAnyStatus(uint32_t u32Flag)
+{
+ DDL_ASSERT(IS_EFM_FLAG(u32Flag));
+
+ return ((0UL == READ_REG32_BIT(CM_EFM->FSR, u32Flag)) ? RESET : SET);
+}
+
+/**
+ * @brief Check all the specified flag is set or not.
+ * @param [in] u32Flag Specifies the FLASH flag to check.
+ * @arg This parameter can be of a value of @ref EFM_Flag_Sel
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t EFM_GetStatus(uint32_t u32Flag)
+{
+ DDL_ASSERT(IS_EFM_FLAG(u32Flag));
+
+ return ((u32Flag == READ_REG32_BIT(CM_EFM->FSR, u32Flag)) ? SET : RESET);
+}
+
+/**
+ * @brief Clear the flash flag.
+ * @param [in] u32Flag Specifies the FLASH flag to clear.
+ * @arg This parameter can be of a value of @ref EFM_Flag_Sel
+ * @retval None
+ * @note Call EFM_REG_Unlock() unlock EFM register first.
+ */
+void EFM_ClearStatus(uint32_t u32Flag)
+{
+ DDL_ASSERT(IS_EFM_REG_UNLOCK());
+ DDL_ASSERT(IS_EFM_CLRFLAG(u32Flag));
+
+ SET_REG32_BIT(CM_EFM->FSCLR, u32Flag);
+}
+
+/**
+ * @brief Set bus status while flash program or erase.
+ * @param [in] u32Status Specifies the new bus status while flash program or erase.
+ * This parameter can be one of the following values:
+ * @arg EFM_BUS_HOLD: Bus busy while flash program or erase.
+ * @arg EFM_BUS_RELEASE: Bus release while flash program or erase.
+ * @retval None
+ */
+void EFM_SetBusStatus(uint32_t u32Status)
+{
+ DDL_ASSERT(IS_EFM_REG_UNLOCK());
+ DDL_ASSERT(IS_EFM_BUS_STATUS(u32Status));
+ DDL_ASSERT(IS_EFM_FWMC_UNLOCK());
+
+ WRITE_REG32(bCM_EFM->FWMC_b.BUSHLDCTL, u32Status);
+}
+
+/**
+ * @brief EFM read byte.
+ * @param [in] u32Addr The specified address to read.
+ * @param [in] pu8ReadBuf The specified read buffer.
+ * @param [in] u32ByteLen The specified length to read.
+ * @retval int32_t:
+ * - LL_OK: Read successfully
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ * - LL_ERR_NOT_RDY: EFM is not ready.
+ */
+int32_t EFM_ReadByte(uint32_t u32Addr, uint8_t *pu8ReadBuf, uint32_t u32ByteLen)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ __IO uint8_t *pu8Buf = (uint8_t *)u32Addr;
+ uint32_t u32Len = u32ByteLen;
+ uint32_t u32ReadyFlag = EFM_FLAG_RDY;
+
+ DDL_ASSERT(IS_EFM_ADDR(u32Addr));
+ DDL_ASSERT(IS_EFM_ADDR(u32Addr + u32ByteLen - 1UL));
+
+ if (NULL != pu8ReadBuf) {
+ uint32_t u32EndAddr = u32Addr + u32ByteLen;
+ if (u32Addr < EFM_FLASH_1_START_ADDR) {
+ if (u32EndAddr > EFM_FLASH_1_START_ADDR) {
+ u32ReadyFlag |= EFM_FLAG_RDY1;
+ }
+ } else {
+ u32ReadyFlag = EFM_FLAG_RDY1;
+ }
+
+ if (LL_OK == EFM_WaitFlag(u32ReadyFlag, EFM_TIMEOUT)) {
+ while (0UL != u32Len) {
+ *(pu8ReadBuf++) = *(pu8Buf++);
+ u32Len--;
+ }
+ i32Ret = LL_OK;
+ } else {
+ i32Ret = LL_ERR_NOT_RDY;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief EFM program (single program mode).
+ * @param [in] u32Addr The specified program address.
+ * @param [in] pu8Buf The pointer of specified program data.
+ * @param [in] u32Len The length of specified program data.
+ * @retval int32_t:
+ * - LL_OK: Program successful.
+ * - LL_ERR_NOT_RDY: EFM if not ready.
+ * @note Call EFM_REG_Unlock() unlock EFM register first.
+ */
+int32_t EFM_Program(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len)
+{
+ int32_t i32Ret = LL_OK;
+ uint32_t u32Tmp;
+ uint8_t u8Shift;
+ uint32_t u32LoopWords = u32Len >> 2UL;
+ uint32_t u32RemainBytes = u32Len % 4UL;
+ uint32_t *u32pSource = (uint32_t *)(uint32_t)pu8Buf;
+ uint32_t *u32pDest = (uint32_t *)u32Addr;
+ uint32_t u32LastWord;
+
+ DDL_ASSERT(IS_EFM_REG_UNLOCK());
+ DDL_ASSERT(IS_EFM_FWMC_UNLOCK());
+ DDL_ASSERT(IS_EFM_ADDR(u32Addr));
+ DDL_ASSERT(IS_EFM_ADDR(u32Addr + u32Len - 1UL));
+ DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr));
+
+ /* CLear the error flag. */
+ EFM_ClearStatus(EFM_FLAG_ALL);
+ /* Get CACHE status */
+ u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
+ /* Disable CACHE */
+ CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
+
+ /* Set single program mode. */
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE);
+
+ while (u32LoopWords-- > 0UL) {
+ u8Shift = EFM_FlagShift((uint32_t)u32pDest);
+ /* program data. */
+ *u32pDest++ = *u32pSource++;
+ /* Wait for ready flag. */
+ if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) {
+ i32Ret = LL_ERR_NOT_RDY;
+ }
+ /* CLear the operation end flag. */
+ EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift);
+ }
+
+ if (0U != u32RemainBytes) {
+ u32LastWord = *u32pSource;
+ u32LastWord |= 0xFFFFFFFFUL << (u32RemainBytes * 8UL);
+ u8Shift = EFM_FlagShift((uint32_t)u32pDest);
+ *u32pDest++ = u32LastWord;
+ /* Wait for ready flag. */
+ if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) {
+ i32Ret = LL_ERR_NOT_RDY;
+ }
+ /* CLear the operation end flag. */
+ EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift);
+
+ }
+ /* Set read only mode. */
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY);
+ /* Recover CACHE function */
+ MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp);
+ return i32Ret;
+}
+
+/**
+ * @brief EFM single program mode(Word).
+ * @param [in] u32Addr The specified program address.
+ * @param [in] u32Data The specified program data.
+ * @retval int32_t:
+ * - LL_OK: Program successfully
+ * - LL_ERR_NOT_RDY: EFM is not ready.
+ * @note Call EFM_REG_Unlock() unlock EFM register first.
+ */
+int32_t EFM_ProgramWord(uint32_t u32Addr, uint32_t u32Data)
+{
+ int32_t i32Ret = LL_OK;
+ uint32_t u32Tmp;
+ uint8_t u8Shift;
+
+ DDL_ASSERT(IS_EFM_REG_UNLOCK());
+ DDL_ASSERT(IS_EFM_FWMC_UNLOCK());
+ DDL_ASSERT(IS_EFM_ADDR(u32Addr));
+ DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr));
+
+ /* Clear the error flag. */
+ EFM_ClearStatus(EFM_FLAG_ALL);
+ /* Get CACHE status */
+ u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
+ /* Disable CACHE function */
+ CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
+ u8Shift = EFM_FlagShift(u32Addr);
+ /* Set single program mode. */
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE);
+ /* Program data. */
+ RW_MEM32(u32Addr) = u32Data;
+
+ /* Wait for ready flag. */
+ if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) {
+ i32Ret = LL_ERR_NOT_RDY;
+ }
+ /* CLear the operation end flag. */
+ EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift);
+
+ /* Set read only mode. */
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY);
+
+ /* Recover CACHE function */
+ MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp);
+
+ return i32Ret;
+}
+
+/**
+ * @brief EFM single program with read back(Word).
+ * @param [in] u32Addr The specified program address.
+ * @param [in] u32Data The specified program data.
+ * @retval int32_t:
+ * - LL_OK: Program successfully
+ * - LL_ERR: program error
+ * - LL_ERR_NOT_RDY: EFM is not ready.
+ * @note Call EFM_REG_Unlock() unlock EFM register first.
+ */
+int32_t EFM_ProgramWordReadBack(uint32_t u32Addr, uint32_t u32Data)
+{
+ int32_t i32Ret = LL_OK;
+ uint32_t u32Tmp;
+ uint8_t u8Shift;
+
+ DDL_ASSERT(IS_EFM_REG_UNLOCK());
+ DDL_ASSERT(IS_EFM_FWMC_UNLOCK());
+ DDL_ASSERT(IS_EFM_ADDR(u32Addr));
+ DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr));
+
+ /* Clear the error flag. */
+ EFM_ClearStatus(EFM_FLAG_ALL);
+ /* Get CACHE status */
+ u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
+ /* Disable CACHE */
+ CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
+ u8Shift = EFM_FlagShift(u32Addr);
+ /* Set Program and read back mode. */
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_READBACK);
+ /* Program data. */
+ RW_MEM32(u32Addr) = (uint32_t)u32Data;
+
+ /* Wait for ready flag. */
+ if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) {
+ i32Ret = LL_ERR_NOT_RDY;
+ }
+
+ /* Get the flag PGMISMTCH */
+ if (SET == EFM_GetStatus(EFM_FLAG_PGMISMTCH << u8Shift)) {
+ /* Clear flag PGMISMTCH */
+ EFM_ClearStatus(EFM_FLAG_PGMISMTCH << u8Shift);
+ i32Ret = LL_ERR;
+ }
+ /* CLear the operation end flag. */
+ EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift);
+ /* Set read only mode. */
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY);
+
+ /* recover CACHE function */
+ MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp);
+
+ return i32Ret;
+}
+
+/**
+ * @brief EFM program (sequence program mode).
+ * @param [in] u32Addr The specified program address.
+ * @param [in] pu8Buf The pointer of specified program data.
+ * @param [in] u32Len The length of specified program data.
+ * @retval int32_t:
+ * - LL_OK: Program successfully
+ * - LL_ERR_TIMEOUT: program error timeout
+ * @note Call EFM_REG_Unlock() unlock EFM register first.
+ * __EFM_FUNC default value is __RAM_FUNC.
+ * __EFM_FUNC also could be attributed to FLASH0 or FLASH1 which is determined by users.
+ * If want to attribute to other place, please define in hc32f4xx_conf.h.
+ */
+__EFM_FUNC int32_t EFM_SequenceProgram(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len)
+{
+ int32_t i32Ret = LL_OK;
+ uint32_t u32Tmp;
+ uint32_t u32LoopWords = u32Len >> 2UL;
+ uint32_t u32RemainBytes = u32Len % 4UL;
+ uint32_t *u32pSource = (uint32_t *)(uint32_t)pu8Buf;
+ uint32_t *u32pDest = (uint32_t *)u32Addr;
+ uint32_t u32Timeout;
+ uint32_t u32LastWord;
+ uint8_t u8Shift = 0U;
+ uint8_t u8SwapState;
+ uint8_t u8OtpState;
+ uint8_t u8Flag;
+
+ /* Assert */
+ if (!IS_EFM_REG_UNLOCK()) {
+ return LL_ERR_NOT_RDY;
+ }
+ if ((!IS_EFM_FWMC_UNLOCK()) || (!IS_EFM_ADDR(u32Addr)) || (!IS_EFM_ADDR(u32Addr + u32Len - 1UL))) {
+ return LL_ERR_INVD_PARAM;
+ }
+ if (!IS_ADDR_ALIGN_WORD(u32Addr)) {
+ return LL_ERR_INVD_PARAM;
+ }
+
+ /* Get swap & otp state, enable or disable */
+ u8SwapState = (uint8_t)READ_REG32(bCM_EFM->FSWP_b.FSWP);
+ u8OtpState = (0xFFFFFFFFUL == RW_MEM32(EFM_OTP_ENABLE_ADDR)) ? 0U : 1U;
+
+ /* CLear the error flag. */
+ SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_ALL);
+ /* Get CACHE status */
+ u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
+ /* Disable CACHE */
+ CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
+ /* Set sequence program mode. */
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SEQ);
+
+ while (u32LoopWords-- > 0UL) {
+ /* program data. */
+ *u32pDest = *u32pSource++;
+ /* To judge the addr belong to FLASH0 or FLASH1 */
+ if ((uint32_t)u32pDest < EFM_OTP_END_ADDR1) {
+ u8Flag = (1U == u8OtpState) ? 0U : 1U;
+ u8Shift = (u8SwapState & u8Flag) * EFM_FLAG1_POS;
+ } else if ((uint32_t)u32pDest < EFM_FLASH_1_START_ADDR) {
+ u8Shift = u8SwapState * EFM_FLAG1_POS;
+ } else if ((uint32_t)u32pDest < EFM_SWAP_FLASH1_END_ADDR) {
+ u8Flag = (1U == u8SwapState) ? 0U : 1U;
+ u8Shift = (u8Flag | u8OtpState) * EFM_FLAG1_POS;
+ } else if ((uint32_t)u32pDest < EFM_END_ADDR) {
+ u8Flag = (1U == u8SwapState) ? 0U : 1U;
+ u8Shift = u8Flag * EFM_FLAG1_POS;
+ } else {
+ u8Shift = EFM_FLAG0_POS;
+ }
+ u32pDest++;
+ /* wait for operation end flag. */
+ u32Timeout = 0UL;
+ while ((EFM_FLAG_OPTEND << u8Shift) != READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_OPTEND << u8Shift)) {
+ if (u32Timeout++ >= EFM_PGM_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+ /* Clear operation end flag */
+ u32Timeout = 0UL;
+ while ((EFM_FLAG_OPTEND << u8Shift) == READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_OPTEND << u8Shift)) {
+ SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_OPTEND << u8Shift);
+ if (u32Timeout++ >= EFM_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+ }
+
+ if (0U != u32RemainBytes) {
+ /* To judge the addr belong to FLASH0 or FLASH1 */
+ if ((uint32_t)u32pDest < EFM_OTP_END_ADDR1) {
+ u8Flag = (1U == u8OtpState) ? 0U : 1U;
+ u8Shift = (u8SwapState & u8Flag) * EFM_FLAG1_POS;
+ } else if ((uint32_t)u32pDest < EFM_FLASH_1_START_ADDR) {
+ u8Shift = u8SwapState * EFM_FLAG1_POS;
+ } else if ((uint32_t)u32pDest < EFM_SWAP_FLASH1_END_ADDR) {
+ u8Flag = (1U == u8SwapState) ? 0U : 1U;
+ u8Shift = (u8Flag | u8OtpState) * EFM_FLAG1_POS;
+ } else if ((uint32_t)u32pDest < EFM_END_ADDR) {
+ u8Flag = (1U == u8SwapState) ? 0U : 1U;
+ u8Shift = u8Flag * EFM_FLAG1_POS;
+ } else {
+ u8Shift = EFM_FLAG0_POS;
+ }
+ /* Fill the last word */
+ u32LastWord = *u32pSource;
+ u32LastWord |= 0xFFFFFFFFUL << (u32RemainBytes * 8UL);
+ *u32pDest++ = u32LastWord;
+
+ /* wait for operation end flag. */
+ u32Timeout = 0UL;
+ while ((EFM_FLAG_OPTEND << u8Shift) != READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_OPTEND << u8Shift)) {
+ if (u32Timeout++ >= EFM_PGM_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+
+ /* Clear operation end flag */
+ u32Timeout = 0UL;
+ while ((EFM_FLAG_OPTEND << u8Shift) == READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_OPTEND << u8Shift)) {
+ SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_OPTEND << u8Shift);
+ if (u32Timeout++ >= EFM_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+ }
+
+ /* Set read only mode. */
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY);
+ /* Wait for ready flag. */
+ u32Timeout = 0UL;
+ while ((EFM_FLAG_RDY << u8Shift) != READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_RDY << u8Shift)) {
+ if (u32Timeout++ >= EFM_PGM_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+
+ /* Recover CACHE */
+ MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp);
+ return i32Ret;
+}
+
+/**
+ * @brief EFM sector erase.
+ * @param [in] u32Addr The address in the specified sector.
+ * @retval int32_t:
+ * - LL_OK: Erase successful.
+ * - LL_ERR_NOT_RDY: EFM is not ready.
+ * @note Call EFM_REG_Unlock() unlock EFM register first.
+ */
+int32_t EFM_SectorErase(uint32_t u32Addr)
+{
+ int32_t i32Ret = LL_OK;
+ uint32_t u32Tmp;
+ uint8_t u8Shift;
+
+ DDL_ASSERT(IS_EFM_ERASE_ADDR(u32Addr));
+ DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr));
+ DDL_ASSERT(IS_EFM_REG_UNLOCK());
+ DDL_ASSERT(IS_EFM_FWMC_UNLOCK());
+
+ /* CLear the error flag. */
+ EFM_ClearStatus(EFM_FLAG_ALL);
+ /* Get CACHE status */
+ u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
+ /* Disable CACHE */
+ CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
+ u8Shift = EFM_FlagShift(u32Addr);
+ /* Set sector erase mode. */
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_SECTOR);
+
+ /* Erase */
+ RW_MEM32(u32Addr) = 0UL;
+
+ /* Wait for ready flag. */
+ if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_ERASE_TIMEOUT)) {
+ i32Ret = LL_ERR_NOT_RDY;
+ }
+ /* Clear the operation end flag */
+ EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift);
+ /* Set read only mode. */
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY);
+ /* Recover CACHE */
+ MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp);
+
+ return i32Ret;
+}
+
+/**
+ * @brief EFM chip erase.
+ * @param [in] u8Chip Specifies the chip to be erased @ref EFM_Chip_Sel
+ * @retval int32_t:
+ * - LL_OK: Erase successfully
+ * - LL_ERR_NOT_RDY: EFM is not ready.
+ * @note Call EFM_REG_Unlock() unlock EFM register first.
+ * __EFM_FUNC default value is __RAM_FUNC.
+ * __EFM_FUNC also could be attributed to FLASH0 or FLASH1 which is determined by users.
+ * If want to attribute to other place, please define in hc32f4xx_conf.h.
+ */
+__EFM_FUNC int32_t EFM_ChipErase(uint8_t u8Chip)
+{
+ int32_t i32Ret = LL_OK;
+ uint32_t u32Tmp;
+ uint32_t u32Addr = 0UL;
+ uint8_t u8Shift;
+ uint32_t u32Timeout;
+ uint8_t u8SwapState;
+ uint8_t u8OtpState;
+ uint8_t u8Flag;
+
+ /* Assert */
+ if (!IS_EFM_REG_UNLOCK()) {
+ return LL_ERR_NOT_RDY;
+ }
+ if ((!IS_EFM_FWMC_UNLOCK()) || !IS_EFM_CHIP(u8Chip)) {
+ return LL_ERR_INVD_PARAM;
+ }
+
+ /* CLear the error flag. */
+ SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_ALL);
+ /* Get CACHE status */
+ u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
+ /* Disable CACHE */
+ CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
+
+ if (EFM_CHIP1 == u8Chip) {
+ u32Addr = EFM_FLASH_1_START_ADDR;
+ }
+ /* Get swap & otp state, enable or disable */
+ u8SwapState = (uint8_t)READ_REG32(bCM_EFM->FSWP_b.FSWP);
+ u8OtpState = (0xFFFFFFFFUL == RW_MEM32(EFM_OTP_ENABLE_ADDR)) ? 0U : 1U;
+ /* To judge the addr belong to FLASH0 or FLASH1 */
+ if (u32Addr < EFM_OTP_END_ADDR1) {
+ u8Flag = (1U == u8OtpState) ? 0U : 1U;
+ u8Shift = (u8SwapState & u8Flag) * EFM_FLAG1_POS;
+ } else {
+ u8Flag = (1U == u8SwapState) ? 0U : 1U;
+ u8Shift = (u8Flag | u8OtpState) * EFM_FLAG1_POS;
+ }
+
+ if (EFM_CHIP_ALL == u8Chip) {
+ if (1UL == (READ_REG32(bCM_EFM->FSWP_b.FSWP))) {
+ /* Set Sector erase mode. */
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_SECTOR);
+ /* Disable flash switch function */
+ RW_MEM32(EFM_SWAP_ADDR) = 0x0UL;
+ /* wait for operation end flag. */
+ u32Timeout = 0UL;
+ while (EFM_FLAG_OPTEND != READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_OPTEND)) {
+ if (u32Timeout++ >= EFM_PGM_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+ /* CLear the operation end flag */
+ SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_OPTEND);
+ }
+ }
+
+ /* Set chip erase mode. */
+ if (EFM_CHIP_ALL == u8Chip) {
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_ALL_CHIP);
+ } else {
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_ONE_CHIP);
+ }
+ /* Erase */
+ RW_MEM32(u32Addr) = 0UL;
+ /* Wait for ready flag. */
+ u32Timeout = 0UL;
+ while ((EFM_FLAG_RDY << u8Shift) != READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_RDY << u8Shift)) {
+ if (u32Timeout++ >= EFM_ERASE_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+ /* CLear the operation end flag. */
+ SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_OPTEND << u8Shift);
+ /* Set read only mode. */
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY);
+
+ /* recover CACHE */
+ MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp);
+ return i32Ret;
+}
+
+/**
+ * @brief FWMC register write enable or disable.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void EFM_FWMC_Cmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ WRITE_REG32(CM_EFM->KEY1, 0x01234567UL);
+ WRITE_REG32(CM_EFM->KEY1, 0xFEDCBA98UL);
+ } else {
+ SET_REG32_BIT(CM_EFM->FWMC, EFM_FWMC_KEY1LOCK);
+ }
+}
+
+/**
+ * @brief EFM OTP lock.
+ * @param [in] u32Addr Specifies the OTP block
+ * @retval int32_t:
+ * - LL_OK: Lock successfully
+ * - LL_ERR_NOT_RDY: EFM is not ready.
+ * @note The address should be word align.
+ * Call EFM_REG_Unlock() and EFM_OTP_WP_Unlock() unlock EFM_FWMC register first.
+ */
+int32_t EFM_OTP_Lock(uint32_t u32Addr)
+{
+ int32_t i32Ret = LL_OK;
+ uint32_t u32Tmp;
+
+ if ((u32Addr >= EFM_OTP_LOCK_ADDR_START) && (u32Addr < EFM_OTP_LOCK_ADDR_END)) {
+ DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr));
+ DDL_ASSERT(IS_EFM_FWMC_UNLOCK());
+ DDL_ASSERT(IS_EFM_REG_UNLOCK());
+ DDL_ASSERT(IS_EFM_OTP_UNLOCK());
+ /* Get CACHE status */
+ u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
+ /* Disable CACHE */
+ CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
+
+ /* Set single program mode. */
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE);
+
+ /* OTP latch */
+ RW_MEM32(u32Addr) = (uint32_t)0UL;
+ /* Wait for ready flag. */
+ if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_ERASE_TIMEOUT)) {
+ i32Ret = LL_ERR_NOT_RDY;
+ }
+ /* CLear the operation end flag. */
+ EFM_ClearStatus(EFM_FLAG_OPTEND);
+
+ /* Set read only mode. */
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY);
+
+ /* Recover CACHE */
+ MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp);
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Get chip ID.
+ * @param None
+ * @retval Returns the value of the Chip ID
+ */
+uint32_t EFM_GetCID(void)
+{
+ return READ_REG32(CM_EFM->CHIPID);
+}
+
+/**
+ * @brief EFM OTP operate unlock.
+ * @param None
+ * @retval None
+ * @note Call EFM_REG_Unlock() unlock EFM register first.
+ */
+void EFM_OTP_WP_Unlock(void)
+{
+ DDL_ASSERT(IS_EFM_REG_UNLOCK());
+
+ WRITE_REG32(CM_EFM->KEY2, EFM_OTP_UNLOCK_KEY1);
+ WRITE_REG32(CM_EFM->KEY2, EFM_OTP_UNLOCK_KEY2);
+}
+
+/**
+ * @brief EFM OTP write protect lock.
+ * @param None
+ * @retval None
+ */
+void EFM_OTP_WP_Lock(void)
+{
+ DDL_ASSERT(IS_EFM_REG_UNLOCK());
+
+ SET_REG32_BIT(CM_EFM->FWMC, EFM_FWMC_KEY2LOCK);
+}
+
+/**
+ * @brief EFM OTP Enable.
+ * @param None
+ * @retval None
+ */
+int32_t EFM_OTP_Enable(void)
+{
+ uint32_t u32Tmp;
+ int32_t i32Ret = LL_OK;
+
+ DDL_ASSERT(IS_EFM_OTP_UNLOCK());
+
+ /* Get CACHE status */
+ u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
+ /* Disable CACHE */
+ CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
+
+ /* Set single program mode. */
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE);
+
+ if (0xFFFFFFFFUL == RW_MEM32(EFM_OTP_ENABLE_ADDR)) {
+ /* Enable OTP */
+ RW_MEM32(EFM_OTP_ENABLE_ADDR) = (uint32_t)0UL;
+ /* Wait for ready flag. */
+ if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_PGM_TIMEOUT)) {
+ i32Ret = LL_ERR_NOT_RDY;
+ }
+ /* CLear the operation end flag. */
+ EFM_ClearStatus(EFM_FLAG_OPTEND);
+ }
+
+ /* Set read only mode. */
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY);
+
+ /* Recover CACHE */
+ MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp);
+
+ return i32Ret;
+}
+
+/**
+ * @brief Sector protected register lock.
+ * @param [in] u32RegLock Specifies sector protected register locking.
+ * @arg EFM_WRLOCK0, EFM_WRLOCK1
+ * @retval None
+ * @note Call EFM_REG_Unlock() unlock EFM register first.
+ */
+void EFM_SectorProtectRegLock(uint32_t u32RegLock)
+{
+ DDL_ASSERT(IS_EFM_SECTOR_PROTECT_REG_LOCK(u32RegLock));
+ DDL_ASSERT(IS_EFM_REG_UNLOCK());
+
+ SET_REG32_BIT(CM_EFM->WLOCK, u32RegLock);
+}
+
+/**
+ * @brief Set sector lock or unlock (Single).
+ * @param [in] u8SectorNum Specifies sector for unlock.
+ * This parameter can be set 0~63.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ * @note Call EFM_REG_Unlock() unlock EFM register first.
+ * If you want to unlock sequence sectors,Please call EFM_SequenceSectorOperateCmd function
+ */
+void EFM_SingleSectorOperateCmd(uint8_t u8SectorNum, en_functional_state_t enNewState)
+{
+ __IO uint32_t *EFM_FxNWPRTy;
+ const uint8_t u8RegIndex = u8SectorNum / REG_LEN;
+ const uint8_t u8BitPos = u8SectorNum % REG_LEN;
+ DDL_ASSERT(IS_EFM_REG_UNLOCK());
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_EFM_SECTOR_IDX(u8SectorNum));
+
+ EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&FNWPRT_REG) + ((uint32_t)u8RegIndex << EFM_FNWPRT_REG_OFFSET));
+ MODIFY_REG32(*EFM_FxNWPRTy, 1UL << u8BitPos, (uint32_t)enNewState << u8BitPos);
+}
+
+/**
+ * @brief Set sector lock or unlock (Sequence).
+ * @param [in] u32StartSectorNum Specifies start sector to unlock.
+ * This parameter can be set 0~63.
+ * @param [in] u16Count Specifies count of sectors to unlock.
+ * This parameter can be set 1~64.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ * @note Call EFM_REG_Unlock() unlock EFM register first.
+ * If you want to unlock only one sector,Please call EFM_SingleSectorOperateCmd function
+ */
+void EFM_SequenceSectorOperateCmd(uint32_t u32StartSectorNum, uint16_t u16Count, en_functional_state_t enNewState)
+{
+ __IO uint32_t *EFM_FxNWPRTy;
+ uint32_t u32EndSectorNum;
+ uint16_t u16StartRegIndex;
+ uint16_t u16StartBitPos;
+ uint16_t u16EndRegIndex;
+ uint16_t u16EndBitPos;
+ uint32_t u32RegValue;
+
+ DDL_ASSERT(IS_EFM_REG_UNLOCK());
+ DDL_ASSERT(IS_EFM_SECTOR_IDX(u32StartSectorNum));
+ DDL_ASSERT(IS_EFM_SECTOR_NUM(u32StartSectorNum + u16Count));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (SET == EFM_GetSwapStatus()) {
+ if (0xFFFFFFFFUL != RW_MEM32(EFM_OTP_ENABLE_ADDR)) {
+ if (u32StartSectorNum > EFM_SWAP_FLASH1_END_SECTOR_NUM) {
+ u32StartSectorNum -= EFM_FLASH1_START_SECTOR_NUM;
+ } else if ((u32StartSectorNum > EFM_OTP_END_SECTOR_NUM) && (u32StartSectorNum < EFM_FLASH1_START_SECTOR_NUM)) {
+ u32StartSectorNum += EFM_FLASH1_START_SECTOR_NUM;
+ } else {
+ /* rsvd */
+ }
+ } else {
+ if (u32StartSectorNum >= EFM_FLASH1_START_SECTOR_NUM) {
+ u32StartSectorNum -= EFM_FLASH1_START_SECTOR_NUM;
+ } else {
+ u32StartSectorNum += EFM_FLASH1_START_SECTOR_NUM;
+ }
+ }
+ }
+
+ u16StartRegIndex = (uint16_t)(u32StartSectorNum / REG_LEN); /* Register offset for the start sector */
+ u16StartBitPos = (uint16_t)(u32StartSectorNum % REG_LEN); /* Bit offset for the start sector */
+ u32EndSectorNum = (uint16_t)(u32StartSectorNum + u16Count - 1U); /* Calculate the end sector */
+ u16EndRegIndex = (uint16_t)(u32EndSectorNum / REG_LEN); /* Register offset for the end sector */
+ u16EndBitPos = (uint16_t)(u32EndSectorNum % REG_LEN); /* Bit offset for the end sector */
+
+ if ((u16StartBitPos == 0U) && (u16EndBitPos == 31U)) {
+ while (u16StartRegIndex <= u16EndRegIndex) {
+ EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&FNWPRT_REG) + ((uint32_t)u16StartRegIndex << EFM_FNWPRT_REG_OFFSET));
+ if (EFM_FxNWPRTy > EFM_FNWPRT_REG_END_ADDR) {
+ EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&FNWPRT_REG) + (((uint32_t)u16StartRegIndex - EFM_FNWPRT_REG_NUM) << EFM_FNWPRT_REG_OFFSET));
+ }
+ if (enNewState == ENABLE) {
+ WRITE_REG32(*EFM_FxNWPRTy, 0xFFFFFFFFUL);
+ } else {
+ WRITE_REG32(*EFM_FxNWPRTy, 0x0UL);
+ }
+ u16StartRegIndex += 1U;
+ }
+ } else {
+ EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&FNWPRT_REG) + ((uint32_t)u16StartRegIndex << EFM_FNWPRT_REG_OFFSET));
+ if (u16StartRegIndex == u16EndRegIndex) {
+ u32RegValue = ((1UL << u16EndBitPos) - (1UL << u16StartBitPos)) | (1UL << u16EndBitPos);
+ if (enNewState == ENABLE) {
+ SET_REG32_BIT(*EFM_FxNWPRTy, u32RegValue);
+ } else {
+ CLR_REG32_BIT(*EFM_FxNWPRTy, u32RegValue);
+ }
+ } else {
+ u32RegValue = ((1UL << 31U) - (1UL << u16StartBitPos)) | (1UL << 31U);
+ if (enNewState == ENABLE) {
+ SET_REG32_BIT(*EFM_FxNWPRTy, u32RegValue);
+ while (u16StartRegIndex < (u16EndRegIndex - 1U)) {
+ u16StartRegIndex += 1U;
+ EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&FNWPRT_REG) + ((uint32_t)u16StartRegIndex << EFM_FNWPRT_REG_OFFSET));
+ if (EFM_FxNWPRTy > EFM_FNWPRT_REG_END_ADDR) {
+ EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&FNWPRT_REG) + (((uint32_t)u16StartRegIndex - EFM_FNWPRT_REG_NUM) << EFM_FNWPRT_REG_OFFSET));
+ }
+ WRITE_REG32(*EFM_FxNWPRTy, 0xFFFFFFFFUL);
+ }
+ u16StartRegIndex += 1U;
+ u32RegValue = ((1UL << u16EndBitPos) - 1UL) | (1UL << u16EndBitPos);
+ EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&FNWPRT_REG) + ((uint32_t)u16StartRegIndex << EFM_FNWPRT_REG_OFFSET));
+ if (EFM_FxNWPRTy > EFM_FNWPRT_REG_END_ADDR) {
+ EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&FNWPRT_REG) + (((uint32_t)u16EndRegIndex - EFM_FNWPRT_REG_NUM) << EFM_FNWPRT_REG_OFFSET));
+ }
+ SET_REG32_BIT(*EFM_FxNWPRTy, u32RegValue);
+ } else {
+ CLR_REG32_BIT(*EFM_FxNWPRTy, u32RegValue);
+ while (u16StartRegIndex < (u16EndRegIndex - 1U)) {
+ u16StartRegIndex += 1U;
+ EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&FNWPRT_REG) + ((uint32_t)u16StartRegIndex << EFM_FNWPRT_REG_OFFSET));
+ if (EFM_FxNWPRTy > EFM_FNWPRT_REG_END_ADDR) {
+ EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&FNWPRT_REG) + (((uint32_t)u16StartRegIndex - EFM_FNWPRT_REG_NUM) << EFM_FNWPRT_REG_OFFSET));
+ }
+ WRITE_REG32(*EFM_FxNWPRTy, 0x0UL);
+ }
+ u32RegValue = ((1UL << u16EndBitPos) - 1UL) | (1UL << u16EndBitPos);
+ EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&FNWPRT_REG) + ((uint32_t)u16StartRegIndex << EFM_FNWPRT_REG_OFFSET));
+ if (EFM_FxNWPRTy > EFM_FNWPRT_REG_END_ADDR) {
+ EFM_FxNWPRTy = (__IO uint32_t *)((uint32_t)(&FNWPRT_REG) + (((uint32_t)u16EndRegIndex - EFM_FNWPRT_REG_NUM) << EFM_FNWPRT_REG_OFFSET));
+ }
+ CLR_REG32_BIT(*EFM_FxNWPRTy, u32RegValue);
+ }
+ }
+ }
+}
+
+/**
+ * @brief Get unique ID.
+ * @param [out] pstcUID Unique ID struct
+ * @retval Returns the value of the unique ID
+ */
+void EFM_GetUID(stc_efm_unique_id_t *pstcUID)
+{
+ if (NULL != pstcUID) {
+ pstcUID->u32UniqueID0 = READ_REG32(CM_EFM->UQID0);
+ pstcUID->u32UniqueID1 = READ_REG32(CM_EFM->UQID1);
+ pstcUID->u32UniqueID2 = READ_REG32(CM_EFM->UQID2);
+ }
+}
+
+/**
+ * @brief Init REMAP initial structure with default value.
+ * @param [in] pstcEfmRemapInit specifies the Parameter of REMAP.
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t EFM_REMAP_StructInit(stc_efm_remap_init_t *pstcEfmRemapInit)
+{
+ int32_t i32Ret = LL_OK;
+ if (NULL == pstcEfmRemapInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ pstcEfmRemapInit->u32State = EFM_REMAP_OFF;
+ pstcEfmRemapInit->u32Addr = 0UL;
+ pstcEfmRemapInit->u32Size = EFM_REMAP_4K;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief REMAP initialize.
+ * @param [in] u8RemapIdx Specifies the remap ID.
+ * @param [in] pstcEfmRemapInit specifies the Parameter of REMAP.
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t EFM_REMAP_Init(uint8_t u8RemapIdx, stc_efm_remap_init_t *pstcEfmRemapInit)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t *REMCRx;
+
+ if (NULL == pstcEfmRemapInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ DDL_ASSERT(IS_EFM_REMAP_UNLOCK());
+ DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx));
+ DDL_ASSERT(IS_EFM_REMAP_SIZE(pstcEfmRemapInit->u32Size));
+ DDL_ASSERT(IS_EFM_REMAP_ADDR(pstcEfmRemapInit->u32Addr));
+ DDL_ASSERT(IS_EFM_REMAP_STATE(pstcEfmRemapInit->u32State));
+ if ((pstcEfmRemapInit->u32Addr % (1UL << pstcEfmRemapInit->u32Size)) != 0U) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ REMCRx = &REMCR_REG(u8RemapIdx);
+ MODIFY_REG32(*REMCRx, EFM_MMF_REMCR_EN | EFM_MMF_REMCR_RMTADDR | EFM_MMF_REMCR_RMSIZE, \
+ pstcEfmRemapInit->u32State | pstcEfmRemapInit->u32Addr | pstcEfmRemapInit->u32Size);
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief EFM REMAP de-initialize.
+ * @param None
+ * @retval None
+ */
+void EFM_REMAP_DeInit(void)
+{
+ DDL_ASSERT(IS_EFM_REMAP_UNLOCK());
+
+ WRITE_REG32(CM_EFM->MMF_REMCR0, 0UL);
+ WRITE_REG32(CM_EFM->MMF_REMCR1, 0UL);
+}
+
+/**
+ * @brief Enable or disable REMAP function.
+ * @param [in] u8RemapIdx Specifies the remap ID.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void EFM_REMAP_Cmd(uint8_t u8RemapIdx, en_functional_state_t enNewState)
+{
+ __IO uint32_t *REMCRx;
+
+ DDL_ASSERT(IS_EFM_REMAP_UNLOCK());
+ DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ REMCRx = &REMCR_REG(u8RemapIdx);
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(*REMCRx, EFM_MMF_REMCR_EN);
+ } else {
+ CLR_REG32_BIT(*REMCRx, EFM_MMF_REMCR_EN);
+ }
+}
+
+/**
+ * @brief Set specified REMAP target address.
+ * @param [in] u8RemapIdx Specifies the remap ID.
+ * @param [in] u32Addr Specifies the target address.
+ * @retval None
+ */
+void EFM_REMAP_SetAddr(uint8_t u8RemapIdx, uint32_t u32Addr)
+{
+ __IO uint32_t *REMCRx;
+
+ DDL_ASSERT(IS_EFM_REMAP_UNLOCK());
+ DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx));
+ DDL_ASSERT(IS_EFM_REMAP_ADDR(u32Addr));
+
+ REMCRx = &REMCR_REG(u8RemapIdx);
+ MODIFY_REG32(*REMCRx, EFM_MMF_REMCR_RMTADDR, u32Addr);
+}
+
+/**
+ * @brief Set specified REMAP size.
+ * @param [in] u8RemapIdx Specifies the remap ID.
+ * @param [in] u32Size Specifies the remap size.
+ * @retval None
+ */
+void EFM_REMAP_SetSize(uint8_t u8RemapIdx, uint32_t u32Size)
+{
+ __IO uint32_t *REMCRx;
+
+ DDL_ASSERT(IS_EFM_REMAP_UNLOCK());
+ DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx));
+ DDL_ASSERT(IS_EFM_REMAP_SIZE(u32Size));
+
+ REMCRx = &REMCR_REG(u8RemapIdx);
+ MODIFY_REG32(*REMCRx, EFM_MMF_REMCR_RMSIZE, u32Size);
+}
+
+/**
+ * @brief Enable efm protect.
+ * @param [in] u8Level Specifies the protect level. @ref EFM_Protect_Level
+ * @retval None
+ */
+void EFM_Protect_Enable(uint8_t u8Level)
+{
+
+ if (SET == EFM_GetSwapStatus()) {
+ (void)EFM_SingleSectorOperateCmd(EFM_SWAP_ON_PROTECT_SECTOR_NUM, ENABLE);
+ } else {
+ (void)EFM_SingleSectorOperateCmd(0U, ENABLE);
+ }
+ if (EFM_PROTECT_LEVEL1 == u8Level) {
+ (void)EFM_ProgramWord(EFM_PROTECT1_ADDR, EFM_PROTECT1_KEY);
+ } else if (EFM_PROTECT_LEVEL2 == u8Level) {
+ (void)EFM_ProgramWord(EFM_PROTECT2_ADDR, EFM_PROTECT2_KEY);
+ } else if (EFM_PROTECT_LEVEL3 == u8Level) {
+ (void)EFM_ProgramWord(EFM_PROTECT3_ADDR1, EFM_PROTECT3_KEY);
+ (void)EFM_ProgramWord(EFM_PROTECT3_ADDR2, EFM_PROTECT3_KEY);
+ (void)EFM_ProgramWord(EFM_PROTECT3_ADDR3, EFM_PROTECT3_KEY);
+ } else {
+ /* rsvd */
+ }
+}
+
+/**
+ * @brief Write the security code.
+ * @param [in] pu8Buf Specifies the security code.
+ * @param [in] u32Len Specified the length of the security code.
+ * @retval int32_t
+ */
+int32_t EFM_WriteSecurityCode(uint8_t *pu8Buf, uint32_t u32Len)
+{
+ int32_t i32Ret = LL_OK;
+ uint32_t u32Tmp;
+ uint32_t u32LoopWords = u32Len >> 2UL;
+ uint32_t *u32pSource = (uint32_t *)(uint32_t)pu8Buf;
+ uint32_t *u32pDest = (uint32_t *)EFM_SECURITY_ADDR;
+
+ DDL_ASSERT(IS_EFM_REG_UNLOCK());
+ DDL_ASSERT(IS_EFM_FWMC_UNLOCK());
+ DDL_ASSERT(IS_EFM_SECURITY_CODE_LEN(u32Len));
+
+ /* CLear the error flag. */
+ EFM_ClearStatus(EFM_FLAG_ALL);
+ /* Get CACHE status */
+ u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
+ /* Disable CACHE */
+ CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL);
+
+ /* Set sector erase mode. */
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_SECTOR);
+ /* Erase */
+ RW_MEM32(EFM_SECURITY_ADDR) = 0UL;
+ if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_PGM_TIMEOUT)) {
+ i32Ret = LL_ERR_NOT_RDY;
+ }
+ /* CLear the operation end flag. */
+ EFM_ClearStatus(EFM_FLAG_OPTEND);
+
+ /* Set single program mode. */
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE);
+
+ while (u32LoopWords-- > 0UL) {
+ /* program data. */
+ *u32pDest++ = *u32pSource++;
+ /* Wait for ready flag. */
+ if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_PGM_TIMEOUT)) {
+ i32Ret = LL_ERR_NOT_RDY;
+ }
+ /* CLear the operation end flag. */
+ EFM_ClearStatus(EFM_FLAG_OPTEND);
+ }
+
+ /* Set read only mode. */
+ MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY);
+
+ /* Recover CACHE function */
+ MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp);
+ return i32Ret;
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_EFM_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_emb.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_emb.c
new file mode 100644
index 0000000000..947cb7752b
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_emb.c
@@ -0,0 +1,823 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_emb.c
+ * @brief This file provides firmware functions to manage the EMB
+ * (Emergency Brake).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Function EMB_TMR4_Init don't call EMB_DeInit
+ 2023-12-15 CDT Modify stc_emb_monitor_sys_t structure relevant code
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_emb.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_EMB EMB
+ * @brief Emergency Brake Driver Library
+ * @{
+ */
+
+#if (LL_EMB_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup EMB_Local_Macros EMB Local Macros
+ * @{
+ */
+
+/**
+ * @defgroup EMB_Check_Parameters_Validity EMB Check Parameters Validity
+ * @{
+ */
+#define IS_EMB_GROUP(x) \
+( ((x) == CM_EMB0) || \
+ ((x) == CM_EMB1) || \
+ ((x) == CM_EMB2) || \
+ ((x) == CM_EMB3) || \
+ ((x) == CM_EMB4) || \
+ ((x) == CM_EMB5) || \
+ ((x) == CM_EMB6))
+#define IS_EMB_TMR4_GROUP(x) ((x) == CM_EMB6)
+#define IS_EMB_TMR6_GROUP(x) \
+( ((x) == CM_EMB0) || \
+ ((x) == CM_EMB1) || \
+ ((x) == CM_EMB2) || \
+ ((x) == CM_EMB3) || \
+ ((x) == CM_EMB4) || \
+ ((x) == CM_EMB5))
+
+#define IS_EMB_OSC_STAT(x) \
+( ((x) == EMB_OSC_ENABLE) || \
+ ((x) == EMB_OSC_DISABLE))
+
+#define IS_EMB_SRAM_ECC_ERR_STAT(x) \
+( ((x) == EMB_SRAM_ECC_ERR_ENABLE) || \
+ ((x) == EMB_SRAM_ECC_ERR_DISABLE))
+
+#define IS_EMB_SRAM_PARITY_ERR_STAT(x) \
+( ((x) == EMB_SRAM_PARITY_ERR_ENABLE) || \
+ ((x) == EMB_SRAM_PARITY_ERR_DISABLE))
+
+#define IS_EMB_LOCKUP_STAT(x) \
+( ((x) == EMB_LOCKUP_ENABLE) || \
+ ((x) == EMB_LOCKUP_DISABLE))
+
+#define IS_EMB_LVD_STAT(x) \
+( ((x) == EMB_LVD_ENABLE) || \
+ ((x) == EMB_LVD_DISABLE))
+
+#define IS_EMB_TMR4_PWM_W_STAT(x) \
+( ((x) == EMB_TMR4_PWM_W_ENABLE) || \
+ ((x) == EMB_TMR4_PWM_W_DISABLE))
+
+#define IS_EMB_DETECT_TMR4_PWM_W_LVL(x) \
+( ((x) == EMB_DETECT_TMR4_PWM_W_BOTH_LOW) || \
+ ((x) == EMB_DETECT_TMR4_PWM_W_BOTH_HIGH))
+
+#define IS_EMB_TMR4_PWM_V_STAT(x) \
+( ((x) == EMB_TMR4_PWM_V_ENABLE) || \
+ ((x) == EMB_TMR4_PWM_V_DISABLE))
+
+#define IS_EMB_DETECT_TMR4_PWM_V_LVL(x) \
+( ((x) == EMB_DETECT_TMR4_PWM_V_BOTH_LOW) || \
+ ((x) == EMB_DETECT_TMR4_PWM_V_BOTH_HIGH))
+
+#define IS_EMB_TMR4_PWM_U_STAT(x) \
+( ((x) == EMB_TMR4_PWM_U_ENABLE) || \
+ ((x) == EMB_TMR4_PWM_U_DISABLE))
+
+#define IS_EMB_DETECT_TMR4_PWM_U_LVL(x) \
+( ((x) == EMB_DETECT_TMR4_PWM_U_BOTH_LOW) || \
+ ((x) == EMB_DETECT_TMR4_PWM_U_BOTH_HIGH))
+
+#define IS_EMB_CMP1_STAT(x) \
+( ((x) == EMB_CMP1_ENABLE) || \
+ ((x) == EMB_CMP1_DISABLE))
+
+#define IS_EMB_CMP2_STAT(x) \
+( ((x) == EMB_CMP2_ENABLE) || \
+ ((x) == EMB_CMP2_DISABLE))
+
+#define IS_EMB_CMP3_STAT(x) \
+( ((x) == EMB_CMP3_ENABLE) || \
+ ((x) == EMB_CMP3_DISABLE))
+
+#define IS_EMB_CMP4_STAT(x) \
+( ((x) == EMB_CMP4_ENABLE) || \
+ ((x) == EMB_CMP4_DISABLE))
+
+#define IS_EMB_PORT1_STAT(x) \
+( ((x) == EMB_PORT1_ENABLE) || \
+ ((x) == EMB_PORT1_DISABLE))
+
+#define IS_EMB_PORT1_DETECT_LVL(x) \
+( ((x) == EMB_PORT1_DETECT_LVL_LOW) || \
+ ((x) == EMB_PORT1_DETECT_LVL_HIGH))
+
+#define IS_EMB_PORT1_FILTER_STAT(x) \
+( ((x) == EMB_PORT1_FILTER_ENABLE) || \
+ ((x) == EMB_PORT1_FILTER_DISABLE))
+
+#define IS_EMB_PORT1_FILTER_DIV(x) (((x) & (~EMB_PORT1_FILTER_CLK_DIV_MASK)) == 0UL)
+#define IS_EMB_PORT2_STAT(x) \
+( ((x) == EMB_PORT2_ENABLE) || \
+ ((x) == EMB_PORT2_DISABLE))
+
+#define IS_EMB_PORT2_DETECT_LVL(x) \
+( ((x) == EMB_PORT2_DETECT_LVL_LOW) || \
+ ((x) == EMB_PORT2_DETECT_LVL_HIGH))
+
+#define IS_EMB_PORT2_FILTER_STAT(x) \
+( ((x) == EMB_PORT2_FILTER_ENABLE) || \
+ ((x) == EMB_PORT2_FILTER_DISABLE))
+
+#define IS_EMB_PORT2_FILTER_DIV(x) (((x) & (~EMB_PORT2_FILTER_CLK_DIV_MASK)) == 0UL)
+
+#define IS_EMB_PORT3_STAT(x) \
+( ((x) == EMB_PORT3_ENABLE) || \
+ ((x) == EMB_PORT3_DISABLE))
+
+#define IS_EMB_PORT3_DETECT_LVL(x) \
+( ((x) == EMB_PORT3_DETECT_LVL_LOW) || \
+ ((x) == EMB_PORT3_DETECT_LVL_HIGH))
+
+#define IS_EMB_PORT3_FILTER_STAT(x) \
+( ((x) == EMB_PORT3_FILTER_ENABLE) || \
+ ((x) == EMB_PORT3_FILTER_DISABLE))
+
+#define IS_EMB_PORT3_FILTER_DIV(x) (((x) & (~EMB_PORT3_FILTER_CLK_DIV_MASK)) == 0UL)
+#define IS_EMB_PORT4_STAT(x) \
+( ((x) == EMB_PORT4_ENABLE) || \
+ ((x) == EMB_PORT4_DISABLE))
+
+#define IS_EMB_PORT4_DETECT_LVL(x) \
+( ((x) == EMB_PORT4_DETECT_LVL_LOW) || \
+ ((x) == EMB_PORT4_DETECT_LVL_HIGH))
+
+#define IS_EMB_PORT4_FILTER_STAT(x) \
+( ((x) == EMB_PORT4_FILTER_ENABLE) || \
+ ((x) == EMB_PORT4_FILTER_DISABLE))
+
+#define IS_EMB_PORT4_FILTER_DIV(x) (((x) & (~EMB_PORT4_FILTER_CLK_DIV_MASK)) == 0UL)
+#define IS_EMB_PORT5_STAT(x) \
+( ((x) == EMB_PORT5_ENABLE) || \
+ ((x) == EMB_PORT5_DISABLE))
+
+#define IS_EMB_PORT5_DETECT_LVL(x) \
+( ((x) == EMB_PORT5_DETECT_LVL_LOW) || \
+ ((x) == EMB_PORT5_DETECT_LVL_HIGH))
+
+#define IS_EMB_PORT5_FILTER_STAT(x) \
+( ((x) == EMB_PORT5_FILTER_ENABLE) || \
+ ((x) == EMB_PORT5_FILTER_DISABLE))
+
+#define IS_EMB_PORT5_FILTER_DIV(x) (((x) & (~EMB_PORT5_FILTER_CLK_DIV_MASK)) == 0UL)
+
+#define IS_EMB_TMR6_1_PWM_STAT(x) \
+( ((x) == EMB_TMR6_1_PWM_ENABLE) || \
+ ((x) == EMB_TMR6_1_PWM_DISABLE))
+
+#define IS_EMB_DETECT_TMR6_1_PWM_LVL(x) \
+( ((x) == EMB_DETECT_TMR6_1_PWM_BOTH_LOW) || \
+ ((x) == EMB_DETECT_TMR6_1_PWM_BOTH_HIGH))
+
+#define IS_EMB_TMR6_2_PWM_STAT(x) \
+( ((x) == EMB_TMR6_2_PWM_ENABLE) || \
+ ((x) == EMB_TMR6_2_PWM_DISABLE))
+
+#define IS_EMB_DETECT_TMR6_2_PWM_LVL(x) \
+( ((x) == EMB_DETECT_TMR6_2_PWM_BOTH_LOW) || \
+ ((x) == EMB_DETECT_TMR6_2_PWM_BOTH_HIGH))
+#define IS_EMB_TMR6_3_PWM_STAT(x) \
+( ((x) == EMB_TMR6_3_PWM_ENABLE) || \
+ ((x) == EMB_TMR6_3_PWM_DISABLE))
+
+#define IS_EMB_DETECT_TMR6_3_PWM_LVL(x) \
+( ((x) == EMB_DETECT_TMR6_3_PWM_BOTH_LOW) || \
+ ((x) == EMB_DETECT_TMR6_3_PWM_BOTH_HIGH))
+#define IS_EMB_TMR6_4_PWM_STAT(x) \
+( ((x) == EMB_TMR6_4_PWM_ENABLE) || \
+ ((x) == EMB_TMR6_4_PWM_DISABLE))
+
+#define IS_EMB_DETECT_TMR6_4_PWM_LVL(x) \
+( ((x) == EMB_DETECT_TMR6_4_PWM_BOTH_LOW) || \
+ ((x) == EMB_DETECT_TMR6_4_PWM_BOTH_HIGH))
+#define IS_EMB_TMR6_5_PWM_STAT(x) \
+( ((x) == EMB_TMR6_5_PWM_ENABLE) || \
+ ((x) == EMB_TMR6_5_PWM_DISABLE))
+
+#define IS_EMB_DETECT_TMR6_5_PWM_LVL(x) \
+( ((x) == EMB_DETECT_TMR6_5_PWM_BOTH_LOW) || \
+ ((x) == EMB_DETECT_TMR6_5_PWM_BOTH_HIGH))
+
+#define IS_EMB_TMR6_6_PWM_STAT(x) \
+( ((x) == EMB_TMR6_6_PWM_ENABLE) || \
+ ((x) == EMB_TMR6_6_PWM_DISABLE))
+
+#define IS_EMB_DETECT_TMR6_6_PWM_LVL(x) \
+( ((x) == EMB_DETECT_TMR6_6_PWM_BOTH_LOW) || \
+ ((x) == EMB_DETECT_TMR6_6_PWM_BOTH_HIGH))
+
+#define IS_EMB_TMR6_7_PWM_STAT(x) \
+( ((x) == EMB_TMR6_7_PWM_ENABLE) || \
+ ((x) == EMB_TMR6_7_PWM_DISABLE))
+
+#define IS_EMB_DETECT_TMR6_7_PWM_LVL(x) \
+( ((x) == EMB_DETECT_TMR6_7_PWM_BOTH_LOW) || \
+ ((x) == EMB_DETECT_TMR6_7_PWM_BOTH_HIGH))
+
+#define IS_EMB_TMR6_8_PWM_STAT(x) \
+( ((x) == EMB_TMR6_8_PWM_ENABLE) || \
+ ((x) == EMB_TMR6_8_PWM_DISABLE))
+
+#define IS_EMB_DETECT_TMR6_8_PWM_LVL(x) \
+( ((x) == EMB_DETECT_TMR6_8_PWM_BOTH_LOW) || \
+ ((x) == EMB_DETECT_TMR6_8_PWM_BOTH_HIGH))
+#define IS_EMB_TMR6_9_PWM_STAT(x) \
+( ((x) == EMB_TMR6_9_PWM_ENABLE) || \
+ ((x) == EMB_TMR6_9_PWM_DISABLE))
+
+#define IS_EMB_DETECT_TMR6_9_PWM_LVL(x) \
+( ((x) == EMB_DETECT_TMR6_9_PWM_BOTH_LOW) || \
+ ((x) == EMB_DETECT_TMR6_9_PWM_BOTH_HIGH))
+
+#define IS_EMB_TMR6_10_PWM_STAT(x) \
+( ((x) == EMB_TMR6_10_PWM_ENABLE) || \
+ ((x) == EMB_TMR6_10_PWM_DISABLE))
+
+#define IS_EMB_DETECT_TMR6_10_PWM_LVL(x) \
+( ((x) == EMB_DETECT_TMR6_10_PWM_BOTH_LOW) || \
+ ((x) == EMB_DETECT_TMR6_10_PWM_BOTH_HIGH))
+
+#define IS_VALID_EMB_INT(x) \
+( ((x) != 0UL) && \
+ (((x) | EMB_INT_ALL) == EMB_INT_ALL))
+
+#define IS_EMB_FLAG(x) \
+( ((x) != 0UL) && \
+ (((x) | EMB_FLAG_ALL) == EMB_FLAG_ALL))
+
+#define IS_EMB_CLR_FLAG(x) \
+( ((x) != 0UL) && \
+ (((x) | EMB_FLAG_CLR_ALL) == EMB_FLAG_CLR_ALL))
+
+#define IS_EMB_RELEASE_PWM_COND(x) \
+( ((x) == EMB_RELEASE_PWM_COND_FLAG_ZERO) || \
+ ((x) == EMB_RELEASE_PWM_COND_STAT_ZERO))
+
+#define IS_EMB_MONITOR_EVT(x) \
+( ((x) == EMB_EVT_PWMS) || \
+ ((x) == EMB_EVT_CMP) || \
+ ((x) == EMB_EVT_SYS) || \
+ ((x) == EMB_EVT_PORT1) || \
+ ((x) == EMB_EVT_PORT2) || \
+ ((x) == EMB_EVT_PORT3) || \
+ ((x) == EMB_EVT_PORT4) || \
+ ((x) == EMB_EVT_PORT5))
+
+/**
+ * @}
+ */
+
+#define EMB_PORT1_FILTER_CLK_DIV_MASK EMB_PORT1_FILTER_CLK_DIV128
+#define EMB_PORT2_FILTER_CLK_DIV_MASK EMB_PORT2_FILTER_CLK_DIV128
+#define EMB_PORT3_FILTER_CLK_DIV_MASK EMB_PORT3_FILTER_CLK_DIV128
+#define EMB_PORT4_FILTER_CLK_DIV_MASK EMB_PORT4_FILTER_CLK_DIV128
+#define EMB_PORT5_FILTER_CLK_DIV_MASK EMB_PORT5_FILTER_CLK_DIV128
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ * @defgroup EMB_Global_Functions EMB Global Functions
+ * @{
+ */
+
+/**
+ * @brief Set the fields of structure stc_emb_tmr4_init_t to default values
+ * @param [out] pstcEmbInit Pointer to a @ref stc_emb_tmr4_init_t structure
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcEmbInit value is NULL.
+ */
+int32_t EMB_TMR4_StructInit(stc_emb_tmr4_init_t *pstcEmbInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcEmbInit) {
+
+ /* CMP */
+ pstcEmbInit->stcCmp.u32Cmp1State = EMB_CMP1_DISABLE;
+ pstcEmbInit->stcCmp.u32Cmp2State = EMB_CMP2_DISABLE;
+ pstcEmbInit->stcCmp.u32Cmp3State = EMB_CMP3_DISABLE;
+ pstcEmbInit->stcCmp.u32Cmp4State = EMB_CMP4_DISABLE;
+
+ /* Port */
+ pstcEmbInit->stcPort.stcPort1.u32PortState = EMB_PORT1_DISABLE;
+ pstcEmbInit->stcPort.stcPort1.u32PortLevel = EMB_PORT1_DETECT_LVL_HIGH;
+ pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv = EMB_PORT1_FILTER_CLK_DIV1;
+ pstcEmbInit->stcPort.stcPort1.u32PortFilterState = EMB_PORT1_FILTER_DISABLE;
+ pstcEmbInit->stcPort.stcPort2.u32PortState = EMB_PORT2_DISABLE;
+ pstcEmbInit->stcPort.stcPort2.u32PortLevel = EMB_PORT2_DETECT_LVL_HIGH;
+ pstcEmbInit->stcPort.stcPort2.u32PortFilterDiv = EMB_PORT2_FILTER_CLK_DIV1;
+ pstcEmbInit->stcPort.stcPort2.u32PortFilterState = EMB_PORT2_FILTER_DISABLE;
+ pstcEmbInit->stcPort.stcPort3.u32PortState = EMB_PORT3_DISABLE;
+ pstcEmbInit->stcPort.stcPort3.u32PortLevel = EMB_PORT3_DETECT_LVL_HIGH;
+ pstcEmbInit->stcPort.stcPort3.u32PortFilterDiv = EMB_PORT3_FILTER_CLK_DIV1;
+ pstcEmbInit->stcPort.stcPort3.u32PortFilterState = EMB_PORT3_FILTER_DISABLE;
+ pstcEmbInit->stcPort.stcPort4.u32PortState = EMB_PORT4_DISABLE;
+ pstcEmbInit->stcPort.stcPort4.u32PortLevel = EMB_PORT4_DETECT_LVL_HIGH;
+ pstcEmbInit->stcPort.stcPort4.u32PortFilterDiv = EMB_PORT4_FILTER_CLK_DIV1;
+ pstcEmbInit->stcPort.stcPort4.u32PortFilterState = EMB_PORT4_FILTER_DISABLE;
+ pstcEmbInit->stcPort.stcPort5.u32PortState = EMB_PORT5_DISABLE;
+ pstcEmbInit->stcPort.stcPort5.u32PortLevel = EMB_PORT5_DETECT_LVL_HIGH;
+ pstcEmbInit->stcPort.stcPort5.u32PortFilterDiv = EMB_PORT5_FILTER_CLK_DIV1;
+ pstcEmbInit->stcPort.stcPort5.u32PortFilterState = EMB_PORT5_FILTER_DISABLE;
+
+ /* PWM */
+ pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmState = EMB_TMR4_PWM_U_DISABLE;
+ pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmLevel = EMB_DETECT_TMR4_PWM_U_BOTH_LOW;
+ pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmState = EMB_TMR4_PWM_V_DISABLE;
+ pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmLevel = EMB_DETECT_TMR4_PWM_V_BOTH_LOW;
+ pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmState = EMB_TMR4_PWM_W_DISABLE;
+ pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmLevel = EMB_DETECT_TMR4_PWM_W_BOTH_LOW;
+
+ /* System */
+ pstcEmbInit->stcSys.u32Osc = EMB_OSC_DISABLE;
+ pstcEmbInit->stcSys.u32SramEccError = EMB_SRAM_ECC_ERR_DISABLE;
+ pstcEmbInit->stcSys.u32SramParityError = EMB_SRAM_PARITY_ERR_DISABLE;
+ pstcEmbInit->stcSys.u32Lockup = EMB_LOCKUP_DISABLE;
+ pstcEmbInit->stcSys.u32Lvd = EMB_LVD_DISABLE;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize EMB for TMR4.
+ * @param [in] EMBx Pointer to EMB instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_EMBx: EMB group instance register base
+ * @param [in] pstcEmbInit Pointer to a @ref stc_emb_tmr4_init_t structure
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcEmbInit value is NULL.
+ */
+int32_t EMB_TMR4_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr4_init_t *pstcEmbInit)
+{
+ uint32_t u32Reg1Value;
+ uint32_t u32Reg2Value;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcEmbInit) {
+ DDL_ASSERT(IS_EMB_TMR4_GROUP(EMBx));
+ DDL_ASSERT(IS_EMB_CMP1_STAT(pstcEmbInit->stcCmp.u32Cmp1State));
+ DDL_ASSERT(IS_EMB_CMP2_STAT(pstcEmbInit->stcCmp.u32Cmp2State));
+ DDL_ASSERT(IS_EMB_CMP3_STAT(pstcEmbInit->stcCmp.u32Cmp3State));
+ DDL_ASSERT(IS_EMB_CMP4_STAT(pstcEmbInit->stcCmp.u32Cmp4State));
+ DDL_ASSERT(IS_EMB_PORT1_STAT(pstcEmbInit->stcPort.stcPort1.u32PortState));
+ DDL_ASSERT(IS_EMB_PORT1_DETECT_LVL(pstcEmbInit->stcPort.stcPort1.u32PortLevel));
+ DDL_ASSERT(IS_EMB_PORT1_FILTER_DIV(pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv));
+ DDL_ASSERT(IS_EMB_PORT1_FILTER_STAT(pstcEmbInit->stcPort.stcPort1.u32PortFilterState));
+ DDL_ASSERT(IS_EMB_PORT1_STAT(pstcEmbInit->stcPort.stcPort1.u32PortState));
+ DDL_ASSERT(IS_EMB_PORT1_DETECT_LVL(pstcEmbInit->stcPort.stcPort1.u32PortLevel));
+ DDL_ASSERT(IS_EMB_PORT1_FILTER_DIV(pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv));
+ DDL_ASSERT(IS_EMB_PORT1_FILTER_STAT(pstcEmbInit->stcPort.stcPort1.u32PortFilterState));
+ DDL_ASSERT(IS_EMB_PORT2_STAT(pstcEmbInit->stcPort.stcPort2.u32PortState));
+ DDL_ASSERT(IS_EMB_PORT2_DETECT_LVL(pstcEmbInit->stcPort.stcPort2.u32PortLevel));
+ DDL_ASSERT(IS_EMB_PORT2_FILTER_DIV(pstcEmbInit->stcPort.stcPort2.u32PortFilterDiv));
+ DDL_ASSERT(IS_EMB_PORT2_FILTER_STAT(pstcEmbInit->stcPort.stcPort2.u32PortFilterState));
+ DDL_ASSERT(IS_EMB_PORT3_STAT(pstcEmbInit->stcPort.stcPort3.u32PortState));
+ DDL_ASSERT(IS_EMB_PORT3_DETECT_LVL(pstcEmbInit->stcPort.stcPort3.u32PortLevel));
+ DDL_ASSERT(IS_EMB_PORT3_FILTER_DIV(pstcEmbInit->stcPort.stcPort3.u32PortFilterDiv));
+ DDL_ASSERT(IS_EMB_PORT3_FILTER_STAT(pstcEmbInit->stcPort.stcPort3.u32PortFilterState));
+ DDL_ASSERT(IS_EMB_PORT4_STAT(pstcEmbInit->stcPort.stcPort4.u32PortState));
+ DDL_ASSERT(IS_EMB_PORT4_DETECT_LVL(pstcEmbInit->stcPort.stcPort4.u32PortLevel));
+ DDL_ASSERT(IS_EMB_PORT4_FILTER_DIV(pstcEmbInit->stcPort.stcPort4.u32PortFilterDiv));
+ DDL_ASSERT(IS_EMB_PORT4_FILTER_STAT(pstcEmbInit->stcPort.stcPort4.u32PortFilterState));
+ DDL_ASSERT(IS_EMB_PORT5_STAT(pstcEmbInit->stcPort.stcPort5.u32PortState));
+ DDL_ASSERT(IS_EMB_PORT5_DETECT_LVL(pstcEmbInit->stcPort.stcPort5.u32PortLevel));
+ DDL_ASSERT(IS_EMB_PORT5_FILTER_DIV(pstcEmbInit->stcPort.stcPort5.u32PortFilterDiv));
+ DDL_ASSERT(IS_EMB_PORT5_FILTER_STAT(pstcEmbInit->stcPort.stcPort5.u32PortFilterState));
+ DDL_ASSERT(IS_EMB_TMR4_PWM_U_STAT(pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmState));
+ DDL_ASSERT(IS_EMB_DETECT_TMR4_PWM_U_LVL(pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmLevel));
+ DDL_ASSERT(IS_EMB_TMR4_PWM_V_STAT(pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmState));
+ DDL_ASSERT(IS_EMB_DETECT_TMR4_PWM_V_LVL(pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmLevel));
+ DDL_ASSERT(IS_EMB_TMR4_PWM_W_STAT(pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmState));
+ DDL_ASSERT(IS_EMB_DETECT_TMR4_PWM_W_LVL(pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmLevel));
+ DDL_ASSERT(IS_EMB_OSC_STAT(pstcEmbInit->stcSys.u32Osc));
+ DDL_ASSERT(IS_EMB_SRAM_ECC_ERR_STAT(pstcEmbInit->stcSys.u32SramEccError));
+ DDL_ASSERT(IS_EMB_SRAM_PARITY_ERR_STAT(pstcEmbInit->stcSys.u32SramParityError));
+ DDL_ASSERT(IS_EMB_LOCKUP_STAT(pstcEmbInit->stcSys.u32Lockup));
+ DDL_ASSERT(IS_EMB_LVD_STAT(pstcEmbInit->stcSys.u32Lvd));
+
+ u32Reg2Value = 0UL;
+
+ /* PWM */
+ u32Reg1Value = (pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmState | pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmState | \
+ pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmState);
+ u32Reg2Value |= (pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmLevel | pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmLevel | \
+ pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmLevel);
+
+ /* CMP */
+ u32Reg1Value |= (pstcEmbInit->stcCmp.u32Cmp1State | pstcEmbInit->stcCmp.u32Cmp2State | \
+ pstcEmbInit->stcCmp.u32Cmp3State | pstcEmbInit->stcCmp.u32Cmp4State);
+
+ /* PORT */
+ u32Reg1Value |= (pstcEmbInit->stcPort.stcPort1.u32PortState | pstcEmbInit->stcPort.stcPort1.u32PortLevel | \
+ pstcEmbInit->stcPort.stcPort2.u32PortState | pstcEmbInit->stcPort.stcPort2.u32PortLevel | \
+ pstcEmbInit->stcPort.stcPort3.u32PortState | pstcEmbInit->stcPort.stcPort3.u32PortLevel | \
+ pstcEmbInit->stcPort.stcPort4.u32PortState | pstcEmbInit->stcPort.stcPort4.u32PortLevel | \
+ pstcEmbInit->stcPort.stcPort5.u32PortState | pstcEmbInit->stcPort.stcPort5.u32PortLevel);
+ u32Reg2Value |= (pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort1.u32PortFilterState | \
+ pstcEmbInit->stcPort.stcPort2.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort2.u32PortFilterState | \
+ pstcEmbInit->stcPort.stcPort3.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort3.u32PortFilterState | \
+ pstcEmbInit->stcPort.stcPort4.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort4.u32PortFilterState | \
+ pstcEmbInit->stcPort.stcPort5.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort5.u32PortFilterState);
+
+ /* System */
+ u32Reg1Value |= (pstcEmbInit->stcSys.u32Osc | pstcEmbInit->stcSys.u32SramEccError | \
+ pstcEmbInit->stcSys.u32Lockup | pstcEmbInit->stcSys.u32SramParityError | \
+ pstcEmbInit->stcSys.u32Lvd);
+ if ((pstcEmbInit->stcSys.u32Osc != 0UL) || (pstcEmbInit->stcSys.u32SramParityError != 0UL) || \
+ (pstcEmbInit->stcSys.u32SramEccError != 0UL) || (pstcEmbInit->stcSys.u32Lockup != 0UL) || \
+ (pstcEmbInit->stcSys.u32Lvd != 0UL)) {
+ u32Reg1Value |= EMB_CTL1_SYSEN;
+ }
+
+ WRITE_REG32(EMBx->CTL2, u32Reg2Value);
+ WRITE_REG32(EMBx->CTL1, u32Reg1Value);
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set the fields of structure stc_emb_tmr6_init_t to default values
+ * @param [out] pstcEmbInit Pointer to a @ref stc_emb_tmr6_init_t structure
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcEmbInit value is NULL.
+ */
+int32_t EMB_TMR6_StructInit(stc_emb_tmr6_init_t *pstcEmbInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcEmbInit) {
+
+ /* CMP */
+ pstcEmbInit->stcCmp.u32Cmp1State = EMB_CMP1_DISABLE;
+ pstcEmbInit->stcCmp.u32Cmp2State = EMB_CMP2_DISABLE;
+ pstcEmbInit->stcCmp.u32Cmp3State = EMB_CMP3_DISABLE;
+ pstcEmbInit->stcCmp.u32Cmp4State = EMB_CMP4_DISABLE;
+
+ /* Port */
+ pstcEmbInit->stcPort.stcPort1.u32PortState = EMB_PORT1_DISABLE;
+ pstcEmbInit->stcPort.stcPort1.u32PortLevel = EMB_PORT1_DETECT_LVL_HIGH;
+ pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv = EMB_PORT1_FILTER_CLK_DIV1;
+ pstcEmbInit->stcPort.stcPort1.u32PortFilterState = EMB_PORT1_FILTER_DISABLE;
+ pstcEmbInit->stcPort.stcPort2.u32PortState = EMB_PORT2_DISABLE;
+ pstcEmbInit->stcPort.stcPort2.u32PortLevel = EMB_PORT2_DETECT_LVL_HIGH;
+ pstcEmbInit->stcPort.stcPort2.u32PortFilterDiv = EMB_PORT2_FILTER_CLK_DIV1;
+ pstcEmbInit->stcPort.stcPort2.u32PortFilterState = EMB_PORT2_FILTER_DISABLE;
+ pstcEmbInit->stcPort.stcPort3.u32PortState = EMB_PORT3_DISABLE;
+ pstcEmbInit->stcPort.stcPort3.u32PortLevel = EMB_PORT3_DETECT_LVL_HIGH;
+ pstcEmbInit->stcPort.stcPort3.u32PortFilterDiv = EMB_PORT3_FILTER_CLK_DIV1;
+ pstcEmbInit->stcPort.stcPort3.u32PortFilterState = EMB_PORT3_FILTER_DISABLE;
+ pstcEmbInit->stcPort.stcPort4.u32PortState = EMB_PORT4_DISABLE;
+ pstcEmbInit->stcPort.stcPort4.u32PortLevel = EMB_PORT4_DETECT_LVL_HIGH;
+ pstcEmbInit->stcPort.stcPort4.u32PortFilterDiv = EMB_PORT4_FILTER_CLK_DIV1;
+ pstcEmbInit->stcPort.stcPort4.u32PortFilterState = EMB_PORT4_FILTER_DISABLE;
+ pstcEmbInit->stcPort.stcPort5.u32PortState = EMB_PORT5_DISABLE;
+ pstcEmbInit->stcPort.stcPort5.u32PortLevel = EMB_PORT5_DETECT_LVL_HIGH;
+ pstcEmbInit->stcPort.stcPort5.u32PortFilterDiv = EMB_PORT5_FILTER_CLK_DIV1;
+ pstcEmbInit->stcPort.stcPort5.u32PortFilterState = EMB_PORT5_FILTER_DISABLE;
+ /* PWM */
+ pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmLevel = EMB_DETECT_TMR6_1_PWM_BOTH_LOW;
+ pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmState = EMB_TMR6_1_PWM_DISABLE;
+ pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmLevel = EMB_DETECT_TMR6_2_PWM_BOTH_LOW;
+ pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmState = EMB_TMR6_2_PWM_DISABLE;
+ pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmLevel = EMB_DETECT_TMR6_3_PWM_BOTH_LOW;
+ pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmState = EMB_TMR6_3_PWM_DISABLE;
+ pstcEmbInit->stcTmr6.stcTmr6_4.u32PwmLevel = EMB_DETECT_TMR6_4_PWM_BOTH_LOW;
+ pstcEmbInit->stcTmr6.stcTmr6_4.u32PwmState = EMB_TMR6_4_PWM_DISABLE;
+ pstcEmbInit->stcTmr6.stcTmr6_5.u32PwmLevel = EMB_DETECT_TMR6_6_PWM_BOTH_LOW;
+ pstcEmbInit->stcTmr6.stcTmr6_5.u32PwmState = EMB_TMR6_5_PWM_DISABLE;
+ pstcEmbInit->stcTmr6.stcTmr6_6.u32PwmLevel = EMB_DETECT_TMR6_6_PWM_BOTH_LOW;
+ pstcEmbInit->stcTmr6.stcTmr6_6.u32PwmState = EMB_TMR6_6_PWM_DISABLE;
+ pstcEmbInit->stcTmr6.stcTmr6_7.u32PwmLevel = EMB_DETECT_TMR6_7_PWM_BOTH_LOW;
+ pstcEmbInit->stcTmr6.stcTmr6_7.u32PwmState = EMB_TMR6_7_PWM_DISABLE;
+ pstcEmbInit->stcTmr6.stcTmr6_8.u32PwmLevel = EMB_DETECT_TMR6_8_PWM_BOTH_LOW;
+ pstcEmbInit->stcTmr6.stcTmr6_8.u32PwmState = EMB_TMR6_8_PWM_DISABLE;
+ pstcEmbInit->stcTmr6.stcTmr6_9.u32PwmLevel = EMB_DETECT_TMR6_9_PWM_BOTH_LOW;
+ pstcEmbInit->stcTmr6.stcTmr6_9.u32PwmState = EMB_TMR6_9_PWM_DISABLE;
+ pstcEmbInit->stcTmr6.stcTmr6_10.u32PwmLevel = EMB_DETECT_TMR6_10_PWM_BOTH_LOW;
+ pstcEmbInit->stcTmr6.stcTmr6_10.u32PwmState = EMB_TMR6_10_PWM_DISABLE;
+
+ /* System */
+ pstcEmbInit->stcSys.u32Osc = EMB_OSC_DISABLE;
+ pstcEmbInit->stcSys.u32SramEccError = EMB_SRAM_ECC_ERR_DISABLE;
+ pstcEmbInit->stcSys.u32SramParityError = EMB_SRAM_PARITY_ERR_DISABLE;
+ pstcEmbInit->stcSys.u32Lockup = EMB_LOCKUP_DISABLE;
+ pstcEmbInit->stcSys.u32Lvd = EMB_LVD_DISABLE;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize EMB for TMR6.
+ * @param [in] EMBx Pointer to EMB instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_EMBx: EMB group instance register base
+ * @param [in] pstcEmbInit Pointer to a @ref stc_emb_tmr6_init_t structure
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcEmbInit value is NULL.
+ */
+int32_t EMB_TMR6_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr6_init_t *pstcEmbInit)
+{
+ uint32_t u32Reg1Value;
+ uint32_t u32Reg2Value;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcEmbInit) {
+ DDL_ASSERT(IS_EMB_TMR6_GROUP(EMBx));
+ DDL_ASSERT(IS_EMB_CMP1_STAT(pstcEmbInit->stcCmp.u32Cmp1State));
+ DDL_ASSERT(IS_EMB_CMP2_STAT(pstcEmbInit->stcCmp.u32Cmp2State));
+ DDL_ASSERT(IS_EMB_CMP3_STAT(pstcEmbInit->stcCmp.u32Cmp3State));
+ DDL_ASSERT(IS_EMB_CMP4_STAT(pstcEmbInit->stcCmp.u32Cmp4State));
+ DDL_ASSERT(IS_EMB_PORT1_STAT(pstcEmbInit->stcPort.stcPort1.u32PortState));
+ DDL_ASSERT(IS_EMB_PORT1_DETECT_LVL(pstcEmbInit->stcPort.stcPort1.u32PortLevel));
+ DDL_ASSERT(IS_EMB_PORT1_FILTER_DIV(pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv));
+ DDL_ASSERT(IS_EMB_PORT1_FILTER_STAT(pstcEmbInit->stcPort.stcPort1.u32PortFilterState));
+ DDL_ASSERT(IS_EMB_PORT2_STAT(pstcEmbInit->stcPort.stcPort2.u32PortState));
+ DDL_ASSERT(IS_EMB_PORT2_DETECT_LVL(pstcEmbInit->stcPort.stcPort2.u32PortLevel));
+ DDL_ASSERT(IS_EMB_PORT2_FILTER_DIV(pstcEmbInit->stcPort.stcPort2.u32PortFilterDiv));
+ DDL_ASSERT(IS_EMB_PORT2_FILTER_STAT(pstcEmbInit->stcPort.stcPort2.u32PortFilterState));
+ DDL_ASSERT(IS_EMB_PORT3_STAT(pstcEmbInit->stcPort.stcPort3.u32PortState));
+ DDL_ASSERT(IS_EMB_PORT3_DETECT_LVL(pstcEmbInit->stcPort.stcPort3.u32PortLevel));
+ DDL_ASSERT(IS_EMB_PORT3_FILTER_DIV(pstcEmbInit->stcPort.stcPort3.u32PortFilterDiv));
+ DDL_ASSERT(IS_EMB_PORT3_FILTER_STAT(pstcEmbInit->stcPort.stcPort3.u32PortFilterState));
+ DDL_ASSERT(IS_EMB_PORT4_STAT(pstcEmbInit->stcPort.stcPort4.u32PortState));
+ DDL_ASSERT(IS_EMB_PORT4_DETECT_LVL(pstcEmbInit->stcPort.stcPort4.u32PortLevel));
+ DDL_ASSERT(IS_EMB_PORT4_FILTER_DIV(pstcEmbInit->stcPort.stcPort4.u32PortFilterDiv));
+ DDL_ASSERT(IS_EMB_PORT4_FILTER_STAT(pstcEmbInit->stcPort.stcPort4.u32PortFilterState));
+ DDL_ASSERT(IS_EMB_PORT5_STAT(pstcEmbInit->stcPort.stcPort5.u32PortState));
+ DDL_ASSERT(IS_EMB_PORT5_DETECT_LVL(pstcEmbInit->stcPort.stcPort5.u32PortLevel));
+ DDL_ASSERT(IS_EMB_PORT5_FILTER_DIV(pstcEmbInit->stcPort.stcPort5.u32PortFilterDiv));
+ DDL_ASSERT(IS_EMB_PORT5_FILTER_STAT(pstcEmbInit->stcPort.stcPort5.u32PortFilterState));
+ DDL_ASSERT(IS_EMB_TMR6_1_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmState));
+ DDL_ASSERT(IS_EMB_DETECT_TMR6_1_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmLevel));
+ DDL_ASSERT(IS_EMB_TMR6_2_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmState));
+ DDL_ASSERT(IS_EMB_DETECT_TMR6_2_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmLevel));
+ DDL_ASSERT(IS_EMB_TMR6_3_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmState));
+ DDL_ASSERT(IS_EMB_DETECT_TMR6_3_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmLevel));
+ DDL_ASSERT(IS_EMB_TMR6_4_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_4.u32PwmState));
+ DDL_ASSERT(IS_EMB_DETECT_TMR6_4_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_4.u32PwmLevel));
+ DDL_ASSERT(IS_EMB_TMR6_5_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_5.u32PwmState));
+ DDL_ASSERT(IS_EMB_DETECT_TMR6_5_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_5.u32PwmLevel));
+ DDL_ASSERT(IS_EMB_TMR6_6_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_6.u32PwmState));
+ DDL_ASSERT(IS_EMB_DETECT_TMR6_6_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_6.u32PwmLevel));
+ DDL_ASSERT(IS_EMB_TMR6_7_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_7.u32PwmState));
+ DDL_ASSERT(IS_EMB_DETECT_TMR6_7_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_7.u32PwmLevel));
+ DDL_ASSERT(IS_EMB_TMR6_8_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_8.u32PwmState));
+ DDL_ASSERT(IS_EMB_DETECT_TMR6_8_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_8.u32PwmLevel));
+ DDL_ASSERT(IS_EMB_TMR6_9_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_9.u32PwmState));
+ DDL_ASSERT(IS_EMB_DETECT_TMR6_9_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_9.u32PwmLevel));
+ DDL_ASSERT(IS_EMB_TMR6_10_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_10.u32PwmState));
+ DDL_ASSERT(IS_EMB_DETECT_TMR6_10_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_10.u32PwmLevel));
+ DDL_ASSERT(IS_EMB_OSC_STAT(pstcEmbInit->stcSys.u32Osc));
+ DDL_ASSERT(IS_EMB_SRAM_ECC_ERR_STAT(pstcEmbInit->stcSys.u32SramEccError));
+ DDL_ASSERT(IS_EMB_SRAM_PARITY_ERR_STAT(pstcEmbInit->stcSys.u32SramParityError));
+ DDL_ASSERT(IS_EMB_LOCKUP_STAT(pstcEmbInit->stcSys.u32Lockup));
+ DDL_ASSERT(IS_EMB_LVD_STAT(pstcEmbInit->stcSys.u32Lvd));
+
+ u32Reg2Value = 0UL;
+
+ /* PWM */
+ u32Reg1Value = (pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmState | pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmState | \
+ pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmState | pstcEmbInit->stcTmr6.stcTmr6_4.u32PwmState | \
+ pstcEmbInit->stcTmr6.stcTmr6_5.u32PwmState | pstcEmbInit->stcTmr6.stcTmr6_6.u32PwmState | \
+ pstcEmbInit->stcTmr6.stcTmr6_7.u32PwmState | pstcEmbInit->stcTmr6.stcTmr6_8.u32PwmState | \
+ pstcEmbInit->stcTmr6.stcTmr6_9.u32PwmState | pstcEmbInit->stcTmr6.stcTmr6_10.u32PwmState);
+ u32Reg2Value |= (pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmLevel | pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmLevel | \
+ pstcEmbInit->stcTmr6.stcTmr6_3.u32PwmLevel | pstcEmbInit->stcTmr6.stcTmr6_4.u32PwmLevel | \
+ pstcEmbInit->stcTmr6.stcTmr6_5.u32PwmLevel | pstcEmbInit->stcTmr6.stcTmr6_6.u32PwmLevel | \
+ pstcEmbInit->stcTmr6.stcTmr6_7.u32PwmLevel | pstcEmbInit->stcTmr6.stcTmr6_8.u32PwmLevel | \
+ pstcEmbInit->stcTmr6.stcTmr6_9.u32PwmLevel | pstcEmbInit->stcTmr6.stcTmr6_10.u32PwmLevel);
+
+ /* CMP */
+ u32Reg1Value |= (pstcEmbInit->stcCmp.u32Cmp1State | pstcEmbInit->stcCmp.u32Cmp2State | \
+ pstcEmbInit->stcCmp.u32Cmp3State | pstcEmbInit->stcCmp.u32Cmp4State);
+
+ /* PORT */
+ u32Reg1Value |= (pstcEmbInit->stcPort.stcPort1.u32PortState | pstcEmbInit->stcPort.stcPort1.u32PortLevel | \
+ pstcEmbInit->stcPort.stcPort2.u32PortState | pstcEmbInit->stcPort.stcPort2.u32PortLevel | \
+ pstcEmbInit->stcPort.stcPort3.u32PortState | pstcEmbInit->stcPort.stcPort3.u32PortLevel | \
+ pstcEmbInit->stcPort.stcPort4.u32PortState | pstcEmbInit->stcPort.stcPort4.u32PortLevel | \
+ pstcEmbInit->stcPort.stcPort5.u32PortState | pstcEmbInit->stcPort.stcPort5.u32PortLevel);
+ u32Reg2Value |= (pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort1.u32PortFilterState | \
+ pstcEmbInit->stcPort.stcPort2.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort2.u32PortFilterState | \
+ pstcEmbInit->stcPort.stcPort3.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort3.u32PortFilterState | \
+ pstcEmbInit->stcPort.stcPort4.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort4.u32PortFilterState | \
+ pstcEmbInit->stcPort.stcPort5.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort5.u32PortFilterState);
+
+ u32Reg1Value |= (pstcEmbInit->stcSys.u32Osc | pstcEmbInit->stcSys.u32SramEccError | \
+ pstcEmbInit->stcSys.u32Lockup | pstcEmbInit->stcSys.u32SramParityError | \
+ pstcEmbInit->stcSys.u32Lvd);
+ if ((pstcEmbInit->stcSys.u32Osc != 0UL) || (pstcEmbInit->stcSys.u32SramParityError != 0UL) || \
+ (pstcEmbInit->stcSys.u32SramEccError != 0UL) || (pstcEmbInit->stcSys.u32Lockup != 0UL) || \
+ (pstcEmbInit->stcSys.u32Lvd != 0UL)) {
+ u32Reg1Value |= EMB_CTL1_SYSEN;
+ }
+
+ WRITE_REG32(EMBx->CTL2, u32Reg2Value);
+ WRITE_REG32(EMBx->CTL1, u32Reg1Value);
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief De-Initialize EMB function
+ * @param [in] EMBx Pointer to EMB instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_EMBx: EMB group instance register base
+ * @retval None
+ */
+void EMB_DeInit(CM_EMB_TypeDef *EMBx)
+{
+ DDL_ASSERT(IS_EMB_GROUP(EMBx));
+
+ WRITE_REG32(EMBx->SOE, 0x00UL);
+ WRITE_REG32(EMBx->INTEN, 0x00UL);
+ WRITE_REG32(EMBx->RLSSEL, 0x00UL);
+}
+
+/**
+ * @brief Set the EMB interrupt function
+ * @param [in] EMBx Pointer to EMB instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_EMBx: EMB group instance register base
+ * @param [in] u32IntType EMB interrupt source
+ * This parameter can be any composed value of the macros group @ref EMB_Interrupt.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void EMB_IntCmd(CM_EMB_TypeDef *EMBx, uint32_t u32IntType, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_EMB_GROUP(EMBx));
+ DDL_ASSERT(IS_VALID_EMB_INT(u32IntType));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(EMBx->INTEN, u32IntType);
+ } else {
+ CLR_REG32_BIT(EMBx->INTEN, u32IntType);
+ }
+}
+
+/**
+ * @brief Clear EMB flag status.
+ * @param [in] EMBx Pointer to EMB instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_EMBx: EMB group instance register base
+ * @param [in] u32Flag EMB flag
+ * This parameter can be any composed value(prefix with EMB_FLAG) of the macros group @ref EMB_Flag_State.
+ * @retval None
+ * @note This parameter u32Flag prefix with EMB_FLAG(eg EMB_FLAG_CMP) of the macros group @ref EMB_Flag_State.
+ */
+void EMB_ClearStatus(CM_EMB_TypeDef *EMBx, uint32_t u32Flag)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_EMB_GROUP(EMBx));
+ DDL_ASSERT(IS_EMB_CLR_FLAG(u32Flag));
+
+ SET_REG32_BIT(EMBx->STATCLR, u32Flag);
+}
+
+/**
+ * @brief Get EMB flag status.
+ * @param [in] EMBx Pointer to EMB instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_EMBx: EMB group instance register base
+ * @param [in] u32Flag EMB flag
+ * This parameter can be any composed value of the macros group @ref EMB_Flag_State.
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t EMB_GetStatus(const CM_EMB_TypeDef *EMBx, uint32_t u32Flag)
+{
+ DDL_ASSERT(IS_EMB_GROUP(EMBx));
+ DDL_ASSERT(IS_EMB_FLAG(u32Flag));
+
+ return (READ_REG32_BIT(EMBx->STAT, u32Flag) == 0UL) ? RESET : SET;
+}
+
+/**
+ * @brief Start/stop EMB brake by software control
+ * @param [in] EMBx Pointer to EMB instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_EMBx: EMB group instance register base
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void EMB_SWBrake(CM_EMB_TypeDef *EMBx, en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_EMB_GROUP(EMBx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ WRITE_REG32(EMBx->SOE, enNewState);
+}
+
+/**
+ * @brief Set EMB release PWM condition for the specified event.
+ * @param [in] EMBx Pointer to EMB instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_EMBx: EMB group instance register base
+ * @param [in] u32Event Monitor event
+ * This parameter can be any composed value of the macros group @ref EMB_Monitor_Event.
+ * @param [in] u32Cond Release PWM condition
+ * This parameter can be one of the macros group @ref EMB_Release_TMR_PWM_Condition
+ * @arg EMB_RELEASE_PWM_COND_FLAG_ZERO: Release PWM when flag bit of the specified event is zero
+ * @arg EMB_RELEASE_PWM_COND_STAT_ZERO: Release PWM when state bit of the specified event is zero
+ * @retval None
+ */
+void EMB_SetReleasePwmCond(CM_EMB_TypeDef *EMBx, uint32_t u32Event, uint32_t u32Cond)
+{
+ DDL_ASSERT(IS_EMB_GROUP(EMBx));
+ DDL_ASSERT(IS_EMB_MONITOR_EVT(u32Event));
+ DDL_ASSERT(IS_EMB_RELEASE_PWM_COND(u32Cond));
+
+ if (EMB_RELEASE_PWM_COND_FLAG_ZERO == u32Cond) {
+ CLR_REG32_BIT(EMBx->RLSSEL, u32Event);
+ } else {
+ SET_REG32_BIT(EMBx->RLSSEL, u32Event);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_EMB_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_event_port.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_event_port.c
new file mode 100644
index 0000000000..27fd0a34cc
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_event_port.c
@@ -0,0 +1,442 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_event_port.c
+ * @brief This file provides firmware functions to manage the Event Port (EP).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_event_port.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_EVENT_PORT EVENT_PORT
+ * @brief Event Port Driver Library
+ * @{
+ */
+
+#if (LL_EVENT_PORT_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup EP_Local_Macros Event Port Local Macros
+ * @{
+ */
+#define EP_OFFSET (0x1CUL)
+#define PEVNTDIR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTDIRR1) + (EP_OFFSET * (x))))
+#define PEVNTIDR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTIDR1) + (EP_OFFSET * (x))))
+#define PEVNTODR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTODR1) + (EP_OFFSET * (x))))
+#define PEVNTORR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTORR1) + (EP_OFFSET * (x))))
+#define PEVNTOSR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTOSR1) + (EP_OFFSET * (x))))
+#define PEVNTRIS_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTRISR1) + (EP_OFFSET * (x))))
+#define PEVNTFAL_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTFALR1) + (EP_OFFSET * (x))))
+#define PEVNTTRGSR_RST_VALUE (0x1FFUL)
+#define EP_PIN_MAX (16U)
+
+/**
+ * @defgroup EP_Check_Parameters_Validity Event Port Check Parameters Validity
+ * @{
+ */
+/*! Parameter validity check for port group. */
+#define IS_EVENT_PORT(port) \
+( ((port) == EVT_PORT_1) || \
+ ((port) == EVT_PORT_2) || \
+ ((port) == EVT_PORT_3) || \
+ ((port) == EVT_PORT_4))
+
+/*! Parameter valid check for event port trigger edge. */
+#define IS_EP_TRIG_EDGE(edge) \
+( ((edge) == EP_TRIG_NONE) || \
+ ((edge) == EP_TRIG_FALLING) || \
+ ((edge) == EP_TRIG_RISING) || \
+ ((edge) == EP_TRIG_BOTH))
+
+/*! Parameter valid check for event port initial output state. */
+#define IS_EP_STATE(state) \
+( ((state) == EVT_PIN_RESET) || \
+ ((state) == EVT_PIN_SET))
+
+/*! Parameter valid check for event port filter function. */
+#define IS_EP_FILTER(filter) \
+( ((filter) == EP_FILTER_OFF) || \
+ ((filter) == EP_FILTER_ON))
+
+/*! Parameter validity check for pin. */
+#define IS_EVENT_PIN(pin) (((pin) & EVT_PIN_MASK ) != 0x0000U)
+
+/*! Parameter valid check for event port operation after triggered. */
+#define IS_EP_OPS(ops) \
+( ((ops) == EP_OPS_NONE) || \
+ ((ops) == EP_OPS_LOW) || \
+ ((ops) == EP_OPS_HIGH) || \
+ ((ops) == EP_OPS_TOGGLE))
+
+/*! Parameter valid check for event port direction. */
+#define IS_EP_DIR(dir) \
+( ((dir) == EP_DIR_IN) || \
+ ((dir) == EP_DIR_OUT))
+
+/*! Parameter valid check for event port filter clock div. */
+#define IS_EP_FILTER_CLK(clk) \
+( ((clk) == EP_FCLK_DIV1) || \
+ ((clk) == EP_FCLK_DIV8) || \
+ ((clk) == EP_FCLK_DIV32) || \
+ ((clk) == EP_FCLK_DIV64))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup EP_Global_Functions Event Port Global Functions
+ * @{
+ */
+
+/**
+ * @brief Initialize Event Port.
+ * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP port peripheral
+ * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index
+ * @param [in] pstcEventPortInit Pointer to a stc_ep_init_t structure that
+ * contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: Event Port initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t EP_Init(uint8_t u8EventPort, uint16_t u16EventPin, const stc_ep_init_t *pstcEventPortInit)
+{
+ uint16_t u16PinPos;
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcEventPortInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ DDL_ASSERT(IS_EVENT_PORT(u8EventPort));
+ DDL_ASSERT(IS_EVENT_PIN(u16EventPin));
+ DDL_ASSERT(IS_EP_OPS(pstcEventPortInit->u32PinTriggerOps));
+ DDL_ASSERT(IS_EP_DIR(pstcEventPortInit->u32PinDir));
+ DDL_ASSERT(IS_EP_STATE(pstcEventPortInit->enPinState));
+ DDL_ASSERT(IS_EP_TRIG_EDGE(pstcEventPortInit->u32Edge));
+ DDL_ASSERT(IS_EP_FILTER(pstcEventPortInit->u32Filter));
+ DDL_ASSERT(IS_EP_FILTER_CLK(pstcEventPortInit->u32FilterClock));
+
+ for (u16PinPos = 0U; u16PinPos < EP_PIN_MAX; u16PinPos++) {
+ if ((u16EventPin & (1UL << u16PinPos)) != 0U) {
+ /* Direction config */
+ if (EP_DIR_OUT == pstcEventPortInit->u32PinDir) {
+ SET_REG32_BIT(PEVNTDIR_REG(u8EventPort), u16EventPin);
+ } else {
+ CLR_REG32_BIT(PEVNTDIR_REG(u8EventPort), u16EventPin);
+ }
+ /* Set pin initial output value */
+ if (EVT_PIN_SET == pstcEventPortInit->enPinState) {
+ SET_REG32_BIT(PEVNTODR_REG(u8EventPort), u16EventPin);
+ } else {
+ CLR_REG32_BIT(PEVNTODR_REG(u8EventPort), u16EventPin);
+ }
+ /* Set Pin operation after triggered */
+ (void)EP_SetTriggerOps(u8EventPort, u16EventPin, pstcEventPortInit->u32PinTriggerOps);
+ /* Set trigger edge */
+ (void)EP_SetTriggerEdge(u8EventPort, u16EventPin, pstcEventPortInit->u32Edge);
+ }
+ MODIFY_REG32(CM_AOS->PEVNTNFCR, \
+ ((AOS_PEVNTNFCR_NFEN1 | AOS_PEVNTNFCR_DIVS1) << (u8EventPort * 8UL)), \
+ ((pstcEventPortInit->u32Filter | pstcEventPortInit->u32FilterClock) << (u8EventPort * 8UL)));
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief De-init Event Port register to default value
+ * @param None
+ * @retval None
+ */
+void EP_DeInit(void)
+{
+ uint8_t u8EventPort;
+
+ /* Restore all registers to default value */
+ WRITE_REG32(CM_AOS->PEVNT_TRGSEL12, PEVNTTRGSR_RST_VALUE);
+ WRITE_REG32(CM_AOS->PEVNT_TRGSEL34, PEVNTTRGSR_RST_VALUE);
+ WRITE_REG32(CM_AOS->PEVNTNFCR, 0UL);
+ for (u8EventPort = EVT_PORT_1; u8EventPort < EVT_PORT_4; u8EventPort++) {
+ WRITE_REG32(PEVNTDIR_REG(u8EventPort), 0UL);
+ WRITE_REG32(PEVNTODR_REG(u8EventPort), 0UL);
+ WRITE_REG32(PEVNTORR_REG(u8EventPort), 0UL);
+ WRITE_REG32(PEVNTOSR_REG(u8EventPort), 0UL);
+ WRITE_REG32(PEVNTRIS_REG(u8EventPort), 0UL);
+ WRITE_REG32(PEVNTFAL_REG(u8EventPort), 0UL);
+ }
+}
+
+/**
+ * @brief Initialize Event Port config structure. Fill each pstcEventPortInit with default value
+ * @param [in] pstcEventPortInit: Pointer to a stc_ep_init_t structure that
+ * contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: Event Port structure initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t EP_StructInit(stc_ep_init_t *pstcEventPortInit)
+{
+ int32_t i32Ret = LL_OK;
+ /* Check if pointer is NULL */
+ if (NULL == pstcEventPortInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Reset Event Port init structure parameters values */
+ pstcEventPortInit->u32PinDir = EP_DIR_IN;
+ pstcEventPortInit->enPinState = EVT_PIN_RESET;
+ pstcEventPortInit->u32PinTriggerOps = EP_OPS_NONE;
+ pstcEventPortInit->u32Edge = EP_TRIG_NONE;
+ pstcEventPortInit->u32Filter = EP_FILTER_OFF;
+ pstcEventPortInit->u32FilterClock = EP_FCLK_DIV1;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Set event port trigger edge.
+ * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP port peripheral
+ * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index
+ * @param [in] u32Edge: Trigger edge, @ref EP_Trigger_Sel for details
+ * @retval int32_t:
+ * - LL_OK: Trigger edge set successful
+ * - LL_ERR_INVD_PARAM: Undefined edge
+ */
+int32_t EP_SetTriggerEdge(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Edge)
+{
+ int32_t i32Ret = LL_OK;
+
+ DDL_ASSERT(IS_EVENT_PORT(u8EventPort));
+ DDL_ASSERT(IS_EVENT_PIN(u16EventPin));
+ DDL_ASSERT(IS_EP_TRIG_EDGE(u32Edge));
+
+ /* Set trigger edge */
+ switch (u32Edge) {
+ case EP_TRIG_NONE:
+ CLR_REG32_BIT(PEVNTFAL_REG(u8EventPort), u16EventPin);
+ CLR_REG32_BIT(PEVNTRIS_REG(u8EventPort), u16EventPin);
+ break;
+ case EP_TRIG_FALLING:
+ SET_REG32_BIT(PEVNTFAL_REG(u8EventPort), u16EventPin);
+ CLR_REG32_BIT(PEVNTRIS_REG(u8EventPort), u16EventPin);
+ break;
+ case EP_TRIG_RISING:
+ CLR_REG32_BIT(PEVNTFAL_REG(u8EventPort), u16EventPin);
+ SET_REG32_BIT(PEVNTRIS_REG(u8EventPort), u16EventPin);
+ break;
+ case EP_TRIG_BOTH:
+ SET_REG32_BIT(PEVNTFAL_REG(u8EventPort), u16EventPin);
+ SET_REG32_BIT(PEVNTRIS_REG(u8EventPort), u16EventPin);
+ break;
+ default:
+ i32Ret = LL_ERR_INVD_PARAM;
+ break;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Set event port operation after triggered
+ * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral
+ * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index
+ * @param [in] u32Ops: The operation after triggered, @ref EP_TriggerOps_Sel for details
+ * @retval Specified Event port pin input value
+ */
+int32_t EP_SetTriggerOps(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Ops)
+{
+ int32_t i32Ret = LL_OK;
+
+ DDL_ASSERT(IS_EVENT_PORT(u8EventPort));
+ DDL_ASSERT(IS_EVENT_PIN(u16EventPin));
+ DDL_ASSERT(IS_EP_OPS(u32Ops));
+
+ switch (u32Ops) {
+ case EP_OPS_NONE:
+ CLR_REG32_BIT(PEVNTORR_REG(u8EventPort), u16EventPin);
+ CLR_REG32_BIT(PEVNTOSR_REG(u8EventPort), u16EventPin);
+ break;
+ case EP_OPS_LOW:
+ SET_REG32_BIT(PEVNTORR_REG(u8EventPort), u16EventPin);
+ CLR_REG32_BIT(PEVNTOSR_REG(u8EventPort), u16EventPin);
+ break;
+ case EP_OPS_HIGH:
+ CLR_REG32_BIT(PEVNTORR_REG(u8EventPort), u16EventPin);
+ SET_REG32_BIT(PEVNTOSR_REG(u8EventPort), u16EventPin);
+ break;
+ case EP_OPS_TOGGLE:
+ SET_REG32_BIT(PEVNTORR_REG(u8EventPort), u16EventPin);
+ SET_REG32_BIT(PEVNTOSR_REG(u8EventPort), u16EventPin);
+ break;
+ default:
+ i32Ret = LL_ERR_INVD_PARAM;
+ break;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Read specified Event port input data port pins
+ * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral
+ * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index
+ * @retval Specified Event port pin input value
+ */
+en_ep_state_t EP_ReadInputPins(uint8_t u8EventPort, uint16_t u16EventPin)
+{
+ DDL_ASSERT(IS_EVENT_PORT(u8EventPort));
+ DDL_ASSERT(IS_EVENT_PIN(u16EventPin));
+
+ return ((READ_REG32(PEVNTIDR_REG(u8EventPort)) & (u16EventPin)) != 0UL) ? EVT_PIN_SET : EVT_PIN_RESET;
+}
+
+/**
+ * @brief Read specified Event port input data port
+ * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the Event Port peripheral
+ * @retval Specified Event Port input value
+ */
+uint16_t EP_ReadInputPort(uint8_t u8EventPort)
+{
+ DDL_ASSERT(IS_EVENT_PORT(u8EventPort));
+
+ return (uint16_t)(READ_REG32(PEVNTIDR_REG(u8EventPort)) & 0xFFFFUL);
+}
+
+/**
+ * @brief Read specified Event port output data port pins
+ * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral
+ * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index
+ * @retval Specified Event port pin output value
+ */
+en_ep_state_t EP_ReadOutputPins(uint8_t u8EventPort, uint16_t u16EventPin)
+{
+ DDL_ASSERT(IS_EVENT_PORT(u8EventPort));
+ DDL_ASSERT(IS_EVENT_PIN(u16EventPin));
+
+ return ((READ_REG32(PEVNTODR_REG(u8EventPort)) & (u16EventPin)) != 0UL) ? EVT_PIN_SET : EVT_PIN_RESET;
+}
+
+/**
+ * @brief Read specified Event port output data port
+ * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the Event Port peripheral
+ * @retval Specified Event Port output value
+ */
+uint16_t EP_ReadOutputPort(uint8_t u8EventPort)
+{
+ DDL_ASSERT(IS_EVENT_PORT(u8EventPort));
+
+ return (uint16_t)(READ_REG32(PEVNTODR_REG(u8EventPort)) & 0xFFFFUL);
+}
+
+/**
+ * @brief Set specified Event port output data port pins
+ * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral
+ * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index
+ * @retval None
+ */
+void EP_SetPins(uint8_t u8EventPort, uint16_t u16EventPin)
+{
+ DDL_ASSERT(IS_EVENT_PORT(u8EventPort));
+ DDL_ASSERT(IS_EVENT_PIN(u16EventPin));
+
+ SET_REG32_BIT(PEVNTODR_REG(u8EventPort), u16EventPin);
+}
+
+/**
+ * @brief Reset specified Event port output data port pins
+ * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral
+ * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index
+ * @retval None
+ */
+void EP_ResetPins(uint8_t u8EventPort, uint16_t u16EventPin)
+{
+ DDL_ASSERT(IS_EVENT_PORT(u8EventPort));
+ DDL_ASSERT(IS_EVENT_PIN(u16EventPin));
+
+ CLR_REG32_BIT(PEVNTODR_REG(u8EventPort), u16EventPin);
+}
+
+/**
+ * @brief Set specified Event port pins direction
+ * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral
+ * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index
+ * @param [in] u32Dir: Pin direction
+ * @arg EP_DIR_IN
+ * @arg EP_DIR_OUT
+ * @retval None
+ */
+void EP_SetDir(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Dir)
+{
+ DDL_ASSERT(IS_EVENT_PORT(u8EventPort));
+ DDL_ASSERT(IS_EVENT_PIN(u16EventPin));
+ DDL_ASSERT(IS_EP_DIR(u32Dir));
+
+ if (EP_DIR_OUT == u32Dir) {
+ SET_REG32_BIT(PEVNTDIR_REG(u8EventPort), u16EventPin);
+ } else {
+ CLR_REG32_BIT(PEVNTDIR_REG(u8EventPort), u16EventPin);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_EVENT_PORT_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_fcg.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_fcg.c
new file mode 100644
index 0000000000..422e40c3cd
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_fcg.c
@@ -0,0 +1,194 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_fcg.c
+ * @brief This file provides firmware functions to manage the Function Clock
+ * Gate (FCG).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_fcg.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_FCG FCG
+ * @brief FCG Driver Library
+ * @{
+ */
+
+#if (LL_FCG_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup FCG_Local_Macros FCG Local Macros
+ * @{
+ */
+#define IS_FCG0_UNLOCKED() ((CM_PWC->FCG0PC & PWC_FCG0PC_PRT0) == PWC_FCG0PC_PRT0)
+
+/**
+ * @defgroup FCG_Check_Parameters_Validity FCG Check Parameters Validity
+ * @{
+ */
+/* Parameter validity check for peripheral in fcg0. */
+#define IS_FCG0_PERIPH(per) \
+( ((per) != 0x00UL) && \
+ (((per) | FCG_FCG0_PERIPH_MASK) == FCG_FCG0_PERIPH_MASK))
+
+/* Parameter validity check for peripheral in fcg1. */
+#define IS_FCG1_PERIPH(per) \
+( ((per) != 0x00UL) && \
+ (((per) | FCG_FCG1_PERIPH_MASK) == FCG_FCG1_PERIPH_MASK))
+
+/* Parameter validity check for peripheral in fcg2. */
+#define IS_FCG2_PERIPH(per) \
+( ((per) != 0x00UL) && \
+ (((per) | FCG_FCG2_PERIPH_MASK) == FCG_FCG2_PERIPH_MASK))
+
+/* Parameter validity check for peripheral in fcg3. */
+#define IS_FCG3_PERIPH(per) \
+( ((per) != 0x00UL) && \
+ (((per) | FCG_FCG3_PERIPH_MASK) == FCG_FCG3_PERIPH_MASK))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup FCG_Global_Functions FCG Global Functions
+ * @{
+ */
+
+/**
+ * @brief Enable or disable the FCG0 peripheral clock.
+ * @param [in] u32Fcg0Periph The peripheral in FCG0 @ref FCG_FCG0_Peripheral.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void FCG_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FCG0_PERIPH(u32Fcg0Periph));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_FCG0_UNLOCKED());
+
+ if (ENABLE == enNewState) {
+ CLR_REG32_BIT(CM_PWC->FCG0, u32Fcg0Periph);
+ } else {
+ SET_REG32_BIT(CM_PWC->FCG0, u32Fcg0Periph);
+ }
+}
+
+/**
+ * @brief Enable or disable the FCG1 peripheral clock.
+ * @param [in] u32Fcg1Periph The peripheral in FCG1 @ref FCG_FCG1_Peripheral.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void FCG_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FCG1_PERIPH(u32Fcg1Periph));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ CLR_REG32_BIT(CM_PWC->FCG1, u32Fcg1Periph);
+ } else {
+ SET_REG32_BIT(CM_PWC->FCG1, u32Fcg1Periph);
+ }
+}
+
+/**
+ * @brief Enable or disable the FCG2 peripheral clock.
+ * @param [in] u32Fcg2Periph The peripheral in FCG2 @ref FCG_FCG2_Peripheral.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void FCG_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FCG2_PERIPH(u32Fcg2Periph));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ CLR_REG32_BIT(CM_PWC->FCG2, u32Fcg2Periph);
+ } else {
+ SET_REG32_BIT(CM_PWC->FCG2, u32Fcg2Periph);
+ }
+}
+
+/**
+ * @brief Enable or disable the FCG3 peripheral clock.
+ * @param [in] u32Fcg3Periph The peripheral in FCG3 @ref FCG_FCG3_Peripheral.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void FCG_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FCG3_PERIPH(u32Fcg3Periph));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ CLR_REG32_BIT(CM_PWC->FCG3, u32Fcg3Periph);
+ } else {
+ SET_REG32_BIT(CM_PWC->FCG3, u32Fcg3Periph);
+ }
+}
+
+#endif /* LL_FCG_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_fcm.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_fcm.c
new file mode 100644
index 0000000000..94da2f356a
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_fcm.c
@@ -0,0 +1,396 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_fcm.c
+ * @brief This file provides firmware functions to manage the Frequency Clock
+ * Measurement (FCM).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2022-10-31 CDT Modify parameter check for reference clock source
+ 2023-06-30 CDT Modify API FCM_DeInit()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_fcm.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_FCM FCM
+ * @brief FCM Driver Library
+ * @{
+ */
+
+#if (LL_FCM_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup FCM_Local_Macros FCM Local Macros
+ * @{
+ */
+
+/* FCM Registers RESET Value */
+#define FCM_REG_RST_VALUE (0x00000000UL)
+
+/* FCM interrupt mask */
+#define FCM_INT_MASK (FCM_INT_OVF | FCM_INT_END | FCM_INT_ERR)
+/* FCM status flag mask */
+#define FCM_FLAG_MASK (FCM_SR_ERRF | FCM_SR_MENDF | FCM_SR_OVF)
+
+#define FCM_RMU_TIMEOUT (100UL)
+/**
+ * @defgroup FCM_Check_Parameters_Validity FCM Check Parameters Validity
+ * @{
+ */
+
+/* Parameter validity check for FCM target and reference clock source. */
+#define IS_FCM_TARGET_SRC(x) \
+( ((x) == FCM_TARGET_CLK_XTAL) || \
+ ((x) == FCM_TARGET_CLK_XTAL32) || \
+ ((x) == FCM_TARGET_CLK_HRC) || \
+ ((x) == FCM_TARGET_CLK_LRC) || \
+ ((x) == FCM_TARGET_CLK_SWDTLRC) || \
+ ((x) == FCM_TARGET_CLK_PCLK1) || \
+ ((x) == FCM_TARGET_CLK_MRC) || \
+ ((x) == FCM_TARGET_CLK_PLLHP))
+
+#define IS_FCM_REF_SRC(x) \
+( ((x) == FCM_REF_CLK_EXTCLK) || \
+ ((x) == FCM_REF_CLK_XTAL) || \
+ ((x) == FCM_REF_CLK_XTAL32) || \
+ ((x) == FCM_REF_CLK_HRC) || \
+ ((x) == FCM_REF_CLK_LRC) || \
+ ((x) == FCM_REF_CLK_SWDTLRC) || \
+ ((x) == FCM_REF_CLK_PCLK1) || \
+ ((x) == FCM_REF_CLK_MRC) || \
+ ((x) == FCM_REF_CLK_PLLHP))
+
+/* Parameter validity check for FCM target clock division. */
+#define IS_FCM_TARGET_DIV(x) \
+( ((x) == FCM_TARGET_CLK_DIV1) || \
+ ((x) == FCM_TARGET_CLK_DIV4) || \
+ ((x) == FCM_TARGET_CLK_DIV8) || \
+ ((x) == FCM_TARGET_CLK_DIV32))
+
+/* Parameter validity check for FCM external reference input function. */
+#define IS_FCM_EXT_REF_FUNC(x) \
+( ((x) == FCM_EXT_REF_OFF) || \
+ ((x) == FCM_EXT_REF_ON))
+
+/* Parameter validity check for FCM reference clock edge. */
+#define IS_FCM_REF_EDGE(x) \
+( ((x) == FCM_REF_CLK_RISING) || \
+ ((x) == FCM_REF_CLK_FALLING) || \
+ ((x) == FCM_REF_CLK_BOTH))
+
+/* Parameter validity check for FCM digital filter function. */
+#define IS_FCM_DIG_FILTER(x) \
+( ((x) == FCM_DIG_FILTER_OFF) || \
+ ((x) == FCM_DIG_FILTER_DIV1) || \
+ ((x) == FCM_DIG_FILTER_DIV4) || \
+ ((x) == FCM_DIG_FILTER_DIV16))
+
+/* Parameter validity check for FCM reference clock division. */
+#define IS_FCM_REF_DIV(x) \
+( ((x) == FCM_REF_CLK_DIV32) || \
+ ((x) == FCM_REF_CLK_DIV128) || \
+ ((x) == FCM_REF_CLK_DIV1024) || \
+ ((x) == FCM_REF_CLK_DIV8192))
+
+/* Parameter validity check for FCM exception type function. */
+#define IS_FCM_EXP_TYPE(x) \
+( ((x) == FCM_EXP_TYPE_INT) || \
+ ((x) == FCM_EXP_TYPE_RST))
+
+/* Parameter validity check for FCM interrupt. */
+#define IS_FCM_INT(x) (((x) | FCM_INT_MASK) == FCM_INT_MASK)
+
+/* Parameter validity check for FCM flag state. */
+#define IS_FCM_FLAG(x) \
+( ((x) != 0x00UL) && \
+ (((x) | FCM_FLAG_MASK) == FCM_FLAG_MASK))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup FCM_Global_Functions FCM Global Functions
+ * @{
+ */
+
+/**
+ * @brief Initialize FCM.
+ * @param [in] pstcFcmInit Pointer to a @ref stc_fcm_init_t structure
+ * that contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: FCM initialize successful
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t FCM_Init(const stc_fcm_init_t *pstcFcmInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ /* Check if pointer is NULL */
+ if (NULL == pstcFcmInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_FCM_TARGET_SRC(pstcFcmInit->u32TargetClock));
+ DDL_ASSERT(IS_FCM_TARGET_DIV(pstcFcmInit->u32TargetClockDiv));
+ DDL_ASSERT(IS_FCM_EXT_REF_FUNC(pstcFcmInit->u32ExtRefClockEnable));
+ DDL_ASSERT(IS_FCM_REF_EDGE(pstcFcmInit->u32RefClockEdge));
+ DDL_ASSERT(IS_FCM_DIG_FILTER(pstcFcmInit->u32DigitalFilter));
+ DDL_ASSERT(IS_FCM_REF_SRC(pstcFcmInit->u32RefClock));
+ DDL_ASSERT(IS_FCM_REF_DIV(pstcFcmInit->u32RefClockDiv));
+ DDL_ASSERT(IS_FCM_EXP_TYPE(pstcFcmInit->u32ExceptionType));
+
+ WRITE_REG32(CM_FCM->LVR, pstcFcmInit->u16LowerLimit);
+ WRITE_REG32(CM_FCM->UVR, pstcFcmInit->u16UpperLimit);
+ WRITE_REG32(CM_FCM->MCCR, (pstcFcmInit->u32TargetClock | pstcFcmInit->u32TargetClockDiv));
+ WRITE_REG32(CM_FCM->RCCR, (pstcFcmInit->u32ExtRefClockEnable | pstcFcmInit->u32RefClockEdge |
+ pstcFcmInit->u32DigitalFilter | pstcFcmInit->u32RefClock |
+ pstcFcmInit->u32RefClockDiv));
+ MODIFY_REG32(CM_FCM->RIER, FCM_RIER_ERRINTRS, pstcFcmInit->u32ExceptionType);
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize FCM structure. Fill each pstcFcmInit with default value.
+ * @param [in] pstcFcmInit Pointer to a @ref stc_fcm_init_t structure
+ * that contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: FCM structure initialize successful
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t FCM_StructInit(stc_fcm_init_t *pstcFcmInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ /* Check if pointer is NULL */
+ if (NULL == pstcFcmInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* RESET FCM init structure parameters values */
+ pstcFcmInit->u16LowerLimit = 0U;
+ pstcFcmInit->u16UpperLimit = 0U;
+ pstcFcmInit->u32TargetClock = FCM_TARGET_CLK_XTAL;
+ pstcFcmInit->u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
+ pstcFcmInit->u32ExtRefClockEnable = FCM_EXT_REF_OFF;
+ pstcFcmInit->u32RefClockEdge = FCM_REF_CLK_RISING;
+ pstcFcmInit->u32DigitalFilter = FCM_DIG_FILTER_OFF;
+ pstcFcmInit->u32RefClock = FCM_REF_CLK_XTAL;
+ pstcFcmInit->u32RefClockDiv = FCM_REF_CLK_DIV32;
+ pstcFcmInit->u32ExceptionType = FCM_EXP_TYPE_INT;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief De-Initialize FCM.
+ * @param None
+ * @retval int32_t:
+ * - LL_OK: De-Initialize success.
+ * - LL_ERR_TIMEOUT: Timeout.
+ */
+int32_t FCM_DeInit(void)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t u32TimeOut = 0U;
+ /* Check FRST register protect */
+ DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1);
+
+ /* Reset FCM */
+ WRITE_REG32(bCM_RMU->FRST0_b.FCM, 0UL);
+ /* Ensure reset procedure is completed */
+ while (0UL == READ_REG32(bCM_RMU->FRST0_b.FCM)) {
+ u32TimeOut++;
+ if (u32TimeOut > FCM_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Get FCM state, get FCM overflow, complete, error flag.
+ * @param [in] u32Flag FCM flags.This parameter can be one or any
+ * combination of the following values: @ref FCM_Flag_Sel
+ * @arg FCM_FLAG_ERR: FCM error.
+ * @arg FCM_FLAG_END: FCM measure end.
+ * @arg FCM_FLAG_OVF: FCM overflow.
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t FCM_GetStatus(uint32_t u32Flag)
+{
+ DDL_ASSERT(IS_FCM_FLAG(u32Flag));
+
+ return ((READ_REG32_BIT(CM_FCM->SR, u32Flag) != 0UL) ? SET : RESET);
+}
+
+/**
+ * @brief Clear FCM state, Clear FCM overflow, complete, error flag.
+ * @param [in] u32Flag FCM flags.This parameter can be one or any
+ * combination of the following values: @ref FCM_Flag_Sel
+ * @arg FCM_FLAG_ERR: FCM error.
+ * @arg FCM_FLAG_END: FCM measure end.
+ * @arg FCM_FLAG_OVF: FCM overflow.
+ * @retval None.
+ */
+void FCM_ClearStatus(uint32_t u32Flag)
+{
+ DDL_ASSERT(IS_FCM_FLAG(u32Flag));
+
+ SET_REG32_BIT(CM_FCM->CLR, u32Flag);
+}
+
+/**
+ * @brief Get FCM counter value.
+ * @param None
+ * @retval FCM counter value.
+ */
+uint16_t FCM_GetCountValue(void)
+{
+ return (uint16_t)(READ_REG32(CM_FCM->CNTR) & 0xFFFFU);
+}
+
+/**
+ * @brief FCM target clock type and division config.
+ * @param [in] u32ClockSrc Target clock type. @ref FCM_Target_Clock_Src
+ * @param [in] u32Div Target clock division. @ref FCM_Target_Clock_Div
+ * @arg FCM_TARGET_CLK_DIV1
+ * @arg FCM_TARGET_CLK_DIV4
+ * @arg FCM_TARGET_CLK_DIV8
+ * @arg FCM_TARGET_CLK_DIV32
+ * @retval None.
+ */
+void FCM_SetTargetClock(uint32_t u32ClockSrc, uint32_t u32Div)
+{
+ DDL_ASSERT(IS_FCM_TARGET_SRC(u32ClockSrc));
+ DDL_ASSERT(IS_FCM_TARGET_DIV(u32Div));
+ WRITE_REG32(CM_FCM->MCCR, (u32ClockSrc | u32Div));
+}
+
+/**
+ * @brief FCM reference clock type and division config.
+ * @param [in] u32ClockSrc Reference clock type. @ref FCM_Ref_Clock_Src
+ * @param [in] u32Div Reference clock division. @ref FCM_Ref_Clock_Div
+ * @arg FCM_REF_CLK_DIV32
+ * @arg FCM_REF_CLK_DIV128
+ * @arg FCM_REF_CLK_DIV1024
+ * @arg FCM_REF_CLK_DIV8192
+ * @retval None.
+ */
+void FCM_SetRefClock(uint32_t u32ClockSrc, uint32_t u32Div)
+{
+ DDL_ASSERT(IS_FCM_REF_SRC(u32ClockSrc));
+ DDL_ASSERT(IS_FCM_REF_DIV(u32Div));
+ MODIFY_REG32(CM_FCM->RCCR, (FCM_RCCR_INEXS | FCM_RCCR_RCKS | FCM_RCCR_RDIVS), (u32ClockSrc | u32Div));
+}
+
+/**
+ * @brief Enable or disable the FCM reset
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void FCM_ResetCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ WRITE_REG32(bCM_FCM->RIER_b.ERRE, enNewState);
+}
+
+/**
+ * @brief Enable or disable the FCM interrupt
+ * @param [in] u32IntType The FCM interrupt type. This parameter can be
+ * one or any combination @ref FCM_Int_Type
+ * @arg FCM_INT_OVF: FCM overflow interrupt
+ * @arg FCM_INT_END: FCM calculate end interrupt
+ * @arg FCM_INT_ERR: FCM frequency abnormal interrupt
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void FCM_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FCM_INT(u32IntType));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(CM_FCM->RIER, u32IntType);
+ } else {
+ CLR_REG32_BIT(CM_FCM->RIER, u32IntType);
+ }
+}
+
+/**
+ * @brief FCM function config.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None.
+ */
+void FCM_Cmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ WRITE_REG32(bCM_FCM->STR_b.START, enNewState);
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_FCM_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_fmac.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_fmac.c
new file mode 100644
index 0000000000..757d59d36b
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_fmac.c
@@ -0,0 +1,372 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_fmac.c
+ * @brief This file provides firmware functions to manage the Filter Math
+ * Accelerate (FMAC).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Modify API FMAC_DeInit()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_fmac.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_FMAC FMAC
+ * @brief FMAC Driver Library
+ * @{
+ */
+
+#if (LL_FMAC_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup FMAC_Local_Macros FMAC Local Macros
+ * @{
+ */
+#define FMAC_RMU_TIMEOUT (100U)
+
+/**
+ * @defgroup FMAC_Check_Parameters_Validity FMAC Check Parameters Validity
+ * @{
+ */
+#define IS_FMAC_FIR_SHIFT(x) ((x) <= FMAC_FIR_SHIFT_21BIT)
+
+#define IS_FMAC_FIR_STAGE(x) ((x) <= FMAC_FIR_STAGE_16)
+
+#define IS_FMAC_INT_FUNC(x) \
+( ((x) == FMAC_INT_ENABLE) || \
+ ((x) == FMAC_INT_DISABLE))
+
+#define IS_VALID_UNIT(x) \
+( ((x) == CM_FMAC1) || \
+ ((x) == CM_FMAC2) || \
+ ((x) == CM_FMAC3) || \
+ ((x) == CM_FMAC4))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup FMAC_Global_Functions FMAC Global Functions
+ * @{
+ */
+
+/**
+ * @brief FMAC peripheral initialization structure clear
+ * @param [in] pstcFmacInit FMAC function structure
+ * @arg See the structure definition for @ref stc_fmac_init_t
+ * @retval int32_t:
+ * - LL_OK: Success
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t FMAC_StructInit(stc_fmac_init_t *pstcFmacInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (pstcFmacInit != NULL) {
+ pstcFmacInit->u32Stage = FMAC_FIR_STAGE_0;
+ pstcFmacInit->u32Shift = FMAC_FIR_SHIFT_0BIT;
+ pstcFmacInit->pi16Factor = NULL;
+ pstcFmacInit->u32IntCmd = FMAC_INT_DISABLE;
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief De-Initialize FMAC function
+ * @param [in] FMACx Pointer to FMAC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_FMAC1: FMAC unit 1 instance register base
+ * @arg CM_FMAC2: FMAC unit 2 instance register base
+ * @arg CM_FMAC3: FMAC unit 3 instance register base
+ * @arg CM_FMAC4: FMAC unit 4 instance register base
+ * @retval int32_t:
+ * - LL_OK: Reset success.
+ * - LL_ERR_TIMEOUT: Reset time out.
+ */
+int32_t FMAC_DeInit(CM_FMAC_TypeDef *FMACx)
+{
+ int32_t i32Ret = LL_OK;
+ uint32_t i;
+ __IO uint8_t u8TimeOut = 0U;
+ __IO uint32_t *bCM_RMU_FRST1_FMACx = NULL;
+ const uint32_t au32FMACx[] = {CM_FMAC1_BASE, CM_FMAC2_BASE, CM_FMAC3_BASE, CM_FMAC4_BASE};
+
+ DDL_ASSERT(IS_VALID_UNIT(FMACx));
+ DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1);
+
+ for (i = 0U; i < ARRAY_SZ(au32FMACx); i++) {
+ if ((uint32_t)FMACx == au32FMACx[i]) {
+ bCM_RMU_FRST1_FMACx = (uint32_t *)((uint32_t)&bCM_RMU->FRST1_b.FMAC1 + (i << 2UL));
+ break;
+ }
+ }
+ /* Reset FMAC */
+ WRITE_REG32(*bCM_RMU_FRST1_FMACx, 0UL);
+ /* Ensure reset procedure is completed */
+ while (READ_REG32(*bCM_RMU_FRST1_FMACx) != 1UL) {
+ u8TimeOut++;
+ if (u8TimeOut > FMAC_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief FMAC peripheral function initialize
+ * @param [in] FMACx Pointer to FMAC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_FMAC1: FMAC unit 1 instance register base
+ * @arg CM_FMAC2: FMAC unit 2 instance register base
+ * @arg CM_FMAC3: FMAC unit 3 instance register base
+ * @arg CM_FMAC4: FMAC unit 4 instance register base
+ * @param [in] pstcFmacInit FMAC function base parameter structure
+ * @arg See the structure definition for @ref stc_fmac_init_t
+ * @retval int32_t:
+ * - LL_OK: Success
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t FMAC_Init(CM_FMAC_TypeDef *FMACx, const stc_fmac_init_t *pstcFmacInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ int16_t *pi16Factor;
+ __IO uint32_t *FMAC_CORx;
+ uint32_t i;
+ if ((pstcFmacInit != NULL) && (pstcFmacInit->pi16Factor != NULL)) {
+ DDL_ASSERT(IS_VALID_UNIT(FMACx));
+ DDL_ASSERT(IS_FMAC_FIR_SHIFT(pstcFmacInit->u32Shift));
+ DDL_ASSERT(IS_FMAC_FIR_STAGE(pstcFmacInit->u32Stage));
+ DDL_ASSERT(IS_FMAC_INT_FUNC(pstcFmacInit->u32IntCmd));
+
+ pi16Factor = (pstcFmacInit->pi16Factor);
+ /* Configure filter stage and results right shift bits */
+ WRITE_REG32(FMACx->CTR, (pstcFmacInit->u32Stage | (pstcFmacInit->u32Shift << FMAC_CTR_SHIFT_POS)));
+ /* Configure interrupt command */
+ WRITE_REG32(FMACx->IER, pstcFmacInit->u32IntCmd);
+ for (i = 0U; i < pstcFmacInit->u32Stage + 1U; i++) {
+ FMAC_CORx = (__IO uint32_t *)((uint32_t)(&FMACx->COR0) + (i << 2UL));
+ WRITE_REG32(*FMAC_CORx, *pi16Factor++);
+ }
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Enable or Disable FMAC
+ * @param [in] FMACx Pointer to FMAC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_FMAC1: FMAC unit 1 instance register base
+ * @arg CM_FMAC2: FMAC unit 2 instance register base
+ * @arg CM_FMAC3: FMAC unit 3 instance register base
+ * @arg CM_FMAC4: FMAC unit 4 instance register base
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void FMAC_Cmd(CM_FMAC_TypeDef *FMACx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_UNIT(FMACx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ WRITE_REG32(FMACx->ENR, enNewState);
+}
+
+/**
+ * @brief Set Filter result shift bits.
+ * @param [in] FMACx Pointer to FMAC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_FMAC1: FMAC unit 1 instance register base
+ * @arg CM_FMAC2: FMAC unit 2 instance register base
+ * @arg CM_FMAC3: FMAC unit 3 instance register base
+ * @arg CM_FMAC4: FMAC unit 4 instance register base
+ * @param [in] u32ShiftNum Result shift times.
+ * This parameter can be one of @ref FMAC_Filter_Shift
+ * @retval None
+ */
+void FMAC_SetResultShift(CM_FMAC_TypeDef *FMACx, uint32_t u32ShiftNum)
+{
+ DDL_ASSERT(IS_VALID_UNIT(FMACx));
+ DDL_ASSERT(IS_FMAC_FIR_SHIFT(u32ShiftNum));
+ /* Set Filter result shift bits */
+ MODIFY_REG32(FMACx->CTR, FMAC_CTR_SHIFT, u32ShiftNum << FMAC_CTR_SHIFT_POS);
+}
+
+/**
+ * @brief Set filter stage and filter factor.
+ * @param [in] FMACx Pointer to FMAC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_FMAC1: FMAC unit 1 instance register base
+ * @arg CM_FMAC2: FMAC unit 2 instance register base
+ * @arg CM_FMAC3: FMAC unit 3 instance register base
+ * @arg CM_FMAC4: FMAC unit 4 instance register base
+ * @param [in] u32FilterStage FMAC filter stage.
+ * This parameter can be one of @ref FMAC_Filter_Stage
+ * @param [in] pi16Factor FMAC filter factor.
+ * This parameter can be set -32768 ~ 32767
+ * @retval None
+ */
+void FMAC_SetStageFactor(CM_FMAC_TypeDef *FMACx, uint32_t u32FilterStage, int16_t *pi16Factor)
+{
+ __IO uint32_t *FMAC_CORx;
+ uint8_t i;
+ DDL_ASSERT(IS_VALID_UNIT(FMACx));
+ DDL_ASSERT(IS_FMAC_FIR_STAGE(u32FilterStage));
+ /* FMAC Software reset */
+ CLR_REG32_BIT(FMACx->ENR, FMAC_ENR_FMACEN);
+ SET_REG32_BIT(FMACx->ENR, FMAC_ENR_FMACEN);
+ /* Set the filter stage */
+ MODIFY_REG32(FMACx->CTR, FMAC_CTR_STAGE_NUM, u32FilterStage);
+ for (i = 0U; i < (u32FilterStage + 1UL); i++) {
+ FMAC_CORx = (__IO uint32_t *)((uint32_t)(&FMACx->COR0) + ((uint32_t)i << 2UL));
+ WRITE_REG32(*FMAC_CORx, *pi16Factor++);
+ }
+}
+
+/**
+ * @brief Configure interrupt command.
+ * @param [in] FMACx Pointer to FMAC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_FMAC1: FMAC unit 1 instance register base
+ * @arg CM_FMAC2: FMAC unit 2 instance register base
+ * @arg CM_FMAC3: FMAC unit 3 instance register base
+ * @arg CM_FMAC4: FMAC unit 4 instance register base
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void FMAC_IntCmd(CM_FMAC_TypeDef *FMACx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_UNIT(FMACx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ WRITE_REG32(FMACx->IER, enNewState);
+}
+
+/**
+ * @brief Data input.
+ * @param [in] FMACx Pointer to FMAC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_FMAC1: FMAC unit 1 instance register base
+ * @arg CM_FMAC2: FMAC unit 2 instance register base
+ * @arg CM_FMAC3: FMAC unit 3 instance register base
+ * @arg CM_FMAC4: FMAC unit 4 instance register base
+ * @param [in] i16Factor Data that needs to be processed.
+ * @retval None
+ */
+void FMAC_FIRInput(CM_FMAC_TypeDef *FMACx, int16_t i16Factor)
+{
+ DDL_ASSERT(IS_VALID_UNIT(FMACx));
+ WRITE_REG32(FMACx->DTR, i16Factor);
+}
+
+/**
+ * @brief Get FMAC status.
+ * @param [in] FMACx Pointer to FMAC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_FMAC1: FMAC unit 1 instance register base
+ * @arg CM_FMAC2: FMAC unit 2 instance register base
+ * @arg CM_FMAC3: FMAC unit 3 instance register base
+ * @arg CM_FMAC4: FMAC unit 4 instance register base
+ * @retval An @ref en_flag_status_t enumeration type value.
+ * - SET Calculate complete
+ * - RESET Calculation in progress
+ */
+en_flag_status_t FMAC_GetStatus(const CM_FMAC_TypeDef *FMACx)
+{
+ DDL_ASSERT(IS_VALID_UNIT(FMACx));
+ return ((READ_REG32_BIT(FMACx->STR, FMAC_STR_READY) != 0UL) ? SET : RESET);
+}
+
+/**
+ * @brief Get calculation results.
+ * @param [in] FMACx Pointer to FMAC instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_FMAC1: FMAC unit 1 instance register base
+ * @arg CM_FMAC2: FMAC unit 2 instance register base
+ * @arg CM_FMAC3: FMAC unit 3 instance register base
+ * @arg CM_FMAC4: FMAC unit 4 instance register base
+ * @param [out] pstcResult Get result.
+ * u32ResultHigh: The high value of the result
+ * u32ResultLow: The low value of the result
+ * @retval int32_t:
+ * - LL_OK: Success
+ * - LL_ERR_INVD_PARAM: pstcResult == NULL
+ */
+int32_t FMAC_GetResult(const CM_FMAC_TypeDef *FMACx, stc_fmac_result_t *pstcResult)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ DDL_ASSERT(IS_VALID_UNIT(FMACx));
+
+ if (pstcResult != NULL) {
+ pstcResult->u32ResultHigh = READ_REG32(FMACx->RTR0);
+ pstcResult->u32ResultLow = READ_REG32(FMACx->RTR1);
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_FMAC_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
+
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_gpio.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_gpio.c
new file mode 100644
index 0000000000..9a79294835
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_gpio.c
@@ -0,0 +1,745 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_gpio.c
+ * @brief This file provides firmware functions to manage the General Purpose
+ * Input/Output(GPIO).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Modify GPIO_SetFunc()
+ Rename GPIO_ExIntCmd() as GPIO_ExtIntCmd
+ 2023-12-15 CDT Add assert for GPIO register lock status in API GPIO_AnalogCmd(), GPIO_ExtIntCmd()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_gpio.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_GPIO GPIO
+ * @brief GPIO Driver Library
+ * @{
+ */
+
+#if (LL_GPIO_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+/**
+ * @defgroup GPIO_Local_Types GPIO Local Typedefs
+ * @{
+ */
+/**
+ * @brief GPIO port pin table definition
+ */
+typedef struct {
+ uint8_t u8Port; /*!< GPIO Port Source, @ref GPIO_Port_Source for details */
+ uint16_t u16PinMask; /*!< Pin active or inactive, @ref GPIO_All_Pins_Define for details */
+} stc_gpio_port_pin_tbl_t;
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup GPIO_Local_Macros GPIO Local Macros
+ * @{
+ */
+/**
+ * @defgroup GPIO_Registers_Setting_definition GPIO Registers setting definition
+ * @{
+ */
+#define GPIO_PSPCR_RST_VALUE (0x001FU)
+#define GPIO_PCCR_RST_VALUE (0x1000U)
+#define GPIO_PIN_NUM_MAX (16U)
+#define GPIO_PORT_OFFSET (0x40UL)
+#define GPIO_PIN_OFFSET (0x04UL)
+#define GPIO_REG_OFFSET (0x10UL)
+#define GPIO_REG_TYPE uint16_t
+#define GPIO_PIDR_BASE ((uint32_t)(&CM_GPIO->PIDRA))
+#define GPIO_PODR_BASE ((uint32_t)(&CM_GPIO->PODRA))
+#define GPIO_POSR_BASE ((uint32_t)(&CM_GPIO->POSRA))
+#define GPIO_PORR_BASE ((uint32_t)(&CM_GPIO->PORRA))
+#define GPIO_POTR_BASE ((uint32_t)(&CM_GPIO->POTRA))
+#define GPIO_POER_BASE ((uint32_t)(&CM_GPIO->POERA))
+#define GPIO_PCR_BASE ((uint32_t)(&CM_GPIO->PCRA0))
+#define GPIO_PFSR_BASE ((uint32_t)(&CM_GPIO->PFSRA0))
+
+#define PIDR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_PIDR_BASE + GPIO_REG_OFFSET * (x)))
+#define PODR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_PODR_BASE + GPIO_REG_OFFSET * (x)))
+#define POSR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_POSR_BASE + GPIO_REG_OFFSET * (x)))
+#define PORR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_PORR_BASE + GPIO_REG_OFFSET * (x)))
+#define POTR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_POTR_BASE + GPIO_REG_OFFSET * (x)))
+#define POER_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_POER_BASE + GPIO_REG_OFFSET * (x)))
+#define PCR_REG(x, y) (*(__IO uint16_t *)(GPIO_PCR_BASE + (uint32_t)((x) * GPIO_PORT_OFFSET) + (y) * GPIO_PIN_OFFSET))
+#define PFSR_REG(x, y) (*(__IO uint16_t *)(GPIO_PFSR_BASE + (uint32_t)((x) * GPIO_PORT_OFFSET) + (y) * GPIO_PIN_OFFSET))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup GPIO_Check_Parameters_Validity GPIO Check Parameters Validity
+ * @{
+ */
+/*! Parameter validity check for pin state. */
+#define IS_GPIO_PIN_STATE(state) \
+( ((state) == PIN_STAT_RST) || \
+ ((state) == PIN_STAT_SET))
+
+/*! Parameter validity check for pin direction. */
+#define IS_GPIO_DIR(dir) \
+( ((dir) == PIN_DIR_IN) || \
+ ((dir) == PIN_DIR_OUT))
+
+/*! Parameter validity check for pin output type. */
+#define IS_GPIO_OUT_TYPE(type) \
+( ((type) == PIN_OUT_TYPE_CMOS) || \
+ ((type) == PIN_OUT_TYPE_NMOS))
+
+/*! Parameter validity check for pin driver capacity. */
+#define IS_GPIO_PIN_DRV(drv) \
+( ((drv) == PIN_LOW_DRV) || \
+ ((drv) == PIN_MID_DRV) || \
+ ((drv) == PIN_HIGH_DRV))
+
+/*! Parameter validity check for pin attribute. */
+#define IS_GPIO_ATTR(attr) \
+( ((attr) == PIN_ATTR_DIGITAL) || \
+ ((attr) == PIN_ATTR_ANALOG))
+
+/*! Parameter validity check for pin latch function. */
+#define IS_GPIO_LATCH(latch) \
+( ((latch) == PIN_LATCH_OFF) || \
+ ((latch) == PIN_LATCH_ON))
+
+/*! Parameter validity check for internal pull-up resistor. */
+#define IS_GPIO_PIN_PU(pu) \
+( ((pu) == PIN_PU_OFF) || \
+ ((pu) == PIN_PU_ON))
+
+/*! Parameter validity check for internal pull-down resistor. */
+#define IS_GPIO_PIN_PD(pd) \
+( ((pd) == PIN_PD_OFF) || \
+ ((pd) == PIN_PD_ON))
+
+/*! Parameter validity check for input MOS alays on. */
+#define IS_GPIO_PIN_INMOS(sw) \
+( ((sw) == PIN_IN_MOS_OFF) || \
+ ((sw) == PIN_IN_MOS_ON))
+
+/*! Parameter validity check for pin state invert. */
+#define IS_GPIO_PIN_INVERT(invert) \
+( ((invert) == PIN_INVT_OFF) || \
+ ((invert) == PIN_INVT_ON))
+
+/*! Parameter validity check for pin input type. */
+#define IS_GPIO_IN_TYPE(type) \
+( ((type) == PIN_IN_TYPE_SMT) || \
+ ((type) == PIN_IN_TYPE_CMOS))
+
+/*! Parameter validity check for external interrupt function. */
+#define IS_GPIO_EXTINT(extint) \
+( ((extint) == PIN_EXTINT_OFF) || \
+ ((extint) == PIN_EXTINT_ON))
+
+/*! Parameter validity check for pin number. */
+#define IS_GPIO_PIN(pin) \
+( ((pin) != 0U) && \
+ (((pin) & GPIO_PIN_ALL) != 0U))
+
+/*! Parameter validity check for port source. */
+#define IS_GPIO_PORT(port) \
+( ((port) == GPIO_PORT_A) || \
+ ((port) == GPIO_PORT_B) || \
+ ((port) == GPIO_PORT_C) || \
+ ((port) == GPIO_PORT_D) || \
+ ((port) == GPIO_PORT_E) || \
+ ((port) == GPIO_PORT_F))
+
+/*! Parameter validity check for pin function. */
+#define IS_GPIO_FUNC(func) \
+( ((func) <= GPIO_FUNC_26) || \
+ (((func) >= GPIO_FUNC_32) && ((func) <= GPIO_FUNC_63)))
+
+/*! Parameter validity check for debug pin definition. */
+#define IS_GPIO_DEBUG_PORT(port) \
+( ((port) != 0U) && \
+ (((port) | GPIO_PIN_DEBUG) == GPIO_PIN_DEBUG))
+
+/*! Parameter validity check for pin read wait cycle. */
+#define IS_GPIO_READ_WAIT(wait) \
+( ((wait) == GPIO_RD_WAIT0) || \
+ ((wait) == GPIO_RD_WAIT1) || \
+ ((wait) == GPIO_RD_WAIT2) || \
+ ((wait) == GPIO_RD_WAIT3) || \
+ ((wait) == GPIO_RD_WAIT4) || \
+ ((wait) == GPIO_RD_WAIT5) || \
+ ((wait) == GPIO_RD_WAIT6) || \
+ ((wait) == GPIO_RD_WAIT7))
+
+/* Check GPIO register lock status. */
+#define IS_GPIO_UNLOCK() (GPIO_PWPR_WE == (CM_GPIO->PWPR & GPIO_PWPR_WE))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+/**
+ * @defgroup GPIO_Local_Variables GPIO Local Variables
+ * @{
+ */
+static const stc_gpio_port_pin_tbl_t m_astcGpioPortPinTbl[] = {
+ {GPIO_PORT_A, GPIO_PIN_A_ALL},
+ {GPIO_PORT_B, GPIO_PIN_B_ALL},
+ {GPIO_PORT_C, GPIO_PIN_C_ALL},
+ {GPIO_PORT_D, GPIO_PIN_D_ALL},
+ {GPIO_PORT_E, GPIO_PIN_E_ALL},
+ {GPIO_PORT_F, GPIO_PIN_F_ALL},
+
+};
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup GPIO_Global_Functions GPIO Global Functions
+ * @{
+ */
+
+/**
+ * @brief Initialize GPIO.
+ * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product
+ * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product
+ * @param [in] pstcGpioInit: Pointer to a stc_gpio_init_t structure that
+ * contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: GPIO initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t GPIO_Init(uint8_t u8Port, uint16_t u16Pin, const stc_gpio_init_t *pstcGpioInit)
+{
+ uint8_t u8PinPos;
+ uint16_t u16PCRVal;
+ uint16_t u16PCRMask;
+ int32_t i32Ret = LL_OK;
+ __IO uint16_t *PCRx;
+
+ /* Check if pointer is NULL */
+ if (NULL == pstcGpioInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_GPIO_UNLOCK());
+ DDL_ASSERT(IS_GPIO_PORT(u8Port));
+ DDL_ASSERT(IS_GPIO_PIN(u16Pin));
+ DDL_ASSERT(IS_GPIO_PIN_STATE(pstcGpioInit->u16PinState));
+ DDL_ASSERT(IS_GPIO_DIR(pstcGpioInit->u16PinDir));
+ DDL_ASSERT(IS_GPIO_OUT_TYPE(pstcGpioInit->u16PinOutputType));
+ DDL_ASSERT(IS_GPIO_PIN_DRV(pstcGpioInit->u16PinDrv));
+ DDL_ASSERT(IS_GPIO_LATCH(pstcGpioInit->u16Latch));
+ DDL_ASSERT(IS_GPIO_PIN_PU(pstcGpioInit->u16PullUp));
+ DDL_ASSERT(IS_GPIO_PIN_PD(pstcGpioInit->u16PullDown));
+ DDL_ASSERT(IS_GPIO_PIN_INMOS(pstcGpioInit->u16InputMos));
+ DDL_ASSERT(IS_GPIO_PIN_INVERT(pstcGpioInit->u16Invert));
+ DDL_ASSERT(IS_GPIO_EXTINT(pstcGpioInit->u16ExtInt));
+ DDL_ASSERT(IS_GPIO_ATTR(pstcGpioInit->u16PinAttr));
+
+ for (u8PinPos = 0U; u8PinPos < GPIO_PIN_NUM_MAX; u8PinPos++) {
+ if ((u16Pin & 1U) != 0U) {
+ u16PCRVal = pstcGpioInit->u16PinState | pstcGpioInit->u16PinDir | pstcGpioInit->u16PinOutputType | \
+ pstcGpioInit->u16PinDrv | pstcGpioInit->u16PullUp | pstcGpioInit->u16Invert | \
+ pstcGpioInit->u16ExtInt | pstcGpioInit->u16Latch;
+
+ u16PCRMask = GPIO_PCR_POUT | GPIO_PCR_POUTE | GPIO_PCR_NOD | \
+ GPIO_PCR_DRV | GPIO_PCR_PUU | GPIO_PCR_INVE | \
+ GPIO_PCR_INTE | GPIO_PCR_LTE ;
+ u16PCRVal |= pstcGpioInit->u16PinAttr;
+ u16PCRMask |= GPIO_PCR_DDIS;
+ u16PCRVal |= pstcGpioInit->u16PullDown | pstcGpioInit->u16InputMos;
+ u16PCRMask |= GPIO_PCR_PUD | GPIO_PCR_PINAE;
+
+ PCRx = &PCR_REG(u8Port, u8PinPos);
+ MODIFY_REG16(*PCRx, u16PCRMask, u16PCRVal);
+ }
+ u16Pin >>= 1U;
+ if (0U == u16Pin) {
+ break;
+ }
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief De-init GPIO register to default value
+ * @param None
+ * @retval None
+ */
+void GPIO_DeInit(void)
+{
+ stc_gpio_init_t stcGpioInit;
+ uint8_t i;
+ DDL_ASSERT(IS_GPIO_UNLOCK());
+
+ (void)GPIO_StructInit(&stcGpioInit);
+
+ for (i = 0U; i < ARRAY_SZ(m_astcGpioPortPinTbl); i++) {
+ (void)GPIO_Init(m_astcGpioPortPinTbl[i].u8Port, m_astcGpioPortPinTbl[i].u16PinMask, &stcGpioInit);
+ }
+ /* GPIO global register reset */
+ WRITE_REG16(CM_GPIO->PSPCR, GPIO_PSPCR_RST_VALUE);
+ WRITE_REG16(CM_GPIO->PCCR, GPIO_PCCR_RST_VALUE);
+
+}
+
+/**
+ * @brief Initialize GPIO config structure. Fill each pstcGpioInit with default value
+ * @param [in] pstcGpioInit: Pointer to a stc_gpio_init_t structure that
+ * contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: GPIO structure initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t GPIO_StructInit(stc_gpio_init_t *pstcGpioInit)
+{
+ int32_t i32Ret = LL_OK;
+ /* Check if pointer is NULL */
+ if (NULL == pstcGpioInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Reset GPIO init structure parameters values */
+ pstcGpioInit->u16PinState = PIN_STAT_RST;
+ pstcGpioInit->u16PinDir = PIN_DIR_IN;
+ pstcGpioInit->u16PinDrv = PIN_LOW_DRV;
+ pstcGpioInit->u16PinAttr = PIN_ATTR_DIGITAL;
+ pstcGpioInit->u16PullDown = PIN_PD_OFF;
+ pstcGpioInit->u16InputMos = PIN_IN_MOS_OFF;
+ pstcGpioInit->u16Latch = PIN_LATCH_OFF;
+ pstcGpioInit->u16PullUp = PIN_PU_OFF;
+ pstcGpioInit->u16Invert = PIN_INVT_OFF;
+ pstcGpioInit->u16ExtInt = PIN_EXTINT_OFF;
+ pstcGpioInit->u16PinOutputType = PIN_OUT_TYPE_CMOS;
+ pstcGpioInit->u16PinInputType = PIN_IN_TYPE_SMT;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief GPIO debug port configure. Set debug pins to GPIO
+ * @param [in] u8DebugPort: @ref GPIO_DebugPin_Sel for each product
+ * @param [in] enNewState: An @ref en_functional_state_t enumeration value.
+ * @arg ENABLE: set to debug port (SWD/JTAG)
+ * @arg DISABLE: set to GPIO
+ * @retval None
+ */
+void GPIO_SetDebugPort(uint8_t u8DebugPort, en_functional_state_t enNewState)
+{
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_GPIO_DEBUG_PORT(u8DebugPort));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_GPIO_UNLOCK());
+
+ if (ENABLE == enNewState) {
+ SET_REG16_BIT(CM_GPIO->PSPCR, ((uint16_t)u8DebugPort & GPIO_PSPCR_SPFE));
+ } else {
+ CLR_REG16_BIT(CM_GPIO->PSPCR, ((uint16_t)u8DebugPort & GPIO_PSPCR_SPFE));
+ }
+}
+
+/**
+ * @brief Set specified Port Pin function
+ * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product
+ * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product
+ * @param [in] u16Func: GPIO_FUNC_x, x can be the suffix in @ref GPIO_Function_Sel for each product
+ * @retval None
+ */
+void GPIO_SetFunc(uint8_t u8Port, uint16_t u16Pin, uint16_t u16Func)
+{
+ uint8_t u8PinPos;
+ __IO uint16_t *PFSRx;
+
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_GPIO_PORT(u8Port));
+ DDL_ASSERT(IS_GPIO_PIN(u16Pin));
+ DDL_ASSERT(IS_GPIO_FUNC(u16Func));
+ DDL_ASSERT(IS_GPIO_UNLOCK());
+
+ for (u8PinPos = 0U; u8PinPos < GPIO_PIN_NUM_MAX; u8PinPos++) {
+ if ((u16Pin & 1U) != 0U) {
+ PFSRx = &PFSR_REG(u8Port, u8PinPos);
+ MODIFY_REG16(*PFSRx, GPIO_PFSR_FSEL, u16Func);
+ }
+ u16Pin >>= 1U;
+ if (0U == u16Pin) {
+ break;
+ }
+ }
+}
+
+/**
+ * @brief GPIO pin sub-function ENABLE.
+ * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product
+ * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product
+ * @param [in] enNewState: An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void GPIO_SubFuncCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState)
+{
+ uint8_t u8PinPos;
+ __IO uint16_t *PFSRx;
+
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_GPIO_PORT(u8Port));
+ DDL_ASSERT(IS_GPIO_PIN(u16Pin));
+ DDL_ASSERT(IS_GPIO_UNLOCK());
+
+ for (u8PinPos = 0U; u8PinPos < GPIO_PIN_NUM_MAX; u8PinPos++) {
+ if ((u16Pin & 1U) != 0U) {
+ PFSRx = &PFSR_REG(u8Port, u8PinPos);
+ if (ENABLE == enNewState) {
+ SET_REG16_BIT(*PFSRx, PIN_SUBFUNC_ENABLE);
+ } else {
+ CLR_REG16_BIT(*PFSRx, PIN_SUBFUNC_ENABLE);
+ }
+ }
+ u16Pin >>= 1U;
+ if (0U == u16Pin) {
+ break;
+ }
+ }
+}
+
+/**
+ * @brief Set the sub-function, it's a global configuration
+ * @param [in] u8Func: GPIO_FUNC_x, x can be the suffix in @ref GPIO_Function_Sel for each product
+ * @retval None
+ */
+void GPIO_SetSubFunc(uint8_t u8Func)
+{
+ DDL_ASSERT(IS_GPIO_FUNC(u8Func));
+ DDL_ASSERT(IS_GPIO_UNLOCK());
+
+ MODIFY_REG16(CM_GPIO->PCCR, GPIO_PCCR_BFSEL, u8Func);
+}
+
+/**
+ * @brief GPIO output ENABLE.
+ * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product
+ * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product
+ * @param [in] enNewState: An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void GPIO_OutputCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState)
+{
+ __IO GPIO_REG_TYPE *POERx;
+
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_GPIO_PORT(u8Port));
+ DDL_ASSERT(IS_GPIO_PIN(u16Pin));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ POERx = &POER_REG(u8Port);
+ if (ENABLE == enNewState) {
+ SET_REG_BIT(*POERx, (GPIO_REG_TYPE)u16Pin);
+ } else {
+ CLR_REG_BIT(*POERx, (GPIO_REG_TYPE)u16Pin);
+ }
+}
+
+/**
+ * @brief GPIO read wait cycle configure.
+ * @param [in] u16ReadWait: @ref GPIO_ReadCycle_Sel for each product
+ * @retval None
+ */
+void GPIO_SetReadWaitCycle(uint16_t u16ReadWait)
+{
+ DDL_ASSERT(IS_GPIO_READ_WAIT(u16ReadWait));
+ DDL_ASSERT(IS_GPIO_UNLOCK());
+
+ MODIFY_REG16(CM_GPIO->PCCR, GPIO_PCCR_RDWT, u16ReadWait);
+}
+
+/**
+ * @brief GPIO input MOS always ON configure.
+ * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product
+ * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product
+ * @param [in] enNewState: An @ref en_functional_state_t enumeration value.
+ * @arg ENABLE: set input MOS always ON
+ * @arg DISABLE: set input MOS turns on while read operation
+ * @retval None
+ */
+void GPIO_InputMOSCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState)
+{
+ __IO uint16_t *PCRx;
+ uint8_t u8PinPos;
+
+ DDL_ASSERT(IS_GPIO_PORT(u8Port));
+ DDL_ASSERT(IS_GPIO_PIN(u16Pin));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_GPIO_UNLOCK());
+
+ for (u8PinPos = 0U; u8PinPos < GPIO_PIN_NUM_MAX; u8PinPos++) {
+ if ((u16Pin & 1U) != 0U) {
+ PCRx = &PCR_REG(u8Port, u8PinPos);
+ if (ENABLE == enNewState) {
+ SET_REG16_BIT(*PCRx, GPIO_PCR_PINAE);
+ } else {
+ CLR_REG16_BIT(*PCRx, GPIO_PCR_PINAE);
+ }
+ }
+ u16Pin >>= 1U;
+ if (0U == u16Pin) {
+ break;
+ }
+ }
+}
+
+/**
+ * @brief Read specified GPIO input data port pins
+ * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product
+ * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product
+ * @retval Specified GPIO port pin input value
+ */
+en_pin_state_t GPIO_ReadInputPins(uint8_t u8Port, uint16_t u16Pin)
+{
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_GPIO_PORT(u8Port));
+ DDL_ASSERT(IS_GPIO_PIN(u16Pin));
+
+ return ((READ_REG(PIDR_REG(u8Port)) & (u16Pin)) != 0U) ? PIN_SET : PIN_RESET;
+}
+
+/**
+ * @brief Read specified GPIO input data port
+ * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product
+ * @retval Specified GPIO port input value
+ */
+uint16_t GPIO_ReadInputPort(uint8_t u8Port)
+{
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_GPIO_PORT(u8Port));
+
+ return READ_REG(PIDR_REG(u8Port));
+}
+
+/**
+ * @brief Read specified GPIO output data port pins
+ * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product
+ * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product
+ * @retval Specified GPIO port pin output value
+ */
+en_pin_state_t GPIO_ReadOutputPins(uint8_t u8Port, uint16_t u16Pin)
+{
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_GPIO_PORT(u8Port));
+ DDL_ASSERT(IS_GPIO_PIN(u16Pin));
+
+ return ((READ_REG(PODR_REG(u8Port)) & (u16Pin)) != 0U) ? PIN_SET : PIN_RESET;
+}
+
+/**
+ * @brief Read specified GPIO output data port
+ * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product
+ * @retval Specified GPIO port output value
+ */
+uint16_t GPIO_ReadOutputPort(uint8_t u8Port)
+{
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_GPIO_PORT(u8Port));
+
+ return READ_REG(PODR_REG(u8Port));
+}
+
+/**
+ * @brief Set specified GPIO output data port pins
+ * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product
+ * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product
+ * @retval None
+ */
+void GPIO_SetPins(uint8_t u8Port, uint16_t u16Pin)
+{
+ __IO GPIO_REG_TYPE *POSRx;
+
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_GPIO_PORT(u8Port));
+ DDL_ASSERT(IS_GPIO_PIN(u16Pin));
+
+ POSRx = &POSR_REG(u8Port);
+ SET_REG_BIT(*POSRx, (GPIO_REG_TYPE)u16Pin);
+}
+
+/**
+ * @brief Reset specified GPIO output data port pins
+ * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product
+ * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product
+ * @retval None
+ */
+void GPIO_ResetPins(uint8_t u8Port, uint16_t u16Pin)
+{
+ __IO GPIO_REG_TYPE *PORRx;
+
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_GPIO_PORT(u8Port));
+ DDL_ASSERT(IS_GPIO_PIN(u16Pin));
+
+ PORRx = &PORR_REG(u8Port);
+ SET_REG_BIT(*PORRx, (GPIO_REG_TYPE)u16Pin);
+}
+
+/**
+ * @brief Write specified GPIO data port
+ * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product
+ * @param [in] u16PortVal: Pin output value
+ * @retval None
+ */
+void GPIO_WritePort(uint8_t u8Port, uint16_t u16PortVal)
+{
+ __IO GPIO_REG_TYPE *PODRx;
+
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_GPIO_PORT(u8Port));
+
+ PODRx = &PODR_REG(u8Port);
+ WRITE_REG(*PODRx, (GPIO_REG_TYPE)u16PortVal);
+}
+
+/**
+ * @brief Toggle specified GPIO output data port pin
+ * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product
+ * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product
+ * @retval None
+ */
+void GPIO_TogglePins(uint8_t u8Port, uint16_t u16Pin)
+{
+ __IO GPIO_REG_TYPE *POTRx;
+
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_GPIO_PORT(u8Port));
+ DDL_ASSERT(IS_GPIO_PIN(u16Pin));
+
+ POTRx = &POTR_REG(u8Port);
+ SET_REG_BIT(*POTRx, (GPIO_REG_TYPE)u16Pin);
+}
+
+/**
+ * @brief GPIO Analog command.
+ * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product
+ * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product
+ * @param [in] enNewState: An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void GPIO_AnalogCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState)
+{
+ __IO uint16_t *PCRx;
+ uint8_t u8PinPos;
+
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_GPIO_UNLOCK());
+ DDL_ASSERT(IS_GPIO_PORT(u8Port));
+ DDL_ASSERT(IS_GPIO_PIN(u16Pin));
+
+ for (u8PinPos = 0U; u8PinPos < GPIO_PIN_NUM_MAX; u8PinPos++) {
+ if ((u16Pin & 1U) != 0U) {
+ PCRx = &PCR_REG(u8Port, u8PinPos);
+ if (ENABLE == enNewState) {
+ SET_REG16_BIT(*PCRx, GPIO_PCR_DDIS);
+ } else {
+ CLR_REG16_BIT(*PCRx, GPIO_PCR_DDIS);
+ }
+ }
+ u16Pin >>= 1U;
+ if (0U == u16Pin) {
+ break;
+ }
+ }
+}
+
+/**
+ * @brief GPIO external interrupt command.
+ * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product
+ * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product
+ * @param [in] enNewState: An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void GPIO_ExtIntCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState)
+{
+ __IO uint16_t *PCRx;
+ uint8_t u8PinPos;
+
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_GPIO_UNLOCK());
+ DDL_ASSERT(IS_GPIO_PORT(u8Port));
+ DDL_ASSERT(IS_GPIO_PIN(u16Pin));
+
+ for (u8PinPos = 0U; u8PinPos < GPIO_PIN_NUM_MAX; u8PinPos++) {
+ if ((u16Pin & 1U) != 0U) {
+ PCRx = &PCR_REG(u8Port, u8PinPos);
+ if (ENABLE == enNewState) {
+ SET_REG16_BIT(*PCRx, GPIO_PCR_INTE);
+ } else {
+ CLR_REG16_BIT(*PCRx, GPIO_PCR_INTE);
+ }
+ }
+ u16Pin >>= 1U;
+ if (0U == u16Pin) {
+ break;
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_GPIO_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_hash.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_hash.c
new file mode 100644
index 0000000000..a4a36103fc
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_hash.c
@@ -0,0 +1,626 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_hash.c
+ * @brief This file provides firmware functions to manage the HASH.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Add HASH_DeInit function
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_hash.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_HASH HASH
+ * @brief HASH Driver Library
+ * @{
+ */
+
+#if (LL_HASH_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup HASH_Local_Macros HASH Local Macros
+ * @{
+ */
+
+/**
+ * @defgroup HASH_Miscellaneous_Macros HASH Miscellaneous Macros
+ * @{
+ */
+#define HASH_GROUP_SIZE (64U)
+#define HASH_GROUP_SIZE_WORD (HASH_GROUP_SIZE / 4U)
+#define HASH_LAST_GROUP_SIZE_MAX (56U)
+#define HASH_TIMEOUT (6000U)
+#define HASH_MSG_DIGEST_SIZE_WORD (8U)
+
+#define HASH_KEY_LONG_SIZE (64U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup HASH_Action HASH Action
+ * @{
+ */
+#define HASH_ACTION_START (HASH_CR_START)
+#define HASH_ACTION_HMAC_END (HASH_CR_HMAC_END)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup HASH_Check_Parameters_Validity HASH Check Parameters Validity
+ * @{
+ */
+#define IS_HASH_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask)))
+
+#define IS_HASH_MD(x) (((x) == HASH_MD_SHA256) || ((x) == HASH_MD_HMAC))
+
+#define IS_HASH_KEY_SIZE_MD(x) (((x) == HASH_KEY_MD_LONG_SIZE) || ((x) == HASH_KEY_MD_SHORT_SIZE))
+
+#define IS_HASH_INT(x) IS_HASH_BIT_MASK(x, HASH_INT_ALL)
+
+#define IS_HASH_FLAG(x) IS_HASH_BIT_MASK(x, HASH_FLAG_ALL)
+
+#define IS_HASH_FLAG_CLR(x) IS_HASH_BIT_MASK(x, HASH_FLAG_CLR_ALL)
+
+#define IS_HASH_MSG_GRP(x) \
+( ((x) == HASH_MSG_GRP_FIRST) || \
+ ((x) == HASH_MSG_GRP_END) || \
+ ((x) == HASH_MSG_GRP_ONLY_ONE))
+/**
+ * @}
+ */
+
+#define IS_HASH_PWC_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1)
+
+/* HASH reset timeout */
+#define HASH_RMU_TIMEOUT (100UL)
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup HASH_Local_Functions HASH Local Functions
+ * @{
+ */
+
+/**
+ * @brief Writes the input buffer in data register.
+ * @param [in] pu8Data The buffer for source data
+ * @retval None
+ */
+static void HASH_WriteData(const uint8_t *pu8Data)
+{
+ uint8_t i;
+ __IO uint32_t *regDR = &CM_HASH->DR15;
+ const uint32_t *pu32Data = (const uint32_t *)((uint32_t)pu8Data);
+
+ for (i = 0U; i < HASH_GROUP_SIZE_WORD; i++) {
+ regDR[i] = __REV(pu32Data[i]);
+ }
+}
+
+/**
+ * @brief Memory copy.
+ * @param [in] pu8Dest Pointer to a destination address.
+ * @param [in] pu8Src Pointer to a source address.
+ * @param [in] u32Size Data size.
+ * @retval None
+ */
+static void HASH_MemCopy(uint8_t *pu8Dest, const uint8_t *pu8Src, uint32_t u32Size)
+{
+ uint32_t i = 0UL;
+ while (i < u32Size) {
+ pu8Dest[i] = pu8Src[i];
+ i++;
+ }
+}
+
+/**
+ * @brief Memory set.
+ * @param [in] pu8Mem Pointer to an address.
+ * @param [in] u8Value Data value.
+ * @param [in] u32Size Data size.
+ * @retval None
+ */
+static void HASH_MemSet(uint8_t *pu8Mem, uint8_t u8Value, uint32_t u32Size)
+{
+ uint32_t i = 0UL;
+ while (i < u32Size) {
+ pu8Mem[i] = u8Value;
+ i++;
+ }
+}
+
+/**
+ * @brief Wait for the HASH to stop
+ * @param [in] u32Action HASH action. This parameter can be a value of @ref HASH_Action.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred
+ * - LL_ERR_TIMEOUT: Works timeout
+ */
+static int32_t HASH_Wait(uint32_t u32Action)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t u32TimeCount = 0UL;
+
+ /* Wait for the HASH to stop */
+ while (READ_REG32_BIT(CM_HASH->CR, u32Action) != 0UL) {
+ if (u32TimeCount++ > HASH_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief HASH Filling data
+ * @param [in] pu8Data The source data buffer
+ * @param [in] u32DataSize Length of the input buffer in bytes
+ * @retval int32_t:
+ * - LL_OK: No errors occurred
+ * - LL_ERR_TIMEOUT: Works timeout
+ */
+static int32_t HASH_DoCalc(const uint8_t *pu8Data, uint32_t u32DataSize)
+{
+ uint8_t u8FillBuffer[HASH_GROUP_SIZE];
+ uint32_t u32BitLenHigh;
+ uint32_t u32BitLenLow;
+ uint32_t u32Index = 0U;
+ uint8_t u8FirstGroup = 1U;
+ uint8_t u8HashEnd = 0U;
+ uint8_t u8DataEndMark = 0U;
+ uint8_t u8LastGroup = 0U;
+ int32_t i32Ret;
+
+ u32BitLenHigh = (u32DataSize >> 29U) & 0x7U;
+ u32BitLenLow = (u32DataSize << 3U);
+
+ /* Stop hash calculating. */
+ i32Ret = HASH_Wait(HASH_ACTION_START);
+
+ while ((i32Ret == LL_OK) && (u8HashEnd == 0U)) {
+ if (u32DataSize >= HASH_GROUP_SIZE) {
+ HASH_WriteData(&pu8Data[u32Index]);
+ u32DataSize -= HASH_GROUP_SIZE;
+ u32Index += HASH_GROUP_SIZE;
+ } else if (u32DataSize >= HASH_LAST_GROUP_SIZE_MAX) {
+ HASH_MemSet(u8FillBuffer, 0, HASH_GROUP_SIZE);
+ HASH_MemCopy(u8FillBuffer, &pu8Data[u32Index], u32DataSize);
+ u8FillBuffer[u32DataSize] = 0x80U;
+ u8DataEndMark = 1U;
+ HASH_WriteData(u8FillBuffer);
+ u32DataSize = 0U;
+ } else {
+ u8HashEnd = 1U;
+ }
+
+ if (u8HashEnd != 0U) {
+ HASH_MemSet(u8FillBuffer, 0, HASH_GROUP_SIZE);
+ if (u32DataSize > 0U) {
+ HASH_MemCopy(u8FillBuffer, &pu8Data[u32Index], u32DataSize);
+ }
+ if (u8DataEndMark == 0U) {
+ u8FillBuffer[u32DataSize] = 0x80U;
+ }
+ u8FillBuffer[63U] = (uint8_t)(u32BitLenLow);
+ u8FillBuffer[62U] = (uint8_t)(u32BitLenLow >> 8U);
+ u8FillBuffer[61U] = (uint8_t)(u32BitLenLow >> 16U);
+ u8FillBuffer[60U] = (uint8_t)(u32BitLenLow >> 24U);
+ u8FillBuffer[59U] = (uint8_t)(u32BitLenHigh);
+ u8FillBuffer[58U] = (uint8_t)(u32BitLenHigh >> 8U);
+ u8FillBuffer[57U] = (uint8_t)(u32BitLenHigh >> 16U);
+ u8FillBuffer[56U] = (uint8_t)(u32BitLenHigh >> 24U);
+ HASH_WriteData(u8FillBuffer);
+ u8LastGroup = 1U;
+ }
+
+ /* First group and last group check */
+ /* check if first group */
+ if (u8FirstGroup != 0U) {
+ u8FirstGroup = 0U;
+ /* Set first group. */
+ WRITE_REG32(bCM_HASH->CR_b.FST_GRP, 1U);
+ }
+ /* check if last group */
+ if (u8LastGroup != 0U) {
+ u8LastGroup = 0U;
+ /* Set last group. */
+ WRITE_REG32(bCM_HASH->CR_b.KMSG_END, 1U);
+ }
+
+ /* Start hash calculating. */
+ WRITE_REG32(bCM_HASH->CR_b.START, 1U);
+ i32Ret = HASH_Wait(HASH_ACTION_START);
+ }
+ /* Stop hash calculating. */
+ WRITE_REG32(bCM_HASH->CR_b.START, 0U);
+
+ return i32Ret;
+}
+
+/**
+ * @brief Read message digest.
+ * @param [out] pu8MsgDigest Buffer for message digest.
+ * @retval None
+ */
+static void HASH_ReadMsgDigest(uint8_t *pu8MsgDigest)
+{
+ uint8_t i;
+ __IO uint32_t *regHR = &CM_HASH->HR7;
+ uint32_t *pu32MsgDigest = (uint32_t *)((uint32_t)pu8MsgDigest);
+
+ for (i = 0U; i < HASH_MSG_DIGEST_SIZE_WORD; i++) {
+ pu32MsgDigest[i] = __REV(regHR[i]);
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup HASH_Global_Functions HASH Global Functions
+ * @{
+ */
+
+/**
+ * @brief De-initializes HASH.
+ * @param None
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_TIMEOUT: Works timeout.
+ */
+int32_t HASH_DeInit(void)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t u32TimeOut = 0U;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_HASH_PWC_UNLOCKED());
+
+ CLR_REG32_BIT(CM_RMU->FRST0, RMU_FRST0_HASH);
+ /* Ensure reset procedure is completed */
+ while (RMU_FRST0_HASH != READ_REG32_BIT(CM_RMU->FRST0, RMU_FRST0_HASH)) {
+ u32TimeOut++;
+ if (u32TimeOut > HASH_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief HASH calculate.
+ * @param [in] pu8SrcData Pointer to the source data buffer.
+ * @param [in] u32SrcDataSize Length of the source data buffer in bytes.
+ * @param [out] pu8MsgDigest Buffer of the digest. The size must be 32 bytes.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_INVD_PARAM: Parameter error.
+ * - LL_ERR_TIMEOUT: Works timeout.
+ */
+int32_t HASH_Calculate(const uint8_t *pu8SrcData, uint32_t u32SrcDataSize, uint8_t *pu8MsgDigest)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if ((pu8SrcData != NULL) && (u32SrcDataSize != 0UL) && (pu8MsgDigest != NULL)) {
+ /* Set HASH mode */
+ (void)HASH_SetMode(HASH_MD_SHA256);
+ i32Ret = HASH_DoCalc(pu8SrcData, u32SrcDataSize);
+ if (i32Ret == LL_OK) {
+ /* Get the message digest result */
+ HASH_ReadMsgDigest(pu8MsgDigest);
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief HMAC calculate.
+ * @param [in] pu8SrcData Pointer to the source data buffer.
+ * @param [in] u32SrcDataSize Length of the source data buffer in bytes.
+ * @param [in] pu8Key Buffer of the secret key.
+ * @param [in] u32KeySize Size of the input secret key in bytes.
+ * @param [out] pu8MsgDigest Buffer of the digest data buffer. The size must be 32 bytes.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_INVD_PARAM: Parameter error.
+ * - LL_ERR_BUF_FULL: Data filling error.
+ * - LL_ERR_TIMEOUT: Works timeout.
+ */
+int32_t HASH_HMAC_Calculate(const uint8_t *pu8SrcData, uint32_t u32SrcDataSize,
+ const uint8_t *pu8Key, uint32_t u32KeySize,
+ uint8_t *pu8MsgDigest)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ uint8_t u8FillBuffer[HASH_GROUP_SIZE] = {0U};
+
+ if ((pu8SrcData != NULL) && (u32SrcDataSize != 0UL) && \
+ (pu8Key != NULL) && (u32KeySize != 0UL) && (pu8MsgDigest != NULL)) {
+ /* Set HMAC Mode */
+ (void)HASH_SetMode(HASH_MD_HMAC);
+ if (u32KeySize > HASH_KEY_LONG_SIZE) {
+ /* Key size longer than 64 bytes. */
+ WRITE_REG32(bCM_HASH->CR_b.LKEY, 1U);
+ /* Write the key to the data register */
+ i32Ret = HASH_DoCalc(pu8Key, u32KeySize);
+ } else {
+ HASH_MemCopy(u8FillBuffer, pu8Key, u32KeySize);
+ /* Key size equal to or shorter than 64 bytes. */
+ WRITE_REG32(bCM_HASH->CR_b.LKEY, 0U);
+ /* Write the key to the data register */
+ HASH_WriteData(u8FillBuffer);
+ /* Only one group. */
+ SET_REG32_BIT(CM_HASH->CR, HASH_MSG_GRP_ONLY_ONE);
+ /* Start hash calculating. */
+ WRITE_REG32(bCM_HASH->CR_b.START, 1U);
+ /* Wait for operation completion */
+ i32Ret = HASH_Wait(HASH_ACTION_START);
+ }
+ /* Clear operation completion flag */
+ WRITE_REG32(bCM_HASH->CR_b.CYC_END, 0U);
+ if (i32Ret == LL_OK) {
+ i32Ret = HASH_DoCalc(pu8SrcData, u32SrcDataSize);
+ /* Write the message to the data register */
+ if (i32Ret == LL_OK) {
+ i32Ret = HASH_Wait(HASH_ACTION_HMAC_END);
+ if (i32Ret == LL_OK) {
+ /* Clear operation completion flag */
+ CLR_REG32_BIT(CM_HASH->CR, HASH_CR_CYC_END | HASH_CR_HMAC_END);
+ /* Get the message digest result */
+ HASH_ReadMsgDigest(pu8MsgDigest);
+ }
+ }
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Enable or disable HASH interrupt.
+ * @param [in] u32HashInt Specifies the HASH interrupt to check.
+ * This parameter can be values of @ref HASH_Interrupt
+ * @arg HASH_INT_GRP: A set of data operations complete interrupt.
+ * @arg HASH_INT_ALL_CPLT: All data operations complete interrupt.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_TIMEOUT: Works timeout.
+ */
+int32_t HASH_IntCmd(uint32_t u32HashInt, en_functional_state_t enNewState)
+{
+ int32_t i32Ret;
+
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_HASH_INT(u32HashInt));
+
+ /* Wait for the HASH to stop */
+ i32Ret = HASH_Wait(HASH_ACTION_START);
+ if (i32Ret == LL_OK) {
+ if (enNewState == ENABLE) {
+ SET_REG32_BIT(CM_HASH->CR, u32HashInt);
+ } else {
+ CLR_REG32_BIT(CM_HASH->CR, u32HashInt);
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Get the status of the specified HASH flag.
+ * @param [in] u32Flag HASH status flag.
+ * This parameter can be a value of @ref HASH_Status_Flag
+ * @arg HASH_FLAG_START: Operation in progress.
+ * @arg HASH_FLAG_BUSY: Operation in progress.
+ * @arg HASH_FLAG_CYC_END: key or message operation completed.
+ * @arg HASH_FLAG_HMAC_END: HMAC operation completed.
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t HASH_GetStatus(uint32_t u32Flag)
+{
+ en_flag_status_t enStatus = RESET;
+
+ DDL_ASSERT(IS_HASH_FLAG(u32Flag));
+ if (READ_REG32_BIT(CM_HASH->CR, u32Flag) != 0UL) {
+ enStatus = SET;
+ }
+
+ return enStatus;
+}
+
+/**
+ * @brief Clear the status of the specified HASH flag.
+ * @param [in] u32Flag HASH status flag.
+ * This parameter can be a value of @ref HASH_Status_Flag
+ * @arg HASH_FLAG_CYC_END: Clear the key or message operation completed flag
+ * @arg HASH_FLAG_HMAC_END: Clear the HMAC operation completed flag
+ * @retval int32_t:
+ * - LL_OK: No errors occurred
+ * - LL_ERR_TIMEOUT: Works timeout
+ */
+int32_t HASH_ClearStatus(uint32_t u32Flag)
+{
+ int32_t i32Ret;
+
+ DDL_ASSERT(IS_HASH_FLAG_CLR(u32Flag));
+ /* Wait for the HASH to stop */
+ i32Ret = HASH_Wait(HASH_ACTION_START);
+ if (i32Ret == LL_OK) {
+ CLR_REG32_BIT(CM_HASH->CR, u32Flag);
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Specifies HASH mode: SHA256 mode or HMAC mode.
+ * @param [in] u32HashMode HASH mode selection.
+ * This parameter can be a value of @ref HASH_Mode
+ * @arg HASH_MD_SHA256: SHA256 mode
+ * @arg HASH_MD_HMAC: HMAC mode
+ * @retval int32_t:
+ * - LL_OK: No errors occurred
+ * - LL_ERR_TIMEOUT: Works timeout
+ */
+int32_t HASH_SetMode(uint32_t u32HashMode)
+{
+ int32_t i32Ret;
+
+ DDL_ASSERT(IS_HASH_MD(u32HashMode));
+ /* Wait for the HASH to stop */
+ i32Ret = HASH_Wait(HASH_ACTION_START);
+ if (i32Ret == LL_OK) {
+ MODIFY_REG32(CM_HASH->CR, HASH_CR_MODE, u32HashMode);
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set HASH key size mode.
+ * @param [in] u32SizeMode Key size mode. This parameter can be a value of @ref HASH_Key_Size_Mode
+ * @arg HASH_KEY_MD_LONG_SIZE: Key size > 64 Bytes
+ * @arg HASH_KEY_MD_SHORT_SIZE: Key size <= 64 Bytes
+ * @retval int32_t:
+ * - LL_OK: No errors occurred
+ * - LL_ERR_TIMEOUT: Works timeout
+ */
+int32_t HASH_SetKeySizeMode(uint32_t u32SizeMode)
+{
+ int32_t i32Ret;
+
+ DDL_ASSERT(IS_HASH_KEY_SIZE_MD(u32SizeMode));
+ /* Wait for the HASH to stop */
+ i32Ret = HASH_Wait(HASH_ACTION_START);
+ if (i32Ret == LL_OK) {
+ MODIFY_REG32(CM_HASH->CR, HASH_CR_LKEY, u32SizeMode);
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set message group.
+ * @param [in] u32MsgGroup First group or Last group of messages.
+ * This parameter can be a value of @ref HASH_Msg_Group
+
+ * @arg HASH_MSG_GRP_FIRST: The first group of messages or keys
+ * @arg HASH_MSG_GRP_END: The last group of messages or keys
+ * @arg HASH_MSG_GRP_ONLY_ONE: Only one set of message or key
+ * @retval int32_t:
+ * - LL_OK: No errors occurred
+ * - LL_ERR_TIMEOUT: Works timeout
+ */
+int32_t HASH_SetMsgGroup(uint32_t u32MsgGroup)
+{
+ int32_t i32Ret;
+
+ DDL_ASSERT(IS_HASH_MSG_GRP(u32MsgGroup));
+ /* Wait for the HASH to stop */
+ i32Ret = HASH_Wait(HASH_ACTION_START);
+ if (i32Ret == LL_OK) {
+ SET_REG32_BIT(CM_HASH->CR, u32MsgGroup);
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Start HASH.
+ * @param None
+ * @retval int32_t:
+ * - LL_OK: No errors occurred
+ * - LL_ERR_TIMEOUT: Works timeout
+ */
+int32_t HASH_Start(void)
+{
+ int32_t i32Ret;
+
+ /* Wait for the HASH to stop */
+ i32Ret = HASH_Wait(HASH_ACTION_START);
+ if (i32Ret == LL_OK) {
+ /* Start hash calculating. */
+ SET_REG32_BIT(CM_HASH->CR, HASH_CR_START);
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Provides the message digest result.
+ * @param [out] pu8MsgDigest Buffer for message digest.
+ * @retval None
+ */
+void HASH_GetMsgDigest(uint8_t *pu8MsgDigest)
+{
+ HASH_ReadMsgDigest(pu8MsgDigest);
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_HASH_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_i2c.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_i2c.c
new file mode 100644
index 0000000000..c5b7cdc24b
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_i2c.c
@@ -0,0 +1,1383 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_i2c.c
+ * @brief This file provides firmware functions to manage the Inter-Integrated
+ * Circuit(I2C).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Fix bug for I2C_FastAckCmd()
+ Move macro define I2C_SRC_CLK to head file
+ 2023-12-15 CDT Remove API I2C_FIFO_ClearRequestStatus() & I2C_FIFO_GetStatus
+ Modify I2C_Restart()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_i2c.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_I2C I2C
+ * @brief I2C Driver Library
+ * @{
+ */
+
+#if (LL_I2C_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup I2C_Local_Macros I2C Local Macros
+ * @{
+ */
+#define I2C_BAUDRATE_MAX (1000000UL)
+#define I2C_BAUDRATE_400K (400000UL)
+
+#define I2C_SCL_HIGHT_LOW_LVL_SUM_MAX ((float32_t)0x1FE)
+#define I2C_7BIT_MAX (0x7FUL)
+#define I2C_10BIT_MAX (0x3FFUL)
+
+/**
+ * @defgroup I2C_Check_Parameters_Validity I2C Check Parameters Validity
+ * @{
+ */
+
+#define IS_I2C_UNIT(x) \
+( ((x) == CM_I2C1) || \
+ ((x) == CM_I2C2) || \
+ ((x) == CM_I2C3))
+
+#define IS_I2C_DIG_FILTER_CLK(x) ((x) <= I2C_DIG_FILTER_CLK_DIV4)
+
+#define IS_I2C_7BIT_ADDR(x) ((x) <= I2C_7BIT_MAX)
+#define IS_I2C_10BIT_ADDR(x) ((x) <= I2C_10BIT_MAX)
+
+#define IS_I2C_SPEED(x) \
+( ((x) != 0U) && \
+ ((x) <= I2C_BAUDRATE_MAX))
+
+#define IS_I2C_FLAG(x) \
+( ((x) != 0U) && \
+ (((x) | I2C_FLAG_ALL) == I2C_FLAG_ALL))
+
+#define IS_I2C_CLR_FLAG(x) \
+( ((x) != 0U) && \
+ (((x) | I2C_FLAG_CLR_ALL) == I2C_FLAG_CLR_ALL))
+
+#define IS_I2C_INT(x) \
+( ((x) != 0U) && \
+ (((x) | I2C_INT_ALL) == I2C_INT_ALL))
+
+#define IS_I2C_SMBUS_CONFIG(x) \
+( ((x) != 0U) && \
+ (((x) | I2C_SMBUS_MATCH_ALL) == I2C_SMBUS_MATCH_ALL))
+
+#define IS_I2C_ADDR(mode, addr) \
+( ((I2C_ADDR_7BIT == (mode)) && ((addr) <= 0x7FU)) || \
+ ((I2C_ADDR_10BIT == (mode)) && ((addr) <= 0x3FFU)) || \
+ (I2C_ADDR_DISABLE == (mode)))
+
+#define IS_I2C_ADDR_NUM(x) \
+( ((x) == I2C_ADDR0) || \
+ ((x) == I2C_ADDR1))
+
+#define IS_I2C_CLK_DIV(x) \
+( (x) <= I2C_CLK_DIV128)
+
+#define IS_I2C_TRANS_DIR(x) \
+( ((x) == I2C_DIR_TX) || \
+ ((x) == I2C_DIR_RX))
+
+#define IS_I2C_ACK_CONFIG(x) \
+( ((x) == I2C_ACK) || \
+ ((x) == I2C_NACK))
+
+#define IS_I2C_FLAG_STD(x) \
+( ((x) == RESET) || \
+ ((x) == SET))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ * @defgroup I2C_Global_Functions I2C Global Functions
+ * @{
+ */
+
+/**
+ * @brief Try to wait a status of specified flags
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] u32Flag Specify the flags to check, This parameter can be any combination of the member from
+ * @ref I2C_Flag values:
+ * @param [in] enStatus Expected status @ref en_flag_status_t
+ * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register
+ * @retval int32_t
+ * - LL_OK: Success
+ * - LL_ERR_TIMEOUT: Failed
+ */
+int32_t I2C_WaitStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout)
+{
+ int32_t i32Ret = LL_ERR_TIMEOUT;
+ uint32_t u32RegStatusBit;
+
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_I2C_FLAG(u32Flag));
+ DDL_ASSERT(IS_I2C_FLAG_STD(enStatus));
+
+ for (;;) {
+ u32RegStatusBit = (READ_REG32_BIT(I2Cx->SR, u32Flag));
+ if (((enStatus == SET) && (u32Flag == u32RegStatusBit)) || ((enStatus == RESET) && (0UL == u32RegStatusBit))) {
+ i32Ret = LL_OK;
+ }
+
+ if ((LL_OK == i32Ret) || (0UL == u32Timeout)) {
+ break;
+ } else {
+ u32Timeout--;
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief I2C generate start condition
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @retval None
+ */
+void I2C_GenerateStart(CM_I2C_TypeDef *I2Cx)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ SET_REG32_BIT(I2Cx->CR1, I2C_CR1_START);
+}
+
+/**
+ * @brief I2C generate restart condition
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @retval None
+ */
+void I2C_GenerateRestart(CM_I2C_TypeDef *I2Cx)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ SET_REG32_BIT(I2Cx->CR1, I2C_CR1_RESTART);
+}
+
+/**
+ * @brief I2C generate stop condition
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @retval None
+ */
+void I2C_GenerateStop(CM_I2C_TypeDef *I2Cx)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ SET_REG32_BIT(I2Cx->CR1, I2C_CR1_STOP);
+}
+
+/**
+ * @brief Set the baudrate for I2C peripheral.
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] pstcI2cInit Pointer to I2C config structure @ref stc_i2c_init_t
+ * @arg pstcI2cInit->u32ClockDiv: Division of i2c source clock, reference as:
+ * step1: calculate div = (I2cSrcClk/Baudrate/(Imme+2*Dnfsum+SclTime)
+ * I2cSrcClk -- I2c source clock
+ * Baudrate -- baudrate of i2c
+ * SclTime -- =(SCL rising time + SCL falling time)/period of i2c clock
+ * according to i2c bus hardware parameter.
+ * Dnfsum -- 0 if digital filter off;
+ * Filter capacity if digital filter on(1 ~ 4)
+ * Imme -- An Immediate data, 516
+ * step2: chose a division item which is similar and bigger than div from @ref I2C_Clock_Division.
+ * @arg pstcI2cInit->u32Baudrate : Baudrate configuration
+ * @arg pstcI2cInit->u32SclTime : Indicate SCL pin rising and falling
+ * time, should be number of T(i2c clock period time)
+ * @param [out] pf32Error Baudrate error
+ * @retval int32_t
+ * - LL_OK: Success
+ * - LL_ERR_TIMEOUT: Failed
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t I2C_BaudrateConfig(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error)
+{
+ int32_t i32Ret = LL_OK;
+ uint32_t I2cSrcClk;
+ uint32_t I2cDivClk;
+ uint32_t SclCnt;
+ uint32_t Baudrate;
+ uint32_t Dnfsum = 0UL;
+ uint32_t Divsum = 2UL;
+ uint32_t TheoryBaudrate;
+ float32_t WidthTotal;
+ float32_t SumTotal;
+ float32_t WidthHL;
+ float32_t fErr = 0.0F;
+
+ if ((NULL == pstcI2cInit) || (NULL == pf32Error)) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Check parameters */
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_I2C_SPEED(pstcI2cInit->u32Baudrate));
+ DDL_ASSERT(IS_I2C_CLK_DIV(pstcI2cInit->u32ClockDiv));
+
+ /* Get configuration for i2c */
+ I2cSrcClk = I2C_SRC_CLK;
+ I2cDivClk = 1UL << pstcI2cInit->u32ClockDiv;
+ SclCnt = pstcI2cInit->u32SclTime;
+ Baudrate = pstcI2cInit->u32Baudrate;
+
+ /* Judge digital filter status */
+ if (0U != READ_REG32_BIT(I2Cx->FLTR, I2C_FLTR_DNFEN)) {
+ Dnfsum = (READ_REG32_BIT(I2Cx->FLTR, I2C_FLTR_DNF) >> I2C_FLTR_DNF_POS) + 1U;
+ }
+
+ /* Judge if clock divider on*/
+ if (I2C_CLK_DIV1 == pstcI2cInit->u32ClockDiv) {
+ Divsum = 3UL;
+ }
+
+ if (I2cDivClk != 0UL) { /* Judge for misra */
+ WidthTotal = (float32_t)I2cSrcClk / (float32_t)Baudrate / (float32_t)I2cDivClk;
+ SumTotal = (2.0F * (float32_t)Divsum) + (2.0F * (float32_t)Dnfsum) + (float32_t)SclCnt;
+ WidthHL = WidthTotal - SumTotal;
+
+ /* Integer for WidthTotal, rounding off */
+ if ((WidthTotal - (float32_t)((uint32_t)WidthTotal)) >= 0.5F) {
+ WidthTotal = (float32_t)((uint32_t)WidthTotal) + 1.0F;
+ } else {
+ WidthTotal = (float32_t)((uint32_t)WidthTotal);
+ }
+
+ if (WidthTotal <= SumTotal) {
+ /* Err, Should set a smaller division value for pstcI2cInit->u32ClockDiv */
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ if (WidthHL > I2C_SCL_HIGHT_LOW_LVL_SUM_MAX) {
+ /* Err, Should set a bigger division value for pstcI2cInit->u32ClockDiv */
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ TheoryBaudrate = I2cSrcClk / (uint32_t)WidthTotal / I2cDivClk;
+ fErr = ((float32_t)Baudrate - (float32_t)TheoryBaudrate) / (float32_t)TheoryBaudrate;
+ WRITE_REG32(I2Cx->CCR, \
+ (pstcI2cInit->u32ClockDiv << I2C_CCR_FREQ_POS) | \
+ (((uint32_t)WidthHL / 2U) << I2C_CCR_SLOWW_POS) | \
+ (((uint32_t)WidthHL - (((uint32_t)WidthHL) / 2U)) << I2C_CCR_SHIGHW_POS));
+ if (Baudrate > I2C_BAUDRATE_400K) {
+ SET_REG32_BIT(I2Cx->CCR, I2C_CCR_FMPLUSEN);
+ }
+ }
+ }
+ } else {
+ i32Ret = LL_ERR_INVD_PARAM;
+ }
+ }
+
+ if ((NULL != pf32Error) && (LL_OK == i32Ret)) {
+ *pf32Error = fErr;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief De-initialize I2C unit
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ */
+int32_t I2C_DeInit(CM_I2C_TypeDef *I2Cx)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ /* RESET peripheral register and internal status*/
+ CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_PE);
+ SET_REG32_BIT(I2Cx->CR1, I2C_CR1_SWRST);
+
+ return LL_OK;
+}
+
+/**
+ * @brief Initialize I2C peripheral according to the structure
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] pstcI2cInit Pointer to I2C config structure @ref stc_i2c_init_t
+ * @arg pstcI2cInit->u32ClockDiv: Division of i2c source clock, reference as:
+ * step1: calculate div = (I2cSrcClk/Baudrate/(Imme+2*Dnfsum+SclTime)
+ * I2cSrcClk -- I2c source clock
+ * Baudrate -- baudrate of i2c
+ * SclTime -- =(SCL rising time + SCL falling time)/period of i2c clock
+ * according to i2c bus hardware parameter.
+ * Dnfsum -- 0 if digital filter off;
+ * Filter capacity if digital filter on(1 ~ 4)
+ * Imme -- An Immediate data, 516
+ * step2: chose a division item which is similar and bigger than div
+ * from @ref I2C_Clock_Division.
+ * @arg pstcI2cInit->u32Baudrate : Baudrate configuration
+ * @arg pstcI2cInit->u32SclTime : Indicate SCL pin rising and falling
+ * time, should be number of T(i2c clock period time)
+ * @param [out] pf32Error Baudrate error
+ * @retval int32_t
+ * - LL_OK: Success
+ * - LL_ERR_TIMEOUT: Failed
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t I2C_Init(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error)
+{
+ int32_t i32Ret;
+
+ if (NULL == pstcI2cInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Check parameters */
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_I2C_SPEED(pstcI2cInit->u32Baudrate));
+ DDL_ASSERT(IS_I2C_CLK_DIV(pstcI2cInit->u32ClockDiv));
+
+ /* Register and internal status reset */
+ CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_PE);
+ SET_REG32_BIT(I2Cx->CR1, I2C_CR1_SWRST);
+ SET_REG32_BIT(I2Cx->CR1, I2C_CR1_PE);
+
+ /* I2C baudrate config */
+ i32Ret = I2C_BaudrateConfig(I2Cx, pstcI2cInit, pf32Error);
+
+ /* Disable global broadcast address function */
+ CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_ENGC);
+ /* Release software reset */
+ CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_SWRST);
+ /* Disable I2C peripheral */
+ CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_PE);
+ /* Disable slave address function */
+ CLR_REG32_BIT(I2Cx->SLR0, I2C_SLR0_SLADDR0EN);
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief I2C slave address config
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] u32AddrNum I2C address 0 or address 1 @ref I2C_Address_Num
+ * @param [in] u32AddrMode Address mode configuration @ref I2C_Addr_Config
+ * @param [in] u32Addr The slave address
+ * @retval None
+ */
+void I2C_SlaveAddrConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, uint32_t u32AddrMode, uint32_t u32Addr)
+{
+ __IO uint32_t *const pu32SLRx = (__IO uint32_t *)((uint32_t)&I2Cx->SLR0 + (u32AddrNum * 4UL));
+
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_I2C_ADDR_NUM(u32AddrNum));
+ DDL_ASSERT(IS_I2C_ADDR(u32AddrMode, u32Addr));
+
+ if (I2C_ADDR_DISABLE == u32AddrMode) {
+ CLR_REG32_BIT(*pu32SLRx, I2C_SLR0_SLADDR0EN);
+ } else {
+ if (I2C_ADDR_10BIT == u32AddrMode) {
+ MODIFY_REG32(*pu32SLRx, I2C_SLR0_SLADDR0EN | I2C_SLR0_ADDRMOD0 | I2C_SLR0_SLADDR0,
+ u32AddrMode | u32Addr);
+ } else {
+ MODIFY_REG32(*pu32SLRx, I2C_SLR0_SLADDR0EN | I2C_SLR0_ADDRMOD0 | I2C_SLR0_SLADDR0,
+ u32AddrMode | (u32Addr << 1U));
+ }
+ }
+}
+
+/**
+ * @brief I2C slave address config
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] u32AddrNum I2C address 0 or address 1 @ref I2C_Address_Num
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void I2C_SlaveAddrCmd(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, en_functional_state_t enNewState)
+{
+ __IO uint32_t *const pu32SLRx = (__IO uint32_t *)((uint32_t)&I2Cx->SLR0 + (u32AddrNum * 4UL));
+ /* Check parameters */
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_I2C_ADDR_NUM(u32AddrNum));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ MODIFY_REG32(*pu32SLRx, I2C_SLR0_SLADDR0EN, (uint32_t)enNewState << I2C_SLR0_SLADDR0EN_POS);
+}
+
+/**
+ * @brief I2C slave address mask function config
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] u32AddrNum I2C address 0 or address 1 @ref I2C_Address_Num
+ * @param [in] u32AddrMode Address mode configuration @ref I2C_Addr_Config
+ * @param [in] u32MaskAddr The slave mask address
+ * @retval None
+ */
+void I2C_SlaveMaskAddrConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, uint32_t u32AddrMode, uint32_t u32MaskAddr)
+{
+ __IO uint32_t *const pu32SLRx = (__IO uint32_t *)((uint32_t)&I2Cx->SLR0 + (u32AddrNum * 4UL));
+
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_I2C_ADDR_NUM(u32AddrNum));
+ DDL_ASSERT(IS_I2C_ADDR(u32AddrMode, u32MaskAddr));
+
+ if (I2C_ADDR_10BIT == u32AddrMode) {
+ MODIFY_REG32(*pu32SLRx, I2C_SLR0_ADDRMOD0 | I2C_SLR0_MSLADDR0,
+ u32AddrMode | (u32MaskAddr << I2C_SLR0_MSLADDR0_POS));
+ } else {
+ MODIFY_REG32(*pu32SLRx, I2C_SLR0_ADDRMOD0 | I2C_SLR0_MSLADDR0,
+ u32AddrMode | (u32MaskAddr << (I2C_SLR0_MSLADDR0_POS + 1U)));
+ }
+}
+
+/**
+ * @brief I2C mask slave address function command
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] u32AddrNum I2C address 0 or address 1 @ref I2C_Address_Num
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void I2C_SlaveMaskAddrCmd(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, en_functional_state_t enNewState)
+{
+ __IO uint32_t *const pu32SLRx = (__IO uint32_t *)((uint32_t)&I2Cx->SLR0 + (u32AddrNum * 4UL));
+ /* Check parameters */
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_I2C_ADDR_NUM(u32AddrNum));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ MODIFY_REG32(*pu32SLRx, I2C_SLR0_MASKEN0, (uint32_t)enNewState << I2C_SLR0_MASKEN0_POS);
+}
+
+/**
+ * @brief I2C function command
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void I2C_Cmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ MODIFY_REG32(I2Cx->CR1, I2C_CR1_PE, (uint32_t)enNewState << I2C_CR1_PE_POS);
+}
+
+/**
+ * @brief I2C fast ACK config
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void I2C_FastAckCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ if (ENABLE == enNewState) {
+ CLR_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN);
+ } else {
+ SET_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN);
+ }
+}
+
+/**
+ * @brief I2C bus wait function command
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void I2C_BusWaitCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(I2Cx->CR4, I2C_CR4_BUSWAIT);
+ } else {
+ CLR_REG32_BIT(I2Cx->CR4, I2C_CR4_BUSWAIT);
+ }
+}
+
+/**
+ * @brief I2C SMBUS function configuration
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] u32SmbusConfig Indicate the SMBUS address match function configuration. @ref I2C_Smbus_Match_Config
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void I2C_SmbusConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32SmbusConfig, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_I2C_SMBUS_CONFIG(u32SmbusConfig));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(I2Cx->CR1, u32SmbusConfig);
+ } else {
+ CLR_REG32_BIT(I2Cx->CR1, u32SmbusConfig);
+ }
+}
+
+/**
+ * @brief I2C SMBUS function command
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void I2C_SmbusCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ MODIFY_REG32(I2Cx->CR1, I2C_CR1_SMBUS, (uint32_t)enNewState << I2C_CR1_SMBUS_POS);
+}
+
+/**
+ * @brief I2C digital filter function configuration
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] u32FilterClock Chose the digital filter clock, @ref I2C_Digital_Filter_Clock
+ * @retval None
+ */
+void I2C_DigitalFilterConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32FilterClock)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_I2C_DIG_FILTER_CLK(u32FilterClock));
+
+ MODIFY_REG32(I2Cx->FLTR, I2C_FLTR_DNF, u32FilterClock);
+}
+
+/**
+ * @brief I2C digital filter command
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void I2C_DigitalFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ MODIFY_REG32(I2Cx->FLTR, I2C_FLTR_DNFEN, (uint32_t)enNewState << I2C_FLTR_DNFEN_POS);
+}
+
+/**
+ * @brief I2C analog filter function command
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void I2C_AnalogFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ MODIFY_REG32(I2Cx->FLTR, I2C_FLTR_ANFEN, (uint32_t)enNewState << I2C_FLTR_ANFEN_POS);
+}
+
+/**
+ * @brief I2C general call command
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void I2C_GeneralCallCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ MODIFY_REG32(I2Cx->CR1, I2C_CR1_ENGC, (uint32_t)enNewState << I2C_CR1_ENGC_POS);
+}
+
+/**
+ * @brief I2C flags status get
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] u32Flag Specify the flags to check, This parameter can be any combination of the member from
+ * @ref I2C_Flag
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t I2C_GetStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_I2C_FLAG(u32Flag));
+
+ return ((0UL != READ_REG32_BIT(I2Cx->SR, u32Flag)) ? SET : RESET);
+}
+
+/**
+ * @brief Clear I2C flags
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] u32Flag Specifies the flag to clear, This parameter can be any combination of the member from
+ * @ref I2C_Flag_Clear
+ * @retval None
+ */
+void I2C_ClearStatus(CM_I2C_TypeDef *I2Cx, uint32_t u32Flag)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_I2C_CLR_FLAG(u32Flag));
+
+ WRITE_REG32(I2Cx->CLR, u32Flag);
+}
+
+/**
+ * @brief I2C FIFO function command
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void I2C_FIFO_Cmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ MODIFY_REG32(I2Cx->FSTR, I2C_FSTR_FEN, (uint32_t)enNewState << I2C_FSTR_FEN_POS);
+}
+
+/**
+ * @brief I2C Get Transfer FIFO data number
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @retval uint32_t The transfer FIFO data number
+ */
+uint32_t I2C_FIFO_GetTxDataNum(const CM_I2C_TypeDef *I2Cx)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ return ((READ_REG32_BIT(I2Cx->SR, I2C_SR_TFST) >> I2C_SR_TFST_POS));
+}
+
+/**
+ * @brief I2C get receive FIFO data status
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @retval uint32_t The FIFO data status @ref I2C_FIFO_Data_Status
+ */
+uint32_t I2C_FIFO_GetRxDataStatus(const CM_I2C_TypeDef *I2Cx)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ return ((READ_REG32_BIT(I2Cx->FSTR, I2C_FSTR_RFST) >> I2C_FSTR_RFST_POS));
+}
+
+/**
+ * @brief I2C get transfer FIFO data status
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @retval uint32_t The FIFO data status @ref I2C_FIFO_Data_Status
+ */
+uint32_t I2C_FIFO_GetTxDataStatus(const CM_I2C_TypeDef *I2Cx)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ return ((READ_REG32_BIT(I2Cx->FSTR, I2C_FSTR_TFST) >> I2C_FSTR_TFST_POS));
+}
+
+/**
+ * @brief I2C FIFO NACK reset transfer FIFO function command
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void I2C_FIFO_NackResetFIFOCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ MODIFY_REG32(I2Cx->FSTR, I2C_FSTR_NACKTFFLUSH, (uint32_t)enNewState << I2C_FSTR_NACKTFFLUSH_POS);
+}
+
+/**
+ * @brief I2C flush transfer FIFO
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @retval None
+ */
+void I2C_FIFO_TxFlush(CM_I2C_TypeDef *I2Cx)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ SET_REG32_BIT(I2Cx->FSTR, I2C_FSTR_TFFLUSH);
+ CLR_REG32_BIT(I2Cx->FSTR, I2C_FSTR_TFFLUSH);
+}
+
+/**
+ * @brief I2C flush receive FIFO
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @retval None
+ */
+void I2C_FIFO_RxFlush(CM_I2C_TypeDef *I2Cx)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ SET_REG32_BIT(I2Cx->FSTR, I2C_FSTR_RFFLUSH);
+ CLR_REG32_BIT(I2Cx->FSTR, I2C_FSTR_RFFLUSH);
+}
+
+/**
+ * @brief I2C Bus free clear function command
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void I2C_BusFreeClearCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ MODIFY_REG32(I2Cx->CR4, I2C_CR4_BUSFREECLREN, (uint32_t)enNewState << I2C_CR4_BUSFREECLREN_POS);
+}
+
+/**
+ * @brief I2C software reset function command
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void I2C_SWResetCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ MODIFY_REG32(I2Cx->CR1, I2C_CR1_SWRST, (uint32_t)enNewState << I2C_CR1_SWRST_POS);
+}
+
+/**
+ * @brief I2C interrupt command
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] u32IntType Specifies the I2C interrupts @ref I2C_Int_Flag
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void I2C_IntCmd(CM_I2C_TypeDef *I2Cx, uint32_t u32IntType, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_I2C_INT(u32IntType));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(I2Cx->CR2, u32IntType);
+ } else {
+ CLR_REG32_BIT(I2Cx->CR2, u32IntType);
+ }
+}
+
+/**
+ * @brief I2C send data
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] u8Data The data to be send
+ * @retval None
+ */
+void I2C_WriteData(CM_I2C_TypeDef *I2Cx, uint8_t u8Data)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+
+ WRITE_REG8(I2Cx->DTR, u8Data);
+}
+
+/**
+ * @brief I2C read data from register
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @retval uint8_t The value of the received data
+ */
+uint8_t I2C_ReadData(const CM_I2C_TypeDef *I2Cx)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+
+ return READ_REG8(I2Cx->DRR);
+}
+
+/**
+ * @brief I2C ACK status configuration
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] u32AckConfig I2C ACK configure. @ref I2C_Ack_Config
+ * @retval None
+ */
+void I2C_AckConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AckConfig)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_I2C_ACK_CONFIG(u32AckConfig));
+
+ MODIFY_REG32(I2Cx->CR1, I2C_CR1_ACK, u32AckConfig);
+}
+
+/**
+ * @brief I2C SCL high level timeout configuration
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] u16TimeoutH Clock timeout period for high level
+ * @retval None
+ */
+void I2C_SCLHighTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutH)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+
+ MODIFY_REG32(I2Cx->SLTR, I2C_SLTR_TOUTHIGH, (uint32_t)u16TimeoutH << I2C_SLTR_TOUTHIGH_POS);
+}
+
+/**
+ * @brief I2C SCL low level timeout configuration
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] u16TimeoutL Clock timeout period for low level
+ * @retval None
+ */
+void I2C_SCLLowTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutL)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ MODIFY_REG32(I2Cx->SLTR, I2C_SLTR_TOUTLOW, u16TimeoutL);
+}
+
+/**
+ * @brief Enable or disable I2C SCL high level timeout function
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void I2C_SCLHighTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(I2Cx->CR3, I2C_CR3_HTMOUT);
+ } else {
+ CLR_REG32_BIT(I2Cx->CR3, I2C_CR3_HTMOUT);
+ }
+}
+
+/**
+ * @brief Enable or disable I2C SCL low level timeout function
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void I2C_SCLLowTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(I2Cx->CR3, I2C_CR3_LTMOUT);
+ } else {
+ CLR_REG32_BIT(I2Cx->CR3, I2C_CR3_LTMOUT);
+ }
+}
+
+/**
+ * @brief Enable or disable I2C SCL timeout function
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void I2C_SCLTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(I2Cx->CR3, I2C_CR3_TMOUTEN);
+ } else {
+ CLR_REG32_BIT(I2Cx->CR3, I2C_CR3_TMOUTEN);
+ }
+}
+
+/**
+ * @brief I2Cx start
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register
+ * @retval int32_t
+ * - LL_OK: Success
+ * - LL_ERR_TIMEOUT: Failed
+ */
+int32_t I2C_Start(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout)
+{
+ int32_t i32Ret;
+
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+
+ i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_BUSY, RESET, u32Timeout);
+
+ if (LL_OK == i32Ret) {
+ /* generate start signal */
+ I2C_GenerateStart(I2Cx);
+ /* Judge if start success*/
+ i32Ret = I2C_WaitStatus(I2Cx, (I2C_FLAG_BUSY | I2C_FLAG_START), SET, u32Timeout);
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief I2Cx restart
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register
+ * @retval int32_t
+ * - LL_OK: Success
+ * - LL_ERR_TIMEOUT: Failed
+ */
+int32_t I2C_Restart(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout)
+{
+ int32_t i32Ret;
+
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+
+ i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_BUSY, SET, u32Timeout);
+
+ if (LL_OK == i32Ret) {
+ /* Clear start status flag */
+ I2C_ClearStatus(I2Cx, I2C_FLAG_CLR_START);
+ /* Send restart condition */
+ I2C_GenerateRestart(I2Cx);
+ /* Judge if start success*/
+ i32Ret = I2C_WaitStatus(I2Cx, (I2C_FLAG_BUSY | I2C_FLAG_START), SET, u32Timeout);
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief I2Cx send address
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] u16Addr The address to be sent
+ * @param [in] u8Dir Transfer direction, @ref I2C_Trans_Dir
+ * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register
+ * @retval int32_t
+ * - LL_OK: Success
+ * - LL_ERR_TIMEOUT: Failed
+ * - LL_ERR: NACK received
+ */
+int32_t I2C_TransAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout)
+{
+ int32_t i32Ret;
+
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_I2C_TRANS_DIR(u8Dir));
+ DDL_ASSERT(IS_I2C_7BIT_ADDR(u16Addr));
+
+ i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_EMPTY, SET, u32Timeout);
+
+ if (LL_OK == i32Ret) {
+ /* Send I2C address */
+ I2C_WriteData(I2Cx, (uint8_t)(u16Addr << 1U) | u8Dir);
+
+ if (I2C_DIR_TX == u8Dir) {
+ /* If in master transfer process, Need wait transfer end */
+ i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_CPLT, SET, u32Timeout);
+ } else {
+ /* If in master receive process, wait I2C_FLAG_TRA changed to receive */
+ i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TRA, RESET, u32Timeout);
+ }
+
+ if (i32Ret == LL_OK) {
+ if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == SET) {
+ i32Ret = LL_ERR;
+ }
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief I2Cx send 10 bit address
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] u16Addr The address to be sent
+ * @param [in] u8Dir Transfer direction @ref I2C_Trans_Dir
+ * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register
+ * @retval int32_t
+ * - LL_OK: Success
+ * - LL_ERR_TIMEOUT: Failed
+ * - LL_ERR: NACK received
+ */
+int32_t I2C_Trans10BitAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout)
+{
+ int32_t i32Ret;
+
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+ DDL_ASSERT(IS_I2C_TRANS_DIR(u8Dir));
+ DDL_ASSERT(IS_I2C_10BIT_ADDR(u16Addr));
+
+ i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_EMPTY, SET, u32Timeout);
+
+ if (LL_OK == i32Ret) {
+ /* Write 11110 + SLA(bit9:8) + W#(1bit) */
+ I2C_WriteData(I2Cx, (uint8_t)((u16Addr >> 7U) & 0x06U) | 0xF0U | I2C_DIR_TX);
+ i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_CPLT, SET, u32Timeout);
+
+ if (LL_OK == i32Ret) {
+ /* If receive ACK */
+ if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == RESET) {
+ /* Write SLA(bit7:0)*/
+ I2C_WriteData(I2Cx, (uint8_t)(u16Addr & 0xFFU));
+ i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_CPLT, SET, u32Timeout);
+
+ if (LL_OK == i32Ret) {
+ if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == SET) {
+ i32Ret = LL_ERR;
+ }
+ }
+ } else {
+ i32Ret = LL_ERR;
+ }
+ }
+ }
+
+ if ((u8Dir == I2C_DIR_RX) && (LL_OK == i32Ret)) {
+ /* Restart */
+ I2C_ClearStatus(I2Cx, I2C_FLAG_CLR_START);
+ I2C_GenerateRestart(I2Cx);
+ i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_START, SET, u32Timeout);
+
+ if (LL_OK == i32Ret) {
+ /* Write 11110 + SLA(bit9:8) + R(1bit) */
+ I2C_WriteData(I2Cx, (uint8_t)((u16Addr >> 7U) & 0x06U) | 0xF0U | I2C_DIR_RX);
+ /* If in master receive process, Need wait TRA flag */
+ i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TRA, RESET, u32Timeout);
+
+ if (LL_OK == i32Ret) {
+ /* If receive NACK */
+ if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == SET) {
+ i32Ret = LL_ERR;
+ }
+ }
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief I2Cx send data
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] au8TxData The data array to be sent
+ * @param [in] u32Size Number of data in array pau8TxData
+ * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register
+ * @retval int32_t
+ * - LL_OK: Success
+ * - LL_ERR_TIMEOUT: Failed
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t I2C_TransData(CM_I2C_TypeDef *I2Cx, uint8_t const au8TxData[], uint32_t u32Size, uint32_t u32Timeout)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t u32Count = 0UL;
+
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+
+ if (au8TxData != NULL) {
+ while ((u32Count != u32Size) && (i32Ret == LL_OK)) {
+ /* Wait tx buffer empty */
+ i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_EMPTY, SET, u32Timeout);
+
+ if (i32Ret == LL_OK) {
+ /* Send one byte data */
+ I2C_WriteData(I2Cx, au8TxData[u32Count]);
+
+ /* Wait transfer end */
+ i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_CPLT, SET, u32Timeout);
+
+ /* If receive NACK */
+ if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == SET) {
+ break;
+ }
+ u32Count++;
+ }
+ }
+ } else {
+ i32Ret = LL_ERR_INVD_PARAM;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief I2Cx receive data
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [out] au8RxData Array to hold the received data
+ * @param [in] u32Size Number of data to be received
+ * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register
+ * @retval int32_t
+ * - LL_OK: Success
+ * - LL_ERR_TIMEOUT: Failed
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t I2C_ReceiveData(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout)
+{
+ int32_t i32Ret = LL_OK;
+ uint32_t i;
+
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+
+ if (au8RxData != NULL) {
+ uint32_t u32FastAckDis = READ_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN);
+ for (i = 0UL; i < u32Size; i++) {
+ i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_RX_FULL, SET, u32Timeout);
+
+ if (0UL == u32FastAckDis) {
+ if ((u32Size >= 2UL) && (i == (u32Size - 2UL))) {
+ I2C_AckConfig(I2Cx, I2C_NACK);
+ }
+ } else {
+ if (i != (u32Size - 1UL)) {
+ I2C_AckConfig(I2Cx, I2C_ACK);
+ } else {
+ I2C_AckConfig(I2Cx, I2C_NACK);
+ }
+ }
+
+ if (i32Ret == LL_OK) {
+ /* read data from register */
+ au8RxData[i] = I2C_ReadData(I2Cx);
+ } else {
+ break;
+ }
+ }
+ I2C_AckConfig(I2Cx, I2C_ACK);
+ } else {
+ i32Ret = LL_ERR_INVD_PARAM;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief I2Cx receive data and stop(for master)
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [out] au8RxData Array to hold the received data
+ * @param [in] u32Size Number of data to be received
+ * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register
+ * @retval int32_t
+ * - LL_OK: Success
+ * - LL_ERR_TIMEOUT: Failed
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t I2C_MasterReceiveDataAndStop(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout)
+{
+ int32_t i32Ret = LL_OK;
+ uint32_t i;
+
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+
+ if (au8RxData != NULL) {
+ uint32_t u32FastAckDis = READ_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN);
+
+ for (i = 0UL; i < u32Size; i++) {
+ i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_RX_FULL, SET, u32Timeout);
+
+ if (0UL == u32FastAckDis) {
+ if ((u32Size >= 2UL) && (i == (u32Size - 2UL))) {
+ I2C_AckConfig(I2Cx, I2C_NACK);
+ }
+ } else {
+ if (i != (u32Size - 1UL)) {
+ I2C_AckConfig(I2Cx, I2C_ACK);
+ } else {
+ I2C_AckConfig(I2Cx, I2C_NACK);
+ }
+ }
+
+ if (i32Ret == LL_OK) {
+ /* Stop before read last data */
+ if (i == (u32Size - 1UL)) {
+ I2C_ClearStatus(I2Cx, I2C_FLAG_CLR_STOP);
+ I2C_GenerateStop(I2Cx);
+ }
+ /* read data from register */
+ au8RxData[i] = I2C_ReadData(I2Cx);
+
+ if (i == (u32Size - 1UL)) {
+ /* Wait stop flag after DRR read */
+ i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_STOP, SET, u32Timeout);
+ }
+ } else {
+ break;
+ }
+ }
+ I2C_AckConfig(I2Cx, I2C_ACK);
+ } else {
+ i32Ret = LL_ERR_INVD_PARAM;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief I2Cx stop
+ * @param [in] I2Cx Pointer to I2C instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_I2C or CM_I2Cx: I2C instance register base.
+ * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register
+ * @retval int32_t
+ * - LL_OK: Success
+ * - LL_ERR_TIMEOUT: Failed
+ */
+int32_t I2C_Stop(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout)
+{
+ int32_t i32Ret;
+
+ DDL_ASSERT(IS_I2C_UNIT(I2Cx));
+
+ /* Clear stop flag */
+ while ((SET == I2C_GetStatus(I2Cx, I2C_FLAG_STOP)) && (u32Timeout > 0UL)) {
+ I2C_ClearStatus(I2Cx, I2C_FLAG_CLR_STOP);
+ u32Timeout--;
+ }
+ I2C_GenerateStop(I2Cx);
+ /* Wait stop flag */
+ i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_STOP, SET, u32Timeout);
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize structure stc_i2c_init_t variable with default value.
+ * @param [out] pstcI2cInit Pointer to a stc_i2c_init_t structure variable which will be initialized.
+ * @ref stc_i2c_init_t.
+ * @retval int32_t
+ * - LL_OK: Success
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t I2C_StructInit(stc_i2c_init_t *pstcI2cInit)
+{
+ int32_t i32Ret = LL_OK;
+ if (pstcI2cInit == NULL) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ pstcI2cInit->u32Baudrate = 50000UL;
+ pstcI2cInit->u32SclTime = 0UL;
+ pstcI2cInit->u32ClockDiv = I2C_CLK_DIV1;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_I2C_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_icg.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_icg.c
new file mode 100644
index 0000000000..c79d795626
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_icg.c
@@ -0,0 +1,138 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_icg.c
+ * @brief This file provides firmware functions to manage the Initial
+ * Configuration(ICG).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_icg.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_ICG ICG
+ * @brief Initial Configuration Driver Library
+ * @{
+ */
+
+#if (LL_ICG_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup ICG_Local_Macros ICG Local Macros
+ * @{
+ */
+
+/**
+ * @brief ICG Start Address
+ */
+#define ICG_START_ADDR 0x400
+#define ICG_START_ADDR_AC6 ".ARM.__at_0x400"
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+/**
+ * @brief ICG parameters configuration
+ */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+const uint32_t u32ICGValue[] __attribute__((section(ICG_START_ADDR_AC6))) =
+#elif defined (__GNUC__) && !defined (__CC_ARM)
+const uint32_t u32ICGValue[] __attribute__((section(".icg_sec"))) =
+#elif defined (__CC_ARM)
+const uint32_t u32ICGValue[] __attribute__((at(ICG_START_ADDR))) =
+#elif defined (__ICCARM__)
+#pragma location = ICG_START_ADDR
+__root static const uint32_t u32ICGValue[] =
+#else
+#error "unsupported compiler!!"
+#endif
+{
+ /* ICG 0~1 */
+ ICG_REG_CFG0_CONST,
+ ICG_REG_CFG1_CONST,
+ /* ICG 2~4 */
+ ICG_REG_CFG2_CONST,
+ ICG_REG_CFG3_CONST,
+ ICG_REG_CFG4_CONST,
+ /* Reserved 0~3 */
+ ICG_REG_RESV_CONST,
+ ICG_REG_RESV_CONST,
+ ICG_REG_RESV_CONST,
+ ICG_REG_RESV_CONST,
+ /* Reserved 4~7 */
+ ICG_REG_RESV_CONST,
+ ICG_REG_RESV_CONST,
+ ICG_REG_RESV_CONST,
+ ICG_REG_RESV_CONST,
+ /* Reserved 8~11 */
+ ICG_REG_RESV_CONST,
+ ICG_REG_RESV_CONST,
+ ICG_REG_RESV_CONST,
+ ICG_REG_RESV_CONST,
+ /* Reserved 12~15 */
+ ICG_REG_RESV_CONST,
+ ICG_REG_RESV_CONST,
+ ICG_REG_RESV_CONST,
+ ICG_REG_RESV_CONST,
+ /* Reserved 16~18 */
+ ICG_REG_RESV_CONST,
+ ICG_REG_RESV_CONST,
+ ICG_REG_RESV_CONST,
+};
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+#endif /* LL_ICG_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_interrupts.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_interrupts.c
new file mode 100644
index 0000000000..902d2c5526
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_interrupts.c
@@ -0,0 +1,765 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_interrupts.c
+ * @brief This file provides firmware functions to manage the Interrupt Controller
+ * (INTC).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT IRQxxx_Handler add __DSB for Arm Errata 838869
+ 2023-09-30 CDT Remove space line
+ 2023-12-15 CDT Add API INTC_GetIntSrcState()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_interrupts.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_INTERRUPTS INTERRUPTS
+ * @brief INTC Driver Library
+ * @{
+ */
+
+#if (LL_INTERRUPTS_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup INTC_Local_Macros INTC Local Macros
+ * @{
+ */
+/**
+ * @brief Maximum IRQ handler number
+ */
+#define IRQ_NUM_MAX (16U)
+#define IRQn_MIN (INT000_IRQn)
+#define IRQn_MAX (INT015_IRQn)
+#define IRQn_OFFSET (0U)
+#define EXTINT_CH_NUM_MAX (16U)
+#define EIRQCFR_REG (CM_INTC->EIFCR)
+#define EIRQFR_REG (CM_INTC->EIFR)
+#define NMIENR_REG (CM_INTC->NMIER)
+#define NMICFR_REG (CM_INTC->NMIFCR)
+#define INTSEL_REG (uint32_t)(&CM_INTC->INTSEL0)
+#define INTWKEN_REG (CM_INTC->WKEN)
+#define INTSEL_RST_VALUE (0x1FFUL)
+#define INTEN_REG_MOD (32U)
+
+/**
+ * @defgroup INTC_Check_Parameters_Validity INTC Check Parameters Validity
+ * @{
+ */
+/*! Parameter validity check for wakeup source from stop mode. */
+#define IS_INTC_WKUP_SRC(src) \
+( ((src) != 0x00UL) && \
+ (((src) | INTC_WUPEN_ALL) == INTC_WUPEN_ALL))
+
+/*! Parameter validity check for event index. */
+#define IS_INTC_EVT(event) \
+( ((event) != 0x00UL) && \
+ (((event) | INTC_EVT_ALL) == INTC_EVT_ALL))
+
+/*! Parameter validity check for interrupt index. */
+#define IS_INTC_INT(it) \
+( ((it) != 0x00UL) && \
+ (((it) | INTC_INT_ALL) == INTC_INT_ALL))
+
+/*! Parameter validity check for software interrupt index. */
+#define IS_INTC_SWI(swi) \
+( ((swi) != 0x00UL) && \
+ (((swi) | SWINT_ALL) == SWINT_ALL))
+
+/*! Parameter validity check for NMI trigger source. */
+#define IS_NMI_SRC(src) \
+( ((src) != 0x00UL) && \
+ (((src) | NMI_SRC_ALL) == NMI_SRC_ALL))
+
+/*! Parameter validity check for EXTINT filter A function. */
+#define IS_EXTINT_FAE(fae) \
+( ((fae) == EXTINT_FILTER_OFF) || \
+ ((fae) == EXTINT_FILTER_ON))
+
+/*! Parameter validity check for EXTINT filter A clock division. */
+#define IS_EXTINT_FACLK(faclk) \
+( ((faclk) == EXTINT_FCLK_DIV1) || \
+ ((faclk) == EXTINT_FCLK_DIV8) || \
+ ((faclk) == EXTINT_FCLK_DIV32) || \
+ ((faclk) == EXTINT_FCLK_DIV64))
+
+/*! Parameter validity check for EXTINT filter B function. */
+#define IS_NMI_EXTINT_FBE(fbe) \
+( ((fbe) == NMI_EXTINT_FILTER_B_OFF) || \
+ ((fbe) == NMI_EXTINT_FILTER_B_ON))
+
+/*! Parameter validity check for EXTINT filter B time. */
+#define IS_NMI_EXTINT_FBTIME(fbtime) \
+( ((fbtime) == NMI_EXTINT_FCLK_B_500NS) || \
+ ((fbtime) == NMI_EXTINT_FCLK_B_1US) || \
+ ((fbtime) == NMI_EXTINT_FCLK_B_2US) || \
+ ((fbtime) == NMI_EXTINT_FCLK_B_4US))
+
+/*! Parameter validity check for EXTINT trigger edge. */
+#define IS_EXTINT_TRIG(trigger) \
+( ((trigger) == EXTINT_TRIG_LOW) || \
+ ((trigger) == EXTINT_TRIG_RISING) || \
+ ((trigger) == EXTINT_TRIG_FALLING) || \
+ ((trigger) == EXTINT_TRIG_BOTH))
+
+/*! Parameter validity check for EXTINT channel. */
+#define IS_EXTINT_CH(ch) \
+( ((ch) != 0x00UL) && \
+ (((ch) | EXTINT_CH_ALL) == EXTINT_CH_ALL))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+/**
+ * @defgroup INTC_Local_Variable INTC Local Variable
+ * @{
+ */
+static func_ptr_t m_apfnIrqHandler[IRQ_NUM_MAX] = {NULL};
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup INTC_Global_Functions INTC Global Functions
+ * @{
+ */
+/**
+ * @brief IRQ sign in function
+ * @param [in] pstcIrqSignConfig: pointer of IRQ registration structure
+ * @arg enIntSrc: can be any value @ref en_int_src_t
+ * @arg enIRQn: can be any value from IRQn_MIN ~ IRQn_MAX for different product
+ * @arg pfnCallback: Callback function
+ * @retval int32_t:
+ * - LL_OK: IRQ register successfully
+ * - LL_ERR_INVD_PARAM: IRQ No. and Peripheral Int source are not match; NULL pointer.
+ * - LL_ERR_UNINIT: Specified IRQ entry was signed before.
+ */
+int32_t INTC_IrqSignIn(const stc_irq_signin_config_t *pstcIrqSignConfig)
+{
+ __IO uint32_t *INTC_SELx;
+ int32_t i32Ret = LL_OK;
+
+ /* Check if pointer is NULL */
+ if (NULL == pstcIrqSignConfig) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ DDL_ASSERT(pstcIrqSignConfig->enIntSrc <= INT_SRC_MAX);
+ if (pstcIrqSignConfig->enIRQn > INT015_IRQn) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ }
+
+ else {
+ INTC_SELx = (__IO uint32_t *)(INTSEL_REG + (4U * (uint32_t)(pstcIrqSignConfig->enIRQn)));
+ /* for MISRAC2004-12.4 */
+ if (INTSEL_RST_VALUE == ((*INTC_SELx) & INTSEL_RST_VALUE)) {
+ WRITE_REG32(*INTC_SELx, pstcIrqSignConfig->enIntSrc);
+ m_apfnIrqHandler[pstcIrqSignConfig->enIRQn] = pstcIrqSignConfig->pfnCallback;
+ } else if ((uint32_t)(pstcIrqSignConfig->enIntSrc) == ((*INTC_SELx) & INTSEL_RST_VALUE)) {
+ m_apfnIrqHandler[pstcIrqSignConfig->enIRQn] = pstcIrqSignConfig->pfnCallback;
+ } else {
+ i32Ret = LL_ERR_UNINIT;
+ }
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief IRQ sign out function
+ * @param [in] enIRQn: can be any value from IRQn_MIN ~ IRQn_MAX for different product
+ * @retval int32_t:
+ * - LL_OK: IRQ sign out successfully
+ * - LL_ERR_INVD_PARAM: IRQ No. is out of range
+ */
+int32_t INTC_IrqSignOut(IRQn_Type enIRQn)
+{
+ __IO uint32_t *INTC_SELx;
+ int32_t i32Ret = LL_OK;
+
+ if ((enIRQn < IRQn_MIN) || (enIRQn > IRQn_MAX)) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ INTC_SELx = (__IO uint32_t *)(INTSEL_REG + (4UL * (uint32_t)enIRQn));
+ WRITE_REG32(*INTC_SELx, INTSEL_RST_VALUE);
+ m_apfnIrqHandler[(uint8_t)enIRQn - IRQn_OFFSET] = NULL;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Stop mode wake-up source configure
+ * @param [in] u32WakeupSrc: Wake-up source, @ref INTC_Stop_Wakeup_Source_Sel for details
+ * @param [in] enNewState: An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void INTC_WakeupSrcCmd(uint32_t u32WakeupSrc, en_functional_state_t enNewState)
+{
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_INTC_WKUP_SRC(u32WakeupSrc));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(INTWKEN_REG, u32WakeupSrc);
+ } else {
+ CLR_REG32_BIT(INTWKEN_REG, u32WakeupSrc);
+ }
+}
+
+/**
+ * @brief Event or Interrupt output configure
+ * @param [in] u32Event: Event index, @ref INTC_Event_Channel_Sel for details
+ * @param [in] enNewState: An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void INTC_EventCmd(uint32_t u32Event, en_functional_state_t enNewState)
+{
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_INTC_EVT(u32Event));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(CM_INTC->EVTER, u32Event);
+ } else {
+ CLR_REG32_BIT(CM_INTC->EVTER, u32Event);
+ }
+}
+
+/**
+ * @brief Interrupt function configure
+ * @param [in] u32Int: Interrupt index, @ref INT_Channel_Sel for details
+ * @param [in] enNewState: An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void INTC_IntCmd(uint32_t u32Int, en_functional_state_t enNewState)
+{
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_INTC_INT(u32Int));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(CM_INTC->IER, u32Int);
+ } else {
+ CLR_REG32_BIT(CM_INTC->IER, u32Int);
+ }
+}
+
+/**
+ * @brief Software Interrupt initialize function
+ * @param [in] u32Ch: Software Interrupt channel, @ref SWINT_Channel_Sel for details
+ * @param [in] pfnCallback: Callback function
+ * @param [in] u32Priority: Software interrupt priority
+ * @retval None
+ */
+void INTC_SWIntInit(uint32_t u32Ch, const func_ptr_t pfnCallback, uint32_t u32Priority)
+{
+ stc_irq_signin_config_t stcIrqSignConfig;
+
+ stcIrqSignConfig.enIRQn = (IRQn_Type)(__CLZ(__RBIT(u32Ch)));
+ (void)(pfnCallback);
+
+ NVIC_ClearPendingIRQ(stcIrqSignConfig.enIRQn);
+ NVIC_SetPriority(stcIrqSignConfig.enIRQn, u32Priority);
+ NVIC_EnableIRQ(stcIrqSignConfig.enIRQn);
+}
+
+/**
+ * @brief Software Interrupt function configure
+ * @param [in] u32SWInt: Software Interrupt channel, @ref SWINT_Channel_Sel for details
+ * @param [in] enNewState: An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void INTC_SWIntCmd(uint32_t u32SWInt, en_functional_state_t enNewState)
+{
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_INTC_SWI(u32SWInt));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(CM_INTC->SWIER, u32SWInt);
+ } else {
+ CLR_REG32_BIT(CM_INTC->SWIER, u32SWInt);
+ }
+}
+
+/**
+ * @brief Initialize NMI. Fill each pstcNmiInit with default value
+ * @param [in] pstcNmiInit: Pointer to a stc_nmi_init_t structure that
+ * contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: NMI structure initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t NMI_StructInit(stc_nmi_init_t *pstcNmiInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ /* Check if pointer is NULL */
+ if (NULL == pstcNmiInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Configure to default value */
+ pstcNmiInit->u32Src = 0UL;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize NMI.
+ * @param [in] pstcNmiInit: Pointer to a pstcNmiInit structure that
+ * contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: NMI initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t NMI_Init(const stc_nmi_init_t *pstcNmiInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ /* Check if pointer is NULL */
+ if (NULL == pstcNmiInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_NMI_SRC(pstcNmiInit->u32Src));
+ /* Clear all NMI trigger source before set */
+ WRITE_REG32(NMICFR_REG, NMI_SRC_ALL);
+
+ /* NMI trigger source configure */
+ WRITE_REG32(NMIENR_REG, pstcNmiInit->u32Src);
+
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Get NMI trigger source
+ * @param [in] u32Src: NMI trigger source, @ref NMI_TriggerSrc_Sel for details
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t NMI_GetNmiStatus(uint32_t u32Src)
+{
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_NMI_SRC(u32Src));
+
+ return (((READ_REG32(CM_INTC->NMIFR) & u32Src)) != 0UL) ? SET : RESET;
+}
+
+/**
+ * @brief Set NMI trigger source
+ * @param [in] u32Src: NMI trigger source, @ref NMI_TriggerSrc_Sel for details
+ * @param [in] enNewState: An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void NMI_NmiSrcCmd(uint32_t u32Src, en_functional_state_t enNewState)
+{
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_NMI_SRC(u32Src));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(NMIENR_REG, u32Src);
+ } else {
+ CLR_REG32_BIT(NMIENR_REG, u32Src);
+ }
+}
+
+/**
+ * @brief Clear specified NMI trigger source
+ * @param [in] u32Src: NMI trigger source, @ref NMI_TriggerSrc_Sel for diff. MCU in details
+ * @retval None
+ */
+void NMI_ClearNmiStatus(uint32_t u32Src)
+{
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_NMI_SRC(u32Src));
+
+ SET_REG32_BIT(NMICFR_REG, u32Src);
+}
+
+/**
+ * @brief Initialize External interrupt.
+ * @param [in] u32Ch: ExtInt channel.
+ * @param [in] pstcExtIntInit: Pointer to a stc_extint_init_t structure that
+ * contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: EXTINT initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t EXTINT_Init(uint32_t u32Ch, const stc_extint_init_t *pstcExtIntInit)
+{
+ uint8_t u8ExtIntPos;
+ int32_t i32Ret = LL_OK;
+ uint32_t EIRQCRVal;
+ __IO uint32_t *EIRQCRx;
+
+ /* Check if pointer is NULL */
+ if (NULL == pstcExtIntInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_EXTINT_CH(u32Ch));
+ DDL_ASSERT(IS_EXTINT_FAE(pstcExtIntInit->u32Filter));
+ DDL_ASSERT(IS_EXTINT_FACLK(pstcExtIntInit->u32FilterClock));
+ DDL_ASSERT(IS_EXTINT_TRIG(pstcExtIntInit->u32Edge));
+ DDL_ASSERT(IS_NMI_EXTINT_FBE(pstcExtIntInit->u32FilterB));
+ DDL_ASSERT(IS_NMI_EXTINT_FBTIME(pstcExtIntInit->u32FilterBClock));
+ for (u8ExtIntPos = 0U; u8ExtIntPos < EXTINT_CH_NUM_MAX; u8ExtIntPos++) {
+ if (0UL != (u32Ch & (1UL << u8ExtIntPos))) {
+ EIRQCRVal = pstcExtIntInit->u32Filter | pstcExtIntInit->u32FilterClock | \
+ pstcExtIntInit->u32Edge;
+ EIRQCRVal |= (pstcExtIntInit->u32FilterB | pstcExtIntInit->u32FilterBClock);
+ EIRQCRx = (__IO uint32_t *)((uint32_t)&CM_INTC->EIRQCR0 + 4UL * u8ExtIntPos);
+ WRITE_REG32(*EIRQCRx, EIRQCRVal);
+ }
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize ExtInt. Fill each pstcExtIntInit with default value
+ * @param [in] pstcExtIntInit: Pointer to a stc_extint_init_t structure
+ * that contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: EXTINT structure initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t EXTINT_StructInit(stc_extint_init_t *pstcExtIntInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ /* Check if pointer is NULL */
+ if (NULL == pstcExtIntInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Configure to default value */
+ pstcExtIntInit->u32Filter = EXTINT_FILTER_OFF;
+ pstcExtIntInit->u32FilterClock = EXTINT_FCLK_DIV1;
+ pstcExtIntInit->u32Edge = EXTINT_TRIG_FALLING;
+ pstcExtIntInit->u32FilterB = NMI_EXTINT_FILTER_B_OFF;
+ pstcExtIntInit->u32FilterBClock = NMI_EXTINT_FCLK_B_500NS;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Clear specified External interrupt trigger source
+ * @param [in] u32ExtIntCh: External interrupt channel, @ref EXTINT_Channel_Sel for details
+ * @retval None
+ */
+void EXTINT_ClearExtIntStatus(uint32_t u32ExtIntCh)
+{
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_EXTINT_CH(u32ExtIntCh));
+
+ SET_REG32_BIT(EIRQCFR_REG, u32ExtIntCh);
+}
+
+/**
+ * @brief Get specified External interrupt trigger source
+ * @param [in] u32ExtIntCh: External interrupt channel, @ref EXTINT_Channel_Sel for details
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t EXTINT_GetExtIntStatus(uint32_t u32ExtIntCh)
+{
+ /* Parameter validity checking */
+ DDL_ASSERT(IS_EXTINT_CH(u32ExtIntCh));
+
+ return ((READ_REG16(EIRQFR_REG) & u32ExtIntCh) != 0U) ? SET : RESET;
+}
+
+/**
+ * @brief Interrupt source interrupt function configure
+ * @param [in] enIntSrc: Interrupt source, can be any value @ref en_int_src_t
+ * @param [in] enNewState: An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void INTC_IntSrcCmd(en_int_src_t enIntSrc, en_functional_state_t enNewState)
+{
+ __IO uint32_t *INTENx;
+
+ /* Parameter validity checking */
+ DDL_ASSERT(enIntSrc <= INT_SRC_MAX);
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ INTENx = (__IO uint32_t *)((uint32_t)&CM_INTC->INTEN0 + 4UL * ((uint32_t)enIntSrc / INTEN_REG_MOD));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(*INTENx, 1UL << ((uint32_t)enIntSrc & 0x1FU));
+ } else {
+ CLR_REG32_BIT(*INTENx, 1UL << ((uint32_t)enIntSrc & 0x1FU));
+ }
+}
+
+/**
+ * @brief Get interrupt source interrupt status
+ * @param [in] enIntSrc: Interrupt source, can be any value @ref en_int_src_t
+ * @retval An @ref en_functional_state_t enumeration type value.
+ */
+en_functional_state_t INTC_GetIntSrcState(en_int_src_t enIntSrc)
+{
+ __IO uint32_t *INTENx;
+
+ /* Parameter validity checking */
+ DDL_ASSERT(enIntSrc <= INT_SRC_MAX);
+
+ INTENx = (__IO uint32_t *)((uint32_t)&CM_INTC->INTEN0 + 4UL * ((uint32_t)enIntSrc / INTEN_REG_MOD));
+
+ return ((*INTENx & (1UL << ((uint32_t)enIntSrc & 0x1FU))) != 0UL) ? ENABLE : DISABLE;
+}
+
+/**
+ * @brief Interrupt No.000 IRQ handler
+ * @param None
+ * @retval None
+ */
+void IRQ000_Handler(void)
+{
+ m_apfnIrqHandler[INT000_IRQn]();
+ /* Arm Errata 838869: Cortex-M4, Cortex-M4F */
+ __DSB();
+}
+
+/**
+ * @brief Interrupt No.001 IRQ handler
+ * @param None
+ * @retval None
+ */
+void IRQ001_Handler(void)
+{
+ m_apfnIrqHandler[INT001_IRQn]();
+ /* Arm Errata 838869: Cortex-M4, Cortex-M4F */
+ __DSB();
+}
+
+/**
+ * @brief Interrupt No.002 IRQ handler
+ * @param None
+ * @retval None
+ */
+void IRQ002_Handler(void)
+{
+ m_apfnIrqHandler[INT002_IRQn]();
+ /* Arm Errata 838869: Cortex-M4, Cortex-M4F */
+ __DSB();
+}
+
+/**
+ * @brief Interrupt No.003 IRQ handler
+ * @param None
+ * @retval None
+ */
+void IRQ003_Handler(void)
+{
+ m_apfnIrqHandler[INT003_IRQn]();
+ /* Arm Errata 838869: Cortex-M4, Cortex-M4F */
+ __DSB();
+}
+
+/**
+ * @brief Interrupt No.004 IRQ handler
+ * @param None
+ * @retval None
+ */
+void IRQ004_Handler(void)
+{
+ m_apfnIrqHandler[INT004_IRQn]();
+ /* Arm Errata 838869: Cortex-M4, Cortex-M4F */
+ __DSB();
+}
+
+/**
+ * @brief Interrupt No.005 IRQ handler
+ * @param None
+ * @retval None
+ */
+void IRQ005_Handler(void)
+{
+ m_apfnIrqHandler[INT005_IRQn]();
+ /* Arm Errata 838869: Cortex-M4, Cortex-M4F */
+ __DSB();
+}
+
+/**
+ * @brief Interrupt No.006 IRQ handler
+ * @param None
+ * @retval None
+ */
+void IRQ006_Handler(void)
+{
+ m_apfnIrqHandler[INT006_IRQn]();
+ /* Arm Errata 838869: Cortex-M4, Cortex-M4F */
+ __DSB();
+}
+
+/**
+ * @brief Interrupt No.007 IRQ handler
+ * @param None
+ * @retval None
+ */
+void IRQ007_Handler(void)
+{
+ m_apfnIrqHandler[INT007_IRQn]();
+ /* Arm Errata 838869: Cortex-M4, Cortex-M4F */
+ __DSB();
+}
+
+/**
+ * @brief Interrupt No.008 IRQ handler
+ * @param None
+ * @retval None
+ */
+void IRQ008_Handler(void)
+{
+ m_apfnIrqHandler[(uint32_t)INT008_IRQn - IRQn_OFFSET]();
+ /* Arm Errata 838869: Cortex-M4, Cortex-M4F */
+ __DSB();
+}
+
+/**
+ * @brief Interrupt No.009 IRQ handler
+ * @param None
+ * @retval None
+ */
+void IRQ009_Handler(void)
+{
+ m_apfnIrqHandler[(uint32_t)INT009_IRQn - IRQn_OFFSET]();
+ /* Arm Errata 838869: Cortex-M4, Cortex-M4F */
+ __DSB();
+}
+
+/**
+ * @brief Interrupt No.010 IRQ handler
+ * @param None
+ * @retval None
+ */
+void IRQ010_Handler(void)
+{
+ m_apfnIrqHandler[(uint32_t)INT010_IRQn - IRQn_OFFSET]();
+ /* Arm Errata 838869: Cortex-M4, Cortex-M4F */
+ __DSB();
+}
+
+/**
+ * @brief Interrupt No.011 IRQ handler
+ * @param None
+ * @retval None
+ */
+void IRQ011_Handler(void)
+{
+ m_apfnIrqHandler[(uint32_t)INT011_IRQn - IRQn_OFFSET]();
+ /* Arm Errata 838869: Cortex-M4, Cortex-M4F */
+ __DSB();
+}
+
+/**
+ * @brief Interrupt No.012 IRQ handler
+ * @param None
+ * @retval None
+ */
+void IRQ012_Handler(void)
+{
+ m_apfnIrqHandler[(uint32_t)INT012_IRQn - IRQn_OFFSET]();
+ /* Arm Errata 838869: Cortex-M4, Cortex-M4F */
+ __DSB();
+}
+
+/**
+ * @brief Interrupt No.013 IRQ handler
+ * @param None
+ * @retval None
+ */
+void IRQ013_Handler(void)
+{
+ m_apfnIrqHandler[(uint32_t)INT013_IRQn - IRQn_OFFSET]();
+ /* Arm Errata 838869: Cortex-M4, Cortex-M4F */
+ __DSB();
+}
+
+/**
+ * @brief Interrupt No.014 IRQ handler
+ * @param None
+ * @retval None
+ */
+void IRQ014_Handler(void)
+{
+ m_apfnIrqHandler[(uint32_t)INT014_IRQn - IRQn_OFFSET]();
+ /* Arm Errata 838869: Cortex-M4, Cortex-M4F */
+ __DSB();
+}
+
+/**
+ * @brief Interrupt No.015 IRQ handler
+ * @param None
+ * @retval None
+ */
+void IRQ015_Handler(void)
+{
+ m_apfnIrqHandler[(uint32_t)INT015_IRQn - IRQn_OFFSET]();
+ /* Arm Errata 838869: Cortex-M4, Cortex-M4F */
+ __DSB();
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_INTERRUPTS_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_keyscan.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_keyscan.c
new file mode 100644
index 0000000000..26e786a3de
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_keyscan.c
@@ -0,0 +1,258 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_keyscan.c
+ * @brief This file provides firmware functions to manage the matrix keyscan
+ * function (KEYSCAN).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Add function KEYSCAN_DeInit
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_keyscan.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_KEYSCAN KEYSCAN
+ * @brief Matrix keyscan Driver Library
+ * @{
+ */
+
+#if (LL_KEYSCAN_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup KEYSCAN_Local_Macros KEYSCAN Local Macros
+ * @{
+ */
+
+/**
+ * @defgroup KEYSCAN_Check_Parameters_Validity KEYSCAN Check Parameters Validity
+ * @{
+ */
+/*! Parameter valid check for KEYSCAN HiZ state cycles. */
+#define IS_KEYSCAN_HIZ_CYCLE(clc) \
+( ((clc) == KEYSCAN_HIZ_CYCLE_4) || \
+ ((clc) == KEYSCAN_HIZ_CYCLE_8) || \
+ ((clc) == KEYSCAN_HIZ_CYCLE_16) || \
+ ((clc) == KEYSCAN_HIZ_CYCLE_32) || \
+ ((clc) == KEYSCAN_HIZ_CYCLE_64) || \
+ ((clc) == KEYSCAN_HIZ_CYCLE_256) || \
+ ((clc) == KEYSCAN_HIZ_CYCLE_512) || \
+ ((clc) == KEYSCAN_HIZ_CYCLE_1024))
+
+/*! Parameter valid check for KEYSCAN low level output cycles. */
+#define IS_KEYSCAN_LOW_CYCLE(clc) \
+( ((clc) == KEYSCAN_LOW_CYCLE_4) || \
+ ((clc) == KEYSCAN_LOW_CYCLE_8) || \
+ ((clc) == KEYSCAN_LOW_CYCLE_16) || \
+ ((clc) == KEYSCAN_LOW_CYCLE_32) || \
+ ((clc) == KEYSCAN_LOW_CYCLE_64) || \
+ ((clc) == KEYSCAN_LOW_CYCLE_128) || \
+ ((clc) == KEYSCAN_LOW_CYCLE_256) || \
+ ((clc) == KEYSCAN_LOW_CYCLE_512) || \
+ ((clc) == KEYSCAN_LOW_CYCLE_1K) || \
+ ((clc) == KEYSCAN_LOW_CYCLE_2K) || \
+ ((clc) == KEYSCAN_LOW_CYCLE_4K) || \
+ ((clc) == KEYSCAN_LOW_CYCLE_8K) || \
+ ((clc) == KEYSCAN_LOW_CYCLE_16K) || \
+ ((clc) == KEYSCAN_LOW_CYCLE_32K) || \
+ ((clc) == KEYSCAN_LOW_CYCLE_64K) || \
+ ((clc) == KEYSCAN_LOW_CYCLE_128K) || \
+ ((clc) == KEYSCAN_LOW_CYCLE_256K) || \
+ ((clc) == KEYSCAN_LOW_CYCLE_512K) || \
+ ((clc) == KEYSCAN_LOW_CYCLE_1M) || \
+ ((clc) == KEYSCAN_LOW_CYCLE_2M) || \
+ ((clc) == KEYSCAN_LOW_CYCLE_4M) || \
+ ((clc) == KEYSCAN_LOW_CYCLE_8M) || \
+ ((clc) == KEYSCAN_LOW_CYCLE_16M))
+
+/*! Parameter valid check for KEYSCAN scan clock. */
+#define IS_KEYSCAN_CLK(clk) \
+( ((clk) == KEYSCAN_CLK_HCLK) || \
+ ((clk) == KEYSCAN_CLK_LRC) || \
+ ((clk) == KEYSCAN_CLK_XTAL32))
+
+/*! Parameter valid check for KEYSCAN keyout pins. */
+#define IS_KEYSCAN_OUT(out) \
+( ((out) == KEYSCAN_OUT_0T1) || \
+ ((out) == KEYSCAN_OUT_0T2) || \
+ ((out) == KEYSCAN_OUT_0T3) || \
+ ((out) == KEYSCAN_OUT_0T4) || \
+ ((out) == KEYSCAN_OUT_0T5) || \
+ ((out) == KEYSCAN_OUT_0T6) || \
+ ((out) == KEYSCAN_OUT_0T7))
+
+/*! Parameter valid check for KEYSCAN keyin(EIRQ) pins. */
+#define IS_KEYSCAN_IN(in) \
+( ((in) != 0x00U) && \
+ (((in) | KEYSCAN_IN_ALL) == KEYSCAN_IN_ALL))
+
+/**
+ * @}
+ */
+
+#define KEYSCAN_RMU_TIMEOUT (100U)
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup KEYSCAN_Global_Functions KEYSCAN Global Functions
+ * @{
+ */
+
+/**
+ * @brief KEYSCAN function config.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void KEYSCAN_Cmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ WRITE_REG32(CM_KEYSCAN->SER, enNewState);
+}
+
+/**
+ * @brief Initialize KEYSCAN config structure. Fill each pstcKeyscanInit with default value
+ * @param [in] pstcKeyscanInit Pointer to a stc_keyscan_init_t structure that
+ * contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: KEYSCAN structure initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t KEYSCAN_StructInit(stc_keyscan_init_t *pstcKeyscanInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcKeyscanInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ pstcKeyscanInit->u32HizCycle = KEYSCAN_HIZ_CYCLE_4;
+ pstcKeyscanInit->u32LowCycle = KEYSCAN_LOW_CYCLE_4;
+ pstcKeyscanInit->u32KeyClock = KEYSCAN_CLK_HCLK;
+ pstcKeyscanInit->u32KeyOut = KEYSCAN_OUT_0T1;
+ pstcKeyscanInit->u32KeyIn = KEYSCAN_IN_0;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief KEYSCAN initialize.
+ * @param [in] pstcKeyscanInit KEYSCAN config structure.
+ * @arg u32HizCycle Hiz state keep cycles during low level output.
+ * @arg u32LowCycle Low level output cycles.
+ * @arg u32KeyClock Scan clock.
+ * @arg u32KeyOut KEYOUT selection.
+ * @arg u32KeyIn KEYIN(EIRQ) selection.
+ * @retval int32_t:
+ * - LL_OK: KEYSCAN function initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t KEYSCAN_Init(const stc_keyscan_init_t *pstcKeyscanInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcKeyscanInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ DDL_ASSERT(IS_KEYSCAN_HIZ_CYCLE(pstcKeyscanInit->u32HizCycle));
+ DDL_ASSERT(IS_KEYSCAN_LOW_CYCLE(pstcKeyscanInit->u32LowCycle));
+ DDL_ASSERT(IS_KEYSCAN_CLK(pstcKeyscanInit->u32KeyClock));
+ DDL_ASSERT(IS_KEYSCAN_OUT(pstcKeyscanInit->u32KeyOut));
+ DDL_ASSERT(IS_KEYSCAN_IN(pstcKeyscanInit->u32KeyIn));
+
+ WRITE_REG32(CM_KEYSCAN->SCR, \
+ (pstcKeyscanInit->u32HizCycle | pstcKeyscanInit->u32LowCycle | \
+ pstcKeyscanInit->u32KeyClock | pstcKeyscanInit->u32KeyOut | \
+ pstcKeyscanInit->u32KeyIn));
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief De-initialize the KEYSCAN.
+ * @param None
+ * @retval int32_t:
+ * - LL_OK: De-Initialize success.
+ * - LL_ERR_TIMEOUT: Timeout
+ */
+int32_t KEYSCAN_DeInit(void)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint8_t u8TimeOut = 0U;
+
+ DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB0) == PWC_FPRC_FPRCB0);
+
+ /* Reset KEYSCAN */
+ WRITE_REG32(bCM_RMU->FRST0_b.KEY, 0UL);
+
+ /* Ensure reset procedure is completed */
+ while (0UL == READ_REG32(bCM_RMU->FRST0_b.KEY)) {
+ u8TimeOut++;
+ if (u8TimeOut > KEYSCAN_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_KEYSCAN_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_mau.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_mau.c
new file mode 100644
index 0000000000..91be84a562
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_mau.c
@@ -0,0 +1,306 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_mau.c
+ * @brief This file provides firmware functions to manage the MAU.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Add API MAU_DeInit()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_mau.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_MAU MAU
+ * @brief MAU Driver Library
+ * @{
+ */
+
+#if (LL_MAU_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup MAU_Local_Macros MAU Local Macros
+ * @{
+ */
+
+#define MAU_RMU_TIMEOUT (100UL)
+
+/**
+ * @defgroup MAU_Check_Parameters_Validity MAU Check Parameters Validity
+ * @{
+ */
+#define IS_VALID_UNIT(x) ((x) == CM_MAU)
+#define IS_LSHBIT_NUM(x) ((x) <= MAU_SQRT_OUTPUT_LSHIFT_MAX)
+#define IS_ANGLE_IDX(x) ((x) < MAU_SIN_ANGIDX_TOTAL)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ * @defgroup MAU_Global_Functions MAU Global Functions
+ * @{
+ */
+
+/**
+ * @brief Sqrt result left shift config
+ * @param [in] MAUx Pointer to MAU instance register base.
+ * This parameter can only be: @arg CM_MAU
+ * @param [in] u8ShiftNum Number of left shift bits
+ * Max value is MAU_SQRT_OUTPUT_LSHIFT_MAX
+ * @retval None
+ */
+void MAU_SqrtResultLShiftConfig(CM_MAU_TypeDef *MAUx, uint8_t u8ShiftNum)
+{
+ DDL_ASSERT(IS_VALID_UNIT(MAUx));
+ DDL_ASSERT(IS_LSHBIT_NUM(u8ShiftNum));
+
+ MODIFY_REG32(MAUx->CSR, MAU_CSR_SHIFT, ((uint32_t)u8ShiftNum << MAU_CSR_SHIFT_POS));
+}
+
+/**
+ * @brief Sqrt interrupt function command
+ * @param [in] MAUx Pointer to MAU instance register base.
+ * This parameter can only be: @arg CM_MAU
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void MAU_SqrtIntCmd(CM_MAU_TypeDef *MAUx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_UNIT(MAUx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ MODIFY_REG32(MAUx->CSR, MAU_CSR_INTEN, (uint32_t)enNewState << MAU_CSR_INTEN_POS);
+}
+
+/**
+ * @brief Input radicand for sqrt
+ * @param [in] MAUx Pointer to MAU instance register base.
+ * This parameter can only be: @arg CM_MAU
+ * @param [in] u32Radicand Data to be square rooted
+ * @retval None
+ */
+void MAU_SqrtWriteData(CM_MAU_TypeDef *MAUx, uint32_t u32Radicand)
+{
+ DDL_ASSERT(IS_VALID_UNIT(MAUx));
+
+ WRITE_REG32(MAUx->DTR0, u32Radicand);
+}
+
+/**
+ * @brief Start sqrt calculation
+ * @param [in] MAUx Pointer to MAU instance register base.
+ * This parameter can only be: @arg CM_MAU
+ * @retval None
+ */
+void MAU_SqrtStart(CM_MAU_TypeDef *MAUx)
+{
+ DDL_ASSERT(IS_VALID_UNIT(MAUx));
+
+ SET_REG32_BIT(MAUx->CSR, MAU_CSR_START);
+}
+
+/**
+ * @brief Check whether the sqrt calculation is in progress
+ * @param [in] MAUx Pointer to MAU instance register base.
+ * This parameter can only be: @arg CM_MAU
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t MAU_SqrtGetStatus(const CM_MAU_TypeDef *MAUx)
+{
+ DDL_ASSERT(IS_VALID_UNIT(MAUx));
+
+ return (0UL != READ_REG32_BIT(MAUx->CSR, MAU_CSR_BUSY)) ? SET : RESET;
+}
+
+/**
+ * @brief Read result of sqrt
+ * @param [in] MAUx Pointer to MAU instance register base.
+ * This parameter can only be: @arg CM_MAU
+ * @retval Result of sqrt,range is [0,0x10000]
+ */
+uint32_t MAU_SqrtReadData(const CM_MAU_TypeDef *MAUx)
+{
+ DDL_ASSERT(IS_VALID_UNIT(MAUx));
+
+ return READ_REG32(MAUx->RTR0);
+}
+
+/**
+ * @brief Initialize the MAU Sqrt function.
+ * @param [in] MAUx Pointer to MAU instance register base.
+ * This parameter can only be: @arg CM_MAU
+ * @param [in] u8ShiftNum Sqrt result left shift bits, max value is @ref MAU_SQRT_OUTPUT_LSHIFT_MAX
+ * @param [in] enNewState Enable or Disable sqrt interrupt @ref en_functional_state_t
+ * @retval None
+ */
+void MAU_SqrtInit(CM_MAU_TypeDef *MAUx, uint8_t u8ShiftNum, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_UNIT(MAUx));
+ DDL_ASSERT(IS_LSHBIT_NUM(u8ShiftNum));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ MODIFY_REG32(MAUx->CSR, MAU_CSR_SHIFT | MAU_CSR_INTEN,
+ ((((uint32_t)u8ShiftNum << MAU_CSR_SHIFT_POS)) | ((uint32_t)enNewState << MAU_CSR_INTEN_POS)));
+}
+
+/**
+ * @brief De-initialize the MAU Sqrt function.
+ * @param [in] MAUx Pointer to MAU instance register base.
+ * This parameter can only be: @arg CM_MAU
+ * @retval None
+ */
+void MAU_SqrtDeInit(CM_MAU_TypeDef *MAUx)
+{
+ DDL_ASSERT(IS_VALID_UNIT(MAUx));
+
+ CLR_REG32_BIT(MAUx->CSR, MAU_CSR_SHIFT | MAU_CSR_INTEN);
+}
+
+/**
+ * @brief Square root
+ * @param [in] MAUx Pointer to MAU instance register base.
+ * This parameter can only be: @arg CM_MAU
+ * @param [in] u32Radicand Data to be square rooted
+ * @param [out] pu32Result Result of sqrt,range is [0,0x10000]
+ * @retval int32_t:
+ * - LL_OK: No errors occurred
+ * - LL_ERR: Errors occurred
+ */
+int32_t MAU_Sqrt(CM_MAU_TypeDef *MAUx, uint32_t u32Radicand, uint32_t *pu32Result)
+{
+ __IO uint32_t u32TimeCount = MAU_SQRT_TIMEOUT;
+ int32_t i32Ret = LL_OK;
+
+ DDL_ASSERT(IS_VALID_UNIT(MAUx));
+ DDL_ASSERT(pu32Result != (void *)0UL);
+
+ WRITE_REG32(MAUx->DTR0, u32Radicand);
+
+ SET_REG32_BIT(MAUx->CSR, MAU_CSR_START);
+ __ASM("NOP");
+ __ASM("NOP");
+ __ASM("NOP");
+
+ while ((MAUx->CSR & MAU_CSR_BUSY) != 0UL) {
+ if (u32TimeCount-- == 0UL) {
+ i32Ret = LL_ERR;
+ break;
+ }
+ }
+
+ if (LL_OK == i32Ret) {
+ *pu32Result = READ_REG32(MAUx->RTR0);
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Sine
+ * @param [in] MAUx Pointer to MAU instance register base.
+ * This parameter can only be: @arg CM_MAU
+ * @param u16AngleIdx: Angle index,range is [0,0xFFF], calculation method for reference:
+ AngleIdx = (uint16_t)(Angle * 4096.0F / 360.0F + 0.5F) % 4096U
+ * @retval Result of Sine in Q15 format
+ */
+int16_t MAU_Sin(CM_MAU_TypeDef *MAUx, uint16_t u16AngleIdx)
+{
+ DDL_ASSERT(IS_VALID_UNIT(MAUx));
+ DDL_ASSERT(IS_ANGLE_IDX(u16AngleIdx));
+
+ WRITE_REG16(MAUx->DTR1, u16AngleIdx);
+ __ASM("NOP");
+
+ return (int16_t)READ_REG16(MAUx->RTR1);
+}
+
+/**
+ * @brief De-initializes MAU.
+ * @param None
+ * @retval int32_t:
+ * - LL_OK: De-Initialize success.
+ * - LL_ERR_TIMEOUT: Timeout.
+ */
+int32_t MAU_DeInit(void)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t u32TimeOut = 0UL;
+ /* Check FRST register protect */
+ DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1);
+
+ WRITE_REG32(bCM_RMU->FRST0_b.MAU, 0UL);
+ /* Ensure reset procedure is completed */
+ while (0UL == READ_REG32(bCM_RMU->FRST0_b.MAU)) {
+ u32TimeOut++;
+ if (u32TimeOut > MAU_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_MAU_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_mdio.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_mdio.c
new file mode 100644
index 0000000000..263f170a9f
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_mdio.c
@@ -0,0 +1,608 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_mdio.c
+ * @brief This file provides firmware functions to manage the MDIO Serial Bus
+ * Interface(MDIO).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Modify typo
+ Optimized MDIO_DeInit function
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_mdio.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_MDIO MDIO
+ * @brief MDIO Serial Bus Interface
+ * @{
+ */
+
+#if (LL_MDIO_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup MDIO_Local_Macros MDIO Local Macros
+ * @{
+ */
+
+/* Wait timeout */
+#define MDIO_RST_TIMEOUT (0x1000UL)
+
+/**
+ * @defgroup MDIO_Check_Parameters_Validity MDIO Check Parameters Validity
+ * @{
+ */
+#define IS_MDIO_UNIT(x) ((x) == CM_MDIO)
+
+#define IS_MDIO_PHY_ADDR_BIT_WIDTH(x) \
+( ((x) == MDIO_PHY_ADDR_5BIT) || \
+ ((x) == MDIO_PHY_ADDR_3BIT))
+
+#define IS_MDIO_PHY_ADDR_MD(x) \
+( ((x) == MDIO_PHY_ADDR_MD_HW) || \
+ ((x) == MDIO_PHY_ADDR_MD_SW))
+
+#define IS_MDIO_PHY_ADDR(x) ((x) <= 0x1FUL)
+
+#define IS_MDIO_DEV_ADDR_MASK(x) \
+( ((x) == MDIO_DEV_ADDR_MASK_DISABLE) || \
+ ((x) == MDIO_DEV_ADDR_MASK_ENABLE))
+
+#define IS_MDIO_DEV_ADDR(x) ((x) <= 0x1FUL)
+
+#define IS_MDIO_MDC_DETECT_LVL(x) \
+( ((x) == MDIO_MDC_DETECT_LVL_LOW) || \
+ ((x) == MDIO_MDC_DETECT_LVL_HIGH))
+
+#define IS_MDIO_WR_DATA(x) ((x) <= 0xFFFFUL)
+
+#define IS_MDIO_MDC_TIMEOUT(x) ((x) <= 0xFFFFUL)
+
+#define IS_MDIO_INT(x) \
+( ((x) != 0UL) && \
+ (((x) | MDIO_INT_ALL) == MDIO_INT_ALL))
+
+#define IS_MDIO_FLAG(x) \
+( ((x) != 0UL) && \
+ (((x) | MDIO_FLAG_ALL) == MDIO_FLAG_ALL))
+
+#define IS_MDIO_PWC_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1)
+
+/* MDIO reset timeout */
+#define MDIO_RMU_TIMEOUT (100UL)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup MDIO_Local_Func MDIO Local Functions
+ * @{
+ */
+
+/**
+ * @brief De-Initialize MDIO.
+ * @param [in] MDIOx Pointer to MDIO unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_MDIO or CM_MDIOx: MDIO unit instance
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_TIMEOUT: Works timeout.
+ */
+int32_t MDIO_DeInit(CM_MDIO_TypeDef *MDIOx)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t u32TimeOut = 0U;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_MDIO_PWC_UNLOCKED());
+
+ CLR_REG32_BIT(CM_RMU->FRST1, RMU_FRST1_MDIO);
+ /* Ensure reset procedure is completed */
+ while (RMU_FRST1_MDIO != READ_REG32_BIT(CM_RMU->FRST1, RMU_FRST1_MDIO)) {
+ u32TimeOut++;
+ if (u32TimeOut > MDIO_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize MDIO.
+ * @param [in] MDIOx Pointer to MDIO unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_MDIO or CM_MDIOx: MDIO unit instance
+ * @param [in] pstcMdioInit Pointer to a @ref stc_mdio_init_t structure.
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: pstcMdioInit is NULL
+ */
+int32_t MDIO_Init(CM_MDIO_TypeDef *MDIOx, const stc_mdio_init_t *pstcMdioInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcMdioInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Check parameters */
+ DDL_ASSERT(IS_MDIO_UNIT(MDIOx));
+ DDL_ASSERT(IS_MDIO_PHY_ADDR_BIT_WIDTH(pstcMdioInit->u32PhyAddrBitWidth));
+ DDL_ASSERT(IS_MDIO_PHY_ADDR_MD(pstcMdioInit->u32PhyAddrMode));
+ DDL_ASSERT(IS_MDIO_PHY_ADDR(pstcMdioInit->u32PhyAddr));
+ DDL_ASSERT(IS_MDIO_DEV_ADDR_MASK(pstcMdioInit->u32DevAddrMask));
+ DDL_ASSERT(IS_MDIO_DEV_ADDR(pstcMdioInit->u32DevAddr));
+
+ MODIFY_REG32(MDIOx->MDCON, MDIO_MDCON_MD_PHYB, pstcMdioInit->u32PhyAddrBitWidth);
+ MODIFY_REG32(MDIOx->MDCON1, MDIO_MDCON1_MD_MSDEV, pstcMdioInit->u32DevAddrMask);
+ if (MDIO_PHY_ADDR_MD_SW == pstcMdioInit->u32PhyAddrMode) {
+ MODIFY_REG32(MDIOx->MDPHY, (MDIO_MDPHY_MD_PHYSEL | MDIO_MDPHY_MD_DEVADD | MDIO_MDPHY_MD_PHYSW),
+ (pstcMdioInit->u32PhyAddrMode | (pstcMdioInit->u32DevAddr << MDIO_MDPHY_MD_DEVADD_POS) |
+ pstcMdioInit->u32PhyAddr));
+ } else {
+ MODIFY_REG32(MDIOx->MDPHY, (MDIO_MDPHY_MD_PHYSEL | MDIO_MDPHY_MD_DEVADD),
+ (pstcMdioInit->u32PhyAddrMode | (pstcMdioInit->u32DevAddr << MDIO_MDPHY_MD_DEVADD_POS)));
+ }
+
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set the fields of structure stc_mdio_init_t to default values.
+ * @param [out] pstcMdioInit Pointer to a @ref stc_mdio_init_t structure.
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: pstcMdioInit is NULL
+ */
+int32_t MDIO_StructInit(stc_mdio_init_t *pstcMdioInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcMdioInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ pstcMdioInit->u32PhyAddrBitWidth = MDIO_PHY_ADDR_5BIT;
+ pstcMdioInit->u32PhyAddrMode = MDIO_PHY_ADDR_MD_HW;
+ pstcMdioInit->u32PhyAddr = 0UL;
+ pstcMdioInit->u32DevAddrMask = MDIO_DEV_ADDR_MASK_DISABLE;
+ pstcMdioInit->u32DevAddr = 1UL;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Reset the MDIO.
+ * @param [in] MDIOx Pointer to MDIO unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_MDIO or CM_MDIOx: MDIO unit instance
+ * @retval int32_t:
+ * - LL_OK: Software reset success
+ * - LL_ERR_TIMEOUT: Reset timeout
+ */
+int32_t MDIO_Reset(CM_MDIO_TypeDef *MDIOx)
+{
+ __IO uint32_t u32Count = MDIO_RST_TIMEOUT;
+ int32_t i32Ret = LL_OK;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_MDIO_UNIT(MDIOx));
+
+ SET_REG32_BIT(MDIOx->MDCON, MDIO_MDCON_MD_RST);
+ while (0UL != READ_REG32_BIT(MDIOx->MDCON, MDIO_MDCON_MD_RST)) {
+ if (0UL == u32Count) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ u32Count--;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set the mask of the device address.
+ * @param [in] MDIOx Pointer to MDIO unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_MDIO or CM_MDIOx: MDIO unit instance
+ * @param [in] u32Mask Select the mask.
+ * This parameter can be one of the following values:
+ * @arg MDIO_DEV_ADDR_MASK_DISABLE: Don't mask the result of the device address
+ * @arg MDIO_DEV_ADDR_MASK_ENABLE: Masking the result of the device address
+ * @retval None
+ */
+void MDIO_SetDevAddrMask(CM_MDIO_TypeDef *MDIOx, uint32_t u32Mask)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_MDIO_UNIT(MDIOx));
+ DDL_ASSERT(IS_MDIO_DEV_ADDR_MASK(u32Mask));
+
+ if (MDIO_DEV_ADDR_MASK_ENABLE == u32Mask) {
+ SET_REG32_BIT(MDIOx->MDCON1, MDIO_MDCON1_MD_MSDEV);
+ } else {
+ CLR_REG32_BIT(MDIOx->MDCON1, MDIO_MDCON1_MD_MSDEV);
+ }
+}
+
+/**
+ * @brief Read data of data frame.
+ * @param [in] MDIOx Pointer to MDIO unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_MDIO or CM_MDIOx: MDIO unit instance
+ * @retval uint32_t Receive data.
+ */
+uint32_t MDIO_ReadData(const CM_MDIO_TypeDef *MDIOx)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_MDIO_UNIT(MDIOx));
+
+ return READ_REG32(MDIOx->MDRXD);
+}
+
+/**
+ * @brief Read data of address frame.
+ * @param [in] MDIOx Pointer to MDIO unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_MDIO or CM_MDIOx: MDIO unit instance
+ * @retval uint32_t Receive data.
+ */
+uint32_t MDIO_ReadAddr(const CM_MDIO_TypeDef *MDIOx)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_MDIO_UNIT(MDIOx));
+
+ return READ_REG32(MDIOx->MDADR);
+}
+
+/**
+ * @brief Write data.
+ * @param [in] MDIOx Pointer to MDIO unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_MDIO or CM_MDIOx: MDIO unit instance
+ * @param [in] u32Data Send data.
+ * This parameter can be a number between 0UL and 0xFFFFUL.
+ * @retval None
+ */
+void MDIO_WriteData(CM_MDIO_TypeDef *MDIOx, uint32_t u32Data)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_MDIO_UNIT(MDIOx));
+ DDL_ASSERT(IS_MDIO_WR_DATA(u32Data));
+
+ WRITE_REG32(MDIOx->MDTXD, u32Data);
+}
+
+/**
+ * @brief Set device address.
+ * @param [in] MDIOx Pointer to MDIO unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_MDIO or CM_MDIOx: MDIO unit instance
+ * @param [in] u32Addr Device address value.
+ * This parameter can be a number between 0UL and 0x1FUL.
+ * @retval None
+ */
+void MDIO_SetDevAddr(CM_MDIO_TypeDef *MDIOx, uint32_t u32Addr)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_MDIO_UNIT(MDIOx));
+ DDL_ASSERT(IS_MDIO_DEV_ADDR(u32Addr));
+
+ MODIFY_REG32(MDIOx->MDPHY, MDIO_MDPHY_MD_DEVADD, (u32Addr << MDIO_MDPHY_MD_DEVADD_POS));
+}
+
+/**
+ * @brief Set PHY address.
+ * @param [in] MDIOx Pointer to MDIO unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_MDIO or CM_MDIOx: MDIO unit instance
+ * @param [in] u32Addr Phy address value.
+ * This parameter can be a number between 0UL and 0x1FUL.
+ * @retval None
+ */
+void MDIO_SetPhyAddr(CM_MDIO_TypeDef *MDIOx, uint32_t u32Addr)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_MDIO_UNIT(MDIOx));
+ DDL_ASSERT(IS_MDIO_PHY_ADDR(u32Addr));
+
+ MODIFY_REG32(MDIOx->MDPHY, MDIO_MDPHY_MD_PHYSW, u32Addr);
+}
+
+/**
+ * @brief Get PHY address.
+ * @param [in] MDIOx Pointer to MDIO unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_MDIO or CM_MDIOx: MDIO unit instance
+ * @param [in] u32Mode Phy address mode.
+ * This parameter can be one of the following values:
+ * @arg MDIO_PHY_ADDR_MD_HW: Hardware address mode
+ * @arg MDIO_PHY_ADDR_MD_SW: Software address mode
+ * @retval uint32_t Phy address value.
+ */
+uint32_t MDIO_GetPhyAddr(CM_MDIO_TypeDef *MDIOx, uint32_t u32Mode)
+{
+ uint32_t u32Addr;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_MDIO_UNIT(MDIOx));
+ DDL_ASSERT(IS_MDIO_PHY_ADDR_MD(u32Mode));
+
+ if (MDIO_PHY_ADDR_MD_SW == u32Mode) {
+ u32Addr = READ_REG32_BIT(MDIOx->MDPHY, MDIO_MDPHY_MD_PHYSW);
+ } else {
+ u32Addr = READ_REG32_BIT(MDIOx->MDPIN, MDIO_MDPIN_MD_PIN);
+ }
+
+ return u32Addr;
+}
+
+/**
+ * @brief Configure the MDC Timeout.
+ * @param [in] MDIOx Pointer to MDIO unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_MDIO or CM_MDIOx: MDIO unit instance
+ * @param [in] u32Level Select the detect level of the MDC.
+ * This parameter can be one of the following values:
+ * @arg MDIO_MDC_DETECT_LVL_LOW: Detect low level
+ * @arg MDIO_MDC_DETECT_LVL_HIGH: Detect high level
+ * @param [in] u32Time Timeout time.
+ * This parameter can be a number between 0UL and 0xFFFFUL.
+ * @retval None
+ */
+void MDIO_MdcTimeoutConfig(CM_MDIO_TypeDef *MDIOx, uint32_t u32Level, uint32_t u32Time)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_MDIO_UNIT(MDIOx));
+ DDL_ASSERT(IS_MDIO_MDC_DETECT_LVL(u32Level));
+ DDL_ASSERT(IS_MDIO_MDC_TIMEOUT(u32Time));
+
+ MODIFY_REG32(MDIOx->MDCON1, MDIO_MDCON1_SEL_EDGE, u32Level);
+ MODIFY_REG32(MDIOx->MDTO, MDIO_MDTO_TOCNT, u32Time);
+}
+
+/**
+ * @brief Enable or disable the MDC timeout.
+ * @param [in] MDIOx Pointer to MDIO unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_MDIO or CM_MDIOx: MDIO unit instance
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void MDIO_MdcTimeoutCmd(CM_MDIO_TypeDef *MDIOx, en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_MDIO_UNIT(MDIOx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (DISABLE != enNewState) {
+ SET_REG32_BIT(MDIOx->MDTO, MDIO_MDTO_TOEN);
+ } else {
+ CLR_REG32_BIT(MDIOx->MDTO, MDIO_MDTO_TOEN);
+ }
+}
+
+/**
+ * @brief Enable or disable the MDIO.
+ * @param [in] MDIOx Pointer to MDIO unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_MDIO or CM_MDIOx: MDIO unit instance
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void MDIO_Cmd(CM_MDIO_TypeDef *MDIOx, en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_MDIO_UNIT(MDIOx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (DISABLE != enNewState) {
+ SET_REG32_BIT(MDIOx->MDCON1, MDIO_MDCON1_MD_EN);
+ } else {
+ CLR_REG32_BIT(MDIOx->MDCON1, MDIO_MDCON1_MD_EN);
+ }
+}
+
+/**
+ * @brief Get the operation code in receive frame.
+ * @param [in] MDIOx Pointer to MDIO unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_MDIO or CM_MDIOx: MDIO unit instance
+ * @retval uint32_t Operation code.
+ */
+uint32_t MDIO_GetReceiveOperaCode(CM_MDIO_TypeDef *MDIOx)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_MDIO_UNIT(MDIOx));
+
+ return READ_REG32_BIT(MDIOx->MDFRM, MDIO_MDFRM_MD_ROP);
+}
+
+/**
+ * @brief Get the phy address in receive frame.
+ * @param [in] MDIOx Pointer to MDIO unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_MDIO or CM_MDIOx: MDIO unit instance
+ * @retval uint32_t Phy address.
+ */
+uint32_t MDIO_GetReceivePhyAddr(CM_MDIO_TypeDef *MDIOx)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_MDIO_UNIT(MDIOx));
+
+ return (READ_REG32_BIT(MDIOx->MDFRM, MDIO_MDFRM_MD_RPHYAD) >> MDIO_MDFRM_MD_RPHYAD_POS);
+}
+
+/**
+ * @brief Get the device address in receive frame.
+ * @param [in] MDIOx Pointer to MDIO unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_MDIO or CM_MDIOx: MDIO unit instance
+ * @retval uint32_t Device address.
+ */
+uint32_t MDIO_GetReceiveDevAddr(CM_MDIO_TypeDef *MDIOx)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_MDIO_UNIT(MDIOx));
+
+ return (READ_REG32_BIT(MDIOx->MDFRM, MDIO_MDFRM_MD_RDEVAD) >> MDIO_MDFRM_MD_RDEVAD_POS);
+}
+
+/**
+ * @brief Get the convert bit in receive frame.
+ * @param [in] MDIOx Pointer to MDIO unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_MDIO or CM_MDIOx: MDIO unit instance
+ * @retval uint32_t Convert bit.
+ */
+uint32_t MDIO_GetReceiveConvertBit(CM_MDIO_TypeDef *MDIOx)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_MDIO_UNIT(MDIOx));
+
+ return READ_REG32_BIT(MDIOx->MDFRM, MDIO_MDFRM_MD_RTA);
+}
+
+/**
+ * @brief Enable or disable the specified MDIO interrupt.
+ * @param [in] MDIOx Pointer to MDIO unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_MDIO or CM_MDIOx: MDIO unit instance
+ * @param [in] u32IntType MDIO interrupt type
+ * This parameter can be any combination value of the following values:
+ * @arg @ref MDIO_Interrupt
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void MDIO_IntCmd(CM_MDIO_TypeDef *MDIOx, uint32_t u32IntType, en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_MDIO_UNIT(MDIOx));
+ DDL_ASSERT(IS_MDIO_INT(u32IntType));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(MDIOx->MDIEN, u32IntType);
+ } else {
+ CLR_REG32_BIT(MDIOx->MDIEN, u32IntType);
+ }
+}
+
+/**
+ * @brief Get MDIO status.
+ * @param [in] MDIOx Pointer to MDIO unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_MDIO or CM_MDIOx: MDIO unit instance
+ * @param [in] u32Flag MDIO flag type
+ * This parameter can be one or any combination of the following values:
+ * @arg MDIO_FLAG_WR_FRAME_MATCH: PHY and device address match flags in write frame
+ * @arg MDIO_FLAG_ADDR_FRAME_MATCH: PHY and device address match flags in address frame
+ * @arg MDIO_FLAG_INC_ADDR_FRAME_MATCH: PHY and device address match flags in increase address frame
+ * @arg MDIO_FLAG_RD_FRAME_MATCH: PHY and device address match flags in read frame
+ * @arg MDIO_FLAG_DEV_ADDR_MATCH: Device address match flag
+ * @arg MDIO_FLAG_DEV_ADDR_MISMATCH: Device address mismatch flag
+ * @arg MDIO_FLAG_PHY_ADDR_MATCH: PHY address match flag
+ * @arg MDIO_FLAG_PHY_ADDR_MISMATCH: PHY address mismatch flag
+ * @arg MDIO_FLAG_TA_MISMATCH: TA bit mismatch flag
+ * @arg MDIO_FLAG_MDC_TIMEOUT: MDC timeout flag
+ * @arg MDIO_FLAG_DATA_UNF: Data send underflow flag
+ * @arg MDIO_FLAG_DATA_OVF: Data receive overflow flag
+ * @arg MDIO_FLAG_RX_FULL: Data receive buffer full flag
+ * @arg MDIO_FLAG_COMM_BUSY: Communication busy flag
+ * @arg MDIO_FLAG_ALL: All of the above
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t MDIO_GetStatus(const CM_MDIO_TypeDef *MDIOx, uint32_t u32Flag)
+{
+ en_flag_status_t enFlagSta = RESET;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_MDIO_FLAG(u32Flag));
+
+ if (0UL != READ_REG32_BIT(MDIOx->MDSTA, u32Flag)) {
+ enFlagSta = SET;
+ }
+
+ return enFlagSta;
+}
+
+/**
+ * @brief Get all status of the MDIO.
+ * @param [in] MDIOx Pointer to MDIO unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_MDIO or CM_MDIOx: MDIO unit instance
+ * @retval uint32_t MDIO status value.
+ */
+uint32_t MDIO_GetAllStatus(const CM_MDIO_TypeDef *MDIOx)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_MDIO_UNIT(MDIOx));
+
+ return READ_REG32(MDIOx->MDSTA);
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_MDIO_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_mpu.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_mpu.c
new file mode 100644
index 0000000000..478f694ce2
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_mpu.c
@@ -0,0 +1,1208 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_mpu.c
+ * @brief This file provides firmware functions to manage the Memory Protection
+ * Unit(MPU).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-09-30 CDT Optimize MPU_ClearStatus function
+ 2023-12-15 CDT Add API MPU_UnitInit(), MPU_UnitStructInit()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_mpu.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_MPU MPU
+ * @brief Memory Protection Unit Driver Library
+ * @{
+ */
+
+#if (LL_MPU_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup MPU_Local_Macros MPU Local Macros
+ * @{
+ */
+
+/* Number of MPU region */
+#define MPU_REGION_MAX_NUM (16UL)
+
+/* Number of MPU unit */
+#define MPU_UNIT_MAX_NUM (3UL)
+
+/* Number of SP unit */
+#define MPU_SP_UNIT_MAX_NUM (2UL)
+
+/* MPU Register Combination Mask */
+#define MPU_UNIT_CONFIG_MASK (MPU_SCR_SMPUBRP | MPU_SCR_SMPUBWP | MPU_SCR_SMPUACT)
+/* DMA units have 16 regions */
+#define MPU_16REGION_UNIT (MPU_UNIT_DMA1 | MPU_UNIT_DMA2)
+
+/* Get the specified register address of the MPU Intrusion Control */
+#define MPU_RGD_ADDR(__NUM__) (__IO uint32_t *)((uint32_t)(&(CM_MPU->RGD0)) + ((uint32_t)(__NUM__) << 2U))
+#define MPU_RGE_ADDR(__UNIT__) (__IO uint32_t *)((uint32_t)(&(CM_MPU->S1RGE)) + ((uint32_t)(__UNIT__) << 4U))
+#define MPU_RGWP_ADDR(__UNIT__) (__IO uint32_t *)((uint32_t)(&(CM_MPU->S1RGWP)) + ((uint32_t)(__UNIT__) << 4U))
+#define MPU_RGRP_ADDR(__UNIT__) (__IO uint32_t *)((uint32_t)(&(CM_MPU->S1RGRP)) + ((uint32_t)(__UNIT__) << 4U))
+#define MPU_CR_ADDR(__UNIT__) (__IO uint32_t *)((uint32_t)(&(CM_MPU->S1CR)) + ((uint32_t)(__UNIT__) << 4U))
+
+/* Get the SP register address */
+#define MPU_SPPBA_ADDR(__UNIT__) (__IO uint32_t *)((uint32_t)(&(CM_MPU->MSPPBA)) + ((uint32_t)(__UNIT__) << 3U))
+#define MPU_SPPCTL_ADDR(__UNIT__) (__IO uint32_t *)((uint32_t)(&(CM_MPU->MSPPCTL)) + ((uint32_t)(__UNIT__) << 3U))
+
+/**
+ * @defgroup MPU_Check_Parameters_Validity MPU Check Parameters Validity
+ * @{
+ */
+#define IS_MPU_UNIT(x) \
+( ((x) != 0UL) && \
+ (((x) | MPU_UNIT_ALL) == MPU_UNIT_ALL))
+
+#define IS_MPU_INIT_UNIT(x) \
+( ((x) == MPU_UNIT_DMA1) || \
+ ((x) == MPU_UNIT_DMA2) || \
+ ((x) == MPU_UNIT_USBFS_DMA))
+
+#define IS_MPU_REGION(x) ((x) <= MPU_REGION_NUM15)
+
+#define IS_MPU_UNIT_REGION(unit, region) \
+( (((unit) | MPU_16REGION_UNIT) == MPU_16REGION_UNIT) || \
+ ((region) <= MPU_REGION_NUM7))
+
+#define IS_MPU_BACKGROUND_WR(x) \
+( ((x) == MPU_BACKGROUND_WR_DISABLE) || \
+ ((x) == MPU_BACKGROUND_WR_ENABLE))
+
+#define IS_MPU_BACKGROUND_RD(x) \
+( ((x) == MPU_BACKGROUND_RD_DISABLE) || \
+ ((x) == MPU_BACKGROUND_RD_ENABLE))
+
+#define IS_MPU_EXP_TYPE(x) \
+( ((x) == MPU_EXP_TYPE_NONE) || \
+ ((x) == MPU_EXP_TYPE_BUS_ERR) || \
+ ((x) == MPU_EXP_TYPE_NMI) || \
+ ((x) == MPU_EXP_TYPE_RST))
+
+#define IS_MPU_REGION_WR(x) \
+( ((x) == MPU_REGION_WR_DISABLE) || \
+ ((x) == MPU_REGION_WR_ENABLE))
+
+#define IS_MPU_REGION_RD(x) \
+( ((x) == MPU_REGION_RD_DISABLE) || \
+ ((x) == MPU_REGION_RD_ENABLE))
+
+#define IS_MPU_REGION_SIZE(x) \
+( ((x) >= MPU_REGION_SIZE_32BYTE) && \
+ ((x) <= MPU_REGION_SIZE_4GBYTE))
+
+#define IS_MPU_REGION_BASE_ADDER(addr, size) \
+( ((addr) & ((uint32_t)(~((uint64_t)0xFFFFFFFFUL << ((size) + 1U))))) == 0UL)
+
+#define IS_MPU_FLAG(x) \
+( ((x) != 0UL) && \
+ (((x) | MPU_FLAG_ALL) == MPU_FLAG_ALL))
+
+#define IS_MPU_IP_TYPE(x) \
+( ((x) != 0UL) && \
+ (((x) | MPU_IP_ALL) == MPU_IP_ALL))
+
+#define IS_MPU_IP_EXP_TYPE(x) \
+( ((x) == MPU_IP_EXP_TYPE_NONE) || \
+ ((x) == MPU_IP_EXP_TYPE_BUS_ERR))
+
+#define IS_MPU_SP_UNIT(x) \
+( ((x) != 0UL) && \
+ (((x) | MPU_SP_UNIT_ALL) == MPU_SP_UNIT_ALL))
+
+#define IS_MPU_SP_EXP_TYPE(x) \
+( ((x) == MPU_SP_EXP_TYPE_NMI) || \
+ ((x) == MPU_SP_EXP_TYPE_RST))
+
+#define IS_MPU_SP_START_ADDR(x) \
+( ((x) | MPU_PSPPBA_PSPPBA) == MPU_PSPPBA_PSPPBA)
+
+#define IS_MPU_SP_ADDR_SIZE(x) \
+( ((x) >= 4UL) && ((x) <= 65536UL))
+
+#define IS_MPU_UNLOCK() ((CM_MPU->WP & MPU_WP_MPUWE) == MPU_WP_MPUWE)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup MPU_Global_Functions MPU Global Functions
+ * @{
+ */
+
+/**
+ * @brief De-Initialize MPU.
+ * @param None
+ * @retval None
+ */
+void MPU_DeInit(void)
+{
+ uint32_t i;
+ __IO uint32_t *RGD;
+ __IO uint32_t *RGE;
+ __IO uint32_t *RGWP;
+ __IO uint32_t *RGRP;
+ __IO uint32_t *CR;
+ __IO uint32_t *SPPBA;
+ __IO uint32_t *SPPCTL;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_UNLOCK());
+
+ for (i = 0UL; i < MPU_REGION_MAX_NUM; i++) {
+ RGD = MPU_RGD_ADDR(i);
+ WRITE_REG32(*RGD, 0UL);
+ }
+ WRITE_REG32(CM_MPU->ECLR, MPU_FLAG_ALL);
+ WRITE_REG32(CM_MPU->IPPR, 0UL);
+ for (i = 0UL; i < MPU_UNIT_MAX_NUM; i++) {
+ RGE = MPU_RGE_ADDR(i);
+ WRITE_REG32(*RGE, 0UL);
+ RGWP = MPU_RGWP_ADDR(i);
+ WRITE_REG32(*RGWP, 0UL);
+ RGRP = MPU_RGRP_ADDR(i);
+ WRITE_REG32(*RGRP, 0UL);
+ CR = MPU_CR_ADDR(i);
+ WRITE_REG32(*CR, 0UL);
+ }
+ for (i = 0UL; i < MPU_SP_UNIT_MAX_NUM; i++) {
+ SPPBA = MPU_SPPBA_ADDR(i);
+ WRITE_REG32(*SPPBA, 0UL);
+ SPPCTL = MPU_SPPCTL_ADDR(i);
+ WRITE_REG32(*SPPCTL, 0UL);
+ }
+}
+
+/**
+ * @brief Initialize MPU.
+ * @param [in] pstcMpuInit Pointer to a @ref stc_mpu_init_t structure
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t MPU_Init(const stc_mpu_init_t *pstcMpuInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcMpuInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_UNLOCK());
+ DDL_ASSERT(IS_MPU_EXP_TYPE(pstcMpuInit->stcDma1.u32ExceptionType));
+ DDL_ASSERT(IS_MPU_BACKGROUND_WR(pstcMpuInit->stcDma1.u32BackgroundWrite));
+ DDL_ASSERT(IS_MPU_BACKGROUND_RD(pstcMpuInit->stcDma1.u32BackgroundRead));
+ DDL_ASSERT(IS_MPU_EXP_TYPE(pstcMpuInit->stcDma2.u32ExceptionType));
+ DDL_ASSERT(IS_MPU_BACKGROUND_WR(pstcMpuInit->stcDma2.u32BackgroundWrite));
+ DDL_ASSERT(IS_MPU_BACKGROUND_RD(pstcMpuInit->stcDma2.u32BackgroundRead));
+ DDL_ASSERT(IS_MPU_EXP_TYPE(pstcMpuInit->stcUsbFSDma.u32ExceptionType));
+ DDL_ASSERT(IS_MPU_BACKGROUND_WR(pstcMpuInit->stcUsbFSDma.u32BackgroundWrite));
+ DDL_ASSERT(IS_MPU_BACKGROUND_RD(pstcMpuInit->stcUsbFSDma.u32BackgroundRead));
+ MODIFY_REG32(CM_MPU->S1CR, MPU_UNIT_CONFIG_MASK,
+ (pstcMpuInit->stcDma1.u32ExceptionType | pstcMpuInit->stcDma1.u32BackgroundWrite |
+ pstcMpuInit->stcDma1.u32BackgroundRead));
+ MODIFY_REG32(CM_MPU->S2CR, MPU_UNIT_CONFIG_MASK,
+ (pstcMpuInit->stcDma2.u32ExceptionType | pstcMpuInit->stcDma2.u32BackgroundWrite |
+ pstcMpuInit->stcDma2.u32BackgroundRead));
+ MODIFY_REG32(CM_MPU->FCR, MPU_UNIT_CONFIG_MASK,
+ (pstcMpuInit->stcUsbFSDma.u32ExceptionType | pstcMpuInit->stcUsbFSDma.u32BackgroundWrite |
+ pstcMpuInit->stcUsbFSDma.u32BackgroundRead));
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Fills each stc_mpu_init_t member with default value.
+ * @param [out] pstcMpuInit Pointer to a @ref stc_mpu_init_t structure
+ * @retval int32_t:
+ * - LL_OK: stc_mpu_init_t member initialize success
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t MPU_StructInit(stc_mpu_init_t *pstcMpuInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcMpuInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ pstcMpuInit->stcDma1.u32ExceptionType = MPU_EXP_TYPE_NONE;
+ pstcMpuInit->stcDma1.u32BackgroundWrite = MPU_BACKGROUND_WR_DISABLE;
+ pstcMpuInit->stcDma1.u32BackgroundRead = MPU_BACKGROUND_RD_DISABLE;
+ pstcMpuInit->stcDma2.u32ExceptionType = MPU_EXP_TYPE_NONE;
+ pstcMpuInit->stcDma2.u32BackgroundWrite = MPU_BACKGROUND_WR_DISABLE;
+ pstcMpuInit->stcDma2.u32BackgroundRead = MPU_BACKGROUND_RD_DISABLE;
+ pstcMpuInit->stcUsbFSDma.u32ExceptionType = MPU_EXP_TYPE_NONE;
+ pstcMpuInit->stcUsbFSDma.u32BackgroundWrite = MPU_BACKGROUND_WR_DISABLE;
+ pstcMpuInit->stcUsbFSDma.u32BackgroundRead = MPU_BACKGROUND_RD_DISABLE;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize MPU Unit.
+ * @param [in] u32Unit The type of MPU unit.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref MPU_Unit_Type
+ * @param [in] pstcUnitInit Pointer to a @ref stc_mpu_unit_init_t structure
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t MPU_UnitInit(uint32_t u32Unit, stc_mpu_unit_init_t *pstcUnitInit)
+{
+ __IO uint32_t *CR;
+ uint32_t u32UnitPos;
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcUnitInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_UNLOCK());
+ DDL_ASSERT(IS_MPU_INIT_UNIT(u32Unit));
+
+ u32UnitPos = __CLZ(__RBIT(u32Unit));
+
+ CR = MPU_CR_ADDR(u32UnitPos);
+ WRITE_REG32(*CR, pstcUnitInit->u32MpuState | pstcUnitInit->u32ExceptionType | \
+ pstcUnitInit->u32BackgroundWrite | pstcUnitInit->u32BackgroundRead);
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Fills each stc_mpu_unit_init_t member with default value.
+ * @param [out] pstcUnitInit Pointer to a @ref stc_mpu_unit_init_t structure
+ * @retval int32_t:
+ * - LL_OK: stc_mpu_unit_init_t member initialize success
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t MPU_UnitStructInit(stc_mpu_unit_init_t *pstcUnitInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcUnitInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ pstcUnitInit->u32MpuState = MPU_UNIT_DISABLE;
+ pstcUnitInit->u32ExceptionType = MPU_EXP_TYPE_NONE;
+ pstcUnitInit->u32BackgroundWrite = MPU_BACKGROUND_WR_DISABLE;
+ pstcUnitInit->u32BackgroundRead = MPU_BACKGROUND_RD_DISABLE;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Set the exception type of the unit.
+ * @param [in] u32Unit The type of MPU unit.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref MPU_Unit_Type
+ * @param [in] u32Type Exception type of MPU unit.
+ * This parameter can be one of the following values:
+ * @arg MPU_EXP_TYPE_NONE: The host unit access protection regions will be ignored
+ * @arg MPU_EXP_TYPE_BUS_ERR: The host unit access protection regions will be ignored and a bus error will be triggered
+ * @arg MPU_EXP_TYPE_NMI: The host unit access protection regions will be ignored and a NMI interrupt will be triggered
+ * @arg MPU_EXP_TYPE_RST: The host unit access protection regions will trigger the reset
+ * @retval None
+ */
+void MPU_SetExceptionType(uint32_t u32Unit, uint32_t u32Type)
+{
+ __IO uint32_t *CR;
+ uint32_t u32UnitPos = 0UL;
+ uint32_t u32Temp;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_UNLOCK());
+ DDL_ASSERT(IS_MPU_UNIT(u32Unit));
+ DDL_ASSERT(IS_MPU_EXP_TYPE(u32Type));
+
+ u32Temp = u32Unit;
+ while (0UL != u32Temp) {
+ if (0UL != (u32Temp & 0x1UL)) {
+ CR = MPU_CR_ADDR(u32UnitPos);
+ MODIFY_REG32(*CR, MPU_SCR_SMPUACT, u32Type);
+ }
+ u32Temp >>= 1UL;
+ u32UnitPos++;
+ }
+}
+
+/**
+ * @brief Enable or disable the write of the unit for background space.
+ * @param [in] u32Unit The type of MPU unit.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref MPU_Unit_Type
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void MPU_BackgroundWriteCmd(uint32_t u32Unit, en_functional_state_t enNewState)
+{
+ __IO uint32_t *CR;
+ uint32_t u32UnitPos = 0UL;
+ uint32_t u32Temp;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_UNLOCK());
+ DDL_ASSERT(IS_MPU_UNIT(u32Unit));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u32Temp = u32Unit;
+ while (0UL != u32Temp) {
+ if (0UL != (u32Temp & 0x1UL)) {
+ CR = MPU_CR_ADDR(u32UnitPos);
+ if (DISABLE != enNewState) {
+ CLR_REG32_BIT(*CR, MPU_SCR_SMPUBWP);
+ } else {
+ SET_REG32_BIT(*CR, MPU_SCR_SMPUBWP);
+ }
+ }
+ u32Temp >>= 1UL;
+ u32UnitPos++;
+ }
+}
+
+/**
+ * @brief Enable or disable the read of the unit for background space.
+ * @param [in] u32Unit The type of MPU unit.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref MPU_Unit_Type
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void MPU_BackgroundReadCmd(uint32_t u32Unit, en_functional_state_t enNewState)
+{
+ __IO uint32_t *CR;
+ uint32_t u32UnitPos = 0UL;
+ uint32_t u32Temp;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_UNLOCK());
+ DDL_ASSERT(IS_MPU_UNIT(u32Unit));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u32Temp = u32Unit;
+ while (0UL != u32Temp) {
+ if (0UL != (u32Temp & 0x1UL)) {
+ CR = MPU_CR_ADDR(u32UnitPos);
+ if (DISABLE != enNewState) {
+ CLR_REG32_BIT(*CR, MPU_SCR_SMPUBRP);
+ } else {
+ SET_REG32_BIT(*CR, MPU_SCR_SMPUBRP);
+ }
+ }
+ u32Temp >>= 1UL;
+ u32UnitPos++;
+ }
+}
+
+/**
+ * @brief Enable or disable the access control of the unit.
+ * @param [in] u32Unit The type of MPU unit.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref MPU_Unit_Type
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void MPU_UnitCmd(uint32_t u32Unit, en_functional_state_t enNewState)
+{
+ __IO uint32_t *CR;
+ uint32_t u32UnitPos = 0UL;
+ uint32_t u32Temp;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_UNLOCK());
+ DDL_ASSERT(IS_MPU_UNIT(u32Unit));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u32Temp = u32Unit;
+ while (0UL != u32Temp) {
+ if (0UL != (u32Temp & 0x1UL)) {
+ CR = MPU_CR_ADDR(u32UnitPos);
+ if (DISABLE != enNewState) {
+ SET_REG32_BIT(*CR, MPU_SCR_SMPUE);
+ } else {
+ CLR_REG32_BIT(*CR, MPU_SCR_SMPUE);
+ }
+ }
+ u32Temp >>= 1UL;
+ u32UnitPos++;
+ }
+}
+
+/**
+ * @brief Gets the status of MPU flag.
+ * @param [in] u32Flag The type of MPU flag.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref MPU_Flag
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t MPU_GetStatus(uint32_t u32Flag)
+{
+ en_flag_status_t enFlagSta = RESET;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_FLAG(u32Flag));
+
+ if (0UL != (READ_REG32_BIT(CM_MPU->SR, u32Flag))) {
+ enFlagSta = SET;
+ }
+
+ return enFlagSta;
+}
+
+/**
+ * @brief Clear the flag of MPU.
+ * @param [in] u32Flag The type of MPU flag.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref MPU_Flag
+ * @retval None
+ */
+void MPU_ClearStatus(uint32_t u32Flag)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_FLAG(u32Flag));
+
+ WRITE_REG32(CM_MPU->ECLR, u32Flag);
+}
+
+/**
+ * @brief Initialize the region.
+ * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'.
+ * @note The effective bits of the 'u32BaseAddr' are related to the 'u32Size' of the region,
+ * and the low 'u32Size+1' bits are fixed at 0.
+ * @param [in] u32Num The number of the region.
+ * This parameter can be one of the following values:
+ * @arg MPU_REGION_NUM0: MPU region number 0
+ * @arg MPU_REGION_NUM1: MPU region number 1
+ * @arg MPU_REGION_NUM2: MPU region number 2
+ * @arg MPU_REGION_NUM3: MPU region number 3
+ * @arg MPU_REGION_NUM4: MPU region number 4
+ * @arg MPU_REGION_NUM5: MPU region number 5
+ * @arg MPU_REGION_NUM6: MPU region number 6
+ * @arg MPU_REGION_NUM7: MPU region number 7
+ * @arg MPU_REGION_NUM8: MPU region number 8
+ * @arg MPU_REGION_NUM9: MPU region number 9
+ * @arg MPU_REGION_NUM10: MPU region number 10
+ * @arg MPU_REGION_NUM11: MPU region number 11
+ * @arg MPU_REGION_NUM12: MPU region number 12
+ * @arg MPU_REGION_NUM13: MPU region number 13
+ * @arg MPU_REGION_NUM14: MPU region number 14
+ * @arg MPU_REGION_NUM15: MPU region number 15
+ * @param [in] pstcRegionInit Pointer to a @ref stc_mpu_region_init_t structure
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t MPU_RegionInit(uint32_t u32Num, const stc_mpu_region_init_t *pstcRegionInit)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t *RGD;
+ __IO uint32_t *RGWP;
+ __IO uint32_t *RGRP;
+ uint32_t i;
+ uint32_t u32UnitNum = MPU_UNIT_MAX_NUM;
+ stc_mpu_region_permission_t RegionBuffer[MPU_UNIT_MAX_NUM];
+
+ if (NULL == pstcRegionInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_UNLOCK());
+ DDL_ASSERT(IS_MPU_REGION(u32Num));
+ DDL_ASSERT(IS_MPU_REGION_SIZE(pstcRegionInit->u32Size));
+ DDL_ASSERT(IS_MPU_REGION_BASE_ADDER(pstcRegionInit->u32BaseAddr, pstcRegionInit->u32Size));
+ DDL_ASSERT(IS_MPU_REGION_WR(pstcRegionInit->stcDma1.u32RegionWrite));
+ DDL_ASSERT(IS_MPU_REGION_RD(pstcRegionInit->stcDma1.u32RegionRead));
+ DDL_ASSERT(IS_MPU_REGION_WR(pstcRegionInit->stcDma2.u32RegionWrite));
+ DDL_ASSERT(IS_MPU_REGION_RD(pstcRegionInit->stcDma2.u32RegionRead));
+ DDL_ASSERT(IS_MPU_REGION_WR(pstcRegionInit->stcUsbFSDma.u32RegionWrite));
+ DDL_ASSERT(IS_MPU_REGION_RD(pstcRegionInit->stcUsbFSDma.u32RegionRead));
+
+ RGD = MPU_RGD_ADDR(u32Num);
+ WRITE_REG32(*RGD, (pstcRegionInit->u32Size | pstcRegionInit->u32BaseAddr));
+ /* Configure the read/write permission for the region */
+ RegionBuffer[0] = pstcRegionInit->stcDma1;
+ RegionBuffer[1] = pstcRegionInit->stcDma2;
+ RegionBuffer[2] = pstcRegionInit->stcUsbFSDma;
+ if ((u32Num >= MPU_REGION_NUM8) && (u32Num <= MPU_REGION_NUM15)) {
+ u32UnitNum = 2UL;
+ }
+ for (i = 0UL; i < u32UnitNum; i++) {
+ /* Configure the write permission for the region */
+ RGWP = MPU_RGWP_ADDR(i);
+ if (MPU_REGION_WR_DISABLE != RegionBuffer[i].u32RegionWrite) {
+ CLR_REG32_BIT(*RGWP, (0x1UL << u32Num));
+ } else {
+ SET_REG32_BIT(*RGWP, (0x1UL << u32Num));
+ }
+ /* Configure the read permission for the region */
+ RGRP = MPU_RGRP_ADDR(i);
+ if (MPU_REGION_WR_DISABLE != RegionBuffer[i].u32RegionRead) {
+ CLR_REG32_BIT(*RGRP, (0x1UL << u32Num));
+ } else {
+ SET_REG32_BIT(*RGRP, (0x1UL << u32Num));
+ }
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Fills each stc_mpu_region_init_t member with default value.
+ * @param [out] pstcRegionInit Pointer to a @ref stc_mpu_region_init_t structure
+ * @retval int32_t:
+ * - LL_OK: stc_mpu_region_init_t member initialize success
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t MPU_RegionStructInit(stc_mpu_region_init_t *pstcRegionInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcRegionInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ pstcRegionInit->u32BaseAddr = 0UL;
+ pstcRegionInit->u32Size = MPU_REGION_SIZE_32BYTE;
+ pstcRegionInit->stcDma1.u32RegionWrite = MPU_REGION_WR_DISABLE;
+ pstcRegionInit->stcDma1.u32RegionRead = MPU_REGION_RD_DISABLE;
+ pstcRegionInit->stcDma2.u32RegionWrite = MPU_REGION_WR_DISABLE;
+ pstcRegionInit->stcDma2.u32RegionRead = MPU_REGION_RD_DISABLE;
+ pstcRegionInit->stcUsbFSDma.u32RegionWrite = MPU_REGION_WR_DISABLE;
+ pstcRegionInit->stcUsbFSDma.u32RegionRead = MPU_REGION_RD_DISABLE;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set the base address of the region.
+ * @note The effective bits of the 'u32Addr' are related to the 'size' of the region,
+ * and the low 'size+1' bits are fixed at 0.
+ * @param [in] u32Num The number of the region.
+ * This parameter can be one of the following values:
+ * @arg MPU_REGION_NUM0: MPU region number 0
+ * @arg MPU_REGION_NUM1: MPU region number 1
+ * @arg MPU_REGION_NUM2: MPU region number 2
+ * @arg MPU_REGION_NUM3: MPU region number 3
+ * @arg MPU_REGION_NUM4: MPU region number 4
+ * @arg MPU_REGION_NUM5: MPU region number 5
+ * @arg MPU_REGION_NUM6: MPU region number 6
+ * @arg MPU_REGION_NUM7: MPU region number 7
+ * @arg MPU_REGION_NUM8: MPU region number 8
+ * @arg MPU_REGION_NUM9: MPU region number 9
+ * @arg MPU_REGION_NUM10: MPU region number 10
+ * @arg MPU_REGION_NUM11: MPU region number 11
+ * @arg MPU_REGION_NUM12: MPU region number 12
+ * @arg MPU_REGION_NUM13: MPU region number 13
+ * @arg MPU_REGION_NUM14: MPU region number 14
+ * @arg MPU_REGION_NUM15: MPU region number 15
+ * @param [in] u32Addr The base address of the region.
+ * @retval None
+ */
+void MPU_SetRegionBaseAddr(uint32_t u32Num, uint32_t u32Addr)
+{
+ __IO uint32_t *RGD;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_UNLOCK());
+ DDL_ASSERT(IS_MPU_REGION(u32Num));
+
+ RGD = MPU_RGD_ADDR(u32Num);
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_REGION_BASE_ADDER(u32Addr, READ_REG32_BIT(*RGD, MPU_RGD_MPURGSIZE)));
+
+ MODIFY_REG32(*RGD, MPU_RGD_MPURGADDR, u32Addr);
+}
+
+/**
+ * @brief Set the size of the region.
+ * @param [in] u32Num The number of the region.
+ * This parameter can be one of the following values:
+ * @arg MPU_REGION_NUM0: MPU region number 0
+ * @arg MPU_REGION_NUM1: MPU region number 1
+ * @arg MPU_REGION_NUM2: MPU region number 2
+ * @arg MPU_REGION_NUM3: MPU region number 3
+ * @arg MPU_REGION_NUM4: MPU region number 4
+ * @arg MPU_REGION_NUM5: MPU region number 5
+ * @arg MPU_REGION_NUM6: MPU region number 6
+ * @arg MPU_REGION_NUM7: MPU region number 7
+ * @arg MPU_REGION_NUM8: MPU region number 8
+ * @arg MPU_REGION_NUM9: MPU region number 9
+ * @arg MPU_REGION_NUM10: MPU region number 10
+ * @arg MPU_REGION_NUM11: MPU region number 11
+ * @arg MPU_REGION_NUM12: MPU region number 12
+ * @arg MPU_REGION_NUM13: MPU region number 13
+ * @arg MPU_REGION_NUM14: MPU region number 14
+ * @arg MPU_REGION_NUM15: MPU region number 15
+ * @param [in] u32Size The size of the region.
+ * This parameter can be one of the following values:
+ * @arg MPU_REGION_SIZE_32BYTE: 32 Byte
+ * @arg MPU_REGION_SIZE_64BYTE: 64 Byte
+ * @arg MPU_REGION_SIZE_128BYTE: 126 Byte
+ * @arg MPU_REGION_SIZE_256BYTE: 256 Byte
+ * @arg MPU_REGION_SIZE_512BYTE: 512 Byte
+ * @arg MPU_REGION_SIZE_1KBYTE: 1K Byte
+ * @arg MPU_REGION_SIZE_2KBYTE: 2K Byte
+ * @arg MPU_REGION_SIZE_4KBYTE: 4K Byte
+ * @arg MPU_REGION_SIZE_8KBYTE: 8K Byte
+ * @arg MPU_REGION_SIZE_16KBYTE: 16K Byte
+ * @arg MPU_REGION_SIZE_32KBYTE: 32K Byte
+ * @arg MPU_REGION_SIZE_64KBYTE: 64K Byte
+ * @arg MPU_REGION_SIZE_128KBYTE: 128K Byte
+ * @arg MPU_REGION_SIZE_256KBYTE: 256K Byte
+ * @arg MPU_REGION_SIZE_512KBYTE: 512K Byte
+ * @arg MPU_REGION_SIZE_1MBYTE: 1M Byte
+ * @arg MPU_REGION_SIZE_2MBYTE: 2M Byte
+ * @arg MPU_REGION_SIZE_4MBYTE: 4M Byte
+ * @arg MPU_REGION_SIZE_8MBYTE: 8M Byte
+ * @arg MPU_REGION_SIZE_16MBYTE: 16M Byte
+ * @arg MPU_REGION_SIZE_32MBYTE: 32M Byte
+ * @arg MPU_REGION_SIZE_64MBYTE: 64M Byte
+ * @arg MPU_REGION_SIZE_128MBYTE: 128M Byte
+ * @arg MPU_REGION_SIZE_256MBYTE: 256M Byte
+ * @arg MPU_REGION_SIZE_512MBYTE: 512M Byte
+ * @arg MPU_REGION_SIZE_1GBYTE: 1G Byte
+ * @arg MPU_REGION_SIZE_2GBYTE: 2G Byte
+ * @arg MPU_REGION_SIZE_4GBYTE: 4G Byte
+ * @retval None
+ */
+void MPU_SetRegionSize(uint32_t u32Num, uint32_t u32Size)
+{
+ __IO uint32_t *RGD;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_UNLOCK());
+ DDL_ASSERT(IS_MPU_REGION(u32Num));
+ DDL_ASSERT(IS_MPU_REGION_SIZE(u32Size));
+
+ RGD = MPU_RGD_ADDR(u32Num);
+ MODIFY_REG32(*RGD, MPU_RGD_MPURGSIZE, u32Size);
+}
+
+/**
+ * @brief Enable or disable the write of the unit for the region.
+ * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'.
+ * @param [in] u32Num The number of the region.
+ * This parameter can be one of the following values:
+ * @arg MPU_REGION_NUM0: MPU region number 0
+ * @arg MPU_REGION_NUM1: MPU region number 1
+ * @arg MPU_REGION_NUM2: MPU region number 2
+ * @arg MPU_REGION_NUM3: MPU region number 3
+ * @arg MPU_REGION_NUM4: MPU region number 4
+ * @arg MPU_REGION_NUM5: MPU region number 5
+ * @arg MPU_REGION_NUM6: MPU region number 6
+ * @arg MPU_REGION_NUM7: MPU region number 7
+ * @arg MPU_REGION_NUM8: MPU region number 8
+ * @arg MPU_REGION_NUM9: MPU region number 9
+ * @arg MPU_REGION_NUM10: MPU region number 10
+ * @arg MPU_REGION_NUM11: MPU region number 11
+ * @arg MPU_REGION_NUM12: MPU region number 12
+ * @arg MPU_REGION_NUM13: MPU region number 13
+ * @arg MPU_REGION_NUM14: MPU region number 14
+ * @arg MPU_REGION_NUM15: MPU region number 15
+ * @param [in] u32Unit The type of MPU unit.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref MPU_Unit_Type
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void MPU_RegionWriteCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState)
+{
+ __IO uint32_t *RGWP;
+ uint32_t u32UnitPos = 0UL;
+ uint32_t u32Temp;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_UNLOCK());
+ DDL_ASSERT(IS_MPU_REGION(u32Num));
+ DDL_ASSERT(IS_MPU_UNIT(u32Unit));
+ DDL_ASSERT(IS_MPU_UNIT_REGION(u32Unit, u32Num));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u32Temp = u32Unit;
+ while (0UL != u32Temp) {
+ if (0UL != (u32Temp & 0x1UL)) {
+ /* Configure the write permission for the region */
+ RGWP = MPU_RGWP_ADDR(u32UnitPos);
+ if (DISABLE != enNewState) {
+ CLR_REG32_BIT(*RGWP, (0x1UL << u32Num));
+ } else {
+ SET_REG32_BIT(*RGWP, (0x1UL << u32Num));
+ }
+ }
+ u32Temp >>= 1UL;
+ u32UnitPos++;
+ }
+}
+
+/**
+ * @brief Enable or disable the read of the unit for the region.
+ * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'.
+ * @param [in] u32Num The number of the region.
+ * This parameter can be one of the following values:
+ * @arg MPU_REGION_NUM0: MPU region number 0
+ * @arg MPU_REGION_NUM1: MPU region number 1
+ * @arg MPU_REGION_NUM2: MPU region number 2
+ * @arg MPU_REGION_NUM3: MPU region number 3
+ * @arg MPU_REGION_NUM4: MPU region number 4
+ * @arg MPU_REGION_NUM5: MPU region number 5
+ * @arg MPU_REGION_NUM6: MPU region number 6
+ * @arg MPU_REGION_NUM7: MPU region number 7
+ * @arg MPU_REGION_NUM8: MPU region number 8
+ * @arg MPU_REGION_NUM9: MPU region number 9
+ * @arg MPU_REGION_NUM10: MPU region number 10
+ * @arg MPU_REGION_NUM11: MPU region number 11
+ * @arg MPU_REGION_NUM12: MPU region number 12
+ * @arg MPU_REGION_NUM13: MPU region number 13
+ * @arg MPU_REGION_NUM14: MPU region number 14
+ * @arg MPU_REGION_NUM15: MPU region number 15
+ * @param [in] u32Unit The type of MPU unit.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref MPU_Unit_Type
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void MPU_RegionReadCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState)
+{
+ __IO uint32_t *RGRP;
+ uint32_t u32UnitPos = 0UL;
+ uint32_t u32Temp;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_UNLOCK());
+ DDL_ASSERT(IS_MPU_REGION(u32Num));
+ DDL_ASSERT(IS_MPU_UNIT(u32Unit));
+ DDL_ASSERT(IS_MPU_UNIT_REGION(u32Unit, u32Num));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u32Temp = u32Unit;
+ while (0UL != u32Temp) {
+ if (0UL != (u32Temp & 0x1UL)) {
+ /* Configure the read permission for the region */
+ RGRP = MPU_RGRP_ADDR(u32UnitPos);
+ if (DISABLE != enNewState) {
+ CLR_REG32_BIT(*RGRP, (0x1UL << u32Num));
+ } else {
+ SET_REG32_BIT(*RGRP, (0x1UL << u32Num));
+ }
+ }
+ u32Temp >>= 1UL;
+ u32UnitPos++;
+ }
+}
+
+/**
+ * @brief Enable or disable the access control of the unit for the region.
+ * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'.
+ * @param [in] u32Num The number of the region.
+ * This parameter can be one of the following values:
+ * @arg MPU_REGION_NUM0: MPU region number 0
+ * @arg MPU_REGION_NUM1: MPU region number 1
+ * @arg MPU_REGION_NUM2: MPU region number 2
+ * @arg MPU_REGION_NUM3: MPU region number 3
+ * @arg MPU_REGION_NUM4: MPU region number 4
+ * @arg MPU_REGION_NUM5: MPU region number 5
+ * @arg MPU_REGION_NUM6: MPU region number 6
+ * @arg MPU_REGION_NUM7: MPU region number 7
+ * @arg MPU_REGION_NUM8: MPU region number 8
+ * @arg MPU_REGION_NUM9: MPU region number 9
+ * @arg MPU_REGION_NUM10: MPU region number 10
+ * @arg MPU_REGION_NUM11: MPU region number 11
+ * @arg MPU_REGION_NUM12: MPU region number 12
+ * @arg MPU_REGION_NUM13: MPU region number 13
+ * @arg MPU_REGION_NUM14: MPU region number 14
+ * @arg MPU_REGION_NUM15: MPU region number 15
+ * @param [in] u32Unit The type of MPU unit.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref MPU_Unit_Type
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void MPU_RegionCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState)
+{
+ __IO uint32_t *RGE;
+ uint32_t u32UnitPos = 0UL;
+ uint32_t u32Temp;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_UNLOCK());
+ DDL_ASSERT(IS_MPU_REGION(u32Num));
+ DDL_ASSERT(IS_MPU_UNIT(u32Unit));
+ DDL_ASSERT(IS_MPU_UNIT_REGION(u32Unit, u32Num));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u32Temp = u32Unit;
+ while (0UL != u32Temp) {
+ if (0UL != (u32Temp & 0x1UL)) {
+ RGE = MPU_RGE_ADDR(u32UnitPos);
+ if (DISABLE != enNewState) {
+ SET_REG32_BIT(*RGE, (0x1UL << u32Num));
+ } else {
+ CLR_REG32_BIT(*RGE, (0x1UL << u32Num));
+ }
+ }
+ u32Temp >>= 1UL;
+ u32UnitPos++;
+ }
+}
+
+/**
+ * @brief Initialize the SP unit of MPU.
+ * @param [in] u32Unit The type of MPU SP unit.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref MPU_SP_Unit_Type
+ * @param [in] pstcSpInit Pointer to a @ref stc_mpu_sp_init_t structure
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t MPU_SPInit(uint32_t u32Unit, const stc_mpu_sp_init_t *pstcSpInit)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t *SPPBA;
+ __IO uint32_t *SPPCTL;
+ uint32_t u32UnitPos = 0UL;
+ uint32_t u32Temp;
+
+ if (NULL == pstcSpInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_UNLOCK());
+ DDL_ASSERT(IS_MPU_SP_UNIT(u32Unit));
+ DDL_ASSERT(IS_MPU_SP_EXP_TYPE(pstcSpInit->u32ExceptionType));
+ DDL_ASSERT(IS_MPU_SP_START_ADDR(pstcSpInit->u32Addr));
+ DDL_ASSERT(IS_MPU_SP_ADDR_SIZE(pstcSpInit->u32Size));
+ DDL_ASSERT(IS_ADDR_ALIGN_WORD(pstcSpInit->u32Addr));
+ DDL_ASSERT(IS_ADDR_ALIGN_WORD(pstcSpInit->u32Size));
+
+ u32Temp = u32Unit;
+ while (0UL != u32Temp) {
+ if (0UL != (u32Temp & 0x1UL)) {
+ SPPBA = MPU_SPPBA_ADDR(u32UnitPos);
+ WRITE_REG32(*SPPBA, pstcSpInit->u32Addr & MPU_PSPPBA_PSPPBA);
+ SPPCTL = MPU_SPPCTL_ADDR(u32UnitPos);
+ MODIFY_REG32(*SPPCTL, (MPU_MSPPCTL_MSPPACT | MPU_MSPPCTL_MSPPSIZE),
+ (pstcSpInit->u32ExceptionType | (pstcSpInit->u32Size - 1U)));
+ }
+ u32Temp >>= 1UL;
+ u32UnitPos++;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Fills each stc_mpu_sp_init_t member with default value.
+ * @param [out] pstcSpInit Pointer to a @ref stc_mpu_sp_init_t structure
+ * @retval int32_t:
+ * - LL_OK: stc_mpu_sp_init_t member initialize success
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t MPU_SPStructInit(stc_mpu_sp_init_t *pstcSpInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcSpInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ pstcSpInit->u32ExceptionType = MPU_SP_EXP_TYPE_NMI;
+ pstcSpInit->u32Addr = 0UL;
+ pstcSpInit->u32Size = 0x04UL;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set the start address of the SP.
+ * @param [in] u32Unit The type of MPU SP unit.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref MPU_SP_Unit_Type
+ * @param [in] u32Addr The start address of the SP.
+ This parameter can be a number between 0UL and 0xFFFFFFFCUL.
+ * @retval None
+ */
+void MPU_SetSPStartAddr(uint32_t u32Unit, uint32_t u32Addr)
+{
+ __IO uint32_t *SPPBA;
+ uint32_t u32UnitPos = 0UL;
+ uint32_t u32Temp;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_UNLOCK());
+ DDL_ASSERT(IS_MPU_SP_UNIT(u32Unit));
+ DDL_ASSERT(IS_MPU_SP_START_ADDR(u32Addr));
+ DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr));
+
+ u32Temp = u32Unit;
+ while (0UL != u32Temp) {
+ if (0UL != (u32Temp & 0x1UL)) {
+ SPPBA = MPU_SPPBA_ADDR(u32UnitPos);
+ WRITE_REG32(*SPPBA, u32Addr & MPU_PSPPBA_PSPPBA);
+ }
+ u32Temp >>= 1UL;
+ u32UnitPos++;
+ }
+}
+
+/**
+ * @brief Set the address size of the SP.
+ * @param [in] u32Unit The type of MPU SP unit.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref MPU_SP_Unit_Type
+ * @param [in] u32Size The size of the SP.
+ * This parameter can be a number between 4UL and 65536UL.
+ * @retval None
+ */
+void MPU_SetSPSize(uint32_t u32Unit, uint32_t u32Size)
+{
+ __IO uint32_t *SPPCTL;
+ uint32_t u32UnitPos = 0UL;
+ uint32_t u32Temp;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_UNLOCK());
+ DDL_ASSERT(IS_MPU_SP_UNIT(u32Unit));
+ DDL_ASSERT(IS_MPU_SP_ADDR_SIZE(u32Size));
+ DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Size));
+
+ u32Temp = u32Unit;
+ while (0UL != u32Temp) {
+ if (0UL != (u32Temp & 0x1UL)) {
+ SPPCTL = MPU_SPPCTL_ADDR(u32UnitPos);
+ MODIFY_REG32(*SPPCTL, MPU_MSPPCTL_MSPPSIZE, (u32Size - 1U));
+ }
+ u32Temp >>= 1UL;
+ u32UnitPos++;
+ }
+}
+
+/**
+ * @brief Set the exception type of the SP.
+ * @param [in] u32Unit The type of MPU SP unit.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref MPU_SP_Unit_Type
+ * @param [in] u32Type Exception type of MPU SP unit.
+ * This parameter can be one of the following values:
+ * @arg MPU_SP_EXP_TYPE_NMI: The SP access outside specified range will trigger a NMI interrupt.
+ * @arg MPU_SP_EXP_TYPE_RST: The SP access outside specified range will trigger a reset.
+ * @retval None
+ */
+void MPU_SetSPExceptionType(uint32_t u32Unit, uint32_t u32Type)
+{
+ __IO uint32_t *SPPCTL;
+ uint32_t u32UnitPos = 0UL;
+ uint32_t u32Temp;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_UNLOCK());
+ DDL_ASSERT(IS_MPU_SP_UNIT(u32Unit));
+ DDL_ASSERT(IS_MPU_SP_EXP_TYPE(u32Type));
+
+ u32Temp = u32Unit;
+ while (0UL != u32Temp) {
+ if (0UL != (u32Temp & 0x1UL)) {
+ SPPCTL = MPU_SPPCTL_ADDR(u32UnitPos);
+ MODIFY_REG32(*SPPCTL, MPU_MSPPCTL_MSPPACT, u32Type);
+ }
+ u32Temp >>= 1UL;
+ u32UnitPos++;
+ }
+}
+
+/**
+ * @brief Enable or disable the access control of the unit for the SP.
+ * @param [in] u32Unit The type of MPU SP unit.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref MPU_SP_Unit_Type
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void MPU_SPCmd(uint32_t u32Unit, en_functional_state_t enNewState)
+{
+ __IO uint32_t *SPPCTL;
+ uint32_t u32UnitPos = 0UL;
+ uint32_t u32Temp;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_UNLOCK());
+ DDL_ASSERT(IS_MPU_SP_UNIT(u32Unit));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u32Temp = u32Unit;
+ while (0UL != u32Temp) {
+ if (0UL != (u32Temp & 0x1UL)) {
+ SPPCTL = MPU_SPPCTL_ADDR(u32UnitPos);
+ if (DISABLE != enNewState) {
+ SET_REG32_BIT(*SPPCTL, MPU_MSPPCTL_MSPPE);
+ } else {
+ CLR_REG32_BIT(*SPPCTL, MPU_MSPPCTL_MSPPE);
+ }
+
+ }
+ u32Temp >>= 1UL;
+ u32UnitPos++;
+ }
+}
+
+/**
+ * @brief Set the type of exception to access the protected IP.
+ * @param [in] u32Type Exception type of MPU IP.
+ * This parameter can be one of the following values:
+ * @arg MPU_IP_EXP_TYPE_NONE: Access to the protected IP will be ignored
+ * @arg MPU_IP_EXP_TYPE_BUS_ERR: Access to the protected IP will trigger a bus error
+ * @retval None
+ */
+void MPU_IP_SetExceptionType(uint32_t u32Type)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_UNLOCK());
+ DDL_ASSERT(IS_MPU_IP_EXP_TYPE(u32Type));
+
+ WRITE_REG32(bCM_MPU->IPPR_b.BUSERRE, (u32Type >> MPU_IPPR_BUSERRE_POS));
+}
+
+/**
+ * @brief Enable or disable write for the IP.
+ * @param [in] u32Periph The peripheral of the chip.
+ * This parameter can be one or any combination of the following values:
+ * @arg MPU_IP_AES: AES module
+ * @arg MPU_IP_HASH: HASH module
+ * @arg MPU_IP_TRNG: TRNG module
+ * @arg MPU_IP_CRC: CRC module
+ * @arg MPU_IP_EFM: EFM module
+ * @arg MPU_IP_WDT: WDT module
+ * @arg MPU_IP_SWDT: SWDT module
+ * @arg MPU_IP_BKSRAM: BKSRAM module
+ * @arg MPU_IP_RTC: RTC module
+ * @arg MPU_IP_MPU: MPU module
+ * @arg MPU_IP_SRAMC: SRAMC module
+ * @arg MPU_IP_INTC: INTC module
+ * @arg MPU_IP_RMU_CMU_PWC: RMU, CMU and PWC modules
+ * @arg MPU_IP_FCG: PWR_FCG0/1/2/3 and PWR_FCG0PC registers
+ * @arg MPU_IP_ALL: All of the above
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void MPU_IP_WriteCmd(uint32_t u32Periph, en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_UNLOCK());
+ DDL_ASSERT(IS_MPU_IP_TYPE(u32Periph));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (DISABLE != enNewState) {
+ CLR_REG32_BIT(CM_MPU->IPPR, (u32Periph << 1U));
+ } else {
+ SET_REG32_BIT(CM_MPU->IPPR, (u32Periph << 1U));
+ }
+}
+
+/**
+ * @brief Enable or disable read for the IP.
+ * @param [in] u32Periph The peripheral of the chip.
+ * This parameter can be one or any combination of the following values:
+ * @arg MPU_IP_AES: AES module
+ * @arg MPU_IP_HASH: HASH module
+ * @arg MPU_IP_TRNG: TRNG module
+ * @arg MPU_IP_CRC: CRC module
+ * @arg MPU_IP_EFM: EFM module
+ * @arg MPU_IP_WDT: WDT module
+ * @arg MPU_IP_SWDT: SWDT module
+ * @arg MPU_IP_BKSRAM: BKSRAM module
+ * @arg MPU_IP_RTC: RTC module
+ * @arg MPU_IP_MPU: MPU module
+ * @arg MPU_IP_SRAMC: SRAMC module
+ * @arg MPU_IP_INTC: INTC module
+ * @arg MPU_IP_RMU_CMU_PWC: RMU, CMU and PWC modules
+ * @arg MPU_IP_FCG: PWR_FCG0/1/2/3 and PWR_FCG0PC registers
+ * @arg MPU_IP_ALL: All of the above
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void MPU_IP_ReadCmd(uint32_t u32Periph, en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_MPU_UNLOCK());
+ DDL_ASSERT(IS_MPU_IP_TYPE(u32Periph));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (DISABLE != enNewState) {
+ CLR_REG32_BIT(CM_MPU->IPPR, u32Periph);
+ } else {
+ SET_REG32_BIT(CM_MPU->IPPR, u32Periph);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_MPU_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_ots.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_ots.c
new file mode 100644
index 0000000000..38004be21f
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_ots.c
@@ -0,0 +1,419 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_ots.c
+ * @brief This file provides firmware functions to manage the OTS.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Modify API OTS_DeInit()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_ots.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_OTS OTS
+ * @brief OTS Driver Library
+ * @{
+ */
+
+#if (LL_OTS_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup OTS_Local_Macros OTS Local Macros
+ * @{
+ */
+
+#define OTS_RMU_TIMEOUT (100UL)
+
+/**
+ * @defgroup OTS_Configuration_Bit_Mask OTS Configuration Bit Mask
+ * @{
+ */
+#define OTS_CTL_INIT_MSK (OTS_CTL_OTSCK | OTS_CTL_TSSTP)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup OTS_Ext_Reg_Address OTS Extension Register Address
+ * @{
+ */
+#define OTS_PDR1_ADDR ((uint32_t)(&CM_OTS->PDR1))
+#define OTS_PDR2_ADDR ((uint32_t)(&CM_OTS->PDR2))
+#define OTS_PDR3_ADDR ((uint32_t)(&CM_OTS->PDR3))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup OTS_Factor OTS Factor
+ * @{
+ */
+#define OTS_DR1_FACTOR (1.7F)
+
+#define OTS_DR2_FACTOR (1.0F)
+#define OTS_ECR_XTAL_FACTOR (1.0F)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup OTS_Check_Parameters_Validity OTS check parameters validity
+ * @{
+ */
+#define IS_OTS_CLK(x) (((x) == OTS_CLK_HRC) || ((x) == OTS_CLK_XTAL))
+
+#define IS_OTS_AUTO_OFF_EN(x) (((x) == OTS_AUTO_OFF_DISABLE) || ((x) == OTS_AUTO_OFF_ENABLE))
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+/**
+ * @defgroup OTS_Local_Variables OTS Local Variables
+ * @{
+ */
+static float32_t m_f32SlopeK = 0.0F;
+static float32_t m_f32OffsetM = 0.0F;
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @addtogroup OTS_Local_Functions OTS Local Functions
+ * @{
+ */
+/**
+ * @brief Get built-in slope K and offset M.
+ * @param [in] pstcOTSInit Pointer to a stc_ots_init_t structure value that
+ * contains the configuration information for OTS.
+ * @retval None
+ */
+static void OTS_GetDfltPara(const stc_ots_init_t *pstcOTSInit)
+{
+#define OTS_SCAL_T1 (ai8Temp[pstcOTSInit->stcParaCond.u8T1])
+#define OTS_SCAL_T2 (ai8Temp[pstcOTSInit->stcParaCond.u8T2])
+#define OTS_SCAL_A1 (af32A[0U])
+#define OTS_SCAL_A2 (af32A[1U])
+
+ uint8_t i;
+ int8_t ai8Temp[] = {-40, 25, 125};
+ uint32_t au32PDRAddr[3U];
+ uint32_t au32PDR[2U];
+ uint16_t u16D1;
+ uint16_t u16D2;
+ uint32_t u32PDRAddrT1;
+ uint32_t u32PDRAddrT2;
+ float32_t f32D1;
+ float32_t f32D2;
+ float32_t af32A[2U];
+ float32_t f32Ehrc = OTS_ECR_XTAL_FACTOR;
+ float32_t f32ClkFactor = (float32_t)pstcOTSInit->stcParaCond.u16ClockFreq / 8.0F;
+
+ /* Intermediate variables: avoid misrac2012-13.2_c, 13.1 */
+ au32PDRAddr[0U] = OTS_PDR3_ADDR;
+ au32PDRAddr[1U] = OTS_PDR1_ADDR;
+ au32PDRAddr[2U] = OTS_PDR2_ADDR;
+ u32PDRAddrT1 = au32PDRAddr[pstcOTSInit->stcParaCond.u8T1];
+ u32PDRAddrT2 = au32PDRAddr[pstcOTSInit->stcParaCond.u8T2];
+
+ au32PDR[0U] = RW_MEM32(u32PDRAddrT1);
+ au32PDR[1U] = RW_MEM32(u32PDRAddrT2);
+
+ if (pstcOTSInit->u16ClockSrc == OTS_CLK_HRC) {
+ f32Ehrc = (float32_t)pstcOTSInit->stcParaCond.u16ClockFreq / 0.032768F;
+ }
+
+ for (i = 0U; i < 2U; i++) {
+ u16D1 = (uint16_t)au32PDR[i];
+ u16D2 = (uint16_t)(au32PDR[i] >> 16U);
+ f32D1 = ((float32_t)u16D1) * f32ClkFactor;
+ f32D2 = ((float32_t)u16D2) * f32ClkFactor;
+ af32A[i] = ((OTS_DR1_FACTOR / f32D1) - (OTS_DR2_FACTOR / f32D2)) * f32Ehrc;
+ }
+ m_f32SlopeK = ((float32_t)OTS_SCAL_T2 - (float32_t)OTS_SCAL_T1) / (OTS_SCAL_A2 - OTS_SCAL_A1);
+ m_f32OffsetM = (float32_t)OTS_SCAL_T2 - (m_f32SlopeK * OTS_SCAL_A2);
+}
+/**
+ * @}
+ */
+
+/**
+ * @defgroup OTS_Global_Functions OTS Global Functions
+ * @{
+ */
+
+/**
+ * @brief Initializes OTS according to the specified parameters in the structure stc_ots_init_t.
+ * @param [in] pstcOTSInit Pointer to a stc_ots_init_t structure value that
+ * contains the configuration information for OTS.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_INVD_PARAM: pstcOTSInit == NULL.
+ */
+int32_t OTS_Init(const stc_ots_init_t *pstcOTSInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (pstcOTSInit != NULL) {
+ DDL_ASSERT(IS_OTS_CLK(pstcOTSInit->u16ClockSrc));
+ DDL_ASSERT(IS_OTS_AUTO_OFF_EN(pstcOTSInit->u16AutoOffEn));
+
+ /* Stop OTS sampling. */
+ OTS_Stop();
+ WRITE_REG16(CM_OTS->CTL, (pstcOTSInit->u16ClockSrc | pstcOTSInit->u16AutoOffEn));
+ if ((pstcOTSInit->f32SlopeK == 0.0F) && (pstcOTSInit->f32OffsetM == 0.0F)) {
+ OTS_GetDfltPara(pstcOTSInit);
+ } else {
+ m_f32SlopeK = pstcOTSInit->f32SlopeK;
+ m_f32OffsetM = pstcOTSInit->f32OffsetM;
+ }
+
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set a default value for OTS initialization structure.
+ * @param [in] pstcOTSInit Pointer to a stc_ots_init_t structure that
+ * contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_INVD_PARAM: pstcOTSInit == NULL.
+ */
+int32_t OTS_StructInit(stc_ots_init_t *pstcOTSInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (pstcOTSInit != NULL) {
+ pstcOTSInit->u16ClockSrc = OTS_CLK_HRC;
+ pstcOTSInit->f32SlopeK = 0.0F;
+ pstcOTSInit->f32OffsetM = 0.0F;
+ pstcOTSInit->u16AutoOffEn = OTS_AUTO_OFF_ENABLE;
+ pstcOTSInit->stcParaCond.u16ClockFreq = 8U;
+ pstcOTSInit->stcParaCond.u8T1 = OTS_PARAM_TEMP_COND_T25;
+ pstcOTSInit->stcParaCond.u8T2 = OTS_PARAM_TEMP_COND_T125;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief De-initializes OTS peripheral. Reset the registers of OTS.
+ * @param None
+ * @retval int32_t:
+ * - LL_OK: De-Initialize success.
+ * - LL_ERR_TIMEOUT: Timeout.
+ */
+int32_t OTS_DeInit(void)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t u32TimeOut = 0U;
+ /* Check RMU_FRST register protect */
+ DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1);
+
+ /* Reset */
+ WRITE_REG32(bCM_RMU->FRST3_b.OTS, 0UL);
+ /* Ensure reset procedure is completed */
+ while (0UL == READ_REG32(bCM_RMU->FRST3_b.OTS)) {
+ u32TimeOut++;
+ if (u32TimeOut > OTS_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Get temperature via normal mode.
+ * @param [out] pf32Temp Pointer to a float32_t type address that the temperature value to be stored.
+ * @param [in] u32Timeout Timeout value.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_TIMEOUT: Works timeout.
+ * - LL_ERR_INVD_PARAM: pf32Temp == NULL.
+ */
+int32_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout)
+{
+ __IO uint32_t u32TimeCount = u32Timeout;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (pf32Temp != NULL) {
+ i32Ret = LL_ERR_TIMEOUT;
+ OTS_Start();
+ while (u32TimeCount-- != 0U) {
+ if (READ_REG32(bCM_OTS->CTL_b.OTSST) == 0UL) {
+ *pf32Temp = OTS_CalculateTemp();
+ i32Ret = LL_OK;
+ break;
+ }
+ }
+ OTS_Stop();
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Enable or disable the OTS interrupt.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void OTS_IntCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ WRITE_REG32(bCM_OTS->CTL_b.OTSIE, enNewState);
+}
+
+/**
+ * @brief OTS scaling experiment. Get the value of the data register at the specified temperature to calculate K and M.
+ * @param [out] pu16Dr1: Pointer to an address to store the value of data register 1.
+ * @param [out] pu16Dr2: Pointer to an address to store the value of data register 2.
+ * @param [out] pu16Ecr: Pointer to an address to store the value of register ECR.
+ * @param [out] pf32A: Pointer to an address to store the parameter A.
+ * @param [in] u32Timeout: Timeout value.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_TIMEOUT: Works timeout.
+ * - LL_ERR_INVD_PARAM: If one the following cases matches:
+ * - pu16Dr1 == NULL.
+ * - pu16Dr2 == NULL.
+ * - pu16Ecr == NULL.
+ * - pf32A == NULL.
+ */
+int32_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2,
+ uint16_t *pu16Ecr, float32_t *pf32A,
+ uint32_t u32Timeout)
+{
+ float32_t f32Dr1;
+ float32_t f32Dr2;
+ float32_t f32Ecr;
+ __IO uint32_t u32TimeCount = u32Timeout;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if ((NULL != pu16Dr1) && (NULL != pu16Dr2) && \
+ (NULL != pu16Ecr) && (NULL != pf32A)) {
+ i32Ret = LL_ERR_TIMEOUT;
+ OTS_Start();
+ while (u32TimeCount-- != 0U) {
+ if (READ_REG32(bCM_OTS->CTL_b.OTSST) == 0UL) {
+ i32Ret = LL_OK;
+ break;
+ }
+ }
+ OTS_Stop();
+
+ if (i32Ret == LL_OK) {
+ *pu16Dr1 = READ_REG16(CM_OTS->DR1);
+ *pu16Dr2 = READ_REG16(CM_OTS->DR2);
+
+ f32Dr1 = (float32_t)(*pu16Dr1);
+ f32Dr2 = (float32_t)(*pu16Dr2);
+
+ if (READ_REG8_BIT(CM_OTS->CTL, OTS_CTL_OTSCK) == OTS_CLK_HRC) {
+ *pu16Ecr = READ_REG16(CM_OTS->ECR);
+ f32Ecr = (float32_t)(*pu16Ecr);
+ } else {
+ *pu16Ecr = 1U;
+ f32Ecr = OTS_ECR_XTAL_FACTOR;
+ }
+
+ if ((f32Dr1 != 0.0F) && (f32Dr2 != 0.0F) && (f32Ecr != 0.0F)) {
+ *pf32A = ((OTS_DR1_FACTOR / f32Dr1) - (OTS_DR2_FACTOR / f32Dr2)) * f32Ecr;
+ }
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Calculate the temperature value.
+ * @param None
+ * @retval A float32_t type value of temperature.
+ */
+float32_t OTS_CalculateTemp(void)
+{
+ float32_t f32Ret = -300.0F;
+ uint16_t u16Dr1 = READ_REG16(CM_OTS->DR1);
+ uint16_t u16Dr2 = READ_REG16(CM_OTS->DR2);
+ uint16_t u16Ecr = READ_REG16(CM_OTS->ECR);
+ float32_t f32Dr1 = (float32_t)u16Dr1;
+ float32_t f32Dr2 = (float32_t)u16Dr2;
+ float32_t f32Ecr = (float32_t)u16Ecr;
+
+ if (READ_REG8_BIT(CM_OTS->CTL, OTS_CTL_OTSCK) == OTS_CLK_XTAL) {
+ f32Ecr = OTS_ECR_XTAL_FACTOR;
+ }
+
+ if ((f32Dr1 != 0.0F) && (f32Dr2 != 0.0F) && (f32Ecr != 0.0F)) {
+ f32Ret = m_f32SlopeK * ((OTS_DR1_FACTOR / f32Dr1) - (OTS_DR2_FACTOR / f32Dr2)) * f32Ecr + m_f32OffsetM;
+ }
+
+ return f32Ret;
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_OTS_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_pla.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_pla.c
new file mode 100644
index 0000000000..9c2574a047
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_pla.c
@@ -0,0 +1,420 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_pla.c
+ * @brief This file provides firmware functions to manage the Programmable Logic
+ * Array(PLA).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Optimized PLA_DeInit function
+ 2023-09-30 CDT Modify API for Reference Manual Rev1.0
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_pla.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_PLA PLA
+ * @brief Programmable Logic Array
+ * @{
+ */
+
+#if (LL_PLA_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup PLA_Local_Macros PLA Local Macros
+ * @{
+ */
+
+/* PLA maximum channel */
+#define PLA_UNIT_MAX (16UL)
+
+/**
+ * @defgroup PLA_Calculate_Register_Address PLA Calculate Register Address
+ * @{
+ */
+#define PLA_MUXS_ADDR(__PLA__, __UNIT__) (__IO uint32_t*)((uint32_t)(&((__PLA__)->MUXS0)) + ((__UNIT__) * 0xCUL))
+#define PLA_LUTCTL_ADDR(__PLA__, __UNIT__) (__IO uint32_t*)((uint32_t)(&((__PLA__)->LUTCTL0)) + ((__UNIT__) * 0xCUL))
+#define PLA_CTL_ADDR(__PLA__, __UNIT__) (__IO uint32_t*)((uint32_t)(&((__PLA__)->CTL0)) + ((__UNIT__) * 0xCUL))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup PLA_Check_Parameters_Validity PLA Check Parameters Validity
+ * @{
+ */
+#define IS_PLA_PERIPH(x) ((x) == CM_PLA)
+
+#define IS_PLA_UNIT(x) \
+( ((x) != 0UL) && \
+ (((x) | PLA_UNIT_ALL) == PLA_UNIT_ALL))
+
+#define IS_PLA_MUX_CH(x) \
+( ((x) == PLA_MUX_CH0) || \
+ ((x) == PLA_MUX_CH1))
+
+#define IS_PLA_MUX_SRC(x) ((x) <= PLA_MUX_SRC_SIGNAL27)
+
+#define IS_PLA_COMB_LOGIC(x) ((x) <= 0xFFUL)
+
+#define IS_PLA_OUTPUT_SRC(x) \
+( ((x) == PLA_OUTPUT_SRC_NONE) || \
+ ((x) == PLA_OUTPUT_SRC_LUT))
+
+#define IS_PLA_INT(x) \
+( ((x) != 0UL) && \
+ (((x) | PLA_INT_ALL) == PLA_INT_ALL))
+
+#define IS_PLA_FLAG(x) \
+( ((x) != 0UL) && \
+ (((x) | PLA_FLAG_ALL) == PLA_FLAG_ALL))
+
+#define IS_PLA_PWC_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1)
+
+/* PLA reset timeout */
+#define PLA_RMU_TIMEOUT (100UL)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup PLA_Global_Functions PLA Global Functions
+ * @{
+ */
+
+/**
+ * @brief De-Initialize PLA unit base function.
+ * @param [in] PLAx Pointer to PLA unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_PLA or CM_PLAx: PLA unit instance
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_TIMEOUT: Works timeout.
+ */
+int32_t PLA_DeInit(CM_PLA_TypeDef *PLAx)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t u32TimeOut = 0U;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_PLA_PWC_UNLOCKED());
+
+ CLR_REG32_BIT(CM_RMU->FRST0, RMU_FRST0_PLA);
+ /* Ensure reset procedure is completed */
+ while (RMU_FRST0_PLA != READ_REG32_BIT(CM_RMU->FRST0, RMU_FRST0_PLA)) {
+ u32TimeOut++;
+ if (u32TimeOut > PLA_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize PLA base function.
+ * @param [in] PLAx Pointer to PLA unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_PLA or CM_PLAx: PLA unit instance
+ * @param [in] u32Unit The PLA unit.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref PLA_Unit
+ * @param [in] pstcPlaInit Pointer to a @ref stc_pla_init_t structure.
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: pstcPlaInit is NULL
+ */
+int32_t PLA_Init(CM_PLA_TypeDef *PLAx, uint32_t u32Unit, const stc_pla_init_t *pstcPlaInit)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t *LUTCTL;
+ __IO uint32_t *MUXS;
+ __IO uint32_t *CTL;
+ uint32_t u32UnitPos = 0UL;
+ uint32_t u32Temp;
+
+ if (NULL == pstcPlaInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Check parameters */
+ DDL_ASSERT(IS_PLA_PERIPH(PLAx));
+ DDL_ASSERT(IS_PLA_UNIT(u32Unit));
+ DDL_ASSERT(IS_PLA_MUX_SRC(pstcPlaInit->u32Mux0Src));
+ DDL_ASSERT(IS_PLA_MUX_SRC(pstcPlaInit->u32Mux1Src));
+ DDL_ASSERT(IS_PLA_COMB_LOGIC(pstcPlaInit->u32CombLogic));
+ DDL_ASSERT(IS_PLA_OUTPUT_SRC(pstcPlaInit->u32OutputSrc));
+
+ u32Temp = u32Unit;
+ while (0UL != u32Temp) {
+ if (0UL != (u32Temp & 0x1UL)) {
+ MUXS = PLA_MUXS_ADDR(PLAx, u32UnitPos);
+ WRITE_REG32(*MUXS, ((pstcPlaInit->u32Mux1Src & 0x0FUL) | ((pstcPlaInit->u32Mux1Src & 0x10UL) << 10U) |
+ ((pstcPlaInit->u32Mux0Src & 0x0FUL) << 4U) | ((pstcPlaInit->u32Mux0Src & 0x10UL) << 11U)));
+ LUTCTL = PLA_LUTCTL_ADDR(PLAx, u32UnitPos);
+ WRITE_REG32(*LUTCTL, pstcPlaInit->u32CombLogic);
+ CTL = PLA_CTL_ADDR(PLAx, u32UnitPos);
+ MODIFY_REG32(*CTL, PLA_CTL_OSEL, pstcPlaInit->u32OutputSrc);
+ }
+ u32Temp >>= 1UL;
+ u32UnitPos++;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set the fields of structure stc_pla_init_t to default values.
+ * @param [out] pstcPlaInit Pointer to a @ref stc_pla_init_t structure.
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: pstcPlaInit is NULL
+ */
+int32_t PLA_StructInit(stc_pla_init_t *pstcPlaInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcPlaInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ pstcPlaInit->u32Mux0Src = PLA_MUX_SRC_SIGNAL0;
+ pstcPlaInit->u32Mux1Src = PLA_MUX_SRC_SIGNAL0;
+ pstcPlaInit->u32CombLogic = 0UL;
+ pstcPlaInit->u32OutputSrc = PLA_OUTPUT_SRC_LUT;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Get output level of the PLA unit.
+ * @param [in] PLAx Pointer to PLA unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_PLA or CM_PLAx: PLA unit instance
+ * @param [in] u32Unit The PLA unit.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref PLA_Unit
+ * @retval An @ref en_functional_state_t enumeration value.
+ * - ENABLE: The PLA output high level
+ * - DISABLE: The PLA output low level
+ */
+en_functional_state_t PLA_GetOutputLevel(CM_PLA_TypeDef *PLAx, uint32_t u32Unit)
+{
+ en_functional_state_t enState = DISABLE;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_PLA_PERIPH(PLAx));
+ DDL_ASSERT(IS_PLA_UNIT(u32Unit));
+
+ if (0UL != (READ_REG32_BIT(PLAx->STAT, u32Unit))) {
+ enState = ENABLE;
+ }
+
+ return enState;
+}
+
+/**
+ * @brief Set the MUX source of the PLA unit.
+ * @param [in] PLAx Pointer to PLA unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_PLA or CM_PLAx: PLA unit instance
+ * @param [in] u32Unit The PLA unit.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref PLA_Unit
+ * @param [in] u32Ch PLA MUX channel
+ * This parameter can be one of the following values:
+ * @arg @ref PLA_MUX_Channel
+ * @param [in] u32Src Select the MUX source.
+ * This parameter can be one of the following values:
+ * @arg @ref PLA_MUX_Source
+ * @retval None
+ */
+void PLA_SetMuxSrc(CM_PLA_TypeDef *PLAx, uint32_t u32Unit, uint32_t u32Ch, uint32_t u32Src)
+{
+ __IO uint32_t *MUXS;
+ uint32_t u32UnitPos = 0UL;
+ uint32_t u32Temp;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_PLA_PERIPH(PLAx));
+ DDL_ASSERT(IS_PLA_UNIT(u32Unit));
+ DDL_ASSERT(IS_PLA_MUX_CH(u32Ch));
+ DDL_ASSERT(IS_PLA_MUX_SRC(u32Src));
+
+ u32Temp = u32Unit;
+ while (0UL != u32Temp) {
+ if (0UL != (u32Temp & 0x1UL)) {
+ MUXS = PLA_MUXS_ADDR(PLAx, u32UnitPos);
+ MODIFY_REG32(*MUXS, ((PLA_MUXS_MUX1 << (u32Ch << 2U)) | (PLA_MUXS_MUX1_4 << u32Ch)),
+ (((u32Src & 0x0FUL) << (u32Ch << 2U)) | ((u32Src & 0x10UL) << (10U + u32Ch))));
+ }
+ u32Temp >>= 1UL;
+ u32UnitPos++;
+ }
+}
+
+/**
+ * @brief Set the combinatorial logic of the PLA unit.
+ * @param [in] PLAx Pointer to PLA unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_PLA or CM_PLAx: PLA unit instance
+ * @param [in] u32Unit The PLA unit.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref PLA_Unit
+ * @param [in] u32Value Combinatorial logic value.
+ * This parameter can be a number between 0UL and 0xFFUL.
+ * @retval None
+ */
+void PLA_SetCombLogic(CM_PLA_TypeDef *PLAx, uint32_t u32Unit, uint32_t u32Value)
+{
+ __IO uint32_t *LUTCTL;
+ uint32_t u32UnitPos = 0UL;
+ uint32_t u32Temp;
+ uint32_t u32GctlVal;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_PLA_PERIPH(PLAx));
+ DDL_ASSERT(IS_PLA_UNIT(u32Unit));
+ DDL_ASSERT(IS_PLA_COMB_LOGIC(u32Value));
+
+ u32GctlVal = READ_REG32(PLAx->GCTL);
+ WRITE_REG32(PLAx->GCTL, 0UL);
+ u32Temp = u32Unit;
+ while (0UL != u32Temp) {
+ if (0UL != (u32Temp & 0x1UL)) {
+ LUTCTL = PLA_LUTCTL_ADDR(PLAx, u32UnitPos);
+ WRITE_REG32(*LUTCTL, u32Value);
+ }
+ u32Temp >>= 1UL;
+ u32UnitPos++;
+ }
+ WRITE_REG32(PLAx->GCTL, u32GctlVal);
+}
+
+/**
+ * @brief Enable or disable output of the PLA unit.
+ * @param [in] PLAx Pointer to PLA unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_PLA or CM_PLAx: PLA unit instance
+ * @param [in] u32Unit The PLA unit.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref PLA_Unit
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void PLA_OutputCmd(CM_PLA_TypeDef *PLAx, uint32_t u32Unit, en_functional_state_t enNewState)
+{
+ __IO uint32_t *CTL;
+ uint32_t u32UnitPos = 0UL;
+ uint32_t u32Temp;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_PLA_PERIPH(PLAx));
+ DDL_ASSERT(IS_PLA_UNIT(u32Unit));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u32Temp = u32Unit;
+ while (0UL != u32Temp) {
+ if (0UL != (u32Temp & 0x1UL)) {
+ CTL = PLA_CTL_ADDR(PLAx, u32UnitPos);
+ if (DISABLE != enNewState) {
+ SET_REG32_BIT(*CTL, PLA_CTL_OEN);
+ } else {
+ CLR_REG32_BIT(*CTL, PLA_CTL_OEN);
+ }
+ }
+ u32Temp >>= 1UL;
+ u32UnitPos++;
+ }
+}
+
+/**
+ * @brief Enable or disable the PLA unit.
+ * @param [in] PLAx Pointer to PLA unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_PLA or CM_PLAx: PLA unit instance
+ * @param [in] u32Unit The PLA unit.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref PLA_Unit
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void PLA_Cmd(CM_PLA_TypeDef *PLAx, uint32_t u32Unit, en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_PLA_PERIPH(PLAx));
+ DDL_ASSERT(IS_PLA_UNIT(u32Unit));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (DISABLE != enNewState) {
+ SET_REG32_BIT(PLAx->GCTL, u32Unit);
+ } else {
+ CLR_REG32_BIT(PLAx->GCTL, u32Unit);
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_PLA_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_pwc.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_pwc.c
new file mode 100644
index 0000000000..2fdac35513
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_pwc.c
@@ -0,0 +1,1191 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_pwc.c
+ * @brief This file provides firmware functions to manage the Power Control(PWC).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2022-10-31 CDT Bug fixed# PWC_PD_VdrCmd() and disable VDDR when enter PD3/4
+ 2023-06-30 CDT Modify typo
+ Add api PWC_LVD_DeInit()
+ Add assert to API PWC_STOP_Enter()
+ Modify API PWC_STOP_Enter() & add assert IS_PWC_STOP_TYPE()
+ 2023-12-15 CDT Remove redundant assert
+ Modify API PWC_PD_Enter() #use assert to replace the unlock, and add return value
+ Refine PWC_SLEEP_Enter()
+ Add API PWC_PD_SetIoState() & PWC_PD_SetMode()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_pwc.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_PWC PWC
+ * @brief Power Control Driver Library
+ * @{
+ */
+
+#if (LL_PWC_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup PWC_Local_Macros PWC Local Macros
+ * @{
+ */
+
+/* Get the backup register address of PWC */
+
+#define PWC_MD_SWITCH_TIMEOUT (30UL)
+#define PWC_MD_SWITCH_TIMEOUT2 (0x1000UL)
+
+#define PWC_LVD_EN_REG (CM_PWC->PVDCR0)
+#define PWC_LVD_EN_BIT (PWC_PVDCR0_PVD1EN)
+#define PWC_LVD_EXT_INPUT_EN_REG (CM_PWC->PVDCR0)
+#define PWC_LVD_EXT_INPUT_EN_BIT (PWC_PVDCR0_EXVCCINEN)
+#define PWC_LVD_CMP_OUTPUT_EN_REG (CM_PWC->PVDCR1)
+#define PWC_LVD_CMP_OUTPUT_EN_BIT (PWC_PVDCR1_PVD1CMPOE)
+#define PWC_LVD_FILTER_EN_REG (CM_PWC->PVDFCR)
+#define PWC_LVD_FILTER_EN_BIT (PWC_PVDFCR_PVD1NFDIS)
+#define PWC_LVD_STATUS_REG (CM_PWC->PVDDSR)
+
+#define PWC_LVD2_POS (4U)
+#define PWC_LVD_BIT_OFFSET(x) ((uint8_t)((x) * PWC_LVD2_POS))
+#define PWC_LVD_EN_BIT_OFFSET(x) (x)
+
+#define PWC_RAM_MASK (PWC_RAMPC0_RAMPDC0 | PWC_RAMPC0_RAMPDC10)
+
+#define PWC_PRAM_MASK (PWC_RAM_PD_CAN1 | PWC_RAM_PD_CAN2_3 | \
+ PWC_RAM_PD_CACHE | PWC_RAM_PD_USBFS)
+
+#define PWC_LVD_FLAG_MASK (PWC_LVD1_FLAG_MON | PWC_LVD1_FLAG_DETECT | \
+ PWC_LVD2_FLAG_MON | PWC_LVD2_FLAG_DETECT)
+
+#define PWC_LVD_EXP_NMI_POS (8U)
+
+/**
+ * @defgroup PWC_Check_Parameters_Validity PWC Check Parameters Validity
+ * @{
+ */
+
+/* Check PWC register lock status. */
+#define IS_PWC_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1)
+/* Check PWC LVD register lock status. */
+#define IS_PWC_LVD_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB3) == PWC_FPRC_FPRCB3)
+
+/* Parameter validity check for stop type */
+#define IS_PWC_STOP_TYPE(x) \
+( ((x) == PWC_STOP_WFI) || \
+ ((x) == PWC_STOP_WFE_INT) || \
+ ((x) == PWC_STOP_WFE_EVT))
+
+/* Parameter validity check for sleep type */
+#define IS_PWC_SLEEP_TYPE(x) \
+( ((x) == PWC_SLEEP_WFI) || \
+ ((x) == PWC_SLEEP_WFE_INT) || \
+ ((x) == PWC_SLEEP_WFE_EVT))
+
+/* Parameter validity check for internal RAM setting of power mode control */
+#define IS_PWC_RAM_CONTROL(x) \
+( ((x) != 0x00UL) && \
+ (((x) | PWC_RAM_MASK) == PWC_RAM_MASK))
+
+/* Parameter validity check for peripheral RAM setting of power mode control */
+#define IS_PWC_PRAM_CONTROL(x) \
+( ((x) != 0x00UL) && \
+ (((x) | PWC_PRAM_MASK) == PWC_PRAM_MASK))
+
+/* Parameter validity check for LVD channel. */
+#define IS_PWC_LVD_CH(x) \
+( ((x) == PWC_LVD_CH1) || \
+ ((x) == PWC_LVD_CH2))
+
+/* Parameter validity check for LVD function setting. */
+#define IS_PWC_LVD_EN(x) \
+( ((x) == PWC_LVD_ON) || \
+ ((x) == PWC_LVD_OFF))
+
+/* Parameter validity check for LVD compare output setting. */
+#define IS_PWC_LVD_CMP_EN(x) \
+( ((x) == PWC_LVD_CMP_ON) || \
+ ((x) == PWC_LVD_CMP_OFF))
+
+/* Parameter validity check for PWC LVD exception type. */
+#define IS_PWC_LVD_EXP_TYPE(x) \
+( ((x) == PWC_LVD_EXP_TYPE_NONE) || \
+ ((x) == PWC_LVD_EXP_TYPE_INT) || \
+ ((x) == PWC_LVD_EXP_TYPE_NMI) || \
+ ((x) == PWC_LVD_EXP_TYPE_RST))
+
+/* Parameter validity check for LVD digital noise filter function setting. */
+#define IS_PWC_LVD_FILTER_EN(x) \
+( ((x) == PWC_LVD_FILTER_ON) || \
+ ((x) == PWC_LVD_FILTER_OFF))
+
+/* Parameter validity check for LVD digital noise filter clock setting. */
+#define IS_PWC_LVD_FILTER_CLK(x) \
+( ((x) == PWC_LVD_FILTER_LRC_DIV1) || \
+ ((x) == PWC_LVD_FILTER_LRC_DIV2) || \
+ ((x) == PWC_LVD_FILTER_LRC_DIV4) || \
+ ((x) == PWC_LVD_FILTER_LRC_MUL2))
+
+/* Parameter validity check for LVD detect voltage setting. */
+#define IS_PWC_LVD_THRESHOLD_VOLTAGE(x) \
+( ((x) == PWC_LVD_THRESHOLD_LVL0) || \
+ ((x) == PWC_LVD_THRESHOLD_LVL1) || \
+ ((x) == PWC_LVD_THRESHOLD_LVL2) || \
+ ((x) == PWC_LVD_THRESHOLD_LVL3) || \
+ ((x) == PWC_LVD_THRESHOLD_LVL4) || \
+ ((x) == PWC_LVD_THRESHOLD_LVL5) || \
+ ((x) == PWC_LVD_THRESHOLD_LVL6) || \
+ ((x) == PWC_LVD_THRESHOLD_LVL7))
+
+/* Parameter validity check for LVD trigger setting. */
+#define IS_PWC_LVD_TRIG_EDGE(x) \
+( ((x) == PWC_LVD_TRIG_FALLING) || \
+ ((x) == PWC_LVD_TRIG_RISING) || \
+ ((x) == PWC_LVD_TRIG_BOTH))
+
+/* Parameter validity check for LVD trigger setting. */
+#define IS_PWC_LVD_CLR_FLAG(x) \
+( ((x) == PWC_LVD1_FLAG_DETECT) || \
+ ((x) == PWC_LVD2_FLAG_DETECT))
+
+/* Parameter validity check for LVD flag. */
+#define IS_PWC_LVD_GET_FLAG(x) \
+( ((x) != 0x00U) && \
+ (((x) | PWC_LVD_FLAG_MASK) == PWC_LVD_FLAG_MASK))
+
+/* Parameter validity check for power down mode. */
+#define IS_PWC_PD_MD(x) \
+( ((x) == PWC_PD_MD1) || \
+ ((x) == PWC_PD_MD2) || \
+ ((x) == PWC_PD_MD3) || \
+ ((x) == PWC_PD_MD4))
+
+/* Parameter validity check for IO state while power down mode. */
+#define IS_PWC_PD_IO_STATE(x) \
+( ((x) == PWC_PD_IO_KEEP1) || \
+ ((x) == PWC_PD_IO_KEEP2) || \
+ ((x) == PWC_PD_IO_HIZ))
+
+/* Parameter validity check for power down mode wake up event with trigger. */
+#define IS_PWC_WAKEUP_TRIG_EVT(x) \
+( ((x) != 0x00U) && \
+ (((x) | PWC_PD_WKUP_TRIG_ALL) == PWC_PD_WKUP_TRIG_ALL))
+
+/* Parameter validity check for power down mode wake up trigger edge. */
+#define IS_PWC_WAKEUP_TRIG(x) \
+( ((x) == PWC_PD_WKUP_TRIG_FALLING) || \
+ ((x) == PWC_PD_WKUP_TRIG_RISING))
+
+/* Parameter validity check for wake up flag. */
+#define IS_PWC_WKUP_FLAG(x) \
+( ((x) != 0x00U) && \
+ (((x) | PWC_PD_WKUP_FLAG_ALL) == PWC_PD_WKUP_FLAG_ALL))
+
+/* Parameter validity check for clock setting after wake-up from stop mode. */
+#define IS_PWC_STOP_CLK(x) \
+( ((x) == PWC_STOP_CLK_KEEP) || \
+ ((x) == PWC_STOP_CLK_MRC))
+
+/* Parameter validity check for flash wait setting after wake-up from stop mode. */
+#define IS_PWC_STOP_FLASH_WAIT(x) \
+( ((x)== PWC_STOP_FLASH_WAIT_ON) || \
+ ((x)== PWC_STOP_FLASH_WAIT_OFF))
+
+/* Parameter validity check for ex-bus setting in stop mode. */
+#define IS_PWC_STOP_EXBUS(x) \
+( ((x)== PWC_STOP_EXBUS_HIZ) || \
+ ((x)== PWC_STOP_EXBUS_HOLD))
+
+#define IS_PWC_LDO_SEL(x) \
+( ((x) != 0x00U) && \
+ (((x) | PWC_LDO_MASK) == PWC_LDO_MASK))
+
+/* Parameter validity check for WKT Clock Source. */
+#define IS_PWC_WKT_CLK_SRC(x) \
+( ((x)== PWC_WKT_CLK_SRC_64HZ) || \
+ ((x)== PWC_WKT_CLK_SRC_XTAL32) || \
+ ((x)== PWC_WKT_CLK_SRC_LRC))
+
+/* Parameter validity check for WKT Comparision Value. */
+#define IS_PWC_WKT_COMPARISION_VALUE(x) ((x) <= 0x0FFFU)
+
+/* Parameter validity check for port reset event. */
+#define IS_PWC_PORT_RST_EVT(x) \
+( ((x) != 0x00U) && \
+ (((x) | PWC_PORT_RST_ALL) == PWC_PORT_RST_ALL))
+
+/* Parameter validity check for DAC reset event. */
+#define IS_PWC_DAC_RST_EVT(x) \
+( ((x) != 0x00U) && \
+ (((x) | PWC_DAC_RST_ALL) == PWC_DAC_RST_ALL))
+
+/* Parameter validity check for RTC clock selection. */
+#define IS_PWC_RTC_CLK_SEL(x) \
+( ((x) == PWC_RTC_CLK_LRC) || \
+ ((x) == PWC_RTC_CLK_PIN) || \
+ ((x) == PWC_RTC_CLK_XTAL_DIV))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ * @defgroup PWC_Global_Functions PWC Global Functions
+ * @{
+ */
+
+/**
+ * @brief Enter power down mode.
+ * @param None
+ * @retval int32_t:
+ * - LL_ERR_TIMEOUT: Enter PD mode timeout
+ * @note Not return LL_OK because if enter PD mode ok, the MCU will shut down, and reset after woken-up.
+ */
+int32_t PWC_PD_Enter(void)
+{
+ int32_t i32Ret;
+ uint32_t u32Timeout = 0UL;
+
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+ DDL_ASSERT(IS_PWC_LVD_UNLOCKED());
+
+ /* Ensure pvd not reset exception */
+ CLR_REG8_BIT(CM_PWC->PVDCR1, PWC_PVDCR1_PVD1IRS | PWC_PVDCR1_PVD2IRS);
+ for (; ;) {
+ SET_REG16_BIT(CM_PWC->STPMCR, PWC_STPMCR_STOP);
+ SET_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_PWDN);
+ __WFI();
+ u32Timeout++;
+ if (u32Timeout > 1000UL) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Enter stop mode.
+ * @param [in] u8StopType specifies the type of enter stop's command.
+ * @arg PWC_STOP_WFI Enter stop mode by WFI, and wake-up by interrupt handle.
+ * @arg PWC_STOP_WFE_INT Enter stop mode by WFE, and wake-up by interrupt request.
+ * @arg PWC_STOP_WFE_EVT Enter stop mode by WFE, and wake-up by event.
+ * @retval None
+ */
+void PWC_STOP_Enter(uint8_t u8StopType)
+{
+
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+ DDL_ASSERT(IS_PWC_STOP_TYPE(u8StopType));
+ DDL_ASSERT(0U == (CM_PWC->PWRC0 & PWC_PWRC0_PDMDS));
+
+ SET_REG16_BIT(CM_PWC->STPMCR, PWC_STPMCR_STOP);
+ CLR_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_PWDN);
+ if (PWC_STOP_WFI == u8StopType) {
+ __WFI();
+ } else {
+ if (PWC_STOP_WFE_INT == u8StopType) {
+ SET_REG32_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
+ }
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+
+}
+
+/**
+ * @brief Enter sleep mode.
+ * @param [in] u8SleepType specifies the type of enter sleep's command.
+ * @arg PWC_SLEEP_WFI Enter sleep mode by WFI, and wake-up by interrupt handle.
+ * @arg PWC_SLEEP_WFE_INT Enter sleep mode by WFE, and wake-up by interrupt request.
+ * @arg PWC_SLEEP_WFE_EVT Enter sleep mode by WFE, and wake-up by event.
+
+ * @retval None
+ */
+void PWC_SLEEP_Enter(uint8_t u8SleepType)
+{
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+ DDL_ASSERT(IS_PWC_SLEEP_TYPE(u8SleepType));
+
+ CLR_REG16_BIT(CM_PWC->STPMCR, PWC_STPMCR_STOP);
+ CLR_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_PWDN);
+
+ if (PWC_SLEEP_WFI == u8SleepType) {
+ __WFI();
+ } else {
+ if (PWC_SLEEP_WFE_INT == u8SleepType) {
+ SET_REG32_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
+ }
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+}
+
+/**
+ * @brief Initialize LVD config structure. Fill each pstcLvdInit with default value
+ * @param [in] pstcLvdInit Pointer to a stc_pwc_lvd_init_t structure that contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: LVD structure initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t PWC_LVD_StructInit(stc_pwc_lvd_init_t *pstcLvdInit)
+{
+ int32_t i32Ret = LL_OK;
+ /* Check if pointer is NULL */
+ if (NULL == pstcLvdInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* RESET LVD init structure parameters values */
+ pstcLvdInit->u32State = PWC_LVD_OFF;
+ pstcLvdInit->u32CompareOutputState = PWC_LVD_CMP_OFF;
+ pstcLvdInit->u32ExceptionType = PWC_LVD_EXP_TYPE_NONE;
+ pstcLvdInit->u32Filter = PWC_LVD_FILTER_OFF;
+ pstcLvdInit->u32FilterClock = PWC_LVD_FILTER_LRC_MUL2;
+ pstcLvdInit->u32ThresholdVoltage = PWC_LVD_THRESHOLD_LVL0;
+ pstcLvdInit->u32TriggerEdge = PWC_LVD_TRIG_FALLING;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief LVD configuration.
+ * @param [in] u8Ch LVD channel @ref PWC_LVD_Channel.
+ * @param [in] pstcLvdInit Pointer to a stc_pwc_lvd_init_t structure that contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: LVD initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t PWC_LVD_Init(uint8_t u8Ch, const stc_pwc_lvd_init_t *pstcLvdInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ /* Check if pointer is NULL */
+ if (NULL == pstcLvdInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ DDL_ASSERT(IS_PWC_LVD_UNLOCKED());
+ DDL_ASSERT(IS_PWC_LVD_CH(u8Ch));
+ DDL_ASSERT(IS_PWC_LVD_EN(pstcLvdInit->u32State));
+ DDL_ASSERT(IS_PWC_LVD_EXP_TYPE(pstcLvdInit->u32ExceptionType));
+ DDL_ASSERT(IS_PWC_LVD_CMP_EN(pstcLvdInit->u32CompareOutputState));
+ DDL_ASSERT(IS_PWC_LVD_FILTER_EN(pstcLvdInit->u32Filter));
+ DDL_ASSERT(IS_PWC_LVD_FILTER_CLK(pstcLvdInit->u32FilterClock));
+ DDL_ASSERT(IS_PWC_LVD_THRESHOLD_VOLTAGE(pstcLvdInit->u32ThresholdVoltage));
+ DDL_ASSERT(IS_PWC_LVD_TRIG_EDGE(pstcLvdInit->u32TriggerEdge));
+
+ /* disable filter function in advance */
+ SET_REG8_BIT(CM_PWC->PVDFCR, (PWC_PVDFCR_PVD1NFDIS << PWC_LVD_BIT_OFFSET(u8Ch)));
+ MODIFY_REG8(CM_PWC->PVDFCR, (PWC_PVDFCR_PVD1NFDIS | PWC_PVDFCR_PVD1NFCKS) << PWC_LVD_BIT_OFFSET(u8Ch), \
+ (pstcLvdInit->u32Filter | pstcLvdInit->u32FilterClock) << PWC_LVD_BIT_OFFSET(u8Ch));
+ /* Config LVD threshold voltage */
+ MODIFY_REG8(CM_PWC->PVDLCR, PWC_PVDLCR_PVD1LVL << PWC_LVD_BIT_OFFSET(u8Ch), \
+ pstcLvdInit->u32ThresholdVoltage << PWC_LVD_BIT_OFFSET(u8Ch));
+ /* Enable LVD */
+ MODIFY_REG8(CM_PWC->PVDCR0, PWC_PVDCR0_PVD1EN << u8Ch, pstcLvdInit->u32State << u8Ch);
+ /* Enable compare output */
+ MODIFY_REG8(CM_PWC->PVDCR1, PWC_PVDCR1_PVD1CMPOE << PWC_LVD_BIT_OFFSET(u8Ch), \
+ pstcLvdInit->u32CompareOutputState << PWC_LVD_BIT_OFFSET(u8Ch));
+ MODIFY_REG8(CM_PWC->PVDICR, PWC_PVDICR_PVD1EDGS << PWC_LVD_BIT_OFFSET(u8Ch), \
+ pstcLvdInit->u32TriggerEdge << PWC_LVD_BIT_OFFSET(u8Ch));
+ /* config PVDIRE & PWC_PVDCR1_PVD1IRS while PVDEN & PVDCMPOE enable */
+ MODIFY_REG8(CM_PWC->PVDCR1, (PWC_PVDCR1_PVD1IRE | PWC_PVDCR1_PVD1IRS) << PWC_LVD_BIT_OFFSET(u8Ch), \
+ (pstcLvdInit->u32ExceptionType & 0xFFU) << PWC_LVD_BIT_OFFSET(u8Ch));
+ MODIFY_REG8(CM_PWC->PVDICR, PWC_PVDICR_PVD1NMIS << PWC_LVD_BIT_OFFSET(u8Ch), \
+ ((pstcLvdInit->u32ExceptionType >> PWC_LVD_EXP_NMI_POS) & 0xFFU) << PWC_LVD_BIT_OFFSET(u8Ch));
+
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief De-initialize PWC LVD.
+ * @param [in] u8Ch LVD channel @ref PWC_LVD_Channel.
+ * @retval None
+ */
+void PWC_LVD_DeInit(uint8_t u8Ch)
+{
+ DDL_ASSERT(IS_PWC_LVD_CH(u8Ch));
+ DDL_ASSERT(IS_PWC_LVD_UNLOCKED());
+
+ /* Disable LVD */
+ CLR_REG_BIT(CM_PWC->PVDCR0, PWC_PVDCR0_PVD1EN << u8Ch);
+ /* Disable Ext-Vcc */
+ if (PWC_LVD_CH2 == u8Ch) {
+ CLR_REG8_BIT(CM_PWC->PVDCR0, PWC_PVDCR0_EXVCCINEN);
+ } else {
+ /* rsvd */
+ }
+ /* Reset filter */
+ CLR_REG8_BIT(CM_PWC->PVDFCR, (PWC_PVDFCR_PVD1NFDIS | PWC_PVDFCR_PVD1NFCKS) << PWC_LVD_BIT_OFFSET(u8Ch));
+ /* Reset configure */
+ CLR_REG8_BIT(CM_PWC->PVDCR1, (PWC_PVDCR1_PVD1IRE | PWC_PVDCR1_PVD1IRS | PWC_PVDCR1_PVD1CMPOE) << \
+ PWC_LVD_BIT_OFFSET(u8Ch));
+ CLR_REG8_BIT(CM_PWC->PVDICR, (PWC_PVDICR_PVD1NMIS | PWC_PVDICR_PVD1EDGS) << PWC_LVD_BIT_OFFSET(u8Ch));
+ /* Reset threshold voltage */
+ CLR_REG8_BIT(CM_PWC->PVDLCR, PWC_PVDLCR_PVD1LVL << PWC_LVD_BIT_OFFSET(u8Ch));
+}
+
+/**
+ * @brief Enable or disable LVD.
+ * @param [in] u8Ch Specifies which channel to operate. @ref PWC_LVD_Channel.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void PWC_LVD_Cmd(uint8_t u8Ch, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_PWC_LVD_CH(u8Ch));
+ DDL_ASSERT(IS_PWC_LVD_UNLOCKED());
+
+ if (ENABLE == enNewState) {
+ SET_REG_BIT(PWC_LVD_EN_REG, PWC_LVD_EN_BIT << PWC_LVD_EN_BIT_OFFSET(u8Ch));
+ } else {
+ CLR_REG_BIT(PWC_LVD_EN_REG, PWC_LVD_EN_BIT << PWC_LVD_EN_BIT_OFFSET(u8Ch));
+ }
+}
+
+/**
+ * @brief Enable or disable LVD external input.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ * @note While enable external input, should choose PWC_LVD_CH2 to initialize and threshold voltage must set PWC_LVD_EXTVCC
+ */
+void PWC_LVD_ExtInputCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_PWC_LVD_UNLOCKED());
+
+ if (ENABLE == enNewState) {
+ SET_REG_BIT(PWC_LVD_EXT_INPUT_EN_REG, PWC_LVD_EXT_INPUT_EN_BIT);
+ } else {
+ CLR_REG_BIT(PWC_LVD_EXT_INPUT_EN_REG, PWC_LVD_EXT_INPUT_EN_BIT);
+ }
+}
+
+/**
+ * @brief Enable or disable LVD compare output.
+ * @param [in] u8Ch Specifies which channel to operate. @ref PWC_LVD_Channel.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void PWC_LVD_CompareOutputCmd(uint8_t u8Ch, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_PWC_LVD_CH(u8Ch));
+ DDL_ASSERT(IS_PWC_LVD_UNLOCKED());
+
+ if (ENABLE == enNewState) {
+ SET_REG_BIT(PWC_LVD_CMP_OUTPUT_EN_REG, PWC_LVD_CMP_OUTPUT_EN_BIT << PWC_LVD_BIT_OFFSET(u8Ch));
+ } else {
+ CLR_REG_BIT(PWC_LVD_CMP_OUTPUT_EN_REG, PWC_LVD_CMP_OUTPUT_EN_BIT << PWC_LVD_BIT_OFFSET(u8Ch));
+ }
+}
+
+/**
+ * @brief Enable or disable LVD digital filter.
+ * @param [in] u8Ch Specifies which channel to operate. @ref PWC_LVD_Channel.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void PWC_LVD_DigitalFilterCmd(uint8_t u8Ch, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_PWC_LVD_CH(u8Ch));
+ DDL_ASSERT(IS_PWC_LVD_UNLOCKED());
+
+ if (ENABLE == enNewState) {
+ CLR_REG_BIT(PWC_LVD_FILTER_EN_REG, PWC_LVD_FILTER_EN_BIT << PWC_LVD_BIT_OFFSET(u8Ch));
+ } else {
+ SET_REG_BIT(PWC_LVD_FILTER_EN_REG, PWC_LVD_FILTER_EN_BIT << PWC_LVD_BIT_OFFSET(u8Ch));
+ }
+}
+
+/**
+ * @brief Enable or disable LVD compare output.
+ * @param [in] u8Ch Specifies which channel to operate. @ref PWC_LVD_Channel.
+ * @param [in] u32Clock Specifies filter clock. @ref PWC_LVD_DFS_Clk_Sel
+ * @retval None
+ */
+void PWC_LVD_SetFilterClock(uint8_t u8Ch, uint32_t u32Clock)
+{
+ DDL_ASSERT(IS_PWC_LVD_CH(u8Ch));
+ DDL_ASSERT(IS_PWC_LVD_FILTER_CLK(u32Clock));
+ DDL_ASSERT(IS_PWC_LVD_UNLOCKED());
+ MODIFY_REG8(CM_PWC->PVDFCR, PWC_PVDFCR_PVD1NFCKS << PWC_LVD_BIT_OFFSET(u8Ch), \
+ u32Clock << PWC_LVD_BIT_OFFSET(u8Ch));
+}
+
+/**
+ * @brief Set LVD threshold voltage.
+ * @param [in] u8Ch Specifies which channel to operate. @ref PWC_LVD_Channel.
+ * @param [in] u32Voltage Specifies threshold voltage. @ref PWC_LVD_Detection_Voltage_Sel
+ * @retval None
+ * @note While PWC_LVD_CH2, PWC_LVD_EXTVCC only valid while EXTINPUT enable.
+ */
+void PWC_LVD_SetThresholdVoltage(uint8_t u8Ch, uint32_t u32Voltage)
+{
+ DDL_ASSERT(IS_PWC_LVD_CH(u8Ch));
+ DDL_ASSERT(IS_PWC_LVD_THRESHOLD_VOLTAGE(u32Voltage));
+ DDL_ASSERT(IS_PWC_LVD_UNLOCKED());
+
+ MODIFY_REG8(CM_PWC->PVDLCR, (PWC_PVDLCR_PVD1LVL << PWC_LVD_BIT_OFFSET(u8Ch)), \
+ u32Voltage << PWC_LVD_BIT_OFFSET(u8Ch));
+}
+
+/**
+ * @brief Get LVD flag.
+ * @param [in] u8Flag LVD flag to be get @ref PWC_LVD_Flag
+ * @retval An @ref en_flag_status_t enumeration value
+ * @note PVDxDETFLG is available when PVDCR0.PVDxEN and PVDCR1.PVDxCMPOE are set to '1'
+ */
+en_flag_status_t PWC_LVD_GetStatus(uint8_t u8Flag)
+{
+ DDL_ASSERT(IS_PWC_LVD_GET_FLAG(u8Flag));
+ return ((0x00U != READ_REG8_BIT(PWC_LVD_STATUS_REG, u8Flag)) ? SET : RESET);
+}
+
+/**
+ * @brief Clear LVD flag.
+ * @param [in] u8Flag LVD flag to be get @ref PWC_LVD_Flag
+ * @arg PWC_LVD1_FLAG_DETECT
+ * @arg PWC_LVD2_FLAG_DETECT
+ * @retval None
+ */
+void PWC_LVD_ClearStatus(uint8_t u8Flag)
+{
+ DDL_ASSERT(IS_PWC_LVD_UNLOCKED());
+ DDL_ASSERT(IS_PWC_LVD_CLR_FLAG(u8Flag));
+
+ CLR_REG8_BIT(PWC_LVD_STATUS_REG, u8Flag);
+}
+
+/**
+ * @brief LDO(HRC & PLL) command.
+ * @param [in] u16Ldo Specifies the ldo to command.
+ * @arg PWC_LDO_PLL
+ * @arg PWC_LDO_HRC
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void PWC_LDO_Cmd(uint16_t u16Ldo, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_PWC_LDO_SEL(u16Ldo));
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+
+ if (ENABLE == enNewState) {
+ CLR_REG8_BIT(CM_PWC->PWRC1, u16Ldo);
+ } else {
+ SET_REG8_BIT(CM_PWC->PWRC1, u16Ldo);
+ }
+}
+
+/**
+ * @brief Switch ultra low speed to high speed, set the drive ability.
+ * @param None
+ * @retval int32_t:
+ * - LL_OK: Mode switch successful.
+ * - LL_ERR: Mode switch failure, check whether EFM was unlocked please.
+ * @note After calling this API, the system clock is able to switch high frequency.
+ */
+
+/**
+ * @brief Ram area power down command.
+ * @param [in] u32Ram Specifies which ram to operate. @ref PWC_PD_Ram
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @arg ENABLE: Power down mode
+ * @arg DISABLE: Run mode
+ * @retval None
+ */
+void PWC_PD_RamCmd(uint32_t u32Ram, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_PWC_RAM_CONTROL(u32Ram));
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+
+ if (ENABLE == enNewState) {
+ SET_REG8_BIT(CM_PWC->RAMPC0, u32Ram);
+ } else {
+ CLR_REG8_BIT(CM_PWC->RAMPC0, u32Ram);
+ }
+}
+
+/**
+ * @brief VDR area power down command.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @arg ENABLE: Power down mode
+ * @arg DISABLE: Run mode
+ * @retval None
+ */
+void PWC_PD_VdrCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+
+ if (ENABLE == enNewState) {
+ CLR_REG8_BIT(CM_PWC->PWRC5, PWC_PWRC5_VVDRSD);
+ } else {
+ SET_REG8_BIT(CM_PWC->PWRC5, PWC_PWRC5_VVDRSD);
+ }
+}
+
+/**
+ * @brief Ram area power down command.
+ * @param [in] u32PeriphRam Specifies which ram to operate. @ref PWC_PD_Periph_Ram
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @arg ENABLE: Power down mode
+ * @arg DISABLE: Run mode
+ * @retval None
+ */
+void PWC_PD_PeriphRamCmd(uint32_t u32PeriphRam, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_PWC_PRAM_CONTROL(u32PeriphRam));
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+
+ if (ENABLE == enNewState) {
+ SET_REG8_BIT(CM_PWC->PRAMLPC, u32PeriphRam);
+ } else {
+ CLR_REG8_BIT(CM_PWC->PRAMLPC, u32PeriphRam);
+ }
+}
+
+/**
+ * @brief Initialize Power down mode config structure. Fill each pstcPDModeConfig with default value
+ * @param [in] pstcPDModeConfig Pointer to a stc_pwc_pd_mode_config_t structure that
+ * contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: Power down mode structure initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t PWC_PD_StructInit(stc_pwc_pd_mode_config_t *pstcPDModeConfig)
+{
+ int32_t i32Ret = LL_OK;
+
+ /* Check if pointer is NULL */
+ if (NULL == pstcPDModeConfig) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ pstcPDModeConfig->u8IOState = PWC_PD_IO_KEEP1;
+ pstcPDModeConfig->u8Mode = PWC_PD_MD1;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Power down mode config structure.
+ * @param [in] pstcPDModeConfig Pointer to a stc_pwc_pd_mode_config_t structure that
+ * contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: Power down mode config successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t PWC_PD_Config(const stc_pwc_pd_mode_config_t *pstcPDModeConfig)
+{
+ int32_t i32Ret = LL_OK;
+
+ /* Check if pointer is NULL */
+ if (NULL == pstcPDModeConfig) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+ DDL_ASSERT(IS_PWC_PD_IO_STATE(pstcPDModeConfig->u8IOState));
+ DDL_ASSERT(IS_PWC_PD_MD(pstcPDModeConfig->u8Mode));
+
+ MODIFY_REG8(CM_PWC->PWRC0, (PWC_PWRC0_IORTN | PWC_PWRC0_PDMDS), \
+ (pstcPDModeConfig->u8IOState | pstcPDModeConfig->u8Mode));
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Set IO state while PD mode.
+ * @param [in] u8IoState IO state while power down mode
+ * @arg PWC_PD_IO_KEEP1
+ * @arg PWC_PD_IO_KEEP2
+ * @arg PWC_PD_IO_HIZ
+ * @retval None
+ */
+void PWC_PD_SetIoState(uint8_t u8IoState)
+{
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+ DDL_ASSERT(IS_PWC_PD_IO_STATE(u8IoState));
+
+ MODIFY_REG8(CM_PWC->PWRC0, PWC_PWRC0_IORTN, u8IoState);
+}
+
+/**
+ * @brief Set power down mode.
+ * @param [in] u8PdMode Power down mode
+ * @arg PWC_PD_MD1 Power down mode 1
+ * @arg PWC_PD_MD2 Power down mode 2
+ * @arg PWC_PD_MD3 Power down mode 3
+ * @arg PWC_PD_MD4 Power down mode 4
+ * @retval None
+ */
+void PWC_PD_SetMode(uint8_t u8PdMode)
+{
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+ DDL_ASSERT(IS_PWC_PD_MD(u8PdMode));
+
+ MODIFY_REG8(CM_PWC->PWRC0, PWC_PWRC0_PDMDS, u8PdMode);
+}
+
+/**
+ * @brief Power down mode wake up event config.
+ * @param [in] u32Event Wakeup Event. @ref PWC_WKUP_Event_Sel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void PWC_PD_WakeupCmd(uint32_t u32Event, en_functional_state_t enNewState)
+{
+ uint8_t u8Event0 = (uint8_t)u32Event;
+ uint8_t u8Event1 = (uint8_t)(u32Event >> PWC_PD_WKUP1_POS);
+ uint8_t u8Event2 = (uint8_t)(u32Event >> PWC_PD_WKUP2_POS);
+ if (ENABLE == enNewState) {
+ SET_REG8_BIT(CM_PWC->PDWKE0, u8Event0);
+ SET_REG8_BIT(CM_PWC->PDWKE1, u8Event1);
+ SET_REG8_BIT(CM_PWC->PDWKE2, u8Event2);
+ } else {
+ CLR_REG8_BIT(CM_PWC->PDWKE0, u8Event0);
+ CLR_REG8_BIT(CM_PWC->PDWKE1, u8Event1);
+ CLR_REG8_BIT(CM_PWC->PDWKE2, u8Event2);
+ }
+}
+
+/**
+ * @brief Power down mode wake up event trigger config.
+ * @param [in] u8Event PVD and wake up pin. @ref PWC_WKUP_Trigger_Event_Sel
+ * @param [in] u8TrigEdge The trigger edge.
+ * @arg PWC_PD_WKUP_TRIG_FALLING
+ * @arg PWC_PD_WKUP_TRIG_RISING
+ * @retval None
+ */
+void PWC_PD_SetWakeupTriggerEdge(uint8_t u8Event, uint8_t u8TrigEdge)
+{
+ DDL_ASSERT(IS_PWC_WAKEUP_TRIG_EVT(u8Event));
+ DDL_ASSERT(IS_PWC_WAKEUP_TRIG(u8TrigEdge));
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+
+ if (PWC_PD_WKUP_TRIG_RISING == u8TrigEdge) {
+ SET_REG8_BIT(CM_PWC->PDWKES, u8Event);
+ } else {
+ CLR_REG8_BIT(CM_PWC->PDWKES, u8Event);
+ }
+}
+
+/**
+ * @brief Get wake up event flag.
+ * @param [in] u16Flag Wake up event. @ref PWC_WKUP_Event_Flag_Sel
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t PWC_PD_GetWakeupStatus(uint16_t u16Flag)
+{
+ uint8_t u8Flag0;
+ uint8_t u8Flag1;
+
+ DDL_ASSERT(IS_PWC_WKUP_FLAG(u16Flag));
+
+ u8Flag0 = READ_REG8_BIT(CM_PWC->PDWKF0, u16Flag);
+ u8Flag1 = READ_REG8_BIT(CM_PWC->PDWKF1, (u16Flag >> PWC_PD_WKUP_FLAG1_POS));
+
+ return (((0U != u8Flag0) || (0U != u8Flag1)) ? SET : RESET);
+}
+
+/**
+ * @brief Clear wake up event flag.
+ * @param [in] u16Flag Wake up event. @ref PWC_WKUP_Event_Flag_Sel
+ * @retval None
+ */
+void PWC_PD_ClearWakeupStatus(uint16_t u16Flag)
+{
+ uint8_t u8Flag0;
+ uint8_t u8Flag1;
+
+ DDL_ASSERT(IS_PWC_WKUP_FLAG(u16Flag));
+
+ u8Flag0 = (uint8_t)u16Flag;
+ u8Flag1 = (uint8_t)(u16Flag >> PWC_PD_WKUP_FLAG1_POS);
+
+ CLR_REG8_BIT(CM_PWC->PDWKF0, u8Flag0);
+ CLR_REG8_BIT(CM_PWC->PDWKF1, u8Flag1);
+}
+
+/**
+ * @brief Stop mode config.
+ * @param [in] pstcStopConfig Chip config before entry stop mode.
+ * @arg u8StopDrv, MCU from which speed mode entry stop mode.
+ * @arg u16Clock, System clock setting after wake-up from stop mode.
+ * @arg u16FlashWait, Whether wait flash stable after wake-up from stop mode.
+ * @arg u16ExBusHold, ExBus status in stop mode.
+ * @retval int32_t:
+ * - LL_OK: Stop mode config successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t PWC_STOP_Config(const stc_pwc_stop_mode_config_t *pstcStopConfig)
+{
+ int32_t i32Ret = LL_OK;
+
+ /* Check if pointer is NULL */
+ if (NULL == pstcStopConfig) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+
+ DDL_ASSERT(IS_PWC_STOP_CLK(pstcStopConfig->u16Clock));
+ DDL_ASSERT(IS_PWC_STOP_FLASH_WAIT(pstcStopConfig->u16FlashWait));
+ DDL_ASSERT(IS_PWC_STOP_EXBUS(pstcStopConfig->u16ExBusHold));
+ MODIFY_REG16(CM_PWC->STPMCR, (PWC_STPMCR_EXBUSOE | PWC_STPMCR_CKSMRC | PWC_STPMCR_FLNWT), \
+ (pstcStopConfig->u16ExBusHold | pstcStopConfig->u16Clock | pstcStopConfig->u16FlashWait));
+
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize stop mode config structure. Fill each pstcStopConfig with default value
+ * @param [in] pstcStopConfig Pointer to a stc_pwc_stop_mode_config_t structure that
+ * contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: Stop down mode structure initialize successful
+ * - LL_ERR_INVD_PARAM: NULL pointer
+ */
+int32_t PWC_STOP_StructInit(stc_pwc_stop_mode_config_t *pstcStopConfig)
+{
+ int32_t i32Ret = LL_OK;
+
+ /* Check if pointer is NULL */
+ if (NULL == pstcStopConfig) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ pstcStopConfig->u16Clock = PWC_STOP_CLK_KEEP;
+ pstcStopConfig->u16FlashWait = PWC_STOP_FLASH_WAIT_ON;
+ pstcStopConfig->u16ExBusHold = PWC_STOP_EXBUS_HIZ;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Stop mode wake up clock config.
+ * @param [in] u8Clock System clock setting after wake-up from stop mode. @ref PWC_STOP_CLK_Sel
+ * @retval None
+ */
+void PWC_STOP_ClockSelect(uint8_t u8Clock)
+{
+ DDL_ASSERT(IS_PWC_STOP_CLK(u8Clock));
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+
+ MODIFY_REG16(CM_PWC->STPMCR, PWC_STPMCR_CKSMRC, (uint16_t)u8Clock);
+
+}
+
+/**
+ * @brief Stop mode wake up flash wait config.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void PWC_STOP_FlashWaitCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+
+ if (ENABLE == enNewState) {
+ CLR_REG16_BIT(CM_PWC->STPMCR, PWC_STPMCR_FLNWT);
+ } else {
+ SET_REG16_BIT(CM_PWC->STPMCR, PWC_STPMCR_FLNWT);
+ }
+}
+
+/**
+ * @brief Stop mode ex-bus status config.
+ * @param [in] u16ExBusHold ExBus status in stop mode.
+ * @arg PWC_STOP_EXBUS_HIZ
+ * @arg PWC_STOP_EXBUS_HOLD
+ * @retval None
+ */
+void PWC_STOP_ExBusHoldConfig(uint16_t u16ExBusHold)
+{
+ DDL_ASSERT(IS_PWC_STOP_EXBUS(u16ExBusHold));
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+
+ MODIFY_REG16(CM_PWC->STPMCR, PWC_STPMCR_EXBUSOE, u16ExBusHold);
+}
+
+/**
+ * @brief PWC power monitor command.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ * @note This monitor power is used for ADC and output to REGC pin.
+ */
+void PWC_PowerMonitorCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+ if (ENABLE == enNewState) {
+ SET_REG8_BIT(CM_PWC->PWRC4, PWC_PWRC4_ADBUFE);
+ } else {
+ CLR_REG8_BIT(CM_PWC->PWRC4, PWC_PWRC4_ADBUFE);
+ }
+
+}
+
+/**
+ * @brief WKT Timer Initialize.
+ * @param [in] u16ClkSrc Clock source.
+ * This parameter can be one of the values @ref PWC_WKT_Clock_Source.
+ * @param [in] u16CmpVal Comparison value of the Counter.
+ * @arg This parameter can be a number between Min_Data = 0 and Max_Data = 0xFFF.
+ * @retval None
+ */
+void PWC_WKT_Config(uint16_t u16ClkSrc, uint16_t u16CmpVal)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_PWC_WKT_CLK_SRC(u16ClkSrc));
+ DDL_ASSERT(IS_PWC_WKT_COMPARISION_VALUE(u16CmpVal));
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+
+ WRITE_REG16(CM_PWC->WKTCR, (uint16_t)(u16ClkSrc | (u16CmpVal & PWC_WKTCR_WKTMCMP)));
+}
+
+/**
+ * @brief SET WKT Timer compare value.
+ * @param [in] u16CmpVal Comparison value of the Counter.
+ * @arg This parameter can be a number between Min_Data = 0 and Max_Data = 0xFFF.
+ * @retval None
+ */
+void PWC_WKT_SetCompareValue(uint16_t u16CmpVal)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_PWC_WKT_COMPARISION_VALUE(u16CmpVal));
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+ MODIFY_REG16(CM_PWC->WKTCR, PWC_WKTCR_WKTMCMP, u16CmpVal);
+}
+
+/**
+ * @brief Get WKT Timer compare value.
+ * @param None
+ * @retval uint16_t WKT Compare value
+ */
+uint16_t PWC_WKT_GetCompareValue(void)
+{
+ uint16_t u16CmpVal;
+
+ u16CmpVal = READ_REG16_BIT(CM_PWC->WKTCR, PWC_WKTCR_WKTMCMP);
+
+ return u16CmpVal;
+}
+
+/**
+ * @brief ENABLE or DISABLE WKT Timer.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void PWC_WKT_Cmd(en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+
+ if (ENABLE == enNewState) {
+ MODIFY_REG16(CM_PWC->WKTCR, PWC_WKTCR_WKTCE, PWC_WKT_ON);
+ } else {
+ MODIFY_REG16(CM_PWC->WKTCR, PWC_WKTCR_WKTCE, PWC_WKT_OFF);
+ }
+
+}
+
+/**
+ * @brief Get WKT Timer count match flag.
+ * @param None
+ * @retval An @ref en_flag_status_t enumeration type value. enumeration value:
+ */
+en_flag_status_t PWC_WKT_GetStatus(void)
+{
+ en_flag_status_t enFlagState;
+
+ enFlagState = (0U != READ_REG16_BIT(CM_PWC->WKTCR, PWC_WKTCR_WKOVF)) ? SET : RESET;
+
+ return enFlagState;
+}
+
+/**
+ * @brief Clear WKT Timer count match flag.
+ * @param None
+ * @retval None
+ */
+void PWC_WKT_ClearStatus(void)
+{
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+ CLR_REG16_BIT(CM_PWC->WKTCR, PWC_WKTCR_WKOVF);
+}
+
+/**
+ * @brief ENABLE or DISABLE XTAL32 power.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @arg ENABLE: Power on
+ * @arg DISABLE: Power off
+ * @retval None
+ */
+void PWC_XTAL32_PowerCmd(en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+
+ if (ENABLE == enNewState) {
+ CLR_REG8_BIT(CM_PWC->PWRC5, PWC_PWRC5_CSDIS);
+ } else {
+ SET_REG_BIT(CM_PWC->PWRC5, PWC_PWRC5_CSDIS);
+ }
+}
+
+/**
+ * @brief Ret_Sram area power command.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @arg ENABLE: Power on
+ * @arg DISABLE: Power off
+ * @retval None
+ */
+void PWC_RetSram_PowerCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+
+ if (ENABLE == enNewState) {
+ CLR_REG8_BIT(CM_PWC->PWRC5, PWC_PWRC5_RETRAMSD);
+ } else {
+ SET_REG8_BIT(CM_PWC->PWRC5, PWC_PWRC5_RETRAMSD);
+ }
+}
+
+/**
+ * @brief Port reset event config.
+ * @param [in] u8Event Reset event. @ref PWC_Port_Reset_Sel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void PWC_PortResetCmd(uint8_t u8Event, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_PWC_PORT_RST_EVT(u8Event));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+
+ if (ENABLE == enNewState) {
+ CLR_REG8_BIT(CM_PWC->PWRC6, u8Event);
+ } else {
+ SET_REG8_BIT(CM_PWC->PWRC6, u8Event);
+ }
+}
+
+/**
+ * @brief Release port status.
+ * @param None
+ * @retval None
+ */
+void PWC_ReleasePort(void)
+{
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+
+ SET_REG8_BIT(CM_PWC->PWRC6, PWC_PWRC6_IORTNCLR);
+}
+
+/**
+ * @brief DAC reset event config.
+ * @param [in] u8Event Reset event. @ref PWC_Dac_Reset_Sel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void PWC_DacResetCmd(uint8_t u8Event, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_PWC_DAC_RST_EVT(u8Event));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+
+ if (ENABLE == enNewState) {
+ CLR_REG8_BIT(CM_PWC->PWRC6, u8Event);
+ } else {
+ SET_REG8_BIT(CM_PWC->PWRC6, u8Event);
+ }
+}
+
+/**
+ * @brief Set RTC clock.
+ * @param [in] u8Clock Reset event. @ref PWC_Rtc_Clock_Sel
+ * @retval None
+ */
+void PWC_SetRtcClock(uint8_t u8Clock)
+{
+ DDL_ASSERT(IS_PWC_RTC_CLK_SEL(u8Clock));
+ DDL_ASSERT(IS_PWC_UNLOCKED());
+
+ MODIFY_REG8(CM_PWC->PWRC6, PWC_PWRC6_RTCCKSEL, u8Clock);
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_PWC_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_qspi.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_qspi.c
new file mode 100644
index 0000000000..4b15f453c9
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_qspi.c
@@ -0,0 +1,494 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_qspi.c
+ * @brief This file provides firmware functions to manage the QSPI.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Optimize QSPI_DeInit function
+ 2023-09-30 CDT Optimize QSPI_ClearStatus function
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_qspi.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_QSPI QSPI
+ * @brief QSPI Driver Library
+ * @{
+ */
+
+#if (LL_QSPI_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup QSPI_Local_Macros QSPI Local Macros
+ * @{
+ */
+
+/* QSPI registers Mask */
+#define QSPI_CR_CLR_MASK (QSPI_CR_DIV | QSPI_CR_SPIMD3 | QSPI_CR_PFSAE | \
+ QSPI_CR_PFE | QSPI_CR_MDSEL)
+#define QSPI_FCR_CLR_MASK (QSPI_FCR_DUTY | QSPI_FCR_DMCYCN | QSPI_FCR_SSNLD | \
+ QSPI_FCR_SSNHD | QSPI_FCR_FOUR_BIC | QSPI_FCR_AWSL)
+#define QSPI_CUSTOM_MD_CLR_MASK (QSPI_CR_IPRSL | QSPI_CR_APRSL | QSPI_CR_DPRSL)
+
+/**
+ * @defgroup QSPI_Check_Parameters_Validity QSPI check parameters validity
+ * @{
+ */
+
+#define IS_QSPI_CLK_DIV(x) \
+( ((x) != 0U) && \
+ (((x) | QSPI_CLK_DIV64) == QSPI_CLK_DIV64))
+
+#define IS_QSPI_SPI_MD(x) \
+( ((x) == QSPI_SPI_MD0) || \
+ ((x) == QSPI_SPI_MD3))
+
+#define IS_QSPI_PREFETCH_MD(x) \
+( ((x) == QSPI_PREFETCH_MD_INVD) || \
+ ((x) == QSPI_PREFETCH_MD_EDGE_STOP) || \
+ ((x) == QSPI_PREFETCH_MD_IMMED_STOP))
+
+#define IS_QSPI_READ_MD(x) \
+( ((x) == QSPI_RD_MD_STD_RD) || \
+ ((x) == QSPI_RD_MD_FAST_RD) || \
+ ((x) == QSPI_RD_MD_DUAL_OUTPUT_FAST_RD) || \
+ ((x) == QSPI_RD_MD_DUAL_IO_FAST_RD) || \
+ ((x) == QSPI_RD_MD_QUAD_OUTPUT_FAST_RD) || \
+ ((x) == QSPI_RD_MD_QUAD_IO_FAST_RD) || \
+ ((x) == QSPI_RD_MD_CUSTOM_STANDARD_RD) || \
+ ((x) == QSPI_RD_MD_CUSTOM_FAST_RD))
+
+#define IS_QSPI_DUMMY_CYCLE(x) (((x) | QSPI_DUMMY_CYCLE18) == QSPI_DUMMY_CYCLE18)
+
+#define IS_QSPI_ADDR_WIDTH(x) \
+( ((x) == QSPI_ADDR_WIDTH_8BIT) || \
+ ((x) == QSPI_ADDR_WIDTH_16BIT) || \
+ ((x) == QSPI_ADDR_WIDTH_24BIT) || \
+ ((x) == QSPI_ADDR_WIDTH_32BIT_INSTR_24BIT) || \
+ ((x) == QSPI_ADDR_WIDTH_32BIT_INSTR_32BIT))
+
+#define IS_QSPI_QSSN_SETUP_TIME(x) \
+( ((x) == QSPI_QSSN_SETUP_ADVANCE_QSCK0P5) || \
+ ((x) == QSPI_QSSN_SETUP_ADVANCE_QSCK1P5))
+
+#define IS_QSPI_QSSN_RELEASE_TIME(x) \
+( ((x) == QSPI_QSSN_RELEASE_DELAY_QSCK0P5) || \
+ ((x) == QSPI_QSSN_RELEASE_DELAY_QSCK1P5) || \
+ ((x) == QSPI_QSSN_RELEASE_DELAY_QSCK32) || \
+ ((x) == QSPI_QSSN_RELEASE_DELAY_QSCK128) || \
+ ((x) == QSPI_QSSN_RELEASE_DELAY_INFINITE))
+
+#define IS_QSPI_QSSN_INTERVAL_TIME(x) ((x) <= QSPI_QSSN_INTERVAL_QSCK16)
+
+#define IS_QSPI_INSTR_PROTOCOL(x) \
+( ((x) == QSPI_INSTR_PROTOCOL_1LINE) || \
+ ((x) == QSPI_INSTR_PROTOCOL_2LINE) || \
+ ((x) == QSPI_INSTR_PROTOCOL_4LINE))
+
+#define IS_QSPI_ADDR_PROTOCOL(x) \
+( ((x) == QSPI_ADDR_PROTOCOL_1LINE) || \
+ ((x) == QSPI_ADDR_PROTOCOL_2LINE) || \
+ ((x) == QSPI_ADDR_PROTOCOL_4LINE))
+
+#define IS_QSPI_DATA_PROTOCOL(x) \
+( ((x) == QSPI_DATA_PROTOCOL_1LINE) || \
+ ((x) == QSPI_DATA_PROTOCOL_2LINE) || \
+ ((x) == QSPI_DATA_PROTOCOL_4LINE))
+
+#define IS_QSPI_WP_PIN_LVL(x) \
+( ((x) == QSPI_WP_PIN_LOW) || \
+ ((x) == QSPI_WP_PIN_HIGH))
+
+#define IS_QSPI_FLAG(x) \
+( ((x) != 0U) && \
+ (((x) | QSPI_FLAG_ALL) == QSPI_FLAG_ALL))
+
+#define IS_QSPI_CLR_FLAG(x) \
+( ((x) != 0U) && \
+ (((x) | QSPI_FLAG_CLR_ALL) == QSPI_FLAG_CLR_ALL))
+
+#define IS_QSPI_BLOCK_SIZE(x) ((x) <= (QSPI_EXAR_EXADR >> QSPI_EXAR_EXADR_POS))
+
+#define IS_QSPI_PWC_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1)
+
+/* QSPI reset timeout */
+#define QSPI_RMU_TIMEOUT (100UL)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+/**
+ * @defgroup QSPI_Local_Variable QSPI Local Variable
+ * @{
+ */
+
+/* Current read mode */
+static uint32_t m_u32ReadMode = 0U;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup QSPI_Global_Functions QSPI Global Functions
+ * @{
+ */
+
+/**
+ * @brief De-initializes QSPI.
+ * @param None
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_TIMEOUT: Works timeout.
+ */
+int32_t QSPI_DeInit(void)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t u32TimeOut = 0U;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_QSPI_PWC_UNLOCKED());
+
+ CLR_REG32_BIT(CM_RMU->FRST1, RMU_FRST1_QSPI);
+ /* Ensure reset procedure is completed */
+ while (RMU_FRST1_QSPI != READ_REG32_BIT(CM_RMU->FRST1, RMU_FRST1_QSPI)) {
+ u32TimeOut++;
+ if (u32TimeOut > QSPI_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize QSPI.
+ * @param [in] pstcQspiInit Pointer to a @ref stc_qspi_init_t structure
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t QSPI_Init(const stc_qspi_init_t *pstcQspiInit)
+{
+ int32_t i32Ret = LL_OK;
+ uint32_t u32Duty = 0UL;
+
+ if (NULL == pstcQspiInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Check parameters */
+ DDL_ASSERT(IS_QSPI_CLK_DIV(pstcQspiInit->u32ClockDiv));
+ DDL_ASSERT(IS_QSPI_SPI_MD(pstcQspiInit->u32SpiMode));
+ DDL_ASSERT(IS_QSPI_PREFETCH_MD(pstcQspiInit->u32PrefetchMode));
+ DDL_ASSERT(IS_QSPI_READ_MD(pstcQspiInit->u32ReadMode));
+ DDL_ASSERT(IS_QSPI_DUMMY_CYCLE(pstcQspiInit->u32DummyCycle));
+ DDL_ASSERT(IS_QSPI_ADDR_WIDTH(pstcQspiInit->u32AddrWidth));
+ DDL_ASSERT(IS_QSPI_QSSN_SETUP_TIME(pstcQspiInit->u32SetupTime));
+ DDL_ASSERT(IS_QSPI_QSSN_RELEASE_TIME(pstcQspiInit->u32ReleaseTime));
+ DDL_ASSERT(IS_QSPI_QSSN_INTERVAL_TIME(pstcQspiInit->u32IntervalTime));
+
+ /* Duty cycle compensation */
+ if (0UL == (pstcQspiInit->u32ClockDiv & QSPI_CLK_DIV2)) {
+ u32Duty = QSPI_FCR_DUTY;
+ }
+ MODIFY_REG32(CM_QSPI->CR, QSPI_CR_CLR_MASK, (pstcQspiInit->u32ClockDiv | pstcQspiInit->u32SpiMode |
+ pstcQspiInit->u32PrefetchMode | pstcQspiInit->u32ReadMode));
+ WRITE_REG32(CM_QSPI->CSCR, ((pstcQspiInit->u32ReleaseTime >> 8U) | pstcQspiInit->u32IntervalTime));
+ MODIFY_REG32(CM_QSPI->FCR, QSPI_FCR_CLR_MASK, (pstcQspiInit->u32DummyCycle | pstcQspiInit->u32AddrWidth |
+ pstcQspiInit->u32SetupTime | (pstcQspiInit->u32ReleaseTime & 0xFFU) | u32Duty));
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Fills each stc_qspi_init_t member with default value.
+ * @param [out] pstcQspiInit Pointer to a @ref stc_qspi_init_t structure
+ * @retval int32_t:
+ * - LL_OK: stc_qspi_init_t member initialize success
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t QSPI_StructInit(stc_qspi_init_t *pstcQspiInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcQspiInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ pstcQspiInit->u32ClockDiv = QSPI_CLK_DIV2;
+ pstcQspiInit->u32SpiMode = QSPI_SPI_MD0;
+ pstcQspiInit->u32PrefetchMode = QSPI_PREFETCH_MD_INVD;
+ pstcQspiInit->u32ReadMode = QSPI_RD_MD_STD_RD;
+ pstcQspiInit->u32DummyCycle = QSPI_DUMMY_CYCLE3;
+ pstcQspiInit->u32AddrWidth = QSPI_ADDR_WIDTH_24BIT;
+ pstcQspiInit->u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5;
+ pstcQspiInit->u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK0P5;
+ pstcQspiInit->u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set the level of WP pin.
+ * @param [in] u32Level The level value.
+ * This parameter can be one of the following values:
+ * @arg QSPI_WP_PIN_LOW: WP(QSIO2) pin output low
+ * @arg QSPI_WP_PIN_HIGH: WP(QSIO2) pin output high
+ * @retval None
+ */
+void QSPI_SetWpPinLevel(uint32_t u32Level)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_QSPI_WP_PIN_LVL(u32Level));
+
+ MODIFY_REG32(CM_QSPI->FCR, QSPI_FCR_WPOL, u32Level);
+}
+
+/**
+ * @brief Set the prefetch mode.
+ * @param [in] u32Mode The prefetch mode.
+ * This parameter can be one of the following values:
+ * @arg QSPI_PREFETCH_MD_INVD: Disable prefetch
+ * @arg QSPI_PREFETCH_MD_EDGE_STOP: Stop prefetch at the edge of byte
+ * @arg QSPI_PREFETCH_MD_IMMED_STOP: Stop prefetch at current position immediately
+ * @retval None
+ */
+void QSPI_SetPrefetchMode(uint32_t u32Mode)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_QSPI_PREFETCH_MD(u32Mode));
+
+ MODIFY_REG32(CM_QSPI->CR, (QSPI_CR_PFE | QSPI_CR_PFSAE), u32Mode);
+}
+
+/**
+ * @brief Selects the block to access.
+ * @param [in] u8Block Memory block number (range is 0 to 63)
+ * @retval None
+ */
+void QSPI_SelectMemoryBlock(uint8_t u8Block)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_QSPI_BLOCK_SIZE(u8Block));
+
+ WRITE_REG32(CM_QSPI->EXAR, ((uint32_t)u8Block << QSPI_EXAR_EXADR_POS));
+}
+
+/**
+ * @brief Set the read mode.
+ * @param [in] u32Mode Read mode.
+ * This parameter can be one of the following values:
+ * @arg QSPI_RD_MD_STD_RD: Standard read mode (no dummy cycles)
+ * @arg QSPI_RD_MD_FAST_RD: Fast read mode (dummy cycles between address and data)
+ * @arg QSPI_RD_MD_DUAL_OUTPUT_FAST_RD: Fast read dual output mode (data on 2 lines)
+ * @arg QSPI_RD_MD_DUAL_IO_FAST_RD: Fast read dual I/O mode (address and data on 2 lines)
+ * @arg QSPI_RD_MD_QUAD_OUTPUT_FAST_RD: Fast read quad output mode (data on 4 lines)
+ * @arg QSPI_RD_MD_QUAD_IO_FAST_RD: Fast read quad I/O mode (address and data on 4 lines)
+ * @arg QSPI_RD_MD_CUSTOM_STANDARD_RD: Custom standard read mode
+ * @arg QSPI_RD_MD_CUSTOM_FAST_RD: Custom fast read mode
+ * @retval None
+ */
+void QSPI_SetReadMode(uint32_t u32Mode)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_QSPI_READ_MD(u32Mode));
+
+ MODIFY_REG32(CM_QSPI->CR, QSPI_CR_MDSEL, u32Mode);
+}
+
+/**
+ * @brief Configure the custom read.
+ * @param [in] pstcCustomMode Pointer to a @ref stc_qspi_custom_mode_t structure
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t QSPI_CustomReadConfig(const stc_qspi_custom_mode_t *pstcCustomMode)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcCustomMode) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Check parameters */
+ DDL_ASSERT(IS_QSPI_INSTR_PROTOCOL(pstcCustomMode->u32InstrProtocol));
+ DDL_ASSERT(IS_QSPI_ADDR_PROTOCOL(pstcCustomMode->u32AddrProtocol));
+ DDL_ASSERT(IS_QSPI_DATA_PROTOCOL(pstcCustomMode->u32DataProtocol));
+
+ MODIFY_REG32(CM_QSPI->CR, QSPI_CUSTOM_MD_CLR_MASK, (pstcCustomMode->u32InstrProtocol |
+ pstcCustomMode->u32AddrProtocol | pstcCustomMode->u32DataProtocol));
+ WRITE_REG32(CM_QSPI->CCMD, pstcCustomMode->u8InstrCode);
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Enable or disable XIP mode.
+ * @param [in] u8ModeCode Enter or exit XIP mode code
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void QSPI_XipModeCmd(uint8_t u8ModeCode, en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ WRITE_REG32(CM_QSPI->XCMD, u8ModeCode);
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_XIPE);
+ } else {
+ CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_XIPE);
+ }
+}
+
+/**
+ * @brief Enter direct communication mode.
+ * @param None
+ * @retval None
+ */
+void QSPI_EnterDirectCommMode(void)
+{
+ /* Backup the read mode */
+ m_u32ReadMode = READ_REG32_BIT(CM_QSPI->CR, QSPI_CR_MDSEL);
+ if (m_u32ReadMode <= QSPI_RD_MD_QUAD_IO_FAST_RD) {
+ /* Set standard read mode */
+ CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_MDSEL);
+ }
+ /* Enter direct communication mode */
+ SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
+}
+
+/**
+ * @brief Exit direct communication mode.
+ * @param None
+ * @retval None
+ */
+void QSPI_ExitDirectCommMode(void)
+{
+ /* Exit direct communication mode */
+ CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
+ if (m_u32ReadMode <= QSPI_RD_MD_QUAD_IO_FAST_RD) {
+ /* Recovery the read mode */
+ SET_REG32_BIT(CM_QSPI->CR, m_u32ReadMode);
+ }
+}
+
+/**
+ * @brief Get the size of prefetched buffer.
+ * @param None
+ * @retval uint8_t Prefetched buffer size.
+ */
+uint8_t QSPI_GetPrefetchBufSize(void)
+{
+ return (uint8_t)(READ_REG32_BIT(CM_QSPI->SR, QSPI_SR_PFNUM) >> QSPI_SR_PFNUM_POS);
+}
+
+/**
+ * @brief Get QSPI flag.
+ * @param [in] u32Flag QSPI flag type
+ * This parameter can be one or any combination of the following values:
+ * @arg QSPI_FLAG_DIRECT_COMM_BUSY: Serial transfer being processed
+ * @arg QSPI_FLAG_XIP_MD: XIP mode
+ * @arg QSPI_FLAG_ROM_ACCESS_ERR: ROM access detection status in direct communication mode
+ * @arg QSPI_FLAG_PREFETCH_BUF_FULL: Prefetch buffer is full
+ * @arg QSPI_FLAG_PREFETCH_STOP: Prefetch function operating
+ * @arg QSPI_FLAG_ALL: All of the above
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t QSPI_GetStatus(uint32_t u32Flag)
+{
+ en_flag_status_t enFlagSta = RESET;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_QSPI_FLAG(u32Flag));
+
+ if (0UL != READ_REG32_BIT(CM_QSPI->SR, u32Flag)) {
+ enFlagSta = SET;
+ }
+
+ return enFlagSta;
+}
+
+/**
+ * @brief Clear QSPI flag.
+ * @param [in] u32Flag QSPI flag type
+ * This parameter can be one or any combination of the following values:
+ * @arg QSPI_FLAG_ROM_ACCESS_ERR: ROM access detection status in direct communication mode
+ * @arg QSPI_FLAG_CLR_ALL: All of the above
+ * @retval None
+ */
+void QSPI_ClearStatus(uint32_t u32Flag)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_QSPI_CLR_FLAG(u32Flag));
+
+ WRITE_REG32(CM_QSPI->SR2, u32Flag);
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_QSPI_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_rmu.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_rmu.c
new file mode 100644
index 0000000000..72783f4cdf
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_rmu.c
@@ -0,0 +1,291 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_rmu.c
+ * @brief This file provides firmware functions to manage the Reset Manage Unit
+ * (RMU).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Use IS_RMU_UNLOCKED() to assert and optimize api RMU_PeriphRstCmd() as RMU_FrstxPeriphReset
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_rmu.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_RMU RMU
+ * @brief RMU Driver Library
+ * @{
+ */
+
+#if (LL_RMU_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup RMU_Local_Macros RMU Local Macros
+ * @{
+ */
+#define IS_RMU_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1)
+
+#define RMU_TIMEOUT (100U)
+
+/**
+ * @defgroup RMU_Check_Parameters_Validity RMU Check Parameters Validity
+ * @{
+ */
+
+/*! Parameter validity check for RMU reset cause. */
+#define IS_VALID_RMU_RST_FLAG(x) \
+( ((x) != 0UL) && \
+ (((x) | RMU_FLAG_ALL) == RMU_FLAG_ALL))
+
+/*! Parameter validity check for RMU reset register0. */
+#define IS_FRST0_PERIPH(x) \
+( ((x) != 0UL) && \
+ (((x) | RMU_FRST0_PERIPH_ALL ) == RMU_FRST0_PERIPH_ALL))
+
+/*! Parameter validity check for RMU reset register1. */
+#define IS_FRST1_PERIPH(x) \
+( ((x) != 0UL) && \
+ (((x) | RMU_FRST1_PERIPH_ALL) == RMU_FRST1_PERIPH_ALL))
+
+/*! Parameter validity check for RMU reset register2. */
+#define IS_FRST2_PERIPH(x) \
+( ((x) != 0UL) && \
+ (((x) | RMU_FRST2_PERIPH_ALL) == RMU_FRST2_PERIPH_ALL))
+
+/*! Parameter validity check for RMU reset register3. */
+#define IS_FRST3_PERIPH(x) \
+( ((x) != 0UL) && \
+ (((x) | RMU_FRST3_PERIPH_ALL) == RMU_FRST3_PERIPH_ALL))
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup RMU_Global_Functions RMU Global Functions
+ * @{
+ */
+
+/**
+ * @brief Get the reset cause.
+ * @param [in] u32RmuResetCause Reset flags that need to be queried, @ref RMU_ResetCause in details
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t RMU_GetStatus(uint32_t u32RmuResetCause)
+{
+ en_flag_status_t enStatus;
+ DDL_ASSERT(IS_VALID_RMU_RST_FLAG(u32RmuResetCause));
+
+ enStatus = ((0UL == READ_REG32_BIT(CM_RMU->RSTF0, u32RmuResetCause)) ? RESET : SET);
+ return enStatus;
+}
+
+/**
+ * @brief Clear reset Status.
+ * @param None
+ * @retval NOne
+ * @note Clear reset flag should be done after read RMU_RSTF0 register.
+ * Call PWC_Unlock(PWC_UNLOCK_CODE_1) unlock RMU_RSTF0 register first.
+ */
+void RMU_ClearStatus(void)
+{
+ DDL_ASSERT(IS_RMU_UNLOCKED());
+ SET_REG_BIT(CM_RMU->RSTF0, RMU_RSTF0_CLRF);
+ __NOP();
+ __NOP();
+ __NOP();
+ __NOP();
+ __NOP();
+ __NOP();
+}
+
+/**
+ * @brief Enable or disable LOCKUP reset.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ * @note Call LL_PERIPH_WE(LL_PERIPH_PWC_CLK_RMU) unlock RMU_PRSTCR0 register first.
+ */
+void RMU_CPULockUpCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_RMU_UNLOCKED());
+
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ WRITE_REG32(bCM_RMU->PRSTCR0_b.LKUPREN, enNewState);
+}
+
+/**
+ * @brief Reset FRST0 peripheral.
+ * @param [in] u32Frst0Periph The peripheral in FRST0 @ref RMU_FRST0_Peripheral.
+ * @retval int32_t:
+ * - LL_OK: Reset success.
+ * - LL_ERR_TIMEOUT: Reset time out.
+ * @note Call LL_PERIPH_WE(LL_PERIPH_PWC_CLK_RMU) unlock RMU_FRSTx register first.
+ */
+int32_t RMU_Frst0PeriphReset(uint32_t u32Frst0Periph)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint8_t u8TimeOut = 0U;
+ /* Check RMU register protect */
+ DDL_ASSERT(IS_RMU_UNLOCKED());
+ DDL_ASSERT(IS_FRST0_PERIPH(u32Frst0Periph));
+
+ /* Reset */
+ CLR_REG32_BIT(CM_RMU->FRST0, u32Frst0Periph);
+ /* Ensure reset procedure is completed */
+ while (u32Frst0Periph != READ_REG32_BIT(CM_RMU->FRST0, u32Frst0Periph)) {
+ u8TimeOut++;
+ if (u8TimeOut > RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Reset FRST1 peripheral.
+ * @param [in] u32Frst1Periph The peripheral in FRST1 @ref RMU_FRST1_Peripheral.
+ * @retval int32_t:
+ * - LL_OK: Reset success.
+ * - LL_ERR_TIMEOUT: Reset time out.
+ * @note Call LL_PERIPH_WE(LL_PERIPH_PWC_CLK_RMU) unlock RMU_FRSTx register first.
+ */
+int32_t RMU_Frst1PeriphReset(uint32_t u32Frst1Periph)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint8_t u8TimeOut = 0U;
+ /* Check RMU register protect */
+ DDL_ASSERT(IS_RMU_UNLOCKED());
+ DDL_ASSERT(IS_FRST1_PERIPH(u32Frst1Periph));
+
+ /* Reset */
+ CLR_REG32_BIT(CM_RMU->FRST1, u32Frst1Periph);
+ /* Ensure reset procedure is completed */
+ while (u32Frst1Periph != READ_REG32_BIT(CM_RMU->FRST1, u32Frst1Periph)) {
+ u8TimeOut++;
+ if (u8TimeOut > RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Reset FRST2 peripheral.
+ * @param [in] u32Frst2Periph The peripheral in FRST2 @ref RMU_FRST2_Peripheral.
+ * @retval int32_t:
+ * - LL_OK: Reset success.
+ * - LL_ERR_TIMEOUT: Reset time out.
+ * @note Call LL_PERIPH_WE(LL_PERIPH_PWC_CLK_RMU) unlock RMU_FRSTx register first.
+ */
+int32_t RMU_Frst2PeriphReset(uint32_t u32Frst2Periph)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint8_t u8TimeOut = 0U;
+ /* Check RMU register protect */
+ DDL_ASSERT(IS_RMU_UNLOCKED());
+ DDL_ASSERT(IS_FRST2_PERIPH(u32Frst2Periph));
+
+ /* Reset */
+ CLR_REG32_BIT(CM_RMU->FRST2, u32Frst2Periph);
+ /* Ensure reset procedure is completed */
+ while (u32Frst2Periph != READ_REG32_BIT(CM_RMU->FRST2, u32Frst2Periph)) {
+ u8TimeOut++;
+ if (u8TimeOut > RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Reset FRST3 peripheral.
+ * @param [in] u32Frst3Periph The peripheral in FRST3 @ref RMU_FRST3_Peripheral.
+ * @retval int32_t:
+ * - LL_OK: Reset success.
+ * - LL_ERR_TIMEOUT: Reset time out.
+ * @note Call LL_PERIPH_WE(LL_PERIPH_PWC_CLK_RMU) unlock RMU_FRSTx register first.
+ */
+int32_t RMU_Frst3PeriphReset(uint32_t u32Frst3Periph)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint8_t u8TimeOut = 0U;
+ /* Check RMU register protect */
+ DDL_ASSERT(IS_RMU_UNLOCKED());
+ DDL_ASSERT(IS_FRST3_PERIPH(u32Frst3Periph));
+
+ /* Reset */
+ CLR_REG32_BIT(CM_RMU->FRST3, u32Frst3Periph);
+ /* Ensure reset procedure is completed */
+ while (u32Frst3Periph != READ_REG32_BIT(CM_RMU->FRST3, u32Frst3Periph)) {
+ u8TimeOut++;
+ if (u8TimeOut > RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_RMU_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_rtc.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_rtc.c
new file mode 100644
index 0000000000..a359d9d647
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_rtc.c
@@ -0,0 +1,946 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_rtc.c
+ * @brief This file provides firmware functions to manage the Real-Time
+ * Clock(RTC).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Add PWC_FPRC.FPRCB1 assert in RTC_Init and RTC_SetClockSrc functions
+ Delete intrusion function
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_rtc.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_RTC RTC
+ * @brief Real-Time Clock Driver Library
+ * @{
+ */
+
+#if (LL_RTC_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup RTC_Local_Macros RTC Local Macros
+ * @{
+ */
+
+/* RTC software reset timeout(ms) */
+#define RTC_SW_RST_TIMEOUT (100UL)
+/* RTC mode switch timeout(ms) */
+#define RTC_MD_SWITCH_TIMEOUT (100UL)
+
+/**
+ * @defgroup RTC_Check_Parameters_Validity RTC Check Parameters Validity
+ * @{
+ */
+#define IS_RTC_DATA_FMT(x) \
+( ((x) == RTC_DATA_FMT_DEC) || \
+ ((x) == RTC_DATA_FMT_BCD))
+
+#define IS_RTC_CLK_SRC(x) \
+( ((x) == RTC_CLK_SRC_XTAL32) || \
+ ((x) == RTC_CLK_SRC_LRC) || \
+ ((x) == RTC_CLK_SRC_EXTCLK) || \
+ ((x) == RTC_CLK_SRC_XTAL_DIV))
+
+#define IS_RTC_HOUR_FMT(x) \
+( ((x) == RTC_HOUR_FMT_12H) || \
+ ((x) == RTC_HOUR_FMT_24H))
+
+#define IS_RTC_INT_PERIOD(x) \
+( ((x) == RTC_INT_PERIOD_INVD) || \
+ ((x) == RTC_INT_PERIOD_PER_HALF_SEC) || \
+ ((x) == RTC_INT_PERIOD_PER_SEC) || \
+ ((x) == RTC_INT_PERIOD_PER_MINUTE) || \
+ ((x) == RTC_INT_PERIOD_PER_HOUR) || \
+ ((x) == RTC_INT_PERIOD_PER_DAY) || \
+ ((x) == RTC_INT_PERIOD_PER_MONTH))
+
+#define IS_RTC_CLK_COMPEN(x) \
+( ((x) == RTC_CLK_COMPEN_DISABLE) || \
+ ((x) == RTC_CLK_COMPEN_ENABLE))
+
+#define IS_RTC_CLK_COMPEN_MD(x) \
+( ((x) == RTC_CLK_COMPEN_MD_DISTRIBUTED) || \
+ ((x) == RTC_CLK_COMPEN_MD_UNIFORM))
+
+#define IS_RTC_HOUR_12H_AM_PM(x) \
+( ((x) == RTC_HOUR_12H_AM) || \
+ ((x) == RTC_HOUR_12H_PM))
+
+#define IS_RTC_GET_FLAG(x) \
+( ((x) != 0U) && \
+ (((x) | RTC_FLAG_ALL) == RTC_FLAG_ALL))
+
+#define IS_RTC_CLR_FLAG(x) \
+( ((x) != 0U) && \
+ (((x) | RTC_FLAG_CLR_ALL) == RTC_FLAG_CLR_ALL))
+
+#define IS_RTC_INT(x) \
+( ((x) != 0U) && \
+ (((x) | RTC_INT_ALL) == RTC_INT_ALL))
+
+#define IS_RTC_YEAR(x) ((x) <= 99U)
+
+#define IS_RTC_MONTH(x) (((x) >= 1U) && ((x) <= 12U))
+
+#define IS_RTC_DAY(x) (((x) >= 1U) && ((x) <= 31U))
+
+#define IS_RTC_HOUR_12H(x) (((x) >= 1U) && ((x) <= 12U))
+
+#define IS_RTC_HOUR_24H(x) ((x) <= 23U)
+
+#define IS_RTC_MINUTE(x) ((x) <= 59U)
+
+#define IS_RTC_SEC(x) ((x) <= 59U)
+
+#define IS_RTC_WEEKDAY(x) ((x) <= 6U)
+
+#define IS_RTC_ALARM_WEEKDAY(x) (((x) >= 0x01U) && ((x) <= 0x7FU))
+
+#define IS_RTC_COMPEN_VALUE(x) ((x) <= 0x1FFU)
+
+#define IS_RTC_PWC_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup RTC_Global_Functions RTC Global Functions
+ * @{
+ */
+
+/**
+ * @brief De-Initialize RTC.
+ * @param None
+ * @retval int32_t:
+ * - LL_OK: De-Initialize success
+ * - LL_ERR_TIMEOUT: De-Initialize timeout
+ */
+int32_t RTC_DeInit(void)
+{
+ __IO uint32_t u32Count;
+ int32_t i32Ret = LL_OK;
+
+ WRITE_REG32(bCM_RTC->CR0_b.RESET, RESET);
+ /* Waiting for normal count status or end of RTC software reset */
+ u32Count = RTC_SW_RST_TIMEOUT * (HCLK_VALUE / 20000UL);
+ while (0UL != READ_REG32(bCM_RTC->CR0_b.RESET)) {
+ if (0UL == u32Count) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ u32Count--;
+ }
+
+ if (LL_OK == i32Ret) {
+ /* Reset all RTC registers */
+ WRITE_REG32(bCM_RTC->CR0_b.RESET, SET);
+ /* Waiting for RTC software reset to complete */
+ u32Count = RTC_SW_RST_TIMEOUT * (HCLK_VALUE / 20000UL);
+ while (0UL != READ_REG32(bCM_RTC->CR0_b.RESET)) {
+ if (0UL == u32Count) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ u32Count--;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize RTC.
+ * @param [in] pstcRtcInit Pointer to a @ref stc_rtc_init_t structure
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t RTC_Init(const stc_rtc_init_t *pstcRtcInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcRtcInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Check parameters */
+ DDL_ASSERT(IS_RTC_CLK_SRC(pstcRtcInit->u8ClockSrc));
+ DDL_ASSERT(IS_RTC_HOUR_FMT(pstcRtcInit->u8HourFormat));
+ DDL_ASSERT(IS_RTC_INT_PERIOD(pstcRtcInit->u8IntPeriod));
+ DDL_ASSERT(IS_RTC_CLK_COMPEN(pstcRtcInit->u8ClockCompen));
+ DDL_ASSERT(IS_RTC_COMPEN_VALUE(pstcRtcInit->u16CompenValue));
+ DDL_ASSERT(IS_RTC_CLK_COMPEN_MD(pstcRtcInit->u8CompenMode));
+ DDL_ASSERT(IS_RTC_PWC_UNLOCKED());
+
+ /* RTC CR3 Configuration */
+ MODIFY_REG8(CM_RTC->CR3, (RTC_CR3_LRCEN | RTC_CR3_RCKSEL), pstcRtcInit->u8ClockSrc & (RTC_CR3_LRCEN | RTC_CR3_RCKSEL));
+ MODIFY_REG8(CM_PWC->PWRC6, PWC_PWRC6_RTCCKSEL, pstcRtcInit->u8ClockSrc & PWC_PWRC6_RTCCKSEL);
+ /* RTC CR1 Configuration */
+ MODIFY_REG8(CM_RTC->CR1, (RTC_CR1_PRDS | RTC_CR1_AMPM | RTC_CR1_ONEHZSEL),
+ (pstcRtcInit->u8IntPeriod | pstcRtcInit->u8HourFormat | pstcRtcInit->u8CompenMode));
+ /* RTC Compensation Configuration */
+ MODIFY_REG8(CM_RTC->ERRCRH, (RTC_ERRCRH_COMPEN | RTC_ERRCRH_COMP8),
+ (pstcRtcInit->u8ClockCompen | (uint8_t)((pstcRtcInit->u16CompenValue >> 8U) & 0x01U)));
+ WRITE_REG8(CM_RTC->ERRCRL, (uint8_t)(pstcRtcInit->u16CompenValue & 0xFFU));
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Fills each stc_rtc_init_t member with default value.
+ * @param [out] pstcRtcInit Pointer to a @ref stc_rtc_init_t structure
+ * @retval int32_t:
+ * - LL_OK: stc_rtc_init_t member initialize success
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t RTC_StructInit(stc_rtc_init_t *pstcRtcInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcRtcInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ pstcRtcInit->u8ClockSrc = RTC_CLK_SRC_LRC;
+ pstcRtcInit->u8HourFormat = RTC_HOUR_FMT_24H;
+ pstcRtcInit->u8IntPeriod = RTC_INT_PERIOD_INVD;
+ pstcRtcInit->u8ClockCompen = RTC_CLK_COMPEN_DISABLE;
+ pstcRtcInit->u8CompenMode = RTC_CLK_COMPEN_MD_DISTRIBUTED;
+ pstcRtcInit->u16CompenValue = 0U;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Enter RTC read/write mode.
+ * @param None
+ * @retval int32_t:
+ * - LL_OK: Enter mode success
+ * - LL_ERR_TIMEOUT: Enter mode timeout
+ */
+int32_t RTC_EnterRwMode(void)
+{
+ __IO uint32_t u32Count;
+ int32_t i32Ret = LL_OK;
+
+ /* Mode switch when RTC is running */
+ if (0UL != READ_REG32(bCM_RTC->CR1_b.START)) {
+ if (1UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) {
+ WRITE_REG32(bCM_RTC->CR2_b.RWREQ, SET);
+ /* Waiting for RWEN bit set */
+ u32Count = RTC_MD_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL);
+ while (1UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) {
+ if (0UL == u32Count) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ u32Count--;
+ }
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Exit RTC read/write mode.
+ * @param None
+ * @retval int32_t:
+ * - LL_OK: Exit mode success
+ * - LL_ERR_TIMEOUT: Exit mode timeout
+ */
+int32_t RTC_ExitRwMode(void)
+{
+ __IO uint32_t u32Count;
+ int32_t i32Ret = LL_OK;
+
+ /* Mode switch when RTC is running */
+ if (0UL != READ_REG32(bCM_RTC->CR1_b.START)) {
+ if (0UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) {
+ WRITE_REG32(bCM_RTC->CR2_b.RWREQ, RESET);
+ /* Waiting for RWEN bit reset */
+ u32Count = RTC_MD_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL);
+ while (0UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) {
+ if (0UL == u32Count) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ u32Count--;
+ }
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Confirm the condition for RTC to enter low power mode.
+ * @param None
+ * @retval int32_t:
+ * - LL_OK: Can enter low power mode
+ * - LL_ERR_TIMEOUT: Can't enter low power mode
+ */
+int32_t RTC_ConfirmLPMCond(void)
+{
+ __IO uint32_t u32Count;
+ int32_t i32Ret = LL_OK;
+
+ /* Check RTC work status */
+ if (0UL != READ_REG32(bCM_RTC->CR1_b.START)) {
+ WRITE_REG32(bCM_RTC->CR2_b.RWREQ, SET);
+ /* Waiting for RTC RWEN bit set */
+ u32Count = RTC_MD_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL);
+ while (1UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) {
+ if (0UL == u32Count) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ u32Count--;
+ }
+
+ if (LL_OK == i32Ret) {
+ WRITE_REG32(bCM_RTC->CR2_b.RWREQ, RESET);
+ /* Waiting for RTC RWEN bit reset */
+ u32Count = RTC_MD_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL);
+ while (0UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) {
+ if (0UL == u32Count) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ u32Count--;
+ }
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set the RTC interrupt period.
+ * @param [in] u8Period Specifies the interrupt period.
+ * This parameter can be one of the following values:
+ * @arg RTC_INT_PERIOD_INVD: Period interrupt invalid
+ * @arg RTC_INT_PERIOD_PER_HALF_SEC: Interrupt per half second
+ * @arg RTC_INT_PERIOD_PER_SEC: Interrupt per second
+ * @arg RTC_INT_PERIOD_PER_MINUTE: Interrupt per minute
+ * @arg RTC_INT_PERIOD_PER_HOUR: Interrupt per hour
+ * @arg RTC_INT_PERIOD_PER_DAY: Interrupt per day
+ * @arg RTC_INT_PERIOD_PER_MONTH: Interrupt per month
+ * @retval None
+ */
+void RTC_SetIntPeriod(uint8_t u8Period)
+{
+ uint32_t u32RtcSta;
+ uint32_t u32IntSta;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_RTC_INT_PERIOD(u8Period));
+
+ u32RtcSta = READ_REG32(bCM_RTC->CR1_b.START);
+ u32IntSta = READ_REG32(bCM_RTC->CR2_b.PRDIE);
+ /* Disable period interrupt when START=1 and clear period flag after write */
+ if ((0UL != u32IntSta) && (0UL != u32RtcSta)) {
+ WRITE_REG32(bCM_RTC->CR2_b.PRDIE, RESET);
+ }
+
+ /* RTC CR1 Configuration */
+ MODIFY_REG8(CM_RTC->CR1, RTC_CR1_PRDS, u8Period);
+ WRITE_REG32(bCM_RTC->CR2_b.PRDF, RESET);
+
+ if ((0UL != u32IntSta) && (0UL != u32RtcSta)) {
+ WRITE_REG32(bCM_RTC->CR2_b.PRDIE, SET);
+ }
+}
+
+/**
+ * @brief Set the RTC clock source.
+ * @param [in] u8Src Specifies the clock source.
+ * This parameter can be one of the following values:
+ * @arg @ref RTC_Clock_Source
+ * @retval None
+ */
+void RTC_SetClockSrc(uint8_t u8Src)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_RTC_CLK_SRC(u8Src));
+ DDL_ASSERT(IS_RTC_PWC_UNLOCKED());
+
+ MODIFY_REG8(CM_RTC->CR3, (RTC_CR3_LRCEN | RTC_CR3_RCKSEL), u8Src & (RTC_CR3_LRCEN | RTC_CR3_RCKSEL));
+ MODIFY_REG8(CM_PWC->PWRC6, PWC_PWRC6_RTCCKSEL, u8Src & PWC_PWRC6_RTCCKSEL);
+}
+
+/**
+ * @brief Set RTC clock compensation value.
+ * @param [in] u16Value Specifies the clock compensation value of RTC.
+ * @arg This parameter can be a number between Min_Data = 0 and Max_Data = 0x1FF.
+ * @retval None
+ */
+void RTC_SetClockCompenValue(uint16_t u16Value)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_RTC_COMPEN_VALUE(u16Value));
+
+ WRITE_REG32(bCM_RTC->ERRCRH_b.COMP8, ((uint32_t)u16Value >> 8U) & 0x01U);
+ WRITE_REG8(CM_RTC->ERRCRL, (uint8_t)(u16Value & 0x00FFU));
+}
+
+/**
+ * @brief Get RTC counter status.
+ * @param None
+ * @retval An @ref en_functional_state_t enumeration value.
+ * - ENABLE: RTC counter started
+ * - DISABLE: RTC counter stopped
+ */
+en_functional_state_t RTC_GetCounterState(void)
+{
+ en_functional_state_t enState = DISABLE;
+
+ if (0UL != READ_REG32(bCM_RTC->CR1_b.START)) {
+ enState = ENABLE;
+ }
+
+ return enState;
+}
+
+/**
+ * @brief Enable or disable RTC count.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void RTC_Cmd(en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ WRITE_REG32(bCM_RTC->CR1_b.START, enNewState);
+}
+
+/**
+ * @brief Enable or disable RTC LRC function.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void RTC_LrcCmd(en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ WRITE_REG32(bCM_RTC->CR3_b.LRCEN, enNewState);
+}
+
+/**
+ * @brief Enable or disable RTC 1HZ output.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void RTC_OneHzOutputCmd(en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ WRITE_REG32(bCM_RTC->CR1_b.ONEHZOE, enNewState);
+}
+
+/**
+ * @brief Enable or disable clock compensation.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void RTC_ClockCompenCmd(en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ WRITE_REG32(bCM_RTC->ERRCRH_b.COMPEN, enNewState);
+}
+
+/**
+ * @brief Set RTC current date.
+ * @param [in] u8Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_DATA_FMT_DEC: Decimal data format
+ * @arg RTC_DATA_FMT_BCD: BCD data format
+ * @param [in] pstcRtcDate Pointer to a @ref stc_rtc_date_t structure
+ * @retval int32_t:
+ * - LL_OK: Set date success
+ * - LL_ERR: Set date failed
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t RTC_SetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcRtcDate) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Check parameters */
+ DDL_ASSERT(IS_RTC_DATA_FMT(u8Format));
+ if (RTC_DATA_FMT_DEC != u8Format) {
+ DDL_ASSERT(IS_RTC_YEAR(RTC_BCD2DEC(pstcRtcDate->u8Year)));
+ DDL_ASSERT(IS_RTC_MONTH(RTC_BCD2DEC(pstcRtcDate->u8Month)));
+ DDL_ASSERT(IS_RTC_DAY(RTC_BCD2DEC(pstcRtcDate->u8Day)));
+ } else {
+ DDL_ASSERT(IS_RTC_YEAR(pstcRtcDate->u8Year));
+ DDL_ASSERT(IS_RTC_MONTH(pstcRtcDate->u8Month));
+ DDL_ASSERT(IS_RTC_DAY(pstcRtcDate->u8Day));
+ }
+ DDL_ASSERT(IS_RTC_WEEKDAY(pstcRtcDate->u8Weekday));
+
+ /* Enter read/write mode */
+ if (LL_OK != RTC_EnterRwMode()) {
+ i32Ret = LL_ERR;
+ } else {
+ if (RTC_DATA_FMT_DEC == u8Format) {
+ pstcRtcDate->u8Year = RTC_DEC2BCD(pstcRtcDate->u8Year);
+ pstcRtcDate->u8Month = RTC_DEC2BCD(pstcRtcDate->u8Month);
+ pstcRtcDate->u8Day = RTC_DEC2BCD(pstcRtcDate->u8Day);
+ }
+
+ WRITE_REG8(CM_RTC->YEAR, pstcRtcDate->u8Year);
+ WRITE_REG8(CM_RTC->MON, pstcRtcDate->u8Month);
+ WRITE_REG8(CM_RTC->DAY, pstcRtcDate->u8Day);
+ WRITE_REG8(CM_RTC->WEEK, pstcRtcDate->u8Weekday);
+
+ /* Exit read/write mode */
+ if (LL_OK != RTC_ExitRwMode()) {
+ i32Ret = LL_ERR;
+ }
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Get RTC current date.
+ * @param [in] u8Format Specifies the format of the returned parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_DATA_FMT_DEC: Decimal data format
+ * @arg RTC_DATA_FMT_BCD: BCD data format
+ * @param [out] pstcRtcDate Pointer to a @ref stc_rtc_date_t structure
+ * @retval int32_t:
+ * - LL_OK: Get date success
+ * - LL_ERR: Get date failed
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t RTC_GetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcRtcDate) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Check parameters */
+ DDL_ASSERT(IS_RTC_DATA_FMT(u8Format));
+ /* Enter read/write mode */
+ if (LL_OK != RTC_EnterRwMode()) {
+ i32Ret = LL_ERR;
+ } else {
+ /* Get RTC date registers */
+ pstcRtcDate->u8Year = READ_REG8(CM_RTC->YEAR);
+ pstcRtcDate->u8Month = READ_REG8(CM_RTC->MON);
+ pstcRtcDate->u8Day = READ_REG8(CM_RTC->DAY);
+ pstcRtcDate->u8Weekday = READ_REG8(CM_RTC->WEEK);
+
+ /* Check decimal format*/
+ if (RTC_DATA_FMT_DEC == u8Format) {
+ pstcRtcDate->u8Year = RTC_BCD2DEC(pstcRtcDate->u8Year);
+ pstcRtcDate->u8Month = RTC_BCD2DEC(pstcRtcDate->u8Month);
+ pstcRtcDate->u8Day = RTC_BCD2DEC(pstcRtcDate->u8Day);
+ }
+
+ /* exit read/write mode */
+ if (LL_OK != RTC_ExitRwMode()) {
+ i32Ret = LL_ERR;
+ }
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set RTC current time.
+ * @param [in] u8Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_DATA_FMT_DEC: Decimal data format
+ * @arg RTC_DATA_FMT_BCD: BCD data format
+ * @param [in] pstcRtcTime Pointer to a @ref stc_rtc_time_t structure
+ * @retval int32_t:
+ * - LL_OK: Set time success
+ * - LL_ERR: Set time failed
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t RTC_SetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcRtcTime) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Check parameters */
+ DDL_ASSERT(IS_RTC_DATA_FMT(u8Format));
+ if (RTC_DATA_FMT_DEC != u8Format) {
+ if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) {
+ DDL_ASSERT(IS_RTC_HOUR_12H(RTC_BCD2DEC(pstcRtcTime->u8Hour)));
+ DDL_ASSERT(IS_RTC_HOUR_12H_AM_PM(pstcRtcTime->u8AmPm));
+ } else {
+ DDL_ASSERT(IS_RTC_HOUR_24H(RTC_BCD2DEC(pstcRtcTime->u8Hour)));
+ }
+ DDL_ASSERT(IS_RTC_MINUTE(RTC_BCD2DEC(pstcRtcTime->u8Minute)));
+ DDL_ASSERT(IS_RTC_SEC(RTC_BCD2DEC(pstcRtcTime->u8Second)));
+ } else {
+ if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) {
+ DDL_ASSERT(IS_RTC_HOUR_12H(pstcRtcTime->u8Hour));
+ DDL_ASSERT(IS_RTC_HOUR_12H_AM_PM(pstcRtcTime->u8AmPm));
+ } else {
+ DDL_ASSERT(IS_RTC_HOUR_24H(pstcRtcTime->u8Hour));
+ }
+ DDL_ASSERT(IS_RTC_MINUTE(pstcRtcTime->u8Minute));
+ DDL_ASSERT(IS_RTC_SEC(pstcRtcTime->u8Second));
+ }
+
+ /* Enter read/write mode */
+ if (LL_OK != RTC_EnterRwMode()) {
+ i32Ret = LL_ERR;
+ } else {
+ if (RTC_DATA_FMT_DEC == u8Format) {
+ pstcRtcTime->u8Hour = RTC_DEC2BCD(pstcRtcTime->u8Hour);
+ pstcRtcTime->u8Minute = RTC_DEC2BCD(pstcRtcTime->u8Minute);
+ pstcRtcTime->u8Second = RTC_DEC2BCD(pstcRtcTime->u8Second);
+ }
+ if ((RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) &&
+ (RTC_HOUR_12H_PM == pstcRtcTime->u8AmPm)) {
+ SET_REG8_BIT(pstcRtcTime->u8Hour, RTC_HOUR_12H_PM);
+ }
+
+ WRITE_REG8(CM_RTC->HOUR, pstcRtcTime->u8Hour);
+ WRITE_REG8(CM_RTC->MIN, pstcRtcTime->u8Minute);
+ WRITE_REG8(CM_RTC->SEC, pstcRtcTime->u8Second);
+
+ /* Exit read/write mode */
+ if (LL_OK != RTC_ExitRwMode()) {
+ i32Ret = LL_ERR;
+ }
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Get RTC current time.
+ * @param [in] u8Format Specifies the format of the returned parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_DATA_FMT_DEC: Decimal data format
+ * @arg RTC_DATA_FMT_BCD: BCD data format
+ * @param [out] pstcRtcTime Pointer to a @ref stc_rtc_time_t structure
+ * @retval int32_t:
+ * - LL_OK: Get time success
+ * - LL_ERR: Get time failed
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t RTC_GetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcRtcTime) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Check parameters */
+ DDL_ASSERT(IS_RTC_DATA_FMT(u8Format));
+ /* Enter read/write mode */
+ if (LL_OK != RTC_EnterRwMode()) {
+ i32Ret = LL_ERR;
+ } else {
+ /* Get RTC time registers */
+ pstcRtcTime->u8Hour = READ_REG8(CM_RTC->HOUR);
+ pstcRtcTime->u8Minute = READ_REG8(CM_RTC->MIN);
+ pstcRtcTime->u8Second = READ_REG8(CM_RTC->SEC);
+
+ if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) {
+ if (RTC_HOUR_12H_PM == (pstcRtcTime->u8Hour & RTC_HOUR_12H_PM)) {
+ CLR_REG8_BIT(pstcRtcTime->u8Hour, RTC_HOUR_12H_PM);
+ pstcRtcTime->u8AmPm = RTC_HOUR_12H_PM;
+ } else {
+ pstcRtcTime->u8AmPm = RTC_HOUR_12H_AM;
+ }
+ } else {
+ pstcRtcTime->u8AmPm = RTC_HOUR_24H;
+ }
+
+ /* Check decimal format*/
+ if (RTC_DATA_FMT_DEC == u8Format) {
+ pstcRtcTime->u8Hour = RTC_BCD2DEC(pstcRtcTime->u8Hour);
+ pstcRtcTime->u8Minute = RTC_BCD2DEC(pstcRtcTime->u8Minute);
+ pstcRtcTime->u8Second = RTC_BCD2DEC(pstcRtcTime->u8Second);
+ }
+
+ /* exit read/write mode */
+ if (LL_OK != RTC_ExitRwMode()) {
+ i32Ret = LL_ERR;
+ }
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set RTC alarm time.
+ * @param [in] u8Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_DATA_FMT_DEC: Decimal data format
+ * @arg RTC_DATA_FMT_BCD: BCD data format
+ * @param [in] pstcRtcAlarm Pointer to a @ref stc_rtc_alarm_t structure
+ * @retval int32_t:
+ * - LL_OK: Set RTC alarm time success
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t RTC_SetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcRtcAlarm) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Check parameters */
+ DDL_ASSERT(IS_RTC_DATA_FMT(u8Format));
+ if (RTC_DATA_FMT_DEC != u8Format) {
+ if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) {
+ DDL_ASSERT(IS_RTC_HOUR_12H(RTC_BCD2DEC(pstcRtcAlarm->u8AlarmHour)));
+ DDL_ASSERT(IS_RTC_HOUR_12H_AM_PM(pstcRtcAlarm->u8AlarmAmPm));
+ } else {
+ DDL_ASSERT(IS_RTC_HOUR_24H(RTC_BCD2DEC(pstcRtcAlarm->u8AlarmHour)));
+ }
+ DDL_ASSERT(IS_RTC_MINUTE(RTC_BCD2DEC(pstcRtcAlarm->u8AlarmMinute)));
+ } else {
+ if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) {
+ DDL_ASSERT(IS_RTC_HOUR_12H(pstcRtcAlarm->u8AlarmHour));
+ DDL_ASSERT(IS_RTC_HOUR_12H_AM_PM(pstcRtcAlarm->u8AlarmAmPm));
+ } else {
+ DDL_ASSERT(IS_RTC_HOUR_24H(pstcRtcAlarm->u8AlarmHour));
+ }
+ DDL_ASSERT(IS_RTC_MINUTE(pstcRtcAlarm->u8AlarmMinute));
+ }
+ DDL_ASSERT(IS_RTC_ALARM_WEEKDAY(pstcRtcAlarm->u8AlarmWeekday));
+
+ /* Configure alarm registers */
+ if (RTC_DATA_FMT_DEC == u8Format) {
+ pstcRtcAlarm->u8AlarmHour = RTC_DEC2BCD(pstcRtcAlarm->u8AlarmHour);
+ pstcRtcAlarm->u8AlarmMinute = RTC_DEC2BCD(pstcRtcAlarm->u8AlarmMinute);
+ }
+ if ((RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) &&
+ (RTC_HOUR_12H_PM == pstcRtcAlarm->u8AlarmAmPm)) {
+ SET_REG8_BIT(pstcRtcAlarm->u8AlarmHour, RTC_HOUR_12H_PM);
+ }
+
+ WRITE_REG8(CM_RTC->ALMHOUR, pstcRtcAlarm->u8AlarmHour);
+ WRITE_REG8(CM_RTC->ALMMIN, pstcRtcAlarm->u8AlarmMinute);
+ WRITE_REG8(CM_RTC->ALMWEEK, pstcRtcAlarm->u8AlarmWeekday);
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Get RTC alarm time.
+ * @param [in] u8Format Specifies the format of the returned parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_DATA_FMT_DEC: Decimal data format
+ * @arg RTC_DATA_FMT_BCD: BCD data format
+ * @param [out] pstcRtcAlarm Pointer to a @ref stc_rtc_alarm_t structure
+ * @retval int32_t:
+ * - LL_OK: Get RTC alarm time success
+ * - LL_ERR_INVD_PARAM: Invalid parameter
+ */
+int32_t RTC_GetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcRtcAlarm) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Check parameters */
+ DDL_ASSERT(IS_RTC_DATA_FMT(u8Format));
+
+ /* Get RTC date and time register */
+ pstcRtcAlarm->u8AlarmWeekday = READ_REG8(CM_RTC->ALMWEEK);
+ pstcRtcAlarm->u8AlarmMinute = READ_REG8(CM_RTC->ALMMIN);
+ pstcRtcAlarm->u8AlarmHour = READ_REG8(CM_RTC->ALMHOUR);
+
+ if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) {
+ if (RTC_HOUR_12H_PM == (pstcRtcAlarm->u8AlarmHour & RTC_HOUR_12H_PM)) {
+ CLR_REG8_BIT(pstcRtcAlarm->u8AlarmHour, RTC_HOUR_12H_PM);
+ pstcRtcAlarm->u8AlarmAmPm = RTC_HOUR_12H_PM;
+ } else {
+ pstcRtcAlarm->u8AlarmAmPm = RTC_HOUR_12H_AM;
+ }
+ } else {
+ pstcRtcAlarm->u8AlarmAmPm = RTC_HOUR_24H;
+ }
+
+ /* Check decimal format*/
+ if (RTC_DATA_FMT_DEC == u8Format) {
+ pstcRtcAlarm->u8AlarmHour = RTC_BCD2DEC(pstcRtcAlarm->u8AlarmHour);
+ pstcRtcAlarm->u8AlarmMinute = RTC_BCD2DEC(pstcRtcAlarm->u8AlarmMinute);
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Enable or disable RTC alarm.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void RTC_AlarmCmd(en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ WRITE_REG32(bCM_RTC->CR2_b.ALME, enNewState);
+}
+
+/**
+ * @brief Enable or disable specified RTC interrupt.
+ * @param [in] u32IntType Specifies the RTC interrupt source.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref RTC_Interrupt
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void RTC_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState)
+{
+ uint32_t u32IntTemp;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_RTC_INT(u32IntType));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u32IntTemp = u32IntType & 0x0000FFUL;
+ if (0UL != u32IntTemp) {
+ if (DISABLE != enNewState) {
+ SET_REG8_BIT(CM_RTC->CR2, u32IntTemp);
+ } else {
+ CLR_REG8_BIT(CM_RTC->CR2, u32IntTemp);
+ }
+ }
+
+}
+
+/**
+ * @brief Get RTC flag status.
+ * @param [in] u32Flag Specifies the RTC flag type.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref RTC_Flag
+ * @arg RTC_FLAG_ALL: All of the above
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t RTC_GetStatus(uint32_t u32Flag)
+{
+ uint8_t u8FlagTemp;
+ en_flag_status_t enFlagSta = RESET;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_RTC_GET_FLAG(u32Flag));
+
+ u8FlagTemp = (uint8_t)(u32Flag & 0xFFU);
+ if (0U != u8FlagTemp) {
+ if (0U != (READ_REG8_BIT(CM_RTC->CR2, u8FlagTemp))) {
+ enFlagSta = SET;
+ }
+ }
+
+ return enFlagSta;
+}
+
+/**
+ * @brief Clear RTC flag.
+ * @param [in] u32Flag Specifies the RTC flag type.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref RTC_Flag
+ * @arg RTC_FLAG_CLR_ALL: All of the above
+ * @retval None
+ */
+void RTC_ClearStatus(uint32_t u32Flag)
+{
+ uint8_t u8FlagTemp;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_RTC_CLR_FLAG(u32Flag));
+
+ u8FlagTemp = (uint8_t)(u32Flag & 0xFFU);
+ if (0U != u8FlagTemp) {
+ CLR_REG8_BIT(CM_RTC->CR2, u8FlagTemp);
+ }
+
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_RTC_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_smc.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_smc.c
new file mode 100644
index 0000000000..622261fefd
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_smc.c
@@ -0,0 +1,527 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_smc.c
+ * @brief This file provides firmware functions to manage the EXMC_SMC
+ * (External Memory Controller: Static Memory Controller).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT EXMC_SMC_Init add assert for pstcSmcInit->stcTimingConfig.u8PC
+ Optimize function: EXMC_SMC_DeInit
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_smc.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_EXMC EXMC
+ * @brief External Memory Controller Driver Library
+ * @{
+ */
+
+/**
+ * @defgroup LL_SMC SMC
+ * @brief Static Memory Controller Driver Library
+ * @{
+ */
+
+#if (LL_SMC_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup EXMC_SMC_Local_Macros EXMC_SMC Local Macros
+ * @{
+ */
+
+/**
+ * @defgroup EXMC_SMC_Check_Parameters_Validity EXMC_SMC Check Parameters Validity
+ * @{
+ */
+
+#define IS_EXMC_SMC_MEMORY_WIDTH(x) \
+( ((x) == EXMC_SMC_MEMORY_WIDTH_16BIT) || \
+ ((x) == EXMC_SMC_MEMORY_WIDTH_32BIT))
+
+#define IS_EXMC_SMC_READ_MD(x) \
+( ((x) == EXMC_SMC_READ_SYNC) || \
+ ((x) == EXMC_SMC_READ_ASYNC))
+
+#define IS_EXMC_SMC_WRITE_MD(x) \
+( ((x) == EXMC_SMC_WRITE_SYNC) || \
+ ((x) == EXMC_SMC_WRITE_ASYNC))
+
+#define IS_EXMC_SMC_CHIP(x) \
+( ((x) == EXMC_SMC_CHIP0) || \
+ ((x) == EXMC_SMC_CHIP1) || \
+ ((x) == EXMC_SMC_CHIP2) || \
+ ((x) == EXMC_SMC_CHIP3))
+
+#define IS_EXMC_SMC_BLS_SYNC(x) \
+( ((x) == EXMC_SMC_BLS_SYNC_CS) || \
+ ((x) == EXMC_SMC_BLS_SYNC_WE))
+
+#define IS_EXMC_SMC_BAA_PORT(x) \
+( ((x) == EXMC_SMC_BAA_PORT_DISABLE) || \
+ ((x) == EXMC_SMC_BAA_PORT_ENABLE))
+
+#define IS_EXMC_SMC_ADV_PORT(x) \
+( ((x) == EXMC_SMC_ADV_PORT_DISABLE) || \
+ ((x) == EXMC_SMC_ADV_PORT_ENABLE))
+
+#define IS_EXMC_SMC_CMD(x) \
+( ((x) == EXMC_SMC_CMD_MDREGCONFIG) || \
+ ((x) == EXMC_SMC_CMD_UPDATEREGS) || \
+ ((x) == EXMC_SMC_CMD_MDREGCONFIG_AND_UPDATEREGS))
+
+#define IS_EXMC_SMC_CRE_POLARITY(x) \
+( ((x) == EXMC_SMC_CRE_POLARITY_LOW) || \
+ ((x) == EXMC_SMC_CRE_POLARITY_HIGH))
+
+#define IS_EXMC_SMC_SAMPLE_CLK(x) \
+( ((x) == EXMC_SMC_SAMPLE_CLK_INTERNCLK) || \
+ ((x) == EXMC_SMC_SAMPLE_CLK_INTERNCLK_INVT) || \
+ ((x) == EXMC_SMC_SAMPLE_CLK_EXTCLK))
+
+#define IS_EXMC_SMC_MAP_ADDR(match, msk) \
+( (EXMC_SMC_MAP_ADDR((match), (msk)) >= EXMC_SMC_ADDR_MIN) && \
+ (EXMC_SMC_MAP_ADDR((match), (msk)) <= EXMC_SMC_ADDR_MAX))
+
+#define IS_EXMC_SMC_REFRESH_PERIOD(x) ((x) <= (uint8_t)SMC_RFTR_REFPRD)
+
+#define IS_EXMC_SMC_CMD_ADDR(x) ((x) <= 0xFFFFFUL)
+
+#define IS_EXMC_SMC_TIMING_RC_CYCLE(x) ((x) <= 0x0FUL)
+
+#define IS_EXMC_SMC_TIMING_WC_CYCLE(x) ((x) <= 0x0FUL)
+
+#define IS_EXMC_SMC_TIMING_CEOE_CYCLE(x) ((x) <= 7UL)
+
+#define IS_EXMC_SMC_TIMING_WP_CYCLE(x) ((x) <= 7UL)
+
+#define IS_EXMC_SMC_TIMING_PC_CYCLE(x) ((x) <= 7UL)
+
+#define IS_EXMC_SMC_TIMING_TR_CYCLE(x) ((x) <= 7UL)
+
+/**
+ * @}
+ */
+
+/* EXMC_SMC map address */
+#define EXMC_SMC_MAP_ADDR(MATCH, MSK) ((~((MATCH) ^ (MSK))) << 24U)
+
+/**
+ * @defgroup EXMC_SMC_Register EXMC_SMC Register
+ * @{
+ */
+#define EXMC_SMC_CPSRx(__CHIPx__) ((__IO uint32_t *)(((uint32_t)(&CM_SMC->CPSR0)) + (0x20UL * (__CHIPx__))))
+#define EXMC_SMC_TMSRx(__CHIPx__) ((__IO uint32_t *)(((uint32_t)(&CM_SMC->TMSR0)) + (0x20UL * (__CHIPx__))))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EXMC_SMC_Register_Bit_Mask EXMC_SMC Register Bit Mask
+ * @{
+ */
+#define SMC_CSCR0_ADDMSKx_POS(__CHIPx__) (((__CHIPx__) & 0x03UL) << 3U)
+#define SMC_CSCR0_ADDMSKx(__CHIPx__) (SMC_CSCR0_ADDMSK0 << SMC_CSCR0_ADDMSKx_POS((__CHIPx__)))
+
+#define SMC_CSCR1_ADDMATx_POS(__CHIPx__) (((__CHIPx__) & 0x03UL) << 3U)
+#define SMC_CSCR1_ADDMATx(__CHIPx__) (SMC_CSCR1_ADDMAT0 << SMC_CSCR1_ADDMATx_POS((__CHIPx__)))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup EXMC_SMC_Register_Reset_Value EXMC_SMC Register Reset Value
+ * @{
+ */
+#define EXMC_SMC_BACR_RST_VALUE (0x00000300UL)
+/**
+ * @}
+ */
+
+#define EXMC_SMC_RMU_TIMEOUT (100U)
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup EXMC_SMC_Global_Functions EXMC_SMC Global Functions
+ * @{
+ */
+
+/**
+ * @brief Set the fields of structure @ref stc_exmc_smc_init_t to default values
+ * @param [out] pstcSmcInit Pointer to a @ref stc_exmc_smc_init_t structure.
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcSmcInit value is NULL.
+ */
+int32_t EXMC_SMC_StructInit(stc_exmc_smc_init_t *pstcSmcInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcSmcInit) {
+ pstcSmcInit->stcChipConfig.u32ReadMode = EXMC_SMC_READ_ASYNC;
+ pstcSmcInit->stcChipConfig.u32WriteMode = EXMC_SMC_WRITE_ASYNC;
+ pstcSmcInit->stcChipConfig.u32MemoryWidth = EXMC_SMC_MEMORY_WIDTH_16BIT;
+ pstcSmcInit->stcChipConfig.u32BAA = EXMC_SMC_BAA_PORT_DISABLE;
+ pstcSmcInit->stcChipConfig.u32ADV = EXMC_SMC_ADV_PORT_DISABLE;
+ pstcSmcInit->stcChipConfig.u32BLS = EXMC_SMC_BLS_SYNC_CS;
+ pstcSmcInit->stcChipConfig.u32AddrMask = 0xF8UL; /* Address space 128M: 0x60000000 ~ 0x67FFFFFF */
+ pstcSmcInit->stcChipConfig.u32AddrMatch = 0x60UL;
+
+ pstcSmcInit->stcTimingConfig.u8RC = 7U;
+ pstcSmcInit->stcTimingConfig.u8WC = 7U;
+ pstcSmcInit->stcTimingConfig.u8CEOE = 1U;
+ pstcSmcInit->stcTimingConfig.u8WP = 5U;
+ pstcSmcInit->stcTimingConfig.u8PC = 0U;
+ pstcSmcInit->stcTimingConfig.u8TR = 0U;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize EXMC_SMC function.
+ * @param [in] u32Chip The chip number.
+ * This parameter can be one of the macros group @ref EXMC_SMC_Chip
+ * @param [in] pstcSmcInit Pointer to a @ref stc_exmc_smc_init_t structure.
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcSmcInit value is NULL.
+ */
+int32_t EXMC_SMC_Init(uint32_t u32Chip, const stc_exmc_smc_init_t *pstcSmcInit)
+{
+ uint32_t u32TMCR;
+ uint32_t u32CPCR;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcSmcInit) {
+ DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip));
+ DDL_ASSERT(IS_EXMC_SMC_READ_MD(pstcSmcInit->stcChipConfig.u32ReadMode));
+ DDL_ASSERT(IS_EXMC_SMC_WRITE_MD(pstcSmcInit->stcChipConfig.u32WriteMode));
+ DDL_ASSERT(IS_EXMC_SMC_MEMORY_WIDTH(pstcSmcInit->stcChipConfig.u32MemoryWidth));
+ DDL_ASSERT(IS_EXMC_SMC_BAA_PORT(pstcSmcInit->stcChipConfig.u32BAA));
+ DDL_ASSERT(IS_EXMC_SMC_ADV_PORT(pstcSmcInit->stcChipConfig.u32ADV));
+ DDL_ASSERT(IS_EXMC_SMC_BLS_SYNC(pstcSmcInit->stcChipConfig.u32BLS));
+ DDL_ASSERT(IS_EXMC_SMC_MAP_ADDR(pstcSmcInit->stcChipConfig.u32AddrMatch, pstcSmcInit->stcChipConfig.u32AddrMask));
+ DDL_ASSERT(IS_EXMC_SMC_TIMING_RC_CYCLE(pstcSmcInit->stcTimingConfig.u8RC));
+ DDL_ASSERT(IS_EXMC_SMC_TIMING_WC_CYCLE(pstcSmcInit->stcTimingConfig.u8WC));
+ DDL_ASSERT(IS_EXMC_SMC_TIMING_CEOE_CYCLE(pstcSmcInit->stcTimingConfig.u8CEOE));
+ DDL_ASSERT(IS_EXMC_SMC_TIMING_WP_CYCLE(pstcSmcInit->stcTimingConfig.u8WP));
+ DDL_ASSERT(IS_EXMC_SMC_TIMING_PC_CYCLE(pstcSmcInit->stcTimingConfig.u8PC));
+ DDL_ASSERT(IS_EXMC_SMC_TIMING_TR_CYCLE(pstcSmcInit->stcTimingConfig.u8TR));
+
+ u32TMCR = (((uint32_t)pstcSmcInit->stcTimingConfig.u8RC << SMC_TMCR_T_RC_POS) | \
+ ((uint32_t)pstcSmcInit->stcTimingConfig.u8WC << SMC_TMCR_T_WC_POS) | \
+ ((uint32_t)pstcSmcInit->stcTimingConfig.u8CEOE << SMC_TMCR_T_CEOE_POS) | \
+ ((uint32_t)pstcSmcInit->stcTimingConfig.u8WP << SMC_TMCR_T_WP_POS) | \
+ ((uint32_t)pstcSmcInit->stcTimingConfig.u8PC << SMC_TMCR_T_PC_POS) | \
+ ((uint32_t)pstcSmcInit->stcTimingConfig.u8TR << SMC_TMCR_T_TR_POS));
+ u32CPCR = (pstcSmcInit->stcChipConfig.u32ReadMode | \
+ pstcSmcInit->stcChipConfig.u32WriteMode | \
+ pstcSmcInit->stcChipConfig.u32MemoryWidth | \
+ pstcSmcInit->stcChipConfig.u32BAA | \
+ pstcSmcInit->stcChipConfig.u32ADV | \
+ pstcSmcInit->stcChipConfig.u32BLS);
+ WRITE_REG32(CM_SMC->TMCR, u32TMCR); /* Set SMC timing.*/
+ WRITE_REG32(CM_SMC->CPCR, u32CPCR); /* Set SMC chip configuration.*/
+
+ /* Set chip selection address match/mask space for SMC.*/
+ MODIFY_REG32(CM_SMC->CSCR0, SMC_CSCR0_ADDMSKx(u32Chip), \
+ (pstcSmcInit->stcChipConfig.u32AddrMask << SMC_CSCR0_ADDMSKx_POS(u32Chip)));
+ MODIFY_REG32(CM_SMC->CSCR1, SMC_CSCR1_ADDMATx(u32Chip), \
+ (pstcSmcInit->stcChipConfig.u32AddrMatch << SMC_CSCR1_ADDMATx_POS(u32Chip)));
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief De-Initialize EXMC_SMC function.
+ * @param None
+ * @retval int32_t:
+ * - LL_OK: Reset success.
+ * - LL_ERR_TIMEOUT: Reset time out.
+ * @note Call LL_PERIPH_WE(LL_PERIPH_PWC_CLK_RMU) unlock RMU_FRSTx register first.
+ */
+int32_t EXMC_SMC_DeInit(void)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint8_t u8TimeOut = 0U;
+
+ DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1);
+
+ /* Disable SMC */
+ CLR_REG32_BIT(CM_PERIC->SMC_ENAR, PERIC_SMC_ENAR_SMCEN);
+
+ /* Reset SMC */
+ WRITE_REG32(bCM_RMU->FRST3_b.SMC, 0UL);
+
+ /* Ensure reset procedure is completed */
+ while (READ_REG32(bCM_RMU->FRST3_b.SMC) != 1UL) {
+ u8TimeOut++;
+ if (u8TimeOut > EXMC_SMC_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Enable/Disable SMC.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void EXMC_SMC_Cmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(CM_PERIC->SMC_ENAR, PERIC_SMC_ENAR_SMCEN);
+ } else {
+ CLR_REG32_BIT(CM_PERIC->SMC_ENAR, PERIC_SMC_ENAR_SMCEN);
+ }
+}
+
+/**
+ * @brief Enable or disable SMC pin mux.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void EXMC_SMC_PinMuxCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(CM_SMC->BACR, SMC_BACR_MUXMD);
+ } else {
+ CLR_REG32_BIT(CM_SMC->BACR, SMC_BACR_MUXMD);
+ }
+}
+
+/**
+ * @brief Set SMC sample clock.
+ * @param [in] u32SampleClock Sample clock
+ * This parameter can be one of the macros group @ref EXMC_SMC_Command
+ * @arg EXMC_SMC_SAMPLE_CLK_INTERNCLK: Internal EXCLK
+ * @arg EXMC_SMC_SAMPLE_CLK_INTERNCLK_INVT: Invert internal EXCLK
+ * @arg EXMC_SMC_SAMPLE_CLK_EXTCLK: External clock from EXMC_CLK port
+ * @retval None
+ */
+void EXMC_SMC_SetSampleClock(uint32_t u32SampleClock)
+{
+ DDL_ASSERT(IS_EXMC_SMC_SAMPLE_CLK(u32SampleClock));
+
+ MODIFY_REG32(CM_SMC->BACR, SMC_BACR_CKSEL, u32SampleClock);
+}
+
+/**
+ * @brief Set SMC refresh period value
+ * @param [in] u8PeriodVal The SMC refresh period value
+ * @arg This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F
+ * @retval None
+ */
+void EXMC_SMC_SetRefreshPeriod(uint8_t u8PeriodVal)
+{
+ DDL_ASSERT(IS_EXMC_SMC_REFRESH_PERIOD(u8PeriodVal));
+
+ WRITE_REG32(CM_SMC->RFTR, u8PeriodVal);
+}
+
+/**
+ * @brief Set EXMC_SMC command.
+ * @param [in] u32Chip The chip number.
+ * This parameter can be one of the macros group @ref EXMC_SMC_Chip
+ * @param [in] u32Cmd The command.
+ * This parameter can be one of the macros group @ref EXMC_SMC_Command
+ * @arg EXMC_SMC_CMD_MDREGCONFIG: Configure mode register
+ * @arg EXMC_SMC_CMD_UPDATEREGS: Update mode register
+ * @arg EXMC_SMC_CMD_MDREGCONFIG_AND_UPDATEREGS: Configure mode register and update
+ * @param [in] u32CrePolarity The command.
+ * This parameter can be one of the macros group @ref EXMC_SMC_CRE_Polarity
+ * @arg EXMC_SMC_CRE_POLARITY_LOW: CRE is LOW
+ * @arg EXMC_SMC_CRE_POLARITY_HIGH: CRE is HIGH when ModeReg write occurs
+ * @param [in] u32Addr The address parameter is valid when CMD type is MdRegConfig or MdRegConfig
+ * and UpdateRegs only.
+ * @retval None
+ */
+void EXMC_SMC_SetCommand(uint32_t u32Chip, uint32_t u32Cmd, uint32_t u32CrePolarity, uint32_t u32Addr)
+{
+ uint32_t u32SmcCmdr;
+
+ DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip));
+ DDL_ASSERT(IS_EXMC_SMC_CMD(u32Cmd));
+ DDL_ASSERT(IS_EXMC_SMC_CRE_POLARITY(u32CrePolarity));
+ DDL_ASSERT(IS_EXMC_SMC_CMD_ADDR(u32Addr));
+
+ /* Set SMC_CMDR register for SMC.*/
+ u32SmcCmdr = (u32Addr | u32CrePolarity | u32Cmd | (u32Chip << SMC_CMDR_CMDCHIP_POS));
+ WRITE_REG32(CM_SMC->CMDR, u32SmcCmdr);
+}
+
+/**
+ * @brief Get the start address of the specified SMC chip.
+ * @param [in] u32Chip The chip number.
+ * This parameter can be one of the macros group @ref EXMC_SMC_Chip
+ * @retval The start address of the specified SMC chip.
+ */
+uint32_t EXMC_SMC_GetChipStartAddr(uint32_t u32Chip)
+{
+ uint32_t u32Match;
+
+ DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip));
+
+ u32Match = READ_REG32_BIT(CM_SMC->CSCR1, SMC_CSCR1_ADDMATx(u32Chip)) >> SMC_CSCR1_ADDMATx_POS(u32Chip);
+ return (u32Match << 24U);
+}
+
+/**
+ * @brief Get the end address of the specified SMC chip.
+ * @param [in] u32Chip The chip number.
+ * This parameter can be one of the macros group @ref EXMC_SMC_Chip
+ * @retval The end address of the specified SMC chip
+ */
+uint32_t EXMC_SMC_GetChipEndAddr(uint32_t u32Chip)
+{
+ uint32_t u32Mask;
+ uint32_t u32Match;
+
+ DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip));
+
+ u32Mask = (READ_REG32_BIT(CM_SMC->CSCR0, SMC_CSCR0_ADDMSKx(u32Chip)) >> SMC_CSCR0_ADDMSKx_POS(u32Chip));
+ u32Match = (READ_REG32_BIT(CM_SMC->CSCR1, SMC_CSCR1_ADDMATx(u32Chip)) >> SMC_CSCR1_ADDMATx_POS(u32Chip));
+
+ return (~((u32Match ^ u32Mask) << 24U));
+}
+
+/**
+ * @brief Get SMC chip configure.
+ * @param [in] u32Chip The chip number.
+ * This parameter can be one of the macros group @ref EXMC_SMC_Chip
+ * @param [in] pstcChipConfig Pointer to a @ref stc_exmc_smc_chip_config_t structure.
+ * @retval int32_t:
+ * - LL_OK: Get successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcChipConfig value is NULL.
+ */
+int32_t EXMC_SMC_GetChipConfig(uint32_t u32Chip, stc_exmc_smc_chip_config_t *pstcChipConfig)
+{
+ __IO uint32_t *SMC_CPSRx;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcChipConfig) {
+ DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip));
+
+ SMC_CPSRx = EXMC_SMC_CPSRx(u32Chip);
+ pstcChipConfig->u32ReadMode = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_RSYN);
+ pstcChipConfig->u32WriteMode = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_WSYN);
+ pstcChipConfig->u32MemoryWidth = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_MW);
+ pstcChipConfig->u32BAA = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_BAAS);
+ pstcChipConfig->u32ADV = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_ADVS);
+ pstcChipConfig->u32BLS = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_BLSS);
+ pstcChipConfig->u32AddrMask = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_ADDMSK) >> SMC_CPSR_ADDMSK_POS;
+ pstcChipConfig->u32AddrMatch = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_ADDMAT) >> SMC_CPSR_ADDMAT_POS;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Get SMC timing configure.
+ * @param [in] u32Chip The chip number.
+ * This parameter can be one of the macros group @ref EXMC_SMC_Chip
+ * @param [in] pstcTimingConfig Pointer to a @ref stc_exmc_smc_timing_config_t structure.
+ * @retval int32_t:
+ * - LL_OK: Get successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcTimingConfig value is NULL.
+ */
+int32_t EXMC_SMC_GetTimingConfig(uint32_t u32Chip, stc_exmc_smc_timing_config_t *pstcTimingConfig)
+{
+ __IO uint32_t *SMC_TMSRx;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcTimingConfig) {
+ DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip));
+
+ SMC_TMSRx = EXMC_SMC_TMSRx(u32Chip);
+ pstcTimingConfig->u8RC = (uint8_t)(READ_REG32_BIT(*SMC_TMSRx, SMC_TMCR_T_RC) >> SMC_TMCR_T_RC_POS);
+ pstcTimingConfig->u8WC = (uint8_t)(READ_REG32_BIT(*SMC_TMSRx, SMC_TMCR_T_WC) >> SMC_TMCR_T_WC_POS);
+ pstcTimingConfig->u8CEOE = (uint8_t)(READ_REG32_BIT(*SMC_TMSRx, SMC_TMCR_T_CEOE) >> SMC_TMCR_T_CEOE_POS);
+ pstcTimingConfig->u8WP = (uint8_t)(READ_REG32_BIT(*SMC_TMSRx, SMC_TMCR_T_WP) >> SMC_TMCR_T_WP_POS);
+ pstcTimingConfig->u8PC = (uint8_t)(READ_REG32_BIT(*SMC_TMSRx, SMC_TMCR_T_PC) >> SMC_TMCR_T_PC_POS);
+ pstcTimingConfig->u8TR = (uint8_t)(READ_REG32_BIT(*SMC_TMSRx, SMC_TMCR_T_TR) >> SMC_TMCR_T_TR_POS);
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_SMC_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_spi.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_spi.c
new file mode 100644
index 0000000000..544faa2c81
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_spi.c
@@ -0,0 +1,1151 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_spi.c
+ * @brief This file provides firmware functions to manage the Serial Peripheral
+ * Interface(SPI).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Add SPI_SetSckPolarity,SPI_SetSckPhase functions
+ Modify return type of function SPI_DeInit
+ 2023-12-15 CDT Modify some assert
+ Rename some API SPI_xxxConfig as SPI_Setxxx
+ Add Send restriction in SPI_TxRx function
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_spi.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_SPI SPI
+ * @brief Serial Peripheral Interface Driver Library
+ * @{
+ */
+
+#if (LL_SPI_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup SPI_Local_Macros SPI Local Macros
+ * @{
+ */
+#define SPI_CFG1_DEFAULT (0x00000010UL)
+#define SPI_CFG2_DEFAULT (0x00000F1DUL)
+
+#define SPI_SS0_VALID_CFG (0UL)
+#define SPI_SS1_VALID_CFG (SPI_CFG2_SSA_0)
+#define SPI_SS2_VALID_CFG (SPI_CFG2_SSA_1)
+#define SPI_SS3_VALID_CFG (SPI_CFG2_SSA_0 | SPI_CFG2_SSA_1)
+
+#define SPI_SR_DEFAULT (0x00000020UL)
+
+#define SPI_RMU_TIMEOUT (100U)
+
+/**
+ * @defgroup SPI_Check_Parameters_Validity SPI Check Parameters Validity
+ * @{
+ */
+
+/*! Parameter valid check for SPI peripheral */
+#define IS_VALID_SPI_UNIT(x) \
+( ((x) == CM_SPI1) || \
+ ((x) == CM_SPI2) || \
+ ((x) == CM_SPI3) || \
+ ((x) == CM_SPI4))
+
+/*! Parameter valid check for SPI wire mode */
+#define IS_SPI_WIRE_MD(x) \
+( ((x) == SPI_4_WIRE) || \
+ ((x) == SPI_3_WIRE))
+
+/*! Parameter valid check for SPI transfer mode */
+#define IS_SPI_TRANS_MD(x) \
+( ((x) == SPI_FULL_DUPLEX) || \
+ ((x) == SPI_SEND_ONLY))
+
+/*! Parameter valid check for SPI master slave mode */
+#define IS_SPI_MASTER_SLAVE(x) \
+( ((x) == SPI_SLAVE) || \
+ ((x) == SPI_MASTER))
+
+/*! Parameter valid check for SPI loopback mode */
+#define IS_SPI_SPLPBK(x) \
+( ((x) == SPI_LOOPBACK_INVD) || \
+ ((x) == SPI_LOOPBACK_MOSI_INVT) || \
+ ((x) == SPI_LOOPBACK_MOSI))
+
+/*! Parameter valid check for SPI communication suspend function status */
+#define IS_SPI_SUSPD_MD_STAT(x) \
+( ((x) == SPI_COM_SUSP_FUNC_OFF) || \
+ ((x) == SPI_COM_SUSP_FUNC_ON))
+
+/*! Parameter valid check for SPI data frame level */
+#define IS_SPI_DATA_FRAME(x) \
+( ((x) == SPI_1_FRAME) || \
+ ((x) == SPI_2_FRAME) || \
+ ((x) == SPI_3_FRAME) || \
+ ((x) == SPI_4_FRAME))
+
+/*! Parameter valid check for SPI fault detect function status */
+#define IS_SPI_MD_FAULT_DETECT_CMD(x) \
+( ((x) == SPI_MD_FAULT_DETECT_DISABLE) || \
+ ((x) == SPI_MD_FAULT_DETECT_ENABLE))
+
+/*! Parameter valid check for SPI parity check mode */
+#define IS_SPI_PARITY_CHECK(x) \
+( ((x) == SPI_PARITY_INVD) || \
+ ((x) == SPI_PARITY_EVEN) || \
+ ((x) == SPI_PARITY_ODD))
+
+/*! Parameter valid check for SPI interval time delay */
+#define IS_SPI_INTERVAL_DELAY(x) \
+( ((x) == SPI_INTERVAL_TIME_1SCK) || \
+ ((x) == SPI_INTERVAL_TIME_2SCK) || \
+ ((x) == SPI_INTERVAL_TIME_3SCK) || \
+ ((x) == SPI_INTERVAL_TIME_4SCK) || \
+ ((x) == SPI_INTERVAL_TIME_5SCK) || \
+ ((x) == SPI_INTERVAL_TIME_6SCK) || \
+ ((x) == SPI_INTERVAL_TIME_7SCK) || \
+ ((x) == SPI_INTERVAL_TIME_8SCK))
+
+/*! Parameter valid check for SPI release time delay */
+#define IS_SPI_RELEASE_DELAY(x) \
+( ((x) == SPI_RELEASE_TIME_1SCK) || \
+ ((x) == SPI_RELEASE_TIME_2SCK) || \
+ ((x) == SPI_RELEASE_TIME_3SCK) || \
+ ((x) == SPI_RELEASE_TIME_4SCK) || \
+ ((x) == SPI_RELEASE_TIME_5SCK) || \
+ ((x) == SPI_RELEASE_TIME_6SCK) || \
+ ((x) == SPI_RELEASE_TIME_7SCK) || \
+ ((x) == SPI_RELEASE_TIME_8SCK))
+
+/*! Parameter valid check for SPI Setup time delay delay */
+#define IS_SPI_SETUP_DELAY(x) \
+( ((x) == SPI_SETUP_TIME_1SCK) || \
+ ((x) == SPI_SETUP_TIME_2SCK) || \
+ ((x) == SPI_SETUP_TIME_3SCK) || \
+ ((x) == SPI_SETUP_TIME_4SCK) || \
+ ((x) == SPI_SETUP_TIME_5SCK) || \
+ ((x) == SPI_SETUP_TIME_6SCK) || \
+ ((x) == SPI_SETUP_TIME_7SCK) || \
+ ((x) == SPI_SETUP_TIME_8SCK))
+
+/*! Parameter valid check for SPI read data register target buffer */
+#define IS_SPI_RD_TARGET_BUFF(x) \
+( ((x) == SPI_RD_TARGET_RD_BUF) || \
+ ((x) == SPI_RD_TARGET_WR_BUF))
+
+/*! Parameter valid check for SPI mode */
+#define IS_SPI_SPI_MD(x) \
+( ((x) == SPI_MD_0) || \
+ ((x) == SPI_MD_1) || \
+ ((x) == SPI_MD_2) || \
+ ((x) == SPI_MD_3))
+
+/*! Parameter valid check for SPI SCK Polarity */
+#define IS_SPI_SCK_POLARITY(x) \
+( ((x) == SPI_SCK_POLARITY_LOW) || \
+ ((x) == SPI_SCK_POLARITY_HIGH))
+
+/*! Parameter valid check for SPI SCK Phase */
+#define IS_SPI_SCK_PHASE(x) \
+( ((x) == SPI_SCK_PHASE_ODD_EDGE_SAMPLE) || \
+ ((x) == SPI_SCK_PHASE_EVEN_EDGE_SAMPLE))
+
+/*! Parameter valid check for SPI SS signal */
+#define IS_SPI_SS_PIN(x) \
+( ((x) == SPI_PIN_SS0) || \
+ ((x) == SPI_PIN_SS1) || \
+ ((x) == SPI_PIN_SS2) || \
+ ((x) == SPI_PIN_SS3))
+
+/*! Parameter valid check for SPI SS valid level */
+#define IS_SPI_SS_VALID_LVL(x) \
+( ((x) == SPI_SS_VALID_LVL_HIGH) || \
+ ((x) == SPI_SS_VALID_LVL_LOW))
+
+/*! Parameter valid check for SPI baudrate prescaler */
+#define IS_SPI_CLK_DIV(x) \
+( ((x) == SPI_BR_CLK_DIV2) || \
+ ((x) == SPI_BR_CLK_DIV4) || \
+ ((x) == SPI_BR_CLK_DIV6) || \
+ ((x) == SPI_BR_CLK_DIV8) || \
+ ((x) == SPI_BR_CLK_DIV10) || \
+ ((x) == SPI_BR_CLK_DIV12) || \
+ ((x) == SPI_BR_CLK_DIV14) || \
+ ((x) == SPI_BR_CLK_DIV16) || \
+ ((x) == SPI_BR_CLK_DIV18) || \
+ ((x) == SPI_BR_CLK_DIV20) || \
+ ((x) == SPI_BR_CLK_DIV22) || \
+ ((x) == SPI_BR_CLK_DIV24) || \
+ ((x) == SPI_BR_CLK_DIV26) || \
+ ((x) == SPI_BR_CLK_DIV28) || \
+ ((x) == SPI_BR_CLK_DIV30) || \
+ ((x) == SPI_BR_CLK_DIV32) || \
+ ((x) == SPI_BR_CLK_DIV36) || \
+ ((x) == SPI_BR_CLK_DIV40) || \
+ ((x) == SPI_BR_CLK_DIV44) || \
+ ((x) == SPI_BR_CLK_DIV48) || \
+ ((x) == SPI_BR_CLK_DIV52) || \
+ ((x) == SPI_BR_CLK_DIV56) || \
+ ((x) == SPI_BR_CLK_DIV60) || \
+ ((x) == SPI_BR_CLK_DIV64) || \
+ ((x) == SPI_BR_CLK_DIV72) || \
+ ((x) == SPI_BR_CLK_DIV80) || \
+ ((x) == SPI_BR_CLK_DIV88) || \
+ ((x) == SPI_BR_CLK_DIV96) || \
+ ((x) == SPI_BR_CLK_DIV104) || \
+ ((x) == SPI_BR_CLK_DIV112) || \
+ ((x) == SPI_BR_CLK_DIV120) || \
+ ((x) == SPI_BR_CLK_DIV128) || \
+ ((x) == SPI_BR_CLK_DIV144) || \
+ ((x) == SPI_BR_CLK_DIV160) || \
+ ((x) == SPI_BR_CLK_DIV176) || \
+ ((x) == SPI_BR_CLK_DIV192) || \
+ ((x) == SPI_BR_CLK_DIV208) || \
+ ((x) == SPI_BR_CLK_DIV224) || \
+ ((x) == SPI_BR_CLK_DIV240) || \
+ ((x) == SPI_BR_CLK_DIV256))
+
+/*! Parameter valid check for SPI data bits */
+#define IS_SPI_DATA_SIZE(x) \
+( ((x) == SPI_DATA_SIZE_4BIT) || \
+ ((x) == SPI_DATA_SIZE_5BIT) || \
+ ((x) == SPI_DATA_SIZE_6BIT) || \
+ ((x) == SPI_DATA_SIZE_7BIT) || \
+ ((x) == SPI_DATA_SIZE_8BIT) || \
+ ((x) == SPI_DATA_SIZE_9BIT) || \
+ ((x) == SPI_DATA_SIZE_10BIT) || \
+ ((x) == SPI_DATA_SIZE_11BIT) || \
+ ((x) == SPI_DATA_SIZE_12BIT) || \
+ ((x) == SPI_DATA_SIZE_13BIT) || \
+ ((x) == SPI_DATA_SIZE_14BIT) || \
+ ((x) == SPI_DATA_SIZE_15BIT) || \
+ ((x) == SPI_DATA_SIZE_16BIT) || \
+ ((x) == SPI_DATA_SIZE_20BIT) || \
+ ((x) == SPI_DATA_SIZE_24BIT) || \
+ ((x) == SPI_DATA_SIZE_32BIT))
+
+/*! Parameter valid check for SPI LSB MSB mode */
+#define IS_SPI_FIRST_BIT(x) \
+( ((x) == SPI_FIRST_MSB) || \
+ ((x) == SPI_FIRST_LSB))
+
+/*! Parameter valid check for SPI Communication mode */
+#define IS_SPI_COMM_MD(x) \
+( ((x) == SPI_COMM_MD_NORMAL) || \
+ ((x) == SPI_COMM_MD_CONT))
+
+/*! Parameter valid check for interrupt flag */
+#define IS_SPI_INT(x) \
+( ((x) != 0UL) && \
+ (((x) | SPI_INT_ALL) == SPI_INT_ALL))
+
+/*! Parameter valid check for SPI status flag */
+#define IS_SPI_FLAG(x) \
+( ((x) != 0UL) && \
+ (((x) | SPI_FLAG_ALL) == SPI_FLAG_ALL))
+
+/*! Parameter valid check for SPI status flag for clear */
+#define IS_SPI_CLR_FLAG(x) \
+( ((x) != 0UL) && \
+ (((x) | SPI_FLAG_CLR_ALL) == SPI_FLAG_CLR_ALL))
+
+/*! Parameter valid check for SPI command*/
+#define IS_SPI_CMD_ALLOWED(x) \
+( (READ_REG32_BIT(SPIx->SR, SPI_FLAG_MD_FAULT) == 0UL) || \
+ ((x) == DISABLE))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup SPI_Local_Func SPI Local Functions
+ * @{
+ */
+
+/**
+ * @brief SPI check status.
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @param [in] u32FlagMask Bit mask of status flag.
+ * @param [in] u32Value Valid value of the status.
+ * @param [in] u32Timeout Timeout value.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_TIMEOUT: SPI transmit timeout.
+ */
+static int32_t SPI_WaitStatus(const CM_SPI_TypeDef *SPIx, uint32_t u32FlagMask, uint32_t u32Value, uint32_t u32Timeout)
+{
+ int32_t i32Ret = LL_OK;
+
+ while (READ_REG32_BIT(SPIx->SR, u32FlagMask) != u32Value) {
+ if (u32Timeout == 0UL) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ u32Timeout--;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief SPI master release delay.
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @param [in] u32TransMode SPI transfer mode @ref SPI_Trans_Mode_Define
+ * @retval None
+ * @note The delay while CPHA = 0 and full duplex mode in continue communication mode(1 SCK).
+ * @note The delay while send only mode in continue communication mode(x SCK).
+ */
+static void SPI_MasterReleaseDelay(CM_SPI_TypeDef *SPIx, uint32_t u32TransMode)
+{
+ uint32_t u32BusFreq, u32SpiDiv, u32DataBits;
+ uint32_t u32Speed, u32Temp;
+ uint32_t u32DelayTime = 1U;
+
+ u32BusFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS);
+ u32SpiDiv = (((READ_REG32_BIT(SPIx->CFG1, SPI_CFG1_CLKDIV) >> SPI_CFG1_CLKDIV_POS) + 1U) << 1U);
+ u32SpiDiv *= (1UL << (READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_MBR) >> SPI_CFG2_MBR_POS));
+ u32Speed = u32BusFreq / u32SpiDiv;
+ if (SPI_FULL_DUPLEX == u32TransMode) {
+ /* Communication speed below 1Mhz */
+ if ((u32Speed < 1000000UL) && (u32Speed > 0U)) {
+ u32DelayTime = 1000000UL / u32Speed;
+ if (0U != (1000000UL % u32Speed)) {
+ u32DelayTime += 1U;
+ }
+ }
+ } else {
+ if (SPI_CFG2_MSSIE == READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSIE)) {
+ u32Temp = (READ_REG32_BIT(SPIx->CFG1, SPI_CFG1_MSSI) >> SPI_CFG1_MSSI_POS);
+ } else {
+ u32Temp = 0U;
+ }
+ if (0U == READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_CPHA)) {
+ u32Temp += 1U;
+ }
+ u32DataBits = READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_DSIZE);
+ if (u32DataBits <= SPI_DATA_SIZE_16BIT) {
+ u32Temp += (u32DataBits >> SPI_CFG2_DSIZE_POS) + 4U;
+ } else if (u32DataBits == SPI_DATA_SIZE_20BIT) {
+ u32Temp += 20U;
+ } else if (u32DataBits == SPI_DATA_SIZE_24BIT) {
+ u32Temp += 24U;
+ } else {
+ u32Temp += 32U;
+ }
+ /* Total wait time below 1us */
+ u32Speed = u32Speed / u32Temp;
+ if ((u32Speed < 1000000UL) && (u32Speed > 0U)) {
+ u32DelayTime = 1000000UL / u32Speed;
+ if (0U != (1000000UL % u32Speed)) {
+ u32DelayTime += 1U;
+ }
+ }
+ }
+ DDL_DelayUS(u32DelayTime);
+}
+
+/**
+ * @brief SPI transmit and receive data in full duplex mode.
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent.
+ * @param [out] pvRxBuf The pointer to the buffer which the received data will be stored.
+ * @param [in] u32Len The length of the data in byte or half word.
+ * @param [in] u32Timeout Timeout value.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred
+ * - LL_ERR_TIMEOUT: SPI transmit and receive timeout.
+ */
+static int32_t SPI_TxRx(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout)
+{
+ uint32_t u32BitSize;
+ __IO uint32_t u32TxCnt = 0U, u32RxCnt = 0U;
+ __IO uint32_t u32Count = 0U;
+ int32_t i32Ret = LL_OK;
+ uint32_t u32Tmp;
+ __UNUSED __IO uint32_t u32Read;
+ __IO uint32_t u32TxAllow = 1U;
+ uint32_t u32MSMode;
+ __IO uint32_t u32FrameCnt;
+ uint32_t u32FrameNum = READ_REG32_BIT(SPIx->CFG1, SPI_CFG1_FTHLV) + 1UL;
+ DDL_ASSERT(0UL == (u32Len % u32FrameNum));
+
+ u32MSMode = READ_REG32_BIT(SPIx->CR, SPI_CR_MSTR);
+ /* Get data bit size, SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_32BIT */
+ u32BitSize = READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_DSIZE);
+ while (u32RxCnt < u32Len) {
+ /* Tx data */
+ if (u32TxCnt < u32Len) {
+ /* Wait TX buffer empty. */
+ i32Ret = SPI_WaitStatus(SPIx, SPI_FLAG_TX_BUF_EMPTY, SPI_FLAG_TX_BUF_EMPTY, 0U);
+ if ((i32Ret == LL_OK) && (((u32MSMode == SPI_MASTER) && (u32TxAllow == 1U)) || (u32MSMode == SPI_SLAVE))) {
+ if (pvTxBuf != NULL) {
+ u32FrameCnt = 0UL;
+ while (u32FrameCnt < u32FrameNum) {
+ if (u32BitSize <= SPI_DATA_SIZE_8BIT) {
+ /* SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_8BIT */
+ WRITE_REG32(SPIx->DR, ((const uint8_t *)pvTxBuf)[u32TxCnt]);
+ } else if (u32BitSize <= SPI_DATA_SIZE_16BIT) {
+ /* SPI_DATA_SIZE_9BIT ~ SPI_DATA_SIZE_16BIT */
+ WRITE_REG32(SPIx->DR, ((const uint16_t *)pvTxBuf)[u32TxCnt]);
+ } else {
+ /* SPI_DATA_SIZE_20BIT ~ SPI_DATA_SIZE_32BIT */
+ WRITE_REG32(SPIx->DR, ((const uint32_t *)pvTxBuf)[u32TxCnt]);
+ }
+ u32FrameCnt++;
+ u32TxCnt++;
+ }
+ } else {
+ u32FrameCnt = 0UL;
+ while (u32FrameCnt < u32FrameNum) {
+ WRITE_REG32(SPIx->DR, 0xFFFFFFFFUL);
+ u32FrameCnt++;
+ u32TxCnt++;
+ }
+ }
+ u32TxAllow = 0U;
+ }
+ }
+
+ /* RX data */
+ i32Ret = SPI_WaitStatus(SPIx, SPI_FLAG_RX_BUF_FULL, SPI_FLAG_RX_BUF_FULL, 0U);
+ if (i32Ret == LL_OK) {
+ if (pvRxBuf != NULL) {
+ u32FrameCnt = 0UL;
+ while (u32FrameCnt < u32FrameNum) {
+ u32Tmp = READ_REG32(SPIx->DR);
+ if (u32BitSize <= SPI_DATA_SIZE_8BIT) {
+ /* SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_8BIT */
+ ((uint8_t *)pvRxBuf)[u32RxCnt] = (uint8_t)u32Tmp;
+ } else if (u32BitSize <= SPI_DATA_SIZE_16BIT) {
+ /* SPI_DATA_SIZE_9BIT ~ SPI_DATA_SIZE_16BIT */
+ ((uint16_t *)pvRxBuf)[u32RxCnt] = (uint16_t)u32Tmp;
+ } else {
+ /* SPI_DATA_SIZE_20BIT ~ SPI_DATA_SIZE_32BIT */
+ ((uint32_t *)pvRxBuf)[u32RxCnt] = (uint32_t)u32Tmp;
+ }
+ u32FrameCnt++;
+ u32RxCnt++;
+ }
+ } else {
+ /* Dummy read */
+ u32FrameCnt = 0UL;
+ while (u32FrameCnt < u32FrameNum) {
+ u32Read = READ_REG32(SPIx->DR);
+ u32FrameCnt++;
+ u32RxCnt++;
+ }
+ }
+ u32TxAllow = 1U;
+ u32Count = 0U;
+ }
+
+ /* check timeout */
+ if (u32Count > u32Timeout) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ u32Count++;
+ }
+
+ if ((SPI_MASTER == READ_REG32_BIT(SPIx->CR, SPI_CR_MSTR)) && (i32Ret == LL_OK)) {
+ if (SPI_COMM_MD_NORMAL == READ_REG32_BIT(SPIx->CFG1, SPI_CFG1_CTMDS)) {
+ i32Ret = SPI_WaitStatus(SPIx, SPI_FLAG_IDLE, 0UL, u32Timeout);
+ } else {
+ if (0U == READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_CPHA)) {
+ SPI_MasterReleaseDelay(SPIx, SPI_FULL_DUPLEX);
+ }
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief SPI send data only.
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent.
+ * @param [in] u32Len The length of the data in byte or half word or word.
+ * @param [in] u32Timeout Timeout value.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_TIMEOUT: SPI transmit timeout.
+ */
+static int32_t SPI_Tx(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32Len, uint32_t u32Timeout)
+{
+ __IO uint32_t u32TxCnt = 0U;
+ uint32_t u32BitSize;
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t u32FrameCnt;
+ uint32_t u32FrameNum = READ_REG32_BIT(SPIx->CFG1, SPI_CFG1_FTHLV) + 1UL;
+ DDL_ASSERT(0UL == (u32Len % u32FrameNum));
+
+ /* Get data bit size, SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_32BIT */
+ u32BitSize = READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_DSIZE);
+ while (u32TxCnt < u32Len) {
+ u32FrameCnt = 0UL;
+ while (u32FrameCnt < u32FrameNum) {
+ if (u32BitSize <= SPI_DATA_SIZE_8BIT) {
+ /* SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_8BIT */
+ WRITE_REG32(SPIx->DR, ((const uint8_t *)pvTxBuf)[u32TxCnt]);
+ } else if (u32BitSize <= SPI_DATA_SIZE_16BIT) {
+ /* SPI_DATA_SIZE_9BIT ~ SPI_DATA_SIZE_16BIT */
+ WRITE_REG32(SPIx->DR, ((const uint16_t *)pvTxBuf)[u32TxCnt]);
+ } else {
+ /* SPI_DATA_SIZE_20BIT ~ SPI_DATA_SIZE_32BIT */
+ WRITE_REG32(SPIx->DR, ((const uint32_t *)pvTxBuf)[u32TxCnt]);
+ }
+ u32FrameCnt++;
+ u32TxCnt++;
+ }
+ /* Wait TX buffer empty. */
+ i32Ret = SPI_WaitStatus(SPIx, SPI_FLAG_TX_BUF_EMPTY, SPI_FLAG_TX_BUF_EMPTY, u32Timeout);
+ if (i32Ret != LL_OK) {
+ break;
+ }
+ }
+
+ if ((SPI_MASTER == READ_REG32_BIT(SPIx->CR, SPI_CR_MSTR)) && (i32Ret == LL_OK)) {
+ if (SPI_COMM_MD_NORMAL == READ_REG32_BIT(SPIx->CFG1, SPI_CFG1_CTMDS)) {
+ i32Ret = SPI_WaitStatus(SPIx, SPI_FLAG_IDLE, 0UL, u32Timeout);
+ } else {
+ SPI_MasterReleaseDelay(SPIx, SPI_SEND_ONLY);
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_Global_Functions SPI Global Functions
+ * @{
+ */
+
+/**
+ * @brief Initializes the SPI peripheral according to the specified parameters
+ * in the structure stc_spi_init.
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @param [in] pstcSpiInit Pointer to a stc_spi_init_t structure that contains
+ * the configuration information for the SPI.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred
+ * - LL_ERR_INVD_PARAM: pstcSpiInit == NULL or configuration parameter error.
+ * @note -In the 3-Wire slave mode and CHPA = 0, the function needs to cooperate with other processes to communicate properly.
+ * @note -The parameter u32BaudRatePrescaler is invalid while slave mode
+ */
+int32_t SPI_Init(CM_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcSpiInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx));
+
+ if (NULL != pstcSpiInit) {
+ DDL_ASSERT(IS_SPI_WIRE_MD(pstcSpiInit->u32WireMode));
+ DDL_ASSERT(IS_SPI_TRANS_MD(pstcSpiInit->u32TransMode));
+ DDL_ASSERT(IS_SPI_MASTER_SLAVE(pstcSpiInit->u32MasterSlave));
+ DDL_ASSERT(IS_SPI_MD_FAULT_DETECT_CMD(pstcSpiInit->u32ModeFaultDetect));
+ DDL_ASSERT(IS_SPI_PARITY_CHECK(pstcSpiInit->u32Parity));
+ DDL_ASSERT(IS_SPI_SPI_MD(pstcSpiInit->u32SpiMode));
+ DDL_ASSERT(IS_SPI_CLK_DIV(pstcSpiInit->u32BaudRatePrescaler));
+ DDL_ASSERT(IS_SPI_DATA_SIZE(pstcSpiInit->u32DataBits));
+ DDL_ASSERT(IS_SPI_FIRST_BIT(pstcSpiInit->u32FirstBit));
+ DDL_ASSERT(IS_SPI_SUSPD_MD_STAT(pstcSpiInit->u32SuspendMode));
+ DDL_ASSERT(IS_SPI_DATA_FRAME(pstcSpiInit->u32FrameLevel));
+
+ /* Configuration parameter check */
+ if ((SPI_MASTER == pstcSpiInit->u32MasterSlave) && (SPI_MD_FAULT_DETECT_ENABLE == pstcSpiInit->u32ModeFaultDetect)) {
+ /* pstcSpiInit->u32ModeFaultDetect can not be SPI_MD_FAULT_DETECT_ENABLE in master mode */
+ } else {
+ WRITE_REG32(SPIx->CR, pstcSpiInit->u32WireMode | pstcSpiInit->u32TransMode | pstcSpiInit->u32MasterSlave | \
+ pstcSpiInit->u32SuspendMode | pstcSpiInit->u32ModeFaultDetect | pstcSpiInit->u32Parity);
+ if (SPI_MASTER == pstcSpiInit->u32MasterSlave) {
+ MODIFY_REG32(SPIx->CFG1, (SPI_CFG1_FTHLV | SPI_CFG1_CLKDIV),
+ (pstcSpiInit->u32FrameLevel | (pstcSpiInit->u32BaudRatePrescaler & SPI_CFG1_CLKDIV)));
+ WRITE_REG32(SPIx->CFG2, pstcSpiInit->u32SpiMode | pstcSpiInit->u32FirstBit | pstcSpiInit->u32DataBits | \
+ (pstcSpiInit->u32BaudRatePrescaler & SPI_CFG2_MBR));
+ } else {
+ MODIFY_REG32(SPIx->CFG1, SPI_CFG1_FTHLV, pstcSpiInit->u32FrameLevel);
+ WRITE_REG32(SPIx->CFG2, pstcSpiInit->u32SpiMode | pstcSpiInit->u32FirstBit | pstcSpiInit->u32DataBits);
+ }
+
+ i32Ret = LL_OK;
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief De-initializes the SPI peripheral.
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_TIMEOUT: Works timeout.
+ */
+int32_t SPI_DeInit(CM_SPI_TypeDef *SPIx)
+{
+ uint32_t i;
+ int32_t i32Ret = LL_OK;
+ __IO uint8_t u8TimeOut = 0U;
+ __IO uint32_t *bCM_RMU_FRST1_SPIx = NULL;
+ const uint32_t au32SPIx[] = {CM_SPI1_BASE, CM_SPI2_BASE, CM_SPI3_BASE, CM_SPI4_BASE};
+
+ /* Check RMU_FRST register protect */
+ DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1);
+ DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx));
+
+ for (i = 0UL; i < ARRAY_SZ(au32SPIx); i++) {
+ if ((uint32_t)SPIx == au32SPIx[i]) {
+ bCM_RMU_FRST1_SPIx = (__IO uint32_t *)((uint32_t)&bCM_RMU->FRST1_b.SPI1 + (i << 2));
+ break;
+ }
+ }
+
+ /* Reset SPI */
+ WRITE_REG32(*bCM_RMU_FRST1_SPIx, 0UL);
+
+ /* Ensure reset procedure is completed */
+ while (READ_REG32(*bCM_RMU_FRST1_SPIx) != 1UL) {
+ u8TimeOut++;
+ if (u8TimeOut > SPI_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Set a default value for the SPI initialization structure.
+ * @param [in] pstcSpiInit Pointer to a stc_spi_init_t structure that
+ * contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_INVD_PARAM: pstcSpiInit == NULL.
+ */
+int32_t SPI_StructInit(stc_spi_init_t *pstcSpiInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcSpiInit) {
+ pstcSpiInit->u32WireMode = SPI_4_WIRE;
+ pstcSpiInit->u32TransMode = SPI_FULL_DUPLEX;
+ pstcSpiInit->u32MasterSlave = SPI_MASTER;
+ pstcSpiInit->u32ModeFaultDetect = SPI_MD_FAULT_DETECT_DISABLE;
+ pstcSpiInit->u32Parity = SPI_PARITY_INVD;
+ pstcSpiInit->u32SpiMode = SPI_MD_0;
+ pstcSpiInit->u32BaudRatePrescaler = SPI_BR_CLK_DIV8;
+ pstcSpiInit->u32DataBits = SPI_DATA_SIZE_8BIT;
+ pstcSpiInit->u32FirstBit = SPI_FIRST_MSB;
+ pstcSpiInit->u32SuspendMode = SPI_COM_SUSP_FUNC_OFF;
+ pstcSpiInit->u32FrameLevel = SPI_1_FRAME;
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Enable or disable SPI interrupt.
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @param [in] u32IntType SPI interrupt type. Can be one or any
+ * combination of the parameter @ref SPI_Int_Type_Define
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void SPI_IntCmd(CM_SPI_TypeDef *SPIx, uint32_t u32IntType, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_SPI_INT(u32IntType));
+
+ if (enNewState == ENABLE) {
+ SET_REG32_BIT(SPIx->CR, u32IntType);
+ } else {
+ CLR_REG32_BIT(SPIx->CR, u32IntType);
+ }
+}
+
+/**
+ * @brief SPI function enable or disable.
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void SPI_Cmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_SPI_CMD_ALLOWED(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(SPIx->CR, SPI_CR_SPE);
+ } else {
+ CLR_REG32_BIT(SPIx->CR, SPI_CR_SPE);
+ }
+}
+
+/**
+ * @brief Write SPI data register.
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @param [in] u32Data The data will be written to the data register.
+ * @retval None.
+ */
+void SPI_WriteData(CM_SPI_TypeDef *SPIx, uint32_t u32Data)
+{
+ DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx));
+ WRITE_REG32(SPIx->DR, u32Data);
+}
+
+/**
+ * @brief Read SPI data register.
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @retval uint32_t A 32-bit data of SPI data register.
+ */
+uint32_t SPI_ReadData(const CM_SPI_TypeDef *SPIx)
+{
+ DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx));
+
+ return READ_REG32(SPIx->DR);
+}
+
+/**
+ * @brief SPI get status flag.
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @param [in] u32Flag SPI state flag. Can be one or any
+ * combination of the parameter of @ref SPI_State_Flag_Define
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t SPI_GetStatus(const CM_SPI_TypeDef *SPIx, uint32_t u32Flag)
+{
+ en_flag_status_t enFlag = RESET;
+ uint32_t u32Status;
+
+ DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx));
+ DDL_ASSERT(IS_SPI_FLAG(u32Flag));
+
+ u32Status = READ_REG32(SPIx->SR);
+ if (SPI_FLAG_IDLE == (SPI_FLAG_IDLE & u32Flag)) {
+ CLR_REG32_BIT(u32Flag, SPI_FLAG_IDLE);
+ if (0U == (u32Status & SPI_FLAG_IDLE)) {
+ enFlag = SET;
+ }
+ }
+ if (0U != READ_REG32_BIT(u32Status, u32Flag)) {
+ enFlag = SET;
+ }
+
+ return enFlag;
+}
+
+/**
+ * @brief SPI clear state flag.
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @param [in] u32Flag SPI state flag. Can be one or any combination of the parameter below
+ * @arg SPI_FLAG_OVERRUN
+ * @arg SPI_FLAG_MD_FAULT
+ * @arg SPI_FLAG_PARITY_ERR
+ * @arg SPI_FLAG_UNDERRUN
+ * @retval None
+ */
+void SPI_ClearStatus(CM_SPI_TypeDef *SPIx, uint32_t u32Flag)
+{
+ DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx));
+ DDL_ASSERT(IS_SPI_CLR_FLAG(u32Flag));
+
+ CLR_REG32_BIT(SPIx->SR, u32Flag);
+}
+
+/**
+ * @brief SPI loopback function configuration.
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @param [in] u32Mode Loopback mode. Can be one parameter @ref SPI_Loopback_Selection_Define
+ * @retval None
+ */
+void SPI_SetLoopbackMode(CM_SPI_TypeDef *SPIx, uint32_t u32Mode)
+{
+ DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx));
+ DDL_ASSERT(IS_SPI_SPLPBK(u32Mode));
+
+ MODIFY_REG32(SPIx->CR, SPI_CR_SPLPBK | SPI_CR_SPLPBK2, u32Mode);
+}
+
+/**
+ * @brief SPI parity check error self diagnosis function enable or disable.
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+
+void SPI_ParityCheckCmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(SPIx->CR, SPI_CR_PATE);
+ } else {
+ CLR_REG32_BIT(SPIx->CR, SPI_CR_PATE);
+ }
+}
+
+/**
+ * @brief SPI signals delay time configuration
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @param [in] pstcDelayConfig Pointer to a stc_spi_delay_t structure that contains
+ * the configuration information for the SPI delay time.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred
+ * - LL_ERR_INVD_PARAM: pstcDelayConfig == NULL
+ */
+int32_t SPI_DelayTimeConfig(CM_SPI_TypeDef *SPIx, const stc_spi_delay_t *pstcDelayConfig)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx));
+
+ if (NULL != pstcDelayConfig) {
+ DDL_ASSERT(IS_SPI_INTERVAL_DELAY(pstcDelayConfig->u32IntervalDelay));
+ DDL_ASSERT(IS_SPI_RELEASE_DELAY(pstcDelayConfig->u32ReleaseDelay));
+ DDL_ASSERT(IS_SPI_SETUP_DELAY(pstcDelayConfig->u32SetupDelay));
+
+ /* Interval delay */
+ if (SPI_INTERVAL_TIME_1SCK == pstcDelayConfig->u32IntervalDelay) {
+ CLR_REG32_BIT(SPIx->CFG2, SPI_CFG2_MIDIE);
+ CLR_REG32_BIT(SPIx->CFG1, SPI_CFG1_MIDI);
+ } else {
+ MODIFY_REG32(SPIx->CFG1, SPI_CFG1_MIDI, pstcDelayConfig->u32IntervalDelay);
+ SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_MIDIE);
+ }
+
+ /* SCK release delay */
+ if (SPI_RELEASE_TIME_1SCK == pstcDelayConfig->u32ReleaseDelay) {
+ CLR_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSDLE);
+ CLR_REG32_BIT(SPIx->CFG1, SPI_CFG1_MSSDL);
+ } else {
+ SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSDLE);
+ MODIFY_REG32(SPIx->CFG1, SPI_CFG1_MSSDL, pstcDelayConfig->u32ReleaseDelay);
+ }
+
+ /* Setup delay */
+ if (SPI_SETUP_TIME_1SCK == pstcDelayConfig->u32SetupDelay) {
+ CLR_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSIE);
+ CLR_REG32_BIT(SPIx->CFG1, SPI_CFG1_MSSI);
+ } else {
+ SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSIE);
+ MODIFY_REG32(SPIx->CFG1, SPI_CFG1_MSSI, pstcDelayConfig->u32SetupDelay);
+ }
+
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Set a default value for the SPI delay time configuration structure.
+ * @param [in] pstcDelayConfig Pointer to a stc_spi_delay_t structure that
+ * contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_INVD_PARAM: pstcDelayConfig == NULL.
+ */
+int32_t SPI_DelayStructInit(stc_spi_delay_t *pstcDelayConfig)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcDelayConfig) {
+ pstcDelayConfig->u32IntervalDelay = SPI_INTERVAL_TIME_1SCK;
+ pstcDelayConfig->u32ReleaseDelay = SPI_RELEASE_TIME_1SCK;
+ pstcDelayConfig->u32SetupDelay = SPI_SETUP_TIME_1SCK;
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Set the communication mode.
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @param [in] u32Mode Specify the communication mode @ref SPI_Comm_Mode_Define
+ * @retval None
+ */
+void SPI_SetCommMode(CM_SPI_TypeDef *SPIx, uint32_t u32Mode)
+{
+ DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx));
+ DDL_ASSERT(IS_SPI_COMM_MD(u32Mode));
+
+ MODIFY_REG32(SPIx->CFG1, SPI_CFG1_CTMDS, u32Mode);
+}
+
+/**
+ * @brief SPI SS signal valid level configuration
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @param [in] u32SSPin Specify the SS pin @ref SPI_SS_Pin_Define
+ * @param [in] u32SSLevel Specify the SS valid level @ref SPI_SS_Level
+ * @arg SPI_SS_VALID_LVL_HIGH: SS high level valid
+ * @arg SPI_SS_VALID_LVL_LOW: SS low level valid
+ * @retval None
+ */
+void SPI_SetSSValidLevel(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin, uint32_t u32SSLevel)
+{
+ DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx));
+ DDL_ASSERT(IS_SPI_SS_PIN(u32SSPin));
+ DDL_ASSERT(IS_SPI_SS_VALID_LVL(u32SSLevel));
+
+ if (SPI_SS_VALID_LVL_HIGH == u32SSLevel) {
+ SET_REG32_BIT(SPIx->CFG1, u32SSPin);
+ } else {
+ CLR_REG32_BIT(SPIx->CFG1, u32SSPin);
+ }
+}
+
+/**
+ * @brief Set the SPI SCK polarity.
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @param [in] u32Polarity Specify the SPI SCK polarity @ref SPI_SCK_Polarity_Define
+ * @retval None
+ */
+void SPI_SetSckPolarity(CM_SPI_TypeDef *SPIx, uint32_t u32Polarity)
+{
+ DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx));
+ DDL_ASSERT(IS_SPI_SCK_POLARITY(u32Polarity));
+
+ if (SPI_SCK_POLARITY_LOW == u32Polarity) {
+ CLR_REG32_BIT(SPIx->CFG2, SPI_CFG2_CPOL);
+ } else {
+ SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_CPOL);
+ }
+}
+
+/**
+ * @brief Set the SPI SCK phase.
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @param [in] u32Phase Specify the SPI SCK phase @ref SPI_SCK_Phase_Define
+ * @retval None
+ */
+void SPI_SetSckPhase(CM_SPI_TypeDef *SPIx, uint32_t u32Phase)
+{
+ DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx));
+ DDL_ASSERT(IS_SPI_SCK_PHASE(u32Phase));
+
+ if (SPI_SCK_PHASE_ODD_EDGE_SAMPLE == u32Phase) {
+ CLR_REG32_BIT(SPIx->CFG2, SPI_CFG2_CPHA);
+ } else {
+ SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_CPHA);
+ }
+}
+
+/**
+ * @brief SPI valid SS signal configuration
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @param [in] u32SSPin Specify the SS pin @ref SPI_SS_Pin_Define
+ * @retval None
+ */
+void SPI_SSPinSelect(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin)
+{
+ uint32_t u32RegConfig;
+ DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx));
+ DDL_ASSERT(IS_SPI_SS_PIN(u32SSPin));
+
+ switch (u32SSPin) {
+ case SPI_PIN_SS0:
+ u32RegConfig = SPI_SS0_VALID_CFG;
+ break;
+ case SPI_PIN_SS1:
+ u32RegConfig = SPI_SS1_VALID_CFG;
+ break;
+ case SPI_PIN_SS2:
+ u32RegConfig = SPI_SS2_VALID_CFG;
+ break;
+ case SPI_PIN_SS3:
+ u32RegConfig = SPI_SS3_VALID_CFG;
+ break;
+ default:
+ u32RegConfig = SPI_SS0_VALID_CFG;
+ break;
+ }
+ MODIFY_REG32(SPIx->CFG2, SPI_CFG2_SSA, u32RegConfig);
+}
+
+/**
+ * @brief SPI read buffer configuration
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @param [in] u32ReadBuf Target buffer for read operation @ref SPI_Read_Target_Buf_Define
+ * @retval None
+ */
+void SPI_SetReadBuf(CM_SPI_TypeDef *SPIx, uint32_t u32ReadBuf)
+{
+ DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx));
+ DDL_ASSERT(IS_SPI_RD_TARGET_BUFF(u32ReadBuf));
+
+ MODIFY_REG32(SPIx->CFG1, SPI_CFG1_SPRDTD, u32ReadBuf);
+}
+
+/**
+ * @brief SPI transmit data.
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent.
+ * @param [in] u32TxLen The length of the data to be sent.
+ * @param [in] u32Timeout Timeout value.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred
+ * - LL_ERR_TIMEOUT: SPI transmit timeout.
+ * - LL_ERR_INVD_PARAM: pvTxBuf == NULL or u32TxLen == 0U
+ * @note -No SS pin active and inactive operation in 3-wire mode. Add operations of SS pin depending on your application.
+ * -In the send only slave mode, the function needs to increase an appropriate delay after calling to ensure the
+ * integrity of data transmission.
+ */
+int32_t SPI_Trans(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32TxLen, uint32_t u32Timeout)
+{
+ uint32_t u32Flags;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if ((pvTxBuf != NULL) && (u32TxLen != 0U)) {
+ u32Flags = READ_REG32_BIT(SPIx->CR, SPI_CR_TXMDS);
+ if (u32Flags == SPI_SEND_ONLY) {
+ /* Transmit data in send only mode. */
+ i32Ret = SPI_Tx(SPIx, pvTxBuf, u32TxLen, u32Timeout);
+ } else {
+ /* Transmit data in full duplex mode. */
+ i32Ret = SPI_TxRx(SPIx, pvTxBuf, NULL, u32TxLen, u32Timeout);
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief SPI receive data.
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @param [in] pvRxBuf The pointer to the buffer which the received data to be stored.
+ * @param [in] u32RxLen The length of the data to be received.
+ * @param [in] u32Timeout Timeout value.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred
+ * - LL_ERR_TIMEOUT: SPI receive timeout.
+ * - LL_ERR_INVD_PARAM: pvRxBuf == NULL or u32RxLen == 0U
+ * @note -No SS pin active and inactive operation in 3-wire mode. Add operations of SS pin depending on your application.
+ */
+int32_t SPI_Receive(CM_SPI_TypeDef *SPIx, void *pvRxBuf, uint32_t u32RxLen, uint32_t u32Timeout)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if ((pvRxBuf != NULL) && (u32RxLen != 0U)) {
+ /* Receives data in full duplex master mode. */
+ i32Ret = SPI_TxRx(SPIx, NULL, pvRxBuf, u32RxLen, u32Timeout);
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief SPI transmit and receive data.
+ * @param [in] SPIx SPI unit
+ * @arg CM_SPIx or CM_SPI
+ * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent.
+ * If this pointer is NULL and the pvRxBuf is NOT NULL, the MOSI output high
+ * and the the received data will be stored in the buffer pointed by pvRxBuf.
+ * @param [out] pvRxBuf The pointer to the buffer which the received data will be stored.
+ * This for full duplex transfer.
+ * @param [in] u32Len The length of the data(in byte or half word) to be sent and received.
+ * @param [in] u32Timeout Timeout value.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred
+ * - LL_ERR_TIMEOUT: SPI transmit and receive timeout.
+ * - LL_ERR_INVD_PARAM: pvRxBuf == NULL or pvRxBuf == NULL or u32Len == 0U
+ * @note SPI receives data while sending data.
+ */
+int32_t SPI_TransReceive(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if ((pvTxBuf != NULL) && (pvRxBuf != NULL) && (u32Len != 0U)) {
+ /* Transmit and receive data in full duplex master mode. */
+ i32Ret = SPI_TxRx(SPIx, pvTxBuf, pvRxBuf, u32Len, u32Timeout);
+ }
+ return i32Ret;
+}
+/**
+ * @}
+ */
+
+#endif /* LL_SPI_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_sram.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_sram.c
new file mode 100644
index 0000000000..f003242951
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_sram.c
@@ -0,0 +1,358 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_sram.c
+ * @brief This file provides firmware functions to manage the SRAM.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT API fixed: SRAM_ClearStatus()
+ 2023-12-15 CDT Refine SRAM_ErrorInjectBitCmd()
+ Refine SRAM_SetEccMode, and refine SRAM_SetErrorMode() as SRAM_SetExceptionType
+ Remove wait cycle relevant code
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_sram.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_SRAM SRAM
+ * @brief SRAM Driver Library
+ * @{
+ */
+
+#if (LL_SRAM_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup SRAM_Local_Macros SRAM Local Macros
+ * @{
+ */
+
+/**
+ * @defgroup SRAM_Configuration_Bits_Mask SRAM Configuration Bits Mask
+ * @{
+ */
+#define SRAM_CYCLE_MASK (0x00000007UL)
+/**
+ * @}
+ */
+
+#define SRAM_EI_BIT_MASK (0x7FFFFFFFFFUL)
+
+/**
+ * @defgroup SRAM_Ecc_Mode_Mask SRAM ecc mode mask
+ * @{
+ */
+#define SRAM_ECC_MD_MASK (SRAMC_CKCR_ECCMOD | SRAMC_CKCR_BECCMOD)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SRAM_Exception_Type_Mask SRAM exception type mask
+ * @{
+ */
+#define SRAM_EXP_TYPE_MASK (SRAMC_CKCR_ECCOAD | SRAMC_CKCR_BECCOAD | SRAMC_CKCR_PYOAD)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SRAM_Check_Parameters_Validity SRAM check parameters validity
+ * @{
+ */
+#define IS_SRAM_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask)))
+
+/* Parameter valid check for SRAM wait cycle */
+#define IS_SRAM_WAIT_CYCLE(x) ((x) <= SRAM_WAIT_CYCLE7)
+
+/* Parameter valid check for SRAM selection */
+#define IS_SRAM_SEL(x) IS_SRAM_BIT_MASK(x, SRAM_SRAM_ALL)
+
+/* Parameter valid check for SRAM ECC SRAM */
+#define IS_SRAM_ECC_SRAM(x) IS_SRAM_BIT_MASK(x, SRAM_ECC_SRAM_ALL)
+
+/* Parameter valid check for SRAM ECC SRAM */
+#define IS_SRAM_CHECK_SRAM(x) IS_SRAM_BIT_MASK(x, SRAM_CHECK_SRAM_ALL)
+
+/* Parameter valid check for SRAM flag */
+#define IS_SRAM_FLAG(x) IS_SRAM_BIT_MASK(x, SRAM_FLAG_ALL)
+
+/* Check SRAM CKPR register lock status. */
+#define IS_SRAM_CKPR_UNLOCK() (CM_SRAMC->CKPR == SRAM_REG_UNLOCK_KEY)
+
+/* Parameter valid check for SRAM exception type mode */
+#define IS_SRAM_EXP_TYPE(x) \
+( ((x) == SRAM_EXP_TYPE_NMI) || \
+ ((x) == SRAM_EXP_TYPE_RST))
+
+/* Parameter valid check for SRAM ECC mode */
+#define IS_SRAM_ECC_MD(x) \
+( (((x) | SRAM_ECC_MD_MASK) == 0xFFFFFFFFUL) || \
+ (((x) | SRAM_ECC_MD_MASK) == SRAM_ECC_MD_MASK))
+
+/* Parameter valid check for SRAM error inject bit */
+#define IS_SRAM_EI_BIT(x) \
+( ((x) != 0x00UL) && \
+ (((x) | SRAM_EI_BIT_MASK) == SRAM_EI_BIT_MASK))
+
+/* Parameter valid check for SRAM ECC SRAM */
+#define IS_SRAM_ECC_SRAM_ONLY(x) \
+( ((x) == SRAM_ECC_SRAM0) || \
+ ((x) == SRAM_ECC_SRAMB))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup SRAM_Global_Functions SRAM Global Functions
+ * @{
+ */
+
+/**
+ * @brief Initializes SRAM.
+ * @param None
+ * @retval None
+ */
+void SRAM_Init(void)
+{
+ SET_REG32_BIT(CM_SRAMC->CKSR, SRAM_FLAG_ALL);
+}
+
+/**
+ * @brief De-initializes SRAM. RESET the registers of SRAM.
+ * @param None
+ * @retval None
+ * @note Call SRAM_REG_Unlock to unlock registers WTCR and CKCR first.
+ */
+void SRAM_DeInit(void)
+{
+ /* Call SRAM_REG_Unlock to unlock register WTCR and CKCR. */
+ DDL_ASSERT(IS_SRAM_CKPR_UNLOCK());
+ WRITE_REG32(CM_SRAMC->CKCR, 0UL);
+ SET_REG32_BIT(CM_SRAMC->CKSR, SRAM_FLAG_ALL);
+}
+
+/**
+ * @brief Specifies ECC mode.
+ * @param [in] u32EccSram The ECC SRAM.
+ * This parameter can be any combination of @ref SRAM_ECC_SRAM
+ * @param [in] u32EccMode The ECC mode.
+ * @retval None
+ * @note Call SRAM_REG_Unlock to unlock register CKCR first.
+ * The sram of u32EccMode should be the same with the sram of u32EccSram.
+ */
+void SRAM_SetEccMode(uint32_t u32EccSram, uint32_t u32EccMode)
+{
+ uint32_t u32Mask = 0UL;
+ uint32_t u32Pos = 0UL;
+
+ DDL_ASSERT(IS_SRAM_ECC_SRAM(u32EccSram));
+ DDL_ASSERT(IS_SRAM_ECC_MD(u32EccMode));
+ DDL_ASSERT(IS_SRAM_CKPR_UNLOCK());
+
+ while (0UL != u32EccSram) {
+ if (1UL == (u32EccSram & 0x01UL)) {
+ u32Mask |= (SRAMC_CKCR_ECCMOD << u32Pos);
+ }
+ u32EccSram >>= 1UL;
+ u32Pos += 2UL;
+ }
+
+ MODIFY_REG32(CM_SRAMC->CKCR, u32Mask, u32EccMode);
+}
+
+/**
+ * @brief Specifies the exception type while the choosen sram check error occurred.
+ * @param [in] u32CheckSram The check SRAM.
+ * This parameter can be any combination of @ref SRAM_Check_SRAM
+ * @param [in] u32ExceptionType The operation after check error occurred.
+ * This parameter can be a value of @ref SRAM_Exception_Type
+ * @retval None
+ * @note Call SRAM_REG_Unlock to unlock register CKCR first.
+ */
+void SRAM_SetExceptionType(uint32_t u32CheckSram, uint32_t u32ExceptionType)
+{
+ DDL_ASSERT(IS_SRAM_CHECK_SRAM(u32CheckSram));
+ DDL_ASSERT(IS_SRAM_EXP_TYPE(u32ExceptionType));
+ DDL_ASSERT(IS_SRAM_CKPR_UNLOCK());
+
+ if (SRAM_EXP_TYPE_RST == u32ExceptionType) {
+ SET_REG32_BIT(CM_SRAMC->CKCR, u32CheckSram);
+ } else {
+ CLR_REG32_BIT(CM_SRAMC->CKCR, u32CheckSram);
+ }
+}
+
+/**
+ * @brief Get the status of the specified flag of SRAM.
+ * @param [in] u32Flag The flag of SRAM.
+ * This parameter can be a value of @ref SRAM_Err_Status_Flag
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t SRAM_GetStatus(uint32_t u32Flag)
+{
+ en_flag_status_t enStatus = RESET;
+
+ DDL_ASSERT(IS_SRAM_FLAG(u32Flag));
+ if (READ_REG32_BIT(CM_SRAMC->CKSR, u32Flag) != 0U) {
+ enStatus = SET;
+ }
+
+ return enStatus;
+}
+
+/**
+ * @brief Clear the status of the specified flag of SRAM.
+ * @param [in] u32Flag The flag of SRAM.
+ * This parameter can be values of @ref SRAM_Err_Status_Flag
+ * @retval None
+ */
+void SRAM_ClearStatus(uint32_t u32Flag)
+{
+ DDL_ASSERT(IS_SRAM_FLAG(u32Flag));
+ WRITE_REG32(CM_SRAMC->CKSR, u32Flag);
+}
+
+/**
+ * @brief Enable or disable error injection.
+ * @param [in] u32EccSram The SRAM selection.
+ * This parameter can be any combination of @ref SRAM_ECC_SRAM
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void SRAM_ErrorInjectCmd(uint32_t u32EccSram, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_SRAM_ECC_SRAM(u32EccSram));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if ((u32EccSram & SRAM_ECC_SRAM0) != 0U) {
+ WRITE_REG32(CM_SRAMC->SRAM0_EIEN, enNewState);
+ }
+ if ((u32EccSram & SRAM_ECC_SRAMB) != 0U) {
+ WRITE_REG32(CM_SRAMC->SRAMB_EIEN, enNewState);
+ }
+}
+
+/**
+ * @brief Enable or disable error injection bit of SRAM_ECC_SRAM.
+ * @param [in] u32EccSram The SRAM selection.
+ * This parameter can be any combination of @ref SRAM_ECC_SRAM
+ * @param [in] u64BitSel Bit selection. Only bit0~bit38 valid.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void SRAM_ErrorInjectBitCmd(uint32_t u32EccSram, uint64_t u64BitSel, en_functional_state_t enNewState)
+{
+ uint32_t u32Eibit0 = (uint32_t)(u64BitSel & SRAMC_SRAM0_EIBIT0);
+ uint32_t u32Eibit1 = (uint32_t)((u64BitSel >> 32U) & SRAMC_SRAM0_EIBIT1_EIBIT);
+
+ DDL_ASSERT(IS_SRAM_ECC_SRAM(u32EccSram));
+ DDL_ASSERT(IS_SRAM_EI_BIT(u64BitSel));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ if ((u32EccSram & SRAM_ECC_SRAM0) != 0U) {
+ SET_REG32_BIT(CM_SRAMC->SRAM0_EIBIT0, u32Eibit0);
+ SET_REG32_BIT(CM_SRAMC->SRAM0_EIBIT1, u32Eibit1);
+ }
+ if ((u32EccSram & SRAM_ECC_SRAMB) != 0U) {
+ SET_REG32_BIT(CM_SRAMC->SRAMB_EIBIT0, u32Eibit0);
+ SET_REG32_BIT(CM_SRAMC->SRAMB_EIBIT1, u32Eibit1);
+ }
+ } else {
+ if ((u32EccSram & SRAM_ECC_SRAM0) != 0U) {
+ CLR_REG32_BIT(CM_SRAMC->SRAM0_EIBIT0, u32Eibit0);
+ CLR_REG32_BIT(CM_SRAMC->SRAM0_EIBIT1, u32Eibit1);
+ }
+ if ((u32EccSram & SRAM_ECC_SRAMB) != 0U) {
+ CLR_REG32_BIT(CM_SRAMC->SRAMB_EIBIT0, u32Eibit0);
+ CLR_REG32_BIT(CM_SRAMC->SRAMB_EIBIT1, u32Eibit1);
+ }
+ }
+
+}
+
+/**
+ * @brief Get access address when 1bit or 2bit ECC error occurs in SRAM0/SRAMB.
+ * @param [in] u32EccSram The SRAM selection.
+ * This parameter can be any combination of @ref SRAM_ECC_SRAM
+ * @retval An uint32_t type value of access address. If 'u32EccSram' is not equal to the value upon,
+ * it will return 0xFFFFFFFFUL.
+ */
+uint32_t SRAM_GetEccErrorAddr(uint32_t u32EccSram)
+{
+ uint32_t u32RetAddr;
+
+ DDL_ASSERT(IS_SRAM_ECC_SRAM_ONLY(u32EccSram));
+
+ if (u32EccSram == SRAM_ECC_SRAM0) {
+ u32RetAddr = READ_REG32(CM_SRAMC->SRAM0_ECCERRADDR);
+ } else {
+ u32RetAddr = READ_REG32(CM_SRAMC->SRAMB_ECCERRADDR);
+ }
+
+ return u32RetAddr;
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_SRAM_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_swdt.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_swdt.c
new file mode 100644
index 0000000000..94e8e45928
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_swdt.c
@@ -0,0 +1,257 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_swdt.c
+ * @brief This file provides firmware functions to manage the Specialized Watch
+ * Dog Timer(SWDT).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-09-30 CDT Optimize SWDT_ClearStatus function timeout
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_swdt.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_SWDT SWDT
+ * @brief Specialized Watch Dog Timer
+ * @{
+ */
+
+#if (LL_SWDT_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup SWDT_Local_Macros SWDT Local Macros
+ * @{
+ */
+
+/* SWDT Refresh Key */
+#define SWDT_REFRESH_KEY_START (0x0123UL)
+#define SWDT_REFRESH_KEY_END (0x3210UL)
+
+/* SWDT clear flag timeout(ms) */
+#define SWDT_CLR_FLAG_TIMEOUT (400UL)
+
+/* SWDT Registers Clear Mask */
+#define SWDT_CR_CLR_MASK (SWDT_CR_PERI | SWDT_CR_CKS | SWDT_CR_WDPT | \
+ SWDT_CR_SLPOFF | SWDT_CR_ITS)
+
+/**
+ * @defgroup SWDT_Check_Parameters_Validity SWDT Check Parameters Validity
+ * @{
+ */
+
+#define IS_SWDT_CNT_PERIOD(x) \
+( ((x) == SWDT_CNT_PERIOD256) || \
+ ((x) == SWDT_CNT_PERIOD4096) || \
+ ((x) == SWDT_CNT_PERIOD16384) || \
+ ((x) == SWDT_CNT_PERIOD65536))
+
+#define IS_SWDT_CLK_DIV(x) \
+( ((x) == SWDT_CLK_DIV1) || \
+ ((x) == SWDT_CLK_DIV16) || \
+ ((x) == SWDT_CLK_DIV32) || \
+ ((x) == SWDT_CLK_DIV64) || \
+ ((x) == SWDT_CLK_DIV128) || \
+ ((x) == SWDT_CLK_DIV256) || \
+ ((x) == SWDT_CLK_DIV2048))
+
+#define IS_SWDT_REFRESH_RANGE(x) \
+( ((x) == SWDT_RANGE_0TO100PCT) || \
+ ((x) == SWDT_RANGE_0TO25PCT) || \
+ ((x) == SWDT_RANGE_25TO50PCT) || \
+ ((x) == SWDT_RANGE_0TO50PCT) || \
+ ((x) == SWDT_RANGE_50TO75PCT) || \
+ ((x) == SWDT_RANGE_0TO25PCT_50TO75PCT) || \
+ ((x) == SWDT_RANGE_25TO75PCT) || \
+ ((x) == SWDT_RANGE_0TO75PCT) || \
+ ((x) == SWDT_RANGE_75TO100PCT) || \
+ ((x) == SWDT_RANGE_0TO25PCT_75TO100PCT) || \
+ ((x) == SWDT_RANGE_25TO50PCT_75TO100PCT) || \
+ ((x) == SWDT_RANGE_0TO50PCT_75TO100PCT) || \
+ ((x) == SWDT_RANGE_50TO100PCT) || \
+ ((x) == SWDT_RANGE_0TO25PCT_50TO100PCT) || \
+ ((x) == SWDT_RANGE_25TO100PCT))
+
+#define IS_SWDT_LPM_CNT(x) \
+( ((x) == SWDT_LPM_CNT_CONT) || \
+ ((x) == SWDT_LPM_CNT_STOP))
+
+#define IS_SWDT_EXP_TYPE(x) \
+( ((x) == SWDT_EXP_TYPE_INT) || \
+ ((x) == SWDT_EXP_TYPE_RST))
+
+#define IS_SWDT_FLAG(x) \
+( ((x) != 0UL) && \
+ (((x) | SWDT_FLAG_ALL) == SWDT_FLAG_ALL))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @addtogroup SWDT_Global_Functions
+ * @{
+ */
+
+/**
+ * @brief Initializes SWDT.
+ * @param [in] pstcSwdtInit Pointer to a @ref stc_swdt_init_t structure
+ * @retval int32_t:
+ * - LL_OK: Initializes success
+ * - LL_ERR_INVD_PARAM: pstcSwdtInit == NULL
+ */
+int32_t SWDT_Init(const stc_swdt_init_t *pstcSwdtInit)
+{
+ int32_t i32Ret = LL_OK;
+ uint32_t u32Temp;
+
+ if (NULL == pstcSwdtInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Check parameters */
+ DDL_ASSERT(IS_SWDT_CNT_PERIOD(pstcSwdtInit->u32CountPeriod));
+ DDL_ASSERT(IS_SWDT_CLK_DIV(pstcSwdtInit->u32ClockDiv));
+ DDL_ASSERT(IS_SWDT_REFRESH_RANGE(pstcSwdtInit->u32RefreshRange));
+ DDL_ASSERT(IS_SWDT_LPM_CNT(pstcSwdtInit->u32LPMCount));
+ DDL_ASSERT(IS_SWDT_EXP_TYPE(pstcSwdtInit->u32ExceptionType));
+
+ u32Temp = pstcSwdtInit->u32CountPeriod | pstcSwdtInit->u32ClockDiv |
+ pstcSwdtInit->u32RefreshRange | pstcSwdtInit->u32LPMCount | pstcSwdtInit->u32ExceptionType;
+ /* SWDT CR Configuration(Software Start Mode) */
+ MODIFY_REG32(CM_SWDT->CR, SWDT_CR_CLR_MASK, u32Temp);
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief SWDT feed dog.
+ * @note In software startup mode, Start counter when refreshing for the first time.
+ * @param None
+ * @retval None
+ */
+void SWDT_FeedDog(void)
+{
+ WRITE_REG32(CM_SWDT->RR, SWDT_REFRESH_KEY_START);
+ WRITE_REG32(CM_SWDT->RR, SWDT_REFRESH_KEY_END);
+}
+
+/**
+ * @brief Get SWDT flag status.
+ * @param [in] u32Flag SWDT flag type
+ * This parameter can be one or any combination of the following values:
+ * @arg SWDT_FLAG_UDF: Count underflow flag
+ * @arg SWDT_FLAG_REFRESH: Refresh error flag
+ * @arg SWDT_FLAG_ALL: All of the above
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t SWDT_GetStatus(uint32_t u32Flag)
+{
+ en_flag_status_t enFlagSta = RESET;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_SWDT_FLAG(u32Flag));
+
+ if (0UL != (READ_REG32_BIT(CM_SWDT->SR, u32Flag))) {
+ enFlagSta = SET;
+ }
+
+ return enFlagSta;
+}
+
+/**
+ * @brief Clear SWDT flag.
+ * @param [in] u32Flag SWDT flag type
+ * This parameter can be one or any combination of the following values:
+ * @arg SWDT_FLAG_UDF: Count underflow flag
+ * @arg SWDT_FLAG_REFRESH: Refresh error flag
+ * @arg SWDT_FLAG_ALL: All of the above
+ * @retval int32_t:
+ * - LL_OK: Clear flag success
+ * - LL_ERR_TIMEOUT: Clear flag timeout
+ */
+int32_t SWDT_ClearStatus(uint32_t u32Flag)
+{
+ __IO uint32_t u32Count;
+ int32_t i32Ret = LL_OK;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_SWDT_FLAG(u32Flag));
+
+ /* Waiting for FLAG bit clear */
+ u32Count = SWDT_CLR_FLAG_TIMEOUT * (HCLK_VALUE / 25000UL);
+ while (0UL != READ_REG32_BIT(CM_SWDT->SR, u32Flag)) {
+ CLR_REG32_BIT(CM_SWDT->SR, u32Flag);
+ if (0UL == u32Count) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ u32Count--;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_SWDT_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_tmr0.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_tmr0.c
new file mode 100644
index 0000000000..9a06c2f53c
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_tmr0.c
@@ -0,0 +1,624 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_tmr0.c
+ * @brief This file provides firmware functions to manage the TMR0
+ * (TMR0).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_tmr0.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_TMR0 TMR0
+ * @brief TMR0 Driver Library
+ * @{
+ */
+
+#if (LL_TMR0_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup TMR0_Local_Macros TMR0 Local Macros
+ * @{
+ */
+/* Max channel number */
+#define TMR0_CH_MAX (2UL)
+
+#define TMR0_CLK_SRC_MASK (TMR0_BCONR_SYNSA | TMR0_BCONR_SYNCLKA | TMR0_BCONR_ASYNCLKA)
+#define TMR0_BCONR_CLR_MASK (TMR0_BCONR_CAPMDA | TMR0_BCONR_CKDIVA | TMR0_BCONR_HICPA | TMR0_CLK_SRC_MASK)
+
+/**
+ * @defgroup TMR0_Register_Address TMR0 Register Address
+ * @{
+ */
+#define TMR0_CNTR_ADDR(__UNIT__, __CH__) (__IO uint32_t*)((uint32_t)(&((__UNIT__)->CNTAR)) + ((__CH__) << 2UL))
+#define TMR0_CMPR_ADDR(__UNIT__, __CH__) (__IO uint32_t*)((uint32_t)(&((__UNIT__)->CMPAR)) + ((__CH__) << 2UL))
+/**
+ * @}
+ */
+#define TMR0_CH_OFFSET(__CH__) ((__CH__) << 4U)
+
+/**
+ * @defgroup TMR0_Check_Parameters_Validity TMR0 Check Parameters Validity
+ * @{
+ */
+#define IS_TMR0_UNIT(x) \
+( ((x) == CM_TMR0_1) || \
+ ((x) == CM_TMR0_2))
+
+#define IS_TMR0_CH(x) \
+( ((x) == TMR0_CH_A) || \
+ ((x) == TMR0_CH_B))
+
+#define IS_TMR0_CLK_SRC(x) \
+( ((x) == TMR0_CLK_SRC_INTERN_CLK) || \
+ ((x) == TMR0_CLK_SRC_SPEC_EVT) || \
+ ((x) == TMR0_CLK_SRC_LRC) || \
+ ((x) == TMR0_CLK_SRC_XTAL32))
+
+#define IS_TMR0_CLK_DIV(x) \
+( ((x) == TMR0_CLK_DIV1) || \
+ ((x) == TMR0_CLK_DIV2) || \
+ ((x) == TMR0_CLK_DIV4) || \
+ ((x) == TMR0_CLK_DIV8) || \
+ ((x) == TMR0_CLK_DIV16) || \
+ ((x) == TMR0_CLK_DIV32) || \
+ ((x) == TMR0_CLK_DIV64) || \
+ ((x) == TMR0_CLK_DIV128) || \
+ ((x) == TMR0_CLK_DIV256) || \
+ ((x) == TMR0_CLK_DIV512) || \
+ ((x) == TMR0_CLK_DIV1024))
+
+#define IS_TMR0_FUNC(x) \
+( ((x) == TMR0_FUNC_CMP) || \
+ ((x) == TMR0_FUNC_CAPT))
+
+#define IS_TMR0_INT(x) \
+( ((x) != 0U) && \
+ (((x) | TMR0_INT_ALL) == TMR0_INT_ALL))
+
+#define IS_TMR0_FLAG(x) \
+( ((x) != 0U) && \
+ (((x) | TMR0_FLAG_ALL) == TMR0_FLAG_ALL))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup TMR0_Global_Functions TMR0 Global Functions
+ * @{
+ */
+
+/**
+ * @brief De-Initialize TMR0 function
+ * @param [in] TMR0x Pointer to TMR0 unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance
+ * @retval None
+ */
+void TMR0_DeInit(CM_TMR0_TypeDef *TMR0x)
+{
+ uint32_t u32Ch;
+ __IO uint32_t *CNTR;
+ __IO uint32_t *CMPR;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_TMR0_UNIT(TMR0x));
+
+ WRITE_REG32(TMR0x->BCONR, 0UL);
+ WRITE_REG32(TMR0x->STFLR, 0UL);
+ for (u32Ch = 0UL; u32Ch < TMR0_CH_MAX; u32Ch++) {
+ CNTR = TMR0_CNTR_ADDR(TMR0x, u32Ch);
+ WRITE_REG32(*CNTR, 0UL);
+ CMPR = TMR0_CMPR_ADDR(TMR0x, u32Ch);
+ WRITE_REG32(*CMPR, 0x0000FFFFUL);
+ }
+}
+
+/**
+ * @brief Initialize TMR0 function.
+ * @param [in] TMR0x Pointer to TMR0 unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance
+ * @param [in] u32Ch TMR0 channel
+ * This parameter can be one of the following values:
+ * @arg @ref TMR0_Channel
+ * @param [in] pstcTmr0Init Pointer to a @ref stc_tmr0_init_t.
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: pstcTmr0Init is NULL
+ */
+int32_t TMR0_Init(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, const stc_tmr0_init_t *pstcTmr0Init)
+{
+ __IO uint32_t *CNTR;
+ __IO uint32_t *CMPR;
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcTmr0Init) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Check parameters */
+ DDL_ASSERT(IS_TMR0_UNIT(TMR0x));
+ DDL_ASSERT(IS_TMR0_CH(u32Ch));
+ DDL_ASSERT(IS_TMR0_CLK_SRC(pstcTmr0Init->u32ClockSrc));
+ DDL_ASSERT(IS_TMR0_CLK_DIV(pstcTmr0Init->u32ClockDiv));
+ DDL_ASSERT(IS_TMR0_FUNC(pstcTmr0Init->u32Func));
+
+ CNTR = TMR0_CNTR_ADDR(TMR0x, u32Ch);
+ WRITE_REG32(*CNTR, 0UL);
+ CMPR = TMR0_CMPR_ADDR(TMR0x, u32Ch);
+ WRITE_REG32(*CMPR, pstcTmr0Init->u16CompareValue);
+ MODIFY_REG32(TMR0x->BCONR, (TMR0_BCONR_CLR_MASK << TMR0_CH_OFFSET(u32Ch)),
+ ((pstcTmr0Init->u32ClockSrc | pstcTmr0Init->u32ClockDiv |
+ pstcTmr0Init->u32Func) << TMR0_CH_OFFSET(u32Ch)));
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set the fields of structure stc_tmr0_init_t to default values.
+ * @param [out] pstcTmr0Init Pointer to a @ref stc_tmr0_init_t structure.
+ * @retval int32_t:
+ * - LL_OK: Initialize success
+ * - LL_ERR_INVD_PARAM: pstcTmr0Init is NULL
+ */
+int32_t TMR0_StructInit(stc_tmr0_init_t *pstcTmr0Init)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcTmr0Init) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ pstcTmr0Init->u32ClockSrc = TMR0_CLK_SRC_INTERN_CLK;
+ pstcTmr0Init->u32ClockDiv = TMR0_CLK_DIV1;
+ pstcTmr0Init->u32Func = TMR0_FUNC_CMP;
+ pstcTmr0Init->u16CompareValue = 0xFFFFU;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Start TMR0.
+ * @param [in] TMR0x Pointer to TMR0 unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance
+ * @param [in] u32Ch TMR0 channel
+ * This parameter can be one of the following values:
+ * @arg @ref TMR0_Channel
+ * @retval None
+ */
+void TMR0_Start(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_TMR0_UNIT(TMR0x));
+ DDL_ASSERT(IS_TMR0_CH(u32Ch));
+
+ SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_CSTA << TMR0_CH_OFFSET(u32Ch)));
+}
+
+/**
+ * @brief Stop TMR0.
+ * @param [in] TMR0x Pointer to TMR0 unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance
+ * @param [in] u32Ch TMR0 channel
+ * This parameter can be one of the following values:
+ * @arg @ref TMR0_Channel
+ * @retval None
+ */
+void TMR0_Stop(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_TMR0_UNIT(TMR0x));
+ DDL_ASSERT(IS_TMR0_CH(u32Ch));
+
+ CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_CSTA << TMR0_CH_OFFSET(u32Ch)));
+}
+
+/**
+ * @brief Set Tmr0 counter value.
+ * @note Setting the count requires stop tmr0.
+ * @param [in] TMR0x Pointer to TMR0 unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance
+ * @param [in] u32Ch TMR0 channel
+ * This parameter can be one of the following values:
+ * @arg @ref TMR0_Channel
+ * @param [in] u16Value The data to write to the counter register
+ * @retval None
+ */
+void TMR0_SetCountValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value)
+{
+ __IO uint32_t *CNTR;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_TMR0_UNIT(TMR0x));
+ DDL_ASSERT(IS_TMR0_CH(u32Ch));
+
+ CNTR = TMR0_CNTR_ADDR(TMR0x, u32Ch);
+ WRITE_REG32(*CNTR, u16Value);
+}
+
+/**
+ * @brief Get Tmr0 counter value.
+ * @param [in] TMR0x Pointer to TMR0 unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance
+ * @param [in] u32Ch TMR0 channel
+ * This parameter can be one of the following values:
+ * @arg @ref TMR0_Channel
+ * @retval uint16_t The counter register data
+ */
+uint16_t TMR0_GetCountValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch)
+{
+ __IO uint32_t *CNTR;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_TMR0_UNIT(TMR0x));
+ DDL_ASSERT(IS_TMR0_CH(u32Ch));
+
+ CNTR = TMR0_CNTR_ADDR(TMR0x, u32Ch);
+ return (uint16_t)READ_REG32(*CNTR);
+}
+
+/**
+ * @brief Set Tmr0 compare value.
+ * @param [in] TMR0x Pointer to TMR0 unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance
+ * @param [in] u32Ch TMR0 channel
+ * This parameter can be one of the following values:
+ * @arg @ref TMR0_Channel
+ * @param [in] u16Value The data to write to the compare register
+ * @retval None
+ */
+void TMR0_SetCompareValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value)
+{
+ __IO uint32_t *CMPR;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_TMR0_UNIT(TMR0x));
+ DDL_ASSERT(IS_TMR0_CH(u32Ch));
+
+ CMPR = TMR0_CMPR_ADDR(TMR0x, u32Ch);
+ WRITE_REG32(*CMPR, u16Value);
+}
+
+/**
+ * @brief Get Tmr0 compare value.
+ * @param [in] TMR0x Pointer to TMR0 unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance
+ * @param [in] u32Ch TMR0 channel
+ * This parameter can be one of the following values:
+ * @arg @ref TMR0_Channel
+ * @retval The compare register data
+ */
+uint16_t TMR0_GetCompareValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch)
+{
+ __IO uint32_t *CMPR;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_TMR0_UNIT(TMR0x));
+ DDL_ASSERT(IS_TMR0_CH(u32Ch));
+
+ CMPR = TMR0_CMPR_ADDR(TMR0x, u32Ch);
+ return (uint16_t)READ_REG32(*CMPR);
+}
+
+/**
+ * @brief Set clock source.
+ * @param [in] TMR0x Pointer to TMR0 unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance
+ * @param [in] u32Ch TMR0 channel
+ * This parameter can be one of the following values:
+ * @arg @ref TMR0_Channel
+ * @param [in] u32Src Specifies the clock source
+ * This parameter can be a value of the following:
+ * @arg @ref TMR0_Clock_Source
+ * @retval None
+ */
+void TMR0_SetClockSrc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Src)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_TMR0_UNIT(TMR0x));
+ DDL_ASSERT(IS_TMR0_CH(u32Ch));
+ DDL_ASSERT(IS_TMR0_CLK_SRC(u32Src));
+
+ MODIFY_REG32(TMR0x->BCONR, (TMR0_CLK_SRC_MASK << TMR0_CH_OFFSET(u32Ch)), (u32Src << TMR0_CH_OFFSET(u32Ch)));
+}
+
+/**
+ * @brief Set the division of clock.
+ * @param [in] TMR0x Pointer to TMR0 unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance
+ * @param [in] u32Ch TMR0 channel
+ * This parameter can be one of the following values:
+ * @arg @ref TMR0_Channel
+ * @param [in] u32Div Specifies the clock source division
+ * This parameter can be a value of the following:
+ * @arg TMR0_CLK_DIV1: Clock source / 1
+ * @arg TMR0_CLK_DIV2: Clock source / 2
+ * @arg TMR0_CLK_DIV4: Clock source / 4
+ * @arg TMR0_CLK_DIV8: Clock source / 8
+ * @arg TMR0_CLK_DIV16: Clock source / 16
+ * @arg TMR0_CLK_DIV32: Clock source / 32
+ * @arg TMR0_CLK_DIV64: Clock source / 64
+ * @arg TMR0_CLK_DIV128: Clock source / 128
+ * @arg TMR0_CLK_DIV256: Clock source / 256
+ * @arg TMR0_CLK_DIV512: Clock source / 512
+ * @arg TMR0_CLK_DIV1024: Clock source / 1024
+ * @retval None.
+ */
+void TMR0_SetClockDiv(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Div)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_TMR0_UNIT(TMR0x));
+ DDL_ASSERT(IS_TMR0_CH(u32Ch));
+ DDL_ASSERT(IS_TMR0_CLK_DIV(u32Div));
+
+ MODIFY_REG32(TMR0x->BCONR, (TMR0_BCONR_CKDIVA << TMR0_CH_OFFSET(u32Ch)), (u32Div << TMR0_CH_OFFSET(u32Ch)));
+}
+
+/**
+ * @brief Set Tmr0 Function.
+ * @param [in] TMR0x Pointer to TMR0 unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance
+ * @param [in] u32Ch TMR0 channel
+ * This parameter can be one of the following values:
+ * @arg @ref TMR0_Channel
+ * @param [in] u32Func Select TMR0 function
+ * This parameter can be a value of the following:
+ * @arg TMR0_FUNC_CMP: Select the Compare function
+ * @arg TMR0_FUNC_CAPT: Select the Capture function
+ * @retval None
+ */
+void TMR0_SetFunc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Func)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_TMR0_UNIT(TMR0x));
+ DDL_ASSERT(IS_TMR0_CH(u32Ch));
+ DDL_ASSERT(IS_TMR0_FUNC(u32Func));
+
+ MODIFY_REG32(TMR0x->BCONR, ((TMR0_BCONR_CAPMDA | TMR0_BCONR_HICPA) << TMR0_CH_OFFSET(u32Ch)),
+ (u32Func << TMR0_CH_OFFSET(u32Ch)));
+}
+
+/**
+ * @brief Enable or disable HardWare trigger capture function.
+ * @param [in] TMR0x Pointer to TMR0 unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance
+ * @param [in] u32Ch TMR0 channel
+ * This parameter can be one of the following values:
+ * @arg @ref TMR0_Channel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR0_HWCaptureCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_TMR0_UNIT(TMR0x));
+ DDL_ASSERT(IS_TMR0_CH(u32Ch));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HICPA << TMR0_CH_OFFSET(u32Ch)));
+ } else {
+ CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HICPA << TMR0_CH_OFFSET(u32Ch)));
+ }
+}
+
+/**
+ * @brief Enable or disable HardWare trigger start function.
+ * @param [in] TMR0x Pointer to TMR0 unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance
+ * @param [in] u32Ch TMR0 channel
+ * This parameter can be one of the following values:
+ * @arg @ref TMR0_Channel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR0_HWStartCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_TMR0_UNIT(TMR0x));
+ DDL_ASSERT(IS_TMR0_CH(u32Ch));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HSTAA << TMR0_CH_OFFSET(u32Ch)));
+ } else {
+ CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HSTAA << TMR0_CH_OFFSET(u32Ch)));
+ }
+}
+
+/**
+ * @brief Enable or disable HardWare trigger stop function.
+ * @param [in] TMR0x Pointer to TMR0 unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance
+ * @param [in] u32Ch TMR0 channel
+ * This parameter can be one of the following values:
+ * @arg @ref TMR0_Channel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR0_HWStopCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_TMR0_UNIT(TMR0x));
+ DDL_ASSERT(IS_TMR0_CH(u32Ch));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HSTPA << TMR0_CH_OFFSET(u32Ch)));
+ } else {
+ CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HSTPA << TMR0_CH_OFFSET(u32Ch)));
+ }
+}
+
+/**
+ * @brief Enable or disable HardWare trigger clear function.
+ * @param [in] TMR0x Pointer to TMR0 unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance
+ * @param [in] u32Ch TMR0 channel
+ * This parameter can be one of the following values:
+ * @arg @ref TMR0_Channel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR0_HWClearCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_TMR0_UNIT(TMR0x));
+ DDL_ASSERT(IS_TMR0_CH(u32Ch));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HCLEA << TMR0_CH_OFFSET(u32Ch)));
+ } else {
+ CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HCLEA << TMR0_CH_OFFSET(u32Ch)));
+ }
+}
+
+/**
+ * @brief Enable or disable specified Tmr0 interrupt.
+ * @param [in] TMR0x Pointer to TMR0 unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance
+ * @param [in] u32IntType TMR0 interrupt type
+ * This parameter can be any combination value of the following values:
+ * @arg @ref TMR0_Interrupt.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR0_IntCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32IntType, en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_TMR0_UNIT(TMR0x));
+ DDL_ASSERT(IS_TMR0_INT(u32IntType));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (DISABLE != enNewState) {
+ SET_REG32_BIT(TMR0x->BCONR, u32IntType);
+ } else {
+ CLR_REG32_BIT(TMR0x->BCONR, u32IntType);
+ }
+}
+
+/**
+ * @brief Get Tmr0 status.
+ * @param [in] TMR0x Pointer to TMR0 unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance
+ * @param [in] u32Flag TMR0 flag type
+ * This parameter can be any combination value of the following values:
+ * @arg @ref TMR0_FLAG
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t TMR0_GetStatus(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag)
+{
+ en_flag_status_t enFlagSta = RESET;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_TMR0_UNIT(TMR0x));
+ DDL_ASSERT(IS_TMR0_FLAG(u32Flag));
+
+ if (0UL != (READ_REG32_BIT(TMR0x->STFLR, u32Flag))) {
+ enFlagSta = SET;
+ }
+
+ return enFlagSta;
+}
+
+/**
+ * @brief Clear Tmr0 status.
+ * @param [in] TMR0x Pointer to TMR0 unit instance
+ * This parameter can be one of the following values:
+ * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance
+ * @param [in] u32Flag TMR0 flag type
+ * This parameter can be any combination value of the following values:
+ * @arg @ref TMR0_FLAG
+ * @retval None
+ */
+void TMR0_ClearStatus(CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_TMR0_UNIT(TMR0x));
+ DDL_ASSERT(IS_TMR0_FLAG(u32Flag));
+
+ CLR_REG32_BIT(TMR0x->STFLR, u32Flag);
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_TMR0_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_tmr2.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_tmr2.c
new file mode 100644
index 0000000000..854aad86d8
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_tmr2.c
@@ -0,0 +1,808 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_tmr2.c
+ * @brief This file provides firmware functions to manage the TMR2(Timer2).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_tmr2.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_TMR2 TMR2
+ * @brief TMR2 Driver Library
+ * @{
+ */
+#if (LL_TMR2_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup TMR2_Local_Macros TMR2 Local Macros
+ * @{
+ */
+
+/**
+ * @defgroup TMR2_Configuration_Bit_Mask TMR2 Configuration Bit Mask
+ * @{
+ */
+#define TMR2_BCONR_INIT_MASK (TMR2_BCONR_CAPMDA | TMR2_BCONR_SYNSA | TMR2_BCONR_SYNCLKA | \
+ TMR2_BCONR_ASYNCLKA | TMR2_BCONR_CKDIVA | TMR2_BCONR_SYNCLKAT)
+#define TMR2_BCONR_CLK_CFG_MASK (TMR2_BCONR_SYNSA | TMR2_BCONR_SYNCLKA | \
+ TMR2_BCONR_ASYNCLKA | TMR2_BCONR_SYNCLKAT)
+
+#define TMR2_PWM_POLARITY_MASK (TMR2_PCONR_STACA | TMR2_PCONR_STPCA | TMR2_PCONR_CMPCA)
+#define TMR2_FILTER_CLK_DIV_MASK (TMR2_PCONR_NOFICKA)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR2_Channel_Cfg_Bit_Field_Offset TMR2 Channel Configuration Bit Field Offset
+ * @{
+ */
+#define TMR2_CH_OFFSET (16U)
+
+#define TMR2_PWM_POLARITY_OFFSET (2U)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR2_Check_Parameters_Validity TMR2 check parameters validity
+ * @{
+ */
+#define IS_TMR2_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask)))
+
+#define IS_TMR2_UNIT(x) \
+( ((x) == CM_TMR2_1) || \
+ ((x) == CM_TMR2_2) || \
+ ((x) == CM_TMR2_3) || \
+ ((x) == CM_TMR2_4))
+
+#define IS_TMR2_CH(x) ((x) <= TMR2_CH_B)
+
+#define IS_TMR2_FUNC(x) (((x) == TMR2_FUNC_CMP) || ((x) == TMR2_FUNC_CAPT))
+
+#define IS_TMR2_CLK_SRC(x) \
+( ((x) == TMR2_CLK_PCLK1) || \
+ ((x) == TMR2_CLK_TRIG_RISING) || \
+ ((x) == TMR2_CLK_TRIG_FALLING) || \
+ ((x) == TMR2_CLK_EVT) || \
+ ((x) == TMR2_CLK_TMR6_OVF) || \
+ ((x) == TMR2_CLK_TMR6_UDF) || \
+ ((x) == TMR2_CLK_TMR6_OVF_UDF) || \
+ ((x) == TMR2_CLK_LRC) || \
+ ((x) == TMR2_CLK_XTAL32) || \
+ ((x) == TMR2_CLK_PIN_CLK))
+
+#define IS_TMR2_CLK_DIV(x) \
+( ((x) == TMR2_CLK_DIV1) || \
+ ((x) == TMR2_CLK_DIV2) || \
+ ((x) == TMR2_CLK_DIV4) || \
+ ((x) == TMR2_CLK_DIV8) || \
+ ((x) == TMR2_CLK_DIV16) || \
+ ((x) == TMR2_CLK_DIV32) || \
+ ((x) == TMR2_CLK_DIV64) || \
+ ((x) == TMR2_CLK_DIV128) || \
+ ((x) == TMR2_CLK_DIV256) || \
+ ((x) == TMR2_CLK_DIV512) || \
+ ((x) == TMR2_CLK_DIV1024))
+
+#define IS_TMR2_INT(x) IS_TMR2_BIT_MASK((x), TMR2_INT_ALL)
+
+#define IS_TMR2_FLAG(x) IS_TMR2_BIT_MASK((x), TMR2_FLAG_ALL)
+
+#define IS_TMR2_PWM_START_POLARITY(x) \
+( ((x) == TMR2_PWM_LOW) || \
+ ((x) == TMR2_PWM_HIGH) || \
+ ((x) == TMR2_PWM_HOLD))
+
+#define IS_TMR2_PWM_STOP_POLARITY(x) \
+( ((x) == TMR2_PWM_LOW) || \
+ ((x) == TMR2_PWM_HIGH) || \
+ ((x) == TMR2_PWM_HOLD))
+
+#define IS_TMR2_PWM_MATCH_CMP_POLARITY(x) \
+( ((x) == TMR2_PWM_LOW) || \
+ ((x) == TMR2_PWM_HIGH) || \
+ ((x) == TMR2_PWM_HOLD) || \
+ ((x) == TMR2_PWM_INVT))
+
+#define IS_TMR2_PWM_POLARITY(st, pol) \
+( (((st) == TMR2_CNT_STAT_START) && IS_TMR2_PWM_START_POLARITY(pol)) || \
+ (((st) == TMR2_CNT_STAT_STOP) && IS_TMR2_PWM_STOP_POLARITY(pol)) || \
+ (((st) == TMR2_CNT_STAT_MATCH_CMP) && IS_TMR2_PWM_MATCH_CMP_POLARITY(pol)))
+
+#define IS_TMR2_START_COND(x) IS_TMR2_BIT_MASK((x), TMR2_START_COND_ALL)
+
+#define IS_TMR2_STOP_COND(x) IS_TMR2_BIT_MASK((x), TMR2_STOP_COND_ALL)
+
+#define IS_TMR2_CLR_COND(x) IS_TMR2_BIT_MASK((x), TMR2_CLR_COND_ALL)
+
+#define IS_TMR2_CAPT_COND(x) IS_TMR2_BIT_MASK((x), TMR2_CAPT_COND_ALL)
+
+#define IS_TMR2_FILTER_CLK_DIV(x) \
+( ((x) == TMR2_FILTER_CLK_DIV1) || \
+ ((x) == TMR2_FILTER_CLK_DIV4) || \
+ ((x) == TMR2_FILTER_CLK_DIV16) || \
+ ((x) == TMR2_FILTER_CLK_DIV64))
+
+#define IS_TMR2_VALID_VAL(x) ((x) <= 0xFFFFUL)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup TMR2_Global_Functions TMR2 Global Functions
+ * @{
+ */
+
+/**
+ * @brief Initializes the specified TMR2 channel according to the specified parameters
+ * in the structure stc_tmr2_init_t
+ * @param [in] TMR2x Pointer to TMR2 instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMR2_x or CM_TMR2
+ * @param [in] u32Ch TMR2 channel.
+ * This parameter can be a value of @ref TMR2_Channel
+ * @param [in] pstcTmr2Init Pointer to a stc_tmr2_init_t structure value that
+ * contains the configuration information for the TMR2 channel.
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_INVD_PARAM: pstcTmr2Init == NULL.
+ */
+int32_t TMR2_Init(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, const stc_tmr2_init_t *pstcTmr2Init)
+{
+ uint32_t u32Tmp;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ __IO uint32_t *reg32CMPR;
+
+ DDL_ASSERT(IS_TMR2_UNIT(TMR2x));
+ DDL_ASSERT(IS_TMR2_CH(u32Ch));
+
+ if (pstcTmr2Init != NULL) {
+ DDL_ASSERT(IS_TMR2_CLK_SRC(pstcTmr2Init->u32ClockSrc));
+ DDL_ASSERT(IS_TMR2_CLK_DIV(pstcTmr2Init->u32ClockDiv));
+ DDL_ASSERT(IS_TMR2_FUNC(pstcTmr2Init->u32Func));
+ DDL_ASSERT(IS_TMR2_VALID_VAL(pstcTmr2Init->u32CompareValue));
+
+ u32Tmp = pstcTmr2Init->u32Func | pstcTmr2Init->u32ClockSrc |
+ pstcTmr2Init->u32ClockDiv;
+ reg32CMPR = (__IO uint32_t *)((uint32_t)&TMR2x->CMPAR);
+ WRITE_REG32(reg32CMPR[u32Ch], pstcTmr2Init->u32CompareValue);
+ /* Channel bit filed offset. */
+ u32Ch *= TMR2_CH_OFFSET;
+ MODIFY_REG32(TMR2x->BCONR, (TMR2_BCONR_INIT_MASK << u32Ch), (u32Tmp << u32Ch));
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set a default value for TMR2 initialization structure.
+ * @param [in] pstcTmr2Init Pointer to a stc_tmr2_init_t structure that
+ * contains configuration information.
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_INVD_PARAM: pstcTmr2Init == NULL.
+ */
+int32_t TMR2_StructInit(stc_tmr2_init_t *pstcTmr2Init)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (pstcTmr2Init != NULL) {
+ pstcTmr2Init->u32ClockSrc = TMR2_CLK_PCLK1;
+ pstcTmr2Init->u32ClockDiv = TMR2_CLK_DIV1;
+ pstcTmr2Init->u32Func = TMR2_FUNC_CMP;
+ pstcTmr2Init->u32CompareValue = 0xFFFFUL;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief De-initializes the specified TMR2 unit.
+ * @param [in] TMR2x Pointer to TMR2 instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMR2_x or CM_TMR2
+ * @retval None
+ */
+void TMR2_DeInit(CM_TMR2_TypeDef *TMR2x)
+{
+ DDL_ASSERT(IS_TMR2_UNIT(TMR2x));
+
+ TMR2_Stop(TMR2x, TMR2_CH_A);
+ TMR2_Stop(TMR2x, TMR2_CH_B);
+ WRITE_REG32(TMR2x->CMPBR, 0xFFFFU);
+ CLR_REG32(TMR2x->CNTBR);
+ CLR_REG32(TMR2x->CNTAR);
+ CLR_REG32(TMR2x->BCONR);
+ CLR_REG32(TMR2x->ICONR);
+ CLR_REG32(TMR2x->PCONR);
+ CLR_REG32(TMR2x->HCONR);
+ CLR_REG32(TMR2x->STFLR);
+ WRITE_REG32(TMR2x->CMPAR, 0xFFFFU);
+}
+
+/**
+ * @brief Specifies the function mode for the specified TMR2 channel.
+ * @param [in] TMR2x Pointer to TMR2 instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMR2_x or CM_TMR2
+ * @param [in] u32Ch TMR2 channel.
+ * This parameter can be a value of @ref TMR2_Channel
+ * @param [in] u32Func Function mode.
+ * This parameter can be a value of @ref TMR2_Function
+ * @arg TMR2_FUNC_CMP: The function of TMR2 channel is ouput compare.
+ * @arg TMR2_FUNC_CAPT: The function of TMR2 channel is input capture.
+ * @retval None
+ */
+void TMR2_SetFunc(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Func)
+{
+ DDL_ASSERT(IS_TMR2_UNIT(TMR2x));
+ DDL_ASSERT(IS_TMR2_CH(u32Ch));
+ DDL_ASSERT(IS_TMR2_FUNC(u32Func));
+
+ /* Channel bit filed offset. */
+ u32Ch *= TMR2_CH_OFFSET;
+ MODIFY_REG32(TMR2x->BCONR, (TMR2_BCONR_CAPMDA << u32Ch), (u32Func << u32Ch));
+}
+
+/**
+ * @brief Specifies the clock source for the specified TMR2 channel.
+ * @param [in] TMR2x Pointer to TMR2 instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMR2_x or CM_TMR2
+ * @param [in] u32Ch TMR2 channel.
+ * This parameter can be a value of @ref TMR2_Channel
+ * @param [in] u32Src Clock source.
+ * This parameter can be a value of @ref TMR2_Clock_Source
+ * @retval None
+ */
+void TMR2_SetClockSrc(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Src)
+{
+ DDL_ASSERT(IS_TMR2_UNIT(TMR2x));
+ DDL_ASSERT(IS_TMR2_CH(u32Ch));
+ DDL_ASSERT(IS_TMR2_CLK_SRC(u32Src));
+
+ /* Channel bit filed offset. */
+ u32Ch *= TMR2_CH_OFFSET;
+ MODIFY_REG32(TMR2x->BCONR, (TMR2_BCONR_CLK_CFG_MASK << u32Ch), (u32Src << u32Ch));
+}
+
+/**
+ * @brief Specifies the clock divider for the specified TMR2 channel.
+ * @param [in] TMR2x Pointer to TMR2 instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMR2_x or CM_TMR2
+ * @param [in] u32Ch TMR2 channel.
+ * This parameter can be a value of @ref TMR2_Channel
+ * @param [in] u32Div Clock divider.
+ * This parameter can be a value of @ref TMR2_Clock_Divider
+ * @retval None
+ */
+void TMR2_SetClockDiv(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Div)
+{
+ DDL_ASSERT(IS_TMR2_UNIT(TMR2x));
+ DDL_ASSERT(IS_TMR2_CH(u32Ch));
+ DDL_ASSERT(IS_TMR2_CLK_DIV(u32Div));
+
+ /* Channel bit filed offset. */
+ u32Ch *= TMR2_CH_OFFSET;
+ MODIFY_REG32(TMR2x->BCONR, (TMR2_BCONR_CKDIVA << u32Ch), (u32Div << u32Ch));
+}
+
+/**
+ * @brief Set a default value for the TMR2 output compare configuration structure.
+ * @param [in] pstPwmInit Pointer to a stc_tmr2_pwm_init_t structure value that
+ * contains the configuration information for the TMR2 PWM.
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_INVD_PARAM: pstcTmr2Init == NULL.
+ */
+int32_t TMR2_PWM_StructInit(stc_tmr2_pwm_init_t *pstPwmInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (pstPwmInit != NULL) {
+ pstPwmInit->u32StartPolarity = TMR2_PWM_HIGH;
+ pstPwmInit->u32StopPolarity = TMR2_PWM_LOW;
+ pstPwmInit->u32CompareMatchPolarity = TMR2_PWM_INVT;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Configures the PWM of the specified TMR2 channel
+ * according to the specified parameters in the structure @ref stc_tmr2_pwm_init_t
+ * @param [in] TMR2x Pointer to TMR2 instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMR2_x or CM_TMR2
+ * @param [in] u32Ch TMR2 channel.
+ * This parameter can be a value of @ref TMR2_Channel
+ * @param [in] pstPwmInit Pointer to a @ref stc_tmr2_pwm_init_t structure value that
+ * contains the configuration information for the TMR2 PWM.
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_INVD_PARAM: pstcTmr2Init == NULL.
+ */
+int32_t TMR2_PWM_Init(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, const stc_tmr2_pwm_init_t *pstPwmInit)
+{
+ uint32_t u32Tmp;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ DDL_ASSERT(IS_TMR2_UNIT(TMR2x));
+ DDL_ASSERT(IS_TMR2_CH(u32Ch));
+
+ if (pstPwmInit != NULL) {
+ DDL_ASSERT(IS_TMR2_PWM_START_POLARITY(pstPwmInit->u32StartPolarity));
+ DDL_ASSERT(IS_TMR2_PWM_STOP_POLARITY(pstPwmInit->u32StopPolarity));
+ DDL_ASSERT(IS_TMR2_PWM_MATCH_CMP_POLARITY(pstPwmInit->u32CompareMatchPolarity));
+ /* Configures PWM polarity. */
+ u32Tmp = (pstPwmInit->u32StartPolarity << TMR2_PCONR_STACA_POS) | \
+ (pstPwmInit->u32StopPolarity << TMR2_PCONR_STPCA_POS) | \
+ (pstPwmInit->u32CompareMatchPolarity << TMR2_PCONR_CMPCA_POS);
+ u32Ch *= TMR2_CH_OFFSET;
+ MODIFY_REG32(TMR2x->PCONR, (TMR2_PWM_POLARITY_MASK << u32Ch), (u32Tmp << u32Ch));
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Enable or disable PWM output of the specified TMR2 channel.
+ * @param [in] TMR2x Pointer to TMR2 instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMR2_x or CM_TMR2
+ * @param [in] u32Ch TMR2 channel.
+ * This parameter can be a value of @ref TMR2_Channel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR2_PWM_OutputCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, en_functional_state_t enNewState)
+{
+ uint32_t u32PCONRAddr;
+ uint8_t au8EnPos[] = {TMR2_PCONR_OUTENA_POS, TMR2_PCONR_OUTENB_POS};
+ DDL_ASSERT(IS_TMR2_UNIT(TMR2x));
+ DDL_ASSERT(IS_TMR2_CH(u32Ch));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u32PCONRAddr = (uint32_t)&TMR2x->PCONR;
+ WRITE_REG32(PERIPH_BIT_BAND(u32PCONRAddr, au8EnPos[u32Ch]), enNewState);
+}
+
+/**
+ * @brief Enable or disable the specified hardware capture condition.
+ * @param [in] TMR2x Pointer to TMR2 instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMR2_x or CM_TMR2
+ * @param [in] u32Ch TMR2 channel.
+ * This parameter can be a value of @ref TMR2_Channel
+ * @param [in] u32Cond Hardware capture condition.
+ * This parameter can be a value of @ref TMR2_Capture_Condition
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR2_HWCaptureCondCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_TMR2_UNIT(TMR2x));
+ DDL_ASSERT(IS_TMR2_CH(u32Ch));
+ DDL_ASSERT(IS_TMR2_CAPT_COND(u32Cond));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u32Cond <<= (u32Ch * TMR2_CH_OFFSET);
+
+ if (enNewState == ENABLE) {
+ SET_REG32_BIT(TMR2x->HCONR, u32Cond);
+ } else {
+ CLR_REG32_BIT(TMR2x->HCONR, u32Cond);
+ }
+}
+
+/**
+ * @brief Enable or disable the specified hardware start condition.
+ * @param [in] TMR2x Pointer to TMR2 instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMR2_x or CM_TMR2
+ * @param [in] u32Ch TMR2 channel.
+ * This parameter can be a value of @ref TMR2_Channel
+ * @param [in] u32Cond Hardware start condition.
+ * This parameter can be a value of @ref TMR2_Start_Condition
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR2_HWStartCondCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_TMR2_UNIT(TMR2x));
+ DDL_ASSERT(IS_TMR2_CH(u32Ch));
+ DDL_ASSERT(IS_TMR2_START_COND(u32Cond));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u32Cond <<= (u32Ch * TMR2_CH_OFFSET);
+
+ if (enNewState == ENABLE) {
+ SET_REG32_BIT(TMR2x->HCONR, u32Cond);
+ } else {
+ CLR_REG32_BIT(TMR2x->HCONR, u32Cond);
+ }
+}
+
+/**
+ * @brief Enable or disable the specified hardware stop condition.
+ * @param [in] TMR2x Pointer to TMR2 instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMR2_x or CM_TMR2
+ * @param [in] u32Ch TMR2 channel.
+ * This parameter can be a value of @ref TMR2_Channel
+ * @param [in] u32Cond Hardware stop condition.
+ * This parameter can be a value of @ref TMR2_Stop_Condition
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR2_HWStopCondCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_TMR2_UNIT(TMR2x));
+ DDL_ASSERT(IS_TMR2_CH(u32Ch));
+ DDL_ASSERT(IS_TMR2_STOP_COND(u32Cond));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u32Cond <<= (u32Ch * TMR2_CH_OFFSET);
+
+ if (enNewState == ENABLE) {
+ SET_REG32_BIT(TMR2x->HCONR, u32Cond);
+ } else {
+ CLR_REG32_BIT(TMR2x->HCONR, u32Cond);
+ }
+}
+
+/**
+ * @brief Enable or disable the specified hardware clear condition.
+ * @param [in] TMR2x Pointer to TMR2 instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMR2_x or CM_TMR2
+ * @param [in] u32Ch TMR2 channel.
+ * This parameter can be a value of @ref TMR2_Channel
+ * @param [in] u32Cond Hardware clear condition.
+ * This parameter can be a value of @ref TMR2_Clear_Condition
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR2_HWClearCondCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_TMR2_UNIT(TMR2x));
+ DDL_ASSERT(IS_TMR2_CH(u32Ch));
+ DDL_ASSERT(IS_TMR2_CLR_COND(u32Cond));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u32Cond <<= (u32Ch * TMR2_CH_OFFSET);
+
+ if (enNewState == ENABLE) {
+ SET_REG32_BIT(TMR2x->HCONR, u32Cond);
+ } else {
+ CLR_REG32_BIT(TMR2x->HCONR, u32Cond);
+ }
+}
+
+/**
+ * @brief Specifies the clock divider of filter.
+ * @param [in] TMR2x Pointer to TMR2 instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMR2_x or CM_TMR2
+ * @param [in] u32Ch TMR2 channel.
+ * This parameter can be a value of @ref TMR2_Channel
+ * @param [in] u32Div The clock source divider of the filter.
+ * This parameter can be a value of @ref TMR2_Filter_Clock_Divider
+ * @arg TMR2_FILTER_CLK_DIV1: The filter clock is the clock of timer2 / 1.
+ * @arg TMR2_FILTER_CLK_DIV4: The filter clock is the clock of timer2 / 4.
+ * @arg TMR2_FILTER_CLK_DIV16: The filter clock is the clock of timer2 / 16.
+ * @arg TMR2_FILTER_CLK_DIV64: The filter clock is the clock of timer2 / 64.
+ * @retval None
+ */
+void TMR2_SetFilterClockDiv(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Div)
+{
+ DDL_ASSERT(IS_TMR2_UNIT(TMR2x));
+ DDL_ASSERT(IS_TMR2_CH(u32Ch));
+ DDL_ASSERT(IS_TMR2_FILTER_CLK_DIV(u32Div));
+
+ u32Ch *= TMR2_CH_OFFSET;
+ MODIFY_REG32(TMR2x->PCONR, TMR2_FILTER_CLK_DIV_MASK << u32Ch, u32Div << u32Ch);
+}
+
+/**
+ * @brief Enable or disable the filter of the specified TMR2 channel.
+ * @param [in] TMR2x Pointer to TMR2 instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMR2_x or CM_TMR2
+ * @param [in] u32Ch TMR2 channel.
+ * This parameter can be a value of @ref TMR2_Channel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR2_FilterCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, en_functional_state_t enNewState)
+{
+ uint32_t u32PCONRAddr;
+ uint8_t au8EnPos[] = {TMR2_PCONR_NOFIENA_POS, TMR2_PCONR_NOFIENB_POS};
+ DDL_ASSERT(IS_TMR2_UNIT(TMR2x));
+ DDL_ASSERT(IS_TMR2_CH(u32Ch));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u32PCONRAddr = (uint32_t)&TMR2x->PCONR;
+ WRITE_REG32(PERIPH_BIT_BAND(u32PCONRAddr, au8EnPos[u32Ch]), enNewState);
+}
+
+/**
+ * @brief Enable or disable the interrupt of the specified TMR2 channel.
+ * @param [in] TMR2x Pointer to TMR2 instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMR2_x or CM_TMR2
+ * @param [in] u32IntType The interrupt type.
+ * This parameter can be values of @ref TMR2_Interrupt_Type
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR2_IntCmd(CM_TMR2_TypeDef *TMR2x, uint32_t u32IntType, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_TMR2_UNIT(TMR2x));
+ DDL_ASSERT(IS_TMR2_INT(u32IntType));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (enNewState == ENABLE) {
+ SET_REG32_BIT(TMR2x->ICONR, u32IntType);
+ } else {
+ CLR_REG32_BIT(TMR2x->ICONR, u32IntType);
+ }
+}
+
+/**
+ * @brief Start the specified TMR2 channel.
+ * @param [in] TMR2x Pointer to TMR2 instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMR2_x or CM_TMR2
+ * @param [in] u32Ch TMR2 channel.
+ * This parameter can be a value of @ref TMR2_Channel
+ * @retval None
+ */
+void TMR2_Start(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch)
+{
+ DDL_ASSERT(IS_TMR2_UNIT(TMR2x));
+ DDL_ASSERT(IS_TMR2_CH(u32Ch));
+
+ SET_REG32_BIT(TMR2x->BCONR, TMR2_BCONR_CSTA << (u32Ch * TMR2_CH_OFFSET));
+}
+
+/**
+ * @brief Stop the specified TMR2 channel.
+ * @param [in] TMR2x Pointer to TMR2 instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMR2_x or CM_TMR2
+ * @param [in] u32Ch TMR2 channel.
+ * This parameter can be a value of @ref TMR2_Channel
+ * @retval None
+ */
+void TMR2_Stop(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch)
+{
+ DDL_ASSERT(IS_TMR2_UNIT(TMR2x));
+ DDL_ASSERT(IS_TMR2_CH(u32Ch));
+
+ CLR_REG32_BIT(TMR2x->BCONR, TMR2_BCONR_CSTA << (u32Ch * TMR2_CH_OFFSET));
+}
+
+/**
+ * @brief Get the status of the specified TMR2 flag.
+ * @param [in] TMR2x Pointer to TMR2 instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMR2_x or CM_TMR2
+ * @param [in] u32Flag TMR2 status flag.
+ * This parameter can be values of @ref TMR2_Status_Flag
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t TMR2_GetStatus(const CM_TMR2_TypeDef *TMR2x, uint32_t u32Flag)
+{
+ en_flag_status_t enStatus = RESET;
+
+ DDL_ASSERT(IS_TMR2_UNIT(TMR2x));
+ DDL_ASSERT(IS_TMR2_FLAG(u32Flag));
+
+ if (READ_REG32_BIT(TMR2x->STFLR, u32Flag) != 0U) {
+ enStatus = SET;
+ }
+
+ return enStatus;
+}
+
+/**
+ * @brief Clear the status of the specified TMR2 flag.
+ * @param [in] TMR2x Pointer to TMR2 instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMR2_x or CM_TMR2
+ * @param [in] u32Flag TMR2 status flag.
+ * This parameter can be values of @ref TMR2_Status_Flag
+ * @retval None
+ */
+void TMR2_ClearStatus(CM_TMR2_TypeDef *TMR2x, uint32_t u32Flag)
+{
+ DDL_ASSERT(IS_TMR2_UNIT(TMR2x));
+ DDL_ASSERT(IS_TMR2_FLAG(u32Flag));
+ CLR_REG32_BIT(TMR2x->STFLR, u32Flag);
+}
+
+/**
+ * @brief Set compare value for the specified TMR2 channel.
+ * @param [in] TMR2x Pointer to TMR2 instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMR2_x or CM_TMR2
+ * @param [in] u32Ch The TMR2 channel.
+ * This parameter can be a value of @ref TMR2_Channel
+ * @param [in] u32Value The compare reference value of the specified TMR2 channel.
+ * This parameter can be a number between 0U and 0xFFFFU, inclusive.
+ * @retval None
+ */
+void TMR2_SetCompareValue(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Value)
+{
+ __IO uint32_t *reg32CMPR;
+
+ DDL_ASSERT(IS_TMR2_UNIT(TMR2x));
+ DDL_ASSERT(IS_TMR2_VALID_VAL(u32Value));
+
+ reg32CMPR = (__IO uint32_t *)((uint32_t)&TMR2x->CMPAR);
+ WRITE_REG32(reg32CMPR[u32Ch], u32Value);
+}
+
+/**
+ * @brief Get compare value of the specified TMR2 channel.
+ * @param [in] TMR2x Pointer to TMR2 instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMR2_x or CM_TMR2
+ * @param [in] u32Ch The TMR2 channel.
+ * This parameter can be a value of @ref TMR2_Channel
+ * @retval The compare value of the specified TMR2 channel. A number between 0U and 0xFFFFU, inclusive.
+ */
+uint32_t TMR2_GetCompareValue(const CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch)
+{
+ __IO uint32_t *reg32CMPR;
+
+ DDL_ASSERT(IS_TMR2_UNIT(TMR2x));
+ DDL_ASSERT(IS_TMR2_CH(u32Ch));
+
+ reg32CMPR = (__IO uint32_t *)((uint32_t)&TMR2x->CMPAR);
+ return reg32CMPR[u32Ch];
+}
+
+/**
+ * @brief Set counter value for the specified TMR2 channel.
+ * @param [in] TMR2x Pointer to TMR2 instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMR2_x or CM_TMR2
+ * @param [in] u32Ch The TMR2 channel.
+ * This parameter can be a value of @ref TMR2_Channel
+ * @param [in] u32Value The counter value for the specified TMR2 channel.
+ * This parameter can be a number between 0U and 0xFFFFU, inclusive.
+ * @retval None
+ */
+void TMR2_SetCountValue(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint32_t u32Value)
+{
+ __IO uint32_t *reg32CNTR;
+
+ DDL_ASSERT(IS_TMR2_UNIT(TMR2x));
+ DDL_ASSERT(IS_TMR2_CH(u32Ch));
+ DDL_ASSERT(IS_TMR2_VALID_VAL(u32Value));
+
+ reg32CNTR = (__IO uint32_t *)((uint32_t)&TMR2x->CNTAR);
+ WRITE_REG32(reg32CNTR[u32Ch], u32Value);
+}
+
+/**
+ * @brief Get counter value of the specified TMR2 channel.
+ * @param [in] TMR2x Pointer to TMR2 instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMR2_x or CM_TMR2
+ * @param [in] u32Ch The TMR2 channel.
+ * This parameter can be a value of @ref TMR2_Channel
+ * @retval The counter value of the specified TMR2 channel. A number between 0U and 0xFFFFU, inclusive.
+ */
+uint32_t TMR2_GetCountValue(const CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch)
+{
+ __IO uint32_t *reg32CNTR;
+
+ DDL_ASSERT(IS_TMR2_UNIT(TMR2x));
+ DDL_ASSERT(IS_TMR2_CH(u32Ch));
+
+ reg32CNTR = (__IO uint32_t *)((uint32_t)&TMR2x->CNTAR);
+ return reg32CNTR[u32Ch];
+}
+
+/**
+ * @brief Specifies the ouput polarity of the PWM at the specified state of counter.
+ * @param [in] TMR2x Pointer to TMR2 instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMR2_x or CM_TMR2
+ * @param [in] u32Ch TMR2 channel.
+ * This parameter can be a value @ref TMR2_Channel
+ * @param [in] u8CountState TMR2 counter state.
+ * This parameter can be a value @ref TMR2_Counter_State
+ * @param [in] u32Polarity The polarity of PWM.
+ * This parameter can be a value @ref TMR2_PWM_Polarity
+ * @retval None
+ */
+void TMR2_PWM_SetPolarity(CM_TMR2_TypeDef *TMR2x, uint32_t u32Ch, uint8_t u8CountState, uint32_t u32Polarity)
+{
+ uint32_t u32PolarityPos;
+
+ DDL_ASSERT(IS_TMR2_UNIT(TMR2x));
+ DDL_ASSERT(IS_TMR2_CH(u32Ch));
+ DDL_ASSERT(IS_TMR2_PWM_POLARITY(u8CountState, u32Polarity));
+
+ u32PolarityPos = ((uint32_t)u8CountState * TMR2_PWM_POLARITY_OFFSET) + (u32Ch * TMR2_CH_OFFSET);
+ MODIFY_REG32(TMR2x->PCONR, TMR2_PCONR_STACA << u32PolarityPos, u32Polarity << u32PolarityPos);
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_TMR2_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_tmr4.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_tmr4.c
new file mode 100644
index 0000000000..6fd9662ccb
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_tmr4.c
@@ -0,0 +1,2400 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_tmr4.c
+ * @brief This file provides firmware functions to manage the TMR4(Timer4).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Add function comments: macros group @ref TMR4_OC_Channel
+ Modify function return value comments: TMR4_OC_GetPolarity
+ Modify function parameter comments: TMR4_PWM_SetPolarity
+ Modify typo
+ Modify function: TMR4_DeInit, TMR4_OC_DeInit, TMR4_PWM_DeInit, TMR4_EVT_DeInit
+ Modify macro-definition: IS_TMR4_OC_BUF_OBJECT
+ Fix magic number of function: TMR4_OC_StructInit
+ 2023-09-30 CDT Rename macro-define: TMR4_INT_EVT_CMP_xx -> TMR4_INT_SCMP_EVTx
+ Rename macro-define: TMR4_FLAG_EVT_CMP_xx -> TMR4_FLAG_SCMP_EVTx
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_tmr4.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_TMR4 TMR4
+ * @brief TMR4 Driver Library
+ * @{
+ */
+
+#if (LL_TMR4_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup TMR4_Local_Macros TMR4 Local Macros
+ * @{
+ */
+
+/**
+ * @defgroup TMR4_Check_Parameters_Validity TMR4 Check Parameters Validity
+ * @{
+ */
+#define IS_TMR4_UNIT(x) ((x) == CM_TMR4)
+
+#define IS_TMR4_CLK_DIV(x) \
+( ((x) == TMR4_CLK_DIV1) || \
+ ((x) == TMR4_CLK_DIV2) || \
+ ((x) == TMR4_CLK_DIV4) || \
+ ((x) == TMR4_CLK_DIV8) || \
+ ((x) == TMR4_CLK_DIV16) || \
+ ((x) == TMR4_CLK_DIV32) || \
+ ((x) == TMR4_CLK_DIV64) || \
+ ((x) == TMR4_CLK_DIV128) || \
+ ((x) == TMR4_CLK_DIV256) || \
+ ((x) == TMR4_CLK_DIV512) || \
+ ((x) == TMR4_CLK_DIV1024))
+
+#define IS_TMR4_MD(x) \
+( ((x) == TMR4_MD_SAWTOOTH) || \
+ ((x) == TMR4_MD_TRIANGLE))
+
+#define IS_TMR4_CLK_SRC(x) \
+( ((x) == TMR4_CLK_SRC_INTERNCLK) || \
+ ((x) == TMR4_CLK_SRC_EXTCLK))
+
+#define IS_TMR4_INT_CNT_MASKTIME(x) ((x) <= TMR4_INT_CNT_MASK15)
+
+#define IS_TMR4_INT_CNT(x) \
+( ((x) != 0UL) && \
+ (((x) | TMR4_INT_CNT_MASK) == TMR4_INT_CNT_MASK))
+
+#define IS_TMR4_INT(x) \
+( ((x) != 0UL) && \
+ (((x) | TMR4_INT_ALL) == TMR4_INT_ALL))
+
+#define IS_TMR4_FLAG(x) \
+( ((x) != 0UL) && \
+ (((x) | TMR4_FLAG_ALL) == TMR4_FLAG_ALL))
+
+#define IS_TMR4_OC_HIGH_CH(x) (((x) & 0x1UL) == 0UL)
+#define IS_TMR4_OC_LOW_CH(x) (((x) & 0x1UL) == 1UL)
+
+#define IS_TMR4_OC_BUF_OBJECT(x) \
+( (((x) | TMR4_OC_BUF_OBJECT_MASK) == TMR4_OC_BUF_OBJECT_MASK))
+
+#define IS_TMR4_OC_BUF_COND(x) \
+( ((x) == TMR4_OC_BUF_COND_IMMED) || \
+ ((x) == TMR4_OC_BUF_COND_PEAK) || \
+ ((x) == TMR4_OC_BUF_COND_VALLEY) || \
+ ((x) == TMR4_OC_BUF_COND_PEAK_VALLEY))
+
+#define IS_TMR4_OC_INVD_POLARITY(x) \
+( ((x) == TMR4_OC_INVD_LOW) || \
+ ((x) == TMR4_OC_INVD_HIGH))
+
+#define IS_TMR4_PWM_MD(x) \
+( ((x) == TMR4_PWM_MD_THROUGH) || \
+ ((x) == TMR4_PWM_MD_DEAD_TMR) || \
+ ((x) == TMR4_PWM_MD_DEAD_TMR_FILTER))
+
+#define IS_TMR4_PWM_POLARITY(x) \
+( ((x) == TMR4_PWM_OXH_HOLD_OXL_HOLD) || \
+ ((x) == TMR4_PWM_OXH_INVT_OXL_HOLD) || \
+ ((x) == TMR4_PWM_OXH_HOLD_OXL_INVT) || \
+ ((x) == TMR4_PWM_OXH_INVT_OXL_INVT))
+
+#define IS_TMR4_PWM_CLK_DIV(x) (((x) | TMR4_PWM_CLK_DIV128) == TMR4_PWM_CLK_DIV128)
+
+#define IS_TMR4_PWM_DEADTIME_REG_IDX(x) \
+( ((x) == TMR4_PWM_PDAR_IDX) || \
+ ((x) == TMR4_PWM_PDBR_IDX))
+
+#define IS_TMR4_PWM_OE_EFFECT(x) \
+( ((x) == TMR4_PWM_OE_EFFECT_IMMED) || \
+ ((x) == TMR4_PWM_OE_EFFECT_COUNT_PEAK) || \
+ ((x) == TMR4_PWM_OE_EFFECT_COUNT_VALLEY))
+
+#define IS_TMR4_PWM_PIN_MD(x) \
+( ((x) == TMR4_PWM_PIN_OUTPUT_OS) || \
+ ((x) == TMR4_PWM_PIN_OUTPUT_NORMAL))
+
+#define IS_TMR4_EVT_MATCH_COND(x) (((x) | TMR4_EVT_MATCH_CNT_ALL) == TMR4_EVT_MATCH_CNT_ALL)
+
+#define IS_TMR4_EVT_MASK_TYPE(x) \
+( ((x) != 0U) || \
+ (((x) | TMR4_EVT_MASK_TYPE_ALL) == TMR4_EVT_MASK_TYPE_ALL))
+
+#define IS_TMR4_EVT_DELAY_OBJECT(x) \
+( ((x) == TMR4_EVT_DELAY_OCCRXH) || \
+ ((x) == TMR4_EVT_DELAY_OCCRXL))
+
+#define IS_TMR4_EVT_MD(x) \
+( ((x) == TMR4_EVT_MD_DELAY) || \
+ ((x) == TMR4_EVT_MD_CMP))
+
+#define IS_TMR4_EVT_MASK(x) (((x) | TMR4_EVT_MASK15) == TMR4_EVT_MASK15)
+
+#define IS_TMR4_EVT_BUF_COND(x) \
+( ((x) == TMR4_EVT_BUF_COND_IMMED) || \
+ ((x) == TMR4_EVT_BUF_COND_PEAK) || \
+ ((x) == TMR4_EVT_BUF_COND_VALLEY) || \
+ ((x) == TMR4_EVT_BUF_COND_PEAK_VALLEY))
+
+#define IS_TMR4_OC_CH(x) ((x) <= TMR4_OC_CH_WL)
+#define IS_TMR4_PWM_CH(x) ((x) <= TMR4_PWM_CH_W)
+#define IS_TMR4_PWM_PIN(x) ((x) <= TMR4_PWM_PIN_OWL)
+#define IS_TMR4_EVT_CH(x) ((x) <= TMR4_EVT_CH_WL)
+#define IS_TMR4_EVT_OUTPUT_EVT(x) \
+( ((x) >> TMR4_SCSR_EVTOS_POS) <= (TMR4_EVT_OUTPUT_EVT5 >> TMR4_SCSR_EVTOS_POS))
+#define IS_TMR4_EVT_OUTPUT_SIGNAL(x) ((x) <= TMR4_EVT_OUTPUT_EVT5_SIGNAL)
+
+#define IS_TMR4_PWM_ABNORMAL_PIN_STAT(x) ((x) <= TMR4_PWM_ABNORMAL_PIN_HIGH)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_Channel_Max TMR4 Channel Max
+ * @{
+ */
+#define TMR4_OC_CH_MAX (TMR4_OC_CH_WL)
+#define TMR4_PWM_CH_MAX (TMR4_PWM_CH_W)
+#define TMR4_EVT_CH_MAX (TMR4_EVT_CH_WL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_Flag_Interrupt_Mask TMR4 Flag and Interrupt Mask
+ * @{
+ */
+#define TMR4_FLAG_CNT_MASK (TMR4_FLAG_CNT_PEAK | TMR4_FLAG_CNT_VALLEY)
+#define TMR4_INT_CNT_MASK (TMR4_INT_CNT_PEAK | TMR4_INT_CNT_VALLEY)
+
+#define TMR4_FLAG_OC_MASK (TMR4_FLAG_OC_CMP_UH | TMR4_FLAG_OC_CMP_UL | TMR4_FLAG_OC_CMP_VH | \
+ TMR4_FLAG_OC_CMP_VL | TMR4_FLAG_OC_CMP_WH | TMR4_FLAG_OC_CMP_WL)
+#define TMR4_INT_OC_MASK (TMR4_INT_OC_CMP_UH | TMR4_INT_OC_CMP_UL | TMR4_INT_OC_CMP_VH | \
+ TMR4_INT_OC_CMP_VL | TMR4_INT_OC_CMP_WH | TMR4_INT_OC_CMP_WL)
+
+#define TMR4_FLAG_RELOAD_TMR_MASK (TMR4_FLAG_RELOAD_TMR_U | TMR4_FLAG_RELOAD_TMR_V | TMR4_FLAG_RELOAD_TMR_W)
+#define TMR4_INT_RELOAD_TMR_MASK (TMR4_INT_RELOAD_TMR_U | TMR4_INT_RELOAD_TMR_V | TMR4_INT_RELOAD_TMR_W)
+
+#define TMR4_FLAG_SCMP_EVT_MASK (TMR4_FLAG_SCMP_EVT0 | TMR4_FLAG_SCMP_EVT1 | TMR4_FLAG_SCMP_EVT2 | \
+ TMR4_FLAG_SCMP_EVT3 | TMR4_FLAG_SCMP_EVT4 | TMR4_FLAG_SCMP_EVT5)
+#define TMR4_INT_SCMP_EVT_MASK (TMR4_INT_SCMP_EVT0 | TMR4_INT_SCMP_EVT1 | TMR4_INT_SCMP_EVT2 | \
+ TMR4_INT_SCMP_EVT3 | TMR4_INT_SCMP_EVT4 | TMR4_INT_SCMP_EVT5)
+/**
+ * @}
+ */
+
+#define RCSR_REG_TYPE uint16_t
+
+/**
+ * @defgroup TMR4_Registers_Reset_Value TMR4 Registers Reset Value
+ * @{
+ */
+#define TMR4_CCSR_RST_VALUE (0x0040U)
+#define TMR4_SCER_RST_VALUE (0xFF00U)
+#define TMR4_SCMR_RST_VALUE (0xFF00U)
+#define TMR4_POCR_RST_VALUE (0xFF00U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_OC_Buffer_Object_Mask TMR4 OC Buffer Object Mask
+ * @{
+ */
+#define TMR4_OC_BUF_OBJECT_MASK (TMR4_OC_BUF_CMP_VALUE | TMR4_OC_BUF_CMP_MD)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_OCSR_Bit_Mask TMR4_OCSR Bit Mask
+ * @brief Get the specified TMR4_OCSR register bis value of the specified TMR4 OC channel
+ * @{
+ */
+#define TMR4_OCSR_OCEx_MASK(CH) (((uint16_t)TMR4_OCSR_OCEH) << ((CH) % 2UL))
+#define TMR4_OCSR_OCPx_MASK(CH) (((uint16_t)TMR4_OCSR_OCPH) << ((CH) % 2UL))
+#define TMR4_OCSR_OCIE_MASK (TMR4_OCSR_OCIEH | TMR4_OCSR_OCIEL)
+#define TMR4_OCSR_OCF_MASK (TMR4_OCSR_OCFH | TMR4_OCSR_OCFL)
+#define TMR4_OCSR_MASK(CH) \
+( ((uint16_t)(TMR4_OCSR_OCEH | TMR4_OCSR_OCPH | TMR4_OCSR_OCIEH | TMR4_OCSR_OCFH)) << (((CH) % 2UL)))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_OCSR_Bit TMR4_OCSR Bit
+ * @brief Get the specified TMR4_OCSR register bis value of the specified TMR4 OC channel
+ * @{
+ */
+#define TMR4_OCSR_OCEx(CH, OCEx) (((uint16_t)OCEx) << (((uint16_t)((CH) % 2UL)) + TMR4_OCSR_OCEH_POS))
+#define TMR4_OCSR_OCPx(CH, OCPx) (((uint16_t)OCPx) << ((CH) % 2UL))
+#define TMR4_OCSR_OCIEx(CH, OCIEx) (((uint16_t)OCIEx) << ((CH) % 2UL))
+#define TMR4_OCSR_OCFx(CH, OCFx) (((uint16_t)OCFx) << ((CH) % 2UL))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_OCER_Bit_Mask TMR4_OCER Bit Mask
+ * @brief Get the specified TMR4_OCER register bis value of the specified TMR4 OC channel
+ * @{
+ */
+#define TMR4_OCER_CxBUFEN_MASK(CH) (((uint16_t)TMR4_OCER_CHBUFEN) << (((CH) % 2UL) << 1U))
+#define TMR4_OCER_MxBUFEN_MASK(CH) (((uint16_t)TMR4_OCER_MHBUFEN) << (((CH) % 2UL) << 1U))
+#define TMR4_OCER_LMCx_MASK(CH) (((uint16_t)TMR4_OCER_LMCH) << ((CH) % 2UL))
+#define TMR4_OCER_LMMx_MASK(CH) (((uint16_t)TMR4_OCER_LMMH) << ((CH) % 2UL))
+#define TMR4_OCER_MCECx_MASK(CH) (((uint16_t)TMR4_OCER_MCECH) << ((CH) % 2UL))
+#define TMR4_OCER_MASK(CH) \
+( (((uint16_t)(TMR4_OCER_CHBUFEN | TMR4_OCER_MHBUFEN)) << (((CH) % 2UL) << 1U)) | \
+ (((uint16_t)(TMR4_OCER_LMCH | TMR4_OCER_LMMH | TMR4_OCER_MCECH)) << ((CH) % 2UL)))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_OCER_Bit TMR4_OCER Bit
+ * @brief Get the specified TMR4_OCER register bis value of the specified TMR4 OC channel
+ * @{
+ */
+#define TMR4_OCER_CxBUFEN(CH, CxBUFEN) ((uint16_t)((uint16_t)(CxBUFEN) << ((((CH) % 2UL) << 1U) + TMR4_OCER_CHBUFEN_POS)))
+#define TMR4_OCER_MxBUFEN(CH, MxBUFEN) ((uint16_t)((uint16_t)(MxBUFEN) << ((((CH) % 2UL) << 1U) + TMR4_OCER_MHBUFEN_POS)))
+#define TMR4_OCER_LMCx(CH, LMCx) ((uint16_t)(LMCx) << ((((CH) % 2UL)) + TMR4_OCER_LMCH_POS))
+#define TMR4_OCER_LMMx(CH, LMMx) ((uint16_t)(LMMx) << ((((CH) % 2UL)) + TMR4_OCER_LMMH_POS))
+#define TMR4_OCER_MCECx(CH, MCECx) ((uint16_t)(MCECx) << ((((CH) % 2UL)) + TMR4_OCER_MCECH_POS))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_RCSR_Bit_Mask TMR4_RCSR Bit Mask
+ * @brief Get the specified TMR4_RCSR register bis value of the specified TMR4 PWM channel
+ * @{
+ */
+#define TMR4_RCSR_RTIDx_MASK(CH) ((RCSR_REG_TYPE)(((RCSR_REG_TYPE)TMR4_RCSR_RTIDU) << (CH)))
+#define TMR4_RCSR_RTIFx_MASK(CH) ((RCSR_REG_TYPE)(((RCSR_REG_TYPE)TMR4_RCSR_RTIFU) << ((CH) << 2U)))
+#define TMR4_RCSR_RTICx_MASK(CH) ((RCSR_REG_TYPE)(((RCSR_REG_TYPE)TMR4_RCSR_RTICU) << ((CH) << 2U)))
+#define TMR4_RCSR_RTEx_MASK(CH) ((RCSR_REG_TYPE)(((RCSR_REG_TYPE)TMR4_RCSR_RTEU) << ((CH) << 2U)))
+#define TMR4_RCSR_RTSx_MASK(CH) ((RCSR_REG_TYPE)(((RCSR_REG_TYPE)TMR4_RCSR_RTSU) << ((CH) << 2U)))
+#define TMR4_RCSR_MASK(CH) (TMR4_RCSR_RTIDx_MASK(CH) | TMR4_RCSR_RTIFx_MASK(CH) | TMR4_RCSR_RTICx_MASK(CH) | \
+ TMR4_RCSR_RTEx_MASK(CH) | TMR4_RCSR_RTSx_MASK(CH))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_PSCR_Bit_Mask TMR4_PSCR Bit Mask
+ * @brief Get the specified TMR4_PSCR register bis value of the specified TMR4 PWM port channel
+ * @{
+ */
+#define TMR4_PSCR_OExy_MASK(PORT) (TMR4_PSCR_OEUH << (PORT))
+#define TMR4_PSCR_OSxy_MASK(PORT) (TMR4_PSCR_OSUH << ((PORT) << 1U))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_PSCR_Bit TMR4_PSCR Bit
+ * @brief Get the specified TMR4_PSCR register bis value of the specified TMR4 PWM port channel
+ * @{
+ */
+#define TMR4_PSCR_OExy(PORT, OExy) ((OExy) << (PORT))
+#define TMR4_PSCR_OSxy(PORT, OSxy) ((OSxy) << (((PORT) << 1U) + TMR4_PSCR_OSUH_POS))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_Register TMR4 Register
+ * @{
+ */
+#define TMR4_REG_ADDR(_REG_) ((uint32_t)(&(_REG_)))
+#define TMR4_REG16(_ADDR_) ((__IO uint16_t *)(_ADDR_))
+#define TMR4_REG32(_ADDR_) ((__IO uint32_t *)(_ADDR_))
+#define TMR4_RCSR_REG(_ADDR_) ((__IO RCSR_REG_TYPE *)(_ADDR_))
+
+/**
+ * @defgroup TMR4_OC_Register_UVW TMR4 OC Register
+ * @brief Get the specified OC register address of the specified TMR4 unit
+ * @{
+ */
+#define _TMR4_OCCR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->OCCRUH) + ((CH) << 2U))
+#define _TMR4_OCMR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->OCMRUH) + ((CH) << 2U))
+#define _TMR4_OCER(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->OCERU) + (((CH) & 0x06UL) << 1U))
+#define _TMR4_OCSR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->OCSRU) + (((CH) & 0x06UL) << 1U))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_PWM_Register_UVW TMR4 PWM Register
+ * @brief Get the specified PWM register address of the specified TMR4 unit
+ * @{
+ */
+#define _TMR4_RCSR(UNIT) TMR4_RCSR_REG(TMR4_REG_ADDR((UNIT)->RCSR))
+#define _TMR4_POCR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->POCRU) + ((CH) << 2U))
+#define _TMR4_PFSR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->PFSRU) + ((CH) << 3U))
+#define _TMR4_PDR(UNIT, CH, IDX) TMR4_REG16(TMR4_REG_ADDR((UNIT)->PDARU) + ((CH) << 3U) + ((IDX) << 1U))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_Event_Register_UVW TMR4 Event Register
+ * @brief Get the specified event register address of the specified TMR4 unit
+ * @{
+ */
+#define _TMR4_SCCR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->SCCRUH) + ((CH) << 2U))
+#define _TMR4_SCSR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->SCSRUH) + ((CH) << 2U))
+#define _TMR4_SCMR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->SCMRUH) + ((CH) << 2U))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_OC_Register TMR4 OC Register
+ * @{
+ */
+#define TMR4_OCCR(UNIT, CH) _TMR4_OCCR(UNIT, CH)
+#define TMR4_OCMR(UNIT, CH) _TMR4_OCMR(UNIT, CH)
+#define TMR4_OCER(UNIT, CH) _TMR4_OCER(UNIT, CH)
+#define TMR4_OCSR(UNIT, CH) _TMR4_OCSR(UNIT, CH)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_PWM_Register TMR4 PWM Register
+ * @{
+ */
+#define TMR4_RCSR(UNIT) _TMR4_RCSR(UNIT)
+#define TMR4_POCR(UNIT, CH) _TMR4_POCR(UNIT, CH)
+#define TMR4_PFSR(UNIT, CH) _TMR4_PFSR(UNIT, CH)
+#define TMR4_PDR(UNIT, CH, IDX) _TMR4_PDR(UNIT, CH, IDX)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_Event_Register TMR4 Event Register
+ * @{
+ */
+#define TMR4_SCCR(UNIT, CH) _TMR4_SCCR(UNIT, CH)
+#define TMR4_SCSR(UNIT, CH) _TMR4_SCSR(UNIT, CH)
+#define TMR4_SCMR(UNIT, CH) _TMR4_SCMR(UNIT, CH)
+/**
+ * @}
+ */
+
+#define TMR4_RMU_TIMEOUT (100U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ * @defgroup TMR4_Global_Functions TMR4 Global Functions
+ * @{
+ */
+
+/**
+ * @defgroup TMR4_Counter_Global_Functions TMR4 Counter Global Functions
+ * @{
+ */
+
+/**
+ * @brief Set the fields of structure stc_tmr4_init_t to default values
+ * @param [out] pstcTmr4Init Pointer to a @ref stc_tmr4_init_t structure
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcCntInit value is NULL.
+ */
+int32_t TMR4_StructInit(stc_tmr4_init_t *pstcTmr4Init)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcTmr4Init) {
+ pstcTmr4Init->u16PeriodValue = 0xFFFFU;
+ pstcTmr4Init->u16CountMode = TMR4_MD_SAWTOOTH;
+ pstcTmr4Init->u16ClockSrc = TMR4_CLK_SRC_INTERNCLK;
+ pstcTmr4Init->u16ClockDiv = TMR4_CLK_DIV1;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize TMR4 counter.
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] pstcTmr4Init Pointer to a @ref stc_tmr4_init_t structure
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcCntInit value is NULL.
+ */
+int32_t TMR4_Init(CM_TMR4_TypeDef *TMR4x, const stc_tmr4_init_t *pstcTmr4Init)
+{
+ uint16_t u16Value;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcTmr4Init) {
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_CLK_SRC(pstcTmr4Init->u16ClockSrc));
+ DDL_ASSERT(IS_TMR4_CLK_DIV(pstcTmr4Init->u16ClockDiv));
+ DDL_ASSERT(IS_TMR4_MD(pstcTmr4Init->u16CountMode));
+
+ /* Set TMR4_CCSR */
+ u16Value = (pstcTmr4Init->u16ClockDiv | pstcTmr4Init->u16ClockSrc | \
+ pstcTmr4Init->u16CountMode | TMR4_CCSR_CLEAR | TMR4_CCSR_STOP);
+ WRITE_REG16(TMR4x->CCSR, u16Value);
+
+ /* Set TMR4_CVPR: default value */
+ WRITE_REG16(TMR4x->CVPR, 0x0000U);
+
+ /* Set TMR4 period */
+ WRITE_REG16(TMR4x->CPSR, pstcTmr4Init->u16PeriodValue);
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief De-Initialize TMR4 counter function
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @retval int32_t:
+ * - LL_OK: Reset success.
+ * - LL_ERR_TIMEOUT: Reset time out.
+ * @note Call LL_PERIPH_WE(LL_PERIPH_PWC_CLK_RMU) unlock RMU_FRSTx register first.
+ */
+int32_t TMR4_DeInit(CM_TMR4_TypeDef *TMR4x)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint8_t u8TimeOut = 0U;
+
+ DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1);
+
+ /* Reset TMR4 */
+ WRITE_REG32(bCM_RMU->FRST2_b.TMR4, 0UL);
+
+ /* Ensure reset procedure is completed */
+ while (READ_REG32(bCM_RMU->FRST2_b.TMR4) != 1UL) {
+ u8TimeOut++;
+ if (u8TimeOut > TMR4_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set TMR4 counter clock source
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u16Src TMR4 counter clock source
+ * This parameter can be one of the macros group @ref TMR4_Count_Clock_Source
+ * @arg TMR4_CLK_SRC_INTERNCLK: Uses the internal clock as counter's count clock
+ * @arg TMR4_CLK_SRC_EXTCLK: Uses an external input clock as counter's count clock
+ * @retval None
+ * @note The clock division function is valid when clock source is internal clock.
+ */
+void TMR4_SetClockSrc(CM_TMR4_TypeDef *TMR4x, uint16_t u16Src)
+{
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_CLK_SRC(u16Src));
+
+ MODIFY_REG16(TMR4x->CCSR, TMR4_CCSR_ECKEN, u16Src);
+}
+
+/**
+ * @brief Set TMR4 counter clock division
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u16Div TMR4 clock division
+ * This parameter can be one of the macros group @ref TMR4_Count_Clock_Division
+ * @arg TMR4_CLK_DIV1: CLK
+ * @arg TMR4_CLK_DIV2: CLK/2
+ * @arg TMR4_CLK_DIV4: CLK/4
+ * @arg TMR4_CLK_DIV8: CLK/8
+ * @arg TMR4_CLK_DIV16: CLK/16
+ * @arg TMR4_CLK_DIV32: CLK/32
+ * @arg TMR4_CLK_DIV64: CLK/64
+ * @arg TMR4_CLK_DIV128: CLK/128
+ * @arg TMR4_CLK_DIV256: CLK/256
+ * @arg TMR4_CLK_DIV512: CLK/512
+ * @arg TMR4_CLK_DIV1024: CLK/1024
+ * @retval None
+ * @note The clock division function is valid when clock source is the internal clock.
+ */
+void TMR4_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint16_t u16Div)
+{
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_CLK_DIV(u16Div));
+
+ MODIFY_REG16(TMR4x->CCSR, TMR4_CCSR_CKDIV, u16Div);
+}
+
+/**
+ * @brief Set TMR4 counter count mode
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u16Mode TMR4 counter count mode
+ * This parameter can be one of the macros group @ref TMR4_Count_Mode
+ * @arg TMR4_MD_SAWTOOTH: TMR4 count mode sawtooth wave
+ * @arg TMR4_MD_TRIANGLE: TMR4 count mode triangular
+ * @retval None
+ */
+void TMR4_SetCountMode(CM_TMR4_TypeDef *TMR4x, uint16_t u16Mode)
+{
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_MD(u16Mode));
+
+ MODIFY_REG16(TMR4x->CCSR, TMR4_CCSR_MODE, u16Mode);
+}
+
+/**
+ * @brief Get the period value of the TMR4 counter.
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @retval The period value of the TMR4 counter
+ */
+uint16_t TMR4_GetPeriodValue(const CM_TMR4_TypeDef *TMR4x)
+{
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+
+ return READ_REG16(TMR4x->CPSR);
+}
+
+/**
+ * @brief Set the period value of the TMR4 counter.
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u16Value The period value of the TMR4 counter
+ * @arg number of 16bit
+ * @retval None
+ */
+void TMR4_SetPeriodValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value)
+{
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+
+ WRITE_REG16(TMR4x->CPSR, u16Value);
+}
+
+/**
+ * @brief Get the count value of the TMR4 counter.
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @retval The count value of the TMR4 counter
+ */
+uint16_t TMR4_GetCountValue(const CM_TMR4_TypeDef *TMR4x)
+{
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+
+ return READ_REG16(TMR4x->CNTR);
+}
+
+/**
+ * @brief Set the count value of the TMR4 counter.
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u16Value The count value of the TMR4 counter
+ * @arg number of 16bit
+ * @retval None
+ */
+void TMR4_SetCountValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value)
+{
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+
+ WRITE_REG16(TMR4x->CNTR, u16Value);
+}
+
+/**
+ * @brief Clear TMR4 counter count value
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @retval None
+ */
+void TMR4_ClearCountValue(CM_TMR4_TypeDef *TMR4x)
+{
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+
+ SET_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_CLEAR);
+}
+
+/**
+ * @brief Start TMR4 counter
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @retval None
+ */
+void TMR4_Start(CM_TMR4_TypeDef *TMR4x)
+{
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+
+ CLR_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_STOP);
+}
+
+/**
+ * @brief Stop TMR4 counter
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @retval None
+ */
+void TMR4_Stop(CM_TMR4_TypeDef *TMR4x)
+{
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+
+ SET_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_STOP);
+}
+
+/**
+ * @brief Clear TMR4 flag
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Flag TMR4 flag
+ * This parameter can be any composed value of the macros group @ref TMR4_Flag
+ * @retval None
+ */
+void TMR4_ClearStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag)
+{
+ uint32_t u32ClearFlag;
+ __IO uint16_t *OCSR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_FLAG(u32Flag));
+
+ /* Counter flag */
+ if ((u32Flag & TMR4_FLAG_CNT_MASK) > 0UL) {
+ CLR_REG16_BIT(TMR4x->CCSR, (u32Flag & TMR4_FLAG_CNT_MASK));
+ }
+
+ /* Output-compare flag */
+ u32ClearFlag = (u32Flag & TMR4_FLAG_OC_MASK);
+ if (u32ClearFlag > 0UL) {
+ /* TMR4_OCSRU */
+ u32ClearFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_UH | TMR4_FLAG_OC_CMP_UL)) >> 10U);
+ if (u32ClearFlag > 0UL) {
+ OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_UH);
+ CLR_REG16_BIT(*OCSR, u32ClearFlag);
+ }
+
+ /* TMR4_OCSRV */
+ u32ClearFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_VH | TMR4_FLAG_OC_CMP_VL)) >> 12U);
+ if (u32ClearFlag > 0UL) {
+ OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_VH);
+ CLR_REG16_BIT(*OCSR, u32ClearFlag);
+ }
+
+ /* TMR4_OCSRW */
+ u32ClearFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_WH | TMR4_FLAG_OC_CMP_WL)) >> 14U);
+ if (u32ClearFlag > 0UL) {
+ OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_WH);
+ CLR_REG16_BIT(*OCSR, u32ClearFlag);
+ }
+ }
+
+ /* PWM reload timer flag */
+ u32ClearFlag = ((u32Flag & TMR4_FLAG_RELOAD_TMR_MASK) << 5U);
+ if (u32ClearFlag > 0UL) {
+ SET_REG_BIT(TMR4x->RCSR, (RCSR_REG_TYPE)u32ClearFlag);
+ }
+
+ /* Event-compare interrupt */
+ u32ClearFlag = ((u32Flag & TMR4_FLAG_SCMP_EVT_MASK) >> 24U);
+ if (u32ClearFlag > 0UL) {
+ CLR_REG16_BIT(TMR4x->SCFR, u32ClearFlag);
+ }
+}
+
+/**
+ * @brief Get TMR4 flag
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Flag TMR4 flag
+ * This parameter can be any composed value of the macros group @ref TMR4_Flag
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t TMR4_GetStatus(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag)
+{
+ uint32_t u32ReadFlag;
+ uint8_t u8FlagSetCount = 0;
+ __IO uint16_t *OCSR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_FLAG(u32Flag));
+
+ /* Counter flag status */
+ if (READ_REG16_BIT(TMR4x->CCSR, (u32Flag & TMR4_FLAG_CNT_MASK)) > 0U) {
+ u8FlagSetCount++;
+ }
+
+ /* Output-compare interrupt */
+ u32ReadFlag = (u32Flag & TMR4_FLAG_OC_MASK);
+ if (u32ReadFlag > 0UL) {
+ /* TMR4_OCSRU */
+ u32ReadFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_UH | TMR4_FLAG_OC_CMP_UL)) >> 10U);
+ OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_UH);
+ if (READ_REG16_BIT(*OCSR, u32ReadFlag) > 0U) {
+ u8FlagSetCount++;
+ }
+
+ /* TMR4_OCSRV */
+ u32ReadFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_VH | TMR4_FLAG_OC_CMP_VL)) >> 12U);
+ OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_VH);
+ if (READ_REG16_BIT(*OCSR, u32ReadFlag) > 0U) {
+ u8FlagSetCount++;
+ }
+
+ /* TMR4_OCSRW */
+ u32ReadFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_WH | TMR4_FLAG_OC_CMP_WL)) >> 14U);
+ OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_WH);
+ if (READ_REG16_BIT(*OCSR, u32ReadFlag) > 0U) {
+ u8FlagSetCount++;
+ }
+ }
+
+ /* PWM reload timer flag status */
+ u32ReadFlag = ((u32Flag & (TMR4_FLAG_RELOAD_TMR_MASK)) << 4U);
+ if (READ_REG_BIT(TMR4x->RCSR, (RCSR_REG_TYPE)u32ReadFlag) > 0U) {
+ u8FlagSetCount++;
+ }
+
+ /* Event-compare interrupt */
+ u32ReadFlag = ((u32Flag & TMR4_FLAG_SCMP_EVT_MASK) >> 24U);
+ if (READ_REG16_BIT(TMR4x->SCFR, u32ReadFlag) > 0U) {
+ u8FlagSetCount++;
+ }
+
+ return (u8FlagSetCount == 0U) ? RESET : SET;
+}
+
+/**
+ * @brief Enable or disable the specified TMR4 interrupt
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32IntType TMR4 interrupt source
+ * This parameter can be any composed value of the macros group @ref TMR4_Interrupt
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR4_IntCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, en_functional_state_t enNewState)
+{
+ uint32_t u32Type;
+ __IO uint16_t *OCSR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_INT(u32IntType));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ /* Counter interrupt */
+ u32Type = (u32IntType & TMR4_INT_CNT_MASK);
+ if (u32Type > 0UL) {
+ (ENABLE == enNewState) ? SET_REG16_BIT(TMR4x->CCSR, u32Type) : CLR_REG16_BIT(TMR4x->CCSR, u32Type);
+ }
+
+ /* Output-compare interrupt */
+ u32Type = (u32IntType & TMR4_INT_OC_MASK);
+ if (u32Type > 0UL) {
+ /* TMR4_OCSRU */
+ u32Type = ((u32IntType & (TMR4_INT_OC_CMP_UH | TMR4_INT_OC_CMP_UL)) >> 12U);
+ if (u32Type != 0UL) {
+ OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_UH);
+ (ENABLE == enNewState) ? SET_REG16_BIT(*OCSR, u32Type) : CLR_REG16_BIT(*OCSR, u32Type);
+ }
+
+ /* TMR4_OCSRV */
+ u32Type = ((u32IntType & (TMR4_INT_OC_CMP_VH | TMR4_INT_OC_CMP_VL)) >> 14U);
+ if (u32Type != 0UL) {
+ OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_VH);
+ (ENABLE == enNewState) ? SET_REG16_BIT(*OCSR, u32Type) : CLR_REG16_BIT(*OCSR, u32Type);
+ }
+
+ /* TMR4_OCSRW */
+ u32Type = ((u32IntType & (TMR4_INT_OC_CMP_WH | TMR4_INT_OC_CMP_WL)) >> 16U);
+ if (u32Type != 0UL) {
+ OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_WH);
+ (ENABLE == enNewState) ? SET_REG16_BIT(*OCSR, u32Type) : CLR_REG16_BIT(*OCSR, u32Type);
+ }
+ }
+
+ /* PWM reload timer interrupt */
+ u32Type = (u32IntType & TMR4_INT_RELOAD_TMR_MASK);
+ if (u32Type > 0UL) {
+ (ENABLE == enNewState) ? CLR_REG_BIT(TMR4x->RCSR, (RCSR_REG_TYPE)u32Type) : SET_REG_BIT(TMR4x->RCSR, (RCSR_REG_TYPE)u32Type);
+ }
+
+ /* Event-compare interrupt */
+ u32Type = ((u32IntType & TMR4_INT_SCMP_EVT_MASK) >> 24U);
+ if (u32Type > 0UL) {
+ (ENABLE == enNewState) ? SET_REG16_BIT(TMR4x->SCIR, u32Type) : CLR_REG16_BIT(TMR4x->SCIR, u32Type);
+ }
+}
+
+/**
+ * @brief Enable or disable the TMR4 counter period buffer function.
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR4_PeriodBufCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_BUFEN);
+ } else {
+ CLR_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_BUFEN);
+ }
+}
+
+/**
+ * @brief Get TMR4 count interrupt mask times
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32IntType TMR4 interrupt source
+ * This parameter can be one of the following values:
+ * @arg TMR4_INT_CNT_PEAK: Count peak interrupt
+ * @arg TMR4_INT_CNT_VALLEY : Count valley interrupt
+ * @retval Returned value can be one of the macros group @ref TMR4_Count_Interrupt_Mask_Time
+ * - TMR4_INT_CNT_MASK0: Counter interrupt flag is always set(not masked) for counter count every time at "0x0000" or peak
+ * - TMR4_INT_CNT_MASK1: Counter interrupt flag is set once when counter counts 2 times at "0x0000" or peak (skipping 1 count)
+ * - TMR4_INT_CNT_MASK2: Counter interrupt flag is set once when counter counts 3 times at "0x0000" or peak (skipping 2 count)
+ * - TMR4_INT_CNT_MASK3: Counter interrupt flag is set once when counter counts 4 times at "0x0000" or peak (skipping 3 count)
+ * - TMR4_INT_CNT_MASK4: Counter interrupt flag is set once when counter counts 5 times at "0x0000" or peak (skipping 4 count)
+ * - TMR4_INT_CNT_MASK5: Counter interrupt flag is set once when counter counts 6 times at "0x0000" or peak (skipping 5 count)
+ * - TMR4_INT_CNT_MASK6: Counter interrupt flag is set once when counter counts 7 times at "0x0000" or peak (skipping 6 count)
+ * - TMR4_INT_CNT_MASK7: Counter interrupt flag is set once when counter counts 8 times at "0x0000" or peak (skipping 7 count)
+ * - TMR4_INT_CNT_MASK8: Counter interrupt flag is set once when counter counts 9 times at "0x0000" or peak (skipping 8 count)
+ * - TMR4_INT_CNT_MASK9: Counter interrupt flag is set once when counter counts 10 times at "0x0000" or peak (skipping 9 count)
+ * - TMR4_INT_CNT_MASK10: Counter interrupt flag is set once when counter counts 11 times at "0x0000" or peak (skipping 10 count)
+ * - TMR4_INT_CNT_MASK11: Counter interrupt flag is set once when counter counts 12 times at "0x0000" or peak (skipping 11 count)
+ * - TMR4_INT_CNT_MASK12: Counter interrupt flag is set once when counter counts 13 times at "0x0000" or peak (skipping 12 count)
+ * - TMR4_INT_CNT_MASK13: Counter interrupt flag is set once when counter counts 14 times at "0x0000" or peak (skipping 13 count)
+ * - TMR4_INT_CNT_MASK14: Counter interrupt flag is set once when counter counts 15 times at "0x0000" or peak (skipping 14 count)
+ * - TMR4_INT_CNT_MASK15: Counter interrupt flag is set once when counter counts 16 times at "0x0000" or peak (skipping 15 count)
+ */
+uint16_t TMR4_GetCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType)
+{
+ uint16_t u16MaskTimes;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_INT_CNT(u32IntType));
+
+ if (TMR4_INT_CNT_VALLEY == u32IntType) {
+ u16MaskTimes = (READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_ZIM) >> TMR4_CVPR_ZIM_POS);
+ } else {
+ u16MaskTimes = (READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_PIM) >> TMR4_CVPR_PIM_POS);
+ }
+
+ return u16MaskTimes;
+}
+
+/**
+ * @brief Set TMR4 counter interrupt mask times
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32IntType TMR4 interrupt source
+ * This parameter can be one of the following values:
+ * @arg TMR4_INT_CNT_PEAK: Count peak interrupt
+ * @arg TMR4_INT_CNT_VALLEY : Count valley interrupt
+ * @param [in] u16MaskTime TMR4 counter interrupt mask times
+ * This parameter can be one of the macros group @ref TMR4_Count_Interrupt_Mask_Time
+ * @arg TMR4_INT_CNT_MASK0: Counter interrupt flag is always set(not masked) for counter count every time at "0x0000" or peak
+ * @arg TMR4_INT_CNT_MASK1: Counter interrupt flag is set once when counter counts 2 times at "0x0000" or peak (skipping 1 count)
+ * @arg TMR4_INT_CNT_MASK2: Counter interrupt flag is set once when counter counts 3 times at "0x0000" or peak (skipping 2 count)
+ * @arg TMR4_INT_CNT_MASK3: Counter interrupt flag is set once when counter counts 4 times at "0x0000" or peak (skipping 3 count)
+ * @arg TMR4_INT_CNT_MASK4: Counter interrupt flag is set once when counter counts 5 times at "0x0000" or peak (skipping 4 count)
+ * @arg TMR4_INT_CNT_MASK5: Counter interrupt flag is set once when counter counts 6 times at "0x0000" or peak (skipping 5 count)
+ * @arg TMR4_INT_CNT_MASK6: Counter interrupt flag is set once when counter counts 7 times at "0x0000" or peak (skipping 6 count)
+ * @arg TMR4_INT_CNT_MASK7: Counter interrupt flag is set once when counter counts 8 times at "0x0000" or peak (skipping 7 count)
+ * @arg TMR4_INT_CNT_MASK8: Counter interrupt flag is set once when counter counts 9 times at "0x0000" or peak (skipping 8 count)
+ * @arg TMR4_INT_CNT_MASK9: Counter interrupt flag is set once when counter counts 10 times at "0x0000" or peak (skipping 9 count)
+ * @arg TMR4_INT_CNT_MASK10: Counter interrupt flag is set once when counter counts 11 times at "0x0000" or peak (skipping 10 count)
+ * @arg TMR4_INT_CNT_MASK11: Counter interrupt flag is set once when counter counts 12 times at "0x0000" or peak (skipping 11 count)
+ * @arg TMR4_INT_CNT_MASK12: Counter interrupt flag is set once when counter counts 13 times at "0x0000" or peak (skipping 12 count)
+ * @arg TMR4_INT_CNT_MASK13: Counter interrupt flag is set once when counter counts 14 times at "0x0000" or peak (skipping 13 count)
+ * @arg TMR4_INT_CNT_MASK14: Counter interrupt flag is set once when counter counts 15 times at "0x0000" or peak (skipping 14 count)
+ * @arg TMR4_INT_CNT_MASK15: Counter interrupt flag is set once when counter counts 16 times at "0x0000" or peak (skipping 15 count)
+ * @retval None
+ */
+void TMR4_SetCountIntMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, uint16_t u16MaskTime)
+{
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_INT_CNT(u32IntType));
+ DDL_ASSERT(IS_TMR4_INT_CNT_MASKTIME(u16MaskTime));
+
+ if (TMR4_INT_CNT_VALLEY == (u32IntType & TMR4_INT_CNT_VALLEY)) {
+ MODIFY_REG16(TMR4x->CVPR, TMR4_CVPR_ZIM, (u16MaskTime << TMR4_CVPR_ZIM_POS));
+ }
+
+ if (TMR4_INT_CNT_PEAK == (u32IntType & TMR4_INT_CNT_PEAK)) {
+ MODIFY_REG16(TMR4x->CVPR, TMR4_CVPR_PIM, (u16MaskTime << TMR4_CVPR_PIM_POS));
+ }
+}
+
+/**
+ * @brief Get TMR4 counter current interrupt mask times
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32IntType TMR4 interrupt source
+ * This parameter can be one of the macros group @ref TMR4_Interrupt
+ * @arg TMR4_INT_CNT_PEAK: Count peak interrupt
+ * @arg TMR4_INT_CNT_VALLEY : Count valley interrupt
+ * @retval Returned value can be one of the macros group @ref TMR4_Count_Interrupt_Mask_Time
+ * - TMR4_INT_CNT_MASK0: Counter interrupt flag is always set(not masked) for every counter count at "0x0000" or peak
+ * - TMR4_INT_CNT_MASK1: Counter interrupt flag is set once for 2 every counter counts at "0x0000" or peak (skipping 1 count)
+ * - TMR4_INT_CNT_MASK2: Counter interrupt flag is set once for 3 every counter counts at "0x0000" or peak (skipping 2 count)
+ * - TMR4_INT_CNT_MASK3: Counter interrupt flag is set once for 4 every counter counts at "0x0000" or peak (skipping 3 count)
+ * - TMR4_INT_CNT_MASK4: Counter interrupt flag is set once for 5 every counter counts at "0x0000" or peak (skipping 4 count)
+ * - TMR4_INT_CNT_MASK5: Counter interrupt flag is set once for 6 every counter counts at "0x0000" or peak (skipping 5 count)
+ * - TMR4_INT_CNT_MASK6: Counter interrupt flag is set once for 7 every counter counts at "0x0000" or peak (skipping 6 count)
+ * - TMR4_INT_CNT_MASK7: Counter interrupt flag is set once for 8 every counter counts at "0x0000" or peak (skipping 7 count)
+ * - TMR4_INT_CNT_MASK8: Counter interrupt flag is set once for 9 every counter counts at "0x0000" or peak (skipping 8 count)
+ * - TMR4_INT_CNT_MASK9: Counter interrupt flag is set once for 10 every counter counts at "0x0000" or peak (skipping 9 count)
+ * - TMR4_INT_CNT_MASK10: Counter interrupt flag is set once for 11 every counter counts at "0x0000" or peak (skipping 10 count)
+ * - TMR4_INT_CNT_MASK11: Counter interrupt flag is set once for 12 every counter counts at "0x0000" or peak (skipping 11 count)
+ * - TMR4_INT_CNT_MASK12: Counter interrupt flag is set once for 13 every counter counts at "0x0000" or peak (skipping 12 count)
+ * - TMR4_INT_CNT_MASK13: Counter interrupt flag is set once for 14 every counter counts at "0x0000" or peak (skipping 13 count)
+ * - TMR4_INT_CNT_MASK14: Counter interrupt flag is set once for 15 every counter counts at "0x0000" or peak (skipping 14 count)
+ * - TMR4_INT_CNT_MASK15: Counter interrupt flag is set once for 16 every counter counts at "0x0000" or peak (skipping 15 count)
+ */
+uint16_t TMR4_GetCurrentCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType)
+{
+ uint16_t u16MaskTimes;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_INT_CNT(u32IntType));
+
+ if (TMR4_INT_CNT_VALLEY == u32IntType) {
+ u16MaskTimes = (READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_ZIC) >> TMR4_CVPR_ZIC_POS);
+ } else {
+ u16MaskTimes = (READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_PIC) >> TMR4_CVPR_PIC_POS);
+ }
+
+ return u16MaskTimes;
+}
+
+/**
+ * @brief Enable or disable port output TMR4 counter direction signal
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR4_PortOutputCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG16_BIT(TMR4x->SCER, TMR4_SCER_PCTS);
+ } else {
+ CLR_REG16_BIT(TMR4x->SCER, TMR4_SCER_PCTS);
+ }
+}
+
+/**
+ * @brief Enable or disable hardware start of the TMR4 count.
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR4_HWStartCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_HST);
+ } else {
+ CLR_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_HST);
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_Output_Compare_Global_Functions TMR4 Output-Compare Global Functions
+ * @{
+ */
+
+/**
+ * @brief Set the fields of structure stc_tmr4_oc_init_t to default values
+ * @param [out] pstcTmr4OcInit Pointer to a @ref stc_tmr4_oc_init_t structure
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcTmr4OcInit value is NULL.
+ */
+int32_t TMR4_OC_StructInit(stc_tmr4_oc_init_t *pstcTmr4OcInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcTmr4OcInit) {
+ pstcTmr4OcInit->u16CompareValue = 0U;
+ pstcTmr4OcInit->u16OcInvalidPolarity = TMR4_OC_INVD_LOW;
+ pstcTmr4OcInit->u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED;
+ pstcTmr4OcInit->u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED;
+ pstcTmr4OcInit->u16BufLinkTransObject = TMR4_OC_BUF_NONE;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize TMR4 OC
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 OC channel
+ * This parameter can be one of the macros group @ref TMR4_OC_Channel
+ * @param [in] pstcTmr4OcInit Pointer to a @ref stc_tmr4_oc_init_t structure
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcTmr4OcInit value is NULL.
+ */
+int32_t TMR4_OC_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_oc_init_t *pstcTmr4OcInit)
+{
+ uint16_t u16Value;
+ __IO uint16_t *OCER;
+ __IO uint16_t *OCSR;
+ __IO uint16_t *OCCR;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcTmr4OcInit) {
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_OC_CH(u32Ch));
+ DDL_ASSERT(IS_TMR4_OC_INVD_POLARITY(pstcTmr4OcInit->u16OcInvalidPolarity));
+ DDL_ASSERT(IS_TMR4_OC_BUF_COND(pstcTmr4OcInit->u16CompareModeBufCond));
+ DDL_ASSERT(IS_TMR4_OC_BUF_COND(pstcTmr4OcInit->u16CompareValueBufCond));
+ DDL_ASSERT(IS_TMR4_OC_BUF_OBJECT(pstcTmr4OcInit->u16BufLinkTransObject));
+
+ /* Get pointer of current channel OC register address */
+ OCSR = TMR4_OCSR(TMR4x, u32Ch);
+ OCER = TMR4_OCER(TMR4x, u32Ch);
+ OCCR = TMR4_OCCR(TMR4x, u32Ch);
+
+ /* Set output polarity when OC is disabled. */
+ MODIFY_REG16(*OCSR, TMR4_OCSR_MASK(u32Ch), TMR4_OCSR_OCPx(u32Ch, pstcTmr4OcInit->u16OcInvalidPolarity));
+
+ /* Set OCMR&&OCCR buffer function */
+ u16Value = (TMR4_OCER_MxBUFEN(u32Ch, pstcTmr4OcInit->u16CompareModeBufCond) | \
+ TMR4_OCER_CxBUFEN(u32Ch, pstcTmr4OcInit->u16CompareValueBufCond));
+ if (TMR4_OC_BUF_CMP_VALUE == (pstcTmr4OcInit->u16BufLinkTransObject & TMR4_OC_BUF_CMP_VALUE)) {
+ u16Value |= TMR4_OCER_LMCx_MASK(u32Ch);
+ }
+
+ if (TMR4_OC_BUF_CMP_MD == (pstcTmr4OcInit->u16BufLinkTransObject & TMR4_OC_BUF_CMP_MD)) {
+ u16Value |= TMR4_OCER_LMMx_MASK(u32Ch);
+ }
+
+ MODIFY_REG16(*OCER, TMR4_OCER_MASK(u32Ch), u16Value);
+
+ /* Set OC compare value */
+ WRITE_REG16(*OCCR, pstcTmr4OcInit->u16CompareValue);
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief De-initialize TMR4 OC
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 OC channel
+ * This parameter can be one of the macros group @ref TMR4_OC_Channel
+ * @retval None
+ */
+void TMR4_OC_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch)
+{
+ __IO uint16_t *OCER;
+ __IO uint16_t *OCSR;
+ __IO uint16_t *OCCR;
+ __IO uint16_t *OCMRxH;
+ __IO uint32_t *OCMRxL;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_OC_CH(u32Ch));
+
+ /* Get pointer of current channel OC register address */
+ OCSR = TMR4_OCSR(TMR4x, u32Ch);
+ OCER = TMR4_OCER(TMR4x, u32Ch);
+ OCCR = TMR4_OCCR(TMR4x, u32Ch);
+
+ /* Clear bits: port output valid && OP level && interrupt */
+ CLR_REG16_BIT(*OCSR, TMR4_OCSR_MASK(u32Ch));
+
+ /* Clear bits: OCMR&&OCCR buffer */
+ CLR_REG16_BIT(*OCER, TMR4_OCER_MASK(u32Ch));
+
+ /* Set OC compare match value */
+ WRITE_REG16(*OCCR, 0x0000U);
+
+ /* Set OCMR value */
+ if ((u32Ch & 0x01UL) == 0UL) {
+ OCMRxH = TMR4_OCMR(TMR4x, u32Ch);
+ WRITE_REG16(*OCMRxH, 0x0000U);
+ } else {
+ OCMRxL = (__IO uint32_t *)((uint32_t)TMR4_OCMR(TMR4x, u32Ch));
+ WRITE_REG32(*OCMRxL, 0x00000000UL);
+ }
+}
+
+/**
+ * @brief Get TMR4 OC OCCR compare value
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 OC channel
+ * This parameter can be one of the macros group @ref TMR4_OC_Channel
+ * @retval The compare value of the TMR4 OC OCCR register
+ */
+uint16_t TMR4_OC_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch)
+{
+ __I uint16_t *OCCR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_OC_CH(u32Ch));
+
+ /* Get pointer of current channel OC register address */
+ OCCR = TMR4_OCCR(TMR4x, u32Ch);
+
+ return READ_REG16(*OCCR);
+}
+
+/**
+ * @brief Set TMR4 OC compare value
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 OC channel
+ * This parameter can be one of the macros group @ref TMR4_OC_Channel
+ * @param [in] u16Value The compare value of the TMR4 OC OCCR register
+ * @arg number of 16bit
+ * @retval None
+ */
+void TMR4_OC_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value)
+{
+ __IO uint16_t *OCCR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_OC_CH(u32Ch));
+
+ /* Get pointer of current channel OC register address */
+ OCCR = TMR4_OCCR(TMR4x, u32Ch);
+
+ WRITE_REG16(*OCCR, u16Value);
+}
+
+/**
+ * @brief Enable or disable the TMR4 OC of the specified channel.
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 OC channel
+ * This parameter can be one of the macros group @ref TMR4_OC_Channel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR4_OC_Cmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState)
+{
+ __IO uint16_t *OCSR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_OC_CH(u32Ch));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ /* Get pointer of current channel OC register address */
+ OCSR = TMR4_OCSR(TMR4x, u32Ch);
+
+ /* Set OCSR port output compare */
+ MODIFY_REG16(*OCSR, TMR4_OCSR_OCEx_MASK(u32Ch), TMR4_OCSR_OCEx(u32Ch, enNewState));
+}
+
+/**
+ * @brief Extend the matching conditions of TMR4 OC channel
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 OC channel
+ * This parameter can be one of the macros group @ref TMR4_OC_Channel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR4_OC_ExtendControlCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState)
+{
+ __IO uint16_t *OCER;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_OC_CH(u32Ch));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ /* Get pointer of current channel OC register address */
+ OCER = TMR4_OCER(TMR4x, u32Ch);
+
+ /* Set OCER register: Extend match function */
+ MODIFY_REG16(*OCER, TMR4_OCER_MCECx_MASK(u32Ch), TMR4_OCER_MCECx(u32Ch, enNewState));
+}
+
+/**
+ * @brief Set TMR4 OC OCCR/OCMR buffer interval response function
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 OC channel
+ * This parameter can be one of the macros group @ref TMR4_OC_Channel
+ * @param [in] u16Object TMR4 OC register buffer: OCCR/OCMR
+ * This parameter can be any composed value of the macros group @ref TMR4_OC_Buffer_Object
+ * @arg TMR4_OC_BUF_CMP_VALUE: The register OCCR buffer function
+ * @arg TMR4_OC_BUF_CMP_MD: The register OCMR buffer function
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @arg ENABLE: Enable the OCMR/OCMR register buffer function.
+ * @arg DISABLE: Disable the OCMR/OCMR register buffer function.
+ * @retval None
+ */
+void TMR4_OC_BufIntervalResponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch,
+ uint16_t u16Object, en_functional_state_t enNewState)
+{
+ __IO uint16_t *OCER;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_OC_CH(u32Ch));
+ DDL_ASSERT(IS_TMR4_OC_BUF_OBJECT(u16Object));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ /* Get pointer of current channel OC register address */
+ OCER = TMR4_OCER(TMR4x, u32Ch);
+
+ if (TMR4_OC_BUF_CMP_VALUE == (u16Object & TMR4_OC_BUF_CMP_VALUE)) {
+ /* Set OCER register: OCCR link transfer function */
+ MODIFY_REG16(*OCER, TMR4_OCER_LMCx_MASK(u32Ch), TMR4_OCER_LMCx(u32Ch, enNewState));
+ }
+
+ if (TMR4_OC_BUF_CMP_MD == (u16Object & TMR4_OC_BUF_CMP_MD)) {
+ /* Set OCER register: OCMR link transfer function */
+ MODIFY_REG16(*OCER, TMR4_OCER_LMMx_MASK(u32Ch), TMR4_OCER_LMMx(u32Ch, enNewState));
+ }
+}
+
+/**
+ * @brief Get TMR4 OC output current polarity
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 OC channel
+ * This parameter can be one of the macros group @ref TMR4_OC_Channel
+ * @retval Returned value can be one of the macros group @ref TMR4_OC_Output_Polarity
+ * - TMR4_OC_PORT_LOW: TMR4 OC output low level
+ * - TMR4_OC_PORT_HIGH: TMR4 OC output high level
+ */
+uint16_t TMR4_OC_GetPolarity(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch)
+{
+ __I uint16_t *OCSR;
+ uint16_t u16Polarity;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_OC_CH(u32Ch));
+
+ /* Get pointer of current channel OC register address */
+ OCSR = TMR4_OCSR(TMR4x, u32Ch);
+
+ /* Get OCSR register: OC output polarity */
+ u16Polarity = READ_REG16_BIT(*OCSR, TMR4_OCSR_OCPx_MASK(u32Ch));
+ return (u16Polarity >> (u32Ch % 2UL));
+}
+
+/**
+ * @brief Set TMR4 OC invalid output polarity
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 OC channel
+ * This parameter can be one of the macros group @ref TMR4_OC_Channel
+ * @param [in] u16Polarity TMR4 OC invalid output polarity.
+ * This parameter can be one of the macros group @ref TMR4_OC_Invalid_Output_Polarity
+ * @arg TMR4_OC_INVD_LOW: TMR4 OC output low level when OC is invalid
+ * @arg TMR4_OC_INVD_HIGH: TMR4 OC output high level when OC is invalid
+ * @retval None
+ */
+void TMR4_OC_SetOcInvalidPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity)
+{
+ __IO uint16_t *OCSR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_OC_CH(u32Ch));
+ DDL_ASSERT(IS_TMR4_OC_INVD_POLARITY(u16Polarity));
+
+ /* Get pointer of current channel OC register address */
+ OCSR = TMR4_OCSR(TMR4x, u32Ch);
+
+ /* Set OCSR register: OC invalid output polarity */
+ MODIFY_REG16(*OCSR, TMR4_OCSR_OCPx_MASK(u32Ch), TMR4_OCSR_OCPx(u32Ch, u16Polarity));
+}
+
+/**
+ * @brief Set TMR4 OC OCCR/OCMR buffer transfer condition
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 OC channel
+ * This parameter can be one of the macros group @ref TMR4_OC_Channel
+ * @param [in] u16Object TMR4 OC register buffer type: OCCR/OCMR
+ * This parameter can be any composed value of the macros group @ref TMR4_OC_Buffer_Object
+ * @arg TMR4_OC_BUF_CMP_VALUE: The register OCCR buffer function
+ * @arg TMR4_OC_BUF_CMP_MD: The register OCMR buffer function
+ * @param [in] u16BufCond TMR4 OC OCCR/OCMR buffer transfer condition
+ * This parameter can be one of the macros group @ref TMR4_OC_Buffer_Transfer_Condition
+ * @arg TMR4_OC_BUF_COND_IMMED: Buffer transfer is made when writing to the OCCR/OCMR register.
+ * @arg TMR4_OC_BUF_COND_VALLEY: Buffer transfer is made when counter count valley.
+ * @arg TMR4_OC_BUF_COND_PEAK: Buffer transfer is made when counter count peak.
+ * @arg TMR4_OC_BUF_COND_PEAK_VALLEY: Buffer transfer is made when counter count peak or valley.
+ * @retval None
+ */
+void TMR4_OC_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object, uint16_t u16BufCond)
+{
+ __IO uint16_t *OCER;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_OC_CH(u32Ch));
+ DDL_ASSERT(IS_TMR4_OC_BUF_OBJECT(u16Object));
+ DDL_ASSERT(IS_TMR4_OC_BUF_COND(u16BufCond));
+
+ /* Get pointer of current channel OC register address */
+ OCER = TMR4_OCER(TMR4x, u32Ch);
+
+ if (TMR4_OC_BUF_CMP_VALUE == (u16Object & TMR4_OC_BUF_CMP_VALUE)) {
+ /* Set OCER register: OCCR buffer mode */
+ MODIFY_REG16(*OCER, TMR4_OCER_CxBUFEN_MASK(u32Ch), TMR4_OCER_CxBUFEN(u32Ch, u16BufCond));
+ }
+
+ if (TMR4_OC_BUF_CMP_MD == (u16Object & TMR4_OC_BUF_CMP_MD)) {
+ /* Set OCER register: OCMR buffer mode */
+ MODIFY_REG16(*OCER, TMR4_OCER_MxBUFEN_MASK(u32Ch), TMR4_OCER_MxBUFEN(u32Ch, u16BufCond));
+ }
+}
+
+/**
+ * @brief Get the TMR4 OC high channel mode
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 OC channel.
+ * This parameter can be one of the macros group @ref TMR4_OC_Channel
+ * @retval The TMR4 OC high channel mode
+ * @note The function only can get high channel mode:TMR4_OC_CH_xH(x = U/V/W)
+ */
+uint16_t TMR4_OC_GetHighChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch)
+{
+ __I uint16_t *OCMRxH;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_OC_HIGH_CH(u32Ch));
+
+ /* Get pointer of current channel OC register address */
+ OCMRxH = TMR4_OCMR(TMR4x, u32Ch);
+ return READ_REG16(*OCMRxH);
+}
+
+/**
+ * @brief Set the TMR4 OC high channel mode
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 OC channel.
+ * This parameter can be one of the macros group @ref TMR4_OC_Channel
+ * @param [in] unTmr4Ocmrh The TMR4 OC high channel mode @ref un_tmr4_oc_ocmrh_t
+ * @retval None
+ * @note The function only can set high channel mode:TMR4_OC_CH_xH(x = U/V/W)
+ */
+void TMR4_OC_SetHighChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrh_t unTmr4Ocmrh)
+{
+ __IO uint16_t *OCMRxH;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_OC_HIGH_CH(u32Ch));
+
+ /* Get pointer of current channel OC register address */
+ OCMRxH = TMR4_OCMR(TMR4x, u32Ch);
+ WRITE_REG16(*OCMRxH, unTmr4Ocmrh.OCMRx);
+}
+
+/**
+ * @brief Get the TMR4 OC low channel mode
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 OC channel.
+ * This parameter can be one of the macros group @ref TMR4_OC_Channel
+ * @retval The TMR4 OC low channel mode
+ * @note The function only can get low channel mode:TMR4_OC_CH_xL(x = U/V/W)
+ */
+uint32_t TMR4_OC_GetLowChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch)
+{
+ __I uint32_t *OCMRxL;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_OC_LOW_CH(u32Ch));
+
+ /* Get pointer of current channel OC register address */
+ OCMRxL = (__IO uint32_t *)((uint32_t)TMR4_OCMR(TMR4x, u32Ch));
+ return READ_REG32(*OCMRxL);
+}
+
+/**
+ * @brief Set the TMR4 OC low channel mode
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 OC channel.
+ * This parameter can be one of the macros group @ref TMR4_OC_Channel
+ * @param [in] unTmr4Ocmrl The TMR4 OC low channel mode @ref un_tmr4_oc_ocmrl_t
+ * @retval None
+ * @note The function only can set low channel mode:TMR4_OC_CH_xL(x = U/V/W)
+ */
+void TMR4_OC_SetLowChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrl_t unTmr4Ocmrl)
+{
+ __IO uint32_t *OCMRxL;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_OC_LOW_CH(u32Ch));
+
+ /* Get pointer of current channel OC register address */
+ OCMRxL = (__IO uint32_t *)((uint32_t)TMR4_OCMR(TMR4x, u32Ch));
+ WRITE_REG32(*OCMRxL, unTmr4Ocmrl.OCMRx);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_PWM_Global_Functions TMR4 PWM Global Functions
+ * @{
+ */
+
+/**
+ * @brief Set the fields of structure stc_tmr4_pwm_init_t to default values
+ * @param [out] pstcTmr4PwmInit Pointer to a @ref stc_tmr4_pwm_init_t structure
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcTmr4PwmInit value is NULL.
+ */
+int32_t TMR4_PWM_StructInit(stc_tmr4_pwm_init_t *pstcTmr4PwmInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcTmr4PwmInit) {
+ pstcTmr4PwmInit->u16Mode = TMR4_PWM_MD_THROUGH;
+ pstcTmr4PwmInit->u16ClockDiv = TMR4_PWM_CLK_DIV1;
+ pstcTmr4PwmInit->u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize TMR4 PWM
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 PWM channel
+ * This parameter can be one of the macros group @ref TMR4_PWM_Channel
+ * @param [in] pstcTmr4PwmInit Pointer to a @ref stc_tmr4_pwm_init_t structure
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcTmr4PwmInit value is NULL.
+ */
+int32_t TMR4_PWM_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_pwm_init_t *pstcTmr4PwmInit)
+{
+ uint16_t POCRValue;
+ __IO uint16_t *POCR;
+ RCSR_REG_TYPE RCSRValue;
+ __IO RCSR_REG_TYPE *RCSR;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcTmr4PwmInit) {
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch));
+ DDL_ASSERT(IS_TMR4_PWM_MD(pstcTmr4PwmInit->u16Mode));
+ DDL_ASSERT(IS_TMR4_PWM_CLK_DIV(pstcTmr4PwmInit->u16ClockDiv));
+ DDL_ASSERT(IS_TMR4_PWM_POLARITY(pstcTmr4PwmInit->u16Polarity));
+
+ /* Get pointer of current channel PWM register address */
+ POCR = TMR4_POCR(TMR4x, u32Ch);
+ RCSR = TMR4_RCSR(TMR4x);
+
+ /* Set POCR register */
+ POCRValue = (pstcTmr4PwmInit->u16Mode | pstcTmr4PwmInit->u16ClockDiv | pstcTmr4PwmInit->u16Polarity);
+ WRITE_REG16(*POCR, POCRValue);
+
+ /* Set RCSR register */
+ RCSRValue = (TMR4_RCSR_RTSx_MASK(u32Ch) | TMR4_RCSR_RTIDx_MASK(u32Ch) | TMR4_RCSR_RTICx_MASK(u32Ch));
+ MODIFY_REG(*RCSR, TMR4_RCSR_MASK(u32Ch), RCSRValue);
+
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief De-initialize TMR4 PWM
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 PWM channel
+ * This parameter can be one of the macros group @ref TMR4_PWM_Channel
+ * @retval None
+ */
+void TMR4_PWM_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch)
+{
+ __IO uint16_t *POCR;
+ __IO RCSR_REG_TYPE *RCSR;
+ RCSR_REG_TYPE RCSRValue;
+ __IO uint16_t *PDAR;
+ __IO uint16_t *PDBR;
+ __IO uint16_t *PFSR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch));
+
+ /* Get pointer of current channel PWM register address */
+ POCR = TMR4_POCR(TMR4x, u32Ch);
+ RCSR = TMR4_RCSR(TMR4x);
+ PDAR = TMR4_PDR(TMR4x, u32Ch, TMR4_PWM_PDAR_IDX);
+ PDBR = TMR4_PDR(TMR4x, u32Ch, TMR4_PWM_PDBR_IDX);
+ PFSR = TMR4_PFSR(TMR4x, u32Ch);
+
+ /* Set POCR register to reset value */
+ WRITE_REG16(*POCR, TMR4_POCR_RST_VALUE);
+
+ /* Set RCSR register */
+ RCSRValue = (TMR4_RCSR_RTSx_MASK(u32Ch) | TMR4_RCSR_RTICx_MASK(u32Ch));
+ MODIFY_REG(*RCSR, TMR4_RCSR_MASK(u32Ch), RCSRValue);
+
+ /* Set PDAR/PDBR register to reset value */
+ WRITE_REG16(*PDAR, 0U);
+ WRITE_REG16(*PDBR, 0U);
+
+ /* Set POCR register to reset value */
+ WRITE_REG16(*PFSR, 0U);
+
+ /* Set abnormal pin status to reset value */
+ TMR4_PWM_SetAbnormalPinStatus(TMR4x, ((u32Ch << 1) + 0UL), TMR4_PWM_ABNORMAL_PIN_HIZ);
+ TMR4_PWM_SetAbnormalPinStatus(TMR4x, ((u32Ch << 1) + 1UL), TMR4_PWM_ABNORMAL_PIN_HIZ);
+
+ /* Set port output mode to reset value */
+ TMR4_PWM_SetPortOutputMode(TMR4x, ((u32Ch << 1) + 0UL), TMR4_PWM_PIN_OUTPUT_OS);
+ TMR4_PWM_SetPortOutputMode(TMR4x, ((u32Ch << 1) + 1UL), TMR4_PWM_PIN_OUTPUT_OS);
+}
+
+/**
+ * @brief Set TMR4 PWM clock division
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 PWM channel
+ * This parameter can be one of the macros group @ref TMR4_PWM_Channel
+ * @param [in] u16Div TMR4 PWM internal clock division
+ * This parameter can be one of the macros group @ref TMR4_PWM_Clock_Division
+ * @arg TMR4_PWM_CLK_DIV1: CLK
+ * @arg TMR4_PWM_CLK_DIV2: CLK/2
+ * @arg TMR4_PWM_CLK_DIV4: CLK/4
+ * @arg TMR4_PWM_CLK_DIV8: CLK/8
+ * @arg TMR4_PWM_CLK_DIV16: CLK/16
+ * @arg TMR4_PWM_CLK_DIV32: CLK/32
+ * @arg TMR4_PWM_CLK_DIV64: CLK/64
+ * @arg TMR4_PWM_CLK_DIV128: CLK/128
+ * @retval None
+ */
+void TMR4_PWM_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Div)
+{
+ __IO uint16_t *POCR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch));
+ DDL_ASSERT(IS_TMR4_PWM_CLK_DIV(u16Div));
+
+ /* Get pointer of current channel PWM register address */
+ POCR = TMR4_POCR(TMR4x, u32Ch);
+
+ MODIFY_REG16(*POCR, TMR4_POCR_DIVCK, u16Div);
+}
+
+/**
+ * @brief Set TMR4 PWM output polarity.
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 PWM channel
+ * This parameter can be one of the macros group @ref TMR4_PWM_Channel
+ * @param [in] u16Polarity TMR4 PWM output polarity
+ * This parameter can be one of the macros group @ref TMR4_PWM_Polarity
+ * @arg TMR4_PWM_OXH_HOLD_OXL_HOLD: Output PWML and PWMH signals without changing the level
+ * @arg TMR4_PWM_OXH_INVT_OXL_INVT: Output both PWML and PWMH signals reversed
+ * @arg TMR4_PWM_OXH_INVT_OXL_HOLD: Output the PWMH signal reversed, outputs the PWML signal without changing the level
+ * @arg TMR4_PWM_OXH_HOLD_OXL_INVT: Output the PWMH signal without changing the level, Outputs the PWML signal reversed
+ * @retval None
+ */
+void TMR4_PWM_SetPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity)
+{
+ __IO uint16_t *POCR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch));
+ DDL_ASSERT(IS_TMR4_PWM_POLARITY(u16Polarity));
+
+ /* Get pointer of current channel PWM register address */
+ POCR = TMR4_POCR(TMR4x, u32Ch);
+
+ MODIFY_REG16(*POCR, TMR4_POCR_LVLS, u16Polarity);
+}
+
+/**
+ * @brief Start TMR4 PWM reload-timer
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 PWM channel
+ * This parameter can be one of the macros group @ref TMR4_PWM_Channel
+ * @retval None
+ */
+void TMR4_PWM_StartReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch)
+{
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch));
+
+ SET_REG_BIT(TMR4x->RCSR, TMR4_RCSR_RTEx_MASK(u32Ch));
+}
+
+/**
+ * @brief Stop TMR4 PWM reload-timer
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 PWM channel
+ * This parameter can be one of the macros group @ref TMR4_PWM_Channel
+ * @retval None
+ */
+void TMR4_PWM_StopReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch)
+{
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch));
+
+ SET_REG_BIT(TMR4x->RCSR, TMR4_RCSR_RTSx_MASK(u32Ch));
+}
+
+/**
+ * @brief Set TMR4 PWM filter count value
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 PWM channel
+ * This parameter can be one of the macros group @ref TMR4_PWM_Channel
+ * @param [in] u16Value TMR4 PWM filter count value
+ * @arg number of 16bit
+ * @retval None
+ */
+void TMR4_PWM_SetFilterCountValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value)
+{
+ __IO uint16_t *PFSR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch));
+
+ /* Get pointer of current channel PWM register address */
+ PFSR = TMR4_PFSR(TMR4x, u32Ch);
+
+ WRITE_REG16(*PFSR, u16Value);
+}
+
+/**
+ * @brief Set TMR4 PWM dead time count
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 PWM channel
+ * This parameter can be one of the macros group @ref TMR4_PWM_Channel
+ * @param [in] u32DeadTimeIndex TMR4 PWM dead time register index
+ * This parameter can be one of the macros group @ref TMR4_PWM_Dead_Time_Register_Index
+ * @arg TMR4_PWM_PDAR_IDX: TMR4_PDARn
+ * @arg TMR4_PWM_PDBR_IDX: TMR4_PDBRn
+ * @param [in] u16Value TMR4 PWM dead time register value
+ * @arg number of 16bit
+ * @retval None
+ */
+void TMR4_PWM_SetDeadTimeValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex, uint16_t u16Value)
+{
+ __IO uint16_t *PDR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch));
+ DDL_ASSERT(IS_TMR4_PWM_DEADTIME_REG_IDX(u32DeadTimeIndex));
+
+ /* Get pointer of current channel PWM register address */
+ PDR = TMR4_PDR(TMR4x, u32Ch, u32DeadTimeIndex);
+
+ WRITE_REG16(*PDR, u16Value);
+}
+
+/**
+ * @brief Get TMR4 PWM dead time count
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 PWM channel
+ * This parameter can be one of the macros group @ref TMR4_PWM_Channel
+ * @param [in] u32DeadTimeIndex TMR4 PWM dead time register index
+ * This parameter can be one of the macros group @ref TMR4_PWM_Dead_Time_Register_Index
+ * @arg TMR4_PWM_PDAR_IDX: TMR4_PDARn
+ * @arg TMR4_PWM_PDBR_IDX: TMR4_PDBRn
+ * @retval TMR4 PWM dead time register value
+ */
+uint16_t TMR4_PWM_GetDeadTimeValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex)
+{
+ __I uint16_t *PDR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch));
+ DDL_ASSERT(IS_TMR4_PWM_DEADTIME_REG_IDX(u32DeadTimeIndex));
+
+ /* Get pointer of current channel PWM register address */
+ PDR = TMR4_PDR(TMR4x, u32Ch, u32DeadTimeIndex);
+
+ return READ_REG16(*PDR);
+}
+
+/**
+ * @brief Set TMR4 PWM register TMR4_PSCR.OE bit effect time
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Time Effect time
+ * This parameter can be one of the macros group @ref TMR4_PWM_OE_Bit_Effect_Time
+ * @arg TMR4_PWM_OE_EFFECT_IMMED: TMR4 PWM register TMR4_PSCR.OE bit immediate effect
+ * @arg TMR4_PWM_OE_EFFECT_COUNT_PEAK: TMR4 PWM register TMR4_PSCR.OE bit effect when TMR4 counter count peak
+ * @arg TMR4_PWM_OE_EFFECT_COUNT_VALLEY: TMR4 PWM register TMR4_PSCR.OE bit effect when TMR4 counter count valley
+ * @retval None
+ */
+void TMR4_PWM_SetOEEffectTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32Time)
+{
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_PWM_OE_EFFECT(u32Time));
+
+ MODIFY_REG32(TMR4x->PSCR, TMR4_PSCR_ODT, u32Time);
+}
+
+/**
+ * @brief Enable or disable the TMR4 PWM main output by hardware after clear EMB event.
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @arg ENABLE: The TMR4_PSCR.MOE bit automatically set to 1 by hardware to restore the PWM normal output.
+ * @arg DISABLE: The TMR4_PSCR.MOE bit can only be set to 1 by software to restore the PWM normal output.
+ * @retval None
+ */
+void TMR4_PWM_EmbHWMainOutputCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(TMR4x->PSCR, TMR4_PSCR_AOE);
+ } else {
+ CLR_REG32_BIT(TMR4x->PSCR, TMR4_PSCR_AOE);
+ }
+}
+
+/**
+ * @brief Enable or disable the TMR4 PWM main output function.
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR4_PWM_MainOutputCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(TMR4x->PSCR, TMR4_PSCR_MOE);
+ } else {
+ CLR_REG32_BIT(TMR4x->PSCR, TMR4_PSCR_MOE);
+ }
+}
+
+/**
+ * @brief Set TMR4 PWM port output mode
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32PwmPin TMR4 PWM pin
+ * This parameter can be one of the macros group @ref TMR4_PWM_Pin
+ * @param [in] u32Mode The PWM port output mode
+ * This parameter can be one of the macros group @ref TMR4_PWM_Pin_Output_Mode
+ * @arg TMR4_PWM_PIN_OUTPUT_OS: TIM4__Oxy(x=U/V/W,y=H/L) output polarity by specified OSxy
+ * @arg TMR4_PWM_PIN_OUTPUT_NORMAL: TIM4__Oxy(x=U/V/W,y=H/L) output normal PWM
+ * @retval None
+ */
+void TMR4_PWM_SetPortOutputMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32PwmPin, uint32_t u32Mode)
+{
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_PWM_PIN(u32PwmPin));
+ DDL_ASSERT(IS_TMR4_PWM_PIN_MD(u32Mode));
+
+ MODIFY_REG32(TMR4x->PSCR, TMR4_PSCR_OExy_MASK(u32PwmPin), TMR4_PSCR_OExy(u32PwmPin, u32Mode));
+}
+
+/**
+ * @brief Set TMR4 PWM pin status when below conditions occur:1.EMB 2.MOE=0 3.MOE=1&OExy=0
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32PwmPin TMR4 PWM pin
+ * This parameter can be one of the macros group @ref TMR4_PWM_Pin
+ * @param [in] u32PinStatus TMR4 PWM pin status
+ * This parameter can be one of the macros group @ref TMR4_PWM_Abnormal_Pin_Status.
+ * @retval None
+ */
+void TMR4_PWM_SetAbnormalPinStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32PwmPin, uint32_t u32PinStatus)
+{
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_PWM_ABNORMAL_PIN_STAT(u32PinStatus));
+ DDL_ASSERT(IS_TMR4_PWM_PIN(u32PwmPin));
+
+ MODIFY_REG32(TMR4x->PSCR, TMR4_PSCR_OSxy_MASK(u32PwmPin), TMR4_PSCR_OSxy(u32PwmPin, u32PinStatus));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMR4_Event_Global_Functions TMR4 Event Global Functions
+ * @{
+ */
+
+/**
+ * @brief Set the fields of structure stc_tmr4_evt_init_t to default values
+ * @param [in] pstcTmr4EventInit Pointer to a @ref stc_tmr4_evt_init_t structure
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcTmr4EventInit value is NULL.
+ */
+int32_t TMR4_EVT_StructInit(stc_tmr4_evt_init_t *pstcTmr4EventInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcTmr4EventInit) {
+ pstcTmr4EventInit->u16Mode = TMR4_EVT_MD_CMP;
+ pstcTmr4EventInit->u16CompareValue = 0U;
+ pstcTmr4EventInit->u16OutputEvent = TMR4_EVT_OUTPUT_EVT0;
+ pstcTmr4EventInit->u16MatchCond = 0U;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize TMR4 event
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 event channel
+ * This parameter can be one of the macros group @ref TMR4_Event_Channel
+ * @param [in] pstcTmr4EventInit Pointer to a @ref stc_tmr4_evt_init_t structure
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcTmr4EventInit value is NULL.
+ */
+int32_t TMR4_EVT_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_evt_init_t *pstcTmr4EventInit)
+{
+ uint16_t u16Value;
+ __IO uint16_t *SCCR;
+ __IO uint16_t *SCSR;
+ __IO uint16_t *SCMR;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcTmr4EventInit) {
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch));
+ DDL_ASSERT(IS_TMR4_EVT_MD(pstcTmr4EventInit->u16Mode));
+ DDL_ASSERT(IS_TMR4_EVT_OUTPUT_EVT(pstcTmr4EventInit->u16OutputEvent));
+ DDL_ASSERT(IS_TMR4_EVT_MATCH_COND(pstcTmr4EventInit->u16MatchCond));
+
+ /* Get actual address of register list of current channel */
+ SCCR = TMR4_SCCR(TMR4x, u32Ch);
+ SCSR = TMR4_SCSR(TMR4x, u32Ch);
+ SCMR = TMR4_SCMR(TMR4x, u32Ch);
+
+ /* Set SCSR register */
+ u16Value = (pstcTmr4EventInit->u16Mode | pstcTmr4EventInit->u16OutputEvent | pstcTmr4EventInit->u16MatchCond);
+ WRITE_REG16(*SCSR, u16Value);
+
+ /* Set SCMR register */
+ WRITE_REG16(*SCMR, 0xFF00U);
+
+ /* Set SCCR register: compare value */
+ WRITE_REG16(*SCCR, pstcTmr4EventInit->u16CompareValue);
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief De-initialize TMR4 PWM
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 event channel
+ * This parameter can be one of the macros group @ref TMR4_Event_Channel
+ * @retval None
+ */
+void TMR4_EVT_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch)
+{
+ __IO uint16_t *SCCR;
+ __IO uint16_t *SCSR;
+ __IO uint16_t *SCMR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch));
+
+ /* Get actual address of register list of current channel */
+ SCCR = TMR4_SCCR(TMR4x, u32Ch);
+ SCSR = TMR4_SCSR(TMR4x, u32Ch);
+ SCMR = TMR4_SCMR(TMR4x, u32Ch);
+
+ /* Configure default parameter */
+ WRITE_REG16(*SCCR, 0x0U);
+ WRITE_REG16(*SCSR, 0x0000U);
+ WRITE_REG16(*SCMR, TMR4_SCMR_RST_VALUE);
+}
+
+/**
+ * @brief Set TMR4 event delay object
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 event channel
+ * This parameter can be one of the macros group @ref TMR4_Event_Channel
+ * @param [in] u16Object TMR4 event delay object
+ * This parameter can be one of the macros group @ref TMR4_Event_Delay_Object
+ * @arg TMR4_EVT_DELAY_OCCRXH: TMR4 event delay object - OCCRxh
+ * @arg TMR4_EVT_DELAY_OCCRXL: TMR4 event delay object - OCCRxl
+ * @retval None
+ */
+void TMR4_EVT_SetDelayObject(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object)
+{
+ __IO uint16_t *SCSR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch));
+ DDL_ASSERT(IS_TMR4_EVT_DELAY_OBJECT(u16Object));
+
+ /* Get actual address of register list of current channel */
+ SCSR = TMR4_SCSR(TMR4x, u32Ch);
+
+ /* Set SCSR register */
+ MODIFY_REG16(*SCSR, TMR4_SCSR_EVTDS, u16Object);
+}
+
+/**
+ * @brief Set TMR4 event trigger event.
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 event channel
+ * This parameter can be one of the macros group @ref TMR4_Event_Channel
+ * @param [in] u16MaskTime Mask times
+ * This parameter can be one of the macros group @ref TMR4_Event_Mask_Times
+ * @arg TMR4_EVT_MASK0: Mask 0 times
+ * @arg TMR4_EVT_MASK1: Mask 1 times
+ * @arg TMR4_EVT_MASK2: Mask 2 times
+ * @arg TMR4_EVT_MASK3: Mask 3 times
+ * @arg TMR4_EVT_MASK4: Mask 4 times
+ * @arg TMR4_EVT_MASK5: Mask 5 times
+ * @arg TMR4_EVT_MASK6: Mask 6 times
+ * @arg TMR4_EVT_MASK7: Mask 7 times
+ * @arg TMR4_EVT_MASK8: Mask 8 times
+ * @arg TMR4_EVT_MASK9: Mask 9 times
+ * @arg TMR4_EVT_MASK10: Mask 10 times
+ * @arg TMR4_EVT_MASK11: Mask 11 times
+ * @arg TMR4_EVT_MASK12: Mask 12 times
+ * @arg TMR4_EVT_MASK13: Mask 13 times
+ * @arg TMR4_EVT_MASK14: Mask 14 times
+ * @arg TMR4_EVT_MASK15: Mask 15 times
+ * @retval None
+ */
+void TMR4_EVT_SetMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16MaskTime)
+{
+ __IO uint16_t *SCMR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch));
+ DDL_ASSERT(IS_TMR4_EVT_MASK(u16MaskTime));
+
+ /* Get actual address of register list of current channel */
+ SCMR = TMR4_SCMR(TMR4x, u32Ch);
+
+ /* Set SCMR register */
+ MODIFY_REG16(*SCMR, TMR4_SCMR_AMC, u16MaskTime);
+}
+
+/**
+ * @brief Get TMR4 event SCCR register value
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 event channel
+ * This parameter can be one of the macros group @ref TMR4_Event_Channel
+ * @retval Returned value can be one of the macros group @ref TMR4_Event_Mask_Times
+ * - TMR4_EVT_MASK0: Mask 0 times
+ * - TMR4_EVT_MASK1: Mask 1 times
+ * - TMR4_EVT_MASK2: Mask 2 times
+ * - TMR4_EVT_MASK3: Mask 3 times
+ * - TMR4_EVT_MASK4: Mask 4 times
+ * - TMR4_EVT_MASK5: Mask 5 times
+ * - TMR4_EVT_MASK6: Mask 6 times
+ * - TMR4_EVT_MASK7: Mask 7 times
+ * - TMR4_EVT_MASK8: Mask 8 times
+ * - TMR4_EVT_MASK9: Mask 9 times
+ * - TMR4_EVT_MASK10: Mask 10 times
+ * - TMR4_EVT_MASK11: Mask 11 times
+ * - TMR4_EVT_MASK12: Mask 12 times
+ * - TMR4_EVT_MASK13: Mask 13 times
+ * - TMR4_EVT_MASK14: Mask 14 times
+ * - TMR4_EVT_MASK15: Mask 15 times
+ */
+uint16_t TMR4_EVT_GetMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch)
+{
+ __I uint16_t *SCMR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch));
+
+ /* Get actual address of register list of current channel */
+ SCMR = TMR4_SCMR(TMR4x, u32Ch);
+
+ return READ_REG16_BIT(*SCMR, TMR4_SCMR_AMC);
+}
+
+/**
+ * @brief Set TMR4 event compare value
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 event channel
+ * This parameter can be one of the macros group @ref TMR4_Event_Channel
+ * @param [in] u16Value SCCR register value
+ * @arg number of 16bit
+ * @retval None
+ */
+void TMR4_EVT_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value)
+{
+ __IO uint16_t *SCCR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch));
+
+ /* Get actual address of register list of current channel */
+ SCCR = TMR4_SCCR(TMR4x, u32Ch);
+
+ /* Set SCCR register */
+ WRITE_REG16(*SCCR, u16Value);
+}
+
+/**
+ * @brief Get TMR4 event compare value
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 event channel
+ * This parameter can be one of the macros group @ref TMR4_Event_Channel
+ * @retval SCCR register value
+ */
+uint16_t TMR4_EVT_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch)
+{
+ __I uint16_t *SCCR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch));
+
+ /* Get actual address of register list of current channel */
+ SCCR = TMR4_SCCR(TMR4x, u32Ch);
+
+ return READ_REG16(*SCCR);
+}
+
+/**
+ * @brief Set TMR4 output event
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 event channel
+ * This parameter can be one of the macros group @ref TMR4_Event_Channel
+ * @param [in] u16Event TMR4 event output event
+ * This parameter can be one of the macros group @ref TMR4_Event_Output_Event
+ * @retval None
+ */
+void TMR4_EVT_SetOutputEvent(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Event)
+{
+ __IO uint16_t *SCSR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch));
+ DDL_ASSERT(IS_TMR4_EVT_OUTPUT_EVT(u16Event));
+
+ /* Get actual address of register list of current channel */
+ SCSR = TMR4_SCSR(TMR4x, u32Ch);
+
+ /* Set SCSR register */
+ MODIFY_REG16(*SCSR, TMR4_SCSR_EVTOS, u16Event);
+}
+
+/**
+ * @brief Set the SCCR&SCMR buffer transfer condition
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 event channel
+ * This parameter can be one of the macros group @ref TMR4_Event_Channel
+ * @param [in] u16BufCond The buffer transfer condition
+ * This parameter can be one of the macros group @ref TMR4_Event_Buffer_Transfer_Condition
+ * @arg TMR4_EVT_BUF_COND_IMMED: Register SCCR&SCMR buffer transfer when writing to the SCCR&SCMR register
+ * @arg TMR4_EVT_BUF_COND_VALLEY: Register SCCR&SCMR buffer transfer when counter count valley
+ * @arg TMR4_EVT_BUF_COND_PEAK: Register SCCR&SCMR buffer transfer when counter count peak
+ * @arg TMR4_EVT_BUF_COND_PEAK_VALLEY: Register SCCR&SCMR buffer transfer when counter count peak or valley
+ * @retval None
+ */
+void TMR4_EVT_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16BufCond)
+{
+ __IO uint16_t *SCSR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch));
+ DDL_ASSERT(IS_TMR4_EVT_BUF_COND(u16BufCond));
+
+ /* Get actual address of register list of current channel */
+ SCSR = TMR4_SCSR(TMR4x, u32Ch);
+
+ MODIFY_REG16(*SCSR, TMR4_SCSR_BUFEN, u16BufCond);
+}
+
+/**
+ * @brief Enable or disable the buffer interval response function of TMR4 event.
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 event channel
+ * This parameter can be one of the macros group @ref TMR4_Event_Channel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR4_EVT_BufIntervalResponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState)
+{
+ __IO uint16_t *SCSR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ /* Get actual address of register list of current channel */
+ SCSR = TMR4_SCSR(TMR4x, u32Ch);
+
+ if (ENABLE == enNewState) {
+ SET_REG16_BIT(*SCSR, TMR4_SCSR_LMC);
+ } else {
+ CLR_REG16_BIT(*SCSR, TMR4_SCSR_LMC);
+ }
+}
+
+/**
+ * @brief Enable or disable the specified interval response of TMR4 event.
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 event channel
+ * This parameter can be one of the macros group @ref TMR4_Event_Channel
+ * @param [in] u16MaskType The specified mask compare type of TMR4 event
+ * This parameter can be any composed value of the macros group @ref TMR4_Event_Mask
+ * @arg TMR4_EVT_MASK_VALLEY: Compare with the counter valley interrupt mask counter
+ * @arg TMR4_EVT_MASK_PEAK: Compare with the counter peak interrupt mask counter
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR4_EVT_EventIntervalResponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch,
+ uint16_t u16MaskType, en_functional_state_t enNewState)
+{
+ __IO uint16_t *SCMR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch));
+ DDL_ASSERT(IS_TMR4_EVT_MASK_TYPE(u16MaskType));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ /* Get actual address of register list of current channel */
+ SCMR = TMR4_SCMR(TMR4x, u32Ch);
+
+ if (ENABLE == enNewState) {
+ SET_REG16_BIT(*SCMR, u16MaskType);
+ } else {
+ CLR_REG16_BIT(*SCMR, u16MaskType);
+ }
+}
+
+/**
+ * @brief Enable or disable the specified count compare type of TMR4 event
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u32Ch TMR4 event channel
+ * This parameter can be one of the macros group @ref TMR4_Event_Channel
+ * @param [in] u16Cond The specified count compare type of TMR4 event
+ * This parameter can be any composed value of the macros group @ref TMR4_Event_Match_Condition
+ * @arg TMR4_EVT_MATCH_CNT_UP: Start event operate when match with SCCR&SCMR and TMR4 counter count up
+ * @arg TMR4_EVT_MATCH_CNT_DOWN: Start event operate when match with SCCR&SCMR and TMR4 counter count down
+ * @arg TMR4_EVT_MATCH_CNT_VALLEY: Start event operate when match with SCCR&SCMR and TMR4 counter count valley
+ * @arg TMR4_EVT_MATCH_CNT_PEAK: Start event operate when match with SCCR&SCMR and TMR4 counter count peak
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR4_EVT_MatchCondCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState)
+{
+ __IO uint16_t *SCSR;
+
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch));
+ DDL_ASSERT(IS_TMR4_EVT_MATCH_COND(u16Cond));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ /* Get actual address of register list of current channel */
+ SCSR = TMR4_SCSR(TMR4x, u32Ch);
+
+ if (ENABLE == enNewState) {
+ SET_REG16_BIT(*SCSR, u16Cond);
+ } else {
+ CLR_REG16_BIT(*SCSR, u16Cond);
+ }
+}
+
+/**
+ * @brief Set TMR4 event signal output to port
+ * @param [in] TMR4x Pointer to TMR4 instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base
+ * @param [in] u16Signal TMR4 event signal selection
+ * This parameter can be one of the macros group @ref TMR4_Event_Output_Signal
+ * @retval None
+ */
+void TMR4_EVT_SetOutputEventSignal(CM_TMR4_TypeDef *TMR4x, uint16_t u16Signal)
+{
+ DDL_ASSERT(IS_TMR4_UNIT(TMR4x));
+ DDL_ASSERT(IS_TMR4_EVT_OUTPUT_SIGNAL(u16Signal));
+
+ MODIFY_REG16(TMR4x->SCER, TMR4_SCER_EVTRS, u16Signal);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* LL_TMR4_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_tmr6.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_tmr6.c
new file mode 100644
index 0000000000..cd031b89e7
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_tmr6.c
@@ -0,0 +1,1879 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_tmr6.c
+ * @brief This file provides firmware functions to manage the TMR6(TMR6).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Modify typo
+ Delete union in stc_tmr6_init_t structure
+ Modify API TMR6_GetCountDir()
+ 2023-12-15 CDT Modify for headfile update: CM_TMR6CR -> CM_TMR6_COMMON
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_tmr6.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_TMR6 TMR6
+ * @brief TMR6 Driver Library
+ * @{
+ */
+
+#if (LL_TMR6_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup TMR6_Local_Macros TMR6 Local Macros
+ * @{
+ */
+
+/* Timer6 registers reset value */
+#define TMR6_REG_RST_VALUE_U32 (0xFFFFFFFFUL)
+#define TMR6_REG_RST_VALUE_U16 (0xFFFFU)
+#define TMR6_REG_GCONR_RST_VALUE (0x00000100UL)
+
+/* Define for BCONR register configuration */
+#define BCONR_FUNC_CMD_MASK (0x01UL)
+#define BCONR_GEN_CFG_MASK (0x0000000EUL)
+#define BCONR_GEN_CFG_CHB_OFS (0x04UL)
+#define BCONR_PERIOD_CFG_MASK (0x0000000EUL)
+#define BCONR_PERIOD_CFG_OFS (0x08UL)
+#define BCONR_SPECIAL_CFG_MASK (0x0000000EUL)
+#define BCONR_SPECIAL_CFG_CHA_OFS (0x10UL)
+#define BCONR_SPECIAL_CFG_CHB_OFS (0x14UL)
+
+/* Define mask value for PWM output configuration for PCNAR/PCNBR register */
+#define PCNA_BR_REG_OUTPUT_CFG_MASK (0x8000FFFFUL)
+#define PCNA_BR_REG_EMB_CFG_MASK (TMR6_PCNAR_EMBSA | TMR6_PCNAR_EMBRA | TMR6_PCNAR_EMBCA)
+#define PCONR_REG_POLARITY_MASK (0x03UL)
+
+/* Define mask value for GCONR register */
+#define TMR6_INIT_MASK (TMR6_GCONR_DIR | TMR6_GCONR_MODE | TMR6_GCONR_CKDIV)
+#define TMR6_ZMASK_CFG_MASK (TMR6_GCONR_ZMSKVAL | TMR6_GCONR_ZMSKPOS | TMR6_GCONR_ZMSKREV)
+
+/**
+ * @defgroup TMR6_Check_Param_Validity TMR6 Check Parameters Validity
+ * @{
+ */
+
+/*! Parameter valid check for normal timer6 unit */
+#define IS_VALID_TMR6_UNIT(x) \
+( ((x) == CM_TMR6_1) || \
+ ((x) == CM_TMR6_2) || \
+ ((x) == CM_TMR6_3) || \
+ ((x) == CM_TMR6_4) || \
+ ((x) == CM_TMR6_5) || \
+ ((x) == CM_TMR6_6) || \
+ ((x) == CM_TMR6_7) || \
+ ((x) == CM_TMR6_8) || \
+ ((x) == CM_TMR6_9) || \
+ ((x) == CM_TMR6_10))
+
+/*! Parameter valid check for timer6 count source */
+#define IS_TMR6_CNT_SRC(x) \
+( ((x) == TMR6_CNT_SRC_SW) || \
+ ((x) == TMR6_CNT_SRC_HW))
+
+/*! Parameter valid check for interrupt source configuration */
+#define IS_VALID_IRQ(x) \
+( ((x) != 0UL) && \
+ (((x) | TMR6_INT_ALL) == TMR6_INT_ALL))
+
+/*! Parameter valid check for status bit read */
+#define IS_VALID_GET_FLAG(x) \
+( ((x) != 0UL) && \
+ (((x) | TMR6_FLAG_ALL) == TMR6_FLAG_ALL))
+
+/*! Parameter valid check for status bit clear */
+#define IS_VALID_CLR_FLAG(x) \
+( ((x) != 0UL) && \
+ (((x) | TMR6_FLAG_CLR_ALL) == TMR6_FLAG_CLR_ALL))
+
+/*! Parameter valid check for period register */
+#define IS_VALID_PERIOD_REG(x) \
+( (x) <= TMR6_PERIOD_REG_C)
+
+/*! Parameter valid check for general compare register */
+#define IS_VALID_CMP_REG(x) \
+( (x) <= TMR6_CMP_REG_F)
+
+/*! Parameter valid check for general/special compare channel */
+#define IS_VALID_CNT_CH(x) \
+( ((x) == TMR6_CH_A) || \
+ ((x) == TMR6_CH_B))
+
+/*! Parameter valid check for buffer function number */
+#define IS_VALID_BUF_NUM(x) \
+( ((x) == TMR6_BUF_SINGLE) || \
+ ((x) == TMR6_BUF_DUAL))
+
+/*! Parameter valid check for buffer transfer timer configuration */
+#define IS_VALID_BUF_TRANS_TRIG(x) \
+( ((x) == TMR6_BUF_TRANS_INVD) || \
+ ((x) == TMR6_BUF_TRANS_OVF) || \
+ ((x) == TMR6_BUF_TRANS_UDF) || \
+ ((x) == TMR6_BUF_TRANS_OVF_UDF))
+
+/*! Parameter valid check for count condition for valid period function */
+#define IS_VALID_PERIOD_CNT_COND(x) \
+( ((x) == TMR6_VALID_PERIOD_INVD) || \
+ ((x) == TMR6_VALID_PERIOD_CNT_COND_VALLEY) || \
+ ((x) == TMR6_VALID_PERIOD_CNT_COND_PEAK) || \
+ ((x) == TMR6_VALID_PERIOD_CNT_COND_VALLEY_PEAK))
+
+/*! Parameter valid check for count condition for valid period count */
+#define IS_VALID_PERIOD_CNT(x) \
+( ((x) == TMR6_VALID_PERIOD_CNT_INVD) || \
+ ((x) == TMR6_VALID_PERIOD_CNT1) || \
+ ((x) == TMR6_VALID_PERIOD_CNT2) || \
+ ((x) == TMR6_VALID_PERIOD_CNT3) || \
+ ((x) == TMR6_VALID_PERIOD_CNT4) || \
+ ((x) == TMR6_VALID_PERIOD_CNT5) || \
+ ((x) == TMR6_VALID_PERIOD_CNT6) || \
+ ((x) == TMR6_VALID_PERIOD_CNT7))
+
+/*! Parameter valid check for count register data range */
+#define IS_VALID_REG_RANGE_U16(x) ((x) <= 0xFFFFUL)
+
+/*! Parameter valid check for dead time register */
+#define IS_VALID_DEADTIME_REG(x) \
+( ((x) == TMR6_DEADTIME_REG_UP_A) || \
+ ((x) == TMR6_DEADTIME_REG_DOWN_A) || \
+ ((x) == TMR6_DEADTIME_REG_UP_B) || \
+ ((x) == TMR6_DEADTIME_REG_DOWN_B))
+
+/*! Parameter valid check for pin */
+#define IS_VALID_PIN(x) \
+( ((x) == TMR6_IO_PWMA) || \
+ ((x) == TMR6_IO_PWMB) || \
+ ((x) == TMR6_INPUT_TRIGA) || \
+ ((x) == TMR6_INPUT_TRIGB) || \
+ ((x) == TMR6_INPUT_TRIGC) || \
+ ((x) == TMR6_INPUT_TRIGD))
+
+/*! Parameter valid check for input pin filter clock */
+#define IS_VALID_FILTER_CLK(x) \
+( ((x) == TMR6_FILTER_CLK_DIV1) || \
+ ((x) == TMR6_FILTER_CLK_DIV4) || \
+ ((x) == TMR6_FILTER_CLK_DIV16) || \
+ ((x) == TMR6_FILTER_CLK_DIV64))
+
+/*! Parameter valid check for PWM pin status */
+#define IS_VALID_PWM_POLARITY(x) \
+( ((x) == TMR6_PWM_LOW) || \
+ ((x) == TMR6_PWM_HIGH) || \
+ ((x) == TMR6_PWM_HOLD) || \
+ ((x) == TMR6_PWM_INVT))
+
+/*! Parameter valid check for force PWM output pin */
+#define IS_VALID_PWM_FORCE_POLARITY(x) \
+( ((x) == TMR6_PWM_FORCE_INVD) || \
+ ((x) == TMR6_PWM_FORCE_LOW) || \
+ ((x) == TMR6_PWM_FORCE_HIGH))
+
+/*! Parameter valid check for PWM pin status for count start and stop */
+#define IS_VALID_PWM_POLARITY_START_STOP(x) \
+( ((x) == TMR6_PWM_LOW) || \
+ ((x) == TMR6_PWM_HIGH) || \
+ ((x) == TMR6_PWM_HOLD))
+
+#define IS_VALID_CNT_STAT(x) \
+( ((x) == TMR6_STAT_START) || \
+ ((x) == TMR6_STAT_STOP) || \
+ ((x) == TMR6_STAT_OVF) || \
+ ((x) == TMR6_STAT_UDF) || \
+ ((x) == TMR6_STAT_UP_CNT_MATCH_A) || \
+ ((x) == TMR6_STAT_DOWN_CNT_MATCH_A) || \
+ ((x) == TMR6_STAT_UP_CNT_MATCH_B) || \
+ ((x) == TMR6_STAT_DOWN_CNT_MATCH_B))
+
+/*! Parameter valid check for pin mode */
+#define IS_VALID_PIN_MD(x) \
+( ((x) == TMR6_PIN_CMP_OUTPUT) || \
+ ((x) == TMR6_PIN_CAPT_INPUT))
+
+/*! Parameter valid check for EMB event valid channel */
+#define IS_VALID_EMB_CH(x) \
+( ((x) == TMR6_EMB_EVT_CH0) || \
+ ((x) == TMR6_EMB_EVT_CH1) || \
+ ((x) == TMR6_EMB_EVT_CH2) || \
+ ((x) == TMR6_EMB_EVT_CH3) || \
+ ((x) == TMR6_EMB_EVT_CH4) || \
+ ((x) == TMR6_EMB_EVT_CH5))
+
+/*! Parameter valid check for EMB release mode when EMB event invalid */
+#define IS_VALID_EMB_RELEASE_MD(x) \
+( ((x) == TMR6_EMB_RELEASE_IMMED) || \
+ ((x) == TMR6_EMB_RELEASE_OVF) || \
+ ((x) == TMR6_EMB_RELEASE_UDF) || \
+ ((x) == TMR6_EMB_RELEASE_OVF_UDF))
+
+/*! Parameter valid check for pin output status when EMB event valid */
+#define IS_VALID_EMB_VALID_PIN_POLARITY(x) \
+( ((x) == TMR6_EMB_PIN_NORMAL) || \
+ ((x) == TMR6_EMB_PIN_HIZ) || \
+ ((x) == TMR6_EMB_PIN_LOW) || \
+ ((x) == TMR6_EMB_PIN_HIGH))
+
+/*! Parameter valid check for dead time buffer function for DTUAR and DTUBR register */
+#define IS_VALID_DEADTIME_BUF_FUNC_DTUAR_REG(x) \
+( ((x) == TMR6_DEADTIME_CNT_UP_BUF_OFF) || \
+ ((x) == TMR6_DEADTIME_CNT_UP_BUF_ON))
+
+/*! Parameter valid check for dead time buffer function for DTDAR and DTDBR register */
+#define IS_VALID_DEADTIME_BUF_FUNC_DTDAR_REG(x) \
+( ((x) == TMR6_DEADTIME_CNT_DOWN_BUF_OFF) || \
+ ((x) == TMR6_DEADTIME_CNT_DOWN_BUF_ON))
+
+/*! Parameter valid check for dead time buffer transfer condition */
+#define IS_VALID_DEADTIME_BUF_TRANS_COND_REG(x) \
+( ((x) == TMR6_DEADTIME_BUF_COND_INVD) || \
+ ((x) == TMR6_DEADTIME_BUF_COND_OVF) || \
+ ((x) == TMR6_DEADTIME_BUF_COND_UDF) || \
+ ((x) == TMR6_DEADTIME_BUF_COND_OVF_UDF))
+
+/*! Parameter valid check for dead time equal function for DTUAR and DTDAR register */
+#define IS_VALID_DEADTIME_EQUAL_FUNC_REG(x) \
+( ((x) == TMR6_DEADTIME_EQUAL_OFF) || \
+ ((x) == TMR6_DEADTIME_EQUAL_ON))
+
+/*! Parameter valid check for start condition */
+#define IS_VALID_START_COND(x) \
+( ((x) != 0UL) && \
+ (((x) | TMR6_START_COND_ALL) == TMR6_START_COND_ALL))
+
+/*! Parameter valid check for stop condition */
+#define IS_VALID_STOP_COND(x) \
+( ((x) != 0UL) && \
+ (((x) | TMR6_STOP_COND_ALL) == TMR6_STOP_COND_ALL))
+
+/*! Parameter valid check for clear condition */
+#define IS_VALID_CLR_COND(x) \
+( ((x) != 0UL) && \
+ (((x) | TMR6_CLR_COND_ALL) == TMR6_CLR_COND_ALL))
+
+/*! Parameter valid check for update condition */
+#define IS_VALID_UPD_COND(x) \
+( ((x) != 0UL) && \
+ (((x) | TMR6_UPD_COND_ALL) == TMR6_UPD_COND_ALL))
+
+/*! Parameter valid check for capture condition */
+#define IS_VALID_CAPT_COND(x) \
+( ((x) != 0UL) && \
+ (((x) | TMR6_CAPT_COND_ALL) == TMR6_CAPT_COND_ALL))
+
+/*! Parameter valid check for hardware count up condition */
+#define IS_VALID_CNT_UP_COND(x) \
+( ((x) != 0UL) && \
+ (((x) | TMR6_CNT_UP_COND_ALL) == TMR6_CNT_UP_COND_ALL))
+
+/*! Parameter valid check for hardware count down condition */
+#define IS_VALID_CNT_DOWN_COND(x) \
+( ((x) != 0UL) && \
+ (((x) | TMR6_CNT_DOWN_COND_ALL) == TMR6_CNT_DOWN_COND_ALL))
+
+/*! Parameter valid check for count Mode */
+#define IS_VALID_CNT_MD(x) \
+( ((x) == TMR6_MD_SAWTOOTH) || \
+ ((x) == TMR6_MD_TRIANGLE))
+
+/*! Parameter valid check for count direction */
+#define IS_VALID_CNT_DIR(x) \
+( ((x) == TMR6_CNT_UP) || \
+ ((x) == TMR6_CNT_DOWN))
+
+/*! Parameter valid check for count clock division */
+#define IS_VALID_CNT_CLK_DIV(x) \
+( ((x) == TMR6_CLK_DIV1) || \
+ ((x) == TMR6_CLK_DIV2) || \
+ ((x) == TMR6_CLK_DIV4) || \
+ ((x) == TMR6_CLK_DIV8) || \
+ ((x) == TMR6_CLK_DIV16) || \
+ ((x) == TMR6_CLK_DIV32) || \
+ ((x) == TMR6_CLK_DIV64) || \
+ ((x) == TMR6_CLK_DIV128) || \
+ ((x) == TMR6_CLK_DIV256) || \
+ ((x) == TMR6_CLK_DIV512) || \
+ ((x) == TMR6_CLK_DIV1024))
+
+/*! Parameter valid check for count reload mode */
+#define IS_VALID_CNT_RELOAD_MD(x) \
+( ((x) == TMR6_CNT_RELOAD_ON) || \
+ ((x) == TMR6_CNT_RELOAD_OFF))
+
+/*! Parameter valid check for Z Mask input function mask cycles number */
+#define IS_VALID_ZMASK_CYCLES(x) \
+( ((x) == TMR6_ZMASK_FUNC_INVD) || \
+ ((x) == TMR6_ZMASK_CYCLE_4) || \
+ ((x) == TMR6_ZMASK_CYCLE_8) || \
+ ((x) == TMR6_ZMASK_CYCLE_16))
+
+/*! Parameter valid check for Z Mask function of timer6 position unit */
+#define IS_VALID_POS_UNIT_ZMASK_FUNC(x) \
+( ((x) == TMR6_POS_CLR_ZMASK_FUNC_OFF) || \
+ ((x) == TMR6_POS_CLR_ZMASK_FUNC_ON))
+
+/*! Parameter valid check for Z Mask function of timer6 revolution unit */
+#define IS_VALID_REVO_UNIT_ZMASK_FUNC(x) \
+( ((x) == TMR6_REVO_CNT_ZMASK_FUNC_OFF) || \
+ ((x) == TMR6_REVO_CNT_ZMASK_FUNC_ON))
+
+/*! Parameter valid check for software sync control unit */
+#define IS_VALID_SW_UNIT(x) \
+( ((x) != 0UL) && \
+ (((x) | TMR6_SW_SYNC_ALL) == TMR6_SW_SYNC_ALL))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ * @defgroup TMR6_Global_Functions TMR6 Global Functions
+ * @{
+ */
+
+/**
+ * @brief Initialize the timer6 count function
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] pstcTmr6Init Pointer of configuration structure @ref stc_tmr6_init_t
+ * @retval int32_t:
+ * - LL_OK: Successfully done
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t TMR6_Init(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_init_t *pstcTmr6Init)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+
+ if (NULL != pstcTmr6Init) {
+ /* Check parameters */
+ DDL_ASSERT(IS_TMR6_CNT_SRC(pstcTmr6Init->u8CountSrc));
+
+ if (pstcTmr6Init->u8CountSrc == TMR6_CNT_SRC_SW) {
+ /* Normal count */
+ DDL_ASSERT(IS_VALID_CNT_MD(pstcTmr6Init->sw_count.u32CountMode));
+ DDL_ASSERT(IS_VALID_CNT_DIR(pstcTmr6Init->sw_count.u32CountDir));
+ DDL_ASSERT(IS_VALID_CNT_CLK_DIV(pstcTmr6Init->sw_count.u32ClockDiv));
+
+ MODIFY_REG32(TMR6x->GCONR, TMR6_INIT_MASK, (pstcTmr6Init->sw_count.u32CountMode | pstcTmr6Init->sw_count.u32CountDir | \
+ pstcTmr6Init->sw_count.u32ClockDiv));
+ } else {
+ /* Hardware count */
+ DDL_ASSERT(IS_VALID_CNT_UP_COND(pstcTmr6Init->hw_count.u32CountUpCond) ||
+ (pstcTmr6Init->hw_count.u32CountUpCond == TMR6_CNT_UP_COND_INVD));
+ DDL_ASSERT(IS_VALID_CNT_DOWN_COND(pstcTmr6Init->hw_count.u32CountDownCond) ||
+ (pstcTmr6Init->hw_count.u32CountDownCond == TMR6_CNT_DOWN_COND_INVD));
+
+ WRITE_REG32(TMR6x->HCUPR, pstcTmr6Init->hw_count.u32CountUpCond);
+ WRITE_REG32(TMR6x->HCDOR, pstcTmr6Init->hw_count.u32CountDownCond);
+ }
+
+ DDL_ASSERT(IS_VALID_CNT_RELOAD_MD(pstcTmr6Init->u32CountReload));
+ MODIFY_REG32(TMR6x->GCONR, TMR6_GCONR_OVSTP, pstcTmr6Init->u32CountReload);
+ DDL_ASSERT(IS_VALID_REG_RANGE_U16(pstcTmr6Init->u32PeriodValue));
+ WRITE_REG32(TMR6x->PERAR, pstcTmr6Init->u32PeriodValue);
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Set timer6 base count mode
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Mode @ref TMR6_Count_Mode_Define
+ * @retval None
+ */
+void TMR6_SetCountMode(CM_TMR6_TypeDef *TMR6x, uint32_t u32Mode)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_CNT_MD(u32Mode));
+ MODIFY_REG32(TMR6x->GCONR, TMR6_GCONR_MODE, u32Mode);
+}
+
+/**
+ * @brief Set timer6 base count direction
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Dir @ref TMR6_Count_Dir_Define
+ * @retval None
+ */
+void TMR6_SetCountDir(CM_TMR6_TypeDef *TMR6x, uint32_t u32Dir)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_CNT_DIR(u32Dir));
+ MODIFY_REG32(TMR6x->GCONR, TMR6_GCONR_DIR, u32Dir);
+}
+
+/**
+ * @brief Set timer6 base count direction
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @retval uint32_t Count direction @ref TMR6_Count_Dir_Status_Define
+ */
+uint32_t TMR6_GetCountDir(CM_TMR6_TypeDef *TMR6x)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ return READ_REG32_BIT(TMR6x->STFLR, TMR6_STFLR_DIRF);
+}
+
+/**
+ * @brief Set timer6 clock division
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Div @ref TMR6_Count_Clock_Define
+ * @retval None
+ */
+void TMR6_SetClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Div)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_CNT_CLK_DIV(u32Div));
+
+ MODIFY_REG32(TMR6x->GCONR, TMR6_GCONR_CKDIV, u32Div);
+}
+
+/**
+ * @brief Timer6 count reload function command
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR6_CountReloadCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ CLR_REG32_BIT(TMR6x->GCONR, TMR6_GCONR_OVSTP);
+ } else {
+ SET_REG32_BIT(TMR6x->GCONR, TMR6_GCONR_OVSTP);
+ }
+}
+
+/**
+ * @brief Hardware increase condition command
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Cond Events source for hardware count, maybe one or any combination of the parameter
+ * @ref TMR6_HW_Count_Up_Cond_Define
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR6_HWCountUpCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_CNT_UP_COND(u32Cond));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(TMR6x->HCUPR, u32Cond);
+ } else {
+ CLR_REG32_BIT(TMR6x->HCUPR, u32Cond);
+ }
+}
+
+/**
+ * @brief Hardware decrease condition command
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Cond Events source for hardware count, maybe one or any combination of the parameter
+ * @ref TMR6_HW_Count_Down_Cond_Define
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR6_HWCountDownCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_CNT_DOWN_COND(u32Cond));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(TMR6x->HCDOR, u32Cond);
+ } else {
+ CLR_REG32_BIT(TMR6x->HCDOR, u32Cond);
+ }
+}
+
+/**
+ * @brief Initialize the timer6 hardware count function
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Ch @ref TMR6_Count_Ch_Define
+ * @param [in] pstcPwmInit Pointer of initialize structure
+ * @retval int32_t:
+ * - LL_OK: Successfully done
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t TMR6_PWM_Init(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_pwm_init_t *pstcPwmInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ __IO uint32_t *TMR6_GCMxR;
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_CNT_CH(u32Ch));
+
+ TMR6_GCMxR = (__IO uint32_t *)((uint32_t)&TMR6x->GCMAR + 4UL * u32Ch);
+
+ if (NULL != pstcPwmInit) {
+ DDL_ASSERT(IS_VALID_PWM_POLARITY_START_STOP(pstcPwmInit->u32StartPolarity));
+ DDL_ASSERT(IS_VALID_PWM_POLARITY_START_STOP(pstcPwmInit->u32StopPolarity));
+ DDL_ASSERT(IS_VALID_PWM_POLARITY(pstcPwmInit->u32CountDownMatchBPolarity));
+ DDL_ASSERT(IS_VALID_PWM_POLARITY(pstcPwmInit->u32CountUpMatchBPolarity));
+ DDL_ASSERT(IS_VALID_PWM_POLARITY(pstcPwmInit->u32CountDownMatchAPolarity));
+ DDL_ASSERT(IS_VALID_PWM_POLARITY(pstcPwmInit->u32CountUpMatchAPolarity));
+ DDL_ASSERT(IS_VALID_PWM_POLARITY(pstcPwmInit->u32UdfPolarity));
+ DDL_ASSERT(IS_VALID_PWM_POLARITY(pstcPwmInit->u32OvfPolarity));
+ DDL_ASSERT(IS_VALID_REG_RANGE_U16(pstcPwmInit->u32CompareValue));
+ WRITE_REG32(*TMR6_GCMxR, pstcPwmInit->u32CompareValue);
+
+ if (TMR6_CH_A == u32Ch) {
+ MODIFY_REG32(TMR6x->PCNAR, PCNA_BR_REG_OUTPUT_CFG_MASK, \
+ pstcPwmInit->u32CountDownMatchBPolarity << TMR6_PCNAR_CMBDCA_POS \
+ | pstcPwmInit->u32CountUpMatchBPolarity << TMR6_PCNAR_CMBUCA_POS \
+ | pstcPwmInit->u32CountDownMatchAPolarity << TMR6_PCNAR_CMADCA_POS \
+ | pstcPwmInit->u32CountUpMatchAPolarity << TMR6_PCNAR_CMAUCA_POS \
+ | pstcPwmInit->u32UdfPolarity << TMR6_PCNAR_UDFCA_POS \
+ | pstcPwmInit->u32OvfPolarity << TMR6_PCNAR_OVFCA_POS \
+ | pstcPwmInit->u32StopPolarity << TMR6_PCNAR_STPCA_POS \
+ | pstcPwmInit->u32StartPolarity << TMR6_PCNAR_STACA_POS);
+ } else {
+ MODIFY_REG32(TMR6x->PCNBR, PCNA_BR_REG_OUTPUT_CFG_MASK, \
+ pstcPwmInit->u32CountDownMatchBPolarity << TMR6_PCNBR_CMBDCB_POS \
+ | pstcPwmInit->u32CountUpMatchBPolarity << TMR6_PCNBR_CMBUCB_POS \
+ | pstcPwmInit->u32CountDownMatchAPolarity << TMR6_PCNBR_CMADCB_POS \
+ | pstcPwmInit->u32CountUpMatchAPolarity << TMR6_PCNBR_CMAUCB_POS \
+ | pstcPwmInit->u32UdfPolarity << TMR6_PCNBR_UDFCB_POS \
+ | pstcPwmInit->u32OvfPolarity << TMR6_PCNBR_OVFCB_POS \
+ | pstcPwmInit->u32StopPolarity << TMR6_PCNBR_STPCB_POS \
+ | pstcPwmInit->u32StartPolarity << TMR6_PCNBR_STACB_POS);
+ }
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Timer6 PWM output command
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Ch @ref TMR6_Count_Ch_Define
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR6_PWM_OutputCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState)
+{
+ uint32_t u32Tmp;
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_CNT_CH(u32Ch));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ u32Tmp = 0xFFFFFFFFUL;
+ } else {
+ u32Tmp = 0UL;
+ }
+ if (TMR6_CH_A == u32Ch) {
+ MODIFY_REG32(TMR6x->PCNAR, TMR6_PCNAR_OUTENA, u32Tmp);
+ } else {
+ MODIFY_REG32(TMR6x->PCNBR, TMR6_PCNBR_OUTENB, u32Tmp);
+ }
+}
+
+/**
+ * @brief Timer6 set pin polarity
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Ch @ref TMR6_Count_Ch_Define
+ * @param [in] u32CountState Polarity set for @ref TMR6_Count_State_Define
+ * @param [in] u32Polarity @ref TMR6_Pin_Polarity_Define
+ * @retval None
+ */
+void TMR6_PWM_SetPolarity(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32CountState, uint32_t u32Polarity)
+{
+ uint32_t u32PolarityMask = PCONR_REG_POLARITY_MASK;
+
+ uint8_t au8Pos[8] = {TMR6_PCNAR_STACA_POS, TMR6_PCNAR_STPCA_POS, TMR6_PCNAR_OVFCA_POS, TMR6_PCNAR_UDFCA_POS, \
+ TMR6_PCNAR_CMAUCA_POS, TMR6_PCNAR_CMADCA_POS, TMR6_PCNAR_CMBUCA_POS, TMR6_PCNAR_CMBDCA_POS
+ };
+ DDL_ASSERT(IS_VALID_PWM_POLARITY(u32Polarity));
+ DDL_ASSERT(IS_VALID_CNT_STAT(u32CountState));
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_CNT_CH(u32Ch));
+
+ u32Polarity <<= au8Pos[u32CountState];
+ u32PolarityMask <<= au8Pos[u32CountState];
+
+ if (TMR6_CH_A == u32Ch) {
+ MODIFY_REG32(TMR6x->PCNAR, u32PolarityMask, u32Polarity);
+ } else {
+ MODIFY_REG32(TMR6x->PCNBR, u32PolarityMask, u32Polarity);
+ }
+}
+
+/**
+ * @brief Timer6 set force polarity when next period
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Ch @ref TMR6_Count_Ch_Define
+ * @param [in] u32Polarity @ref TMR6_Force_Output_Polarity_Define
+ * @retval None
+ */
+void TMR6_PWM_SetForcePolarity(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Polarity)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_CNT_CH(u32Ch));
+ DDL_ASSERT(IS_VALID_PWM_FORCE_POLARITY(u32Polarity));
+
+ if (TMR6_CH_A == u32Ch) {
+ MODIFY_REG32(TMR6x->PCNAR, TMR6_PCNAR_FORCA, u32Polarity << TMR6_PCNAR_FORCA_POS);
+ } else {
+ MODIFY_REG32(TMR6x->PCNBR, TMR6_PCNBR_FORCB, u32Polarity << TMR6_PCNBR_FORCB_POS);
+ }
+}
+
+/**
+ * @brief Hardware capture condition command
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Ch Input pin select @ref TMR6_Count_Ch_Define
+ * @param [in] u32Cond Events source for hardware capture, maybe one or any combination of the parameter
+ * @ref TMR6_hardware_capture_condition_Define
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR6_HWCaptureCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState)
+{
+ __IO uint32_t *HCPxR;
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_CNT_CH(u32Ch));
+ DDL_ASSERT(IS_VALID_CAPT_COND(u32Cond));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ HCPxR = (__IO uint32_t *)((uint32_t)&TMR6x->HCPAR + (u32Ch * 4UL));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(*HCPxR, u32Cond);
+ } else {
+ CLR_REG32_BIT(*HCPxR, u32Cond);
+ }
+}
+
+/**
+ * @brief Port input filter function configuration(Trig)
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Pin Pin to be configured @ref TMR6_Pin_Define
+ * @param [in] u32Div Filter clock @ref TMR6_Input_Filter_Clock
+ * @retval None
+ */
+void TMR6_SetFilterClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, uint32_t u32Div)
+{
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_PIN(u32Pin));
+ DDL_ASSERT(IS_VALID_FILTER_CLK(u32Div));
+
+ switch (u32Pin) {
+ case TMR6_IO_PWMA:
+ MODIFY_REG32(TMR6x->FCNGR, TMR6_FCNGR_NOFICKGA, u32Div << TMR6_FCNGR_NOFICKGA_POS);
+ break;
+ case TMR6_IO_PWMB:
+ MODIFY_REG32(TMR6x->FCNGR, TMR6_FCNGR_NOFICKGB, u32Div << TMR6_FCNGR_NOFICKGB_POS);
+ break;
+ case TMR6_INPUT_TRIGA:
+ MODIFY_REG32(CM_TMR6_COMMON->FCNTR, TMR6_COMMON_FCNTR_NOFICKTA, u32Div << TMR6_COMMON_FCNTR_NOFICKTA_POS);
+ break;
+ case TMR6_INPUT_TRIGB:
+ MODIFY_REG32(CM_TMR6_COMMON->FCNTR, TMR6_COMMON_FCNTR_NOFICKTB, u32Div << TMR6_COMMON_FCNTR_NOFICKTB_POS);
+ break;
+ case TMR6_INPUT_TRIGC:
+ MODIFY_REG32(CM_TMR6_COMMON->FCNTR, TMR6_COMMON_FCNTR_NOFICKTC, u32Div << TMR6_COMMON_FCNTR_NOFICKTC_POS);
+ break;
+ case TMR6_INPUT_TRIGD:
+ MODIFY_REG32(CM_TMR6_COMMON->FCNTR, TMR6_COMMON_FCNTR_NOFICKTD, u32Div << TMR6_COMMON_FCNTR_NOFICKTD_POS);
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Port input filter function command
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Pin Input port to be configured @ref TMR6_Pin_Define
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR6_FilterCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_PIN(u32Pin));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ switch (u32Pin) {
+ case TMR6_IO_PWMA:
+ MODIFY_REG32(TMR6x->FCNGR, TMR6_FCNGR_NOFIENGA, ((uint32_t)enNewState) << TMR6_FCNGR_NOFIENGA_POS);
+ break;
+ case TMR6_IO_PWMB:
+ MODIFY_REG32(TMR6x->FCNGR, TMR6_FCNGR_NOFIENGB, ((uint32_t)enNewState) << TMR6_FCNGR_NOFIENGB_POS);
+ break;
+ case TMR6_INPUT_TRIGA:
+ MODIFY_REG32(CM_TMR6_COMMON->FCNTR, TMR6_COMMON_FCNTR_NOFIENTA, ((uint32_t)enNewState) << TMR6_COMMON_FCNTR_NOFIENTA_POS);
+ break;
+ case TMR6_INPUT_TRIGB:
+ MODIFY_REG32(CM_TMR6_COMMON->FCNTR, TMR6_COMMON_FCNTR_NOFIENTB, ((uint32_t)enNewState) << TMR6_COMMON_FCNTR_NOFIENTB_POS);
+ break;
+ case TMR6_INPUT_TRIGC:
+ MODIFY_REG32(CM_TMR6_COMMON->FCNTR, TMR6_COMMON_FCNTR_NOFIENTC, ((uint32_t)enNewState) << TMR6_COMMON_FCNTR_NOFIENTC_POS);
+ break;
+ case TMR6_INPUT_TRIGD:
+ MODIFY_REG32(CM_TMR6_COMMON->FCNTR, TMR6_COMMON_FCNTR_NOFIENTD, ((uint32_t)enNewState) << TMR6_COMMON_FCNTR_NOFIENTD_POS);
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Set channel function
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Ch Channel to be configured @ref TMR6_Count_Ch_Define
+ * @param [in] u32Func IO mode @ref TMR6_Pin_Mode_Define
+ * @retval None
+ */
+void TMR6_SetFunc(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Func)
+{
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_CNT_CH(u32Ch));
+ DDL_ASSERT(IS_VALID_PIN_MD(u32Func));
+
+ switch (u32Ch) {
+ case TMR6_CH_A:
+ MODIFY_REG32(TMR6x->PCNAR, TMR6_PCNAR_CAPMDA, u32Func);
+ break;
+ case TMR6_CH_B:
+ MODIFY_REG32(TMR6x->PCNBR, TMR6_PCNBR_CAPMDB, u32Func);
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Timer6 interrupt enable or disable
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32IntType Irq flag, Can be one or any combination of the values from
+ * @ref TMR6_Int_Flag_Define
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR6_IntCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32IntType, en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_IRQ(u32IntType));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(TMR6x->ICONR, u32IntType);
+ } else {
+ CLR_REG32_BIT(TMR6x->ICONR, u32IntType);
+ }
+}
+
+/**
+ * @brief Get Timer6 status flag
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Flag Status bit to be read, Can be one or any combination of the values from
+ * @ref TMR6_Stat_Flag_Define
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t TMR6_GetStatus(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag)
+{
+ en_flag_status_t enStatus = RESET;
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_GET_FLAG(u32Flag));
+
+ if (0UL != READ_REG32_BIT(TMR6x->STFLR, u32Flag)) {
+ enStatus = SET;
+ }
+ return enStatus;
+}
+
+/**
+ * @brief Clear Timer6 status flag
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Flag Status bit to be read, Can be one or any combination of the values from
+ * @ref TMR6_Stat_Flag_Define
+ * @retval None
+ */
+void TMR6_ClearStatus(CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_CLR_FLAG(u32Flag));
+
+ CLR_REG32_BIT(TMR6x->STFLR, u32Flag);
+}
+
+/**
+ * @brief Get Timer6 period number when valid period function enable
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @retval uint32_t Data for periods number
+ */
+uint32_t TMR6_GetPeriodNum(const CM_TMR6_TypeDef *TMR6x)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+
+ return (READ_REG32_BIT(TMR6x->STFLR, TMR6_STFLR_VPERNUM) >> TMR6_STFLR_VPERNUM_POS);
+}
+
+/**
+ * @brief De-initialize the timer6 unit
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @retval None
+ */
+void TMR6_DeInit(CM_TMR6_TypeDef *TMR6x)
+{
+ uint32_t u32RefRegResetValue;
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ u32RefRegResetValue = TMR6_REG_RST_VALUE_U16;
+
+ WRITE_REG32(TMR6x->GCONR, TMR6_REG_GCONR_RST_VALUE);
+ WRITE_REG32(TMR6x->CNTER, 0UL);
+ WRITE_REG32(TMR6x->PERAR, u32RefRegResetValue);
+ WRITE_REG32(TMR6x->PERBR, u32RefRegResetValue);
+ WRITE_REG32(TMR6x->PERCR, u32RefRegResetValue);
+ WRITE_REG32(TMR6x->GCMAR, u32RefRegResetValue);
+ WRITE_REG32(TMR6x->GCMBR, u32RefRegResetValue);
+ WRITE_REG32(TMR6x->GCMCR, u32RefRegResetValue);
+ WRITE_REG32(TMR6x->GCMDR, u32RefRegResetValue);
+ WRITE_REG32(TMR6x->GCMER, u32RefRegResetValue);
+ WRITE_REG32(TMR6x->GCMFR, u32RefRegResetValue);
+ WRITE_REG32(TMR6x->SCMAR, u32RefRegResetValue);
+ WRITE_REG32(TMR6x->SCMBR, u32RefRegResetValue);
+ WRITE_REG32(TMR6x->SCMCR, u32RefRegResetValue);
+ WRITE_REG32(TMR6x->SCMDR, u32RefRegResetValue);
+ WRITE_REG32(TMR6x->SCMER, u32RefRegResetValue);
+ WRITE_REG32(TMR6x->SCMFR, u32RefRegResetValue);
+ WRITE_REG32(TMR6x->DTUAR, u32RefRegResetValue);
+ WRITE_REG32(TMR6x->DTDAR, u32RefRegResetValue);
+ WRITE_REG32(TMR6x->DTUBR, u32RefRegResetValue);
+ WRITE_REG32(TMR6x->DTDBR, u32RefRegResetValue);
+ WRITE_REG32(TMR6x->ICONR, 0UL);
+ WRITE_REG32(TMR6x->BCONR, 0UL);
+ WRITE_REG32(TMR6x->DCONR, 0UL);
+ WRITE_REG32(TMR6x->PCNAR, 0UL);
+ WRITE_REG32(TMR6x->PCNBR, 0UL);
+ WRITE_REG32(TMR6x->FCNGR, 0UL);
+ WRITE_REG32(CM_TMR6_COMMON->FCNTR, 0UL);
+ WRITE_REG32(TMR6x->VPERR, 0UL);
+ WRITE_REG32(TMR6x->STFLR, 0UL);
+ WRITE_REG32(TMR6x->HSTAR, 0UL);
+ WRITE_REG32(TMR6x->HSTPR, 0UL);
+ WRITE_REG32(TMR6x->HCLRR, 0UL);
+ WRITE_REG32(TMR6x->HUPDR, 0UL);
+ WRITE_REG32(TMR6x->HCPAR, 0UL);
+ WRITE_REG32(TMR6x->HCPBR, 0UL);
+ WRITE_REG32(TMR6x->HCUPR, 0UL);
+ WRITE_REG32(TMR6x->HCDOR, 0UL);
+
+ WRITE_REG32(CM_TMR6_COMMON->SSTAR, 0UL);
+ WRITE_REG32(CM_TMR6_COMMON->SSTPR, 0UL);
+ WRITE_REG32(CM_TMR6_COMMON->SCLRR, 0UL);
+ WRITE_REG32(CM_TMR6_COMMON->SUPDR, 0UL);
+}
+
+/**
+ * @brief Timer6 count start
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @retval None
+ */
+void TMR6_Start(CM_TMR6_TypeDef *TMR6x)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ SET_REG32_BIT(TMR6x->GCONR, TMR6_GCONR_START);
+}
+
+/**
+ * @brief Timer6 count stop
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @retval None
+ */
+void TMR6_Stop(CM_TMR6_TypeDef *TMR6x)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ CLR_REG32_BIT(TMR6x->GCONR, TMR6_GCONR_START);
+}
+
+/**
+ * @brief Timer6 counter register set
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Value Counter value
+ * @retval None
+ */
+void TMR6_SetCountValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Value)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value));
+ WRITE_REG32(TMR6x->CNTER, u32Value);
+}
+
+/**
+ * @brief Timer6 update register set
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Value Counter value
+ * @retval None
+ */
+void TMR6_SetUpdateValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Value)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value));
+ WRITE_REG32(TMR6x->UPDAR, u32Value);
+}
+
+/**
+ * @brief Timer6 get counter register value
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @retval uint32_t Data for the count register value
+ */
+uint32_t TMR6_GetCountValue(const CM_TMR6_TypeDef *TMR6x)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+
+ return READ_REG32(TMR6x->CNTER);
+}
+
+/**
+ * @brief Timer6 get update register value
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @retval uint32_t Data for register value
+ */
+uint32_t TMR6_GetUpdateValue(const CM_TMR6_TypeDef *TMR6x)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+
+ return READ_REG32(TMR6x->UPDAR);
+}
+
+/**
+ * @brief Timer6 set period register(A~C)
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Index Period register to be write, @ref TMR6_Period_Reg_Index_Define
+ * @param [in] u32Value Period value for write
+ * @retval None
+ */
+void TMR6_SetPeriodValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value)
+{
+ __IO uint32_t *TMR6_PERxR;
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_PERIOD_REG(u32Index));
+
+ TMR6_PERxR = (uint32_t *)((uint32_t)&TMR6x->PERAR + 4UL * u32Index);
+
+ DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value));
+ WRITE_REG32(*TMR6_PERxR, u32Value);
+}
+
+/**
+ * @brief Timer6 set general compare register(A~F)
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Index General compare register to be write, @ref TMR6_Compare_Reg_Index_Define
+ * @param [in] u32Value Value for write
+ * @retval None
+ */
+void TMR6_SetCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value)
+{
+ __IO uint32_t *TMR6_GCMxR;
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_CMP_REG(u32Index));
+ TMR6_GCMxR = (__IO uint32_t *)((uint32_t)&TMR6x->GCMAR + 4UL * u32Index);
+
+ DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value));
+ WRITE_REG32(*TMR6_GCMxR, u32Value);
+}
+
+/**
+ * @brief Timer6 set special compare register(A~F)
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Index Special compare register to be write, @ref TMR6_Compare_Reg_Index_Define
+ * @param [in] u32Value Value for write
+ * @retval None
+ */
+void TMR6_SetSpecialCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value)
+{
+ __IO uint32_t *TMR6_SCMxR;
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_CMP_REG(u32Index));
+ TMR6_SCMxR = (uint32_t *)((uint32_t)&TMR6x->SCMAR + 4UL * u32Index);
+
+ DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value));
+ WRITE_REG32(*TMR6_SCMxR, u32Value);
+}
+
+/**
+ * @brief Timer6 set dead time register
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Index Special compare register to be write, @ref TMR6_DeadTime_Reg_Define
+ * @param [in] u32Value Value for write
+ * @retval None
+ */
+void TMR6_SetDeadTimeValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value)
+{
+ __IO uint32_t *TMR6_DTxyR;
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_DEADTIME_REG(u32Index));
+ TMR6_DTxyR = (uint32_t *)((uint32_t)&TMR6x->DTUAR + 4UL * u32Index);
+
+ DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value));
+ WRITE_REG32(*TMR6_DTxyR, u32Value);
+}
+
+/**
+ * @brief Timer6 get general compare registers value(A~F)
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Index General compare register to be read, @ref TMR6_Compare_Reg_Index_Define
+ * @retval uint32_t Data for value of the register
+ */
+uint32_t TMR6_GetCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index)
+{
+ __IO uint32_t *TMR6_GCMxR;
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_CMP_REG(u32Index));
+ TMR6_GCMxR = (uint32_t *)((uint32_t)&TMR6x->GCMAR + 4UL * u32Index);
+
+ return READ_REG32(*TMR6_GCMxR);
+}
+
+/**
+ * @brief Timer6 get special compare registers value(A~F)
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Index Special compare register to be read, @ref TMR6_Compare_Reg_Index_Define
+ * @retval uint32_t Data for value of the register
+ */
+uint32_t TMR6_GetSpecialCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index)
+{
+ __IO uint32_t *TMR6_SCMxR;
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_CMP_REG(u32Index));
+ TMR6_SCMxR = (uint32_t *)((uint32_t)&TMR6x->SCMAR + 4UL * u32Index);
+
+ return READ_REG32(*TMR6_SCMxR);
+}
+
+/**
+ * @brief Timer6 Get period register(A~C)
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Index Period register to be write, @ref TMR6_Period_Reg_Index_Define
+ * @retval uint32_t Data for value of the register
+ */
+uint32_t TMR6_GetPeriodValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index)
+{
+ __IO uint32_t *TMR6_PERxR;
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_PERIOD_REG(u32Index));
+ TMR6_PERxR = (uint32_t *)((uint32_t)&TMR6x->PERAR + 4UL * u32Index);
+
+ return READ_REG32(*TMR6_PERxR);
+}
+
+/**
+ * @brief Timer6 get dead time register
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Index Dead time register to be write, @ref TMR6_DeadTime_Reg_Define
+ * @retval uint32_t Data for value of the register
+ */
+uint32_t TMR6_GetDeadTimeValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index)
+{
+ __IO uint32_t *TMR6_DTxyR;
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_DEADTIME_REG(u32Index));
+ TMR6_DTxyR = (uint32_t *)((uint32_t)&TMR6x->DTUAR + 4UL * u32Index);
+
+ return READ_REG32(*TMR6_DTxyR);
+}
+
+/**
+ * @brief Timer6 general compare buffer function configuration
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Ch General compare buffer chose, @ref TMR6_Count_Ch_Define
+ * @param [in] pstcBufConfig Pointer of configuration structure
+ * @retval int32_t:
+ * - LL_OK: Successfully done
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t TMR6_GeneralBufConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_buf_config_t *pstcBufConfig)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ if (NULL != pstcBufConfig) {
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_CNT_CH(u32Ch));
+ DDL_ASSERT(IS_VALID_BUF_NUM(pstcBufConfig->u32BufNum));
+ DDL_ASSERT(IS_VALID_BUF_TRANS_TRIG(pstcBufConfig->u32BufTransCond));
+
+ if (TMR6_CH_A == u32Ch) {
+ MODIFY_REG32(TMR6x->BCONR, BCONR_GEN_CFG_MASK, (pstcBufConfig->u32BufNum | pstcBufConfig->u32BufTransCond));
+ } else {
+ MODIFY_REG32(TMR6x->BCONR, BCONR_GEN_CFG_MASK << BCONR_GEN_CFG_CHB_OFS, \
+ (pstcBufConfig->u32BufNum | pstcBufConfig->u32BufTransCond) << BCONR_GEN_CFG_CHB_OFS);
+ }
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Timer6 general compare buffer function command
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Ch General compare buffer chose, @ref TMR6_Count_Ch_Define
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR6_GeneralBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_CNT_CH(u32Ch));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (TMR6_CH_A == u32Ch) {
+ MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK, enNewState);
+ } else {
+ MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK << BCONR_GEN_CFG_CHB_OFS, \
+ ((uint32_t)enNewState) << BCONR_GEN_CFG_CHB_OFS);
+ }
+}
+
+/**
+ * @brief Timer6 special compare buffer function configuration
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Ch Special compare buffer chose, @ref TMR6_Count_Ch_Define
+ * @param [in] pstcBufConfig Pointer of configuration structure
+ * @retval int32_t:
+ * - LL_OK: Successfully done
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t TMR6_SpecialBufConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_buf_config_t *pstcBufConfig)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ if (NULL != pstcBufConfig) {
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_CNT_CH(u32Ch));
+ DDL_ASSERT(IS_VALID_BUF_NUM(pstcBufConfig->u32BufNum));
+ DDL_ASSERT(IS_VALID_BUF_TRANS_TRIG(pstcBufConfig->u32BufTransCond));
+
+ if (TMR6_CH_A == u32Ch) {
+ MODIFY_REG32(TMR6x->BCONR, BCONR_SPECIAL_CFG_MASK << BCONR_SPECIAL_CFG_CHA_OFS, \
+ (pstcBufConfig->u32BufNum | pstcBufConfig->u32BufTransCond) << BCONR_SPECIAL_CFG_CHA_OFS);
+ } else {
+ MODIFY_REG32(TMR6x->BCONR, BCONR_SPECIAL_CFG_MASK << BCONR_SPECIAL_CFG_CHB_OFS, \
+ (pstcBufConfig->u32BufNum | pstcBufConfig->u32BufTransCond) << BCONR_SPECIAL_CFG_CHB_OFS);
+ }
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Timer6 special compare buffer function command
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Ch General compare buffer chose, @ref TMR6_Count_Ch_Define
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR6_SpecialBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_CNT_CH(u32Ch));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (TMR6_CH_A == u32Ch) {
+ MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK << BCONR_SPECIAL_CFG_CHA_OFS, \
+ ((uint32_t)enNewState) << BCONR_SPECIAL_CFG_CHA_OFS);
+ } else {
+ MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK << BCONR_SPECIAL_CFG_CHB_OFS, \
+ ((uint32_t)enNewState) << BCONR_SPECIAL_CFG_CHB_OFS);
+ }
+}
+
+/**
+ * @brief Timer6 period buffer function configuration
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] pstcBufConfig Pointer of configuration structure
+ * @retval int32_t:
+ * - LL_OK: Successfully done
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t TMR6_PeriodBufConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_buf_config_t *pstcBufConfig)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ if (NULL != pstcBufConfig) {
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_BUF_NUM(pstcBufConfig->u32BufNum));
+ DDL_ASSERT(IS_VALID_BUF_TRANS_TRIG(pstcBufConfig->u32BufTransCond));
+
+ MODIFY_REG32(TMR6x->BCONR, BCONR_PERIOD_CFG_MASK << BCONR_PERIOD_CFG_OFS, \
+ (pstcBufConfig->u32BufNum | pstcBufConfig->u32BufTransCond) << BCONR_PERIOD_CFG_OFS);
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Timer6 period buffer function configuration
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR6_PeriodBufCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK << BCONR_PERIOD_CFG_OFS,
+ ((uint32_t)enNewState) << BCONR_PERIOD_CFG_OFS);
+}
+
+/**
+ * @brief Timer6 valid period function configuration for special compare function
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] pstcValidperiodConfig Pointer of configuration structure
+ * @retval int32_t:
+ * - LL_OK: Successfully done
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t TMR6_ValidPeriodConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_valid_period_config_t *pstcValidperiodConfig)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ if (NULL != pstcValidperiodConfig) {
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_PERIOD_CNT_COND(pstcValidperiodConfig->u32CountCond));
+ DDL_ASSERT(IS_VALID_PERIOD_CNT(pstcValidperiodConfig->u32PeriodInterval));
+
+ MODIFY_REG32(TMR6x->VPERR, TMR6_VPERR_PCNTS | TMR6_VPERR_PCNTE, \
+ pstcValidperiodConfig->u32CountCond | pstcValidperiodConfig->u32PeriodInterval);
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Timer6 valid period function command
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Ch General compare buffer chose, @ref TMR6_Count_Ch_Define
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR6_ValidPeriodCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_CNT_CH(u32Ch));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (TMR6_CH_A == u32Ch) {
+ MODIFY_REG32(TMR6x->VPERR, TMR6_VPERR_SPPERIA, ((uint32_t)enNewState) << TMR6_VPERR_SPPERIA_POS);
+ } else {
+ MODIFY_REG32(TMR6x->VPERR, TMR6_VPERR_SPPERIB, ((uint32_t)enNewState) << TMR6_VPERR_SPPERIB_POS);
+ }
+}
+
+/**
+ * @brief Timer6 dead time function command
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR6_DeadTimeFuncCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState)
+{
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(TMR6x->DCONR, TMR6_DCONR_DTCEN);
+ } else {
+ CLR_REG32_BIT(TMR6x->DCONR, TMR6_DCONR_DTCEN);
+ }
+}
+
+/**
+ * @brief DeadTime function configuration
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] pstcDeadTimeConfig Timer6 dead time config pointer
+ * @retval int32_t:
+ * - LL_OK: Successfully done
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t TMR6_DeadTimeConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_deadtime_config_t *pstcDeadTimeConfig)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+
+ if (NULL != pstcDeadTimeConfig) {
+ DDL_ASSERT(IS_VALID_DEADTIME_EQUAL_FUNC_REG(pstcDeadTimeConfig->u32EqualUpDown));
+ DDL_ASSERT(IS_VALID_DEADTIME_BUF_FUNC_DTUAR_REG(pstcDeadTimeConfig->u32BufUp));
+ DDL_ASSERT(IS_VALID_DEADTIME_BUF_FUNC_DTDAR_REG(pstcDeadTimeConfig->u32BufDown));
+ DDL_ASSERT(IS_VALID_DEADTIME_BUF_TRANS_COND_REG(pstcDeadTimeConfig->u32BufTransCond));
+
+ WRITE_REG32(TMR6x->DCONR, pstcDeadTimeConfig->u32EqualUpDown | pstcDeadTimeConfig->u32BufUp \
+ | pstcDeadTimeConfig->u32BufDown | pstcDeadTimeConfig->u32BufTransCond);
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Timer6 unit Z phase input mask config
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] pstcZMaskConfig Pointer of configuration structure
+ * @retval int32_t:
+ * - LL_OK: Successfully done
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t TMR6_ZMaskConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_zmask_config_t *pstcZMaskConfig)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ /* Check parameters */
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+
+ if (NULL != pstcZMaskConfig) {
+ DDL_ASSERT(IS_VALID_ZMASK_CYCLES(pstcZMaskConfig->u32ZMaskCycle));
+ DDL_ASSERT(IS_VALID_POS_UNIT_ZMASK_FUNC(pstcZMaskConfig->u32PosCountMaskFunc));
+ DDL_ASSERT(IS_VALID_REVO_UNIT_ZMASK_FUNC(pstcZMaskConfig->u32RevoCountMaskFunc));
+
+ MODIFY_REG32(TMR6x->GCONR, TMR6_ZMASK_CFG_MASK, pstcZMaskConfig->u32ZMaskCycle | \
+ pstcZMaskConfig->u32PosCountMaskFunc | pstcZMaskConfig->u32RevoCountMaskFunc);
+
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief EMB function configuration
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Ch Channel to be configured @ref TMR6_Count_Ch_Define
+ * @param [in] pstcEmbConfig Point EMB function Config Pointer
+ * @retval int32_t:
+ * - LL_OK: Successfully done
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t TMR6_EMBConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_emb_config_t *pstcEmbConfig)
+{
+ __IO uint32_t *PCNXR;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+
+ if (NULL != pstcEmbConfig) {
+ DDL_ASSERT(IS_VALID_CNT_CH(u32Ch));
+ DDL_ASSERT(IS_VALID_EMB_CH(pstcEmbConfig->u32ValidCh));
+ DDL_ASSERT(IS_VALID_EMB_RELEASE_MD(pstcEmbConfig->u32ReleaseMode));
+ DDL_ASSERT(IS_VALID_EMB_VALID_PIN_POLARITY(pstcEmbConfig->u32PinStatus));
+
+ if (TMR6_CH_A == u32Ch) {
+ PCNXR = (__IO uint32_t *)&TMR6x->PCNAR;
+ } else {
+ PCNXR = (__IO uint32_t *)&TMR6x->PCNBR;
+ }
+
+ MODIFY_REG32(*PCNXR, PCNA_BR_REG_EMB_CFG_MASK, pstcEmbConfig->u32ValidCh | pstcEmbConfig->u32ReleaseMode
+ | pstcEmbConfig->u32PinStatus);
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+
+}
+
+/**
+ * @brief Software Sync Start
+ * @param [in] u32Unit Software Sync units, This parameter can be one or any combination of the parameter
+ * @ref TMR6_SW_Sync_Unit_define
+ * @retval None
+ */
+void TMR6_SWSyncStart(uint32_t u32Unit)
+{
+ DDL_ASSERT(IS_VALID_SW_UNIT(u32Unit));
+ WRITE_REG32(CM_TMR6_COMMON->SSTAR, u32Unit);
+}
+
+/**
+ * @brief Software Sync Stop
+ * @param [in] u32Unit Software Sync units, This parameter can be one or any combination of the parameter
+ * @ref TMR6_SW_Sync_Unit_define
+ * @retval None
+ */
+void TMR6_SWSyncStop(uint32_t u32Unit)
+{
+ DDL_ASSERT(IS_VALID_SW_UNIT(u32Unit));
+ WRITE_REG32(CM_TMR6_COMMON->SSTPR, u32Unit);
+}
+
+/**
+ * @brief Software Sync clear
+ * @param [in] u32Unit Software Sync units, This parameter can be one or any combination of the parameter
+ * @ref TMR6_SW_Sync_Unit_define
+ * @retval None
+ */
+void TMR6_SWSyncClear(uint32_t u32Unit)
+{
+ DDL_ASSERT(IS_VALID_SW_UNIT(u32Unit));
+ WRITE_REG32(CM_TMR6_COMMON->SCLRR, u32Unit);
+}
+
+/**
+ * @brief Software Sync update
+ * @param [in] u32Unit Software Sync units, This parameter can be one or any combination of the parameter
+ * @ref TMR6_SW_Sync_Unit_define
+ * @retval None
+ */
+void TMR6_SWSyncUpdate(uint32_t u32Unit)
+{
+ DDL_ASSERT(IS_VALID_SW_UNIT(u32Unit));
+ WRITE_REG32(CM_TMR6_COMMON->SUPDR, u32Unit);
+}
+
+/**
+ * @brief Hardware start function command
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR6_HWStartCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ MODIFY_REG32(TMR6x->HSTAR, TMR6_HSTAR_STAS, ((uint32_t)enNewState) << TMR6_HSTAR_STAS_POS);
+}
+
+/**
+ * @brief Hardware stop function command
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR6_HWStopCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ MODIFY_REG32(TMR6x->HSTPR, TMR6_HSTPR_STPS, ((uint32_t)enNewState) << TMR6_HSTPR_STPS_POS);
+}
+
+/**
+ * @brief Hardware clear function command
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR6_HWClearCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ MODIFY_REG32(TMR6x->HCLRR, TMR6_HCLRR_CLES, ((uint32_t)enNewState) << TMR6_HCLRR_CLES_POS);
+}
+
+/**
+ * @brief Hardware update function command
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR6_HWUpdateCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ MODIFY_REG32(TMR6x->HUPDR, TMR6_HUPDR_UPDS, ((uint32_t)enNewState) << TMR6_HUPDR_UPDS_POS);
+}
+
+/**
+ * @brief Hardware start condition command
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Cond Events source for hardware start, maybe one or any combination of the parameter
+ * @ref TMR6_hardware_start_condition_Define
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR6_HWStartCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_START_COND(u32Cond));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(TMR6x->HSTAR, u32Cond);
+ } else {
+ CLR_REG32_BIT(TMR6x->HSTAR, u32Cond);
+ }
+}
+
+/**
+ * @brief Hardware stop condition command
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Cond Events source for hardware stop, maybe one or any combination of the parameter
+ * @ref TMR6_hardware_stop_condition_Define
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR6_HWStopCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_STOP_COND(u32Cond));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(TMR6x->HSTPR, u32Cond);
+ } else {
+ CLR_REG32_BIT(TMR6x->HSTPR, u32Cond);
+ }
+}
+
+/**
+ * @brief Hardware clear condition command
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Cond Events source for hardware clear, maybe one or any combination of the parameter
+ * @ref TMR6_hardware_clear_condition_Define
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR6_HWClearCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_CLR_COND(u32Cond));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(TMR6x->HCLRR, u32Cond);
+ } else {
+ CLR_REG32_BIT(TMR6x->HCLRR, u32Cond);
+ }
+}
+
+/**
+ * @brief Hardware update condition command
+ * @param [in] TMR6x Timer6 unit
+ * @arg CM_TMR6_x
+ * @param [in] u32Cond Events source for hardware update, maybe one or any combination of the parameter
+ * @ref TMR6_hardware_update_condition_Define
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMR6_HWUpdateCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x));
+ DDL_ASSERT(IS_VALID_UPD_COND(u32Cond));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(TMR6x->HUPDR, u32Cond);
+ } else {
+ CLR_REG32_BIT(TMR6x->HUPDR, u32Cond);
+ }
+}
+
+/**
+ * @brief Set the fields of structure stc_tmr6_init_t to default values
+ * @param [out] pstcTmr6Init Pointer to a @ref stc_tmr6_init_t structure
+ * @retval int32_t:
+ * - LL_OK: Successfully done
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t TMR6_StructInit(stc_tmr6_init_t *pstcTmr6Init)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ uint32_t u32RefRegResetValue;
+
+ /* Check structure pointer */
+ if (NULL != pstcTmr6Init) {
+ pstcTmr6Init->u8CountSrc = TMR6_CNT_SRC_SW;
+ pstcTmr6Init->sw_count.u32ClockDiv = TMR6_CLK_DIV1;
+ pstcTmr6Init->sw_count.u32CountMode = TMR6_MD_SAWTOOTH;
+ pstcTmr6Init->sw_count.u32CountDir = TMR6_CNT_UP;
+ pstcTmr6Init->hw_count.u32CountUpCond = TMR6_CNT_UP_COND_INVD;
+ pstcTmr6Init->hw_count.u32CountDownCond = TMR6_CNT_DOWN_COND_INVD;
+ u32RefRegResetValue = TMR6_REG_RST_VALUE_U16;
+ pstcTmr6Init->u32CountReload = TMR6_CNT_RELOAD_ON;
+ pstcTmr6Init->u32PeriodValue = u32RefRegResetValue;
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Set the fields of structure stc_tmr6_buf_config_t to default values
+ * @param [out] pstcBufConfig Pointer to a @ref stc_tmr6_buf_config_t structure
+ * @retval int32_t:
+ * - LL_OK: Successfully done
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t TMR6_BufFuncStructInit(stc_tmr6_buf_config_t *pstcBufConfig)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ /* Check structure pointer */
+ if (NULL != pstcBufConfig) {
+ pstcBufConfig->u32BufNum = TMR6_BUF_SINGLE;
+ pstcBufConfig->u32BufTransCond = TMR6_BUF_TRANS_INVD;
+
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Set the fields of structure stc_tmr6_valid_period_config_t to default values
+ * @param [out] pstcValidperiodConfig Pointer to a @ref stc_tmr6_valid_period_config_t structure
+ * @retval int32_t:
+ * - LL_OK: Successfully done
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t TMR6_ValidPeriodStructInit(stc_tmr6_valid_period_config_t *pstcValidperiodConfig)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ /* Check structure pointer */
+ if (NULL != pstcValidperiodConfig) {
+ pstcValidperiodConfig->u32CountCond = TMR6_VALID_PERIOD_INVD;
+ pstcValidperiodConfig->u32PeriodInterval = TMR6_VALID_PERIOD_CNT_INVD;
+
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Set the fields of structure stc_tmr6_emb_config_t to default values
+ * @param [out] pstcEmbConfig Pointer to a @ref stc_tmr6_emb_config_t structure
+ * @retval int32_t:
+ * - LL_OK: Successfully done
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t TMR6_EMBConfigStructInit(stc_tmr6_emb_config_t *pstcEmbConfig)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ /* Check structure pointer */
+ if (NULL != pstcEmbConfig) {
+ pstcEmbConfig->u32ValidCh = TMR6_EMB_EVT_CH0;
+ pstcEmbConfig->u32ReleaseMode = TMR6_EMB_RELEASE_IMMED;
+ pstcEmbConfig->u32PinStatus = TMR6_EMB_PIN_NORMAL;
+
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Set the fields of structure stc_tmr6_deadtime_config_t to default values
+ * @param [out] pstcDeadTimeConfig Pointer to a @ref stc_tmr6_deadtime_config_t structure
+ * @retval int32_t:
+ * - LL_OK: Successfully done
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t TMR6_DeadTimeStructInit(stc_tmr6_deadtime_config_t *pstcDeadTimeConfig)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ /* Check structure pointer */
+ if (NULL != pstcDeadTimeConfig) {
+ pstcDeadTimeConfig->u32EqualUpDown = TMR6_DEADTIME_EQUAL_OFF;
+ pstcDeadTimeConfig->u32BufUp = TMR6_DEADTIME_CNT_UP_BUF_OFF;
+ pstcDeadTimeConfig->u32BufDown = TMR6_DEADTIME_CNT_DOWN_BUF_OFF;
+ pstcDeadTimeConfig->u32BufTransCond = TMR6_DEADTIME_BUF_COND_INVD;
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Set the fields of structure stc_tmr6_zmask_config_t to default values
+ * @param [out] pstcZMaskConfig Pointer to a @ref stc_tmr6_zmask_config_t structure
+ * @retval int32_t:
+ * - LL_OK: Successfully done
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t TMR6_ZMaskConfigStructInit(stc_tmr6_zmask_config_t *pstcZMaskConfig)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ /* Check structure pointer */
+ if (NULL != pstcZMaskConfig) {
+ pstcZMaskConfig->u32ZMaskCycle = TMR6_ZMASK_FUNC_INVD;
+ pstcZMaskConfig->u32PosCountMaskFunc = TMR6_POS_CLR_ZMASK_FUNC_OFF;
+ pstcZMaskConfig->u32RevoCountMaskFunc = TMR6_REVO_CNT_ZMASK_FUNC_OFF;
+
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Set the fields of structure stc_tmr6_pwm_init_t to default values
+ * @param [out] pstcPwmInit Pointer to a @ref stc_tmr6_pwm_init_t structure
+ * @retval int32_t:
+ * - LL_OK: Successfully done
+ * - LL_ERR_INVD_PARAM: Parameter error
+ */
+int32_t TMR6_PWM_StructInit(stc_tmr6_pwm_init_t *pstcPwmInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ uint32_t u32RefRegResetValue;
+
+ /* Check structure pointer */
+ if (NULL != pstcPwmInit) {
+ pstcPwmInit->u32StartPolarity = TMR6_PWM_LOW;
+ pstcPwmInit->u32StopPolarity = TMR6_PWM_LOW;
+
+ u32RefRegResetValue = TMR6_REG_RST_VALUE_U32;
+ pstcPwmInit->u32CountDownMatchBPolarity = TMR6_PWM_LOW;
+ pstcPwmInit->u32CountUpMatchBPolarity = TMR6_PWM_LOW;
+ pstcPwmInit->u32CountDownMatchAPolarity = TMR6_PWM_LOW;
+ pstcPwmInit->u32CountUpMatchAPolarity = TMR6_PWM_LOW;
+ pstcPwmInit->u32UdfPolarity = TMR6_PWM_LOW;
+ pstcPwmInit->u32OvfPolarity = TMR6_PWM_LOW;
+ pstcPwmInit->u32CompareValue = u32RefRegResetValue;
+ i32Ret = LL_OK;
+ }
+ return i32Ret;
+}
+/**
+ * @}
+ */
+
+#endif /* LL_TMR6_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_tmra.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_tmra.c
new file mode 100644
index 0000000000..1f1c302c82
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_tmra.c
@@ -0,0 +1,1162 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_tmra.c
+ * @brief This file provides firmware functions to manage the TMRA(TimerA).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Modify typo
+ Delete union in stc_tmra_init_t structure
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_tmra.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_TMRA TMRA
+ * @brief TMRA Driver Library
+ * @{
+ */
+
+#if (LL_TMRA_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup TMRA_Local_Macros TMRA Local Macros
+ * @{
+ */
+/**
+ * @defgroup TMRA_Registers_Setting_definition TMRA Registers setting definition
+ * @{
+ */
+#define TMRA_REG_TYPE uint32_t
+#define TMRA_REG_VALUE_MAX (0xFFFFFFFFUL)
+
+#define SET_VAL_BY_ADDR(addr, v) (*(__IO TMRA_REG_TYPE *)(addr)) = (TMRA_REG_TYPE)(v)
+#define GET_VAL_BY_ADDR(addr) (*(__IO TMRA_REG_TYPE *)(addr))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_Configuration_Bit_Mask TMRA Configuration Bit Mask
+ * @{
+ */
+#define TMRA_BCSTRH_INT_MASK (TMRA_BCSTRH_ITENUDF | TMRA_BCSTRH_ITENOVF)
+#define TMRA_BCSTRH_FLAG_MASK (TMRA_BCSTRH_UDFF | TMRA_BCSTRH_OVFF)
+#define TMRA_FCONR_FILTER_CLK_MASK (0x3UL)
+#define TMRA_CCONR_FILTER_CLK_MASK (TMRA_CCONR_NOFICKCP)
+#define TMRA_PWM_POLARITY_MASK (TMRA_PCONR_STAC)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_Filter_Pin_Max TMRA Pin With Filter Max
+ * @{
+ */
+#define TMRA_PIN_MAX (TMRA_PIN_PWM4)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_Check_Parameters_Validity TMRA check parameters validity
+ * @{
+ */
+#define IS_TMRA_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask)))
+
+#define IS_TMRA_UNIT(x) \
+( ((x) == CM_TMRA_1) || \
+ ((x) == CM_TMRA_2) || \
+ ((x) == CM_TMRA_3) || \
+ ((x) == CM_TMRA_4) || \
+ ((x) == CM_TMRA_5) || \
+ ((x) == CM_TMRA_6))
+
+#define IS_TMRA_SYNC_UNIT(x) \
+( ((x) == CM_TMRA_2) || \
+ ((x) == CM_TMRA_4) || \
+ ((x) == CM_TMRA_6))
+
+#define IS_TMRA_CH(x) ((x) <= TMRA_CH4)
+
+#define IS_TMRA_UNIT_CH(unit, ch) (IS_TMRA_UNIT(unit) && IS_TMRA_CH(ch))
+
+#define IS_TMRA_CNT_SRC(x) (((x) == TMRA_CNT_SRC_SW) || ((x) == TMRA_CNT_SRC_HW))
+
+#define IS_TMRA_FUNC(x) (((x) == TMRA_FUNC_CMP) || ((x) == TMRA_FUNC_CAPT))
+
+#define IS_TMRA_DIR(x) (((x) == TMRA_DIR_DOWN) || ((x) == TMRA_DIR_UP))
+
+#define IS_TMRA_MD(x) (((x) == TMRA_MD_SAWTOOTH) || ((x) == TMRA_MD_TRIANGLE))
+
+#define IS_TMRA_CNT_RELOAD(x) (((x) == TMRA_CNT_RELOAD_DISABLE) || ((x) == TMRA_CNT_RELOAD_ENABLE))
+
+#define IS_TMRA_CMPVAL_BUF_CH(x) (((x) == TMRA_CH1) || ((x) == TMRA_CH3))
+
+#define IS_TMRA_CLK_DIV(x) \
+( ((x) == TMRA_CLK_DIV1) || \
+ ((x) == TMRA_CLK_DIV2) || \
+ ((x) == TMRA_CLK_DIV4) || \
+ ((x) == TMRA_CLK_DIV8) || \
+ ((x) == TMRA_CLK_DIV16) || \
+ ((x) == TMRA_CLK_DIV32) || \
+ ((x) == TMRA_CLK_DIV64) || \
+ ((x) == TMRA_CLK_DIV128) || \
+ ((x) == TMRA_CLK_DIV256) || \
+ ((x) == TMRA_CLK_DIV512) || \
+ ((x) == TMRA_CLK_DIV1024))
+
+#define IS_TMRA_FILTER_PIN(x) ((x) <= TMRA_PIN_MAX)
+
+#define IS_TMRA_CNT_UP_COND(x) IS_TMRA_BIT_MASK(x, TMRA_CNT_UP_COND_ALL)
+
+#define IS_TMRA_CNT_DOWN_COND(x) IS_TMRA_BIT_MASK(x, TMRA_CNT_DOWN_COND_ALL)
+
+#define IS_TMRA_INT(x) IS_TMRA_BIT_MASK(x, TMRA_INT_ALL)
+
+#define IS_TMRA_EVT(x) IS_TMRA_BIT_MASK(x, TMRA_EVT_ALL)
+
+#define IS_TMRA_FLAG(x) IS_TMRA_BIT_MASK(x, TMRA_FLAG_ALL)
+
+#define IS_TMRA_CAPT_COND(x) IS_TMRA_BIT_MASK(x, TMRA_CAPT_COND_ALL)
+
+#define IS_TMRA_FILTER_CLK_DIV(x) ((x) <= TMRA_FILTER_CLK_DIV64)
+
+#define IS_TMRA_UNIT_INT(u, x) (IS_TMRA_UNIT(u) && IS_TMRA_INT(x))
+
+#define IS_TMRA_CH_EVT(u, x) (IS_TMRA_UNIT(u) && IS_TMRA_EVT(x))
+
+#define IS_TMRA_UNIT_FPIN(u, x) (IS_TMRA_UNIT(u) && IS_TMRA_FILTER_PIN(x))
+
+#define IS_TMRA_UNIT_FLAG(u, x) (IS_TMRA_UNIT(u) && IS_TMRA_FLAG(x))
+
+#define IS_TMRA_BUF_TRANS_COND(x) \
+( ((x) == TMRA_BUF_TRANS_COND_OVF_UDF_CLR) || \
+ ((x) == TMRA_BUF_TRANS_COND_PEAK) || \
+ ((x) == TMRA_BUF_TRANS_COND_VALLEY) || \
+ ((x) == TMRA_BUF_TRANS_COND_PEAK_VALLEY))
+
+#define IS_TMRA_PWM_START_POLARITY(x) \
+( ((x) == TMRA_PWM_LOW) || \
+ ((x) == TMRA_PWM_HIGH) || \
+ ((x) == TMRA_PWM_HOLD))
+
+#define IS_TMRA_PWM_STOP_POLARITY(x) \
+( ((x) == TMRA_PWM_LOW) || \
+ ((x) == TMRA_PWM_HIGH) || \
+ ((x) == TMRA_PWM_HOLD))
+
+#define IS_TMRA_PWM_CMP_POLARITY(x) \
+( ((x) == TMRA_PWM_LOW) || \
+ ((x) == TMRA_PWM_HIGH) || \
+ ((x) == TMRA_PWM_HOLD) || \
+ ((x) == TMRA_PWM_INVT))
+
+#define IS_TMRA_PWM_PERIOD_POLARITY(x) \
+( ((x) == TMRA_PWM_LOW) || \
+ ((x) == TMRA_PWM_HIGH) || \
+ ((x) == TMRA_PWM_HOLD) || \
+ ((x) == TMRA_PWM_INVT))
+
+#define IS_TMRA_PWM_FORCE_POLARITY(x) \
+( ((x) == TMRA_PWM_FORCE_INVD) || \
+ ((x) == TMRA_PWM_FORCE_LOW) || \
+ ((x) == TMRA_PWM_FORCE_HIGH))
+
+#define IS_TMRA_PWM_POLARITY(st, pol) \
+( (((st) == TMRA_CNT_STAT_START) && IS_TMRA_PWM_START_POLARITY(pol)) || \
+ (((st) == TMRA_CNT_STAT_STOP) && IS_TMRA_PWM_STOP_POLARITY(pol)) || \
+ (((st) == TMRA_CNT_STAT_MATCH_CMP) && IS_TMRA_PWM_CMP_POLARITY(pol)) || \
+ (((st) == TMRA_CNT_STAT_MATCH_PERIOD) && IS_TMRA_PWM_PERIOD_POLARITY(pol)))
+
+#define IS_TMRA_START_COND(x) IS_TMRA_BIT_MASK((x), TMRA_START_COND_ALL)
+
+#define IS_TMRA_STOP_COND(x) IS_TMRA_BIT_MASK((x), TMRA_STOP_COND_ALL)
+
+#define IS_TMRA_CLR_COND(x) IS_TMRA_BIT_MASK((x), TMRA_CLR_COND_ALL)
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TMRA_Miscellaneous_Macros TMRA Miscellaneous Macros
+ * @{
+ */
+#define TMRA_PIN_PWM_OFFSET (3U)
+
+#define TMRA_CH_NUM (4U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup TMRA_Global_Functions TMRA Global Functions
+ * @{
+ */
+/**
+ * @brief Initializes the specified TMRA peripheral according to the specified parameters
+ * in the structure stc_tmra_init_t
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] pstcTmraInit Pointer to a stc_tmra_init_t structure value that
+ * contains the configuration information for the TMRA.
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_INVD_PARAM: pstcTmraInit == NULL.
+ */
+int32_t TMRA_Init(CM_TMRA_TypeDef *TMRAx, const stc_tmra_init_t *pstcTmraInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ DDL_ASSERT(IS_TMRA_UNIT(TMRAx));
+ if (pstcTmraInit != NULL) {
+ DDL_ASSERT(IS_TMRA_CNT_SRC(pstcTmraInit->u8CountSrc));
+
+ if (pstcTmraInit->u8CountSrc == TMRA_CNT_SRC_SW) {
+ DDL_ASSERT(IS_TMRA_MD(pstcTmraInit->sw_count.u8CountMode));
+ DDL_ASSERT(IS_TMRA_DIR(pstcTmraInit->sw_count.u8CountDir));
+ DDL_ASSERT(IS_TMRA_CLK_DIV(pstcTmraInit->sw_count.u8ClockDiv));
+
+ WRITE_REG8(TMRAx->BCSTRL, pstcTmraInit->sw_count.u8CountMode | \
+ pstcTmraInit->sw_count.u8CountDir | \
+ pstcTmraInit->sw_count.u8ClockDiv);
+ } else {
+ DDL_ASSERT(IS_TMRA_CNT_UP_COND(pstcTmraInit->hw_count.u16CountUpCond) || \
+ (pstcTmraInit->hw_count.u16CountUpCond == TMRA_CNT_UP_COND_INVD));
+ DDL_ASSERT(IS_TMRA_CNT_DOWN_COND(pstcTmraInit->hw_count.u16CountDownCond) || \
+ (pstcTmraInit->hw_count.u16CountDownCond == TMRA_CNT_DOWN_COND_INVD));
+ WRITE_REG16(TMRAx->HCUPR, pstcTmraInit->hw_count.u16CountUpCond);
+ WRITE_REG16(TMRAx->HCDOR, pstcTmraInit->hw_count.u16CountDownCond);
+ }
+
+ /* Counter reload */
+ DDL_ASSERT(IS_TMRA_CNT_RELOAD(pstcTmraInit->u8CountReload));
+ WRITE_REG8(TMRAx->BCSTRH, pstcTmraInit->u8CountReload);
+
+ /* Specifies period value. */
+ TMRA_SetPeriodValue(TMRAx, pstcTmraInit->u32PeriodValue);
+
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set a default value for the TMRA initialization structure.
+ * @param [out] pstcTmraInit Pointer to a stc_tmra_init_t structure value that
+ * contains the configuration information for the TMRA.
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_INVD_PARAM: pstcTmraInit == NULL.
+ */
+int32_t TMRA_StructInit(stc_tmra_init_t *pstcTmraInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (pstcTmraInit != NULL) {
+ pstcTmraInit->u8CountSrc = TMRA_CNT_SRC_SW;
+ pstcTmraInit->sw_count.u8ClockDiv = TMRA_CLK_DIV1;
+ pstcTmraInit->sw_count.u8CountMode = TMRA_MD_SAWTOOTH;
+ pstcTmraInit->sw_count.u8CountDir = TMRA_DIR_UP;
+ pstcTmraInit->hw_count.u16CountUpCond = TMRA_CNT_UP_COND_INVD;
+ pstcTmraInit->hw_count.u16CountDownCond = TMRA_CNT_DOWN_COND_INVD;
+ pstcTmraInit->u32PeriodValue = (TMRA_REG_TYPE)0xFFFFFFFFUL;
+ pstcTmraInit->u8CountReload = TMRA_CNT_RELOAD_ENABLE;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Specifies the counting mode for the specified TMRA unit.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u8Mode Count mode.
+ * This parameter can be a value of @ref TMRA_Count_Mode
+ * @arg TMRA_MD_SAWTOOTH: Count mode is sawtooth wave.
+ * @arg TMRA_MD_TRIANGLE: Count mode is triangle wave.
+ * @retval None
+ */
+void TMRA_SetCountMode(CM_TMRA_TypeDef *TMRAx, uint8_t u8Mode)
+{
+ DDL_ASSERT(IS_TMRA_UNIT(TMRAx));
+ DDL_ASSERT(IS_TMRA_MD(u8Mode));
+ MODIFY_REG8(TMRAx->BCSTRL, TMRA_BCSTRL_MODE, u8Mode);
+}
+
+/**
+ * @brief Specifies the counting direction for the specified TMRA unit.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u8Dir Count direction.
+ * This parameter can be a value of @ref TMRA_Count_Dir
+ * @arg TMRA_DIR_DOWN: TMRA count down.
+ * @arg TMRA_DIR_UP: TMRA count up.
+ * @retval None
+ */
+void TMRA_SetCountDir(CM_TMRA_TypeDef *TMRAx, uint8_t u8Dir)
+{
+ DDL_ASSERT(IS_TMRA_UNIT(TMRAx));
+ DDL_ASSERT(IS_TMRA_DIR(u8Dir));
+ MODIFY_REG8(TMRAx->BCSTRL, TMRA_BCSTRL_DIR, u8Dir);
+}
+
+/**
+ * @brief Specifies the clock divider for the specified TMRA unit.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u8Div Clock divider.
+ * This parameter can be a value of @ref TMRA_Clock_Divider
+ * @retval None
+ */
+void TMRA_SetClockDiv(CM_TMRA_TypeDef *TMRAx, uint8_t u8Div)
+{
+ DDL_ASSERT(IS_TMRA_UNIT(TMRAx));
+ DDL_ASSERT(IS_TMRA_CLK_DIV(u8Div));
+ MODIFY_REG8(TMRAx->BCSTRL, TMRA_BCSTRL_CKDIV, u8Div);
+}
+
+/**
+ * @brief Enable or disable the specified hardware count up condition.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u16Cond Hardware count up condition.
+ * This parameter can be values of @ref TMRA_Hard_Count_Up_Condition
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMRA_HWCountUpCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_TMRA_UNIT(TMRAx));
+ DDL_ASSERT(IS_TMRA_CNT_UP_COND(u16Cond));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (enNewState == ENABLE) {
+ SET_REG16_BIT(TMRAx->HCUPR, u16Cond);
+ } else {
+ CLR_REG16_BIT(TMRAx->HCUPR, u16Cond);
+ }
+}
+
+/**
+ * @brief Enable or disable the specified hardware count down condition.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u16Cond Hardware count down condition.
+ * This parameter can be values of @ref TMRA_Hard_Count_Down_Condition
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMRA_HWCountDownCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_TMRA_UNIT(TMRAx));
+ DDL_ASSERT(IS_TMRA_CNT_DOWN_COND(u16Cond));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (enNewState == ENABLE) {
+ SET_REG16_BIT(TMRAx->HCDOR, u16Cond);
+ } else {
+ CLR_REG16_BIT(TMRAx->HCDOR, u16Cond);
+ }
+}
+
+/**
+ * @brief Specifies function mode of TMRA.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u16Func Function mode of TMRA.
+ * This parameter can be a value of @ref TMRA_Function_Mode
+ * @param [in] u32Ch TMRA channel.
+ * This parameter can be a value of @ref TMRA_Channel
+ * @retval None
+ */
+void TMRA_SetFunc(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Func)
+{
+ uint32_t u32CCONRAddr;
+
+ DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch));
+ DDL_ASSERT(IS_TMRA_FUNC(u16Func));
+
+ u32CCONRAddr = (uint32_t)&TMRAx->CCONR1 + (u32Ch * 4U);
+ MODIFY_REG16(RW_MEM16(u32CCONRAddr), TMRA_CCONR_CAPMD, u16Func);
+}
+
+/**
+ * @brief Initializes the PWM according to the specified parameters
+ * in the structure stc_tmra_pwm_init_t
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] pstcPwmInit Pointer to a stc_tmra_pwm_init_t structure value that
+ * contains the configuration information for PWM.
+ * @param [in] u32Ch TMRA channel.
+ * This parameter can be a value of @ref TMRA_Channel
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_INVD_PARAM: pstcPwmInit == NULL.
+ */
+int32_t TMRA_PWM_Init(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, const stc_tmra_pwm_init_t *pstcPwmInit)
+{
+ uint32_t u32CMPARAddr;
+ uint32_t u32PCONRAddr;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch));
+
+ if (pstcPwmInit != NULL) {
+ DDL_ASSERT(IS_TMRA_PWM_START_POLARITY(pstcPwmInit->u16StartPolarity));
+ DDL_ASSERT(IS_TMRA_PWM_STOP_POLARITY(pstcPwmInit->u16StopPolarity));
+ DDL_ASSERT(IS_TMRA_PWM_CMP_POLARITY(pstcPwmInit->u16CompareMatchPolarity));
+ DDL_ASSERT(IS_TMRA_PWM_PERIOD_POLARITY(pstcPwmInit->u16PeriodMatchPolarity));
+
+ u32Ch *= 4U;
+ u32CMPARAddr = (uint32_t)&TMRAx->CMPAR1 + u32Ch;
+ SET_VAL_BY_ADDR(u32CMPARAddr, pstcPwmInit->u32CompareValue);
+
+ u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + u32Ch;
+ RW_MEM16(u32PCONRAddr) = (uint16_t)((pstcPwmInit->u16StartPolarity << TMRA_PCONR_STAC_POS) | \
+ (pstcPwmInit->u16StopPolarity << TMRA_PCONR_STPC_POS) | \
+ (pstcPwmInit->u16CompareMatchPolarity << TMRA_PCONR_CMPC_POS) | \
+ (pstcPwmInit->u16PeriodMatchPolarity << TMRA_PCONR_PERC_POS));
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set a default value for the PWM initialization structure.
+ * @param [out] pstcPwmInit Pointer to a stc_tmra_pwm_init_t structure value that
+ * contains the configuration information for PWM.
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_INVD_PARAM: pstcPwmInit == NULL.
+ */
+int32_t TMRA_PWM_StructInit(stc_tmra_pwm_init_t *pstcPwmInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (pstcPwmInit != NULL) {
+ pstcPwmInit->u32CompareValue = TMRA_REG_VALUE_MAX;
+ pstcPwmInit->u16StartPolarity = TMRA_PWM_HIGH;
+ pstcPwmInit->u16StopPolarity = TMRA_PWM_LOW;
+ pstcPwmInit->u16CompareMatchPolarity = TMRA_PWM_INVT;
+ pstcPwmInit->u16PeriodMatchPolarity = TMRA_PWM_INVT;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Enable or disable the PWM ouput of the specified channel.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u32Ch TMRA channel.
+ * This parameter can be a value of @ref TMRA_Channel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMRA_PWM_OutputCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState)
+{
+ uint32_t u32PCONRAddr;
+
+ DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + (u32Ch * 4U);
+ WRITE_REG32(PERIPH_BIT_BAND(u32PCONRAddr, TMRA_PCONR_OUTEN_POS), enNewState);
+}
+
+/**
+ * @brief Specifies the ouput polarity of the PWM at the specified state of counter.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u32Ch TMRA channel.
+ * This parameter can be a value @ref TMRA_Channel
+ * @param [in] u8CountState TMRA counter state.
+ * This parameter can be a value @ref TMRA_Counter_State
+ * @param [in] u16Polarity The polarity of PWM.
+ * This parameter can be a value @ref TMRA_PWM_Polarity
+ * @retval None
+ * @note The polarity(high or low) when counting start is only valid when the clock is not divided(BCSTRL.CKDIV == 0).
+ */
+void TMRA_PWM_SetPolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint8_t u8CountState, uint16_t u16Polarity)
+{
+ uint32_t u32PCONRAddr;
+
+ DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch));
+ DDL_ASSERT(IS_TMRA_PWM_POLARITY(u8CountState, u16Polarity));
+
+ u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + (u32Ch * 4U);
+ MODIFY_REG16(RW_MEM16(u32PCONRAddr),
+ (uint16_t)TMRA_PWM_POLARITY_MASK << (u8CountState * 2U),
+ u16Polarity << (u8CountState * 2U));
+}
+
+/**
+ * @brief Specifies the force polarity of the PWM.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u32Ch TMRA channel.
+ * This parameter can be a value @ref TMRA_Channel
+ * @param [in] u16Polarity The force polarity of PWM.
+ * This parameter can be a value @ref TMRA_PWM_Force_Polarity
+ * @retval None
+ */
+void TMRA_PWM_SetForcePolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Polarity)
+{
+ uint32_t u32PCONRAddr;
+
+ DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch));
+ DDL_ASSERT(IS_TMRA_PWM_FORCE_POLARITY(u16Polarity));
+
+ u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + (u32Ch * 4U);
+ MODIFY_REG16(RW_MEM16(u32PCONRAddr), TMRA_PCONR_FORC, u16Polarity);
+}
+
+/**
+ * @brief Enable or disable the specified capture condition.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u32Ch TMRA channel.
+ * This parameter can be a value @ref TMRA_Channel
+ * @param [in] u16Cond The capture condition.
+ * This parameter can be a value @ref TMRA_Capture_Cond
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMRA_HWCaptureCondCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState)
+{
+ uint32_t u32CCONRAddr;
+
+ DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch));
+ DDL_ASSERT(IS_TMRA_CAPT_COND(u16Cond));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+#if defined __DEBUG
+ if ((u16Cond & (TMRA_CAPT_COND_TRIG_RISING | TMRA_CAPT_COND_TRIG_FALLING)) != 0U) {
+ DDL_ASSERT(u32Ch == TMRA_CH4);
+ }
+#endif
+ u32CCONRAddr = (uint32_t)&TMRAx->CCONR1 + (u32Ch * 4U);
+ if (enNewState == ENABLE) {
+ SET_REG16_BIT(RW_MEM16(u32CCONRAddr), u16Cond);
+ } else {
+ CLR_REG16_BIT(RW_MEM16(u32CCONRAddr), u16Cond);
+ }
+}
+
+/**
+ * @brief Enable or disable hardware start condition.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u16Cond Hardware start condition.
+ * This parameter can be a value @ref TMRA_Hardware_Start_Condition
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMRA_HWStartCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_TMRA_UNIT(TMRAx));
+ DDL_ASSERT(IS_TMRA_START_COND(u16Cond));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (enNewState == ENABLE) {
+ SET_REG16_BIT(TMRAx->HCONR, u16Cond);
+ } else {
+ CLR_REG16_BIT(TMRAx->HCONR, u16Cond);
+ }
+}
+
+/**
+ * @brief Enable or disable hardware stop condition.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u16Cond Hardware stop condition.
+ * This parameter can be a value @ref TMRA_Hardware_Stop_Condition
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMRA_HWStopCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_TMRA_UNIT(TMRAx));
+ DDL_ASSERT(IS_TMRA_STOP_COND(u16Cond));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (enNewState == ENABLE) {
+ SET_REG16_BIT(TMRAx->HCONR, u16Cond);
+ } else {
+ CLR_REG16_BIT(TMRAx->HCONR, u16Cond);
+ }
+}
+
+/**
+ * @brief Enable or disable hardware clear condition.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u16Cond Hardware clear condition.
+ * This parameter can be a value @ref TMRA_Hardware_Clear_Condition
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMRA_HWClearCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_TMRA_UNIT(TMRAx));
+ DDL_ASSERT(IS_TMRA_CLR_COND(u16Cond));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ if (enNewState == ENABLE) {
+ SET_REG16_BIT(TMRAx->HCONR, u16Cond);
+ } else {
+ CLR_REG16_BIT(TMRAx->HCONR, u16Cond);
+ }
+}
+
+/**
+ * @brief Specifies the clock divider of filter.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u32Pin The pin with filter of TMRA.
+ * This parameter can be a value of @ref TMRA_Filter_Pin
+ * @param [in] u16Div The clock source divider of the filter.
+ * This parameter can be a value of @ref TMRA_Filter_Clock_Divider
+ * @arg TMRA_FILTER_CLK_DIV1: The filter clock is the clock of timerA / 1.
+ * @arg TMRA_FILTER_CLK_DIV4: The filter clock is the clock of timerA / 4.
+ * @arg TMRA_FILTER_CLK_DIV16: The filter clock is the clock of timerA / 16.
+ * @arg TMRA_FILTER_CLK_DIV64: The filter clock is the clock of timerA / 64.
+ * @retval None
+ */
+void TMRA_SetFilterClockDiv(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, uint16_t u16Div)
+{
+ uint32_t u32Ch;
+ uint32_t u32CCONRAddr;
+ const uint8_t au8Offset[] = {
+ TMRA_FCONR_NOFICKTG_POS, TMRA_FCONR_NOFICKCA_POS, TMRA_FCONR_NOFICKCB_POS,
+ };
+
+ DDL_ASSERT(IS_TMRA_UNIT_FPIN(TMRAx, u32Pin));
+ DDL_ASSERT(IS_TMRA_FILTER_CLK_DIV(u16Div));
+
+ if (u32Pin < TMRA_PIN_PWM_OFFSET) {
+ MODIFY_REG16(TMRAx->FCONR,
+ (TMRA_FCONR_FILTER_CLK_MASK << au8Offset[u32Pin]),
+ (u16Div << au8Offset[u32Pin]));
+ } else {
+ u32Ch = u32Pin - TMRA_PIN_PWM_OFFSET;
+ u32CCONRAddr = (uint32_t)&TMRAx->CCONR1 + u32Ch * 4U;
+ MODIFY_REG16(RW_MEM16(u32CCONRAddr),
+ TMRA_CCONR_FILTER_CLK_MASK,
+ (u16Div << TMRA_CCONR_NOFICKCP_POS));
+ }
+}
+
+/**
+ * @brief Enable or disable the filter function of the specified TMRA input pin.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u32Pin The pin with filter of TMRA.
+ * This parameter can be values of @ref TMRA_Filter_Pin
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMRA_FilterCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, en_functional_state_t enNewState)
+{
+ uint8_t u8EnPos;
+ uint32_t u32Ch;
+ uint32_t u32RegAddr;
+ const uint8_t au8Offset[] = {
+ TMRA_FCONR_NOFIENTG_POS, TMRA_FCONR_NOFIENCA_POS, TMRA_FCONR_NOFIENCB_POS,
+ };
+
+ DDL_ASSERT(IS_TMRA_UNIT_FPIN(TMRAx, u32Pin));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (u32Pin < TMRA_PIN_PWM_OFFSET) {
+ u32RegAddr = (uint32_t)&TMRAx->FCONR;
+ u8EnPos = au8Offset[u32Pin];
+ } else {
+ u32Ch = u32Pin - TMRA_PIN_PWM_OFFSET;
+ u32RegAddr = (uint32_t)&TMRAx->CCONR1 + u32Ch * 4U;
+ u8EnPos = TMRA_CCONR_NOFIENCP_POS;
+ }
+ WRITE_REG32(PERIPH_BIT_BAND(u32RegAddr, u8EnPos), enNewState);
+}
+
+/**
+ * @brief De-initializes the TMRA peripheral. Reset all registers of the specified TMRA unit.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @retval None
+ */
+void TMRA_DeInit(CM_TMRA_TypeDef *TMRAx)
+{
+ uint32_t i;
+ uint32_t u32ChNum = TMRA_CH_NUM;
+ uint32_t u32AddrOffset;
+ uint32_t u32PERARAddr;
+ uint32_t u32CNTERAddr;
+ uint32_t u32CMPARAddr;
+ uint32_t u32CCONRAddr;
+ uint32_t u32PCONRAddr;
+
+ DDL_ASSERT(IS_TMRA_UNIT(TMRAx));
+
+ u32PERARAddr = (uint32_t)&TMRAx->PERAR;
+ u32CNTERAddr = (uint32_t)&TMRAx->CNTER;
+ u32CMPARAddr = (uint32_t)&TMRAx->CMPAR1;
+ u32CCONRAddr = (uint32_t)&TMRAx->CCONR1;
+ u32PCONRAddr = (uint32_t)&TMRAx->PCONR1;
+
+ for (i = 0U; i < u32ChNum; i++) {
+ u32AddrOffset = i * 4U;
+ RW_MEM16(u32CMPARAddr + u32AddrOffset) = 0xFFFFU;
+ RW_MEM16(u32CCONRAddr + u32AddrOffset) = 0x0U;
+ RW_MEM16(u32PCONRAddr + u32AddrOffset) = 0x0U;
+ }
+
+ SET_VAL_BY_ADDR(u32PERARAddr, 0xFFFFFFFFUL);
+ SET_VAL_BY_ADDR(u32CNTERAddr, 0x0U);
+ WRITE_REG8(TMRAx->BCSTRL, 0x2U);
+ WRITE_REG8(TMRAx->BCSTRH, 0x0U);
+ WRITE_REG16(TMRAx->ICONR, 0x0U);
+ WRITE_REG16(TMRAx->ECONR, 0x0U);
+ WRITE_REG16(TMRAx->FCONR, 0x0U);
+ WRITE_REG16(TMRAx->STFLR, 0x0U);
+ WRITE_REG16(TMRAx->HCONR, 0x0U);
+ WRITE_REG16(TMRAx->HCUPR, 0x0U);
+ WRITE_REG16(TMRAx->HCDOR, 0x0U);
+ WRITE_REG16(TMRAx->BCONR1, 0x0U);
+ WRITE_REG16(TMRAx->BCONR2, 0x0U);
+}
+
+/**
+ * @brief Get the counting direction of the specified TMRA unit.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @retval An uint8_t type value of counting direction.
+ * -TMRA_DIR_DOWN: TMRA count down.
+ * -TMRA_DIR_UP: TMRA count up.
+ */
+uint8_t TMRA_GetCountDir(const CM_TMRA_TypeDef *TMRAx)
+{
+ DDL_ASSERT(IS_TMRA_UNIT(TMRAx));
+ return READ_REG8_BIT(TMRAx->BCSTRL, TMRA_BCSTRL_DIR);
+}
+
+/**
+ * @brief Set period value.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u32Value The period value to be set.
+ * This parameter can be a number between:
+ * 0UL and 0xFFFFFFFFUL for 32-bit TimerA units.
+ * 0UL and 0xFFFFUL for 16-bit TimerA units.
+ * @retval None
+ */
+void TMRA_SetPeriodValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value)
+{
+ uint32_t u32PERARAddr;
+
+ DDL_ASSERT(IS_TMRA_UNIT(TMRAx));
+ u32PERARAddr = (uint32_t)&TMRAx->PERAR;
+ SET_VAL_BY_ADDR(u32PERARAddr, u32Value);
+}
+
+/**
+ * @brief Get period value.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @retval An uint32_t type type value of period value between:
+ * - 0UL and 0xFFFFFFFFUL for 32-bit TimerA units.
+ * - 0UL and 0xFFFFUL for 16-bit TimerA units.
+ */
+uint32_t TMRA_GetPeriodValue(const CM_TMRA_TypeDef *TMRAx)
+{
+ DDL_ASSERT(IS_TMRA_UNIT(TMRAx));
+ return (TMRAx->PERAR);
+}
+
+/**
+ * @brief Set general counter value.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u32Value The general counter value to be set.
+ * This parameter can be a number between:
+ * 0UL and 0xFFFFFFFFUL for 32-bit TimerA units.
+ * 0UL and 0xFFFFUL for 16-bit TimerA units.
+ * @retval None
+ */
+void TMRA_SetCountValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value)
+{
+ uint32_t u32CNTERAddr;
+
+ DDL_ASSERT(IS_TMRA_UNIT(TMRAx));
+ u32CNTERAddr = (uint32_t)&TMRAx->CNTER;
+ SET_VAL_BY_ADDR(u32CNTERAddr, u32Value);
+}
+
+/**
+ * @brief Get general counter value.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @retval An uint32_t type type value of counter value between:
+ * - 0UL and 0xFFFFFFFFUL for 32-bit TimerA units.
+ * - 0UL and 0xFFFFUL for 16-bit TimerA units.
+ */
+uint32_t TMRA_GetCountValue(const CM_TMRA_TypeDef *TMRAx)
+{
+ DDL_ASSERT(IS_TMRA_UNIT(TMRAx));
+ return (TMRAx->CNTER);
+}
+
+/**
+ * @brief Set comparison value.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u32Ch TMRA channel.
+ * This parameter can be a value of @ref TMRA_Channel
+ * @param [in] u32Value The comparison value to be set.
+ * This parameter can be a number between:
+ * 0UL and 0xFFFFFFFFUL for 32-bit TimerA units.
+ * 0UL and 0xFFFFUL for 16-bit TimerA units.
+ * @retval None
+ */
+void TMRA_SetCompareValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint32_t u32Value)
+{
+ uint32_t u32CMPARAddr;
+
+ DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch));
+
+ u32CMPARAddr = (uint32_t)&TMRAx->CMPAR1 + u32Ch * 4U;
+ SET_VAL_BY_ADDR(u32CMPARAddr, u32Value);
+}
+
+/**
+ * @brief Get comparison value.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u32Ch TMRA channel.
+ * This parameter can be a value of @ref TMRA_Channel
+ * @retval An uint32_t type type value of comparison value value between:
+ * - 0UL and 0xFFFFFFFFUL for 32-bit TimerA units.
+ * - 0UL and 0xFFFFUL for 16-bit TimerA units.
+ */
+uint32_t TMRA_GetCompareValue(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch)
+{
+ uint32_t u32CMPARAddr;
+
+ DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch));
+
+ u32CMPARAddr = (uint32_t)&TMRAx->CMPAR1 + u32Ch * 4U;
+ return GET_VAL_BY_ADDR(u32CMPARAddr);
+}
+
+/**
+ * @brief Enable or disable synchronous-start. When an even unit enables synchronous-start function,
+ * start the symmetric odd unit can start the even unit at the same time.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x(x is an even number)
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMRA_SyncStartCmd(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState)
+{
+ uint32_t u32Addr;
+
+ DDL_ASSERT(IS_TMRA_SYNC_UNIT(TMRAx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u32Addr = (uint32_t)&TMRAx->BCSTRL;
+ WRITE_REG32(PERIPH_BIT_BAND(u32Addr, TMRA_BCSTRL_SYNST_POS), enNewState);
+}
+
+/**
+ * @brief Enable or disable reload and continue counting when overflow/underflow.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMRA_CountReloadCmd(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_TMRA_UNIT(TMRAx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (enNewState == ENABLE) {
+ CLR_REG8_BIT(TMRAx->BCSTRH, TMRA_BCSTRH_OVSTP);
+ } else {
+ SET_REG8_BIT(TMRAx->BCSTRH, TMRA_BCSTRH_OVSTP);
+ }
+}
+
+/**
+ * @brief Specifies the condition of compare value buffer transmission.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u32Ch TMRA channel.
+ * This parameter can be one of the odd channels of @ref TMRA_Channel
+ * @param [in] u16Cond Buffer condition of the specified TMRA unit.
+ * This parameter can be a value of @ref TMRA_Cmp_Value_Buf_Trans_Cond
+ * @arg TMRA_BUF_TRANS_COND_OVF_UDF_CLR: This configuration value applies to non-triangular wave counting mode.
+ * When counting overflow or underflow or counting register was cleared,
+ * transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...).
+ * @arg TMRA_BUF_TRANS_COND_PEAK: In triangle wave count mode, when count reached peak,
+ * transfer CMMARm(m=2,4,6,8,...) to CMMARn(n=1,3,5,7,...).
+ * @arg TMRA_BUF_TRANS_COND_VALLEY: In triangle wave count mode, when count reached valley,
+ * transfer CMMARm(m=2,4,6,8,...) to CMMARn(n=1,3,5,7,...).
+ * @arg TMRA_BUF_TRANS_COND_PEAK_VALLEY: In triangle wave count mode, when count reached peak or valley,
+ * transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...).
+ * @retval None
+ * @note The specified condition is only valid when TMRA_BCONR.BEN is set.
+ */
+void TMRA_SetCompareBufCond(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond)
+{
+ uint32_t u32BCONRAddr;
+
+ DDL_ASSERT(IS_TMRA_UNIT(TMRAx));
+ DDL_ASSERT(IS_TMRA_CMPVAL_BUF_CH(u32Ch));
+ DDL_ASSERT(IS_TMRA_BUF_TRANS_COND(u16Cond));
+
+ u32BCONRAddr = (uint32_t)&TMRAx->BCONR1 + u32Ch * 4U;
+ MODIFY_REG16(RW_MEM16(u32BCONRAddr), TMRA_BUF_TRANS_COND_PEAK_VALLEY, u16Cond);
+}
+
+/**
+ * @brief Enable or disable compare value buffer.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u32Ch TMRA channel.
+ * This parameter can be one of the odd channels of @ref TMRA_Channel
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ * @note DO NOT set both TMRA_BCONR.BSEN and TMRA_BCONR.BEN to '1'.
+ */
+void TMRA_CompareBufCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState)
+{
+ uint32_t u32BCONRAddr;
+
+ DDL_ASSERT(IS_TMRA_UNIT(TMRAx));
+ DDL_ASSERT(IS_TMRA_CMPVAL_BUF_CH(u32Ch));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u32BCONRAddr = (uint32_t)&TMRAx->BCONR1 + u32Ch * 4U;
+
+ WRITE_REG32(PERIPH_BIT_BAND(u32BCONRAddr, TMRA_BCONR_BEN_POS), enNewState);
+}
+
+/**
+ * @brief Get the status of the specified flag.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u32Flag The status flags of TMRA.
+ * This parameter can be a value of @ref TMRA_Status_Flag
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t TMRA_GetStatus(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag)
+{
+ uint8_t u8BCSTR;
+ uint16_t u16STFLR;
+ en_flag_status_t enStatus = RESET;
+
+ DDL_ASSERT(IS_TMRA_UNIT_FLAG(TMRAx, u32Flag));
+
+ u8BCSTR = (uint8_t)(u32Flag & TMRA_BCSTRH_FLAG_MASK);
+ u16STFLR = (uint16_t)(u32Flag >> 16U);
+ u8BCSTR = READ_REG8_BIT(TMRAx->BCSTRH, u8BCSTR);
+ u16STFLR = READ_REG16_BIT(TMRAx->STFLR, u16STFLR);
+
+ if ((u8BCSTR != 0U) || (u16STFLR != 0U)) {
+ enStatus = SET;
+ }
+
+ return enStatus;
+}
+
+/**
+ * @brief Clear the status of the specified flags.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u32Flag The status flags of TMRA.
+ * This parameter can be values of @ref TMRA_Status_Flag
+ * @retval None
+ */
+void TMRA_ClearStatus(CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag)
+{
+ DDL_ASSERT(IS_TMRA_UNIT_FLAG(TMRAx, u32Flag));
+
+ CLR_REG8_BIT(TMRAx->BCSTRH, u32Flag & TMRA_BCSTRH_FLAG_MASK);
+ CLR_REG16_BIT(TMRAx->STFLR, u32Flag >> 16U);
+}
+
+/**
+ * @brief Enable of disable the specified interrupts of the specified TMRA unit.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u32IntType The interrupt type of TMRA.
+ * This parameter can be values of @ref TMRA_Interrupt_Type
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMRA_IntCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32IntType, en_functional_state_t enNewState)
+{
+ uint32_t u32BCSTRH;
+ uint32_t u32ICONR;
+
+ DDL_ASSERT(IS_TMRA_UNIT_INT(TMRAx, u32IntType));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ u32BCSTRH = u32IntType & TMRA_BCSTRH_INT_MASK;
+ u32ICONR = u32IntType >> 16U;
+ if (enNewState == ENABLE) {
+ SET_REG8_BIT(TMRAx->BCSTRH, u32BCSTRH);
+ SET_REG16_BIT(TMRAx->ICONR, u32ICONR);
+ } else {
+ CLR_REG8_BIT(TMRAx->BCSTRH, u32BCSTRH);
+ CLR_REG16_BIT(TMRAx->ICONR, u32ICONR);
+ }
+}
+
+/**
+ * @brief Enable of disable the specified event of the specified TMRA unit.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @param [in] u32EventType The event type of TMRA.
+ * This parameter can be values of @ref TMRA_Event_Type
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TMRA_EventCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32EventType, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_TMRA_CH_EVT(TMRAx, u32EventType));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (enNewState == ENABLE) {
+ SET_REG16_BIT(TMRAx->ECONR, u32EventType);
+ } else {
+ CLR_REG16_BIT(TMRAx->ECONR, u32EventType);
+ }
+}
+
+/**
+ * @brief Start the specified TMRA unit.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @retval None
+ */
+void TMRA_Start(CM_TMRA_TypeDef *TMRAx)
+{
+ DDL_ASSERT(IS_TMRA_UNIT(TMRAx));
+ SET_REG8_BIT(TMRAx->BCSTRL, TMRA_BCSTRL_START);
+}
+
+/**
+ * @brief Stop the specified TMRA unit.
+ * @param [in] TMRAx Pointer to TMRA instance register base.
+ * This parameter can be a value of the following:
+ * @arg CM_TMRA_x or CM_TMRA
+ * @retval None
+ */
+void TMRA_Stop(CM_TMRA_TypeDef *TMRAx)
+{
+ DDL_ASSERT(IS_TMRA_UNIT(TMRAx));
+ CLR_REG8_BIT(TMRAx->BCSTRL, TMRA_BCSTRL_START);
+}
+/**
+ * @}
+ */
+
+#endif /* LL_TMRA_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_trng.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_trng.c
new file mode 100644
index 0000000000..731b3f3119
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_trng.c
@@ -0,0 +1,261 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_trng.c
+ * @brief This file provides firmware functions to manage the True Random
+ * Number Generator(TRNG).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT API fixed: TRNG_Init()
+ API optimized for better random numbers: TRNG_GenerateRandom(), TRNG_GetRandom()
+ Add TRNG_Cmd,TRNG_DeInit functions and optimize TRNG_Start function
+ 2023-09-30 CDT Remove processing of discarded data in TRNG_Init()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_trng.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_TRNG TRNG
+ * @brief TRNG Driver Library
+ * @{
+ */
+
+#if (LL_TRNG_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup TRNG_Local_Macros TRNG Local Macros
+ * @{
+ */
+#define TRNG_TIMEOUT (20000UL)
+
+/**
+ * @defgroup TRNG_Check_Parameters_Validity TRNG Check Parameters Validity
+ * @{
+ */
+#define IS_TRNG_SHIFT_CNT(x) \
+( ((x) == TRNG_SHIFT_CNT32) || \
+ ((x) == TRNG_SHIFT_CNT64) || \
+ ((x) == TRNG_SHIFT_CNT128) || \
+ ((x) == TRNG_SHIFT_CNT256))
+
+#define IS_RNG_RELOAD_INIT_VAL_EN(x) \
+( ((x) == TRNG_RELOAD_INIT_VAL_ENABLE) || \
+ ((x) == TRNG_RELOAD_INIT_VAL_DISABLE))
+
+#define IS_TRNG_PWC_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1)
+
+/* TRNG reset timeout */
+#define TRNG_RMU_TIMEOUT (100UL)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup TRNG_Global_Functions TRNG Global Functions
+ * @{
+ */
+
+/**
+ * @brief De-initializes TRNG.
+ * @param None
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_TIMEOUT: Works timeout.
+ */
+int32_t TRNG_DeInit(void)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t u32TimeOut = 0U;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_TRNG_PWC_UNLOCKED());
+
+ CLR_REG32_BIT(CM_RMU->FRST0, RMU_FRST0_TRNG);
+ /* Ensure reset procedure is completed */
+ while (RMU_FRST0_TRNG != READ_REG32_BIT(CM_RMU->FRST0, RMU_FRST0_TRNG)) {
+ u32TimeOut++;
+ if (u32TimeOut > TRNG_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initializes TRNG.
+ * @param [in] u32ShiftCount TRNG shift control. This parameter can be a value of @ref TRNG_Shift_Ctrl
+ * @arg TRNG_SHIFT_CNT32: Shift 32 times when capturing random noise.
+ * @arg TRNG_SHIFT_CNT64: Shift 64 times when capturing random noise.
+ * @arg TRNG_SHIFT_CNT128: Shift 128 times when capturing random noise.
+ * @arg TRNG_SHIFT_CNT256: Shift 256 times when capturing random noise.
+ * @param [in] u32ReloadInitValueEn Enable or disable load new initial value.
+ * This parameter can be a value of @ref TRNG_Reload_Init_Value
+ * @arg TRNG_RELOAD_INIT_VAL_ENABLE: Enable load new initial value.
+ * @arg TRNG_RELOAD_INIT_VAL_DISABLE: Disable load new initial value.
+ * @retval None
+ */
+void TRNG_Init(uint32_t u32ShiftCount, uint32_t u32ReloadInitValueEn)
+{
+
+ /* MRC is required */
+ DDL_ASSERT(READ_REG32(bCM_CMU->MRCCR_b.MRCSTP) == 0U);
+ DDL_ASSERT(IS_TRNG_SHIFT_CNT(u32ShiftCount));
+ DDL_ASSERT(IS_RNG_RELOAD_INIT_VAL_EN(u32ReloadInitValueEn));
+ WRITE_REG32(CM_TRNG->MR, u32ShiftCount | u32ReloadInitValueEn);
+}
+
+/**
+ * @brief Start TRNG and get random number.
+ * @param [out] pu32Random The destination buffer to store the random number.
+ * @param [in] u32RandomLen The size(in word) of the destination buffer.
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_TIMEOUT: Works timeout.
+ * - LL_ERR_INVD_PARAM: pu32Random == NULL or u8RandomLen == 0
+ */
+int32_t TRNG_GenerateRandom(uint32_t *pu32Random, uint32_t u32RandomLen)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ __IO uint32_t u32TimeCount = TRNG_TIMEOUT;
+ uint32_t u32Count = 0U;
+
+ if ((pu32Random != NULL) && (u32RandomLen > 0U)) {
+ while (u32RandomLen != u32Count) {
+ /* Start TRNG */
+ WRITE_REG32(bCM_TRNG->CR_b.RUN, 1U);
+ /* Wait generating done. */
+ i32Ret = LL_ERR_TIMEOUT;
+ while (u32TimeCount-- != 0UL) {
+ if (READ_REG32(bCM_TRNG->CR_b.RUN) == 0U) {
+ i32Ret = LL_OK;
+ break;
+ }
+ }
+
+ if (i32Ret == LL_OK) {
+ /* Get the random number. */
+ pu32Random[u32Count++] = READ_REG32(CM_TRNG->DR0);
+ if (u32Count < u32RandomLen) {
+ pu32Random[u32Count++] = READ_REG32(CM_TRNG->DR1);
+ }
+ }
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Start TRNG
+ * @param None
+ * @retval None
+ */
+void TRNG_Start(void)
+{
+ WRITE_REG32(bCM_TRNG->CR_b.RUN, 1U);
+}
+
+/**
+ * @brief TRNG function enable or disable.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void TRNG_Cmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(CM_TRNG->CR, TRNG_CR_EN);
+ } else {
+ CLR_REG32_BIT(CM_TRNG->CR, TRNG_CR_EN);
+ }
+}
+
+/**
+ * @brief Get random number.
+ * @param [out] pu32Random The destination buffer to store the random number.
+ * @param [in] u8RandomLen The size(in word) of the destination buffer.(MAX = 2U)
+ * @retval int32_t:
+ * - LL_OK: No error occurred.
+ * - LL_ERR_INVD_PARAM: pu32Random == NULL or u8RandomLen == 0
+ */
+int32_t TRNG_GetRandom(uint32_t *pu32Random, uint8_t u8RandomLen)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if ((pu32Random != NULL) && (u8RandomLen > 0U)) {
+ /* Get the random number. */
+ pu32Random[0U] = READ_REG32(CM_TRNG->DR0);
+ if (u8RandomLen > 1U) {
+ pu32Random[1U] = READ_REG32(CM_TRNG->DR1);
+ }
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_TRNG_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_usart.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_usart.c
new file mode 100644
index 0000000000..9b6c200fd0
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_usart.c
@@ -0,0 +1,2179 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_usart.c
+ * @brief This file provides firmware functions to manage the USART(Universal
+ * Synchronous/Asynchronous Receiver Transmitter).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Add function note: USART_FuncCmd
+ Modify typo
+ Round off baudrate fraction division
+ Split register USART_DR to USART_RDR and USART_TDR
+ Modify USART_SetTransType parameter: u32Type -> u16Type
+ Delete function: USART_GetUsartClockDiv
+ Fix MISRAC2012 warning: USART_GetUsartClockFreq
+ Code Refine
+ 2023-09-30 CDT Modify USART_SmartCard_Init() for stc_usart_smartcard_init_t has modified(u32StopBit has removed)
+ Fix bug: did not enable MP while USART_MultiProcessor_Init()
+ 2023-12-15 CDT Add API USART_GetFuncState()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_usart.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_USART USART
+ * @brief USART Driver Library
+ * @{
+ */
+
+#if (LL_USART_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/**
+ * @defgroup USART_Local_Types USART Local Types
+ * @{
+ */
+
+/**
+ * @brief usart BRR division calculate structure definition
+ */
+typedef struct {
+ uint32_t u32UsartClock; /*!< USART clock. */
+ uint32_t u32Baudrate; /*!< USART baudrate. */
+ uint32_t u32Integer; /*!< Pointer to BRR integer division value. */
+ uint32_t u32Fraction; /*!< Pointer to BRR fraction division value. */
+ float32_t f32Error; /*!< E(%) baudrate error rate. */
+} stc_usart_brr_t;
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup USART_Local_Macros USART Local Macros
+ * @{
+ */
+
+/**
+ * @defgroup USART_Check_Parameters_Validity USART Check Parameters Validity
+ * @{
+ */
+
+/**
+ * @defgroup USART_Check_Parameters_Validity_Unit USART Check Parameters Validity Unit
+ * @{
+ */
+#define IS_USART_UNIT(x) \
+( ((x) == CM_USART1) || \
+ ((x) == CM_USART2) || \
+ ((x) == CM_USART3) || \
+ ((x) == CM_USART4) || \
+ ((x) == CM_USART5) || \
+ ((x) == CM_USART6))
+#define IS_USART_SMARTCARD_UNIT(x) \
+( ((x) == CM_USART1) || \
+ ((x) == CM_USART2) || \
+ ((x) == CM_USART4) || \
+ ((x) == CM_USART5))
+#define IS_USART_LIN_UNIT(x) \
+( ((x) == CM_USART3) || \
+ ((x) == CM_USART6))
+#define IS_USART_STOP_MD_UNIT(x) ((x) == CM_USART1)
+#define IS_USART_TIMEOUT_UNIT(x) \
+( ((x) == CM_USART1) || \
+ ((x) == CM_USART2) || \
+ ((x) == CM_USART4) || \
+ ((x) == CM_USART5))
+/**
+ * @}
+ */
+
+#define IS_USART_FUNC(x) \
+( ((x) != 0UL) && \
+ (((x) | USART_FUNC_ALL) == USART_FUNC_ALL))
+
+#define IS_USART_FLAG(x) \
+( ((x) != 0UL) && \
+ (((x) | USART_FLAG_ALL) == USART_FLAG_ALL))
+
+#define IS_USART_TRANS_TYPE(x) \
+( ((x) == USART_TRANS_ID) || \
+ ((x) == USART_TRANS_DATA))
+
+#define IS_USART_PARITY(x) \
+( ((x) == USART_PARITY_ODD) || \
+ ((x) == USART_PARITY_EVEN) || \
+ ((x) == USART_PARITY_NONE))
+
+#define IS_USART_DATA_WIDTH(x) \
+( ((x) == USART_DATA_WIDTH_8BIT) || \
+ ((x) == USART_DATA_WIDTH_9BIT))
+
+#define IS_USART_STOPBIT(x) \
+( ((x) == USART_STOPBIT_1BIT) || \
+ ((x) == USART_STOPBIT_2BIT))
+
+#define IS_USART_FIRST_BIT(x) \
+( ((x) == USART_FIRST_BIT_MSB) || \
+ ((x) == USART_FIRST_BIT_LSB))
+
+#define IS_USART_OVER_SAMPLE_BIT(x) \
+( ((x) == USART_OVER_SAMPLE_8BIT) || \
+ ((x) == USART_OVER_SAMPLE_16BIT))
+
+#define IS_USART_START_BIT_POLARITY(x) \
+( ((x) == USART_START_BIT_LOW) || \
+ ((x) == USART_START_BIT_FALLING))
+
+#define IS_USART_CLK_SRC(x) \
+( ((x) == USART_CLK_SRC_EXTCLK) || \
+ ((x) == USART_CLK_SRC_INTERNCLK))
+
+#define IS_USART_CK_OUTPUT(x) \
+( ((x) == USART_CK_OUTPUT_ENABLE) || \
+ ((x) == USART_CK_OUTPUT_DISABLE))
+
+#define IS_USART_CLK_DIV(x) ((x) <= USART_CLK_DIV_MAX)
+
+#define IS_USART_DATA(x) ((x) <= 0x01FFUL)
+
+/**
+ * @defgroup USART_Check_Parameters_Validity_Hardware_Flow_Control USART Check Parameters Validity Hardware Flow Control
+ * @{
+ */
+#define IS_USART_HW_FLOWCTRL(x) \
+( ((x) == USART_HW_FLOWCTRL_NONE) || \
+ ((x) == USART_HW_FLOWCTRL_CTS) || \
+ ((x) == USART_HW_FLOWCTRL_RTS) || \
+ ((x) == USART_HW_FLOWCTRL_RTS_CTS))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_Check_Parameters_Validity_Smartcard_Clock USART Check Parameters Validity Smartcard Clock
+ * @{
+ */
+#define IS_USART_SMARTCARD_ETU_CLK(x) \
+( ((x) == USART_SC_ETU_CLK32) || \
+ ((x) == USART_SC_ETU_CLK64) || \
+ ((x) == USART_SC_ETU_CLK128) || \
+ ((x) == USART_SC_ETU_CLK256) || \
+ ((x) == USART_SC_ETU_CLK372))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_Check_Parameters_Validity_Stopmode_Filter USART Check Parameters Validity Stopmode Filter
+ * @{
+ */
+#define IS_USART_STOP_MD_FILTER(x) \
+( ((x) == USART_STOP_MD_FILTER_LVL1) || \
+ ((x) == USART_STOP_MD_FILTER_LVL2) || \
+ ((x) == USART_STOP_MD_FILTER_LVL3) || \
+ ((x) == USART_STOP_MD_FILTER_LVL4))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_Check_Parameters_Validity_Timeout_Function USART Check Parameters Validity Timeout Function
+ * @{
+ */
+#define IS_USART_TIMEOUT_FUNC(x, func) \
+( IS_USART_TIMEOUT_UNIT(x) || \
+ ((!IS_USART_TIMEOUT_UNIT(x)) && (((func) & (USART_RX_TIMEOUT | USART_INT_RX_TIMEOUT)) == 0UL)))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_Check_Parameters_Validity_LIN_Function USART Check Parameters Validity LIN Function
+ * @{
+ */
+#define IS_USART_LIN_FUNC(x, func) \
+( IS_USART_LIN_UNIT(x) || \
+ ((!IS_USART_LIN_UNIT(x)) && (((func) & USART_LIN_FUNC_MASK) == 0UL)))
+
+#define IS_USART_LIN_BMC_CLK_DIV(x) \
+( ((x) == USART_LIN_BMC_CLK_DIV1) || \
+ ((x) == USART_LIN_BMC_CLK_DIV2) || \
+ ((x) == USART_LIN_BMC_CLK_DIV4) || \
+ ((x) == USART_LIN_BMC_CLK_DIV8))
+
+#define IS_USART_LIN_SEND_BREAK_MD(x) \
+( ((x) == USART_LIN_SEND_BREAK_MD_SBK) || \
+ ((x) == USART_LIN_SEND_BREAK_MD_TDR))
+
+#define IS_USART_LIN_DETECT_BREAK_LEN(x) \
+( ((x) == USART_LIN_DETECT_BREAK_10BIT) || \
+ ((x) == USART_LIN_DETECT_BREAK_11BIT))
+
+#define IS_USART_LIN_SEND_BREAK_LEN(x) \
+( ((x) == USART_LIN_SEND_BREAK_10BIT) || \
+ ((x) == USART_LIN_SEND_BREAK_11BIT) || \
+ ((x) == USART_LIN_SEND_BREAK_13BIT) || \
+ ((x) == USART_LIN_SEND_BREAK_14BIT))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_Flag_Error_Mask USART Flag Error Mask
+ * @{
+ */
+#define USART_FLAG_ERR_MASK (USART_FLAG_OVERRUN | \
+ USART_FLAG_FRAME_ERR | \
+ USART_FLAG_PARITY_ERR)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_Registers_Reset_Value_definition USART Registers Reset Value
+ * @{
+ */
+#define USART_CR1_RST_VALUE (0x80000000UL)
+
+#define USART_CR2_RST_VALUE (0x0600UL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_LIN_Function_Mask USART LIN Function Mask
+ * @{
+ */
+#define USART_LIN_FUNC_OFFSET (16U)
+
+#define USART_LIN_FUNC_MASK (USART_LIN | \
+ USART_LIN_ERR | \
+ USART_LIN_WKUP | \
+ USART_LIN_INT_WKUP | \
+ USART_LIN_INT_BREAK | \
+ USART_LIN_INT_ERR)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_BRR_Division_Max USART BRR Register Division Max
+ * @{
+ */
+#define USART_BRR_DIV_INTEGER_MAX (0xFFUL)
+#define USART_BRR_DIV_FRACTION_MAX (0x7FUL)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_Clock_Division_Max USART Clock Division Max
+ * @{
+ */
+#define USART_CLK_DIV_MAX (USART_CLK_DIV64)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_Default_Baudrate USART Default Baudrate
+ * @{
+ */
+#define USART_DEFAULT_BAUDRATE (9600UL)
+/**
+ * @}
+ */
+
+#define USART_RMU_TIMEOUT (100U)
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ * @defgroup USART_Local_Functions USART Local Functions
+ * @{
+ */
+/**
+ * @brief Try to wait the expected status of specified flags
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] u32Flag USART flag
+ * This parameter can be a value of @ref USART_Flag
+ * @param [in] enStatus Expected status
+ * This parameter can be one of the following values:
+ * @arg SET: Wait flag set
+ * @arg RESET: Wait flag reset
+ * @param [in] u32Timeout Maximum count(Max value @ref USART_Max_Timeout) of trying to get status
+ * @retval int32_t:
+ * - LL_OK: Complete wait the expected status of the specified flags.
+ * - LL_ERR_TIMEOUT: Wait timeout.
+ * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT.
+ */
+static int32_t USART_WaitStatus(const CM_USART_TypeDef *USARTx,
+ uint32_t u32Flag,
+ en_flag_status_t enStatus,
+ uint32_t u32Timeout)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t u32To = 0UL;
+
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_FLAG(u32Flag));
+
+ while (USART_GetStatus(USARTx, u32Flag) != enStatus) {
+ /* Block checking flag if timeout value is USART_TIMEOUT_MAX */
+ if ((u32To > u32Timeout) && (u32Timeout < USART_MAX_TIMEOUT)) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+
+ u32To++;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Calculate baudrate division for UART mode.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] pstcUartBrr Pointer to a stc_usart_brr_t structure.
+ * @retval int32_t:
+ * - LL_OK: Set successfully.
+ * - LL_ERR: Set unsuccessfully.
+ */
+static int32_t UART_CalculateBrr(const CM_USART_TypeDef *USARTx, stc_usart_brr_t *pstcUartBrr)
+{
+ uint32_t B;
+ uint32_t C;
+ uint32_t OVER8;
+ uint64_t u64Temp;
+ uint64_t u64Temp0;
+ uint64_t u64Dividend;
+ uint32_t DIV_Integer;
+ uint32_t DIV_IntegerMod;
+ uint32_t DIV_Fraction;
+ float32_t f32CalcError;
+ uint32_t u32FractionFlag = 1UL;
+ int32_t i32Ret = LL_ERR;
+
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ C = pstcUartBrr->u32UsartClock;
+ B = pstcUartBrr->u32Baudrate;
+ if ((C > 0UL) && (B > 0UL)) {
+ OVER8 = READ_REG32_BIT(USARTx->CR1, USART_CR1_OVER8) >> USART_CR1_OVER8_POS;
+
+ /* UART mode baudrate integer calculation formula: */
+ /* B = C / (8 * (2 - OVER8) * (DIV_Integer + 1)) */
+ /* DIV_Integer = (C / (B * 8 * (2 - OVER8))) - 1 */
+ DIV_Integer = (C / (B * 8UL * (2UL - OVER8))) - 1U;
+ if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) {
+ pstcUartBrr->u32Integer = DIV_Integer;
+ DIV_IntegerMod = C % (B * 8UL * (2UL - OVER8));
+ if (0UL == DIV_IntegerMod) {
+ /* Get accurate baudrate without fraction */
+ pstcUartBrr->f32Error = (float32_t)0.0F;
+ i32Ret = LL_OK;
+ } else {
+ /* UART mode baudrate fraction calculation formula: */
+ /* B = C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256) */
+ /* DIV_Fraction = (256 * (8 * (2 - OVER8) * (DIV_Integer + 1) * B) / C) - 128 */
+ /* u64Temp = (8 * (2 - OVER8) * (DIV_Integer + 1) * B) */
+ u64Temp0 = (uint64_t)((uint64_t)8UL * ((uint64_t)2UL - (uint64_t)OVER8) * \
+ ((uint64_t)DIV_Integer + (uint64_t)1UL) * (uint64_t)B);
+
+ /* u64Temp = u64Temp0 *256 + C/2 */
+ u64Temp0 = (u64Temp0 << 8UL);
+ u64Temp = u64Temp0 + ((uint64_t)C >> 1); /* +(C >> 1) for rounding off */
+ if (u64Temp > (uint64_t)(UINT32_MAX)) {
+ DIV_Fraction = (uint32_t)(u64Temp / C) - 128UL;
+ } else {
+ DIV_Fraction = ((uint32_t)u64Temp) / C - 128UL;
+ }
+ if (DIV_Fraction <= USART_BRR_DIV_FRACTION_MAX) {
+ pstcUartBrr->u32Fraction = DIV_Fraction;
+ /* E(%) = C * (128 + DIV_Fraction) / (256 * (8 * (2 - OVER8) * (DIV_Integer + 1) * B)) - 1 */
+ u64Temp = u64Temp0;
+ u64Dividend = (uint64_t)C * ((uint64_t)128UL + (uint64_t)DIV_Fraction);
+ f32CalcError = (float32_t)((float64_t)(u64Dividend) / (float64_t)(u64Temp)) - 1.0F;
+ pstcUartBrr->f32Error = f32CalcError;
+ i32Ret = LL_OK;
+ } else {
+ u32FractionFlag = 0UL;
+ }
+ }
+ }
+ if (0UL == u32FractionFlag) {
+ /* Integer rounding off */
+ DIV_Integer = ((((C * 10UL) / (B * 8UL * (2UL - OVER8))) + 5UL) / 10UL) - 1UL; /* +5UL for rounding off */
+ if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) {
+ pstcUartBrr->u32Integer = DIV_Integer;
+ /* E(%) = C / (8 * (2 - OVER8) * (DIV_Integer + 1) * B) - 1 */
+ /* u64Temp = (8 * (2 - OVER8) * (DIV_Integer + 1) * B) */
+ u64Temp = (uint64_t)((uint64_t)8UL * ((uint64_t)2UL - (uint64_t)OVER8) * ((uint64_t)DIV_Integer + \
+ (uint64_t)1UL) * (uint64_t)B);
+ f32CalcError = (float32_t)((float64_t)C / (float64_t)u64Temp) - 1.0F;
+ pstcUartBrr->f32Error = f32CalcError;
+ i32Ret = LL_OK;
+ }
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Calculate baudrate division for UART mode.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] pstcClockSyncBrr Pointer to a stc_usart_brr_t structure.
+ * @retval int32_t:
+ * - LL_OK: Set successfully.
+ * - LL_ERR: Set unsuccessfully.
+ */
+static int32_t ClockSync_CalculateBrr(const CM_USART_TypeDef *USARTx, stc_usart_brr_t *pstcClockSyncBrr)
+{
+ uint32_t B;
+ uint32_t C;
+ uint64_t u64Temp;
+ uint64_t u64Dividend;
+ uint32_t DIV_Integer;
+ uint32_t DIV_IntegerMod;
+ uint32_t DIV_Fraction;
+ float32_t f32CalcError;
+ uint32_t u32FractionFlag = 1UL;
+ int32_t i32Ret = LL_ERR;
+
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+
+ C = pstcClockSyncBrr->u32UsartClock;
+ B = pstcClockSyncBrr->u32Baudrate;
+ if ((C > 0UL) && (B > 0UL)) {
+ /* Clock sync mode baudrate integer calculation formula: */
+ /* B = C / (4 * (DIV_Integer + 1)) */
+ /* DIV_Integer = (C / (B * 4)) - 1 */
+ DIV_Integer = (C / (B * 4UL)) - 1UL;
+ if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) {
+ pstcClockSyncBrr->u32Integer = DIV_Integer;
+ DIV_IntegerMod = C % (B * 4UL);
+ if (0UL == DIV_IntegerMod) {
+ /* Get accurate baudrate without fraction */
+ pstcClockSyncBrr->f32Error = (float32_t)0.0F;
+ i32Ret = LL_OK;
+ } else {
+ /* Clock sync mode baudrate fraction calculation formula: */
+ /* B = C * (128 + DIV_Fraction) / (4 * (DIV_Integer + 1) * 256) */
+ /* DIV_Fraction = 256 * (4 * (DIV_Integer + 1) * B) / C - 128 */
+
+ /* u64Temp = (4 * (DIV_Integer + 1) * B) */
+ u64Temp = (uint64_t)((uint64_t)4U * ((uint64_t)DIV_Integer + (uint64_t)1UL) * (uint64_t)B);
+ DIV_Fraction = (uint32_t)((256UL * u64Temp + ((uint64_t)C >> 1)) / C - 128UL); /* +(C >> 1) for rounding off */
+ if (DIV_Fraction <= USART_BRR_DIV_FRACTION_MAX) {
+ pstcClockSyncBrr->u32Fraction = DIV_Fraction;
+ /* E(%) = C * (128 + DIV_Fraction) / (4 * (DIV_Integer + 1) * B * 256) - 1 */
+ u64Temp *= (uint64_t)256UL;
+ u64Dividend = (uint64_t)C * ((uint64_t)128UL + (uint64_t)DIV_Fraction);
+ f32CalcError = (float32_t)((float64_t)(u64Dividend) / (float64_t)(u64Temp)) - 1.0F;
+ pstcClockSyncBrr->f32Error = f32CalcError;
+ i32Ret = LL_OK;
+ } else {
+ u32FractionFlag = 0UL;
+ }
+ }
+ }
+ if (0UL == u32FractionFlag) {
+ /* Integer rounding off */
+ DIV_Integer = ((((C * 10UL) / (B * 4UL)) + 5UL) / 10UL) - 1UL; /* +5UL for rounding off */
+ if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) {
+ pstcClockSyncBrr->u32Integer = DIV_Integer;
+ /* E(%) = C / (4 * (DIV_Integer + 1) * B) - 1 */
+ /* u64Temp = 4 * (DIV_Integer + 1) * B */
+ u64Temp = (uint64_t)((uint64_t)4U * ((uint64_t)DIV_Integer + (uint64_t)1UL) * (uint64_t)B);
+ f32CalcError = (float32_t)((float64_t)C / (float64_t)u64Temp) - 1.0F;
+ pstcClockSyncBrr->f32Error = f32CalcError;
+ i32Ret = LL_OK;
+ }
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Calculate baudrate division for UART mode.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] pstcSmartCardBrr Pointer to a stc_usart_brr_t structure.
+ * @retval int32_t:
+ * - LL_OK: Set successfully.
+ * - LL_ERR: Set unsuccessfully.
+ */
+static int32_t SmartCard_CalculateBrr(const CM_USART_TypeDef *USARTx, stc_usart_brr_t *pstcSmartCardBrr)
+{
+ uint32_t B;
+ uint32_t C;
+ uint32_t BCN;
+ uint64_t u64Temp;
+ uint64_t u64Dividend;
+ uint32_t DIV_Integer;
+ uint32_t DIV_IntegerMod;
+ uint32_t DIV_Fraction;
+ float32_t f32CalcError;
+ const uint16_t au16EtuClkCnts[] = {32U, 64U, 93U, 128U, 186U, 256U, 372U, 512U};
+ int32_t i32Ret = LL_ERR;
+
+ DDL_ASSERT(IS_USART_SMARTCARD_UNIT(USARTx));
+
+ C = pstcSmartCardBrr->u32UsartClock;
+ B = pstcSmartCardBrr->u32Baudrate;
+ if ((C > 0UL) && (B > 0UL)) {
+ BCN = READ_REG32_BIT(USARTx->CR3, USART_CR3_BCN);
+ DDL_ASSERT(IS_USART_SMARTCARD_ETU_CLK(BCN));
+ BCN = au16EtuClkCnts[BCN >> USART_CR3_BCN_POS];
+ /* Smartcard mode baudrate integer calculation formula: */
+ /* B = C / (2 * BCN * (DIV_Integer + 1)) */
+ /* DIV_Integer = (C / (B * 2 * BCN)) - 1 */
+ DIV_Integer = (C / (B * BCN * 2UL)) - 1UL;
+ if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) {
+ pstcSmartCardBrr->u32Integer = DIV_Integer;
+ DIV_IntegerMod = C % (B * BCN * 2UL);
+ if (0UL == DIV_IntegerMod) {
+ /* Get accurate baudrate without fraction */
+ pstcSmartCardBrr->f32Error = (float32_t)0.0F;
+ i32Ret = LL_OK;
+ } else {
+ /* Smartcard mode baudrate fraction calculation formula: */
+ /* B = C * (128 + DIV_Fraction) / ((2 * BCN) * (DIV_Integer + 1) * 256) */
+ /* DIV_Fraction = (256 * (2 * BCN * (DIV_Integer + 1) * B) / C) - 128 */
+
+ /* u64Temp = (2 * BCN * (DIV_Integer + 1) * B) */
+ u64Temp = (uint64_t)((uint64_t)2UL * BCN * ((uint64_t)DIV_Integer + (uint64_t)1UL) * B);
+ DIV_Fraction = (uint32_t)((256UL * u64Temp + ((uint64_t)C >> 1)) / C - 128UL); /* +(C >> 1) for rounding off */
+ if (DIV_Fraction <= USART_BRR_DIV_FRACTION_MAX) {
+ pstcSmartCardBrr->u32Fraction = DIV_Fraction;
+ /* E(%) = C * (128 + DIV_Fraction) / (4 * (DIV_Integer + 1) * B * 256) - 1 */
+ u64Temp *= (uint64_t)256UL;
+ u64Dividend = (uint64_t)C * ((uint64_t)128UL + (uint64_t)DIV_Fraction);
+ f32CalcError = (float32_t)((float64_t)u64Dividend / (float64_t)(u64Temp)) - 1.0F;
+ pstcSmartCardBrr->f32Error = f32CalcError;
+ i32Ret = LL_OK;
+ }
+ }
+ }
+ if (LL_ERR == i32Ret) {
+ /* Integer rounding off */
+ DIV_Integer = (((C * 10UL) / (B * BCN * 2UL) + 5UL) / 10UL) - 1UL; /* +5UL for rounding off */
+ if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) {
+ pstcSmartCardBrr->u32Integer = DIV_Integer;
+ /* E(%) = C / (2 * BCN * (DIV_Integer + 1) * B) - 1 */
+ /* u64Temp = 4 * (DIV_Integer + 1) * B */
+ u64Temp = (uint64_t)((uint64_t)2UL * BCN * ((uint64_t)DIV_Integer + (uint64_t)1UL) * B);
+ f32CalcError = (float32_t)((float64_t)C / (float64_t)u64Temp) - 1.0F;
+ pstcSmartCardBrr->f32Error = f32CalcError;
+ i32Ret = LL_OK;
+ }
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @brief Get bus(which USART mounts on) clock frequency value.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @retval USART clock frequency value
+ */
+static uint32_t USART_GetBusClockFreq(const CM_USART_TypeDef *USARTx)
+{
+ uint32_t u32BusClock;
+
+ (void)USARTx;
+
+ u32BusClock = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS);
+
+ return u32BusClock;
+}
+
+/**
+ * @brief Get USART clock frequency value.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @retval USART clock frequency value
+ */
+static uint32_t USART_GetUsartClockFreq(const CM_USART_TypeDef *USARTx)
+{
+ uint32_t u32BusClock;
+ uint32_t u32UsartClockDiv;
+ uint32_t u32UsartClock;
+
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+
+ u32BusClock = USART_GetBusClockFreq(USARTx);
+
+ u32UsartClockDiv = (1UL << (READ_REG32_BIT(USARTx->PR, USART_PR_PSC) * 2UL));
+
+ u32UsartClock = u32BusClock / u32UsartClockDiv;
+ return u32UsartClock;
+}
+
+/**
+ * @brief Get USART BMC clock frequency value.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @retval USART BMC clock frequency value
+ */
+static uint32_t USART_GetLinBmcClockFreq(const CM_USART_TypeDef *USARTx)
+{
+ uint32_t u32BusClock;
+ uint32_t u32UsartBmcDiv;
+ uint32_t u32UsartBmcClock;
+
+ DDL_ASSERT(IS_USART_LIN_UNIT(USARTx));
+
+ u32BusClock = USART_GetBusClockFreq(USARTx);
+ u32UsartBmcDiv = (1UL << (READ_REG32_BIT((USARTx)->PR, USART_PR_LBMPSC) >> USART_PR_LBMPSC_POS));
+
+ u32UsartBmcClock = u32BusClock / u32UsartBmcDiv;
+ return u32UsartBmcClock;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup USART_Global_Functions USART Global Functions
+ * @{
+ */
+
+/**
+ * @brief Set the fields of structure stc_usart_clocksync_init_t to default values.
+ * @param [out] pstcClockSyncInit Pointer to a @ref stc_usart_clocksync_init_t structure.
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcClockSyncInit value is NULL.
+ */
+int32_t USART_ClockSync_StructInit(stc_usart_clocksync_init_t *pstcClockSyncInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcClockSyncInit) {
+ pstcClockSyncInit->u32ClockSrc = USART_CLK_SRC_INTERNCLK;
+ pstcClockSyncInit->u32ClockDiv = USART_CLK_DIV1;
+ pstcClockSyncInit->u32Baudrate = USART_DEFAULT_BAUDRATE;
+ pstcClockSyncInit->u32FirstBit = USART_FIRST_BIT_LSB;
+ pstcClockSyncInit->u32HWFlowControl = USART_HW_FLOWCTRL_RTS;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize clock synchronization function.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] pstcClockSyncInit Pointer to a @ref stc_usart_clocksync_init_t structure.
+ * @param [out] pf32Error E(%) baudrate error rate
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcClockSyncInit value is NULL or baudrate set unsuccessfully.
+ */
+int32_t USART_ClockSync_Init(CM_USART_TypeDef *USARTx,
+ const stc_usart_clocksync_init_t *pstcClockSyncInit, float32_t *pf32Error)
+{
+ uint32_t u32CR1Value;
+ uint32_t u32CR2Value;
+ uint32_t u32CR3Value;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcClockSyncInit) {
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_CLK_SRC(pstcClockSyncInit->u32ClockSrc));
+ DDL_ASSERT(IS_USART_FIRST_BIT(pstcClockSyncInit->u32FirstBit));
+ DDL_ASSERT(IS_USART_HW_FLOWCTRL(pstcClockSyncInit->u32HWFlowControl));
+
+ u32CR1Value = (pstcClockSyncInit->u32FirstBit | USART_CR1_MS | USART_CR1_SBS);
+ u32CR2Value = (pstcClockSyncInit->u32ClockSrc | USART_CR2_RST_VALUE);
+ if (USART_CLK_SRC_INTERNCLK == pstcClockSyncInit->u32ClockSrc) {
+ u32CR2Value |= USART_CK_OUTPUT_ENABLE;
+ }
+ u32CR3Value = pstcClockSyncInit->u32HWFlowControl;
+
+ /* Set control register: CR1/CR2/CR3 */
+ WRITE_REG32(USARTx->CR1, u32CR1Value);
+ WRITE_REG32(USARTx->CR2, u32CR2Value);
+ WRITE_REG32(USARTx->CR3, u32CR3Value);
+
+ if (USART_CLK_SRC_INTERNCLK == pstcClockSyncInit->u32ClockSrc) {
+ DDL_ASSERT(IS_USART_CLK_DIV(pstcClockSyncInit->u32ClockDiv));
+
+ /* Set prescaler register register: PR */
+ WRITE_REG32(USARTx->PR, pstcClockSyncInit->u32ClockDiv);
+
+ /* Set baudrate */
+ i32Ret = USART_SetBaudrate(USARTx, pstcClockSyncInit->u32Baudrate, pf32Error);
+ } else {
+ i32Ret = LL_OK;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set the fields of structure stc_usart_multiprocessor_init_t to default values.
+ * @param [out] pstcMultiProcessorInit Pointer to a @ref stc_usart_multiprocessor_init_t structure.
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcMultiProcessorInit value is NULL.
+ */
+int32_t USART_MultiProcessor_StructInit(stc_usart_multiprocessor_init_t *pstcMultiProcessorInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcMultiProcessorInit) {
+ pstcMultiProcessorInit->u32ClockSrc = USART_CLK_SRC_INTERNCLK;
+ pstcMultiProcessorInit->u32ClockDiv = USART_CLK_DIV1;
+ pstcMultiProcessorInit->u32CKOutput = USART_CK_OUTPUT_DISABLE;
+ pstcMultiProcessorInit->u32Baudrate = USART_DEFAULT_BAUDRATE;
+ pstcMultiProcessorInit->u32DataWidth = USART_DATA_WIDTH_8BIT;
+ pstcMultiProcessorInit->u32StopBit = USART_STOPBIT_1BIT;
+ pstcMultiProcessorInit->u32OverSampleBit = USART_OVER_SAMPLE_16BIT;
+ pstcMultiProcessorInit->u32FirstBit = USART_FIRST_BIT_LSB;
+ pstcMultiProcessorInit->u32StartBitPolarity = USART_START_BIT_FALLING;
+ pstcMultiProcessorInit->u32HWFlowControl = USART_HW_FLOWCTRL_RTS;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize UART multiple processor function.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] pstcMultiProcessorInit Pointer to a @ref stc_usart_multiprocessor_init_t structure.
+ * @param [out] pf32Error E(%) baudrate error rate
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcMxProcessorInit value is NULL or baudrate set unsuccessfully.
+ */
+int32_t USART_MultiProcessor_Init(CM_USART_TypeDef *USARTx,
+ const stc_usart_multiprocessor_init_t *pstcMultiProcessorInit, float32_t *pf32Error)
+{
+ uint32_t u32CR1Value;
+ uint32_t u32CR2Value;
+ uint32_t u32CR3Value;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcMultiProcessorInit) {
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_CLK_SRC(pstcMultiProcessorInit->u32ClockSrc));
+ DDL_ASSERT(IS_USART_CK_OUTPUT(pstcMultiProcessorInit->u32CKOutput));
+ DDL_ASSERT(IS_USART_DATA_WIDTH(pstcMultiProcessorInit->u32DataWidth));
+ DDL_ASSERT(IS_USART_STOPBIT(pstcMultiProcessorInit->u32StopBit));
+ DDL_ASSERT(IS_USART_OVER_SAMPLE_BIT(pstcMultiProcessorInit->u32OverSampleBit));
+ DDL_ASSERT(IS_USART_FIRST_BIT(pstcMultiProcessorInit->u32FirstBit));
+ DDL_ASSERT(IS_USART_START_BIT_POLARITY(pstcMultiProcessorInit->u32StartBitPolarity));
+ DDL_ASSERT(IS_USART_HW_FLOWCTRL(pstcMultiProcessorInit->u32HWFlowControl));
+
+ u32CR1Value = (pstcMultiProcessorInit->u32DataWidth | pstcMultiProcessorInit->u32OverSampleBit | \
+ pstcMultiProcessorInit->u32FirstBit | pstcMultiProcessorInit->u32StartBitPolarity);
+ u32CR2Value = (USART_CR2_RST_VALUE | USART_CR2_MPE | pstcMultiProcessorInit->u32ClockSrc | \
+ pstcMultiProcessorInit->u32CKOutput | pstcMultiProcessorInit->u32StopBit);
+ u32CR3Value = pstcMultiProcessorInit->u32HWFlowControl;
+
+ /* Set control register: CR1/CR2/CR3 */
+ WRITE_REG32(USARTx->CR1, u32CR1Value);
+ WRITE_REG32(USARTx->CR2, u32CR2Value);
+ WRITE_REG32(USARTx->CR3, u32CR3Value);
+
+ if (USART_CLK_SRC_INTERNCLK == pstcMultiProcessorInit->u32ClockSrc) {
+ DDL_ASSERT(IS_USART_CLK_DIV(pstcMultiProcessorInit->u32ClockDiv));
+
+ /* Set prescaler register register: PR */
+ WRITE_REG32(USARTx->PR, pstcMultiProcessorInit->u32ClockDiv);
+
+ /* Set baudrate */
+ i32Ret = USART_SetBaudrate(USARTx, pstcMultiProcessorInit->u32Baudrate, pf32Error);
+ } else {
+ i32Ret = LL_OK;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set the fields of structure stc_usart_uart_init_t to default values.
+ * @param [out] pstcUartInit Pointer to a @ref stc_usart_uart_init_t structure.
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcUartInit value is NULL.
+ */
+int32_t USART_UART_StructInit(stc_usart_uart_init_t *pstcUartInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcUartInit) {
+ pstcUartInit->u32ClockSrc = USART_CLK_SRC_INTERNCLK;
+ pstcUartInit->u32ClockDiv = USART_CLK_DIV1;
+ pstcUartInit->u32CKOutput = USART_CK_OUTPUT_DISABLE;
+ pstcUartInit->u32Baudrate = USART_DEFAULT_BAUDRATE;
+ pstcUartInit->u32DataWidth = USART_DATA_WIDTH_8BIT;
+ pstcUartInit->u32StopBit = USART_STOPBIT_1BIT;
+ pstcUartInit->u32Parity = USART_PARITY_NONE;
+ pstcUartInit->u32OverSampleBit = USART_OVER_SAMPLE_16BIT;
+ pstcUartInit->u32FirstBit = USART_FIRST_BIT_LSB;
+ pstcUartInit->u32StartBitPolarity = USART_START_BIT_FALLING;
+ pstcUartInit->u32HWFlowControl = USART_HW_FLOWCTRL_RTS;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize UART function.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] pstcUartInit Pointer to a @ref stc_usart_uart_init_t structure.
+ * @param [out] pf32Error E(%) baudrate error rate
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcUartInit value is NULL or baudrate set unsuccessfully.
+ */
+int32_t USART_UART_Init(CM_USART_TypeDef *USARTx, const stc_usart_uart_init_t *pstcUartInit, float32_t *pf32Error)
+{
+ uint32_t u32CR1Value;
+ uint32_t u32CR2Value;
+ uint32_t u32CR3Value;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcUartInit) {
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_CLK_SRC(pstcUartInit->u32ClockSrc));
+ DDL_ASSERT(IS_USART_CK_OUTPUT(pstcUartInit->u32CKOutput));
+ DDL_ASSERT(IS_USART_PARITY(pstcUartInit->u32Parity));
+ DDL_ASSERT(IS_USART_DATA_WIDTH(pstcUartInit->u32DataWidth));
+ DDL_ASSERT(IS_USART_STOPBIT(pstcUartInit->u32StopBit));
+ DDL_ASSERT(IS_USART_OVER_SAMPLE_BIT(pstcUartInit->u32OverSampleBit));
+ DDL_ASSERT(IS_USART_FIRST_BIT(pstcUartInit->u32FirstBit));
+ DDL_ASSERT(IS_USART_START_BIT_POLARITY(pstcUartInit->u32StartBitPolarity));
+ DDL_ASSERT(IS_USART_HW_FLOWCTRL(pstcUartInit->u32HWFlowControl));
+
+ u32CR1Value = (pstcUartInit->u32Parity | pstcUartInit->u32DataWidth | pstcUartInit->u32FirstBit | \
+ pstcUartInit->u32OverSampleBit | pstcUartInit->u32StartBitPolarity);
+ u32CR2Value = (USART_CR2_RST_VALUE | pstcUartInit->u32ClockSrc | \
+ pstcUartInit->u32CKOutput | pstcUartInit->u32StopBit);
+ u32CR3Value = pstcUartInit->u32HWFlowControl;
+
+ /* Set control register: CR1/CR2/CR3 */
+ WRITE_REG32(USARTx->CR1, u32CR1Value);
+ WRITE_REG32(USARTx->CR2, u32CR2Value);
+ WRITE_REG32(USARTx->CR3, u32CR3Value);
+
+ if (USART_CLK_SRC_INTERNCLK == pstcUartInit->u32ClockSrc) {
+ DDL_ASSERT(IS_USART_CLK_DIV(pstcUartInit->u32ClockDiv));
+
+ /* Set prescaler register register: PR */
+ WRITE_REG32(USARTx->PR, pstcUartInit->u32ClockDiv);
+
+ /* Set baudrate */
+ i32Ret = USART_SetBaudrate(USARTx, pstcUartInit->u32Baudrate, pf32Error);
+ } else {
+ i32Ret = LL_OK;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize UART half duplex function.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] pstcUartInit Pointer to a @ref stc_usart_uart_init_t structure.
+ * @param [out] pf32Error E(%) baudrate error rate
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcUartInit value is NULL or baudrate set unsuccessfully.
+ */
+int32_t USART_HalfDuplex_Init(CM_USART_TypeDef *USARTx,
+ const stc_usart_uart_init_t *pstcUartInit, float32_t *pf32Error)
+{
+ int32_t i32Ret;
+
+ i32Ret = USART_UART_Init(USARTx, pstcUartInit, pf32Error);
+ if (LL_OK == i32Ret) {
+ /* Set CR3: UART half duplex */
+ SET_REG32_BIT(USARTx->CR3, USART_CR3_HDSEL);
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set the fields of structure stc_usart_lin_init_t to default values.
+ * @param [out] pstcLinInit Pointer to a @ref stc_usart_lin_init_t structure.
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcLinInit is NULL.
+ */
+int32_t USART_LIN_StructInit(stc_usart_lin_init_t *pstcLinInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcLinInit) {
+ pstcLinInit->u32ClockSrc = USART_CLK_SRC_INTERNCLK;
+ pstcLinInit->u32ClockDiv = USART_CLK_DIV1;
+ pstcLinInit->u32CKOutput = USART_CK_OUTPUT_DISABLE;
+ pstcLinInit->u32Baudrate = USART_DEFAULT_BAUDRATE;
+ pstcLinInit->u32OverSampleBit = USART_OVER_SAMPLE_16BIT;
+ pstcLinInit->u32BmcClockDiv = USART_LIN_BMC_CLK_DIV1;
+ pstcLinInit->u32DetectBreakLen = USART_LIN_DETECT_BREAK_10BIT;
+ pstcLinInit->u32SendBreakLen = USART_LIN_SEND_BREAK_10BIT;
+ pstcLinInit->u32SendBreakMode = USART_LIN_SEND_BREAK_MD_SBK;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Initialize LIN function.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] pstcLinInit Pointer to a @ref stc_usart_lin_init_t structure.
+ * @param [out] pf32Error E(%) baudrate error rate
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcLinInit value is NULL or baudrate set unsuccessfully.
+ */
+int32_t USART_LIN_Init(CM_USART_TypeDef *USARTx, const stc_usart_lin_init_t *pstcLinInit, float32_t *pf32Error)
+{
+ uint32_t u32CR1Value;
+ uint32_t u32CR2Value;
+ uint32_t u32PRValue;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcLinInit) {
+ DDL_ASSERT(IS_USART_LIN_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_CLK_SRC(pstcLinInit->u32ClockSrc));
+ DDL_ASSERT(IS_USART_CK_OUTPUT(pstcLinInit->u32CKOutput));
+ DDL_ASSERT(IS_USART_CLK_DIV(pstcLinInit->u32ClockDiv));
+ DDL_ASSERT(IS_USART_OVER_SAMPLE_BIT(pstcLinInit->u32OverSampleBit));
+
+ u32CR1Value = (pstcLinInit->u32OverSampleBit | USART_CR1_SBS);
+ u32CR2Value = (pstcLinInit->u32ClockSrc | pstcLinInit->u32CKOutput | USART_CR2_LINEN | USART_CR2_RST_VALUE);
+
+ DDL_ASSERT(IS_USART_LIN_DETECT_BREAK_LEN(pstcLinInit->u32DetectBreakLen));
+ DDL_ASSERT(IS_USART_LIN_SEND_BREAK_LEN(pstcLinInit->u32SendBreakLen));
+ DDL_ASSERT(IS_USART_LIN_SEND_BREAK_MD(pstcLinInit->u32SendBreakMode));
+ u32CR2Value |= (pstcLinInit->u32DetectBreakLen | pstcLinInit->u32SendBreakLen | pstcLinInit->u32SendBreakMode);
+
+ /* Set control register: CR1/CR2/CR3 */
+ WRITE_REG32(USARTx->CR1, u32CR1Value);
+ WRITE_REG32(USARTx->CR2, u32CR2Value);
+ WRITE_REG32(USARTx->CR3, 0UL);
+
+ if (USART_CLK_SRC_INTERNCLK == pstcLinInit->u32ClockSrc) {
+ DDL_ASSERT(IS_USART_CLK_DIV(pstcLinInit->u32ClockDiv));
+ u32PRValue = pstcLinInit->u32ClockDiv;
+
+ DDL_ASSERT(IS_USART_LIN_BMC_CLK_DIV(pstcLinInit->u32BmcClockDiv));
+ u32PRValue |= pstcLinInit->u32BmcClockDiv;
+
+ /* Set prescaler register register: PR */
+ WRITE_REG32(USARTx->PR, u32PRValue);
+
+ /* Set baudrate */
+ i32Ret = USART_SetBaudrate(USARTx, pstcLinInit->u32Baudrate, pf32Error);
+ } else {
+ i32Ret = LL_OK;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set the fields of structure stc_usart_smartcard_init_t to default values.
+ * @param [out] pstcSmartCardInit Pointer to a @ref stc_usart_smartcard_init_t structure.
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcSmartCardInit value is NULL.
+ */
+int32_t USART_SmartCard_StructInit(stc_usart_smartcard_init_t *pstcSmartCardInit)
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcSmartCardInit) {
+ pstcSmartCardInit->u32ClockDiv = USART_CLK_DIV1;
+ pstcSmartCardInit->u32CKOutput = USART_CK_OUTPUT_DISABLE;
+ pstcSmartCardInit->u32Baudrate = USART_DEFAULT_BAUDRATE;
+ pstcSmartCardInit->u32FirstBit = USART_FIRST_BIT_LSB;
+ i32Ret = LL_OK;
+ }
+
+ return i32Ret;
+}
+/**
+ * @brief Initialize smartcard function.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] pstcSmartCardInit Pointer to a @ref stc_usart_smartcard_init_t structure.
+ * @param [out] pf32Error E(%) baudrate error rate
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR_INVD_PARAM: The pointer pstcSmartCardInit value is NULL or baudrate set unsuccessfully.
+ */
+int32_t USART_SmartCard_Init(CM_USART_TypeDef *USARTx,
+ const stc_usart_smartcard_init_t *pstcSmartCardInit, float32_t *pf32Error)
+{
+ uint32_t u32CR1Value;
+ uint32_t u32CR2Value;
+ uint32_t u32CR3Value;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pstcSmartCardInit) {
+ DDL_ASSERT(IS_USART_SMARTCARD_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_CK_OUTPUT(pstcSmartCardInit->u32CKOutput));
+ DDL_ASSERT(IS_USART_CLK_DIV(pstcSmartCardInit->u32ClockDiv));
+ DDL_ASSERT(IS_USART_FIRST_BIT(pstcSmartCardInit->u32FirstBit));
+
+ u32CR1Value = (pstcSmartCardInit->u32FirstBit | USART_CR1_PCE | USART_CR1_SBS);
+ u32CR2Value = (pstcSmartCardInit->u32CKOutput | USART_CR2_RST_VALUE);
+ u32CR3Value = USART_CR3_SCEN | USART_SC_ETU_CLK372;
+
+ /* Set control register: CR1/CR2/CR3 */
+ WRITE_REG32(USARTx->CR1, u32CR1Value);
+ WRITE_REG32(USARTx->CR2, u32CR2Value);
+ WRITE_REG32(USARTx->CR3, u32CR3Value);
+
+ /* Set prescaler register register: PR */
+ WRITE_REG32(USARTx->PR, pstcSmartCardInit->u32ClockDiv);
+
+ /* Set baudrate */
+ i32Ret = USART_SetBaudrate(USARTx, pstcSmartCardInit->u32Baudrate, pf32Error);
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief De-Initialize USART function.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @retval int32_t:
+ * - LL_OK: Reset success.
+ * - LL_ERR_TIMEOUT: Reset time out.
+ * @note Call LL_PERIPH_WE(LL_PERIPH_PWC_CLK_RMU) unlock RMU_FRSTx register first.
+ */
+int32_t USART_DeInit(CM_USART_TypeDef *USARTx)
+{
+ uint32_t i;
+ int32_t i32Ret = LL_OK;
+ __IO uint8_t u8TimeOut = 0U;
+ __IO uint32_t *bCM_RMU_FRST3_USARTx = NULL;
+ const uint32_t au32USARTx[] = {CM_USART1_BASE, CM_USART2_BASE, CM_USART3_BASE, \
+ CM_USART4_BASE, CM_USART5_BASE, CM_USART6_BASE
+ };
+
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1);
+
+ for (i = 0UL; i < ARRAY_SZ(au32USARTx); i++) {
+ if ((uint32_t)USARTx == au32USARTx[i]) {
+ bCM_RMU_FRST3_USARTx = (__IO uint32_t *)((uint32_t)&bCM_RMU->FRST3_b.USART1 + (i << 2));
+ break;
+ }
+ }
+
+ /* Reset USART */
+ WRITE_REG32(*bCM_RMU_FRST3_USARTx, 0UL);
+
+ /* Ensure reset procedure is completed */
+ while (READ_REG32(*bCM_RMU_FRST3_USARTx) != 1UL) {
+ u8TimeOut++;
+ if (u8TimeOut > USART_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Enable/disable USART Transmit/Receive Function.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] u32Func USART function type
+ * This parameter can be any composed value of the macros group @ref USART_Function.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ * @note In clock synchronization mode, the bit TE or RE of register USART_CR can only be
+ * written to 1 when TE = 0 and RE = 0 (transmit and receive disabled)
+ */
+void USART_FuncCmd(CM_USART_TypeDef *USARTx, uint32_t u32Func, en_functional_state_t enNewState)
+{
+ uint32_t u32BaseFunc;
+ uint32_t u32LinFunc;
+
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ DDL_ASSERT(IS_USART_FUNC(u32Func));
+ DDL_ASSERT(IS_USART_LIN_FUNC(USARTx, u32Func));
+ DDL_ASSERT(IS_USART_TIMEOUT_FUNC(USARTx, u32Func));
+
+ u32BaseFunc = (u32Func & 0xFFFFUL);
+ if (u32BaseFunc > 0UL) {
+ (ENABLE == enNewState) ? SET_REG32_BIT(USARTx->CR1, u32BaseFunc) : CLR_REG32_BIT(USARTx->CR1, u32BaseFunc);
+ }
+
+ u32LinFunc = ((u32Func & USART_LIN_FUNC_MASK) >> USART_LIN_FUNC_OFFSET);
+ if (u32LinFunc > 0UL) {
+ (ENABLE == enNewState) ? SET_REG32_BIT(USARTx->CR2, u32LinFunc) : CLR_REG32_BIT(USARTx->CR2, u32LinFunc);
+ }
+}
+
+/**
+ * @brief Enable/disable USART Transmit/Receive Function.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] u32Func USART function type
+ * This parameter can be any composed value of the macros group @ref USART_Function.
+ * @retval An @ref en_functional_state_t enumeration value.
+ * - ENABLE: DVP capture started
+ * - DISABLE: DVP capture stopped
+ * @note In clock synchronization mode, the bit TE or RE of register USART_CR can only be
+ * written to 1 when TE = 0 and RE = 0 (transmit and receive disabled)
+ */
+en_functional_state_t USART_GetFuncState(CM_USART_TypeDef *USARTx, uint32_t u32Func)
+{
+ uint32_t u32BaseFunc;
+ en_functional_state_t enNewState = DISABLE;
+
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_FUNC(u32Func));
+ DDL_ASSERT(IS_USART_LIN_FUNC(USARTx, u32Func));
+ DDL_ASSERT(IS_USART_TIMEOUT_FUNC(USARTx, u32Func));
+
+ u32BaseFunc = (u32Func & 0xFFFFUL);
+ if (0UL != u32BaseFunc) {
+ if (0UL != READ_REG32_BIT(USARTx->CR1, u32BaseFunc)) {
+ enNewState = ENABLE;
+ }
+ }
+ u32BaseFunc = u32Func >> USART_LIN_FUNC_OFFSET;
+ if (0UL != u32BaseFunc) {
+ if (0UL != READ_REG32_BIT(USARTx->CR2, u32BaseFunc)) {
+ enNewState = ENABLE;
+ }
+ }
+ return enNewState;
+}
+
+/**
+ * @brief Get USART flag.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] u32Flag USART flag type
+ * This parameter can be any composed value of the macros group @ref USART_Flag.
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t USART_GetStatus(const CM_USART_TypeDef *USARTx, uint32_t u32Flag)
+{
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_FLAG(u32Flag));
+
+ return (0UL == (READ_REG32_BIT(USARTx->SR, u32Flag)) ? RESET : SET);
+}
+
+/**
+ * @brief Clear USART flag.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] u32Flag USART flag type
+ * This parameter can be any composed value of the macros group @ref USART_Flag.
+ * @retval None
+ */
+void USART_ClearStatus(CM_USART_TypeDef *USARTx, uint32_t u32Flag)
+{
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_FLAG(u32Flag));
+
+ if ((u32Flag & USART_FLAG_ERR_MASK) > 0UL) {
+ SET_REG32_BIT(USARTx->CR1, (u32Flag & USART_FLAG_ERR_MASK) << USART_CR1_CPE_POS);
+ }
+
+ /* Timeout flag */
+ if ((u32Flag & USART_FLAG_RX_TIMEOUT) > 0UL) {
+ SET_REG32_BIT(USARTx->CR1, USART_CR1_CRTOF);
+ }
+
+ /* LIN flag */
+ if ((u32Flag & USART_FLAG_LIN_ERR) > 0UL) {
+ SET_REG32_BIT(USARTx->CR1, USART_CR1_CBE);
+ }
+
+ if ((u32Flag & USART_FLAG_LIN_WKUP) > 0UL) {
+ SET_REG32_BIT(USARTx->CR1, USART_CR1_CWKUP);
+ }
+
+ if ((u32Flag & USART_FLAG_LIN_BREAK) > 0UL) {
+ SET_REG32_BIT(USARTx->CR1, USART_CR1_CLBD);
+ }
+
+ /* Transmission complete flag */
+ if ((u32Flag & USART_FLAG_TX_END) > 0UL) {
+ SET_REG32_BIT(USARTx->CR1, USART_CR1_CTEND);
+ }
+}
+
+/**
+ * @brief Set USART parity.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] u32Parity USART parity
+ * This parameter can be one of the macros group @ref USART_Parity_Control
+ * @arg USART_PARITY_NONE: Parity control disabled
+ * @arg USART_PARITY_ODD: Parity control enabled and Odd Parity is selected
+ * @arg USART_PARITY_EVEN: Parity control enabled and Even Parity is selected
+ * @retval None
+ */
+void USART_SetParity(CM_USART_TypeDef *USARTx, uint32_t u32Parity)
+{
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_PARITY(u32Parity));
+
+ MODIFY_REG32(USARTx->CR1, (USART_CR1_PS | USART_CR1_PCE), u32Parity);
+}
+
+/**
+ * @brief Set USART bit direction.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] u32FirstBit USART bit direction
+ * This parameter can be one of the macros group @ref USART_First_Bit
+ * @arg USART_FIRST_BIT_MSB: MSB(Most Significant Bit)
+ * @arg USART_FIRST_BIT_LSB: LSB(Least Significant Bit)
+ * @retval None
+ */
+void USART_SetFirstBit(CM_USART_TypeDef *USARTx, uint32_t u32FirstBit)
+{
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_FIRST_BIT(u32FirstBit));
+
+ MODIFY_REG32(USARTx->CR1, USART_CR1_ML, u32FirstBit);
+}
+
+/**
+ * @brief Set USART stop bit.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] u32StopBit USART stop bits
+ * This parameter can be one of the macros group @ref USART_Stop_Bit
+ * @arg USART_STOPBIT_1BIT: 1 stop bit
+ * @arg USART_STOPBIT_2BIT: 2 stop bit
+ * @retval None
+ */
+void USART_SetStopBit(CM_USART_TypeDef *USARTx, uint32_t u32StopBit)
+{
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_STOPBIT(u32StopBit));
+
+ MODIFY_REG32(USARTx->CR2, USART_CR2_STOP, u32StopBit);
+}
+
+/**
+ * @brief Set USART data width.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] u32DataWidth USART data width
+ * This parameter can be one of the macros group @ref USART_Data_Width_Bit
+ * @arg USART_DATA_WIDTH_8BIT: 8 bits word width
+ * @arg USART_DATA_WIDTH_9BIT: 9 bits word width
+ * @retval None
+ */
+void USART_SetDataWidth(CM_USART_TypeDef *USARTx, uint32_t u32DataWidth)
+{
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_DATA_WIDTH(u32DataWidth));
+
+ MODIFY_REG32(USARTx->CR1, USART_CR1_M, u32DataWidth);
+}
+
+/**
+ * @brief Set USART oversampling bits.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] u32OverSampleBit USART over sample bit
+ * This parameter can be one of the macros group @ref USART_Over_Sample_Bit
+ * @arg USART_OVER_SAMPLE_8BIT: Oversampling by 8 bit
+ * @arg USART_OVER_SAMPLE_16BIT: Oversampling by 16 bit
+ * @retval None
+ */
+void USART_SetOverSampleBit(CM_USART_TypeDef *USARTx, uint32_t u32OverSampleBit)
+{
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_OVER_SAMPLE_BIT(u32OverSampleBit));
+
+ MODIFY_REG32(USARTx->CR1, USART_CR1_OVER8, u32OverSampleBit);
+}
+
+/**
+ * @brief Set USART start bit detect polarity.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] u32Polarity USART start bit detect polarity
+ * This parameter can be one of the macros group @ref USART_Start_Bit_Polarity
+ * @arg USART_START_BIT_LOW: Detect RX pin low level
+ * @arg USART_START_BIT_FALLING: Detect RX pin falling edge
+ * @retval None
+ */
+void USART_SetStartBitPolarity(CM_USART_TypeDef *USARTx, uint32_t u32Polarity)
+{
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_START_BIT_POLARITY(u32Polarity));
+
+ MODIFY_REG32(USARTx->CR1, USART_CR1_SBS, u32Polarity);
+}
+
+/**
+ * @brief Set USART transmission type.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] u16Type USART transmission content type
+ * This parameter can be one of the macros group @ref USART_Transmission_Type
+ * @arg USART_TRANS_ID: USART transmission content type is processor ID
+ * @arg USART_TRANS_DATA: USART transmission content type is frame data
+ * @retval None
+ */
+void USART_SetTransType(CM_USART_TypeDef *USARTx, uint16_t u16Type)
+{
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_TRANS_TYPE(u16Type));
+
+ MODIFY_REG16(USARTx->TDR, USART_TDR_MPID, u16Type);
+}
+
+/**
+ * @brief Set USART clock prescaler division.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] u32ClockDiv USART clock prescaler division.
+ * This parameter can be one of the macros group @ref USART_Clock_Division
+ * @retval None
+ * @note The clock division function is valid only when clock source is internal clock.
+ */
+void USART_SetClockDiv(CM_USART_TypeDef *USARTx, uint32_t u32ClockDiv)
+{
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_CLK_DIV(u32ClockDiv));
+
+ MODIFY_REG32(USARTx->PR, USART_PR_PSC, u32ClockDiv);
+}
+
+/**
+ * @brief Get USART clock prescaler division.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @retval Returned value can be one of the macros group @ref USART_Clock_Division
+ * @note The clock division function is valid only when clock source is internal clock.
+ */
+uint32_t USART_GetClockDiv(const CM_USART_TypeDef *USARTx)
+{
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+
+ return READ_REG32_BIT(USARTx->PR, USART_PR_PSC);
+}
+
+/**
+ * @brief Set USART clock source.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] u32ClockSrc USART clock source
+ * This parameter can be one of the macros group @ref USART_Clock_Source
+ * @arg USART_CLK_SRC_EXTCLK: Clock source is external clock(USART_CK).
+ * @arg USART_CLK_SRC_INTERNCLK: Clock source is internal clock.
+ * @retval None
+ */
+void USART_SetClockSrc(CM_USART_TypeDef *USARTx, uint32_t u32ClockSrc)
+{
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_CLK_SRC(u32ClockSrc));
+
+ MODIFY_REG32(USARTx->CR2, USART_CR2_CLKC_1, u32ClockSrc);
+}
+
+/**
+ * @brief Get USART clock source.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @retval Returned value can be one of the following values:
+ * - USART_CLK_SRC_EXTCLK: Clock source is external clock(USART_CK).
+ * - USART_CLK_SRC_INTERNCLK: Clock source is internal clock.
+ */
+uint32_t USART_GetClockSrc(const CM_USART_TypeDef *USARTx)
+{
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+
+ return READ_REG32_BIT(USARTx->CR2, USART_CR2_CLKC_1);
+}
+
+/**
+ * @brief Enable or disable USART noise filter.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void USART_FilterCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(USARTx->CR1, USART_CR1_NFE);
+ } else {
+ CLR_REG32_BIT(USARTx->CR1, USART_CR1_NFE);
+ }
+}
+
+/**
+ * @brief Enable or disable USART silence.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void USART_SilenceCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(USARTx->CR1, USART_CR1_SLME);
+ } else {
+ CLR_REG32_BIT(USARTx->CR1, USART_CR1_SLME);
+ }
+}
+
+/**
+ * @brief Set UART hardware flow control CTS/RTS selection.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] u32HWFlowControl USART hardware flow control CTS/RTS selection
+ * This parameter can be one of the macros group @ref USART_Hardware_Flow_Control.
+ * @retval None
+ */
+void USART_SetHWFlowControl(CM_USART_TypeDef *USARTx, uint32_t u32HWFlowControl)
+{
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_HW_FLOWCTRL(u32HWFlowControl));
+
+ MODIFY_REG32(USARTx->CR3, (USART_CR3_CTSE | USART_CR3_RTSE), u32HWFlowControl);
+}
+
+/**
+ * @brief USART receive data.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @retval Receive data
+ */
+uint16_t USART_ReadData(const CM_USART_TypeDef *USARTx)
+{
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+
+ return READ_REG16(USARTx->RDR);
+}
+
+/**
+ * @brief USART send data.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] u16Data Transmit data
+ * @retval None
+ */
+void USART_WriteData(CM_USART_TypeDef *USARTx, uint16_t u16Data)
+{
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_DATA(u16Data));
+
+ WRITE_REG16(USARTx->TDR, u16Data);
+}
+
+/**
+ * @brief USART send processor ID.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ ** @param [in] u16ID Processor ID
+ * @retval None
+ */
+void USART_WriteID(CM_USART_TypeDef *USARTx, uint16_t u16ID)
+{
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_DATA(u16ID));
+
+ WRITE_REG16(USARTx->TDR, (USART_TDR_MPID | u16ID));
+}
+
+/**
+ * @brief Set USART baudrate.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] u32Baudrate UART baudrate
+ * @param [out] pf32Error E(%) baudrate error rate
+ * @retval int32_t:
+ * - LL_OK: Set successfully.
+ * - LL_ERR_INVD_PARAM: Set unsuccessfully.
+ * @note The function uses fraction division to ensure baudrate accuracy if USART unit supports baudrate fraction division.
+ */
+int32_t USART_SetBaudrate(CM_USART_TypeDef *USARTx, uint32_t u32Baudrate, float32_t *pf32Error)
+{
+ uint32_t u32Mode;
+ stc_usart_brr_t stcUsartBrr;
+ int32_t i32Ret;
+
+ DDL_ASSERT(u32Baudrate > 0UL);
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+
+ /* Get USART clock frequency */
+ stcUsartBrr.u32UsartClock = USART_GetUsartClockFreq(USARTx);
+ stcUsartBrr.u32Baudrate = u32Baudrate;
+ stcUsartBrr.f32Error = 0.0F;
+ stcUsartBrr.u32Fraction = 0xFFUL;
+
+ /* Get usart mode */
+ u32Mode = READ_REG32_BIT(USARTx->CR1, USART_CR1_MS);
+ /* Calculate baudrate for BRR */
+ if (0UL == u32Mode) {
+ if (0UL == READ_REG32_BIT(USARTx->CR3, USART_CR3_SCEN)) {
+ /* uart mode */
+ i32Ret = UART_CalculateBrr(USARTx, &stcUsartBrr);
+ } else {
+ /* Smart_card function */
+ i32Ret = SmartCard_CalculateBrr(USARTx, &stcUsartBrr);
+ }
+ } else {
+ /* Clock sync mode */
+ i32Ret = ClockSync_CalculateBrr(USARTx, &stcUsartBrr);
+ }
+
+ if (LL_OK == i32Ret) {
+ /* Set BRR value(integer & fraction) */
+ MODIFY_REG32(USARTx->BRR, (USART_BRR_DIV_INTEGER | USART_BRR_DIV_FRACTION), \
+ (stcUsartBrr.u32Fraction | (stcUsartBrr.u32Integer << USART_BRR_DIV_INTEGER_POS)));
+
+ if (0xFFUL != stcUsartBrr.u32Fraction) {
+ SET_REG32_BIT(USARTx->CR1, USART_CR1_FBME);
+ }
+ } else {
+ /* rsvd */
+ }
+ if (NULL != pf32Error) {
+ *pf32Error = stcUsartBrr.f32Error;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Set USART Smartcard ETU Clock.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] u32EtuClock USART Smartcard ETU Clock.
+ * This parameter can be one of the macros group @ref USART_Smartcard_ETU_Clock
+ * @arg USART_SC_ETU_CLK32: 1 etu = 32/f
+ * @arg USART_SC_ETU_CLK64: 1 etu = 64/f
+ * @arg USART_SC_ETU_CLK128: 1 etu = 128/f
+ * @arg USART_SC_ETU_CLK256: 1 etu = 256/f
+ * @arg USART_SC_ETU_CLK372: 1 etu = 372/f
+ * @retval None
+ */
+void USART_SmartCard_SetEtuClock(CM_USART_TypeDef *USARTx, uint32_t u32EtuClock)
+{
+ DDL_ASSERT(IS_USART_SMARTCARD_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_SMARTCARD_ETU_CLK(u32EtuClock));
+
+ MODIFY_REG32(USARTx->CR3, USART_CR3_BCN, u32EtuClock);
+}
+
+/**
+ * @brief Enable/disable stop mode noise filter.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void USART_StopModeNoiseFilterCmd(const CM_USART_TypeDef *USARTx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_USART_STOP_MD_UNIT(USARTx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(CM_PERIC->USART1_NFC, PERIC_USART1_NFC_USART1_NFE);
+ } else {
+ CLR_REG32_BIT(CM_PERIC->USART1_NFC, PERIC_USART1_NFC_USART1_NFE);
+ }
+}
+
+/**
+ * @brief Set stop mode noise filter.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] u32Level The noise filter width level value
+ * This parameter can be one of the macros group @ref USART_Stop_Mode_Noise_Filter_Width_Level
+ * @arg USART_STOP_MD_FILTER_LVL1: Filter width level 1
+ * @arg USART_STOP_MD_FILTER_LVL2: Filter width level 2
+ * @arg USART_STOP_MD_FILTER_LVL3: Filter width level 3
+ * @arg USART_STOP_MD_FILTER_LVL4: Filter width level 4
+ * @retval None
+ */
+void USART_SetStopModeNoiseFilter(const CM_USART_TypeDef *USARTx, uint32_t u32Level)
+{
+ DDL_ASSERT(IS_USART_STOP_MD_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_STOP_MD_FILTER(u32Level));
+
+ MODIFY_REG32(CM_PERIC->USART1_NFC, PERIC_USART1_NFC_USASRT1_NFS, u32Level);
+}
+
+/**
+ * @brief Enable or disable USART loopback function.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void USART_LIN_LoopbackCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_USART_LIN_UNIT(USARTx));
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+
+ if (ENABLE == enNewState) {
+ SET_REG32_BIT(USARTx->CR3, USART_CR3_LOOP);
+ } else {
+ CLR_REG32_BIT(USARTx->CR3, USART_CR3_LOOP);
+ }
+}
+
+/**
+ * @brief Set USART LIN counter clock prescaler division.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] u32ClockDiv USART USART LIN counter clock prescaler division.
+ * This parameter can be one of the macros group @ref USART_LIN_BMC_Clock_Division
+ * @arg USART_LIN_BMC_CLK_DIV1: CLK
+ * @arg USART_LIN_BMC_CLK_DIV2: CLK/2
+ * @arg USART_LIN_BMC_CLK_DIV4: CLK/4
+ * @arg USART_LIN_BMC_CLK_DIV8: CLK/8
+ * @retval None
+ * @note The clock division function is valid when clock source is internal clock.
+ */
+void USART_LIN_SetBmcClockDiv(CM_USART_TypeDef *USARTx, uint32_t u32ClockDiv)
+{
+ DDL_ASSERT(IS_USART_LIN_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_LIN_BMC_CLK_DIV(u32ClockDiv));
+
+ MODIFY_REG32(USARTx->PR, USART_PR_LBMPSC, u32ClockDiv);
+}
+
+/**
+ * @brief LIN Request break sending
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @retval None
+ */
+void USART_LIN_RequestBreakSending(CM_USART_TypeDef *USARTx)
+{
+ DDL_ASSERT(IS_USART_LIN_UNIT(USARTx));
+
+ SET_REG32_BIT(USARTx->CR2, USART_CR2_SBK);
+}
+
+/**
+ * @brief Get request break sending status
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t USART_LIN_GetRequestBreakStatus(const CM_USART_TypeDef *USARTx)
+{
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+
+ return (0UL == READ_REG32_BIT(USARTx->CR2, USART_CR2_SBK)) ? RESET : SET;
+}
+
+/**
+ * @brief Set send break mode for USART LIN.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] u32Mode USART send break mode
+ * This parameter can be one of the macros group @ref USART_LIN_Send_Break_Mode
+ * @arg USART_LIN_SEND_BREAK_MD_SBK: Start send break after USART_CR2 SBK bit set 1 value
+ * @arg USART_LIN_SEND_BREAK_MD_TDR: Start send break after USART_DR TDR write 0x00 value
+ * @retval None
+ */
+void USART_LIN_SetBreakMode(CM_USART_TypeDef *USARTx, uint32_t u32Mode)
+{
+ DDL_ASSERT(IS_USART_LIN_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_LIN_SEND_BREAK_MD(u32Mode));
+
+ MODIFY_REG32(USARTx->CR2, USART_CR2_SBKM, u32Mode);
+}
+
+/**
+ * @brief Get send break mode for USART LIN.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @retval Returned value can be one of the following values:
+ * - USART_LIN_SEND_BREAK_MD_SBK: Start send break after USART_CR2 SBK bit set 1 value
+ * - USART_LIN_SEND_BREAK_MD_TDR: Start send break after USART_DR TDR write 0x00 value
+ */
+uint32_t USART_LIN_GetBreakMode(const CM_USART_TypeDef *USARTx)
+{
+ DDL_ASSERT(IS_USART_LIN_UNIT(USARTx));
+
+ return READ_REG32_BIT(USARTx->CR2, USART_CR2_SBKM);
+}
+
+/**
+ * @brief Get USART LIN baudrate measure count.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @retval LIN baudrate measure count value
+ */
+uint32_t USART_LIN_GetMeasureCount(const CM_USART_TypeDef *USARTx)
+{
+ DDL_ASSERT(IS_USART_LIN_UNIT(USARTx));
+
+ return READ_REG32_BIT(USARTx->LBMC, USART_LBMC_LBMC);
+}
+
+/**
+ * @brief Get USART LIN baudrate measure count.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @retval LIN baudrate measure count value
+ */
+uint32_t USART_LIN_GetMeasureBaudrate(const CM_USART_TypeDef *USARTx)
+{
+ uint32_t u32BmClk;
+ uint32_t u32LBMC;
+
+ DDL_ASSERT(IS_USART_LIN_UNIT(USARTx));
+
+ u32BmClk = USART_GetLinBmcClockFreq(USARTx);
+ u32LBMC = READ_REG32_BIT(USARTx->LBMC, USART_LBMC_LBMC);
+
+ return (u32LBMC > 0UL) ? (u32BmClk / u32LBMC) : 0UL;
+}
+
+/**
+ * @brief Set USART LIN break detection length.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] u32Len USART clock prescaler division.
+ * This parameter can be one of the macros group @ref USART_LIN_Detect_Break_Length
+ * @arg USART_LIN_DETECT_BREAK_10BIT: 10-bit break detection
+ * @arg USART_LIN_DETECT_BREAK_11BIT: 11-bit break detection
+ * @retval None
+ */
+void USART_LIN_SetDetectBreakLen(CM_USART_TypeDef *USARTx, uint32_t u32Len)
+{
+ DDL_ASSERT(IS_USART_LIN_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_LIN_DETECT_BREAK_LEN(u32Len));
+
+ MODIFY_REG32(USARTx->CR2, USART_CR2_LBDL, u32Len);
+}
+
+/**
+ * @brief Set USART LIN break sending length.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] u32Len USART clock prescaler division.
+ * This parameter can be one of the macros group @ref USART_LIN_Send_Break_Length
+ * @arg USART_LIN_SEND_BREAK_10BIT: Send break 10-bit
+ * @arg USART_LIN_SEND_BREAK_11BIT: Send break 11-bit
+ * @arg USART_LIN_SEND_BREAK_13BIT: Send break 13-bit
+ * @arg USART_LIN_SEND_BREAK_14BIT: Send break 14-bit
+ * @retval None
+ */
+void USART_LIN_SetSendBreakLen(CM_USART_TypeDef *USARTx, uint32_t u32Len)
+{
+ DDL_ASSERT(IS_USART_LIN_UNIT(USARTx));
+ DDL_ASSERT(IS_USART_LIN_SEND_BREAK_LEN(u32Len));
+
+ MODIFY_REG32(USARTx->CR2, USART_CR2_SBKL, u32Len);
+}
+
+/**
+ * @brief UART transmit data in polling mode.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [out] pvBuf The pointer to data transmitted buffer
+ * @param [in] u32Len Amount of frame to be sent.
+ * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout)
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_TIMEOUT: Communicate timeout.
+ * - LL_ERR_INVD_PARAM: u32Len value is 0 or pvBuf is NULL.
+ * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT
+ */
+int32_t USART_UART_Trans(CM_USART_TypeDef *USARTx, const void *pvBuf, uint32_t u32Len, uint32_t u32Timeout)
+{
+ uint32_t i;
+ uint32_t u32DataWidth;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+
+ if ((NULL != pvBuf) && (u32Len > 0UL)) {
+ u32DataWidth = READ_REG32_BIT(USARTx->CR1, USART_CR1_M);
+
+ if ((USART_DATA_WIDTH_8BIT == u32DataWidth) || (USART_DATA_WIDTH_9BIT == u32DataWidth)) {
+ for (i = 0UL; i < u32Len; i++) {
+ /* Wait TX buffer empty. */
+ i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_EMPTY, SET, u32Timeout);
+ if (LL_OK != i32Ret) {
+ break;
+ }
+
+ if (u32DataWidth == USART_DATA_WIDTH_8BIT) {
+ USART_WriteData(USARTx, ((const uint8_t *)pvBuf)[i]);
+ } else {
+ USART_WriteData(USARTx, ((const uint16_t *)pvBuf)[i]);
+ }
+ }
+
+ if (LL_OK == i32Ret) {
+ i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_CPLT, SET, u32Timeout);
+ }
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief UART receive data in polling mode.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [out] pvBuf The pointer to data received buffer
+ * @param [in] u32Len Amount of frame to be received.
+ * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout)
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_TIMEOUT: Communicate timeout.
+ * - LL_ERR_INVD_PARAM: u32Len value is 0 or the pointer pvBuf value is NULL.
+ * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT
+ */
+int32_t USART_UART_Receive(const CM_USART_TypeDef *USARTx, void *pvBuf, uint32_t u32Len, uint32_t u32Timeout)
+{
+ uint32_t u32Count;
+ uint32_t u32DataWidth;
+ uint16_t u16ReceiveData;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+
+ if ((NULL != pvBuf) && (u32Len > 0UL)) {
+ u32DataWidth = READ_REG32_BIT(USARTx->CR1, USART_CR1_M);
+
+ for (u32Count = 0UL; u32Count < u32Len; u32Count++) {
+ i32Ret = USART_WaitStatus(USARTx, USART_FLAG_RX_FULL, SET, u32Timeout);
+ if (LL_OK == i32Ret) {
+ u16ReceiveData = USART_ReadData(USARTx);
+ if (USART_DATA_WIDTH_8BIT == u32DataWidth) {
+ ((uint8_t *)pvBuf)[u32Count] = (uint8_t)(u16ReceiveData & 0xFFU);
+ } else {
+ ((uint16_t *)pvBuf)[u32Count] = (uint16_t)(u16ReceiveData & 0x1FFU);
+ }
+ } else {
+ break;
+ }
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Clock sync transmit && receive data in polling mode.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] au8Buf The pointer to data transmitted buffer
+ * @param [in] u32Len Amount of data to be transmitted.
+ * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout)
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_TIMEOUT: Communicate timeout.
+ * - LL_ERR_INVD_PARAM: u32Len value is 0 or the pointer au8Buf value is NULL.
+ * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT
+ */
+int32_t USART_ClockSync_Trans(CM_USART_TypeDef *USARTx, const uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout)
+{
+ uint32_t i;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+
+ if ((NULL != au8Buf) && (u32Len > 0UL)) {
+ for (i = 0UL; i < u32Len; i++) {
+ /* Wait TX buffer empty. */
+ i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_EMPTY, SET, u32Timeout);
+ if (LL_OK == i32Ret) {
+ USART_WriteData(USARTx, au8Buf[i]);
+ if (READ_REG32_BIT(USARTx->CR1, USART_RX) != 0UL) {
+ i32Ret = USART_WaitStatus(USARTx, USART_FLAG_RX_FULL, SET, u32Timeout);
+ if (LL_OK == i32Ret) {
+ (void)USART_ReadData(USARTx);
+ }
+ }
+ }
+
+ if (LL_OK != i32Ret) {
+ break;
+ }
+ }
+
+ if (LL_OK == i32Ret) {
+ i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_CPLT, SET, u32Timeout);
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Clock sync receive data in polling mode.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [out] au8Buf The pointer to data received buffer
+ * @param [in] u32Len Amount of data to be sent and received.
+ * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout)
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_TIMEOUT: Communicate timeout.
+ * - LL_ERR_INVD_PARAM: u32Len value is 0 or the pointer au8Buf value is NULL.
+ * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT.
+ */
+int32_t USART_ClockSync_Receive(CM_USART_TypeDef *USARTx, uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout)
+{
+ uint32_t i;
+ en_functional_state_t enTX;
+ en_functional_state_t enMasterMode;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+
+ if ((NULL != au8Buf) && (u32Len > 0UL)) {
+ i32Ret = LL_OK;
+ enTX = (READ_REG32_BIT(USARTx->CR1, USART_TX) == 0UL) ? DISABLE : ENABLE;
+ enMasterMode = (USART_CLK_SRC_EXTCLK == READ_REG32_BIT(USARTx->CR2, USART_CR2_CLKC)) ? DISABLE : ENABLE;
+
+ for (i = 0UL; i < u32Len; i++) {
+ if ((ENABLE == enMasterMode) || (ENABLE == enTX)) {
+ USART_WriteData(USARTx, 0xFFU);
+
+ /* Wait TX buffer empty. */
+ i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_EMPTY, SET, u32Timeout);
+ }
+
+ if (LL_OK == i32Ret) {
+ i32Ret = USART_WaitStatus(USARTx, USART_FLAG_RX_FULL, SET, u32Timeout);
+ if (LL_OK == i32Ret) {
+ au8Buf[i] = (uint8_t)USART_ReadData(USARTx);
+ }
+ }
+
+ if (LL_OK != i32Ret) {
+ break;
+ }
+ }
+
+ if (LL_OK == i32Ret) {
+ i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_CPLT, SET, u32Timeout);
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Clock sync transmit && receive data in polling mode.
+ * @param [in] USARTx Pointer to USART instance register base
+ * This parameter can be one of the following values:
+ * @arg CM_USARTx: USART unit instance register base
+ * @param [in] au8TxBuf The pointer to data transmitted buffer
+ * @param [out] au8RxBuf The pointer to data received buffer
+ * @param [in] u32Len Amount of data to be sent and received.
+ * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout)
+ * @retval int32_t:
+ * - LL_OK: No errors occurred.
+ * - LL_ERR_TIMEOUT: Communicate timeout.
+ * - LL_ERR_INVD_PARAM: u32Len value is 0.
+ * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT.
+ */
+int32_t USART_ClockSync_TransReceive(CM_USART_TypeDef *USARTx, const uint8_t au8TxBuf[], uint8_t au8RxBuf[],
+ uint32_t u32Len, uint32_t u32Timeout)
+{
+ uint32_t i;
+ uint8_t u8ReceiveData;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ DDL_ASSERT(IS_USART_UNIT(USARTx));
+
+ if (u32Len > 0UL) {
+ for (i = 0UL; i < u32Len; i++) {
+ if (NULL != au8TxBuf) {
+ USART_WriteData(USARTx, au8TxBuf[i]);
+ } else {
+ USART_WriteData(USARTx, 0xFFU);
+ }
+
+ /* Wait TX buffer empty. */
+ i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_EMPTY, SET, u32Timeout);
+ if (LL_OK == i32Ret) {
+ i32Ret = USART_WaitStatus(USARTx, USART_FLAG_RX_FULL, SET, u32Timeout);
+ if (LL_OK == i32Ret) {
+ u8ReceiveData = (uint8_t)USART_ReadData(USARTx);
+ if (NULL != au8RxBuf) {
+ au8RxBuf[i] = u8ReceiveData;
+ }
+ }
+ }
+
+ if (LL_OK != i32Ret) {
+ break;
+ }
+ }
+
+ if (LL_OK == i32Ret) {
+ i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_CPLT, SET, u32Timeout);
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_USART_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_usb.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_usb.c
new file mode 100644
index 0000000000..cb1498cd21
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_usb.c
@@ -0,0 +1,1348 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_usb.c
+ * @brief USB core driver.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Add API USB_DeInit()
+ 2023-09-30 CDT Fix bug for function usb_clearepstall()
+ Modify typo
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_usb.h"
+#include "usb_bsp.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_USB USB
+ * @brief USB Driver Library
+ * @{
+ */
+
+#if (LL_USB_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/* Parameters check */
+#define IS_USB_CORE_ID(x) \
+( ((x) == USBFS_CORE_ID))
+
+#define IS_USB_PHY_TYPE(x) \
+( ((x) == USBHS_PHY_EMBED))
+
+#define USB_RMU_TIMEOUT (100UL)
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup USB_Global_Functions USB Global Functions
+ * @{
+ */
+
+/**
+ * @brief core software reset
+ * @param [in] USBx usb instance
+ * @retval None
+ */
+void usb_coresoftrst(LL_USB_TypeDef *USBx)
+{
+ __IO uint8_t u8Status = USB_OK;;
+ __IO uint32_t u32grstctl = 0UL;
+ __IO uint32_t u32Count = 0UL;
+
+ /* Wait for AHB master to be idle. */
+ do {
+ usb_udelay(1UL);
+ u32grstctl = READ_REG32(USBx->GREGS->GRSTCTL);
+ if (++u32Count > 100000UL) {
+ u8Status = USB_ERROR;
+ }
+ } while (0UL == (u32grstctl & USBFS_GRSTCTL_AHBIDL));
+
+ if (USB_OK == u8Status) {
+ /* Write the Core Soft Reset bit to reset the USB core */
+ u32Count = 0UL;
+ u32grstctl |= USBFS_GRSTCTL_CSRST;
+ WRITE_REG32(USBx->GREGS->GRSTCTL, u32grstctl);
+
+ /* Wait for the reset finishing */
+ do {
+ u32grstctl = READ_REG32(USBx->GREGS->GRSTCTL);
+ if (u32Count > 100000UL) {
+ break;
+ }
+ u32Count++;
+ usb_udelay(1UL);
+ } while (0UL == (u32grstctl & USBFS_GRSTCTL_CSFTRSTDONE));
+ /* Clear reset done status */
+ SET_REG32_BIT(USBx->GREGS->GRSTCTL, USBFS_GRSTCTL_CSFTRSTDONE);
+ /* Releae reset status */
+ CLR_REG32_BIT(USBx->GREGS->GRSTCTL, USBFS_GRSTCTL_CSRST);
+ /* Wait for at least 3 PHY clocks after the core resets */
+ usb_udelay(3UL);
+ }
+}
+
+/**
+ * @brief Writes a packet whose byte number is len into the Tx FIFO associated
+ * with the EP
+ * @param [in] USBx usb instance
+ * @param [in] src source pointer used to hold the transmitted data
+ * @param [in] ch_ep_num end point index
+ * @param [in] len length in bytes
+ * @param [in] u8DmaEn USB DMA status
+ * @retval None
+ */
+void usb_wrpkt(LL_USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t u8DmaEn)
+{
+ __IO uint32_t u32pAddr;
+ __IO uint32_t *fifo;
+ uint32_t u32Count32b;
+ uint32_t u32Tmp;
+ if (u8DmaEn == 0U) {
+ u32Count32b = (len + 3UL);
+ u32Count32b = u32Count32b >> 2U;
+ fifo = USBx->DFIFO[ch_ep_num];
+ u32Tmp = 0UL;
+ while (u32Tmp < u32Count32b) {
+ WRITE_REG32(*fifo, *((uint32_t *)src));
+ u32pAddr = (uint32_t)src;
+ src = (uint8_t *)(u32pAddr + 4U);
+ u32Tmp++;
+ }
+ }
+}
+
+/**
+ * @brief Reads a packet whose byte number is len from the Rx FIFO
+ * @param [in] USBx usb instance
+ * @param [in] dest destination pointer that point to the received data
+ * @param [in] len number of bytes
+ * @retval None
+ */
+void usb_rdpkt(LL_USB_TypeDef *USBx, uint8_t *dest, uint16_t len)
+{
+ uint32_t u32Tmp;
+ __IO uint32_t u32Count32b;
+ __IO uint32_t u32pAddr;
+
+ __IO uint32_t *fifo = USBx->DFIFO[0];
+ u32Count32b = (len + 3UL);
+ u32Count32b = u32Count32b >> 2U;
+ u32pAddr = 0UL;
+ u32Tmp = 0UL;
+ while (u32Tmp < u32Count32b) {
+ *(uint32_t *)dest = READ_REG32(*fifo);
+ u32pAddr = (uint32_t)dest;
+ dest = (uint8_t *)(u32pAddr + 4U);
+ u32Tmp++;
+ }
+}
+
+/**
+ * @brief Initialize the addresses of the core registers.
+ * @param [in] USBx usb instance
+ * @param [in] pstcPortIdentify usb core and phy select
+ * @param [in] basic_cfgs usb core basic cfgs
+ * @retval None
+ */
+void usb_setregaddr(LL_USB_TypeDef *USBx, stc_usb_port_identify *pstcPortIdentify, USB_CORE_BASIC_CFGS *basic_cfgs)
+{
+ uint32_t u32Tmp = 0UL;
+ uint32_t u32baseAddr = CM_USBFS_BASE;
+ DDL_ASSERT(IS_USB_CORE_ID(pstcPortIdentify->u8CoreID));
+#if defined (USB_INTERNAL_DMA_ENABLED)
+ basic_cfgs->dmaen = 1U;
+#else
+ basic_cfgs->dmaen = 0U;
+#endif
+ /* initialize device cfg following its address */
+ basic_cfgs->host_chnum = USB_MAX_CH_NUM;
+ basic_cfgs->dev_epnum = USB_MAX_EP_NUM;
+ basic_cfgs->core_type = pstcPortIdentify->u8CoreID;
+ basic_cfgs->phy_type = USBHS_PHY_EMBED;
+ if (USBFS_CORE_ID == pstcPortIdentify->u8CoreID) {
+#ifdef USB_FS_MODE
+ u32baseAddr = CM_USBFS_BASE;
+#endif
+ } else {
+#ifdef USB_HS_MODE
+ u32baseAddr = CM_USBHS_BASE;
+#endif
+ }
+
+ USBx->GREGS = (USB_CORE_GREGS *)(u32baseAddr + 0UL);
+ USBx->DREGS = (USB_CORE_DREGS *)(u32baseAddr + 0x800UL);
+
+ while (u32Tmp < basic_cfgs->dev_epnum) {
+ USBx->INEP_REGS[u32Tmp] = (USB_CORE_INEPREGS *)(u32baseAddr + 0x900UL + (u32Tmp * 0x20UL));
+ USBx->OUTEP_REGS[u32Tmp] = (USB_CORE_OUTEPREGS *)(u32baseAddr + 0xb00UL + (u32Tmp * 0x20UL));
+ u32Tmp++;
+ }
+ u32Tmp = 0UL;
+ while (u32Tmp < basic_cfgs->dev_epnum) {
+ USBx->DFIFO[u32Tmp] = (uint32_t *)(u32baseAddr + 0x1000UL + (u32Tmp * 0x1000UL));
+ u32Tmp++;
+ }
+ USBx->GCCTL = (uint32_t *)(u32baseAddr + 0xe00UL);
+#ifdef USE_HOST_MODE /* if the application mode is host */
+ USBx->HREGS = (USB_CORE_HREGS *)(u32baseAddr + 0x400UL);
+ USBx->HPRT = (uint32_t *)(u32baseAddr + 0x440UL);
+ u32Tmp = 0UL;
+ while (u32Tmp < basic_cfgs->host_chnum) {
+ USBx->HC_REGS[u32Tmp] = (USB_CORE_HC_REGS *)(u32baseAddr + 0x500UL + (u32Tmp * 0x20UL));
+ u32Tmp++;
+ }
+#endif /* USE_HOST_MODE */
+}
+
+/**
+ * @brief Initializes the USB controller registers and prepares the core
+ * device mode or host mode operation.
+ * @param [in] USBx usb instance
+ * @param [in] basic_cfgs usb core basic cfgs
+ * @retval None
+ */
+void usb_initusbcore(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs)
+{
+ /* reset the core through core soft reset */
+ usb_coresoftrst(USBx);
+
+ /* Select PHY for USB core*/
+ usb_PhySelect(USBx, basic_cfgs->phy_type);
+ /* reset the core through core soft reset */
+ usb_coresoftrst(USBx);
+ usb_mdelay(20UL);
+ if (basic_cfgs->dmaen == 1U) {
+ /* burst length/type(HBstLen) 64-words x32-bit, core operates in a DMA mode*/
+ usb_BurstLenConfig(USBx, 5U);
+ usb_DmaCmd(USBx, 1U);
+ }
+}
+
+/**
+ * @brief Flush a Tx FIFO whose index is num
+ * @param [in] USBx usb instance
+ * @param [in] num txFIFO index
+ * @retval None
+ */
+void usb_txfifoflush(LL_USB_TypeDef *USBx, uint32_t num)
+{
+ __IO uint32_t u32grstctl;
+ __IO uint32_t u32Tmp = 0UL;
+
+ u32grstctl = USBFS_GRSTCTL_TXFFLSH | ((num & 0x1FUL) << USBFS_GRSTCTL_TXFNUM_POS);
+ /* set the TxFIFO Flush bit, set TxFIFO Number */
+ WRITE_REG32(USBx->GREGS->GRSTCTL, u32grstctl);
+
+ /* wait for the finishing of txFIFO flushing */
+ do {
+ u32grstctl = READ_REG32(USBx->GREGS->GRSTCTL);
+ if (u32Tmp <= 200000UL) {
+ u32Tmp++;
+ } else {
+ break;
+ }
+ usb_udelay(1UL);
+ } while (0UL != (u32grstctl & USBFS_GRSTCTL_TXFFLSH));
+ /* Wait for at least 3 PHY clocks after the txfifo has been flushed */
+ usb_udelay(3UL);
+}
+
+/**
+ * @brief Flush the whole rxFIFO
+ * @param [in] USBx usb instance
+ * @retval None
+ */
+void usb_rxfifoflush(LL_USB_TypeDef *USBx)
+{
+ __IO uint32_t u32grstctl;
+ __IO uint32_t u32Tmp = 0UL;
+
+ u32grstctl = USBFS_GRSTCTL_RXFFLSH; /* set the RxFIFO Flush bit */
+ WRITE_REG32(USBx->GREGS->GRSTCTL, u32grstctl);
+ /* wait for the finishing of rxFIFO flushing */
+ do {
+ u32grstctl = READ_REG32(USBx->GREGS->GRSTCTL);
+ if (u32Tmp <= 200000UL) {
+ u32Tmp++;
+ } else {
+ break;
+ }
+ usb_udelay(1UL);
+ } while (0UL != (u32grstctl & USBFS_GRSTCTL_RXFFLSH));
+ /* Wait for at least 3 PHY clocks after the rxfifo has been flushed */
+ usb_udelay(3UL);
+}
+
+/**
+ * @brief set the core to be host mode or device mode through the second
+ * input parameter.
+ * @param [in] USBx usb instance
+ * @param [in] mode mode of HOST_MODE or DEVICE_MODE that the core would be
+ * @retval None
+ */
+void usb_modeset(LL_USB_TypeDef *USBx, uint8_t mode)
+{
+ if (mode == HOST_MODE) {
+ MODIFY_REG32(USBx->GREGS->GUSBCFG, USBFS_GUSBCFG_FHMOD | USBFS_GUSBCFG_FDMOD, USBFS_GUSBCFG_FHMOD);
+ } else {
+ MODIFY_REG32(USBx->GREGS->GUSBCFG, USBFS_GUSBCFG_FHMOD | USBFS_GUSBCFG_FDMOD, USBFS_GUSBCFG_FDMOD);
+ }
+ /* wate for the change to take effect */
+ usb_mdelay(50UL);
+}
+
+#ifdef USE_DEVICE_MODE
+
+/**
+ * @brief initializes the initial status of all endpoints of the device to be
+ * disable.
+ * @param [in] USBx usb instance
+ * @param [in] u8EpNum EP number
+ * @retval None
+ */
+void usb_devepdis(LL_USB_TypeDef *USBx, uint8_t u8EpNum)
+{
+ uint8_t u8Tmp = 0U;
+
+ while (u8Tmp < u8EpNum) {
+ if (0UL != READ_REG32_BIT(USBx->INEP_REGS[u8Tmp]->DIEPCTL, USBFS_DIEPCTL_EPENA)) {
+ WRITE_REG32(USBx->INEP_REGS[u8Tmp]->DIEPCTL, USBFS_DIEPCTL_EPDIS | USBFS_DIEPCTL_SNAK);
+ } else {
+ WRITE_REG32(USBx->INEP_REGS[u8Tmp]->DIEPCTL, 0UL);
+ }
+ WRITE_REG32(USBx->INEP_REGS[u8Tmp]->DIEPTSIZ, 0UL);
+ WRITE_REG32(USBx->INEP_REGS[u8Tmp]->DIEPINT, 0xFFUL);
+ u8Tmp++;
+ }
+
+ u8Tmp = 0U;
+ while (u8Tmp < u8EpNum) {
+ if (0UL != READ_REG32_BIT(USBx->OUTEP_REGS[u8Tmp]->DOEPCTL, USBFS_DOEPCTL_EPENA)) {
+ WRITE_REG32(USBx->OUTEP_REGS[u8Tmp]->DOEPCTL, USBFS_DOEPCTL_EPDIS | USBFS_DOEPCTL_SNAK);
+ } else {
+ WRITE_REG32(USBx->OUTEP_REGS[u8Tmp]->DOEPCTL, 0UL);
+ }
+ WRITE_REG32(USBx->OUTEP_REGS[u8Tmp]->DOEPTSIZ, 0UL);
+ WRITE_REG32(USBx->OUTEP_REGS[u8Tmp]->DOEPINT, 0xFFUL);
+ u8Tmp++;
+ }
+}
+
+#ifdef USB_FS_MODE
+static void usb_DevFSFifoConfig(LL_USB_TypeDef *USBx)
+{
+ uint32_t u32StardAddr;
+
+ WRITE_REG32(USBx->GREGS->GRXFSIZ, RX_FIFO_FS_SIZE);
+ /* set txFIFO and rxFIFO size of EP0 */
+ u32StardAddr = RX_FIFO_FS_SIZE;
+ WRITE_REG32(USBx->GREGS->HNPTXFSIZ,
+ (RX_FIFO_FS_SIZE << USBFS_HNPTXFSIZ_NPTXFSA_POS) | (TX0_FIFO_FS_SIZE << USBFS_HNPTXFSIZ_NPTXFD_POS));
+ /* set txFIFO size of EP1 */
+ u32StardAddr += TX0_FIFO_FS_SIZE;
+ WRITE_REG32(USBx->GREGS->DIEPTXF[0],
+ (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX1_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS));
+ /* set txFIFO size of EP2 */
+ u32StardAddr += TX1_FIFO_FS_SIZE;
+ WRITE_REG32(USBx->GREGS->DIEPTXF[1],
+ (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX2_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS));
+ /* set txFIFO size of EP3 */
+ u32StardAddr += TX2_FIFO_FS_SIZE;
+ WRITE_REG32(USBx->GREGS->DIEPTXF[2],
+ (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX3_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS));
+ /* set txFIFO size of EP4 */
+ u32StardAddr += TX3_FIFO_FS_SIZE;
+ WRITE_REG32(USBx->GREGS->DIEPTXF[3],
+ (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX4_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS));
+ /* set txFIFO size of EP5 */
+ u32StardAddr += TX4_FIFO_FS_SIZE;
+ WRITE_REG32(USBx->GREGS->DIEPTXF[4],
+ (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX5_FIFO_FS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS));
+}
+#endif
+
+#ifdef USB_HS_MODE
+static void usb_DevHSFifoConfig(LL_USB_TypeDef *USBx)
+{
+ uint32_t u32StardAddr;
+
+ WRITE_REG32(USBx->GREGS->GRXFSIZ, RX_FIFO_HS_SIZE);
+ /* set txFIFO and rxFIFO size of EP0 */
+ u32StardAddr = RX_FIFO_HS_SIZE;
+ WRITE_REG32(USBx->GREGS->HNPTXFSIZ,
+ (RX_FIFO_HS_SIZE << USBFS_HNPTXFSIZ_NPTXFSA_POS) | (TX0_FIFO_HS_SIZE << USBFS_HNPTXFSIZ_NPTXFD_POS));
+ /* set txFIFO size of EP1 */
+ u32StardAddr += TX0_FIFO_HS_SIZE;
+ WRITE_REG32(USBx->GREGS->DIEPTXF[0],
+ (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX1_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS));
+ /* set txFIFO size of EP2 */
+ u32StardAddr += TX1_FIFO_HS_SIZE;
+ WRITE_REG32(USBx->GREGS->DIEPTXF[1],
+ (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX2_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS));
+ /* set txFIFO size of EP3 */
+ u32StardAddr += TX2_FIFO_HS_SIZE;
+ WRITE_REG32(USBx->GREGS->DIEPTXF[2],
+ (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX3_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS));
+ /* set txFIFO size of EP4 */
+ u32StardAddr += TX3_FIFO_HS_SIZE;
+ WRITE_REG32(USBx->GREGS->DIEPTXF[3],
+ (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX4_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS));
+ /* set txFIFO size of EP5 */
+ u32StardAddr += TX4_FIFO_HS_SIZE;
+ WRITE_REG32(USBx->GREGS->DIEPTXF[4],
+ (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX5_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS));
+ /* set txFIFO size of EP6 */
+ u32StardAddr += TX5_FIFO_HS_SIZE;
+ WRITE_REG32(USBx->GREGS->DIEPTXF[5],
+ (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX6_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS));
+ /* set txFIFO size of EP7 */
+ u32StardAddr += TX6_FIFO_HS_SIZE;
+ WRITE_REG32(USBx->GREGS->DIEPTXF[6],
+ (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX7_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS));
+ /* set txFIFO size of EP8 */
+ u32StardAddr += TX7_FIFO_HS_SIZE;
+ WRITE_REG32(USBx->GREGS->DIEPTXF[7],
+ (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX8_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS));
+ /* set txFIFO size of EP9 */
+ u32StardAddr += TX8_FIFO_HS_SIZE;
+ WRITE_REG32(USBx->GREGS->DIEPTXF[8],
+ (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX9_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS));
+ /* set txFIFO size of EP10 */
+ u32StardAddr += TX9_FIFO_HS_SIZE;
+ WRITE_REG32(USBx->GREGS->DIEPTXF[9],
+ (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX10_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS));
+ /* set txFIFO size of EP11 */
+ u32StardAddr += TX10_FIFO_HS_SIZE;
+ WRITE_REG32(USBx->GREGS->DIEPTXF[10],
+ (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX11_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS));
+ /* set txFIFO size of EP12 */
+ u32StardAddr += TX11_FIFO_HS_SIZE;
+ WRITE_REG32(USBx->GREGS->DIEPTXF[11],
+ (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX12_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS));
+ /* set txFIFO size of EP13 */
+ u32StardAddr += TX12_FIFO_HS_SIZE;
+ WRITE_REG32(USBx->GREGS->DIEPTXF[12],
+ (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX13_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS));
+ /* set txFIFO size of EP14 */
+ u32StardAddr += TX13_FIFO_HS_SIZE;
+ WRITE_REG32(USBx->GREGS->DIEPTXF[13],
+ (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX14_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS));
+ /* set txFIFO size of EP15 */
+ u32StardAddr += TX14_FIFO_HS_SIZE;
+ WRITE_REG32(USBx->GREGS->DIEPTXF[14],
+ (u32StardAddr << USBFS_DIEPTXF_INEPTXSA_POS) | (TX15_FIFO_HS_SIZE << USBFS_DIEPTXF_INEPTXFD_POS));
+}
+#endif
+
+/**
+ * @brief initializes the USB controller, include the size of txFIFO, rxFIFO
+ * status of endpoints, interrupt register etc. Details are shown as
+ * follows.
+ * @param [in] USBx usb instance
+ * @param [in] basic_cfgs usb core basic cfgs
+ * @retval None
+ */
+void usb_devmodeinit(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs)
+{
+ usb_FrameIntervalConfig(USBx, USB_FRAME_INTERVAL_80);
+ usb_DevPhySelect(USBx, basic_cfgs->phy_type);
+
+ if (basic_cfgs->core_type == 0U) {
+#ifdef USB_FS_MODE
+ usb_DevFSFifoConfig(USBx);
+#endif
+ } else {
+#ifdef USB_HS_MODE
+ usb_DevHSFifoConfig(USBx);
+#endif
+ }
+
+ usb_clrandmskepint(USBx);
+ usb_devepdis(USBx, basic_cfgs->dev_epnum);
+#ifndef VBUS_SENSING_ENABLED
+ usb_coreconn(USBx);
+#endif
+ usb_devinten(USBx, basic_cfgs->dmaen);
+}
+
+/**
+ * @brief Enable the interrupt setting when in device mode.
+ * @param [in] USBx usb instance
+ * @param [in] u8DmaEn USB DMA status
+ * @retval None
+ */
+void usb_devinten(LL_USB_TypeDef *USBx, uint8_t u8DmaEn)
+{
+ uint32_t u32gintmskTmp = 0UL;
+
+ WRITE_REG32(USBx->GREGS->GINTMSK, 0UL);
+ WRITE_REG32(USBx->GREGS->GINTSTS, 0xBFFFFFFFUL);
+ /* Enable the normal interrupt setting */
+ usb_normalinten(USBx);
+ if (u8DmaEn == 0U) {
+ u32gintmskTmp |= USBFS_GINTMSK_RXFNEM;
+ }
+ /* Enable interrupts bits corresponding to the Device mode */
+ u32gintmskTmp |= (USBFS_GINTMSK_USBSUSPM | USBFS_GINTMSK_USBRSTM | USBFS_GINTMSK_ENUMDNEM
+ | USBFS_GINTMSK_IEPIM | USBFS_GINTMSK_OEPIM | USBFS_GINTMSK_SOFM
+ | USBFS_GINTMSK_IISOIXFRM | USBFS_GINTMSK_IPXFRM_INCOMPISOOUTM);
+ SET_REG32_BIT(USBx->GREGS->GINTMSK, u32gintmskTmp);
+}
+
+/**
+ * @brief get the working status of endpoint.
+ * @param [in] USBx usb instance
+ * @param [in] ep endpoint instance
+ * @retval current status of the endpoint
+ */
+uint32_t usb_epstatusget(LL_USB_TypeDef *USBx, USB_DEV_EP *ep)
+{
+ __IO uint32_t u32Status = 0UL;
+ uint32_t u32dxepctl;
+
+ if (ep->ep_dir == 1U) {
+ u32dxepctl = READ_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL);
+
+ if (0UL != (u32dxepctl & USBFS_DIEPCTL_STALL)) {
+ u32Status = USB_EP_TX_STALL;
+ } else if (0UL != (u32dxepctl & USBFS_DIEPCTL_NAKSTS)) {
+ u32Status = USB_EP_TX_NAK;
+ } else {
+ u32Status = USB_EP_TX_VALID;
+ }
+ } else {
+ u32dxepctl = READ_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL);
+ if (0UL != (u32dxepctl & USBFS_DOEPCTL_STALL)) {
+ u32Status = USB_EP_RX_STALL;
+ } else if (0UL != (u32dxepctl & USBFS_DOEPCTL_NAKSTS)) {
+ u32Status = USB_EP_RX_NAK;
+ } else {
+ u32Status = USB_EP_RX_VALID;
+ }
+ }
+
+ return u32Status;
+}
+
+/**
+ * @brief set the working status of endpoint.
+ * @param [in] USBx usb instance
+ * @param [in] ep endpoint instance
+ * @param [in] Status new Status that the endpoint would be
+ * @retval None
+ */
+void usb_epstatusset(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint32_t Status)
+{
+ uint32_t u32dxepctl;
+ uint8_t u8RetFlag = 0U;
+
+ if (ep->ep_dir == 1U) {
+ u32dxepctl = READ_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL);
+
+ switch (Status) {
+ case USB_EP_TX_STALL:
+ usb_setepstall(USBx, ep);
+ u8RetFlag = 1U;
+ break;
+ case USB_EP_TX_NAK:
+ u32dxepctl |= USBFS_DIEPCTL_SNAK;
+ break;
+ case USB_EP_TX_VALID:
+ if (0UL != (u32dxepctl & USBFS_DIEPCTL_STALL)) {
+ ep->datax_pid = 0U;
+ usb_clearepstall(USBx, ep);
+ u8RetFlag = 1U;
+ }
+ u32dxepctl |= (USBFS_DIEPCTL_CNAK | USBFS_DIEPCTL_USBAEP | USBFS_DIEPCTL_EPENA);
+ break;
+ case USB_EP_TX_DIS:
+ u32dxepctl &= (~USBFS_DIEPCTL_USBAEP);
+ break;
+ default:
+ break;
+ }
+ /* Write register */
+ if (1U != u8RetFlag) {
+ WRITE_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL, u32dxepctl);
+ }
+ } else {
+ u32dxepctl = READ_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL);
+
+ switch (Status) {
+ case USB_EP_RX_STALL:
+ u32dxepctl |= USBFS_DOEPCTL_STALL;
+ break;
+ case USB_EP_RX_NAK:
+ u32dxepctl |= USBFS_DOEPCTL_SNAK;
+ break;
+ case USB_EP_RX_VALID:
+ if (0UL != (u32dxepctl & USBFS_DOEPCTL_STALL)) {
+ ep->datax_pid = 0U;
+ usb_clearepstall(USBx, ep);
+ u8RetFlag = 1U;
+ }
+ u32dxepctl |= (USBFS_DOEPCTL_CNAK | USBFS_DOEPCTL_USBAEP | USBFS_DOEPCTL_EPENA);
+ break;
+ case USB_EP_RX_DIS:
+ u32dxepctl &= (~USBFS_DOEPCTL_USBAEP);
+ break;
+ default:
+ break;
+ }
+ /* Write register */
+ if (1U != u8RetFlag) {
+ WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL, u32dxepctl);
+ }
+ }
+}
+
+/**
+ * @brief enable the EP0 to be actiove
+ * @param [in] USBx usb instance
+ * @retval None
+ */
+void usb_ep0activate(LL_USB_TypeDef *USBx)
+{
+ uint32_t u32EnumSpeed;
+ uint32_t u32DiepctlTmp;
+
+ u32EnumSpeed = READ_REG32(USBx->DREGS->DSTS) & USBFS_DSTS_ENUMSPD;
+ u32DiepctlTmp = READ_REG32(USBx->INEP_REGS[0]->DIEPCTL);
+ /* Set the MPS of the DIEPCTL0 based on the enumeration speed */
+ if ((DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ == u32EnumSpeed)
+ || (DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ == u32EnumSpeed)
+ || (DSTS_ENUMSPD_FS_PHY_48MHZ == u32EnumSpeed)) {
+ u32DiepctlTmp &= (~USBFS_DIEPCTL_MPSIZ);
+ } else if (DSTS_ENUMSPD_LS_PHY_6MHZ == u32EnumSpeed) {
+ u32DiepctlTmp &= (~USBFS_DIEPCTL_MPSIZ);
+ u32DiepctlTmp |= (3UL << USBFS_DIEPCTL_MPSIZ_POS);
+ } else {
+ ;
+ }
+ WRITE_REG32(USBx->INEP_REGS[0]->DIEPCTL, u32DiepctlTmp);
+ SET_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_CGINAK);
+}
+
+/**
+ * @brief enable an EP to be active
+ * @param [in] USBx usb instance
+ * @param [in] ep endpoint instance
+ * @retval None
+ */
+void usb_epactive(LL_USB_TypeDef *USBx, USB_DEV_EP *ep)
+{
+ uint32_t u32Addr;
+ uint32_t u32dxepctl;
+ uint32_t u32Daintmsk;
+
+ if (ep->ep_dir == 1U) {
+ u32Addr = (uint32_t)(&(USBx->INEP_REGS[ep->epidx]->DIEPCTL));
+ u32Daintmsk = 1UL << ep->epidx;
+ } else {
+ u32Addr = (uint32_t)(&(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL));
+ u32Daintmsk = 1UL << (USBFS_DAINTMSK_OEPINTM_POS + ep->epidx);
+ }
+ u32dxepctl = READ_REG32(*(__IO uint32_t *)u32Addr);
+ if (0UL == (u32dxepctl & USBFS_DIEPCTL_USBAEP)) {
+ u32dxepctl = ((ep->maxpacket << USBFS_DIEPCTL_MPSIZ_POS)
+ | (((uint32_t)ep->trans_type) << USBFS_DIEPCTL_EPTYP_POS)
+ | (((uint32_t)ep->tx_fifo_num) << USBFS_DIEPCTL_TXFNUM_POS)
+ | USBFS_DIEPCTL_SD0PID_SEVNFRM
+ | USBFS_DIEPCTL_USBAEP);
+
+ WRITE_REG32(*(__IO uint32_t *)u32Addr, u32dxepctl);
+ }
+ SET_REG32_BIT(USBx->DREGS->DAINTMSK, u32Daintmsk);
+}
+
+/**
+ * @brief enable an EP to be deactive state if it is active
+ * @param [in] USBx usb instance
+ * @param [in] ep endpoint instance
+ * @retval None
+ */
+void usb_epdeactive(LL_USB_TypeDef *USBx, USB_DEV_EP *ep)
+{
+ uint32_t u32Daintmsk;
+
+ if (ep->ep_dir == 1U) {
+ CLR_REG32_BIT(USBx->INEP_REGS[ep->epidx]->DIEPCTL, USBFS_DIEPCTL_USBAEP);
+ u32Daintmsk = 1UL << ep->epidx;
+ } else {
+ CLR_REG32_BIT(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL, USBFS_DOEPCTL_USBAEP);
+ u32Daintmsk = 1UL << (USBFS_DAINTMSK_OEPINTM_POS + ep->epidx);
+ }
+ CLR_REG32_BIT(USBx->DREGS->DAINTMSK, u32Daintmsk);
+}
+
+/**
+ * @brief Setup the data into the EP and begin to transmit data.
+ * @param [in] USBx usb instance
+ * @param [in] ep endpoint instance
+ * @param [in] u8DmaEn USB DMA status
+ * @retval None
+ */
+void usb_epntransbegin(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint8_t u8DmaEn)
+{
+ uint32_t u32depctl;
+ uint32_t u32DeptsizTmp;
+ uint32_t u32Pktcnt;
+ uint32_t u32Xfersize;
+
+ if (ep->ep_dir == 1U) {
+ u32depctl = READ_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL);
+ /* Zero Length Packet? */
+ if (ep->xfer_len == 0UL) {
+ u32Xfersize = 0UL;
+ u32Pktcnt = 1UL;
+ u32DeptsizTmp = (u32Xfersize << USBFS_DIEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DIEPTSIZ_PKTCNT_POS);
+ } else {
+ /* Program the transfer size and packet count
+ * as follows: xfersize = N * maxpacket +
+ * short_packet pktcnt = N + (short_packet
+ * exist ? 1 : 0)
+ */
+ u32Xfersize = ep->xfer_len;
+ u32Pktcnt = (ep->xfer_len - 1U + ep->maxpacket) / ep->maxpacket;
+ u32DeptsizTmp = (u32Xfersize << USBFS_DIEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DIEPTSIZ_PKTCNT_POS);
+ }
+ MODIFY_REG32(USBx->INEP_REGS[ep->epidx]->DIEPTSIZ, USBFS_DIEPTSIZ_XFRSIZ | USBFS_DIEPTSIZ_PKTCNT, u32DeptsizTmp);
+
+ if (u8DmaEn == 1U) {
+ WRITE_REG32(USBx->INEP_REGS[ep->epidx]->DIEPDMA, ep->dma_addr);
+ } else {
+ if (ep->trans_type != EP_TYPE_ISOC) {
+ /* Enable the Tx FIFO Empty Interrupt for this EP */
+ if (ep->xfer_len > 0U) {
+ SET_REG32_BIT(USBx->DREGS->DIEPEMPMSK, 1UL << ep->epidx);
+ }
+ }
+ }
+
+ if (ep->trans_type == EP_TYPE_ISOC) {
+ if (((READ_REG32(USBx->DREGS->DSTS) >> USBFS_DSTS_FNSOF_POS) & 0x1U) == 0U) {
+ u32depctl |= USBFS_DIEPCTL_SODDFRM;
+ } else {
+ u32depctl |= USBFS_DIEPCTL_SD0PID_SEVNFRM;
+ }
+ }
+
+ u32depctl |= (USBFS_DIEPCTL_CNAK | USBFS_DIEPCTL_EPENA);
+ WRITE_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL, u32depctl);
+
+ if (ep->trans_type == EP_TYPE_ISOC) {
+ usb_wrpkt(USBx, ep->xfer_buff, ep->epidx, (uint16_t)ep->xfer_len, u8DmaEn);
+ }
+ } else {
+ u32depctl = READ_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL);
+ /* Program the transfer size and packet count as follows:
+ * pktcnt = N
+ * xfersize = N * maxpacket
+ */
+ if (ep->xfer_len == 0U) {
+ u32Xfersize = ep->maxpacket;
+ u32Pktcnt = 1UL;
+ u32DeptsizTmp = (u32Xfersize << USBFS_DOEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DOEPTSIZ_PKTCNT_POS);
+ } else {
+ u32Pktcnt = (ep->xfer_len + (ep->maxpacket - 1U)) / ep->maxpacket;
+ u32Xfersize = u32Pktcnt * ep->maxpacket;
+ u32DeptsizTmp = (u32Xfersize << USBFS_DOEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DOEPTSIZ_PKTCNT_POS);
+ ep->xfer_len = u32Xfersize;
+ }
+ MODIFY_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPTSIZ, USBFS_DOEPTSIZ_XFRSIZ | USBFS_DOEPTSIZ_PKTCNT, u32DeptsizTmp);
+
+ if (u8DmaEn == 1U) {
+ WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPDMA, ep->dma_addr);
+ }
+
+ if (ep->trans_type == EP_TYPE_ISOC) {
+ if (0U != ep->datax_pid) {
+ u32depctl |= USBFS_DOEPCTL_SD1PID;
+ } else {
+ u32depctl |= USBFS_DOEPCTL_SD0PID;
+ }
+ }
+ u32depctl |= (USBFS_DOEPCTL_CNAK | USBFS_DOEPCTL_EPENA);
+ WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL, u32depctl);
+ }
+}
+
+/**
+ * @brief Setup the data into the EP0 and begin to transmit data.
+ * @param [in] USBx usb instance
+ * @param [in] ep endpoint instance
+ * @param [in] u8DmaEn USB DMA status
+ * @retval None
+ */
+void usb_ep0transbegin(LL_USB_TypeDef *USBx, USB_DEV_EP *ep, uint8_t u8DmaEn)
+{
+ uint32_t u32depctl;
+ uint32_t u32DeptsizTmp;
+ uint32_t u32Pktcnt;
+ uint32_t u32Xfersize;
+
+ if (ep->ep_dir == 1U) {
+ u32depctl = READ_REG32(USBx->INEP_REGS[0]->DIEPCTL);
+ /* Zero Length Packet? */
+ if (ep->xfer_len == 0U) {
+ u32Xfersize = 0UL;
+ u32Pktcnt = 1UL;
+ u32DeptsizTmp = (u32Xfersize << USBFS_DIEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DIEPTSIZ_PKTCNT_POS);
+ } else {
+ if (ep->xfer_len > ep->maxpacket) {
+ ep->xfer_len = ep->maxpacket;
+ u32Xfersize = ep->maxpacket;
+ } else {
+ u32Xfersize = ep->xfer_len;
+ }
+ u32Pktcnt = 1UL;
+ u32DeptsizTmp = (u32Xfersize << USBFS_DIEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DIEPTSIZ_PKTCNT_POS);
+ }
+ MODIFY_REG32(USBx->INEP_REGS[0]->DIEPTSIZ, USBFS_DIEPTSIZ_XFRSIZ | USBFS_DIEPTSIZ_PKTCNT, u32DeptsizTmp);
+
+ if (u8DmaEn == 1U) {
+ WRITE_REG32(USBx->INEP_REGS[ep->epidx]->DIEPDMA, ep->dma_addr);
+ }
+
+ u32depctl |= (USBFS_DIEPCTL_CNAK | USBFS_DIEPCTL_EPENA);
+ WRITE_REG32(USBx->INEP_REGS[0]->DIEPCTL, u32depctl);
+
+ if (u8DmaEn == 0U) {
+ /* Enable the Tx FIFO Empty Interrupt for this EP */
+ if (ep->xfer_len > 0U) {
+ SET_REG32_BIT(USBx->DREGS->DIEPEMPMSK, 1UL << ep->epidx);
+ }
+ }
+ } else {
+ u32depctl = READ_REG32(USBx->OUTEP_REGS[0]->DOEPCTL);
+ /* Program the transfer size and packet count as follows:
+ * xfersize = N * (maxpacket + 4 - (maxpacket % 4))
+ * pktcnt = N */
+ if (ep->xfer_len == 0U) {
+ u32Xfersize = 0UL;
+ u32Pktcnt = 1UL;
+ } else {
+ ep->xfer_len = LL_MIN(ep->rem_data_len, ep->maxpacket);
+ u32Xfersize = ep->xfer_len;
+ u32Pktcnt = 1UL;
+ }
+ u32DeptsizTmp = (u32Xfersize << USBFS_DOEPTSIZ_XFRSIZ_POS) | (u32Pktcnt << USBFS_DOEPTSIZ_PKTCNT_POS);
+ MODIFY_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPTSIZ, USBFS_DOEPTSIZ_XFRSIZ | USBFS_DOEPTSIZ_PKTCNT, u32DeptsizTmp);
+
+ if (u8DmaEn == 1U) {
+ WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPDMA, ep->dma_addr);
+ }
+ u32depctl |= (USBFS_DOEPCTL_CNAK | USBFS_DOEPCTL_EPENA);
+ WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL, u32depctl);
+ }
+}
+
+/**
+ * @brief Set the EP to be stall status
+ * @param [in] USBx usb instance
+ * @param [in] ep endpoint instance
+ * @retval None
+ */
+void usb_setepstall(LL_USB_TypeDef *USBx, USB_DEV_EP *ep)
+{
+ uint32_t u32depctl;
+
+ if (ep->ep_dir == 1U) {
+ u32depctl = READ_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL);
+ if (0UL != (u32depctl & USBFS_DIEPCTL_EPENA)) {
+ u32depctl |= USBFS_DIEPCTL_EPDIS;
+ }
+ u32depctl |= USBFS_DIEPCTL_STALL;
+ WRITE_REG32(USBx->INEP_REGS[ep->epidx]->DIEPCTL, u32depctl);
+ } else {
+ u32depctl = READ_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL);
+ u32depctl |= USBFS_DOEPCTL_STALL;
+ WRITE_REG32(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL, u32depctl);
+ }
+}
+
+/**
+ * @brief clear the stall status of a EP
+ * @param [in] USBx usb instance
+ * @param [in] ep endpoint instance
+ * @retval None
+ */
+void usb_clearepstall(LL_USB_TypeDef *USBx, USB_DEV_EP *ep)
+{
+ uint32_t tmp_depctl_addr;
+ uint32_t u32depctl;
+ if (ep->ep_dir == 1U) {
+ tmp_depctl_addr = (uint32_t)(&(USBx->INEP_REGS[ep->epidx]->DIEPCTL));
+ } else {
+ tmp_depctl_addr = (uint32_t)(&(USBx->OUTEP_REGS[ep->epidx]->DOEPCTL));
+ }
+ u32depctl = READ_REG32(*(__IO uint32_t *)tmp_depctl_addr);
+
+ u32depctl &= (~USBFS_DIEPCTL_STALL);
+ if ((ep->trans_type == EP_TYPE_INTR) || (ep->trans_type == EP_TYPE_BULK)) {
+ u32depctl |= USBFS_DIEPCTL_SD0PID_SEVNFRM;
+ }
+
+ WRITE_REG32(*(__IO uint32_t *)tmp_depctl_addr, u32depctl);
+}
+
+/**
+ * @brief configure the EPO to receive data packets
+ * @param [in] USBx usb instance
+ * @param [in] u8DmaEn USB DMA status
+ * @retval None
+ */
+void usb_ep0revcfg(LL_USB_TypeDef *USBx, uint8_t u8DmaEn, uint8_t *u8RevBuf)
+{
+ uint32_t u32deptsize;
+ uint32_t u32doepctl;
+
+ u32deptsize = (3UL << USBFS_DOEPTSIZ0_STUPCNT_POS)
+ | (1UL << USBFS_DOEPTSIZ0_PKTCNT_POS)
+ | (64UL << USBFS_DOEPTSIZ0_XFRSIZ_POS);
+
+ WRITE_REG32(USBx->OUTEP_REGS[0]->DOEPTSIZ, u32deptsize);
+
+ if (u8DmaEn == 1U) {
+ WRITE_REG32(USBx->OUTEP_REGS[0]->DOEPDMA, (uint32_t)&u8RevBuf[0]);
+ u32doepctl = READ_REG32(USBx->OUTEP_REGS[0]->DOEPCTL);
+ u32doepctl |= (USBFS_DOEPCTL_EPENA | USBFS_DOEPCTL_USBAEP);
+ WRITE_REG32(USBx->OUTEP_REGS[0]->DOEPCTL, u32doepctl);
+ }
+}
+
+/**
+ * @brief enable remote wakeup active
+ * @param [in] USBx usb instance
+ * @retval None
+ */
+void usb_remotewakeupen(LL_USB_TypeDef *USBx)
+{
+ uint32_t u32dsts;
+
+ u32dsts = READ_REG32(USBx->DREGS->DSTS);
+ if (0UL != (u32dsts & USBFS_DSTS_SUSPSTS)) {
+ /* un-gate USB Core clock */
+ CLR_REG32_BIT(*USBx->GCCTL, USBFS_GCCTL_GATEHCLK | USBFS_GCCTL_STPPCLK);
+ }
+
+ SET_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_RWUSIG);
+ usb_mdelay(5UL);
+ CLR_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_RWUSIG);
+}
+
+/**
+ * @brief control the device to connect or disconnect
+ * @param [in] USBx usb instance
+ * @param [in] link 0(conn) or 1(disconn)
+ * @retval None
+ */
+void usb_ctrldevconnect(LL_USB_TypeDef *USBx, uint8_t link)
+{
+ if (0U == link) {
+ CLR_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_SDIS);
+ } else {
+ SET_REG32_BIT(USBx->DREGS->DCTL, USBFS_DCTL_SDIS);
+ }
+ usb_mdelay(3UL);
+}
+#endif
+
+#ifdef USE_HOST_MODE
+/**
+ * @brief Initializes the USB controller when it is host mode
+ * @param [in] USBx usb instance
+ * @param [in] basic_cfgs usb core basic cfgs
+ * @retval None
+ */
+void usb_hostmodeinit(LL_USB_TypeDef *USBx, USB_CORE_BASIC_CFGS *basic_cfgs)
+{
+ __IO uint8_t u8Tmp = 0U;
+ WRITE_REG32(*USBx->GCCTL, 0UL); /* reset the register-GCCTL */
+ if (USBHS_PHY_EMBED == basic_cfgs->phy_type) {
+ usb_fslspclkselset(USBx, HCFG_6_MHZ); /* PHY clock is running at 6MHz */
+ } else {
+ usb_fslspclkselset(USBx, HCFG_30_60_MHZ); /* PHY clock is running at 6MHz */
+ }
+ usb_hprtrst(USBx); /* reset the port */
+ usb_enumspeed(USBx); /* FS or LS bases on the maximum speed supported by the connected device */
+ usb_sethostfifo(USBx, basic_cfgs->core_type);
+ /* Flush all the txFIFO and the whole rxFIFO */
+ usb_txfifoflush(USBx, 0x10UL);
+ usb_rxfifoflush(USBx);
+ /* Clear all HC Interrupt bits that are pending */
+ while (u8Tmp < basic_cfgs->host_chnum) {
+ WRITE_REG32(USBx->HC_REGS[u8Tmp]->HCINT, 0xFFFFFFFFUL);
+ WRITE_REG32(USBx->HC_REGS[u8Tmp]->HCINTMSK, 0UL);
+ u8Tmp++;
+ }
+ usb_hostinten(USBx, basic_cfgs->dmaen);
+}
+
+/**
+ * @brief set the vbus if state is 1 or reset the vbus if state is 0.
+ * @param [in] USBx usb instance
+ * @param [in] u8State the vbus state it would be.
+ * @retval None
+ */
+void usb_vbusctrl(LL_USB_TypeDef *USBx, uint8_t u8State)
+{
+ uint32_t u32hprt;
+
+ u32hprt = usb_rdhprt(USBx);
+ if ((0UL == (u32hprt & USBFS_HPRT_PWPR)) && (1U == u8State)) {
+ u32hprt |= USBFS_HPRT_PWPR;
+ WRITE_REG32(*USBx->HPRT, u32hprt);
+ }
+ if ((0UL != (u32hprt & USBFS_HPRT_PWPR)) && (0U == u8State)) {
+ u32hprt &= (~USBFS_HPRT_PWPR);
+ WRITE_REG32(*USBx->HPRT, u32hprt);
+ }
+}
+
+/**
+ * @brief Enables the related interrupts when the core is host mode
+ * @param [in] USBx usb instance
+ * @param [in] u8DmaEn USB DMA status
+ * @retval None
+ */
+void usb_hostinten(LL_USB_TypeDef *USBx, uint8_t u8DmaEn)
+{
+ uint32_t u32gIntmsk = 0UL;
+ WRITE_REG32(USBx->GREGS->GINTMSK, 0UL);
+ /* Clear the pending interrupt bits */
+ WRITE_REG32(USBx->GREGS->GINTSTS, 0xFFFFFFFFUL);
+
+ /* Enable the normal interrupt bits */
+ usb_normalinten(USBx);
+
+ if (u8DmaEn == 0U) {
+ u32gIntmsk |= USBFS_GINTMSK_RXFNEM;
+ }
+ u32gIntmsk |= (USBFS_GINTMSK_HPRTIM
+ | USBFS_GINTMSK_HCIM
+ | USBFS_GINTMSK_DISCIM
+ | USBFS_GINTMSK_SOFM
+ | USBFS_GINTMSK_IPXFRM_INCOMPISOOUTM);
+ SET_REG32_BIT(USBx->GREGS->GINTMSK, u32gIntmsk);
+}
+
+/**
+ * @brief Reset the port, the 1'b0 state must last at lease 10ms.
+ * @param [in] USBx usb instance
+ * @retval None
+ */
+void usb_hprtrst(LL_USB_TypeDef *USBx)
+{
+ uint32_t u32hprt;
+ u32hprt = usb_rdhprt(USBx);
+ u32hprt |= USBFS_HPRT_PRST;
+ WRITE_REG32(*USBx->HPRT, u32hprt);
+ usb_mdelay(10UL);
+ u32hprt &= ~USBFS_HPRT_PRST;
+ WRITE_REG32(*USBx->HPRT, u32hprt);
+ usb_mdelay(20UL);
+}
+
+/**
+ * @brief Prepares transferring packets on a host channel
+ * @param [in] USBx usb instance
+ * @param [in] hc_num channel index
+ * @param [in] pCh channel structure
+ * @param [in] u8DmaEn USB DMA status
+ * @retval status in byte
+ */
+uint8_t usb_inithch(LL_USB_TypeDef *USBx, uint8_t hc_num, USB_HOST_CH *pCh, uint8_t u8DmaEn)
+{
+ uint32_t u32hcintmsk = 0UL;
+ uint32_t u32hcchar = 0UL;
+
+ WRITE_REG32(USBx->HC_REGS[hc_num]->HCINT, 0xFFFFFFFFUL);
+ switch (pCh->ep_type) {
+ case EP_TYPE_CTRL:
+ case EP_TYPE_BULK:
+ u32hcintmsk |= (USBFS_HCINTMSK_XFRCM
+ | USBFS_HCINTMSK_STALLM
+ | USBFS_HCINTMSK_TXERRM
+ | USBFS_HCINTMSK_DTERRM
+ | USBFS_HCINTMSK_NAKM);
+ if (0U != pCh->is_epin) {
+ u32hcintmsk |= USBFS_HCINTMSK_BBERRM;
+ } else {
+ if (0U != pCh->do_ping) {
+ u32hcintmsk |= USBFS_HCINTMSK_ACKM;
+ }
+ }
+ break;
+ case EP_TYPE_INTR:
+ u32hcintmsk |= (USBFS_HCINTMSK_XFRCM
+ | USBFS_HCINTMSK_NAKM
+ | USBFS_HCINTMSK_STALLM
+ | USBFS_HCINTMSK_TXERRM
+ | USBFS_HCINTMSK_DTERRM
+ | USBFS_HCINTMSK_FRMORM);
+ if (0U != pCh->is_epin) {
+ u32hcintmsk |= USBFS_HCINTMSK_BBERRM;
+ }
+ break;
+ case EP_TYPE_ISOC:
+ u32hcintmsk |= (USBFS_HCINTMSK_XFRCM
+ | USBFS_HCINTMSK_FRMORM
+ | USBFS_HCINTMSK_ACKM);
+
+ if (0U != pCh->is_epin) {
+ u32hcintmsk |= (USBFS_HCINTMSK_TXERRM | USBFS_HCINTMSK_BBERRM);
+ }
+ break;
+ default:
+ break;
+ }
+
+ WRITE_REG32(USBx->HC_REGS[hc_num]->HCINTMSK, u32hcintmsk);
+ SET_REG32_BIT(USBx->HREGS->HAINTMSK, 1UL << hc_num);
+
+ /* enable the host channel interrupts */
+ SET_REG32_BIT(USBx->GREGS->GINTMSK, USBFS_GINTMSK_HCIM);
+
+ /* modify HCCHAR */
+ u32hcchar |= (((uint32_t)pCh->dev_addr) << USBFS_HCCHAR_DAD_POS);
+ u32hcchar |= (((uint32_t)pCh->ep_idx) << USBFS_HCCHAR_EPNUM_POS);
+ u32hcchar |= (((uint32_t)pCh->is_epin) << USBFS_HCCHAR_EPDIR_POS);
+ u32hcchar |= (((uint32_t)pCh->ep_type) << USBFS_HCCHAR_EPTYP_POS);
+ u32hcchar |= (((uint32_t)pCh->max_packet) << USBFS_HCCHAR_MPSIZ_POS);
+ if (PRTSPD_LOW_SPEED == pCh->ch_speed) {
+ u32hcchar |= USBFS_HCCHAR_LSDEV;
+ } else {
+ u32hcchar &= ~USBFS_HCCHAR_LSDEV;
+ }
+
+ if (pCh->ep_type == EP_TYPE_INTR) {
+ u32hcchar |= USBFS_HCCHAR_ODDFRM;
+ }
+ WRITE_REG32(USBx->HC_REGS[hc_num]->HCCHAR, u32hcchar);
+ return USB_OK;
+}
+
+/**
+ * @brief Start transfer on the channel whose index is hc_num.
+ * @param [in] USBx usb instance
+ * @param [in] hc_num channel index
+ * @param [in] pCh channel structure
+ * @param [in] u8DmaEn USB DMA status
+ * @retval status in 8 bits
+ */
+uint8_t usb_hchtransbegin(LL_USB_TypeDef *USBx, uint8_t hc_num, USB_HOST_CH *pCh, uint8_t u8DmaEn)
+{
+ uint32_t u32hcchar;
+ uint32_t u32hctsiz = 0UL;
+ uint32_t u32hnptxsts;
+ uint32_t u32hptxsts;
+ uint16_t u16LenWords;
+ uint16_t u16NumPacket;
+ uint16_t u16MaxHcPktCount = 256U;
+
+ /* Compute the expected number of packets associated to the transfer */
+ if (pCh->xfer_len > 0U) {
+ u16NumPacket = (uint16_t)((pCh->xfer_len +
+ (uint32_t)pCh->max_packet - 1UL) / (uint32_t)pCh->max_packet);
+
+ if (u16NumPacket > u16MaxHcPktCount) {
+ u16NumPacket = u16MaxHcPktCount;
+ pCh->xfer_len = (uint32_t)u16NumPacket * (uint32_t)pCh->max_packet;
+ }
+ } else {
+ u16NumPacket = 1U;
+ }
+ if (0U != pCh->is_epin) {
+ pCh->xfer_len = (uint32_t)u16NumPacket * (uint32_t)pCh->max_packet;
+ }
+
+ u32hctsiz |= (((uint32_t)pCh->xfer_len) << USBFS_HCTSIZ_XFRSIZ_POS);
+ u32hctsiz |= (((uint32_t)u16NumPacket) << USBFS_HCTSIZ_PKTCNT_POS);
+ u32hctsiz |= (((uint32_t)pCh->pid_type) << USBFS_HCTSIZ_DPID_POS);
+ WRITE_REG32(USBx->HC_REGS[hc_num]->HCTSIZ, u32hctsiz);
+
+ if (u8DmaEn == 1U) {
+ WRITE_REG32(USBx->HC_REGS[hc_num]->HCDMA, pCh->xfer_buff);
+ }
+
+ u32hcchar = READ_REG32(USBx->HC_REGS[hc_num]->HCCHAR);
+ u32hcchar &= ~USBFS_HCCHAR_ODDFRM;
+ u32hcchar |= (usb_ifevenframe(USBx) << USBFS_HCCHAR_ODDFRM_POS);
+
+ /* enable this host channel whose number is hc_num */
+ u32hcchar |= USBFS_HCCHAR_CHENA;
+ u32hcchar &= ~USBFS_HCCHAR_CHDIS;
+ WRITE_REG32(USBx->HC_REGS[hc_num]->HCCHAR, u32hcchar);
+
+ if (u8DmaEn == 0U) {
+ if ((pCh->is_epin == 0U) && (pCh->xfer_len > 0U)) {
+ switch (pCh->ep_type) {
+ /* Non-periodic transmit */
+ case EP_TYPE_CTRL:
+ case EP_TYPE_BULK:
+ u32hnptxsts = READ_REG32(USBx->GREGS->HNPTXSTS);
+ u16LenWords = (uint16_t)((pCh->xfer_len + 3UL) / 4UL);
+ /* check if the amount of free space available in the non-periodic txFIFO is enough */
+ if (u16LenWords > ((u32hnptxsts & USBFS_HNPTXSTS_NPTXFSAV) >> USBFS_HNPTXSTS_NPTXFSAV_POS)) {
+ /* enable interrrupt of nptxfempty of GINTMSK*/
+ SET_REG32_BIT(USBx->GREGS->GINTMSK, USBFS_GINTMSK_NPTXFEM);
+ }
+ break;
+ /* Periodic trnsmit */
+ case EP_TYPE_INTR:
+ case EP_TYPE_ISOC:
+ u32hptxsts = READ_REG32(USBx->HREGS->HPTXSTS);
+ u16LenWords = (uint16_t)((pCh->xfer_len + 3UL) / 4UL);
+ /* check if the space of periodic TxFIFO is enough */
+ if (u16LenWords > ((u32hptxsts & USBFS_HPTXSTS_PTXFSAVL) >> USBFS_HPTXSTS_PTXFSAVL_POS)) {
+ /* enable interrrupt of ptxfempty of GINTMSK */
+ SET_REG32_BIT(USBx->GREGS->GINTMSK, USBFS_GINTMSK_PTXFEM);
+ }
+ break;
+ default:
+ break;
+ }
+
+ usb_wrpkt(USBx, pCh->xfer_buff, hc_num, (uint16_t)pCh->xfer_len, u8DmaEn);
+ }
+ }
+ return USB_OK;
+}
+
+/**
+ * @brief Stop the host and flush all the txFIFOs and the whole rxFIFO.
+ * @param [in] USBx usb instance
+ * @param [in] u8ChNum Host channel number
+ * @retval None
+ */
+void usb_hoststop(LL_USB_TypeDef *USBx, uint8_t u8ChNum)
+{
+ __IO uint32_t u32Tmp = 0UL;
+
+ WRITE_REG32(USBx->HREGS->HAINTMSK, 0UL);
+ WRITE_REG32(USBx->HREGS->HAINT, 0xFFFFFFFFUL);
+
+ do {
+ usb_chrst(USBx, (uint8_t)u32Tmp);
+ u32Tmp++;
+ } while (u32Tmp < u8ChNum);
+ /* flush all the txFIFOs and the whole rxFIFO */
+ usb_rxfifoflush(USBx);
+ usb_txfifoflush(USBx, 0x10UL);
+}
+
+/**
+ * @brief make the channel to halt
+ * @param [in] USBx usb instance
+ * @param [in] hc_num channel index
+ * @retval None
+ */
+void usb_hchstop(LL_USB_TypeDef *USBx, uint8_t hc_num)
+{
+ uint32_t u32hcchar;
+
+ u32hcchar = READ_REG32(USBx->HC_REGS[hc_num]->HCCHAR);
+ u32hcchar |= USBFS_HCCHAR_CHDIS;
+ /* Check for space in the request queue to issue the halt. */
+ if ((EP_TYPE_CTRL == ((u32hcchar & USBFS_HCCHAR_EPTYP) >> USBFS_HCCHAR_EPTYP_POS))
+ || (EP_TYPE_BULK == ((u32hcchar & USBFS_HCCHAR_EPTYP) >> USBFS_HCCHAR_EPTYP_POS))) {
+ if (0UL == (READ_REG32(USBx->GREGS->HNPTXSTS) & USBFS_HNPTXSTS_NPTQXSAV)) {
+ u32hcchar &= (~USBFS_HCCHAR_CHENA);
+ WRITE_REG32(USBx->HC_REGS[hc_num]->HCCHAR, u32hcchar);
+ }
+ } else {
+ if (0UL == (READ_REG32(USBx->HREGS->HPTXSTS) & USBFS_HPTXSTS_PTXQSAV)) {
+ u32hcchar &= (~USBFS_HCCHAR_CHENA);
+ WRITE_REG32(USBx->HC_REGS[hc_num]->HCCHAR, u32hcchar);
+ }
+ }
+ u32hcchar |= USBFS_HCCHAR_CHENA;
+ WRITE_REG32(USBx->HC_REGS[hc_num]->HCCHAR, u32hcchar);
+}
+
+#endif
+
+/**
+ * @brief De-initializes the USB peripheral.
+ * @param [in] USBx usb instance
+ * @retval int32_t:
+ * - LL_OK: De-Initialize success.
+ * - LL_ERR_TIMEOUT: Timeout.
+ */
+int32_t USB_DeInit(LL_USB_TypeDef *USBx)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t u32TimeOut = 0U;
+ /* Check RMU_FRST register protect */
+ DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1);
+
+ /* Reset */
+ WRITE_REG32(bCM_RMU->FRST1_b.USBFS, 0UL);
+ /* Ensure reset procedure is completed */
+ while (0UL == READ_REG32(bCM_RMU->FRST1_b.USBFS)) {
+ u32TimeOut++;
+ if (u32TimeOut > USB_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @}
+*/
+
+#endif /* LL_USB_ENABLE */
+
+/**
+ * @}
+*/
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_utility.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_utility.c
new file mode 100644
index 0000000000..868881801a
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_utility.c
@@ -0,0 +1,440 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_utility.c
+ * @brief This file provides utility functions for DDL.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2022-06-30 CDT Support re-target printf for IAR EW version 9 or later
+ 2023-06-30 CDT Modify register USART DR to USART TDR
+ Prohibit DDL_DelayMS and DDL_DelayUS functions from being optimized
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_UTILITY UTILITY
+ * @brief DDL Utility Driver
+ * @{
+ */
+
+#if (LL_UTILITY_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+/**
+ * @defgroup UTILITY_Local_Variables UTILITY Local Variables
+ * @{
+ */
+
+static uint32_t m_u32TickStep = 0UL;
+static __IO uint32_t m_u32TickCount = 0UL;
+
+#if (LL_PRINT_ENABLE == DDL_ON)
+static void *m_pvPrintDevice = NULL;
+static uint32_t m_u32PrintTimeout = 0UL;
+#endif
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+
+/**
+ * @defgroup UTILITY_Local_Functions UTILITY Local Functions
+ * @{
+ */
+#if (LL_PRINT_ENABLE == DDL_ON)
+
+/**
+ * @brief Set print device.
+ * @param [in] pvPrintDevice Pointer to print device
+ * @retval None
+ */
+__STATIC_INLINE void LL_SetPrintDevice(void *pvPrintDevice)
+{
+ m_pvPrintDevice = pvPrintDevice;
+}
+
+/**
+ * @brief Get print device.
+ * @param None
+ * @retval Pointer to print device
+ */
+__STATIC_INLINE void *LL_GetPrintDevice(void)
+{
+ return m_pvPrintDevice;
+}
+
+/**
+ * @brief Set print timeout.
+ * @param [in] u32Timeout Print timeout value
+ * @retval None
+ */
+__STATIC_INLINE void LL_SetPrintTimeout(uint32_t u32Timeout)
+{
+ m_u32PrintTimeout = u32Timeout;
+}
+
+/**
+ * @brief Get print timeout.
+ * @param None
+ * @retval Print timeout value
+ */
+__STATIC_INLINE uint32_t LL_GetPrintTimeout(void)
+{
+ return m_u32PrintTimeout;
+}
+#endif /* LL_PRINT_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup UTILITY_Global_Functions UTILITY Global Functions
+ * @{
+ */
+
+/**
+ * @brief Delay function, delay ms approximately
+ * @param [in] u32Count ms
+ * @retval None
+ */
+#if defined (__CC_ARM) /*!< ARM Compiler */
+#pragma push
+#pragma O0
+#endif
+__NO_OPTIMIZE void DDL_DelayMS(uint32_t u32Count)
+{
+ __IO uint32_t i;
+ const uint32_t u32Cyc = (HCLK_VALUE + 10000UL - 1UL) / 10000UL;
+
+ while (u32Count-- > 0UL) {
+ i = u32Cyc;
+ while (i-- > 0UL) {
+ }
+ }
+}
+
+/**
+ * @brief Delay function, delay us approximately
+ * @param [in] u32Count us
+ * @retval None
+ */
+__NO_OPTIMIZE void DDL_DelayUS(uint32_t u32Count)
+{
+ __IO uint32_t i;
+ const uint32_t u32Cyc = (HCLK_VALUE + 10000000UL - 1UL) / 10000000UL;
+
+ while (u32Count-- > 0UL) {
+ i = u32Cyc;
+ while (i-- > 0UL) {
+ }
+ }
+}
+#if defined (__CC_ARM) /*!< ARM Compiler */
+#pragma pop
+#endif
+
+/**
+ * @brief This function Initializes the interrupt frequency of the SysTick.
+ * @param [in] u32Freq SysTick interrupt frequency (1 to 1000).
+ * @retval int32_t:
+ * - LL_OK: SysTick Initializes succeed
+ * - LL_ERR: SysTick Initializes failed
+ */
+__WEAKDEF int32_t SysTick_Init(uint32_t u32Freq)
+{
+ int32_t i32Ret = LL_ERR;
+
+ if ((0UL != u32Freq) && (u32Freq <= 1000UL)) {
+ m_u32TickStep = 1000UL / u32Freq;
+ /* Configure the SysTick interrupt */
+ if (0UL == SysTick_Config(HCLK_VALUE / u32Freq)) {
+ i32Ret = LL_OK;
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief This function provides minimum delay (in milliseconds).
+ * @param [in] u32Delay Delay specifies the delay time.
+ * @retval None
+ */
+__WEAKDEF void SysTick_Delay(uint32_t u32Delay)
+{
+ const uint32_t tickStart = SysTick_GetTick();
+ uint32_t tickEnd = u32Delay;
+ uint32_t tickMax;
+
+ if (m_u32TickStep != 0UL) {
+ tickMax = 0xFFFFFFFFUL / m_u32TickStep * m_u32TickStep;
+ /* Add a freq to guarantee minimum wait */
+ if ((u32Delay >= tickMax) || ((tickMax - u32Delay) < m_u32TickStep)) {
+ tickEnd = tickMax;
+ }
+ while ((SysTick_GetTick() - tickStart) < tickEnd) {
+ }
+ }
+}
+
+/**
+ * @brief This function is called to increment a global variable "u32TickCount".
+ * @note This variable is incremented in SysTick ISR.
+ * @param None
+ * @retval None
+ */
+__WEAKDEF void SysTick_IncTick(void)
+{
+ m_u32TickCount += m_u32TickStep;
+}
+
+/**
+ * @brief Provides a tick value in millisecond.
+ * @param None
+ * @retval Tick value
+ */
+__WEAKDEF uint32_t SysTick_GetTick(void)
+{
+ return m_u32TickCount;
+}
+
+/**
+ * @brief Suspend SysTick increment.
+ * @param None
+ * @retval None
+ */
+__WEAKDEF void SysTick_Suspend(void)
+{
+ /* Disable SysTick Interrupt */
+ SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+ * @brief Resume SysTick increment.
+ * @param None
+ * @retval None
+ */
+__WEAKDEF void SysTick_Resume(void)
+{
+ /* Enable SysTick Interrupt */
+ SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+}
+
+#ifdef __DEBUG
+/**
+ * @brief DDL assert error handle function
+ * @param [in] file Point to the current assert the wrong file.
+ * @param [in] line Point line assert the wrong file in the current.
+ * @retval None
+ */
+__WEAKDEF void DDL_AssertHandler(const char *file, int line)
+{
+ /* Users can re-implement this function to print information */
+ DDL_Printf("Wrong parameters value: file %s on line %d\r\n", file, line);
+
+ for (;;) {
+ }
+}
+#endif /* __DEBUG */
+
+#if (LL_PRINT_ENABLE == DDL_ON)
+
+#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \
+ (defined (__ICCARM__) && (__VER__ < 9000000)) || (defined (__CC_ARM))
+/**
+ * @brief Re-target fputc function.
+ * @param [in] ch
+ * @param [in] f
+ * @retval int32_t
+ */
+int32_t fputc(int32_t ch, FILE *f)
+{
+ (void)f; /* Prevent unused argument compilation warning */
+
+ return (LL_OK == DDL_ConsoleOutputChar((char)ch)) ? ch : -1;
+}
+
+#elif (defined (__ICCARM__) && (__VER__ >= 9000000))
+#include
+#pragma module_name = "?__write"
+size_t __dwrite(int handle, const unsigned char *buffer, size_t size)
+{
+ size_t nChars = 0;
+ size_t i;
+
+ if (buffer == NULL) {
+ /*
+ * This means that we should flush internal buffers. Since we
+ * don't we just return. (Remember, "handle" == -1 means that all
+ * handles should be flushed.)
+ */
+ return 0;
+ }
+
+ /* This template only writes to "standard out" and "standard err",
+ * for all other file handles it returns failure. */
+ if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR) {
+ return _LLIO_ERROR;
+ }
+
+ for (i = 0; i < size; i++) {
+ if (DDL_ConsoleOutputChar((char)buffer[i]) < 0) {
+ return _LLIO_ERROR;
+ }
+
+ ++nChars;
+ }
+
+ return nChars;
+}
+
+#elif defined ( __GNUC__ ) && !defined (__CC_ARM)
+/**
+ * @brief Re-target _write function.
+ * @param [in] fd
+ * @param [in] data
+ * @param [in] size
+ * @retval int32_t
+ */
+int32_t _write(int fd, char data[], int32_t size)
+{
+ int32_t i = -1;
+
+ if (NULL != data) {
+ (void)fd; /* Prevent unused argument compilation warning */
+
+ for (i = 0; i < size; i++) {
+ if (LL_OK != DDL_ConsoleOutputChar(data[i])) {
+ break;
+ }
+ }
+ }
+
+ return i ? i : -1;
+}
+#endif
+
+/**
+ * @brief Initialize printf function
+ * @param [in] vpDevice Pointer to print device
+ * @param [in] u32Param Print device parameter
+ * @param [in] pfnPreinit The function pointer for initializing clock, port, print device etc.
+ * @retval int32_t:
+ * - LL_OK: Initialize successfully.
+ * - LL_ERR: The callback function pfnPreinit occurs error.
+ * - LL_ERR_INVD_PARAM: The pointer pfnPreinit is NULL.
+ */
+int32_t LL_PrintfInit(void *vpDevice, uint32_t u32Param, int32_t (*pfnPreinit)(void *vpDevice, uint32_t u32Param))
+{
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+
+ if (NULL != pfnPreinit) {
+ i32Ret = pfnPreinit(vpDevice, u32Param); /* The callback function initialize clock, port, print device etc */
+ if (LL_OK == i32Ret) {
+ LL_SetPrintDevice(vpDevice);
+ LL_SetPrintTimeout((u32Param == 0UL) ? 0UL : (HCLK_VALUE / u32Param));
+ } else {
+ i32Ret = LL_ERR;
+ DDL_ASSERT(i32Ret == LL_OK); /* Initialize unsuccessfully */
+ }
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief Transmit character.
+ * @param [in] cData The character for transmitting
+ * @retval int32_t:
+ * - LL_OK: Transmit successfully.
+ * - LL_ERR_TIMEOUT: Transmit timeout.
+ * - LL_ERR_INVD_PARAM: The print device is invalid.
+ */
+__WEAKDEF int32_t DDL_ConsoleOutputChar(char cData)
+{
+ uint32_t u32TxEmpty = 0UL;
+ __IO uint32_t u32TmpCount = 0UL;
+ int32_t i32Ret = LL_ERR_INVD_PARAM;
+ uint32_t u32Timeout = LL_GetPrintTimeout();
+ CM_USART_TypeDef *USARTx = (CM_USART_TypeDef *)LL_GetPrintDevice();
+
+ if (NULL != USARTx) {
+ /* Wait TX data register empty */
+ while ((u32TmpCount <= u32Timeout) && (0UL == u32TxEmpty)) {
+ u32TxEmpty = READ_REG32_BIT(USARTx->SR, USART_SR_TXE);
+ u32TmpCount++;
+ }
+
+ if (0UL != u32TxEmpty) {
+ WRITE_REG16(USARTx->TDR, (uint16_t)cData);
+ i32Ret = LL_OK;
+ } else {
+ i32Ret = LL_ERR_TIMEOUT;
+ }
+ }
+
+ return i32Ret;
+}
+
+#endif /* LL_PRINT_ENABLE */
+
+/**
+ * @}
+ */
+
+#endif /* LL_UTILITY_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_vref.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_vref.c
new file mode 100644
index 0000000000..a37014ae63
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_vref.c
@@ -0,0 +1,236 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_vref.c
+ * @brief This file provides firmware functions to manage the high precision
+ * Reference Voltage(VREF).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-06-30 CDT Modify typo
+ Add API VREF_DeInit()
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_vref.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_VREF VREF
+ * @brief VREF Driver Library
+ * @{
+ */
+
+#if (LL_VREF_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup VREF_Local_Macros VREF Local Macros
+ * @{
+ */
+
+#define VREF_RMU_TIMEOUT (100UL)
+
+/**
+ * @defgroup VREF_Check_Parameters_Validity VREF Check Parameters Validity
+ * @{
+ */
+#define IS_VREF_OPERATING_MD(x) \
+( ((x) == VREF_EXT_REF_MD) || \
+ ((x) == VREF_SHORT_MD) || \
+ ((x) == VREF_INTERN_REF_MD))
+
+#define IS_VREF_AVCC_DIV_OUTPUT(x) \
+( ((x) == VREF_AVCC_DIV_QUARTER) || \
+ ((x) == VREF_AVCC_DIV_ONE_THIRD) || \
+ ((x) == VREF_AVCC_DIV_TWO_FIFTHS) || \
+ ((x) == VREF_AVCC_DIV_HALF))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup VREF_Global_Functions VREF Global Functions
+ * @{
+ */
+
+/**
+ * @brief Enable or disable Band Gap Reference circuit.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void VREF_BandGapRefCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ WRITE_REG32(CM_VREF->BGRCR, enNewState);
+}
+
+/**
+ * @brief Enable or disable Current Source circuit.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void VREF_CurrentSrcCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ WRITE_REG32(CM_VREF->CSCR, enNewState);
+}
+
+/**
+ * @brief AVCC divider voltage command.
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void VREF_AvccDivCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ if (enNewState == ENABLE) {
+ SET_REG32_BIT(CM_VREF->CR, VREF_CR_AVCCMONEN);
+ } else {
+ CLR_REG32_BIT(CM_VREF->CR, VREF_CR_AVCCMONEN);
+ }
+}
+
+/**
+ * @brief AVCC divider configure.
+ * @param [in] u32Div AVCC voltage divider @ref VREF_Avcc_Div_Config
+ * @retval None
+ */
+void VREF_AvccDivConfig(uint32_t u32Div)
+{
+ DDL_ASSERT(IS_VREF_AVCC_DIV_OUTPUT(u32Div));
+ MODIFY_REG32(CM_VREF->CR, VREF_CR_AVCCMONS, u32Div);
+}
+
+/**
+ * @brief VREFINT voltage command
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void VREF_VrefintCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ if (enNewState == ENABLE) {
+ SET_REG32_BIT(CM_VREF->CR, VREF_CR_VREFINTEN);
+ } else {
+ CLR_REG32_BIT(CM_VREF->CR, VREF_CR_VREFINTEN);
+ }
+}
+
+/**
+ * @brief IVREF(internal reference) voltage command
+ * @param [in] enNewState An @ref en_functional_state_t enumeration value.
+ * @retval None
+ */
+void VREF_IvrefCmd(en_functional_state_t enNewState)
+{
+ DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
+ if (enNewState == ENABLE) {
+ SET_REG32_BIT(CM_VREF->CR, VREF_CR_IVREFEN);
+ } else {
+ CLR_REG32_BIT(CM_VREF->CR, VREF_CR_IVREFEN);
+ }
+}
+
+/**
+ * @brief Set the mode of IVREF voltage.
+ * @param [in] u32Mode VREF operating mode.
+ * This parameter can be a value of @ref VREF_Intern_Vref_Mode
+ * @arg VREF_EXT_REF_MD: External reference voltage mode, VREFH input as reference voltage.
+ * Internal reference voltage is OFF.
+ * @arg VREF_SHORT_MD: VREFH is short to VSS. Internal reference voltage is OFF.
+ * @arg VREF_INTERN_REF_MD: Use internal reference voltage.
+ * External VREFH is short to internal VREF circuit.
+ * @retval None
+ */
+void VREF_SetIvrefMode(uint32_t u32Mode)
+{
+ DDL_ASSERT(IS_VREF_OPERATING_MD(u32Mode));
+ MODIFY_REG32(CM_VREF->CR, VREF_CR_HIZ | VREF_CR_IVREFEN, u32Mode);
+}
+
+/**
+ * @brief De-initializes the VREF peripheral.
+ * @param None
+ * @retval int32_t:
+ * - LL_OK: De-Initialize success.
+ * - LL_ERR_TIMEOUT: Timeout.
+ */
+int32_t VREF_DeInit(void)
+{
+ int32_t i32Ret = LL_OK;
+ __IO uint32_t u32TimeOut = 0U;
+ /* Check RMU_FRST register protect */
+ DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1);
+
+ /* Reset */
+ WRITE_REG32(bCM_RMU->FRST3_b.VREF, 0UL);
+ /* Ensure reset procedure is completed */
+ while (0UL == READ_REG32(bCM_RMU->FRST3_b.VREF)) {
+ u32TimeOut++;
+ if (u32TimeOut > VREF_RMU_TIMEOUT) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ }
+ return i32Ret;
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_VREF_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_wdt.c b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_wdt.c
new file mode 100644
index 0000000000..398b5458f9
--- /dev/null
+++ b/bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_wdt.c
@@ -0,0 +1,257 @@
+/**
+ *******************************************************************************
+ * @file hc32_ll_wdt.c
+ * @brief This file provides firmware functions to manage the General Watch Dog
+ * Timer(WDT).
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2022-06-30 CDT First version
+ 2023-09-30 CDT Optimize WDT_ClearStatus function timeout
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "hc32_ll_wdt.h"
+#include "hc32_ll_utility.h"
+
+/**
+ * @addtogroup LL_Driver
+ * @{
+ */
+
+/**
+ * @defgroup LL_WDT WDT
+ * @brief General Watch Dog Timer
+ * @{
+ */
+
+#if (LL_WDT_ENABLE == DDL_ON)
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/**
+ * @defgroup WDT_Local_Macros WDT Local Macros
+ * @{
+ */
+
+/* WDT Refresh Key */
+#define WDT_REFRESH_KEY_START (0x0123UL)
+#define WDT_REFRESH_KEY_END (0x3210UL)
+
+/* WDT clear flag timeout(ms) */
+#define WDT_CLR_FLAG_TIMEOUT (200UL)
+
+/* WDT Registers Clear Mask */
+#define WDT_CR_CLR_MASK (WDT_CR_PERI | WDT_CR_CKS | WDT_CR_WDPT | \
+ WDT_CR_SLPOFF | WDT_CR_ITS)
+
+/**
+ * @defgroup WDT_Check_Parameters_Validity WDT Check Parameters Validity
+ * @{
+ */
+#define IS_WDT_CNT_PERIOD(x) \
+( ((x) == WDT_CNT_PERIOD256) || \
+ ((x) == WDT_CNT_PERIOD4096) || \
+ ((x) == WDT_CNT_PERIOD16384) || \
+ ((x) == WDT_CNT_PERIOD65536))
+
+#define IS_WDT_CLK_DIV(x) \
+( ((x) == WDT_CLK_DIV4) || \
+ ((x) == WDT_CLK_DIV64) || \
+ ((x) == WDT_CLK_DIV128) || \
+ ((x) == WDT_CLK_DIV256) || \
+ ((x) == WDT_CLK_DIV512) || \
+ ((x) == WDT_CLK_DIV1024) || \
+ ((x) == WDT_CLK_DIV2048) || \
+ ((x) == WDT_CLK_DIV8192))
+
+#define IS_WDT_REFRESH_RANGE(x) \
+( ((x) == WDT_RANGE_0TO100PCT) || \
+ ((x) == WDT_RANGE_0TO25PCT) || \
+ ((x) == WDT_RANGE_25TO50PCT) || \
+ ((x) == WDT_RANGE_0TO50PCT) || \
+ ((x) == WDT_RANGE_50TO75PCT) || \
+ ((x) == WDT_RANGE_0TO25PCT_50TO75PCT) || \
+ ((x) == WDT_RANGE_25TO75PCT) || \
+ ((x) == WDT_RANGE_0TO75PCT) || \
+ ((x) == WDT_RANGE_75TO100PCT) || \
+ ((x) == WDT_RANGE_0TO25PCT_75TO100PCT) || \
+ ((x) == WDT_RANGE_25TO50PCT_75TO100PCT) || \
+ ((x) == WDT_RANGE_0TO50PCT_75TO100PCT) || \
+ ((x) == WDT_RANGE_50TO100PCT) || \
+ ((x) == WDT_RANGE_0TO25PCT_50TO100PCT) || \
+ ((x) == WDT_RANGE_25TO100PCT))
+
+#define IS_WDT_LPM_CNT(x) \
+( ((x) == WDT_LPM_CNT_CONT) || \
+ ((x) == WDT_LPM_CNT_STOP))
+
+#define IS_WDT_EXP_TYPE(x) \
+( ((x) == WDT_EXP_TYPE_INT) || \
+ ((x) == WDT_EXP_TYPE_RST))
+
+#define IS_WDT_FLAG(x) \
+( ((x) != 0UL) && \
+ (((x) | WDT_FLAG_ALL) == WDT_FLAG_ALL))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @defgroup WDT_Global_Functions WDT Global Functions
+ * @{
+ */
+
+/**
+ * @brief Initializes WDT.
+ * @param [in] pstcWdtInit Pointer to a @ref stc_wdt_init_t structure
+ * @retval int32_t:
+ * - LL_OK: Initializes success
+ * - LL_ERR_INVD_PARAM: pstcWdtInit == NULL
+ */
+int32_t WDT_Init(const stc_wdt_init_t *pstcWdtInit)
+{
+ int32_t i32Ret = LL_OK;
+
+ if (NULL == pstcWdtInit) {
+ i32Ret = LL_ERR_INVD_PARAM;
+ } else {
+ /* Check parameters */
+ DDL_ASSERT(IS_WDT_CNT_PERIOD(pstcWdtInit->u32CountPeriod));
+ DDL_ASSERT(IS_WDT_CLK_DIV(pstcWdtInit->u32ClockDiv));
+ DDL_ASSERT(IS_WDT_REFRESH_RANGE(pstcWdtInit->u32RefreshRange));
+ DDL_ASSERT(IS_WDT_LPM_CNT(pstcWdtInit->u32LPMCount));
+ DDL_ASSERT(IS_WDT_EXP_TYPE(pstcWdtInit->u32ExceptionType));
+
+ /* WDT CR Configuration(Software Start Mode) */
+ MODIFY_REG32(CM_WDT->CR, WDT_CR_CLR_MASK,
+ (pstcWdtInit->u32CountPeriod | pstcWdtInit->u32ClockDiv |
+ pstcWdtInit->u32RefreshRange | pstcWdtInit->u32LPMCount |
+ pstcWdtInit->u32ExceptionType));
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @brief WDT feed dog.
+ * @note In software startup mode, Start counter when refreshing for the first time.
+ * @param None
+ * @retval None
+ */
+void WDT_FeedDog(void)
+{
+ WRITE_REG32(CM_WDT->RR, WDT_REFRESH_KEY_START);
+ WRITE_REG32(CM_WDT->RR, WDT_REFRESH_KEY_END);
+}
+
+/**
+ * @brief Get WDT flag status.
+ * @param [in] u32Flag WDT flag type
+ * This parameter can be one or any combination of the following values:
+ * @arg WDT_FLAG_UDF: Count underflow flag
+ * @arg WDT_FLAG_REFRESH: Refresh error flag
+ * @arg WDT_FLAG_ALL: All of the above
+ * @retval An @ref en_flag_status_t enumeration type value.
+ */
+en_flag_status_t WDT_GetStatus(uint32_t u32Flag)
+{
+ en_flag_status_t enFlagSta = RESET;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_WDT_FLAG(u32Flag));
+
+ if (0UL != (READ_REG32_BIT(CM_WDT->SR, u32Flag))) {
+ enFlagSta = SET;
+ }
+
+ return enFlagSta;
+}
+
+/**
+ * @brief Clear WDT flag.
+ * @param [in] u32Flag WDT flag type
+ * This parameter can be one or any combination of the following values:
+ * @arg WDT_FLAG_UDF: Count underflow flag
+ * @arg WDT_FLAG_REFRESH: Refresh error flag
+ * @arg WDT_FLAG_ALL: All of the above
+ * @retval int32_t:
+ * - LL_OK: Clear flag success
+ * - LL_ERR_TIMEOUT: Clear flag timeout
+ */
+int32_t WDT_ClearStatus(uint32_t u32Flag)
+{
+ __IO uint32_t u32Count;
+ int32_t i32Ret = LL_OK;
+
+ /* Check parameters */
+ DDL_ASSERT(IS_WDT_FLAG(u32Flag));
+
+ /* Waiting for FLAG bit clear */
+ u32Count = WDT_CLR_FLAG_TIMEOUT * (HCLK_VALUE / 25000UL);
+ while (0UL != READ_REG32_BIT(CM_WDT->SR, u32Flag)) {
+ CLR_REG32_BIT(CM_WDT->SR, u32Flag);
+ if (0UL == u32Count) {
+ i32Ret = LL_ERR_TIMEOUT;
+ break;
+ }
+ u32Count--;
+ }
+
+ return i32Ret;
+}
+
+/**
+ * @}
+ */
+
+#endif /* LL_WDT_ENABLE */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************
+ * EOF (not truncated)
+ *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0_RAM.icf b/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0_RAM.icf
deleted file mode 100644
index c1553e99ec..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0_RAM.icf
+++ /dev/null
@@ -1,51 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x1FFE0000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_IROM1_start__ = 0x1FFE0000;
-define symbol __ICFEDIT_region_IROM1_end__ = 0x1FFFFFFF;
-define symbol __ICFEDIT_region_IROM2_start__ = 0x20000000;
-define symbol __ICFEDIT_region_IROM2_end__ = 0x2001FFFF;
-define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
-define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
-define symbol __ICFEDIT_region_IRAM1_start__ = 0x20020000;
-define symbol __ICFEDIT_region_IRAM1_end__ = 0x2005FFFF;
-define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
-define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
-define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
-
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x2000;
-define symbol __ICFEDIT_size_proc_stack__ = 0x0;
-define symbol __ICFEDIT_size_heap__ = 0x2000;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
- | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
- | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xG.icf b/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xG.icf
deleted file mode 100644
index 23fbf9cbbf..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xG.icf
+++ /dev/null
@@ -1,53 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
-define symbol __ICFEDIT_region_IROM1_end__ = 0x000FFFFF;
-define symbol __ICFEDIT_region_IROM2_start__ = 0x03000000;
-define symbol __ICFEDIT_region_IROM2_end__ = 0x030017FF;
-define symbol __ICFEDIT_region_EROM1_start__ = 0x98000000;
-define symbol __ICFEDIT_region_EROM1_end__ = 0x987FFFFF;
-define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
-define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFE0000;
-define symbol __ICFEDIT_region_IRAM1_end__ = 0x2005FFFF;
-define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
-define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
-define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
-
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x2000;
-define symbol __ICFEDIT_size_proc_stack__ = 0x0;
-define symbol __ICFEDIT_size_heap__ = 0x2000;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
- | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
-define region QSPI_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
- | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in QSPI_region { readonly section .ex_rom };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xI.icf b/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xI.icf
deleted file mode 100644
index 4dec7d352b..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/config/linker/HC32F4A0xI.icf
+++ /dev/null
@@ -1,53 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
-define symbol __ICFEDIT_region_IROM1_end__ = 0x001FFFFF;
-define symbol __ICFEDIT_region_IROM2_start__ = 0x03000000;
-define symbol __ICFEDIT_region_IROM2_end__ = 0x030017FF;
-define symbol __ICFEDIT_region_EROM1_start__ = 0x98000000;
-define symbol __ICFEDIT_region_EROM1_end__ = 0x987FFFFF;
-define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
-define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFE0000;
-define symbol __ICFEDIT_region_IRAM1_end__ = 0x2005FFFF;
-define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
-define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
-define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
-
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x2000;
-define symbol __ICFEDIT_size_proc_stack__ = 0x0;
-define symbol __ICFEDIT_size_heap__ = 0x2000;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
- | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
-define region QSPI_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
-define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
- | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in QSPI_region { readonly section .ex_rom };
-place in RAM_region { readwrite,
- block CSTACK, block HEAP };
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_common.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_common.h
deleted file mode 100644
index 7758a3d83e..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_common.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/**
- *******************************************************************************
- * @file stl_common.h
- * @brief This file contains STL common definitions: enumeration, macros and
- * structures definitions.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_COMMON_H__
-#define __STL_COMMON_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "hc32_ll_def.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup IEC60730_STL
- * @{
- */
-
-/**
- * @addtogroup IEC60730_STL_Common
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/**
- * @defgroup STL_Common_Global_Macros STL Common Global Macros
- * @{
- */
-
-/**
- * @defgroup STL_Generic_Error_Codes STL Generic Error Codes
- * @{
- */
-#define STL_OK (0UL) /*!< No error occurs */
-#define STL_ERR (1UL) /*!< Error occurs */
-/**
- * @}
- */
-
-/**
- * @defgroup STL_Module_Switch STL Module Switch
- * @{
- */
-#define STL_ON (1U)
-#define STL_OFF (0U)
-/**
- * @}
- */
-
-/**
- * @defgroup Compiler_Macros Compiler Macros
- * @{
- */
-#ifdef __CC_ARM /*!< ARM Compiler */
-/* CPU will start executing at the program entry label __main when the CPU is reset */
-extern void __main(void);
-
-/* CC */
-#define STL_SECTION(x) __attribute__((section(x)))
-#define STL_UNUSED __attribute__((unused))
-#define STL_USED __attribute__((used))
-#define STL_ALIGN(n) __attribute__((aligned(n)))
-#define STL_WEAK __WEAKDEF
-#define STL_INLINE static __inline
-
-#define CallApplicationStartUp( ) __main()
-
-#elif defined (__ICCARM__) /*!< IAR Compiler */
-/* CPU will start executing at the program entry label __iar_program_start when the CPU is reset */
-extern void __iar_program_start(void);
-
-/* CC */
-#define STL_SECTION(x) @ x
-#define STL_UNUSED
-#define STL_USED __root
-#define STL_PRAGMA(x) _Pragma(#x)
-#define STL_ALIGN(n) STL_PRAGMA(data_alignment=n)
-#define STL_WEAK __WEAKDEF
-#define STL_INLINE static inline
-
-#define CallApplicationStartUp( ) __iar_program_start()
-#else
-#error Unsupported tool chain
-#endif
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_COMMON_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_conf.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_conf.h
deleted file mode 100644
index 0f5b7d0113..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_conf.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/**
- *******************************************************************************
- * @file stl_conf.h
- * @brief This file contains STL resource configure.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2022-06-30 CDT Optimize macros definitions
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_CONF_H__
-#define __STL_CONF_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_bsp_conf.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup IEC60730_STL
- * @{
- */
-
-/**
- * @addtogroup IEC60730_STL_Configure
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/**
- * @defgroup IEC60730_STL_Configure_ROM_CRC32_Parameters IEC60730 STL Configure ROM CRC32 Parameters
- * @{
- */
-#define STL_ROM_CRC32_START (STL_ROM_START)
-#define STL_ROM_CRC32_END ((uint32_t)(&__checksum))
-#define STL_ROM_CRC32_BLOCK_SIZE (128UL)
-#define STL_ROM_CRC32_CC_CHECKSUM (__checksum)
-/**
- * @}
- */
-
-/**
- * @defgroup IEC60730_STL_Configure_RAM_Parameters IEC60730 STL Configure RAM Parameters
- * @{
- */
-#define STL_MARCH_RAM_SIZE (32UL)
-#define STL_MARCH_RAM_WORDS (STL_MARCH_RAM_SIZE >> 2)
-#define STL_MARCH_RAM_BUF_SIZE (16UL)
-#define STL_MARCH_RAM_BUF_WORDS (STL_MARCH_RAM_BUF_SIZE >> 2)
-
-#define STL_MARCH_RAM_BCKGRND (0x00000000UL)
-#define STL_MARCH_RAM_INVBCKGRND (0xFFFFFFFFUL)
-
-#define STL_STACK_BOUNDARY_WORDS (4UL)
-/**
- * @}
- */
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_CONF_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_sw_crc32.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_sw_crc32.h
deleted file mode 100644
index f90268c03c..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_sw_crc32.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/**
- *******************************************************************************
- * @file stl_test_flash.h
- * @brief This file contains all the functions prototypes of the flash test.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_SW_CRC32_H__
-#define __STL_SW_CRC32_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_common.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @addtogroup STL_IEC60730_CRC32
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/**
- * @defgroup STL_IEC60730_CRC32_Global_Macros STL IEC60730 CRC32 Global Macros
- * @{
- */
-#define STL_CRC32_INIT_VALUE (0xFFFFFFFFUL)
-/**
- * @}
- */
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-/**
- * @addtogroup STL_IEC60730_CRC32_Global_Functions
- * @{
- */
-uint32_t STL_CalculateCRC32Value(uint32_t u32Crc32Value, uint8_t *pu8Data, uint32_t u32Len);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_SW_CRC32_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_cpu.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_cpu.h
deleted file mode 100644
index a5e0df3d48..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_cpu.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
- *******************************************************************************
- * @file stl_test_cpu.h
- * @brief This file contains all the functions prototypes of the CPU test.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_TEST_CPU_H__
-#define __STL_TEST_CPU_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_common.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @addtogroup STL_IEC60730_CPU
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-/**
- * @addtogroup STL_IEC60730_CPU_Global_Functions
- * @{
- */
-uint32_t STL_CpuTestStartup(void);
-uint32_t STL_CpuTestRuntime(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_TEST_CPU_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_flash.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_flash.h
deleted file mode 100644
index 932b8c3a46..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_flash.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
- *******************************************************************************
- * @file stl_test_flash.h
- * @brief This file contains all the functions prototypes of the flash test.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_TEST_FLASH_H__
-#define __STL_TEST_FLASH_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_common.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @addtogroup STL_IEC60730_Flash
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-/**
- * @addtogroup STL_IEC60730_Flash_Global_Functions
- * @{
- */
-uint32_t STL_FlashStartupTest(void);
-uint32_t STL_FlashRuntimeTest(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_TEST_FLASH_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_interrupt.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_interrupt.h
deleted file mode 100644
index fd0ed7c26b..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_interrupt.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/**
- *******************************************************************************
- * @file stl_test_interrupt.h
- * @brief This file contains all the functions prototypes of the interrupt test.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_TEST_INTERRUPT_H__
-#define __STL_TEST_INTERRUPT_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_common.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @addtogroup STL_IEC60730_Interrupt
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-/**
- * @defgroup STL_IEC60730_Interrupt_Global_Type STL IEC60730 Interrupt Global Type
- * @{
- */
-typedef struct stc_stl_int_params {
- uint32_t u32FreqInitVal;
- uint32_t u32FreqLowerVal;
- uint32_t u32FreqUpperVal;
- uint32_t u32PrivateParam;
-} stc_stl_int_params_t;
-/**
- * @}
- */
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-/**
- * @addtogroup STL_IEC60730_Interrupt_Global_Functions
- * @{
- */
-uint32_t STL_IntRuntimeTableInit(stc_stl_int_params_t *pstcParamsTable, uint32_t u32TableSize);
-uint32_t STL_IntRuntimeTest(void);
-void STL_IntUpdateCount(uint8_t u8ParamIndex);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_TEST_INTERRUPT_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_pc.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_pc.h
deleted file mode 100644
index dce5b91b8e..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_pc.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/**
- *******************************************************************************
- * @file stl_test_pc.h
- * @brief This file contains all the functions prototypes of the PC test.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_TEST_PC_H__
-#define __STL_TEST_PC_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_common.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @addtogroup STL_IEC60730_PC
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-/**
- * @addtogroup STL_IEC60730_PC_Global_Functions
- * @{
- */
-uint32_t STL_PcTest(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_TEST_PC_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_ram.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_ram.h
deleted file mode 100644
index 8e7983dc40..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_ram.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/**
- *******************************************************************************
- * @file stl_test_ram.h
- * @brief This file contains all the functions prototypes of the RAM test.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_TEST_RAM_H__
-#define __STL_TEST_RAM_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_common.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @addtogroup STL_IEC60730_RAM
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-/**
- * @addtogroup STL_IEC60730_RAM_Global_Functions
- * @{
- */
-uint32_t STL_StackRuntimeInit(void);
-uint32_t STL_StackRuntimeTest(void);
-uint32_t STL_RamRuntimeInit(void);
-uint32_t STL_RamRuntimeTest(void);
-uint32_t STL_FullRamTestStartup(uint32_t u32StartAddr, uint32_t u32EndAddr);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_TEST_RAM_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm0_startup.s b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm0_startup.s
deleted file mode 100644
index 94582f336c..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm0_startup.s
+++ /dev/null
@@ -1,372 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; * opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/* Test for IAR */
-;/* Version V1.0 */
-;/* Date 2022-09-14 */
-;/****************************************************************************/
-
- SECTION constdata:CONST(2)
-data0xAAAAAAAA DCD 0xAAAAAAAA
-data0x55555555 DCD 0x55555555
-data0x80000000 DCD 0x80000000
-data0xAAAAAAA8 DCD 0xAAAAAAA8
-data0x55555554 DCD 0x55555554
-data0x00000000 DCD 0x00000000
-data0x00000001 DCD 0x00000001
-data0x50000000 DCD 0x50000000
-data0xA0000000 DCD 0xA0000000
-
- ; Exported function
- EXPORT STL_CpuTestStartup
-
-;*******************************************************************************
-; Function Name : STL_CpuTestStartup
-; Description : Test CPU at start-up
-; Input : None.
-; Output : Perform routine when detect failure at set of self test cases
-; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING : all registers destroyed when exiting this function (including
-; preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
- THUMB
- SECTION .text:CODE(2)
-STL_CpuTestStartup:
- PUSH {R4-R7} ; Save registers
-
-_test_cpu_reg0_reg8
- MOVS R0, #0x00
- UXTB R0, R0
- ADDS R0, #0 ; Set Z(ero) Flag
- BNE _test_cpu_reg0_reg13_fail ; Fails if Z clear
- BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
- SUBS R0, #1 ; Set N(egative) Flag
- BPL _test_cpu_reg0_reg13_fail ; Fails if N clear
- ADDS R0, #2 ; Set C(arry) Flag and do not set Z
- BCC _test_cpu_reg0_reg13_fail ; Fails if C clear
- BEQ _test_cpu_reg0_reg13_fail ; Fails if Z is set
- BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
-
- LDR R0, =data0x80000000 ; Prepares Overflow test
- LDR R0, [R0]
- ADDS R0, R0, R0 ; Set V(overflow) Flag
- BVC _test_cpu_reg0_reg13_fail ; Fails if V clear
-
- ; Register R1
- LDR R0, =data0xAAAAAAAA
- LDR R1, [R0]
- LDR R0, [R0]
- CMP R0, R1
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R1, [R0]
- LDR R0, [R0]
- CMP R0, R1
- BNE _test_cpu_reg0_reg13_fail
- MOVS R1, #0x1
-
- ; Register R2
- LDR R0, =data0xAAAAAAAA
- LDR R2, [R0]
- LDR R0, [R0]
- CMP R0, R2
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R2, [R0]
- LDR R0, [R0]
- CMP R0, R2
- BNE _test_cpu_reg0_reg13_fail
- MOVS R2, #0x2
-
- ; Register R3
- LDR R0, =data0xAAAAAAAA
- LDR R3, [R0]
- LDR R0, [R0]
- CMP R0, R3
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R3, [R0]
- LDR R0, [R0]
- CMP R0, R3
- BNE _test_cpu_reg0_reg13_fail
- MOVS R3, #0x3
-
- ; Register R4
- LDR R0, =data0xAAAAAAAA
- LDR R4, [R0]
- LDR R0, [R0]
- CMP R0, R4
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R4, [R0]
- LDR R0, [R0]
- CMP R0, R4
- BNE _test_cpu_reg0_reg13_fail
- MOVS R4, #0x4
-
- ; Register R5
- LDR R0, =data0xAAAAAAAA
- LDR R5, [R0]
- LDR R0, [R0]
- CMP R0, R5
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R5, [R0]
- LDR R0, [R0]
- CMP R0, R5
- BNE _test_cpu_reg0_reg13_fail
- MOVS R5, #0x5
-
- ; Register R6
- LDR R0, =data0xAAAAAAAA
- LDR R6, [R0]
- LDR R0, [R0]
- CMP R0, R6
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R6, [R0]
- LDR R0, [R0]
- CMP R0, R6
- BNE _test_cpu_reg0_reg13_fail
- MOVS R6, #0x6
-
- ; Register R7
- LDR R0, =data0xAAAAAAAA
- LDR R7, [R0]
- LDR R0, [R0]
- CMP R0, R7
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R7, [R0]
- LDR R0, [R0]
- CMP R0, R7
- BNE _test_cpu_reg0_reg13_fail
- MOVS R7, #0x7
-
- ; Register R8
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R8, R0
- CMP R0, R8
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R8, R0
- CMP R0, R8
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x08
- MOV R8, R0
-
- BAL _test_cpu_continue
-
-_test_cpu_reg0_reg13_fail
- ; test fail, R0 will hold value 1
- MOVS R0, #0x1 ; STL_ERR
- B _test_exit
-
-_test_cpu_continue
- ; Register R9
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R9, R0
- CMP R0, R9
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R9, R0
- CMP R0, R9
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x09
- MOV R9, R0
-
- ; Register R10
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R10, R0
- CMP R0, R10
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R10, R0
- CMP R0, R10
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0A
- MOV R10, R0
-
- ; Register R11
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R11, R0
- CMP R0, R11
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R11, R0
- CMP R0, R11
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0B
- MOV R11, R0
-
- ; Register R12
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R12, R0
- CMP R0, R12
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R12, R0
- CMP R0, R12
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0C
- MOV R12, R0
- LDR R0, =_test_cpu_continue
-
- ; pattern verification (R0 is not tested)
- CMP R1, #0x01
- BNE _test_cpu_reg0_reg13_fail
- CMP R2, #0x02
- BNE _test_cpu_reg0_reg13_fail
- CMP R3, #0x03
- BNE _test_cpu_reg0_reg13_fail
- CMP R4, #0x04
- BNE _test_cpu_reg0_reg13_fail
- CMP R5, #0x05
- BNE _test_cpu_reg0_reg13_fail
- CMP R6, #0x06
- BNE _test_cpu_reg0_reg13_fail
- CMP R7, #0x07
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x08
- CMP R0, R8
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x09
- CMP R0, R9
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0A
- CMP R0, R10
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0B
- CMP R0, R11
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0C
- CMP R0, R12
- BNE _test_cpu_reg0_reg13_fail
-
- ; Process Stack pointer (banked Register R13)
- MRS R0, PSP ; Save process stack value
- LDR R1, =data0xAAAAAAA8 ; Test is different (PSP is word aligned, 2 LSB cleared)
- LDR R1, [R1]
- MSR PSP, R1 ; load process stack value
- MRS R2, PSP ; Get back process stack value
- CMP R2, R1 ; Verify value
- BNE _test_cpu_reg0_reg13_fail
- LDR R1, =data0x55555554 ; Test is different (PSP is word aligned, 2 LSB cleared)
- LDR R1, [R1]
- MSR PSP, R1 ; load process stack value
- MRS R2, PSP ; Get back process stack value
- CMP R2, R1 ; Verify value
- BNE _test_cpu_reg0_reg13_fail
- MSR PSP, R0 ; Restore process stack value
-
- ; Stack pointer (Register R13)
- MRS R0, MSP ; Save stack pointer value
- LDR R1, =data0xAAAAAAA8 ; Test is different (SP is word aligned, 2 LSB cleared)
- LDR R1, [R1]
- MSR MSP, R1 ; load SP value
- MRS R2, MSP ; Get back SP value
- CMP R2, R1 ; Verify value
- BNE _test_cpu_reg0_reg13_fail
- LDR R1, =data0x55555554
- LDR R1, [R1] ; load SP value
- MSR MSP, R1 ; Get back SP value
- MRS R2, MSP ; Verify value
- CMP R2, R1
- BNE _test_cpu_reg0_reg13_fail
- MSR MSP, R0 ; Restore stack pointer value
-
-_test_cpu_r14_sfr
- ; Link register R14
- MOV R1, LR
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
-
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
-
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
-
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
- MOV LR, R1
-
- ; APSR
- MRS R0, APSR
- LDR R1, =data0x50000000
- LDR R1,[R1]
- MSR APSR,R1
- MRS R2, APSR
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
-
- LDR R1, =data0xA0000000
- LDR R1,[R1]
- MSR APSR,R1
- MRS R2, APSR
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
- MSR APSR,R0
-
- ; PRIMASK register
- MRS R0, PRIMASK
- LDR R1, =data0x00000000
- LDR R1, [R1]
- MSR PRIMASK, R1
- MRS R2, PRIMASK
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
-
- LDR R1, =data0x00000001
- LDR R1, [R1]
- MSR PRIMASK, R1
- MRS R2, PRIMASK
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
- MSR PRIMASK, R0
- B _test_cpu_pass
-
-_test_cpu_r14_sfr_fail
- ; test fail, R0 will hold value 1
- MOVS R0, #0x1 ; STL_ERR
- B _test_exit
-
-_test_cpu_pass
- ; test pass, R0 will hold value 0
- MOVS R0, #0x0 ; STL_OK
- B _test_exit
-
-_test_exit
- POP {R4-R7} ; Restore registers
- BX LR
-
- END
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm4_startup.s b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm4_startup.s
deleted file mode 100644
index 5abb5a8216..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm4_startup.s
+++ /dev/null
@@ -1,420 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; * opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/* Test for IAR */
-;/* Date Author Notes */
-;/* 2022-09-14 CDT First version */
-;/* 2022-12-20 CDT Load data to R0 before USAT */
-;/* 2023-05-31 CDT Typo: Veriry -> Verify */
-;/****************************************************************************/
-
- SECTION constdata:CONST(2)
-data0xAAAAAAAA DCD 0xAAAAAAAA
-data0x55555555 DCD 0x55555555
-data0x80000000 DCD 0x80000000
-data0xAAAAAAA8 DCD 0xAAAAAAA8
-data0x55555554 DCD 0x55555554
-data0x00000000 DCD 0x00000000
-data0x00000001 DCD 0x00000001
-data0x50000000 DCD 0x50000000
-data0xA8000000 DCD 0xA8000000
-data0x00000050 DCD 0x00000050
-data0x000000A0 DCD 0x000000A0
-data0xFFFFFFFF DCD 0xFFFFFFFF
-
- ; Exported function
- EXPORT STL_CpuTestStartup
-
-;*******************************************************************************
-; Function Name : STL_CpuTestStartup
-; Description : Test CPU at start-up
-; Input : None.
-; Output : Perform routine when detect failure at set of self test cases
-; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING : all registers destroyed when exiting this function (including
-; preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
- THUMB
- SECTION .text:CODE(2)
-STL_CpuTestStartup:
- PUSH {R4-R7} ; Save registers
-
-_test_cpu_reg0_reg8
- MOVS R0, #0x00
- UXTB R0, R0
- ADDS R0, #0 ; Set Z(ero) Flag
- BNE _test_cpu_reg0_reg13_fail ; Fails if Z clear
- BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
- SUBS R0, #1 ; Set N(egative) Flag
- BPL _test_cpu_reg0_reg13_fail ; Fails if N clear
- ADDS R0, #2 ; Set C(arry) Flag and do not set Z
- BCC _test_cpu_reg0_reg13_fail ; Fails if C clear
- BEQ _test_cpu_reg0_reg13_fail ; Fails if Z is set
- BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
-
- LDR R0, =data0x80000000 ; Prepares Overflow test
- LDR R0, [R0]
- ADDS R0, R0, R0 ; Set V(overflow) Flag
- BVC _test_cpu_reg0_reg13_fail ; Fails if V clear
-
- MOV R0, #0
- MSR APSR, R0
- LDR R0, =data0xFFFFFFFF ; Prepares Saturation test
- LDR R0, [R0]
- USAT R1, #10, R0 ; Set Q(saturation) flag
- MRS R0, APSR ; Get APSR status register
- CMP R0, #0x08000000 ; Verify Q=1
- BNE _test_cpu_reg0_reg13_fail ; Fails if Q is set
-
- ; Register R1
- LDR R0, =data0xAAAAAAAA
- LDR R1, [R0]
- LDR R0, [R0]
- CMP R0, R1
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R1, [R0]
- LDR R0, [R0]
- CMP R0, R1
- BNE _test_cpu_reg0_reg13_fail
- MOVS R1, #0x1
-
- ; Register R2
- LDR R0, =data0xAAAAAAAA
- LDR R2, [R0]
- LDR R0, [R0]
- CMP R0, R2
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R2, [R0]
- LDR R0, [R0]
- CMP R0, R2
- BNE _test_cpu_reg0_reg13_fail
- MOVS R2, #0x2
-
- ; Register R3
- LDR R0, =data0xAAAAAAAA
- LDR R3, [R0]
- LDR R0, [R0]
- CMP R0, R3
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R3, [R0]
- LDR R0, [R0]
- CMP R0, R3
- BNE _test_cpu_reg0_reg13_fail
- MOVS R3, #0x3
-
- ; Register R4
- LDR R0, =data0xAAAAAAAA
- LDR R4, [R0]
- LDR R0, [R0]
- CMP R0, R4
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R4, [R0]
- LDR R0, [R0]
- CMP R0, R4
- BNE _test_cpu_reg0_reg13_fail
- MOVS R4, #0x4
-
- ; Register R5
- LDR R0, =data0xAAAAAAAA
- LDR R5, [R0]
- LDR R0, [R0]
- CMP R0, R5
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R5, [R0]
- LDR R0, [R0]
- CMP R0, R5
- BNE _test_cpu_reg0_reg13_fail
- MOVS R5, #0x5
-
- ; Register R6
- LDR R0, =data0xAAAAAAAA
- LDR R6, [R0]
- LDR R0, [R0]
- CMP R0, R6
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R6, [R0]
- LDR R0, [R0]
- CMP R0, R6
- BNE _test_cpu_reg0_reg13_fail
- MOVS R6, #0x6
-
- ; Register R7
- LDR R0, =data0xAAAAAAAA
- LDR R7, [R0]
- LDR R0, [R0]
- CMP R0, R7
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R7, [R0]
- LDR R0, [R0]
- CMP R0, R7
- BNE _test_cpu_reg0_reg13_fail
- MOVS R7, #0x7
-
- ; Register R8
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R8, R0
- CMP R0, R8
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R8, R0
- CMP R0, R8
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x08
- MOV R8, R0
-
- BAL _test_cpu_continue
-
-_test_cpu_reg0_reg13_fail
- ; test fail, R0 will hold value 1
- MOVS R0, #0x1 ; STL_ERR
- B _test_exit
-
-_test_cpu_continue
- ; Register R9
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R9, R0
- CMP R0, R9
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R9, R0
- CMP R0, R9
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x09
- MOV R9, R0
-
- ; Register R10
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R10, R0
- CMP R0, R10
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R10, R0
- CMP R0, R10
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0A
- MOV R10, R0
-
- ; Register R11
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R11, R0
- CMP R0, R11
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R11, R0
- CMP R0, R11
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0B
- MOV R11, R0
-
- ; Register R12
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R12, R0
- CMP R0, R12
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R12, R0
- CMP R0, R12
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0C
- MOV R12, R0
- LDR R0, =_test_cpu_continue
-
- ; pattern verification (R0 is not tested)
- CMP R1, #0x01
- BNE _test_cpu_reg0_reg13_fail
- CMP R2, #0x02
- BNE _test_cpu_reg0_reg13_fail
- CMP R3, #0x03
- BNE _test_cpu_reg0_reg13_fail
- CMP R4, #0x04
- BNE _test_cpu_reg0_reg13_fail
- CMP R5, #0x05
- BNE _test_cpu_reg0_reg13_fail
- CMP R6, #0x06
- BNE _test_cpu_reg0_reg13_fail
- CMP R7, #0x07
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x08
- CMP R0, R8
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x09
- CMP R0, R9
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0A
- CMP R0, R10
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0B
- CMP R0, R11
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0C
- CMP R0, R12
- BNE _test_cpu_reg0_reg13_fail
-
- ; Process Stack pointer (banked Register R13)
- MRS R0, PSP ; Save process stack value
- LDR R1, =data0xAAAAAAA8 ; Test is different (PSP is word aligned, 2 LSB cleared)
- LDR R1, [R1]
- MSR PSP, R1 ; load process stack value
- MRS R2, PSP ; Get back process stack value
- CMP R2, R1 ; Verify value
- BNE _test_cpu_reg0_reg13_fail
- LDR R1, =data0x55555554 ; Test is different (PSP is word aligned, 2 LSB cleared)
- LDR R1, [R1]
- MSR PSP, R1 ; load process stack value
- MRS R2, PSP ; Get back process stack value
- CMP R2, R1 ; Verify value
- BNE _test_cpu_reg0_reg13_fail
- MSR PSP, R0 ; Restore process stack value
-
- ; Stack pointer (Register R13)
- MRS R0, MSP ; Save stack pointer value
- LDR R1, =data0xAAAAAAA8 ; Test is different (SP is word aligned, 2 LSB cleared)
- LDR R1, [R1]
- MSR MSP, R1 ; load SP value
- MRS R2, MSP ; Get back SP value
- CMP R2, R1 ; Verify value
- BNE _test_cpu_reg0_reg13_fail
- LDR R1, =data0x55555554
- LDR R1, [R1] ; load SP value
- MSR MSP, R1 ; Get back SP value
- MRS R2, MSP ; Verify value
- CMP R2, R1
- BNE _test_cpu_reg0_reg13_fail
- MSR MSP, R0 ; Restore stack pointer value
-
-_test_cpu_r14_sfr
- ; Link register R14
- MOV R1, LR
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
-
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
-
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
-
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
- MOV LR, R1
-
- ; APSR
- MRS R0, APSR
- LDR R1, =data0x50000000
- LDR R1,[R1]
- MSR APSR,R1
- MRS R2, APSR
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
-
- LDR R1, =data0xA8000000
- LDR R1,[R1]
- MSR APSR,R1
- MRS R2, APSR
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
- MSR APSR,R0
-
- ; PRIMASK register
- MRS R0, PRIMASK
- LDR R1, =data0x00000000
- LDR R1, [R1]
- MSR PRIMASK, R1
- MRS R2, PRIMASK
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
-
- LDR R1, =data0x00000001
- LDR R1, [R1]
- MSR PRIMASK, R1
- MRS R2, PRIMASK
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
- MSR PRIMASK, R0
-
- ; FAULTMASK register
- MRS R0, FAULTMASK
- LDR R1, =data0x00000000
- LDR R1, [R1]
- MSR FAULTMASK, R1
- MRS R2, FAULTMASK
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
-
- LDR R1, =data0x00000001
- LDR R1, [R1]
- MSR FAULTMASK, R1
- MRS R2, FAULTMASK
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
- MSR FAULTMASK, R0
-
- ; BASEPRI register
- MRS R0, BASEPRI
- LDR R1, =data0x000000A0
- LDR R1, [R1]
- MSR BASEPRI, R1
- MRS R2, BASEPRI
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
-
- LDR R1, =data0x00000050
- LDR R1, [R1]
- MSR BASEPRI, R1
- MRS R2, BASEPRI
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
- MSR BASEPRI, R0
- B _test_cpu_pass
-
-_test_cpu_r14_sfr_fail
- ; test fail, R0 will hold value 1
- MOVS R0, #0x1 ; STL_ERR
- B _test_exit
-
-_test_cpu_pass
- ; test pass, R0 will hold value 0
- MOVS R0, #0x0 ; STL_OK
- B _test_exit
-
-_test_exit
- POP {R4-R7} ; Restore registers
- BX LR
-
- END
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_runtime.s b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_runtime.s
deleted file mode 100644
index d02dd7325a..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_runtime.s
+++ /dev/null
@@ -1,245 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; * opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/* Test for IAR */
-;/* Version V1.0 */
-;/* Date 2022-03-31 */
-;/****************************************************************************/
-
- SECTION constdata:CONST(2)
-data0xAAAAAAAA DCD 0xAAAAAAAA
-data0x55555555 DCD 0x55555555
-
- ; Exported function
- EXPORT STL_CpuTestRuntime
-
-;*******************************************************************************
-; Function Name : STL_CpuTestRuntime
-; Description : Test CPU at run-time
-; Input : None.
-; Output : Perform routine when detect failure at set of self test cases
-; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING : all registers destroyed when exiting this function (including
-; preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
- THUMB
- SECTION .text:CODE(2)
-STL_CpuTestRuntime:
- PUSH {R4-R7} ; Save registers
-
- ; Register R1
- LDR R0, =data0xAAAAAAAA
- LDR R1, [R0]
- LDR R0, [R0]
- CMP R0, R1
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R1, [R0]
- LDR R0, [R0]
- CMP R0, R1
- BNE _test_cpu_fail
- MOVS R1, #0x1
-
- ; Register R2
- LDR R0, =data0xAAAAAAAA
- LDR R2, [R0]
- LDR R0, [R0]
- CMP R0, R2
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R2, [R0]
- LDR R0, [R0]
- CMP R0, R2
- BNE _test_cpu_fail
- MOVS R2, #0x2
-
- ; Register R3
- LDR R0, =data0xAAAAAAAA
- LDR R3, [R0]
- LDR R0, [R0]
- CMP R0, R3
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R3, [R0]
- LDR R0, [R0]
- CMP R0, R3
- BNE _test_cpu_fail
- MOVS R3, #0x3
-
- ; Register R4
- LDR R0, =data0xAAAAAAAA
- LDR R4, [R0]
- LDR R0, [R0]
- CMP R0, R4
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R4, [R0]
- LDR R0, [R0]
- CMP R0, R4
- BNE _test_cpu_fail
- MOVS R4, #0x4
-
- ; Register R5
- LDR R0, =data0xAAAAAAAA
- LDR R5, [R0]
- LDR R0, [R0]
- CMP R0, R5
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R5, [R0]
- LDR R0, [R0]
- CMP R0, R5
- BNE _test_cpu_fail
- MOVS R5, #0x5
-
- ; Register R6
- LDR R0, =data0xAAAAAAAA
- LDR R6, [R0]
- LDR R0, [R0]
- CMP R0, R6
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R6, [R0]
- LDR R0, [R0]
- CMP R0, R6
- BNE _test_cpu_fail
- MOVS R6, #0x6
-
- ; Register R7
- LDR R0, =data0xAAAAAAAA
- LDR R7, [R0]
- LDR R0, [R0]
- CMP R0, R7
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R7, [R0]
- LDR R0, [R0]
- CMP R0, R7
- BNE _test_cpu_fail
- MOVS R7, #0x7
-
- ; Register R8
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R8, R0
- CMP R0, R8
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R8, R0
- CMP R0, R8
- BNE _test_cpu_fail
- MOVS R0, #0x08
- MOV R8, R0
-
- BAL _test_cpu_continue
-
-_test_cpu_fail
- ; test fail, R0 will hold value 1
- MOVS R0, #0x1 ; STL_ERR
- B _test_exit
-
-_test_cpu_continue
- ; Register R9
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R9, R0
- CMP R0, R9
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R9, R0
- CMP R0, R9
- BNE _test_cpu_fail
- MOVS R0, #0x09
- MOV R9, R0
-
- ; Register R10
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R10, R0
- CMP R0, R10
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R10, R0
- CMP R0, R10
- BNE _test_cpu_fail
- MOVS R0, #0x0A
- MOV R10, R0
-
- ; Register R11
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R11, R0
- CMP R0, R11
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R11, R0
- CMP R0, R11
- BNE _test_cpu_fail
- MOVS R0, #0x0B
- MOV R11, R0
-
- ; Register R12
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R12, R0
- CMP R0, R12
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R12, R0
- CMP R0, R12
- BNE _test_cpu_fail
- MOVS R0, #0x0C
- MOV R12, R0
- LDR R0, =_test_cpu_continue
-
- ; pattern verification (R0 is not tested)
- CMP R1, #0x01
- BNE _test_cpu_fail
- CMP R2, #0x02
- BNE _test_cpu_fail
- CMP R3, #0x03
- BNE _test_cpu_fail
- CMP R4, #0x04
- BNE _test_cpu_fail
- CMP R5, #0x05
- BNE _test_cpu_fail
- CMP R6, #0x06
- BNE _test_cpu_fail
- CMP R7, #0x07
- BNE _test_cpu_fail
- MOVS R0, #0x08
- CMP R0, R8
- BNE _test_cpu_fail
- MOVS R0, #0x09
- CMP R0, R9
- BNE _test_cpu_fail
- MOVS R0, #0x0A
- CMP R0, R10
- BNE _test_cpu_fail
- MOVS R0, #0x0B
- CMP R0, R11
- BNE _test_cpu_fail
- MOVS R0, #0x0C
- CMP R0, R12
- BNE _test_cpu_fail
-
- ; Link register R14
- ; test pass, R0 will hold value 0
- MOVS R0, #0x0 ; STL_OK
-_test_exit
- POP {R4-R7} ; Restore registers
- BX LR ; return
-
- END
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_startup.s b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_startup.s
deleted file mode 100644
index 186c49e205..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_startup.s
+++ /dev/null
@@ -1,357 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; * opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/* Test for IAR */
-;/* Version V1.0 */
-;/* Date 2022-03-31 */
-;/****************************************************************************/
-
- SECTION constdata:CONST(2)
-data0xAAAAAAAA DCD 0xAAAAAAAA
-data0x55555555 DCD 0x55555555
-data0x80000000 DCD 0x80000000
-data0xAAAAAAA8 DCD 0xAAAAAAA8
-data0x55555554 DCD 0x55555554
-data0x00000000 DCD 0x00000000
-data0x00000001 DCD 0x00000001
-
- ; Exported function
- EXPORT STL_CpuTestStartup
-
-;*******************************************************************************
-; Function Name : STL_CpuTestStartup
-; Description : Test CPU at start-up
-; Input : None.
-; Output : Perform routine when detect failure at set of self test cases
-; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING : all registers destroyed when exiting this function (including
-; preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
- THUMB
- SECTION .text:CODE(2)
-STL_CpuTestStartup:
- PUSH {R4-R7} ; Save registers
-
-_test_cpu_reg0_reg8
- MOVS R0, #0x00
- UXTB R0, R0
- ADDS R0, #0 ; Set Z(ero) Flag
- BNE _test_cpu_reg0_reg13_fail ; Fails if Z clear
- BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
- SUBS R0, #1 ; Set N(egative) Flag
- BPL _test_cpu_reg0_reg13_fail ; Fails if N clear
- ADDS R0, #2 ; Set C(arry) Flag and do not set Z
- BCC _test_cpu_reg0_reg13_fail ; Fails if C clear
- BEQ _test_cpu_reg0_reg13_fail ; Fails if Z is set
- BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
-
- LDR R0, =data0x80000000 ; Prepares Overflow test
- LDR R0, [R0]
- ADDS R0, R0, R0 ; Set V(overflow) Flag
- BVC _test_cpu_reg0_reg13_fail ; Fails if V clear
-
- ; Register R1
- LDR R0, =data0xAAAAAAAA
- LDR R1, [R0]
- LDR R0, [R0]
- CMP R0, R1
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R1, [R0]
- LDR R0, [R0]
- CMP R0, R1
- BNE _test_cpu_reg0_reg13_fail
- MOVS R1, #0x1
-
- ; Register R2
- LDR R0, =data0xAAAAAAAA
- LDR R2, [R0]
- LDR R0, [R0]
- CMP R0, R2
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R2, [R0]
- LDR R0, [R0]
- CMP R0, R2
- BNE _test_cpu_reg0_reg13_fail
- MOVS R2, #0x2
-
- ; Register R3
- LDR R0, =data0xAAAAAAAA
- LDR R3, [R0]
- LDR R0, [R0]
- CMP R0, R3
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R3, [R0]
- LDR R0, [R0]
- CMP R0, R3
- BNE _test_cpu_reg0_reg13_fail
- MOVS R3, #0x3
-
- ; Register R4
- LDR R0, =data0xAAAAAAAA
- LDR R4, [R0]
- LDR R0, [R0]
- CMP R0, R4
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R4, [R0]
- LDR R0, [R0]
- CMP R0, R4
- BNE _test_cpu_reg0_reg13_fail
- MOVS R4, #0x4
-
- ; Register R5
- LDR R0, =data0xAAAAAAAA
- LDR R5, [R0]
- LDR R0, [R0]
- CMP R0, R5
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R5, [R0]
- LDR R0, [R0]
- CMP R0, R5
- BNE _test_cpu_reg0_reg13_fail
- MOVS R5, #0x5
-
- ; Register R6
- LDR R0, =data0xAAAAAAAA
- LDR R6, [R0]
- LDR R0, [R0]
- CMP R0, R6
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R6, [R0]
- LDR R0, [R0]
- CMP R0, R6
- BNE _test_cpu_reg0_reg13_fail
- MOVS R6, #0x6
-
- ; Register R7
- LDR R0, =data0xAAAAAAAA
- LDR R7, [R0]
- LDR R0, [R0]
- CMP R0, R7
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R7, [R0]
- LDR R0, [R0]
- CMP R0, R7
- BNE _test_cpu_reg0_reg13_fail
- MOVS R7, #0x7
-
- ; Register R8
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R8, R0
- CMP R0, R8
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R8, R0
- CMP R0, R8
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x08
- MOV R8, R0
-
- BAL _test_cpu_continue
-
-_test_cpu_reg0_reg13_fail
- ; test fail, R0 will hold value 1
- MOVS R0, #0x1 ; STL_ERR
- B _test_exit
-
-_test_cpu_continue
- ; Register R9
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R9, R0
- CMP R0, R9
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R9, R0
- CMP R0, R9
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x09
- MOV R9, R0
-
- ; Register R10
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R10, R0
- CMP R0, R10
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R10, R0
- CMP R0, R10
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0A
- MOV R10, R0
-
- ; Register R11
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R11, R0
- CMP R0, R11
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R11, R0
- CMP R0, R11
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0B
- MOV R11, R0
-
- ; Register R12
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R12, R0
- CMP R0, R12
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R12, R0
- CMP R0, R12
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0C
- MOV R12, R0
- LDR R0, =_test_cpu_continue
-
- ; pattern verification (R0 is not tested)
- CMP R1, #0x01
- BNE _test_cpu_reg0_reg13_fail
- CMP R2, #0x02
- BNE _test_cpu_reg0_reg13_fail
- CMP R3, #0x03
- BNE _test_cpu_reg0_reg13_fail
- CMP R4, #0x04
- BNE _test_cpu_reg0_reg13_fail
- CMP R5, #0x05
- BNE _test_cpu_reg0_reg13_fail
- CMP R6, #0x06
- BNE _test_cpu_reg0_reg13_fail
- CMP R7, #0x07
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x08
- CMP R0, R8
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x09
- CMP R0, R9
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0A
- CMP R0, R10
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0B
- CMP R0, R11
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0C
- CMP R0, R12
- BNE _test_cpu_reg0_reg13_fail
-
- ; Process Stack pointer (banked Register R13)
- MRS R0, PSP ; Save process stack value
- LDR R1, =data0xAAAAAAA8 ; Test is different (PSP is word aligned, 2 LSB cleared)
- LDR R1, [R1]
- MSR PSP, R1 ; load process stack value
- MRS R2, PSP ; Get back process stack value
- CMP R2, R1 ; Verify value
- BNE _test_cpu_reg0_reg13_fail
- LDR R1, =data0x55555554 ; Test is different (PSP is word aligned, 2 LSB cleared)
- LDR R1, [R1]
- MSR PSP, R1 ; load process stack value
- MRS R2, PSP ; Get back process stack value
- CMP R2, R1 ; Verify value
- BNE _test_cpu_reg0_reg13_fail
- MSR PSP, R0 ; Restore process stack value
-
- ; Stack pointer (Register R13)
- MRS R0, MSP ; Save stack pointer value
- LDR R1, =data0xAAAAAAA8 ; Test is different (SP is word aligned, 2 LSB cleared)
- LDR R1, [R1]
- MSR MSP, R1 ; load SP value
- MRS R2, MSP ; Get back SP value
- CMP R2, R1 ; Verify value
- BNE _test_cpu_reg0_reg13_fail
- LDR R1, =data0x55555554
- LDR R1, [R1] ; load SP value
- MSR MSP, R1 ; Get back SP value
- MRS R2, MSP ; Verify value
- CMP R2, R1
- BNE _test_cpu_reg0_reg13_fail
- MSR MSP, R0 ; Restore stack pointer value
-
-_test_cpu_r14_sfr
- ; Link register R14
- MOV R1, LR
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
-
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
-
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
-
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
- MOV LR, R1
-
- ; PRIMASK register
- MRS R1, PRIMASK
- LDR R0, =data0x00000000
- LDR R0, [R0]
- MSR PRIMASK, R0
- MRS R2, PRIMASK
- MOVS R3, #1
- ANDS R2, R3
- CMP R2, #0
- BNE _test_cpu_r14_sfr_fail
-
- LDR R0, =data0x00000001
- LDR R0, [R0]
- MSR PRIMASK, R0
- MRS R2, PRIMASK
- MOVS R3, #1
- ANDS R2, R3
- CMP R2, #1
- BNE _test_cpu_r14_sfr_fail
- MSR PRIMASK, R1
- B _test_cpu_pass
-
-_test_cpu_r14_sfr_fail
- ; test fail, R0 will hold value 1
- MOVS R0, #0x1 ; STL_ERR
- B _test_exit
-
-_test_cpu_pass
- ; test pass, R0 will hold value 0
- MOVS R0, #0x0 ; STL_OK
- B _test_exit
-
-_test_exit
- POP {R4-R7} ; Restore registers
- BX LR
-
- END
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_full_ram_startup.s b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_full_ram_startup.s
deleted file mode 100644
index 71915b20d0..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_full_ram_startup.s
+++ /dev/null
@@ -1,186 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; * opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/* Test for IAR */
-;/* Version V1.0 */
-;/* Date 2022-03-31 */
-;/****************************************************************************/
- SECTION constdata:CONST(2)
-data0x00000000 DCD 0x00000000
-data0xFFFFFFFF DCD 0xFFFFFFFF
-
- ; Exported function
- EXPORT STL_FullRamTestStartup
-
-;*******************************************************************************
-; Function Name : STL_FullRamTestStartup
-; Description : Full RAM test at start-up
-; Input : R0 .. RAM begin address
-; R1 .. RAM end address
-; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING : all registers destroyed when exiting this function (including
-; preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
- THUMB
- SECTION .text:CODE(2)
-STL_FullRamTestStartup:
- MOVS R4, #0x0 ; STL_OK:Test success status by default
-
- LDR R2, =data0x00000000 ; Prepares background pattern
- LDR R2, [R2]
- LDR R3, =data0xFFFFFFFF ; Prepares inverted background pattern
- LDR R3, [R3]
-
- ; *** Step 1 ***
- ; Write background pattern with addresses increasing
- MOVS R5, R0
-_step1_loop:
- CMP R5, R1
- BHI _step_2
- STR R2, [R5, #+0]
- ADDS R5, R5, #+4
- B _step1_loop
-
- ; *** Step 2 ***
- ; Verify background and write inverted background with addresses increasing
-_step_2:
- MOVS R5, R0
-_step_2_loop:
- CMP R5, R1
- BHI _step_3
- LDR R6, [R5, #+0]
- CMP R6, R2
- BNE _full_ram1_test_fail
- STR R3, [R5, #+0]
- LDR R6, [R5, #+4]
- CMP R6, R2
- BNE _full_ram1_test_fail
- STR R3, [R5, #+4]
-
- LDR R6, [R5, #+8]
- CMP R6, R2
- BNE _full_ram1_test_fail
- STR R3, [R5, #+8]
- LDR R6, [R5, #+12]
- CMP R6, R2
- BNE _full_ram1_test_fail
- STR R3, [R5, #+12]
-
- ADDS R5, R5, #+16
- B _step_2_loop
-
- ; *** Step 3 ***
- ; Verify inverted background and write background with addresses increasing
-_step_3:
- MOVS R5, R0
-_step_3_loop:
- CMP R5, R1
- BHI _step_4
- LDR R6, [R5, #+0]
- CMP R6, R3
- BNE _full_ram1_test_fail
- STR R2, [R5, #+0]
- LDR R6, [R5, #+4]
- CMP R6, R3
- BNE _full_ram1_test_fail
- STR R2, [R5, #+4]
-
- LDR R6, [R5, #+8]
- CMP R6, R3
- BNE _full_ram1_test_fail
- STR R2, [R5, #+8]
- LDR R6, [R5, #+12]
- CMP R6, R3
- BNE _full_ram1_test_fail
- STR R2, [R5, #+12]
-
- ADDS R5, R5, #+16
- B _step_3_loop
-
- ; *** Step 4 ***
- ; Verify background and write inverted background with addresses decreasing
-_step_4:
- MOVS R5, R1
- SUBS R5, R5, #+15
-_step_4_loop:
- CMP R5, R0
- BLO _step_5
-
- LDR R6, [R5, #+12]
- CMP R6, R2
- BNE _full_ram1_test_fail
- STR R3, [R5, #+12]
- LDR R6, [R5, #+8]
- CMP R6, R2
- BNE _full_ram1_test_fail
- STR R3, [R5, #+8]
-
- LDR R6, [R5, #+4]
- CMP R6, R2
- BNE _full_ram1_test_fail
- STR R3, [R5, #+4]
- LDR R6, [R5, #+0]
- CMP R6, R2
- BNE _full_ram1_test_fail
- STR R3, [R5, #+0]
-
- SUBS R5, R5, #+16
- B _step_4_loop
-
- ; *** Step 5 ***
- ; Verify inverted background and write background with addresses decreasing
-_step_5:
- MOVS R5, R1
- SUBS R5, R5, #+15
-_step_5_loop:
- CMP R5, R0
- BLO _step_6
-
- LDR R6, [R5, #+12]
- CMP R6, R3
- BNE _full_ram1_test_fail
- STR R2, [R5, #+12]
- LDR R6, [R5, #+8]
- CMP R6, R3
- BNE _full_ram1_test_fail
- STR R2, [R5, #+8]
-
- LDR R6, [R5, #+4]
- CMP R6, R3
- BNE _full_ram1_test_fail
- STR R2, [R5, #+4]
- LDR R6, [R5, #+0]
- CMP R6, R3
- BNE _full_ram1_test_fail
- STR R2, [R5, #+0]
- SUBS R5, R5, #+16
- B _step_5_loop
-
- ; *** Step 6 ***
- ; Verify background with addresses increasing
-_step_6:
- MOVS R5, R0
-_step_6_loop:
- CMP R5, R1
- BHI _full_ram1_test_pass
- LDR R6, [R5, #+0]
- CMP R6, R2
- BNE _full_ram1_test_fail
- ADDS R5, R5, #+4
- B _step_6_loop
-
-_full_ram1_test_fail:
- MOVS R4, #1 ; STL_ERR
-
-_full_ram1_test_pass:
- MOVS R0, R4
- BX LR ; return to the caller
-
- END
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_pc.s b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_pc.s
deleted file mode 100644
index 4f180a1d9a..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_pc.s
+++ /dev/null
@@ -1,148 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; * opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/* Test for IAR */
-;/* Date Author Notes */
-;/* 2022-03-31 CDT First version */
-;/* 2023-05-31 CDT Typo: subrouitne -> subroutine */
-;/****************************************************************************/
-
- ; Exported function
- EXPORT STL_PcTest
-
-;*******************************************************************************
-; Function Name : STL_PcTest
-; Description : Test PC
-; Input : None.
-; Output : Perform routine when detect failure at set of self test cases
-; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING : all registers destroyed when exiting this function (including
-; preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
-
- SECTION .text:CODE(2)
- THUMB
-STL_PcTest
- PUSH {R4-R7} ; Save registers
- MOVS R0, #0
- MOVS R1, #0 ; clr R0,R1
- MOV R3, LR
-
-_subroutine_1
- LDR R0, =_return_pc_test_addr_1
- BL _return_pc_test_addr_1
- CMP R0, R1 ; verify return address?
- BEQ _subroutine_2
- B _pc_test_fail
-
-_subroutine_2
- LDR R0, =_return_pc_test_addr_2
- BL _return_pc_test_addr_2
- CMP R0, R1 ; verify return address?
- BEQ _subroutine_3
- B _pc_test_fail
-
-_subroutine_3
- LDR R0, =_return_pc_test_addr_3
- BL _return_pc_test_addr_3
- CMP R0, R1 ; verify return address?
- BEQ _subroutine_4
- B _pc_test_fail
-
-_subroutine_4
- LDR R0, =_return_pc_test_addr_4
- BL _return_pc_test_addr_4
- CMP R0, R1 ; verify return address?
- BEQ _subroutine_5
- B _pc_test_fail
-
-_subroutine_5
- LDR R0, =_return_pc_test_addr_5
- BL _return_pc_test_addr_5
- CMP R0, R1 ; verify return address?
- BEQ _subroutine_6
- B _pc_test_fail
-
-_subroutine_6
- LDR R0, =_return_pc_test_addr_6
- BL _return_pc_test_addr_6
- CMP R0, R1 ; verify return address?
- BEQ _subroutine_7
- B _pc_test_fail
-
-_subroutine_7
- LDR R0, =_return_pc_test_addr_7
- BL _return_pc_test_addr_7
- CMP R0, R1 ; verify return address?
- BEQ _subroutine_8
- B _pc_test_fail
-
-_subroutine_8
- LDR R0, =_return_pc_test_addr_8
- BL _return_pc_test_addr_8
- CMP R0, R1 ; verify return address?
- BEQ _pc_test_pass
- B _pc_test_fail
-
-_pc_test_fail
- ; when test fail, R0 will hold value 1
- MOVS R0, #0x1 ; STL_ERR
- B _pc_test_exit
-
-_pc_test_pass
- ; when test pass, R0 will hold value 0
- MOVS R0, #0x0 ; STL_OK
- B _pc_test_exit
-
-_pc_test_exit:
- POP {R4-R7} ; Restore registers
- BX R3 ; return
-
- SECTION .pctestaddr1:CODE(2)
-_return_pc_test_addr_1
- LDR R1, =_return_pc_test_addr_1 ; store subroutine address in R1
- BX LR
-
- SECTION .pctestaddr2:CODE(2)
-_return_pc_test_addr_2
- LDR R1, =_return_pc_test_addr_2 ; store subroutine address in R1
- BX LR
-
- SECTION .pctestaddr3:CODE(2)
-_return_pc_test_addr_3
- LDR R1, =_return_pc_test_addr_3 ; store subroutine address in R1
- BX LR
-
- SECTION .pctestaddr4:CODE(2)
-_return_pc_test_addr_4
- LDR R1, =_return_pc_test_addr_4 ; store subroutine address in R1
- BX LR
-
- SECTION .pctestaddr5:CODE(2)
-_return_pc_test_addr_5
- LDR R1, =_return_pc_test_addr_5 ; store subroutine address in R1
- BX LR
-
- SECTION .pctestaddr6:CODE(2)
-_return_pc_test_addr_6
- LDR R1, =_return_pc_test_addr_6 ; store subroutine address in R1
- BX LR
-
- SECTION .pctestaddr7:CODE(2)
-_return_pc_test_addr_7
- LDR R1, =_return_pc_test_addr_7 ; store subroutine address in R1
- BX LR
-
- SECTION .pctestaddr8:CODE(2)
-_return_pc_test_addr_8
- LDR R1, =_return_pc_test_addr_8 ; store subroutine address in R1
- BX LR
-
- END
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_cm0_startup.s b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_cm0_startup.s
deleted file mode 100644
index 13bdd9993b..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_cm0_startup.s
+++ /dev/null
@@ -1,378 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; * opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/* Test for MDK */
-;/* Version V1.0 */
-;/* Date 2022-09-14 */
-;/****************************************************************************/
-
- THUMB
- REQUIRE8
- PRESERVE8
-
- AREA |.text|, CODE, READONLY, ALIGN=2
-
-data0xAAAAAAAA DCD 0xAAAAAAAA
-data0x55555555 DCD 0x55555555
-data0x80000000 DCD 0x80000000
-data0xAAAAAAA8 DCD 0xAAAAAAA8
-data0x55555554 DCD 0x55555554
-data0x00000000 DCD 0x00000000
-data0x00000001 DCD 0x00000001
-data0x50000000 DCD 0x50000000
-data0xA0000000 DCD 0xA0000000
-
-;*******************************************************************************
-; Function Name : STL_CpuTestStartup
-; Description : Test CPU at start-up
-; Input : None.
-; Output : Perform routine when detect failure at set of self test cases
-; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING : all registers destroyed when exiting this function (including
-; preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
-STL_CpuTestStartup PROC
- EXPORT STL_CpuTestStartup
-
- PUSH {R4-R7} ; Save registers
-
-_test_cpu_reg0_reg8
- MOVS R0, #0x00
- UXTB R0, R0
- ADDS R0, #0 ; Set Z(ero) Flag
- BNE _test_cpu_reg0_reg13_fail ; Fails if Z clear
- BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
- SUBS R0, #1 ; Set N(egative) Flag
- BPL _test_cpu_reg0_reg13_fail ; Fails if N clear
- ADDS R0, #2 ; Set C(arry) Flag and do not set Z
- BCC _test_cpu_reg0_reg13_fail ; Fails if C clear
- BEQ _test_cpu_reg0_reg13_fail ; Fails if Z is set
- BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
-
- LDR R0, =data0x80000000 ; Prepares Overflow test
- LDR R0, [R0]
- ADDS R0, R0, R0 ; Set V(overflow) Flag
- BVC _test_cpu_reg0_reg13_fail ; Fails if V clear
-
- ; Register R1
- LDR R0, =data0xAAAAAAAA
- LDR R1, [R0]
- LDR R0, [R0]
- CMP R0, R1
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R1, [R0]
- LDR R0, [R0]
- CMP R0, R1
- BNE _test_cpu_reg0_reg13_fail
- MOVS R1, #0x1
-
- ; Register R2
- LDR R0, =data0xAAAAAAAA
- LDR R2, [R0]
- LDR R0, [R0]
- CMP R0, R2
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R2, [R0]
- LDR R0, [R0]
- CMP R0, R2
- BNE _test_cpu_reg0_reg13_fail
- MOVS R2, #0x2
-
- ; Register R3
- LDR R0, =data0xAAAAAAAA
- LDR R3, [R0]
- LDR R0, [R0]
- CMP R0, R3
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R3, [R0]
- LDR R0, [R0]
- CMP R0, R3
- BNE _test_cpu_reg0_reg13_fail
- MOVS R3, #0x3
-
- ; Register R4
- LDR R0, =data0xAAAAAAAA
- LDR R4, [R0]
- LDR R0, [R0]
- CMP R0, R4
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R4, [R0]
- LDR R0, [R0]
- CMP R0, R4
- BNE _test_cpu_reg0_reg13_fail
- MOVS R4, #0x4
-
- ; Register R5
- LDR R0, =data0xAAAAAAAA
- LDR R5, [R0]
- LDR R0, [R0]
- CMP R0, R5
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R5, [R0]
- LDR R0, [R0]
- CMP R0, R5
- BNE _test_cpu_reg0_reg13_fail
- MOVS R5, #0x5
-
- ; Register R6
- LDR R0, =data0xAAAAAAAA
- LDR R6, [R0]
- LDR R0, [R0]
- CMP R0, R6
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R6, [R0]
- LDR R0, [R0]
- CMP R0, R6
- BNE _test_cpu_reg0_reg13_fail
- MOVS R6, #0x6
-
- ; Register R7
- LDR R0, =data0xAAAAAAAA
- LDR R7, [R0]
- LDR R0, [R0]
- CMP R0, R7
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R7, [R0]
- LDR R0, [R0]
- CMP R0, R7
- BNE _test_cpu_reg0_reg13_fail
- MOVS R7, #0x7
-
- ; Register R8
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R8, R0
- CMP R0, R8
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R8, R0
- CMP R0, R8
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x08
- MOV R8, R0
-
- BAL _test_cpu_continue
-
-_test_cpu_reg0_reg13_fail
- ; test fail, R0 will hold value 1
- MOVS R0, #0x1 ; STL_ERR
- B _test_exit
-
-_test_cpu_continue
- ; Register R9
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R9, R0
- CMP R0, R9
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R9, R0
- CMP R0, R9
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x09
- MOV R9, R0
-
- ; Register R10
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R10, R0
- CMP R0, R10
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R10, R0
- CMP R0, R10
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0A
- MOV R10, R0
-
- ; Register R11
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R11, R0
- CMP R0, R11
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R11, R0
- CMP R0, R11
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0B
- MOV R11, R0
-
- ; Register R12
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R12, R0
- CMP R0, R12
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R12, R0
- CMP R0, R12
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0C
- MOV R12, R0
- LDR R0, =_test_cpu_continue
-
- ; pattern verification (R0 is not tested)
- CMP R1, #0x01
- BNE _test_cpu_reg0_reg13_fail
- CMP R2, #0x02
- BNE _test_cpu_reg0_reg13_fail
- CMP R3, #0x03
- BNE _test_cpu_reg0_reg13_fail
- CMP R4, #0x04
- BNE _test_cpu_reg0_reg13_fail
- CMP R5, #0x05
- BNE _test_cpu_reg0_reg13_fail
- CMP R6, #0x06
- BNE _test_cpu_reg0_reg13_fail
- CMP R7, #0x07
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x08
- CMP R0, R8
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x09
- CMP R0, R9
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0A
- CMP R0, R10
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0B
- CMP R0, R11
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0C
- CMP R0, R12
- BNE _test_cpu_reg0_reg13_fail
-
- ; Process Stack pointer (banked Register R13)
- MRS R0, PSP ; Save process stack value
- LDR R1, =data0xAAAAAAA8 ; Test is different (PSP is word aligned, 2 LSB cleared)
- LDR R1, [R1]
- MSR PSP, R1 ; load process stack value
- MRS R2, PSP ; Get back process stack value
- CMP R2, R1 ; Verify value
- BNE _test_cpu_reg0_reg13_fail
- LDR R1, =data0x55555554 ; Test is different (PSP is word aligned, 2 LSB cleared)
- LDR R1, [R1]
- MSR PSP, R1 ; load process stack value
- MRS R2, PSP ; Get back process stack value
- CMP R2, R1 ; Verify value
- BNE _test_cpu_reg0_reg13_fail
- MSR PSP, R0 ; Restore process stack value
-
- ; Stack pointer (Register R13)
- MRS R0, MSP ; Save stack pointer value
- LDR R1, =data0xAAAAAAA8 ; Test is different (SP is word aligned, 2 LSB cleared)
- LDR R1, [R1]
- MSR MSP, R1 ; load SP value
- MRS R2, MSP ; Get back SP value
- CMP R2, R1 ; Verify value
- BNE _test_cpu_reg0_reg13_fail
- LDR R1, =data0x55555554
- LDR R1, [R1] ; load SP value
- MSR MSP, R1 ; Get back SP value
- MRS R2, MSP ; Verify value
- CMP R2, R1
- BNE _test_cpu_reg0_reg13_fail
- MSR MSP, R0 ; Restore stack pointer value
-
-_test_cpu_r14_sfr
- ; Link register R14
- MOV R1, LR
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
-
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
-
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
-
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
- MOV LR, R1
-
- ; APSR
- MRS R0, APSR
- LDR R1, =data0x50000000
- LDR R1,[R1]
- MSR APSR,R1
- MRS R2, APSR
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
-
- LDR R1, =data0xA0000000
- LDR R1,[R1]
- MSR APSR,R1
- MRS R2, APSR
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
- MSR APSR,R0
-
- ; PRIMASK register
- MRS R0, PRIMASK
- LDR R1, =data0x00000000
- LDR R1, [R1]
- MSR PRIMASK, R1
- MRS R2, PRIMASK
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
-
- LDR R1, =data0x00000001
- LDR R1, [R1]
- MSR PRIMASK, R1
- MRS R2, PRIMASK
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
- MSR PRIMASK, R0
- B _test_cpu_pass
-
-_test_cpu_r14_sfr_fail
- ; test fail, R0 will hold value 1
- MOVS R0, #0x1 ; STL_ERR
- B _test_exit
-
-_test_cpu_pass
- ; test pass, R0 will hold value 0
- MOVS R0, #0x0 ; STL_OK
- B _test_exit
-
-_test_exit
- POP {R4-R7} ; Restore registers
- BX LR
-
- ENDP
-
- ALIGN
-
- END
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_cm4_startup.s b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_cm4_startup.s
deleted file mode 100644
index 36bb5faf06..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_cm4_startup.s
+++ /dev/null
@@ -1,426 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; * opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/* Test for MDK */
-;/* Date Author Notes */
-;/* 2022-09-14 CDT First version */
-;/* 2022-12-20 CDT Load data to R0 before USAT */
-;/* 2023-05-31 CDT Typo: Veriry -> Verify */
-;/****************************************************************************/
-
- THUMB
- REQUIRE8
- PRESERVE8
-
- AREA |.text|, CODE, READONLY, ALIGN=2
-
-data0xAAAAAAAA DCD 0xAAAAAAAA
-data0x55555555 DCD 0x55555555
-data0x80000000 DCD 0x80000000
-data0xAAAAAAA8 DCD 0xAAAAAAA8
-data0x55555554 DCD 0x55555554
-data0x00000000 DCD 0x00000000
-data0x00000001 DCD 0x00000001
-data0x50000000 DCD 0x50000000
-data0xA8000000 DCD 0xA8000000
-data0x00000050 DCD 0x00000050
-data0x000000A0 DCD 0x000000A0
-data0xFFFFFFFF DCD 0xFFFFFFFF
-
-;*******************************************************************************
-; Function Name : STL_CpuTestStartup
-; Description : Test CPU at start-up
-; Input : None.
-; Output : Perform routine when detect failure at set of self test cases
-; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING : all registers destroyed when exiting this function (including
-; preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
-STL_CpuTestStartup PROC
- EXPORT STL_CpuTestStartup
-
- PUSH {R4-R7} ; Save registers
-
-_test_cpu_reg0_reg8
- MOVS R0, #0x00
- UXTB R0, R0
- ADDS R0, #0 ; Set Z(ero) Flag
- BNE _test_cpu_reg0_reg13_fail ; Fails if Z clear
- BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
- SUBS R0, #1 ; Set N(egative) Flag
- BPL _test_cpu_reg0_reg13_fail ; Fails if N clear
- ADDS R0, #2 ; Set C(arry) Flag and do not set Z
- BCC _test_cpu_reg0_reg13_fail ; Fails if C clear
- BEQ _test_cpu_reg0_reg13_fail ; Fails if Z is set
- BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
-
- LDR R0, =data0x80000000 ; Prepares Overflow test
- LDR R0, [R0]
- ADDS R0, R0, R0 ; Set V(overflow) Flag
- BVC _test_cpu_reg0_reg13_fail ; Fails if V clear
-
- MOV R0, #0
- MSR APSR, R0
- LDR R0, =data0xFFFFFFFF ; Prepares Saturation test
- LDR R0, [R0]
- USAT R1, #10, R0 ; Set Q(saturation) flag
- MRS R0, APSR ; Get APSR status register
- CMP R0, #0x08000000 ; Verify Q=1
- BNE _test_cpu_reg0_reg13_fail ; Fails if Q is set
-
- ; Register R1
- LDR R0, =data0xAAAAAAAA
- LDR R1, [R0]
- LDR R0, [R0]
- CMP R0, R1
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R1, [R0]
- LDR R0, [R0]
- CMP R0, R1
- BNE _test_cpu_reg0_reg13_fail
- MOVS R1, #0x1
-
- ; Register R2
- LDR R0, =data0xAAAAAAAA
- LDR R2, [R0]
- LDR R0, [R0]
- CMP R0, R2
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R2, [R0]
- LDR R0, [R0]
- CMP R0, R2
- BNE _test_cpu_reg0_reg13_fail
- MOVS R2, #0x2
-
- ; Register R3
- LDR R0, =data0xAAAAAAAA
- LDR R3, [R0]
- LDR R0, [R0]
- CMP R0, R3
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R3, [R0]
- LDR R0, [R0]
- CMP R0, R3
- BNE _test_cpu_reg0_reg13_fail
- MOVS R3, #0x3
-
- ; Register R4
- LDR R0, =data0xAAAAAAAA
- LDR R4, [R0]
- LDR R0, [R0]
- CMP R0, R4
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R4, [R0]
- LDR R0, [R0]
- CMP R0, R4
- BNE _test_cpu_reg0_reg13_fail
- MOVS R4, #0x4
-
- ; Register R5
- LDR R0, =data0xAAAAAAAA
- LDR R5, [R0]
- LDR R0, [R0]
- CMP R0, R5
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R5, [R0]
- LDR R0, [R0]
- CMP R0, R5
- BNE _test_cpu_reg0_reg13_fail
- MOVS R5, #0x5
-
- ; Register R6
- LDR R0, =data0xAAAAAAAA
- LDR R6, [R0]
- LDR R0, [R0]
- CMP R0, R6
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R6, [R0]
- LDR R0, [R0]
- CMP R0, R6
- BNE _test_cpu_reg0_reg13_fail
- MOVS R6, #0x6
-
- ; Register R7
- LDR R0, =data0xAAAAAAAA
- LDR R7, [R0]
- LDR R0, [R0]
- CMP R0, R7
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R7, [R0]
- LDR R0, [R0]
- CMP R0, R7
- BNE _test_cpu_reg0_reg13_fail
- MOVS R7, #0x7
-
- ; Register R8
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R8, R0
- CMP R0, R8
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R8, R0
- CMP R0, R8
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x08
- MOV R8, R0
-
- BAL _test_cpu_continue
-
-_test_cpu_reg0_reg13_fail
- ; test fail, R0 will hold value 1
- MOVS R0, #0x1 ; STL_ERR
- B _test_exit
-
-_test_cpu_continue
- ; Register R9
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R9, R0
- CMP R0, R9
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R9, R0
- CMP R0, R9
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x09
- MOV R9, R0
-
- ; Register R10
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R10, R0
- CMP R0, R10
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R10, R0
- CMP R0, R10
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0A
- MOV R10, R0
-
- ; Register R11
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R11, R0
- CMP R0, R11
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R11, R0
- CMP R0, R11
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0B
- MOV R11, R0
-
- ; Register R12
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R12, R0
- CMP R0, R12
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R12, R0
- CMP R0, R12
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0C
- MOV R12, R0
- LDR R0, =_test_cpu_continue
-
- ; pattern verification (R0 is not tested)
- CMP R1, #0x01
- BNE _test_cpu_reg0_reg13_fail
- CMP R2, #0x02
- BNE _test_cpu_reg0_reg13_fail
- CMP R3, #0x03
- BNE _test_cpu_reg0_reg13_fail
- CMP R4, #0x04
- BNE _test_cpu_reg0_reg13_fail
- CMP R5, #0x05
- BNE _test_cpu_reg0_reg13_fail
- CMP R6, #0x06
- BNE _test_cpu_reg0_reg13_fail
- CMP R7, #0x07
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x08
- CMP R0, R8
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x09
- CMP R0, R9
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0A
- CMP R0, R10
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0B
- CMP R0, R11
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0C
- CMP R0, R12
- BNE _test_cpu_reg0_reg13_fail
-
- ; Process Stack pointer (banked Register R13)
- MRS R0, PSP ; Save process stack value
- LDR R1, =data0xAAAAAAA8 ; Test is different (PSP is word aligned, 2 LSB cleared)
- LDR R1, [R1]
- MSR PSP, R1 ; load process stack value
- MRS R2, PSP ; Get back process stack value
- CMP R2, R1 ; Verify value
- BNE _test_cpu_reg0_reg13_fail
- LDR R1, =data0x55555554 ; Test is different (PSP is word aligned, 2 LSB cleared)
- LDR R1, [R1]
- MSR PSP, R1 ; load process stack value
- MRS R2, PSP ; Get back process stack value
- CMP R2, R1 ; Verify value
- BNE _test_cpu_reg0_reg13_fail
- MSR PSP, R0 ; Restore process stack value
-
- ; Stack pointer (Register R13)
- MRS R0, MSP ; Save stack pointer value
- LDR R1, =data0xAAAAAAA8 ; Test is different (SP is word aligned, 2 LSB cleared)
- LDR R1, [R1]
- MSR MSP, R1 ; load SP value
- MRS R2, MSP ; Get back SP value
- CMP R2, R1 ; Verify value
- BNE _test_cpu_reg0_reg13_fail
- LDR R1, =data0x55555554
- LDR R1, [R1] ; load SP value
- MSR MSP, R1 ; Get back SP value
- MRS R2, MSP ; Verify value
- CMP R2, R1
- BNE _test_cpu_reg0_reg13_fail
- MSR MSP, R0 ; Restore stack pointer value
-
-_test_cpu_r14_sfr
- ; Link register R14
- MOV R1, LR
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
-
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
-
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
-
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
- MOV LR, R1
-
- ; APSR
- MRS R0, APSR
- LDR R1, =data0x50000000
- LDR R1,[R1]
- MSR APSR,R1
- MRS R2, APSR
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
-
- LDR R1, =data0xA8000000
- LDR R1,[R1]
- MSR APSR,R1
- MRS R2, APSR
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
- MSR APSR,R0
-
- ; PRIMASK register
- MRS R0, PRIMASK
- LDR R1, =data0x00000000
- LDR R1, [R1]
- MSR PRIMASK, R1
- MRS R2, PRIMASK
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
-
- LDR R1, =data0x00000001
- LDR R1, [R1]
- MSR PRIMASK, R1
- MRS R2, PRIMASK
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
- MSR PRIMASK, R0
-
- ; FAULTMASK register
- MRS R0, FAULTMASK
- LDR R1, =data0x00000000
- LDR R1, [R1]
- MSR FAULTMASK, R1
- MRS R2, FAULTMASK
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
-
- LDR R1, =data0x00000001
- LDR R1, [R1]
- MSR FAULTMASK, R1
- MRS R2, FAULTMASK
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
- MSR FAULTMASK, R0
-
- ; BASEPRI register
- MRS R0, BASEPRI
- LDR R1, =data0x000000A0
- LDR R1, [R1]
- MSR BASEPRI, R1
- MRS R2, BASEPRI
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
-
- LDR R1, =data0x00000050
- LDR R1, [R1]
- MSR BASEPRI, R1
- MRS R2, BASEPRI
- CMP R1, R2
- BNE _test_cpu_r14_sfr_fail
- MSR BASEPRI, R0
- B _test_cpu_pass
-
-_test_cpu_r14_sfr_fail
- ; test fail, R0 will hold value 1
- MOVS R0, #0x1 ; STL_ERR
- B _test_exit
-
-_test_cpu_pass
- ; test pass, R0 will hold value 0
- MOVS R0, #0x0 ; STL_OK
- B _test_exit
-
-_test_exit
- POP {R4-R7} ; Restore registers
- BX LR
-
- ENDP
-
- ALIGN
-
- END
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_runtime.s b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_runtime.s
deleted file mode 100644
index 9b92ae536d..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_runtime.s
+++ /dev/null
@@ -1,251 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; * opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/* Test for MDK */
-;/* Version V1.0 */
-;/* Date 2022-03-31 */
-;/****************************************************************************/
-
- THUMB
- REQUIRE8
- PRESERVE8
-
- AREA |.text|, CODE, READONLY, ALIGN=2
-
-data0xAAAAAAAA DCD 0xAAAAAAAA
-data0x55555555 DCD 0x55555555
-
-;*******************************************************************************
-; Function Name : STL_CpuTestRuntime
-; Description : Test CPU at run-time
-; Input : None.
-; Output : Perform routine when detect failure at set of self test cases
-; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING : all registers destroyed when exiting this function (including
-; preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
-STL_CpuTestRuntime PROC
- EXPORT STL_CpuTestRuntime
-
- PUSH {R4-R7} ; Save registers
-
- ; Register R1
- LDR R0, =data0xAAAAAAAA
- LDR R1, [R0]
- LDR R0, [R0]
- CMP R0, R1
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R1, [R0]
- LDR R0, [R0]
- CMP R0, R1
- BNE _test_cpu_fail
- MOVS R1, #0x1
-
- ; Register R2
- LDR R0, =data0xAAAAAAAA
- LDR R2, [R0]
- LDR R0, [R0]
- CMP R0, R2
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R2, [R0]
- LDR R0, [R0]
- CMP R0, R2
- BNE _test_cpu_fail
- MOVS R2, #0x2
-
- ; Register R3
- LDR R0, =data0xAAAAAAAA
- LDR R3, [R0]
- LDR R0, [R0]
- CMP R0, R3
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R3, [R0]
- LDR R0, [R0]
- CMP R0, R3
- BNE _test_cpu_fail
- MOVS R3, #0x3
-
- ; Register R4
- LDR R0, =data0xAAAAAAAA
- LDR R4, [R0]
- LDR R0, [R0]
- CMP R0, R4
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R4, [R0]
- LDR R0, [R0]
- CMP R0, R4
- BNE _test_cpu_fail
- MOVS R4, #0x4
-
- ; Register R5
- LDR R0, =data0xAAAAAAAA
- LDR R5, [R0]
- LDR R0, [R0]
- CMP R0, R5
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R5, [R0]
- LDR R0, [R0]
- CMP R0, R5
- BNE _test_cpu_fail
- MOVS R5, #0x5
-
- ; Register R6
- LDR R0, =data0xAAAAAAAA
- LDR R6, [R0]
- LDR R0, [R0]
- CMP R0, R6
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R6, [R0]
- LDR R0, [R0]
- CMP R0, R6
- BNE _test_cpu_fail
- MOVS R6, #0x6
-
- ; Register R7
- LDR R0, =data0xAAAAAAAA
- LDR R7, [R0]
- LDR R0, [R0]
- CMP R0, R7
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R7, [R0]
- LDR R0, [R0]
- CMP R0, R7
- BNE _test_cpu_fail
- MOVS R7, #0x7
-
- ; Register R8
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R8, R0
- CMP R0, R8
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R8, R0
- CMP R0, R8
- BNE _test_cpu_fail
- MOVS R0, #0x08
- MOV R8, R0
-
- BAL _test_cpu_continue
-
-_test_cpu_fail
- ; test fail, R0 will hold value 1
- MOVS R0, #0x1 ; STL_ERR
- B _test_exit
-
-_test_cpu_continue
- ; Register R9
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R9, R0
- CMP R0, R9
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R9, R0
- CMP R0, R9
- BNE _test_cpu_fail
- MOVS R0, #0x09
- MOV R9, R0
-
- ; Register R10
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R10, R0
- CMP R0, R10
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R10, R0
- CMP R0, R10
- BNE _test_cpu_fail
- MOVS R0, #0x0A
- MOV R10, R0
-
- ; Register R11
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R11, R0
- CMP R0, R11
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R11, R0
- CMP R0, R11
- BNE _test_cpu_fail
- MOVS R0, #0x0B
- MOV R11, R0
-
- ; Register R12
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R12, R0
- CMP R0, R12
- BNE _test_cpu_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R12, R0
- CMP R0, R12
- BNE _test_cpu_fail
- MOVS R0, #0x0C
- MOV R12, R0
- LDR R0, =_test_cpu_continue
-
- ; pattern verification (R0 is not tested)
- CMP R1, #0x01
- BNE _test_cpu_fail
- CMP R2, #0x02
- BNE _test_cpu_fail
- CMP R3, #0x03
- BNE _test_cpu_fail
- CMP R4, #0x04
- BNE _test_cpu_fail
- CMP R5, #0x05
- BNE _test_cpu_fail
- CMP R6, #0x06
- BNE _test_cpu_fail
- CMP R7, #0x07
- BNE _test_cpu_fail
- MOVS R0, #0x08
- CMP R0, R8
- BNE _test_cpu_fail
- MOVS R0, #0x09
- CMP R0, R9
- BNE _test_cpu_fail
- MOVS R0, #0x0A
- CMP R0, R10
- BNE _test_cpu_fail
- MOVS R0, #0x0B
- CMP R0, R11
- BNE _test_cpu_fail
- MOVS R0, #0x0C
- CMP R0, R12
- BNE _test_cpu_fail
-
- ; Link register R14
- ; test pass, R0 will hold value 0
- MOVS R0, #0x0 ; STL_OK
-_test_exit
- POP {R4-R7} ; Restore registers
- BX LR ; return
-
- ENDP
-
- ALIGN
-
- END
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_startup.s b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_startup.s
deleted file mode 100644
index cf779fb02b..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_startup.s
+++ /dev/null
@@ -1,363 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; * opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/* Test for MDK */
-;/* Version V1.0 */
-;/* Date 2022-03-31 */
-;/****************************************************************************/
-
- THUMB
- REQUIRE8
- PRESERVE8
-
- AREA |.text|, CODE, READONLY, ALIGN=2
-
-data0xAAAAAAAA DCD 0xAAAAAAAA
-data0x55555555 DCD 0x55555555
-data0x80000000 DCD 0x80000000
-data0xAAAAAAA8 DCD 0xAAAAAAA8
-data0x55555554 DCD 0x55555554
-data0x00000000 DCD 0x00000000
-data0x00000001 DCD 0x00000001
-
-;*******************************************************************************
-; Function Name : STL_CpuTestStartup
-; Description : Test CPU at start-up
-; Input : None.
-; Output : Perform routine when detect failure at set of self test cases
-; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING : all registers destroyed when exiting this function (including
-; preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
-STL_CpuTestStartup PROC
- EXPORT STL_CpuTestStartup
-
- PUSH {R4-R7} ; Save registers
-
-_test_cpu_reg0_reg8
- MOVS R0, #0x00
- UXTB R0, R0
- ADDS R0, #0 ; Set Z(ero) Flag
- BNE _test_cpu_reg0_reg13_fail ; Fails if Z clear
- BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
- SUBS R0, #1 ; Set N(egative) Flag
- BPL _test_cpu_reg0_reg13_fail ; Fails if N clear
- ADDS R0, #2 ; Set C(arry) Flag and do not set Z
- BCC _test_cpu_reg0_reg13_fail ; Fails if C clear
- BEQ _test_cpu_reg0_reg13_fail ; Fails if Z is set
- BMI _test_cpu_reg0_reg13_fail ; Fails if N is set
-
- LDR R0, =data0x80000000 ; Prepares Overflow test
- LDR R0, [R0]
- ADDS R0, R0, R0 ; Set V(overflow) Flag
- BVC _test_cpu_reg0_reg13_fail ; Fails if V clear
-
- ; Register R1
- LDR R0, =data0xAAAAAAAA
- LDR R1, [R0]
- LDR R0, [R0]
- CMP R0, R1
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R1, [R0]
- LDR R0, [R0]
- CMP R0, R1
- BNE _test_cpu_reg0_reg13_fail
- MOVS R1, #0x1
-
- ; Register R2
- LDR R0, =data0xAAAAAAAA
- LDR R2, [R0]
- LDR R0, [R0]
- CMP R0, R2
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R2, [R0]
- LDR R0, [R0]
- CMP R0, R2
- BNE _test_cpu_reg0_reg13_fail
- MOVS R2, #0x2
-
- ; Register R3
- LDR R0, =data0xAAAAAAAA
- LDR R3, [R0]
- LDR R0, [R0]
- CMP R0, R3
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R3, [R0]
- LDR R0, [R0]
- CMP R0, R3
- BNE _test_cpu_reg0_reg13_fail
- MOVS R3, #0x3
-
- ; Register R4
- LDR R0, =data0xAAAAAAAA
- LDR R4, [R0]
- LDR R0, [R0]
- CMP R0, R4
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R4, [R0]
- LDR R0, [R0]
- CMP R0, R4
- BNE _test_cpu_reg0_reg13_fail
- MOVS R4, #0x4
-
- ; Register R5
- LDR R0, =data0xAAAAAAAA
- LDR R5, [R0]
- LDR R0, [R0]
- CMP R0, R5
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R5, [R0]
- LDR R0, [R0]
- CMP R0, R5
- BNE _test_cpu_reg0_reg13_fail
- MOVS R5, #0x5
-
- ; Register R6
- LDR R0, =data0xAAAAAAAA
- LDR R6, [R0]
- LDR R0, [R0]
- CMP R0, R6
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R6, [R0]
- LDR R0, [R0]
- CMP R0, R6
- BNE _test_cpu_reg0_reg13_fail
- MOVS R6, #0x6
-
- ; Register R7
- LDR R0, =data0xAAAAAAAA
- LDR R7, [R0]
- LDR R0, [R0]
- CMP R0, R7
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R7, [R0]
- LDR R0, [R0]
- CMP R0, R7
- BNE _test_cpu_reg0_reg13_fail
- MOVS R7, #0x7
-
- ; Register R8
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R8, R0
- CMP R0, R8
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R8, R0
- CMP R0, R8
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x08
- MOV R8, R0
-
- BAL _test_cpu_continue
-
-_test_cpu_reg0_reg13_fail
- ; test fail, R0 will hold value 1
- MOVS R0, #0x1 ; STL_ERR
- B _test_exit
-
-_test_cpu_continue
- ; Register R9
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R9, R0
- CMP R0, R9
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R9, R0
- CMP R0, R9
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x09
- MOV R9, R0
-
- ; Register R10
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R10, R0
- CMP R0, R10
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R10, R0
- CMP R0, R10
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0A
- MOV R10, R0
-
- ; Register R11
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R11, R0
- CMP R0, R11
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R11, R0
- CMP R0, R11
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0B
- MOV R11, R0
-
- ; Register R12
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R12, R0
- CMP R0, R12
- BNE _test_cpu_reg0_reg13_fail
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R12, R0
- CMP R0, R12
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0C
- MOV R12, R0
- LDR R0, =_test_cpu_continue
-
- ; pattern verification (R0 is not tested)
- CMP R1, #0x01
- BNE _test_cpu_reg0_reg13_fail
- CMP R2, #0x02
- BNE _test_cpu_reg0_reg13_fail
- CMP R3, #0x03
- BNE _test_cpu_reg0_reg13_fail
- CMP R4, #0x04
- BNE _test_cpu_reg0_reg13_fail
- CMP R5, #0x05
- BNE _test_cpu_reg0_reg13_fail
- CMP R6, #0x06
- BNE _test_cpu_reg0_reg13_fail
- CMP R7, #0x07
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x08
- CMP R0, R8
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x09
- CMP R0, R9
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0A
- CMP R0, R10
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0B
- CMP R0, R11
- BNE _test_cpu_reg0_reg13_fail
- MOVS R0, #0x0C
- CMP R0, R12
- BNE _test_cpu_reg0_reg13_fail
-
- ; Process Stack pointer (banked Register R13)
- MRS R0, PSP ; Save process stack value
- LDR R1, =data0xAAAAAAA8 ; Test is different (PSP is word aligned, 2 LSB cleared)
- LDR R1, [R1]
- MSR PSP, R1 ; load process stack value
- MRS R2, PSP ; Get back process stack value
- CMP R2, R1 ; Verify value
- BNE _test_cpu_reg0_reg13_fail
- LDR R1, =data0x55555554 ; Test is different (PSP is word aligned, 2 LSB cleared)
- LDR R1, [R1]
- MSR PSP, R1 ; load process stack value
- MRS R2, PSP ; Get back process stack value
- CMP R2, R1 ; Verify value
- BNE _test_cpu_reg0_reg13_fail
- MSR PSP, R0 ; Restore process stack value
-
- ; Stack pointer (Register R13)
- MRS R0, MSP ; Save stack pointer value
- LDR R1, =data0xAAAAAAA8 ; Test is different (SP is word aligned, 2 LSB cleared)
- LDR R1, [R1]
- MSR MSP, R1 ; load SP value
- MRS R2, MSP ; Get back SP value
- CMP R2, R1 ; Verify value
- BNE _test_cpu_reg0_reg13_fail
- LDR R1, =data0x55555554
- LDR R1, [R1] ; load SP value
- MSR MSP, R1 ; Get back SP value
- MRS R2, MSP ; Verify value
- CMP R2, R1
- BNE _test_cpu_reg0_reg13_fail
- MSR MSP, R0 ; Restore stack pointer value
-
-_test_cpu_r14_sfr
- ; Link register R14
- MOV R1, LR
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
-
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
-
- LDR R0, =data0x55555555
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
-
- LDR R0, =data0xAAAAAAAA
- LDR R0, [R0]
- MOV R14, R0
- CMP R0, R14
- BNE _test_cpu_r14_sfr_fail
- MOV LR, R1
-
- ; PRIMASK register
- MRS R1, PRIMASK
- LDR R0, =data0x00000000
- LDR R0, [R0]
- MSR PRIMASK, R0
- MRS R2, PRIMASK
- MOVS R3, #1
- ANDS R2, R3
- CMP R2, #0
- BNE _test_cpu_r14_sfr_fail
-
- LDR R0, =data0x00000001
- LDR R0, [R0]
- MSR PRIMASK, R0
- MRS R2, PRIMASK
- MOVS R3, #1
- ANDS R2, R3
- CMP R2, #1
- BNE _test_cpu_r14_sfr_fail
- MSR PRIMASK, R1
- B _test_cpu_pass
-
-_test_cpu_r14_sfr_fail
- ; test fail, R0 will hold value 1
- MOVS R0, #0x1 ; STL_ERR
- B _test_exit
-
-_test_cpu_pass
- ; test pass, R0 will hold value 0
- MOVS R0, #0x0 ; STL_OK
- B _test_exit
-
-_test_exit
- POP {R4-R7} ; Restore registers
- BX LR
-
- ENDP
-
- ALIGN
-
- END
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_full_ram_startup.s b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_full_ram_startup.s
deleted file mode 100644
index 77d13f5e9c..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_full_ram_startup.s
+++ /dev/null
@@ -1,191 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; * opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/* Test for MDK */
-;/* Version V1.0 */
-;/* Date 2022-03-31 */
-;/****************************************************************************/
- THUMB
- REQUIRE8
- PRESERVE8
-
- AREA |.text|, CODE, READONLY, ALIGN=2
-data0x00000000 DCD 0x00000000
-data0xFFFFFFFF DCD 0xFFFFFFFF
-
-;*******************************************************************************
-; Function Name : STL_FullRamTestStartup
-; Description : Full RAM test at start-up
-; Input : R0 .. RAM begin address
-; R1 .. RAM end address
-; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING : all registers destroyed when exiting this function (including
-; preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
-STL_FullRamTestStartup PROC
- EXPORT STL_FullRamTestStartup
-
- MOVS R4, #0x0 ; STL_OK:Test success status by default
-
- LDR R2, =data0x00000000 ; Prepares background pattern
- LDR R2, [R2]
- LDR R3, =data0xFFFFFFFF ; Prepares inverted background pattern
- LDR R3, [R3]
-
- ; *** Step 1 ***
- ; Write background pattern with addresses increasing
- MOVS R5, R0
-_step1_loop
- CMP R5, R1
- BHI _step_2
- STR R2, [R5, #+0]
- ADDS R5, R5, #+4
- B _step1_loop
-
- ; *** Step 2 ***
- ; Verify background and write inverted background with addresses increasing
-_step_2
- MOVS R5, R0
-_step_2_loop
- CMP R5, R1
- BHI _step_3
- LDR R6, [R5, #+0]
- CMP R6, R2
- BNE _full_ram1_test_fail
- STR R3, [R5, #+0]
- LDR R6, [R5, #+4]
- CMP R6, R2
- BNE _full_ram1_test_fail
- STR R3, [R5, #+4]
-
- LDR R6, [R5, #+8]
- CMP R6, R2
- BNE _full_ram1_test_fail
- STR R3, [R5, #+8]
- LDR R6, [R5, #+12]
- CMP R6, R2
- BNE _full_ram1_test_fail
- STR R3, [R5, #+12]
-
- ADDS R5, R5, #+16
- B _step_2_loop
-
- ; *** Step 3 ***
- ; Verify inverted background and write background with addresses increasing
-_step_3
- MOVS R5, R0
-_step_3_loop
- CMP R5, R1
- BHI _step_4
- LDR R6, [R5, #+0]
- CMP R6, R3
- BNE _full_ram1_test_fail
- STR R2, [R5, #+0]
- LDR R6, [R5, #+4]
- CMP R6, R3
- BNE _full_ram1_test_fail
- STR R2, [R5, #+4]
-
- LDR R6, [R5, #+8]
- CMP R6, R3
- BNE _full_ram1_test_fail
- STR R2, [R5, #+8]
- LDR R6, [R5, #+12]
- CMP R6, R3
- BNE _full_ram1_test_fail
- STR R2, [R5, #+12]
-
- ADDS R5, R5, #+16
- B _step_3_loop
-
- ; *** Step 4 ***
- ; Verify background and write inverted background with addresses decreasing
-_step_4
- MOVS R5, R1
- SUBS R5, R5, #+15
-_step_4_loop
- CMP R5, R0
- BLO _step_5
-
- LDR R6, [R5, #+12]
- CMP R6, R2
- BNE _full_ram1_test_fail
- STR R3, [R5, #+12]
- LDR R6, [R5, #+8]
- CMP R6, R2
- BNE _full_ram1_test_fail
- STR R3, [R5, #+8]
-
- LDR R6, [R5, #+4]
- CMP R6, R2
- BNE _full_ram1_test_fail
- STR R3, [R5, #+4]
- LDR R6, [R5, #+0]
- CMP R6, R2
- BNE _full_ram1_test_fail
- STR R3, [R5, #+0]
-
- SUBS R5, R5, #+16
- B _step_4_loop
-
- ; *** Step 5 ***
- ; Verify inverted background and write background with addresses decreasing
-_step_5
- MOVS R5, R1
- SUBS R5, R5, #+15
-_step_5_loop
- CMP R5, R0
- BLO _step_6
-
- LDR R6, [R5, #+12]
- CMP R6, R3
- BNE _full_ram1_test_fail
- STR R2, [R5, #+12]
- LDR R6, [R5, #+8]
- CMP R6, R3
- BNE _full_ram1_test_fail
- STR R2, [R5, #+8]
-
- LDR R6, [R5, #+4]
- CMP R6, R3
- BNE _full_ram1_test_fail
- STR R2, [R5, #+4]
- LDR R6, [R5, #+0]
- CMP R6, R3
- BNE _full_ram1_test_fail
- STR R2, [R5, #+0]
- SUBS R5, R5, #+16
- B _step_5_loop
-
- ; *** Step 6 ***
- ; Verify background with addresses increasing
-_step_6
- MOVS R5, R0
-_step_6_loop
- CMP R5, R1
- BHI _full_ram1_test_pass
- LDR R6, [R5, #+0]
- CMP R6, R2
- BNE _full_ram1_test_fail
- ADDS R5, R5, #+4
- B _step_6_loop
-
-_full_ram1_test_fail
- MOVS R4, #1 ; STL_ERR
-
-_full_ram1_test_pass
- MOVS R0, R4
- BX LR ; return to the caller
-
- ENDP
-
- ALIGN
-
- END
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_pc.s b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_pc.s
deleted file mode 100644
index f422011f2e..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_pc.s
+++ /dev/null
@@ -1,147 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; * opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/* Test for MDK */
-;/* Date Author Notes */
-;/* 2022-03-31 CDT First version */
-;/* 2023-05-31 CDT Typo: subrouitne -> subroutine */
-;/****************************************************************************/
-
- THUMB
- REQUIRE8
- PRESERVE8
-
- AREA |.text|, CODE, READONLY, ALIGN=2
-
-;*******************************************************************************
-; Function Name : STL_PcTest
-; Description : Test PC
-; Input : None.
-; Output : Perform routine when detect failure at set of self test cases
-; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING : all registers destroyed when exiting this function (including
-; preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
-
-STL_PcTest PROC
- EXPORT STL_PcTest
-
- PUSH {R4-R7} ; Save registers
- MOVS R0, #0
- MOVS R1, #0 ; clr R0,R1
- MOV R3, LR
-
-_subroutine_1
- LDR R0, =_return_pc_test_addr_1
- BL _return_pc_test_addr_1
- CMP R0, R1 ; verify return address?
- BEQ _subroutine_2
- B _pc_test_fail
-
-_subroutine_2
- LDR R0, =_return_pc_test_addr_2
- BL _return_pc_test_addr_2
- CMP R0, R1 ; verify return address?
- BEQ _subroutine_3
- B _pc_test_fail
-
-_subroutine_3
- LDR R0, =_return_pc_test_addr_3
- BL _return_pc_test_addr_3
- CMP R0, R1 ; verify return address?
- BEQ _subroutine_4
- B _pc_test_fail
-
-_subroutine_4
- LDR R0, =_return_pc_test_addr_4
- BL _return_pc_test_addr_4
- CMP R0, R1 ; verify return address?
- BEQ _subroutine_5
- B _pc_test_fail
-
-_subroutine_5
- LDR R0, =_return_pc_test_addr_5
- BL _return_pc_test_addr_5
- CMP R0, R1 ; verify return address?
- BEQ _subroutine_6
- B _pc_test_fail
-
-_subroutine_6
- LDR R0, =_return_pc_test_addr_6
- BL _return_pc_test_addr_6
- CMP R0, R1 ; verify return address?
- BEQ _subroutine_7
- B _pc_test_fail
-
-_subroutine_7
- LDR R0, =_return_pc_test_addr_7
- BL _return_pc_test_addr_7
- CMP R0, R1 ; verify return address?
- BEQ _subroutine_8
- B _pc_test_fail
-
-_subroutine_8
- LDR R0, =_return_pc_test_addr_8
- BL _return_pc_test_addr_8
- CMP R0, R1 ; verify return address?
- BEQ _pc_test_pass
- B _pc_test_fail
-
-_pc_test_fail
- ; when test fail, R0 will hold value 1
- MOVS R0, #0x1 ; STL_ERR
- B _pc_test_exit
-
-_pc_test_pass
- ; when test pass, R0 will hold value 0
- MOVS R0, #0x0 ; STL_OK
- B _pc_test_exit
-
-_pc_test_exit
- POP {R4-R7} ; Restore registers
- BX R3 ; return
-
-_return_pc_test_addr_1
- LDR R1, =_return_pc_test_addr_1 ; store subroutine address in R1
- BX LR
-
-_return_pc_test_addr_2
- LDR R1, =_return_pc_test_addr_2 ; store subroutine address in R1
- BX LR
-
-_return_pc_test_addr_3
- LDR R1, =_return_pc_test_addr_3 ; store subroutine address in R1
- BX LR
-
-_return_pc_test_addr_4
- LDR R1, =_return_pc_test_addr_4 ; store subroutine address in R1
- BX LR
-
-_return_pc_test_addr_5
- LDR R1, =_return_pc_test_addr_5 ; store subroutine address in R1
- BX LR
-
-_return_pc_test_addr_6
- LDR R1, =_return_pc_test_addr_6 ; store subroutine address in R1
- BX LR
-
-_return_pc_test_addr_7
- LDR R1, =_return_pc_test_addr_7 ; store subroutine address in R1
- BX LR
-
-_return_pc_test_addr_8
- LDR R1, =_return_pc_test_addr_8 ; store subroutine address in R1
- BX LR
-
- ENDP
-
- ALIGN
-
- END
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_sw_crc32.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_sw_crc32.c
deleted file mode 100644
index b02345f93c..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_sw_crc32.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/**
- *******************************************************************************
- * @file stl_sw_crc32.c
- * @brief This file provides firmware functions to manage the software CRC32.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2022-06-30 CDT Fix warning: MISRAC2012-Rule-18.4
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_sw_crc32.h"
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @defgroup STL_IEC60730_CRC32 STL IEC60730 CRC32
- * @brief IEC60730 software CRC32
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-
-/**
- * @defgroup STL_IEC60730_CRC32_Local_Variables STL IEC60730 CRC32 Local Variables
- * @{
- */
-static const uint32_t m_au32Crc32Table[256] = {
- 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, 0x076DC419, 0x706AF48F,
- 0xE963A535, 0x9E6495A3, 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
- 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91, 0x1DB71064, 0x6AB020F2,
- 0xF3B97148, 0x84BE41DE, 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
- 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC, 0x14015C4F, 0x63066CD9,
- 0xFA0F3D63, 0x8D080DF5, 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
- 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B, 0x35B5A8FA, 0x42B2986C,
- 0xDBBBC9D6, 0xACBCF940, 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
- 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, 0x21B4F4B5, 0x56B3C423,
- 0xCFBA9599, 0xB8BDA50F, 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
- 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D, 0x76DC4190, 0x01DB7106,
- 0x98D220BC, 0xEFD5102A, 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
- 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818, 0x7F6A0DBB, 0x086D3D2D,
- 0x91646C97, 0xE6635C01, 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
- 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457, 0x65B0D9C6, 0x12B7E950,
- 0x8BBEB8EA, 0xFCB9887C, 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
- 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2, 0x4ADFA541, 0x3DD895D7,
- 0xA4D1C46D, 0xD3D6F4FB, 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
- 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9, 0x5005713C, 0x270241AA,
- 0xBE0B1010, 0xC90C2086, 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
- 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, 0x59B33D17, 0x2EB40D81,
- 0xB7BD5C3B, 0xC0BA6CAD, 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
- 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683, 0xE3630B12, 0x94643B84,
- 0x0D6D6A3E, 0x7A6A5AA8, 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
- 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE, 0xF762575D, 0x806567CB,
- 0x196C3671, 0x6E6B06E7, 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
- 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5, 0xD6D6A3E8, 0xA1D1937E,
- 0x38D8C2C4, 0x4FDFF252, 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
- 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60, 0xDF60EFC3, 0xA867DF55,
- 0x316E8EEF, 0x4669BE79, 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
- 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F, 0xC5BA3BBE, 0xB2BD0B28,
- 0x2BB45A92, 0x5CB36A04, 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
- 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A, 0x9C0906A9, 0xEB0E363F,
- 0x72076785, 0x05005713, 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
- 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21, 0x86D3D2D4, 0xF1D4E242,
- 0x68DDB3F8, 0x1FDA836E, 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
- 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C, 0x8F659EFF, 0xF862AE69,
- 0x616BFFD3, 0x166CCF45, 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
- 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB, 0xAED16A4A, 0xD9D65ADC,
- 0x40DF0B66, 0x37D83BF0, 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
- 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6, 0xBAD03605, 0xCDD70693,
- 0x54DE5729, 0x23D967BF, 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
- 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
-};
-/**
- * @}
- */
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @defgroup STL_IEC60730_CRC32_Global_Functions STL IEC60730 CRC32 Global Functions
- * @{
- */
-
-/**
- * @brief Calculate CRC32 value.
- * @param [in] u32Crc32Value CRC32 value
- * @param [in] pu8Data Pointer to data buffer
- * @param [in] u32Len Data length
- * @retval CRC32 value
- * @note Poly=0x04C11DB7, Init=0xFFFFFFFF, RefIn=true, RefOut=true, XorOut=0x00000000
- */
-uint32_t STL_CalculateCRC32Value(uint32_t u32Crc32Value, uint8_t *pu8Data, uint32_t u32Len)
-{
- uint32_t i;
- uint32_t u32CurrCrc32Value = u32Crc32Value;
-
- for (i = 0UL; i < u32Len; i++) {
- u32CurrCrc32Value = (u32CurrCrc32Value >> 8) ^ m_au32Crc32Table[(u32CurrCrc32Value & 0xFFUL) ^ pu8Data[i]];
- }
-
- return u32CurrCrc32Value;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_flash.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_flash.c
deleted file mode 100644
index f465ccefbe..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_flash.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/**
- *******************************************************************************
- * @file stl_test_flash.c
- * @brief This file provides firmware functions to manage the flash test.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2022-06-30 CDT Fix warning: MISRAC2012-Rule-18.4
- 2023-01-15 CDT Fix bug: Reading CC Build CRC32 value is error in release project
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_conf.h"
-#include "stl_utility.h"
-#include "stl_sw_crc32.h"
-#include "stl_test_flash.h"
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @defgroup STL_IEC60730_Flash STL IEC60730 Flash
- * @brief IEC60730 flash test
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#if defined (__CC_ARM) /* keil Compiler */
-#define STL_CRC32_XOR_VALUE (0xFFFFFFFFUL)
-#elif defined (__IAR_SYSTEMS_ICC__) /* IAR Compiler */
-#define STL_CRC32_XOR_VALUE (0x00000000UL)
-#endif
-
-#define SW_CRC32_VALUE_XOR(x) ((x) ^ STL_CRC32_XOR_VALUE)
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-/**
- * @defgroup STL_IEC60730_Flash_Local_Variables STL IEC60730 Flash Local Variables
- * @{
- */
-STL_USED const uint32_t __checksum STL_SECTION(".checksum") = 0UL;
-/**
- * @}
- */
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @defgroup STL_IEC60730_Flash_Global_Functions STL IEC60730 Flash Global Functions
- * @{
- */
-
-/**
- * @brief Flash test in startup.
- * @param None
- * @retval uint32_t:
- * - STL_OK: Test pass.
- * - STL_ERR: Flash CRC value error.
- */
-uint32_t STL_FlashStartupTest(void)
-{
- uint32_t u32RomStart = STL_ROM_CRC32_START;
- uint32_t u32RomEnd = STL_ROM_CRC32_END;
- uint32_t u32RomSize = (u32RomEnd - u32RomStart);
- uint8_t *pu8CrcData = (uint8_t *)u32RomStart;
- uint32_t u32CalcCrc32Value;
- volatile uint32_t u32CcBulidCrc32Addr;
- volatile uint32_t u32CcBulidCrc32Value;
- uint32_t u32Ret = STL_ERR;
-
- u32CcBulidCrc32Addr = (uint32_t)(&STL_ROM_CRC32_CC_CHECKSUM);
- u32CcBulidCrc32Value = *(uint32_t *)(u32CcBulidCrc32Addr);
- u32CalcCrc32Value = STL_CalculateCRC32Value(STL_CRC32_INIT_VALUE, pu8CrcData, u32RomSize);
- u32CalcCrc32Value = SW_CRC32_VALUE_XOR(u32CalcCrc32Value);
- if (u32CcBulidCrc32Value == u32CalcCrc32Value) {
- u32Ret = STL_OK;
- }
-
- return u32Ret;
-}
-
-/**
- * @brief Flash test in runtime.
- * @param None
- * @retval uint32_t:
- * - STL_OK: Test pass.
- * - STL_ERR: Flash CRC value error.
- */
-uint32_t STL_FlashRuntimeTest(void)
-{
- uint32_t u32Ret = STL_OK;
- uint32_t u32RomStart = STL_ROM_CRC32_START;
- uint32_t u32RomEnd = STL_ROM_CRC32_END;
- uint32_t u32RomSize = (u32RomEnd - u32RomStart);
- volatile uint32_t u32CcBulidCrc32Addr;
- volatile uint32_t u32CcBulidCrc32Value;
- const uint32_t u32CheckEndAddr = u32RomSize + 3UL - STL_ROM_CRC32_BLOCK_SIZE;
- static uint32_t u32CalcLen;
- static uint32_t u32CheckAddr = STL_ROM_CRC32_START;
- static uint32_t u32CalcCrc32Value = STL_CRC32_INIT_VALUE;
-
- if (u32CheckAddr < STL_ROM_CRC32_END) {
- if (u32CheckAddr == STL_ROM_CRC32_START) {
- u32CalcCrc32Value = STL_CRC32_INIT_VALUE; /* Update CRC32 init value */
- }
-
- if (u32CheckAddr < u32CheckEndAddr) {
- u32CalcLen = STL_ROM_CRC32_BLOCK_SIZE;
- } else {
- u32CalcLen = u32RomEnd - u32CheckAddr;
- }
- u32CalcCrc32Value = STL_CalculateCRC32Value(u32CalcCrc32Value, (uint8_t *)u32CheckAddr, u32CalcLen);
-
- u32CheckAddr += u32CalcLen; /* Update address */
- } else {
- u32CcBulidCrc32Addr = (uint32_t)(&STL_ROM_CRC32_CC_CHECKSUM);
- u32CcBulidCrc32Value = *(uint32_t *)(u32CcBulidCrc32Addr);
- u32CheckAddr = STL_ROM_CRC32_START; /* Update address */
- u32CalcCrc32Value = SW_CRC32_VALUE_XOR(u32CalcCrc32Value);
- if (u32CcBulidCrc32Value == u32CalcCrc32Value) {
- STL_Printf("******** CRC32 verify ok in runtime ********\r\n");
- } else {
- STL_Printf("******** CRC32 verify error in runtime ********\r\n");
- STL_Printf("* Calc_CRC32= 0x%x:CC Build_CRC32= 0x%x *\r\n", u32CalcCrc32Value, u32CcBulidCrc32Value);
- u32Ret = STL_ERR;
- }
- }
-
- return u32Ret;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_interrupt.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_interrupt.c
deleted file mode 100644
index 67dc0c5fc0..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_interrupt.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/**
- *******************************************************************************
- * @file stl_test_interrupt.c
- * @brief This file provides firmware functions to manage the interrupt test.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_conf.h"
-#include "stl_test_interrupt.h"
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @defgroup STL_IEC60730_Interrupt_Runtime STL IEC60730 Interrupt Runtime
- * @brief IEC60730 interrupt runtime test
- * @{
- */
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-/**
- * @defgroup STL_IEC60730_RAM_Local_Variables STL IEC60730 RAM Local Variables
- * @{
- */
-static uint32_t m_u32TestParamTableSize;
-static stc_stl_int_params_t *m_pstcTestParamTable;
-/**
- * @}
- */
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @defgroup STL_IEC60730_Interrupt_Global_Functions STL IEC60730 Interrupt Global Functions
- * @{
- */
-
-/**
- * @brief Interrupt test table initialize in runtime.
- * @param [in] pstcParamsTable Test case table
- * @param [in] u32TableSize Test case size
- * @retval uint32_t:
- * - STL_OK: Initialize successfully.
- * - STL_ERR: Initialize unsuccessfully.
- */
-uint32_t STL_IntRuntimeTableInit(stc_stl_int_params_t *pstcParamsTable, uint32_t u32TableSize)
-{
- uint32_t i;
- uint32_t u32Ret = STL_ERR;
-
- if ((pstcParamsTable != NULL) && (u32TableSize != 0UL)) {
- for (i = 0UL; i < u32TableSize; i++) {
- pstcParamsTable[i].u32PrivateParam = 0UL;
- }
-
- m_pstcTestParamTable = pstcParamsTable;
- m_u32TestParamTableSize = u32TableSize;
- u32Ret = STL_OK;
- }
-
- return u32Ret;
-}
-
-/**
- * @brief Interrupt test in runtime.
- * @param None
- * @retval uint32_t:
- * - STL_OK: Test pass.
- * - STL_ERR: Test error.
- */
-uint32_t STL_IntRuntimeTest(void)
-{
- uint32_t i;
- uint32_t u32Ret = STL_OK;
- stc_stl_int_params_t *pstcTestParam;
- static uint32_t u32SystickCount;
-
- if (++u32SystickCount == STL_SYSTICK_TICK_FREQ) {
- for (i = 0UL; i < m_u32TestParamTableSize; i++) {
- pstcTestParam = &m_pstcTestParamTable[i];
-
- if ((pstcTestParam->u32PrivateParam < pstcTestParam->u32FreqLowerVal) || \
- (pstcTestParam->u32PrivateParam > pstcTestParam->u32FreqUpperVal)) {
- u32Ret = STL_ERR;
- }
- pstcTestParam->u32PrivateParam = 0UL;
- }
- u32SystickCount = 0UL;
- }
-
- return u32Ret;
-}
-
-/**
- * @brief Update interrupt count in runtime.
- * @param [in] u8ParamIndex Params index
- * @retval None
- */
-void STL_IntUpdateCount(uint8_t u8ParamIndex)
-{
- stc_stl_int_params_t *pstcTestParam;
-
- if (u8ParamIndex < m_u32TestParamTableSize) {
- pstcTestParam = &m_pstcTestParamTable[u8ParamIndex];
- pstcTestParam->u32PrivateParam++;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_ram_runtime.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_ram_runtime.c
deleted file mode 100644
index 4f010f9e71..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_ram_runtime.c
+++ /dev/null
@@ -1,269 +0,0 @@
-/**
- *******************************************************************************
- * @file stl_test_ram_runtime.c
- * @brief This file provides firmware functions to manage the RAM test.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2022-06-30 CDT Fix warning: MISRAC2012-Rule-18.4
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_conf.h"
-#include "stl_test_ram.h"
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @defgroup STL_IEC60730_RAM_Runtime STL IEC60730 RAM Runtime
- * @brief IEC60730 RAM runtime test
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-/**
- * @defgroup STL_IEC60730_RAM_Local_Variables STL IEC60730 RAM Local Variables
- * @{
- */
-STL_USED uint32_t m_au32MarchRAM[STL_MARCH_RAM_WORDS] STL_SECTION(".march_ram");
-STL_USED uint32_t m_au32MarchRAMBuf[STL_MARCH_RAM_BUF_WORDS] STL_SECTION(".march_ram_buf");
-STL_USED uint32_t *m_pu32MarchRAM STL_SECTION(".march_ram_pointer");
-STL_USED uint32_t m_au32StackBoundary[STL_STACK_BOUNDARY_WORDS] STL_SECTION(".stack_boundary");
-/**
- * @}
- */
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @defgroup STL_IEC60730_RAM_Global_Functions STL IEC60730 RAM Global Functions
- * @{
- */
-
-/**
- * @brief Stack test initialize in runtime.
- * @param None
- * @retval uint32_t:
- * - STL_OK: Initialization pass.
- */
-uint32_t STL_StackRuntimeInit(void)
-{
- m_au32StackBoundary[0] = 0x5A5A5A5AUL;
- m_au32StackBoundary[1] = 0xA5A5A5A5UL;
- m_au32StackBoundary[2] = 0xAAAAAAAAUL;
- m_au32StackBoundary[3] = 0x55555555UL;
- return STL_OK;
-}
-
-/**
- * @brief Stack test in runtime.
- * @param None
- * @retval uint32_t:
- * - STL_OK: Test pass.
- * - STL_ERR: Stack boundary value error.
- */
-uint32_t STL_StackRuntimeTest(void)
-{
- if ((m_au32StackBoundary[0] != 0x5A5A5A5AUL) || \
- (m_au32StackBoundary[1] != 0xA5A5A5A5UL) || \
- (m_au32StackBoundary[2] != 0xAAAAAAAAUL) || \
- (m_au32StackBoundary[3] != 0x55555555UL)) {
- return STL_ERR;
- }
-
- return STL_OK;
-}
-
-/**
- * @brief RAM test initialize in runtime.
- * @param None
- * @retval uint32_t:
- * - STL_OK: Initialization pass.
- */
-uint32_t STL_RamRuntimeInit(void)
-{
- m_pu32MarchRAM = (uint32_t *)STL_MARCH_RAM_START;
- return STL_OK;
-}
-
-/**
- * @brief RAM test in runtime.
- * @param None
- * @retval uint32_t:
- * - STL_OK: Test pass.
- * - STL_ERR: Test fail.
- */
-uint32_t STL_RamRuntimeTest(void)
-{
- uint32_t i; /* Index for RAM physical addressing */
- uint32_t u32Ret = STL_OK;
-
- if (m_pu32MarchRAM >= (uint32_t *)STL_MARCH_RAM_END) {
- /*------------- March C- to the RAM Buffer itself --------------- */
- m_pu32MarchRAM = &m_au32MarchRAMBuf[0];
-
- /*---------------------------- STEP 1 --------------------------------- */
- /* Write background with addresses increasing */
- for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
- m_pu32MarchRAM[i] = STL_MARCH_RAM_BCKGRND;
- }
-
- /*---------------------------- STEP 2 --------------------------------- */
- /* Verify background and write inverted background addresses increasing */
- for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
- if (m_pu32MarchRAM[i] != STL_MARCH_RAM_BCKGRND) {
- u32Ret = STL_ERR;
- }
- m_pu32MarchRAM[i] = STL_MARCH_RAM_INVBCKGRND;
- }
-
- /*---------------------------- STEP 3 --------------------------------- */
- /* Verify inverted background and write background addresses increasing */
- for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
- if (m_pu32MarchRAM[i] != STL_MARCH_RAM_INVBCKGRND) {
- u32Ret = STL_ERR;
- }
- m_pu32MarchRAM[i] = STL_MARCH_RAM_BCKGRND;
- }
-
- /*---------------------------- STEP 4 --------------------------------- */
- /* Verify background and write inverted background addresses decreasing */
- for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL ; --i) {
- if (m_pu32MarchRAM[i - 1UL] != STL_MARCH_RAM_BCKGRND) {
- u32Ret = STL_ERR;
- }
- m_pu32MarchRAM[i - 1UL] = STL_MARCH_RAM_INVBCKGRND;
- }
-
- /*---------------------------- STEP 5 --------------------------------- */
- /* Verify inverted background and write background addresses decreasing */
- for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL ; --i) {
- if (m_pu32MarchRAM[i - 1UL] != STL_MARCH_RAM_INVBCKGRND) {
- u32Ret = STL_ERR;
- }
- m_pu32MarchRAM[i - 1UL] = STL_MARCH_RAM_BCKGRND;
- }
-
- /*---------------------------- STEP 6 --------------------------------- */
- /* Verify background with addresses increasing */
- for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
- if (m_pu32MarchRAM[i] != STL_MARCH_RAM_BCKGRND) {
- u32Ret = STL_ERR;
- }
- }
-
- /* Prepare next Tranparent RAM test from the beginning of Class A area */
- m_pu32MarchRAM = (uint32_t *)STL_MARCH_RAM_START;
- } else {
- /*---------------------------- STEP 1 --------------------------------- */
- /* Save the content of the 6 words to be tested and start MarchC -
- Write background with addresses increasing */
- for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
- m_au32MarchRAMBuf[i] = m_pu32MarchRAM[i];
- m_pu32MarchRAM[i] = STL_MARCH_RAM_BCKGRND;
- }
-
- /*---------------------------- STEP 2 --------------------------------- */
- /* Verify background and write inverted background addresses increasing */
- for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
- if (m_pu32MarchRAM[i] != STL_MARCH_RAM_BCKGRND) {
- u32Ret = STL_ERR;
- }
- m_pu32MarchRAM[i] = STL_MARCH_RAM_INVBCKGRND;
- }
-
- /*---------------------------- STEP 3 --------------------------------- */
- /* Verify inverted background and write background addresses increasing */
- for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
- if (m_pu32MarchRAM[i] != STL_MARCH_RAM_INVBCKGRND) {
- u32Ret = STL_ERR;
- }
- m_pu32MarchRAM[i] = STL_MARCH_RAM_BCKGRND;
- }
-
- /*---------------------------- STEP 4 --------------------------------- */
- /* Verify background and write inverted background addresses decreasing */
- for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL; --i) {
- if (m_pu32MarchRAM[i - 1UL] != STL_MARCH_RAM_BCKGRND) {
- u32Ret = STL_ERR;
- }
- m_pu32MarchRAM[i - 1UL] = STL_MARCH_RAM_INVBCKGRND;
- }
-
- /*---------------------------- STEP 5 --------------------------------- */
- /* Verify inverted background and write background addresses decreasing */
- for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL; --i) {
- if (m_pu32MarchRAM[i - 1UL] != STL_MARCH_RAM_INVBCKGRND) {
- u32Ret = STL_ERR;
- }
- m_pu32MarchRAM[i - 1UL] = STL_MARCH_RAM_BCKGRND;
- }
-
- /*---------------------------- STEP 6 --------------------------------- */
- /* Verify background with addresses increasing */
- /* and restore the content of the 6 tested words */
- for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
- if (m_pu32MarchRAM[i] != STL_MARCH_RAM_BCKGRND) {
- u32Ret = STL_ERR;
- }
- m_pu32MarchRAM[i] = m_au32MarchRAMBuf[i];
- }
-
- /* Prepare next Row Tranparent RAM test */
- m_pu32MarchRAM = &m_pu32MarchRAM[STL_MARCH_RAM_BUF_WORDS];
- }
-
- return u32Ret;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.c
deleted file mode 100644
index 2a27a38d19..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/**
- *******************************************************************************
- * @file stl_test_runtime.c
- * @brief This file provides firmware functions to manage the runtime self-test.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_test_runtime.h"
-#include "stl_conf.h"
-#include "stl_utility.h"
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @defgroup STL_IEC60730_Runtime STL IEC60730 Runtime
- * @brief IEC60730 runtime test
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @defgroup STL_IEC60730_Runtime_Global_Macros STL IEC60730 Runtime Global Macros
- * @{
- */
-
-/**
- * @brief Self-test initialization in runtime.
- * @param [in] pstcCaseTable Test case table
- * @param [in] u32TableSize Test case size
- * @retval None
- */
-void STL_RuntimeTestInit(const stc_stl_case_runtime_t *pstcCaseTable, uint32_t u32TableSize)
-{
- uint32_t i;
-#if (STL_PRINT_ENABLE == STL_ON)
- static en_flag_status_t enPrintInitActived = RESET;
-#endif
-
-#if (STL_PRINT_ENABLE == STL_ON)
- /* startup debug print */
- if (enPrintInitActived == RESET) {
- (void)STL_PrintfInit();
- enPrintInitActived = SET;
- }
-#endif
-
- STL_Printf("******** Self-test runtime initialize ********\r\n");
-
- if ((pstcCaseTable != NULL) && (u32TableSize != 0UL)) {
- for (i = 0UL; i < u32TableSize; i++) {
- if (pstcCaseTable[i].pfnInit != NULL) {
- if (pstcCaseTable[i].pfnInit() != STL_OK) {
- STL_Printf("******** Init fail in runtime: %-20s ********\r\n", pstcCaseTable[i].pcCaseName);
- }
- }
- }
- }
-}
-
-/**
- * @brief Self-test on runtime.
- * @param [in] pstcCaseTable Test case table
- * @param [in] u32TableSize Test case size
- * @retval None
- */
-void STL_RuntimeTestCase(const stc_stl_case_runtime_t *pstcCaseTable, uint32_t u32TableSize)
-{
- uint32_t i;
-
- if ((pstcCaseTable != NULL) && (u32TableSize != 0UL)) {
- for (i = 0UL; i < u32TableSize; i++) {
- if (pstcCaseTable[i].pfnTest != NULL) {
- if (pstcCaseTable[i].pfnTest() != STL_OK) {
- STL_Printf("******** Test fail in runtime: %-20s ********\r\n", pstcCaseTable[i].pcCaseName);
-
- if (pstcCaseTable[i].pfnFailHandler != NULL) {
- pstcCaseTable[i].pfnFailHandler();
- }
- }
- }
-
- if (pstcCaseTable[i].pfnFeedDog != NULL) {
- pstcCaseTable[i].pfnFeedDog();
- }
- }
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.h
deleted file mode 100644
index 29877056e2..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/**
- *******************************************************************************
- * @file stl_test_runtime.h
- * @brief This file contains all the functions prototypes of runtime test.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_TEST_RUNTIME_H__
-#define __STL_TEST_RUNTIME_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_common.h"
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @addtogroup STL_IEC60730_Runtime
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-
-/**
- * @defgroup STL_IEC60730_Runtime_Global_Type STL IEC60730 Runtime Global Type
- * @{
- */
-typedef struct stc_stl_case_runtime {
- const char *pcCaseName;
- uint32_t (*pfnInit)(void);
- uint32_t (*pfnTest)(void);
-
- void (*pfnFeedDog)(void);
- void (*pfnFailHandler)(void);
-} stc_stl_case_runtime_t;
-/**
- * @}
- */
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/**
- * @defgroup STL_IEC60730_Runtime_Case STL IEC60730 Runtime Case
- * @{
- */
-#define STL_RUNTIME_CASE(CaseName, pfnInit, pfnTest, pfnFeedDog, pfnFailHandler) \
- { #CaseName, pfnInit, pfnTest, pfnFeedDog, pfnFailHandler }
-/**
- * @}
- */
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-/**
- * @addtogroup STL_IEC60730_Runtime_Global_Functions
- * @{
- */
-
-void STL_RuntimeTestInit(const stc_stl_case_runtime_t *pstcCaseTable, uint32_t u32TableSize);
-void STL_RuntimeTestCase(const stc_stl_case_runtime_t *pstcCaseTable, uint32_t u32TableSize);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* #include "stl_common.h" */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.c
deleted file mode 100644
index fc1e486e0d..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/**
- *******************************************************************************
- * @file stl_test_startup.c
- * @brief This file provides firmware functions to manage the startup test.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_common.h"
-#include "stl_conf.h"
-#include "stl_utility.h"
-#include "stl_test_startup.h"
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @defgroup STL_IEC60730_Startup STL IEC60730 Startup
- * @brief IEC60730 startup test
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @defgroup STL_IEC60730_Startup_Global_Macros STL IEC60730 Startup Global Macros
- * @{
- */
-
-/**
- * @brief Power on self-test.
- * @param None
- * @retval None
- */
-STL_WEAK void STL_StartupTest(void)
-{
- /* please implement this function. */
- for (;;) {
- }
-}
-
-/**
- * @brief Power on self-test.
- * @param [in] pstcCaseTable Test case table
- * @param [in] u32TableSize Test case size
- * @retval None
- */
-void STL_StartupTestCase(const stc_stl_case_startup_t *pstcCaseTable, uint32_t u32TableSize)
-{
- uint32_t i;
-
- if ((pstcCaseTable != NULL) && (u32TableSize != 0UL)) {
- for (i = 0UL; i < u32TableSize; i++) {
- if (pstcCaseTable[i].pfnTest != NULL) {
- if (pstcCaseTable[i].pfnTest() != STL_OK) {
- STL_Printf("******** Test fail in startup: %-20s ********\r\n", pstcCaseTable[i].pcCaseName);
-
- if (pstcCaseTable[i].pfnFailHandler != NULL) {
- pstcCaseTable[i].pfnFailHandler();
- }
- }
- }
- }
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.h
deleted file mode 100644
index c7e4628a7c..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/**
- *******************************************************************************
- * @file stl_test_startup.h
- * @brief This file contains all the functions prototypes of startup test.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_TEST_STARTUP_H__
-#define __STL_TEST_STARTUP_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_common.h"
-#include "stl_conf.h"
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @addtogroup STL_IEC60730_Startup
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-
-/**
- * @defgroup STL_IEC60730_Runtime_Global_Type STL IEC60730 Runtime Global Type
- * @{
- */
-typedef struct stc_stl_case_startup {
- const char *pcCaseName;
- uint32_t (*pfnTest)(void);
-
- void (*pfnFailHandler)(void);
-} stc_stl_case_startup_t;
-/**
- * @}
- */
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/**
- * @defgroup STL_IEC60730_Startup_Case STL IEC60730 Startup Case
- * @{
- */
-#define STL_STARTUP_CASE(CaseName, pfnTest, pfnFailHandler) \
- { #CaseName, pfnTest, pfnFailHandler }
-/**
- * @}
- */
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-/**
- * @addtogroup STL_IEC60730_Startup_Global_Functions
- * @{
- */
-void STL_StartupTest(void);
-void STL_StartupTestCase(const stc_stl_case_startup_t *pstcCaseTable, uint32_t u32TableSize);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_TEST_STARTUP_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.c
deleted file mode 100644
index 8cef35f95d..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.c
+++ /dev/null
@@ -1,236 +0,0 @@
-/**
- *******************************************************************************
- * @file stl_utility.c
- * @brief This file provides utility functions for STL.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2023-01-15 CDT Modify USART_SR_TXE to USART_SR_TC in STL_ConsoleOutputChar()
- 2023-05-31 CDT Modify register USART DR to USART TDR
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_utility.h"
-#include "hc32_ll_fcg.h"
-#include "hc32_ll_gpio.h"
-#include "hc32_ll_usart.h"
-#include "hc32_ll_utility.h"
-
-/**
- * @addtogroup IEC60730_STL
- * @{
- */
-
-/**
- * @defgroup IEC60730_STL_Utility IEC60730 STL Utility
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @defgroup STL_IEC60730_Utility_Global_Functions STL IEC60730 Utility Global Functions
- * @{
- */
-
-/**
- * @brief Delay function, delay us approximately
- * @param [in] u32Count us
- * @retval None
- */
-void STL_DelayUS(uint32_t u32Count)
-{
- DDL_DelayUS(u32Count);
-}
-
-/**
- * @brief Delay function, delay ms approximately
- * @param [in] u32Count ms
- * @retval None
- */
-void STL_DelayMS(uint32_t u32Count)
-{
- DDL_DelayMS(u32Count);
-}
-
-/**
- * @brief STL test safety failure handle
- * @param None
- * @retval None
- */
-void STL_SafetyFailure(void)
-{
-#if (STL_RESET_AT_FAILURE == STL_ON)
- NVIC_SystemReset(); /* Generate system reset */
-#endif
-}
-
-#if (STL_PRINT_ENABLE == STL_ON)
-
-/**
- * @brief Transmit character.
- * @param [in] cData The character for transmitting
- * @retval uint32_t:
- * - STL_OK: Transmit successfully.
- * - STL_ERR: Transmit timeout.
- */
-__WEAKDEF uint32_t STL_ConsoleOutputChar(char cData)
-{
- uint32_t u32Ret = STL_ERR;
- uint32_t u32TxEmpty = 0UL;
- __IO uint32_t u32TmpCount = 0UL;
- uint32_t u32Timeout = 10000UL;
-
- /* Wait TX data register empty */
- while ((u32TmpCount <= u32Timeout) && (0UL == u32TxEmpty)) {
- u32TxEmpty = READ_REG32_BIT(STL_PRINTF_DEVICE->SR, USART_SR_TC);
- u32TmpCount++;
- }
-
- if (0UL != u32TxEmpty) {
- WRITE_REG16(STL_PRINTF_DEVICE->TDR, (uint16_t)cData);
- u32Ret = STL_OK;
- }
-
- return u32Ret;
-}
-
-#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \
- (defined (__ICCARM__)) || (defined (__CC_ARM))
-/**
- * @brief Re-target fputc function.
- * @param [in] ch
- * @param [in] f
- * @retval int32_t
- */
-int32_t fputc(int32_t ch, FILE *f)
-{
- (void)f; /* Prevent unused argument compilation warning */
-
- return (STL_OK == STL_ConsoleOutputChar((char)ch)) ? ch : -1;
-}
-
-#elif defined (__GNUC__) && !defined (__CC_ARM)
-/**
- * @brief Re-target _write function.
- * @param [in] fd
- * @param [in] data
- * @param [in] size
- * @retval int32_t
- */
-int32_t _write(int fd, char data[], int32_t size)
-{
- int32_t i = -1;
-
- if (NULL != data) {
- (void)fd; /* Prevent unused argument compilation warning */
-
- for (i = 0; i < size; i++) {
- if (STL_OK != STL_ConsoleOutputChar(data[i])) {
- break;
- }
- }
- }
-
- return i ? i : -1;
-}
-#endif
-
-/**
- * @brief Initialize printf function
- * @param None
- * @retval None
- */
-uint32_t STL_PrintfInit(void)
-{
- uint32_t u32Div;
- float32_t f32Error;
- uint32_t u32Ret = STL_ERR;
- stc_usart_uart_init_t stcUartInit;
-
- /* Set TX port function */
- GPIO_SetFunc(STL_PRINTF_PORT, STL_PRINTF_PIN, STL_PRINTF_PORT_FUNC);
-
- /* Enable clock */
- STL_PRINTF_DEVICE_FCG_ENALBE();
-
- /***************************************************************************
- * Configure UART
- ***************************************************************************
- * Baud rate: STL_PRINTF_BAUDRATE
- * Bit direction: LSB
- * Data bits: 8
- * Stop bits: 1
- * Parity: None
- * Sampling bits: 8
- **************************************************************************/
- /* Configure UART */
- (void)USART_UART_StructInit(&stcUartInit);
- stcUartInit.u32OverSampleBit = USART_OVER_SAMPLE_8BIT;
- (void)USART_UART_Init(STL_PRINTF_DEVICE, &stcUartInit, NULL);
-
- for (u32Div = 0UL; u32Div <= USART_CLK_DIV64; u32Div++) {
- USART_SetClockDiv(STL_PRINTF_DEVICE, u32Div);
- if ((LL_OK == USART_SetBaudrate(STL_PRINTF_DEVICE, STL_PRINTF_BAUDRATE, &f32Error)) && \
- ((-STL_PRINTF_BAUDRATE_ERR_MAX <= f32Error) && (f32Error <= STL_PRINTF_BAUDRATE_ERR_MAX))) {
- USART_FuncCmd(STL_PRINTF_DEVICE, USART_TX, ENABLE);
- u32Ret = STL_OK;
- break;
- }
- }
-
- return u32Ret;
-}
-
-#endif /* STL_PRINT_ENABLE */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.h
deleted file mode 100644
index afd90a0039..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/**
- *******************************************************************************
- * @file stl_utility.h
- * @brief This file contains all the functions prototypes of utility.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_UTILITY_H__
-#define __STL_UTILITY_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_common.h"
-#include "stl_conf.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup IEC60730_STL
- * @{
- */
-
-/**
- * @addtogroup IEC60730_STL_Utility
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-/**
- * @addtogroup STL_UTILITY_Global_Functions
- * @{
- */
-
-#if (STL_PRINT_ENABLE == STL_ON)
-#include
-uint32_t STL_ConsoleOutputChar(char cData);
-#define STL_Printf (void)printf
-#else
-#define STL_Printf(...)
-#endif
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-
-/**
- * @addgroup STL_Utility_Global_Functions
- * @{
- */
-void STL_DelayUS(uint32_t u32Count);
-void STL_DelayMS(uint32_t u32Count);
-
-void STL_SafetyFailure(void);
-
-uint32_t STL_PrintfInit(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_UTILITY_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.c
deleted file mode 100644
index 91c01cc234..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.c
+++ /dev/null
@@ -1,334 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_cdc_msc_wrapper.c
- * @brief USB composite functions.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_cdc_class.h"
-#include "usb_dev_msc_class.h"
-#include "usb_dev_cdc_msc_wrapper.h"
-#include "usb_dev_desc.h"
-#include "usb_dev_stdreq.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CLASS LL USB Device Class
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CDC_MSC_COMPOSITE USB Device CDC MSC Composite
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-void usb_dev_msc_cdc_init(void *pdev);
-void usb_dev_msc_cdc_deinit(void *pdev);
-uint8_t usb_dev_msc_cdc_setup(void *pdev, USB_SETUP_REQ *req);
-void usb_dev_msc_cdc_datain(void *pdev, uint8_t epnum);
-void usb_dev_msc_cdc_dataout(void *pdev, uint8_t epnum);
-uint8_t *usb_dev_msc_cdc_getcfgdesc(uint16_t *length);
-uint8_t usb_dev_msc_cdc_sof(void *pdev);
-void usb_dev_msc_cdc_ctrlep_rxready(void *pdev);
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-usb_dev_class_func usb_dev_composite_cbk = {
- &usb_dev_msc_cdc_init,
- &usb_dev_msc_cdc_deinit,
- &usb_dev_msc_cdc_setup,
- NULL,
- &usb_dev_msc_cdc_ctrlep_rxready,
- &usb_dev_msc_cdc_getcfgdesc,
- &usb_dev_msc_cdc_sof,
- &usb_dev_msc_cdc_datain,
- &usb_dev_msc_cdc_dataout,
- NULL,
- NULL,
-};
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-__USB_ALIGN_BEGIN static uint8_t usb_dev_msc_cdc_cfgdesc[USB_MSC_CDC_CONFIG_DESC_SIZ] = {
- 0x09, /* bLength: Configuration Descriptor size */
- USB_CFG_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */
- USB_MSC_CDC_CONFIG_DESC_SIZ, /* wTotalLength: Bytes returned */
- 0x00,
- 0x03, /* bNumInterfaces: 2 interface */
- 0x01, /* bConfigurationValue: Configuration value */
- 0x00, /* iConfiguration: Index of string descriptor describing the configuration */
- 0xC0, /* bmAttributes: bus powered and Support Remote Wake-up */
- 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */
-
- /* IAD for CDC configuration descriptor */
- 0x08, /* bLength */
- 0x0B, /* bDescriptorType */
- 0x00, /* bFirstInterface */
- 0x02, /* bInterfaceCount */
- 0x02, /* bFunctionClass */
- 0x02, /* bFunctionSubClass */
- 0x01, /* bFunctionProtocol */
- 0x00, /* iFunction (Index of string descriptor describing this function) */
- /* CDC configuration descriptor */
- /* interface descriptor */
- 0x09, /* bLength: Interface Descriptor size */
- 0x04, /* bDescriptorType: Interface */
- 0x00, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x01, /* bNumEndpoints: One endpoints used */
- 0x02, /* bInterfaceClass: Communication Interface Class */
- 0x02, /* bInterfaceSubClass: Abstract Control Model */
- 0x01, /* bInterfaceProtocol: Common AT commands */
- 0x00, /* iInterface: */
- /* Header Functional Descriptor */
- 0x05, /* bLength: Endpoint Descriptor size */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x00, /* bDescriptorSubtype: Header Func Desc */
- 0x10, /* bcdCDC: spec release number */
- 0x01,
- /* Call Management Functional Descriptor */
- 0x05, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x01, /* bDescriptorSubtype: Call Management Func Desc */
- 0x00, /* bmCapabilities: D0+D1 */
- 0x01, /* bDataInterface: 1 */
- /* ACM Functional Descriptor */
- 0x04, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x02, /* bDescriptorSubtype: Abstract Control Management desc */
- 0x02, /* bmCapabilities */
- /* Union Functional Descriptor */
- 0x05, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x06, /* bDescriptorSubtype: Union func desc */
- 0x00, /* bMasterInterface: Communication class interface */
- 0x01, /* bSlaveInterface0: Data Class Interface */
- /* Endpoint 2 Descriptor */
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
- CDC_CMD_EP, /* bEndpointAddress */
- 0x03, /* bmAttributes: Interrupt */
- LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */
- HIBYTE(CDC_CMD_PACKET_SIZE),
- 0xFF, /* bInterval: */
- /* Data class interface descriptor */
- 0x09, /* bLength: Endpoint Descriptor size */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */
- 0x01, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x02, /* bNumEndpoints: Two endpoints used */
- 0x0A, /* bInterfaceClass: CDC */
- 0x00, /* bInterfaceSubClass: */
- 0x00, /* bInterfaceProtocol: */
- 0x00, /* iInterface: */
- /* Endpoint OUT Descriptor */
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
- CDC_OUT_EP, /* bEndpointAddress */
- 0x02, /* bmAttributes: Bulk */
- LOBYTE(MAX_CDC_PACKET_SIZE), /* wMaxPacketSize: */
- HIBYTE(MAX_CDC_PACKET_SIZE),
- 0x00, /* bInterval: ignore for Bulk transfer */
- /* Endpoint IN Descriptor */
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
- CDC_IN_EP, /* bEndpointAddress */
- 0x02, /* bmAttributes: Bulk */
- LOBYTE(MAX_CDC_PACKET_SIZE), /* wMaxPacketSize: */
- HIBYTE(MAX_CDC_PACKET_SIZE),
- 0x00,
-
- /* Mass Storage interface ********************/
- 0x09, /* bLength: Interface Descriptor size */
- 0x04, /* bDescriptorType: */
- 0x02, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x02, /* bNumEndpoints*/
- 0x08, /* bInterfaceClass: MSC Class */
- 0x06, /* bInterfaceSubClass : SCSI transparent*/
- 0x50, /* nInterfaceProtocol */
- 0x05, /* iInterface: */
- /* Mass Storage Endpoints ********************/
- 0x07, /* Endpoint descriptor length = 7 */
- 0x05, /* Endpoint descriptor type */
- MSC_IN_EP, /* Endpoint address (IN, address 1) */
- 0x02, /* Bulk endpoint type */
- LOBYTE(MSC_MAX_PACKET),
- HIBYTE(MSC_MAX_PACKET),
- 0x00, /* Polling interval in milliseconds */
-
- 0x07, /* Endpoint descriptor length = 7 */
- 0x05, /* Endpoint descriptor type */
- MSC_OUT_EP, /* Endpoint address (OUT, address 1) */
- 0x02, /* Bulk endpoint type */
- LOBYTE(MSC_MAX_PACKET),
- HIBYTE(MSC_MAX_PACKET),
- 0x00 /* Polling interval in milliseconds*/
-} ;
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @brief Initialize the composite device of MSC-HID interface
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_dev_msc_cdc_init(void *pdev)
-{
- usb_dev_cdc_init(pdev);
- usb_dev_msc_init(pdev);
-}
-
-/**
- * @brief de-initialize the composite device of MSC-HID interface
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_dev_msc_cdc_deinit(void *pdev)
-{
- usb_dev_cdc_deinit(pdev);
- usb_dev_msc_deinit(pdev);
-}
-
-/**
- * @brief process the setup requests
- * @param [in] pdev device instance
- * @param [in] req setup request
- * @retval status
- */
-uint8_t usb_dev_msc_cdc_setup(void *pdev, USB_SETUP_REQ *req)
-{
- uint8_t u8Res = USB_DEV_OK;
- switch (req->bmRequest & USB_REQ_RECIPIENT_MASK) {
- case USB_REQ_RECIPIENT_INTERFACE:
- if (req->wIndex == 0x02U) {
- u8Res = usb_dev_msc_setup(pdev, req);
- } else {
- u8Res = usb_dev_cdc_setup(pdev, req);
- }
- break;
-
- case USB_REQ_RECIPIENT_ENDPOINT:
- if (req->wIndex == CDC_IN_EP) {
- u8Res = usb_dev_cdc_setup(pdev, req);
- } else {
- u8Res = usb_dev_msc_setup(pdev, req);
- }
- break;
- default:
- break;
- }
- return u8Res;
-}
-
-/**
- * @brief Data received on control endpoint
- * @param [in] pdev device device instance
- * @retval None
- */
-void usb_dev_msc_cdc_ctrlep_rxready(void *pdev)
-{
- usb_dev_cdc_ctrlep_rxready(pdev);
-}
-
-/**
- * @brief process the sof
- * @param [in] pdev device instance
- * @retval status
- */
-uint8_t usb_dev_msc_cdc_sof(void *pdev)
-{
- return usb_dev_cdc_sof(pdev);
-}
-
-/**
- * @brief process data IN DATA
- * @param [in] pdev device instance
- * @param [in] epnum endpoint index
- * @retval None
- */
-void usb_dev_msc_cdc_datain(void *pdev, uint8_t epnum)
-{
- if (epnum == (uint8_t)(MSC_IN_EP & ((uint8_t)~0x80U))) {
- usb_dev_msc_datain(pdev, epnum);
- } else {
- usb_dev_cdc_datain(pdev, epnum);
- }
-}
-
-/**
- * @brief process data OUT DATA
- * @param [in] pdev device instance
- * @param [in] epnum endpoint index
- * @retval None
- */
-void usb_dev_msc_cdc_dataout(void *pdev, uint8_t epnum)
-{
- if (epnum == (uint8_t)(MSC_OUT_EP & ((uint8_t)~0x80U))) {
- usb_dev_msc_dataout(pdev, epnum);
- } else {
- usb_dev_cdc_dataout(pdev, epnum);
- }
-}
-
-/**
- * @brief get the configuration descriptor
- * @param [in] length length of data butter in bytes
- * @retval buffer pointer
- */
-uint8_t *usb_dev_msc_cdc_getcfgdesc(uint16_t *length)
-{
- *length = (uint16_t)sizeof(usb_dev_msc_cdc_cfgdesc);
- return usb_dev_msc_cdc_cfgdesc;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.h
deleted file mode 100644
index 7aeacb4bc7..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_cdc_msc_wrapper.h
- * @brief header file for the usb_dev_cdc_msc_wrapper.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_DEV_CDC_MSC_WRAPPER_H__
-#define __USB_DEV_CDC_MSC_WRAPPER_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_ctrleptrans.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CDC_MSC_COMPOSITE
- * @{
- */
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#define USB_MSC_CDC_CONFIG_DESC_SIZ (USB_CDC_CONFIG_DESC_SIZ - 9U + USB_MSC_CONFIG_DESC_SIZ)
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-extern usb_dev_class_func usb_dev_composite_cbk;
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_DEV_CDC_MSC_WRAPPER_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/custom_hid/usb_dev_custom_hid_class.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/custom_hid/usb_dev_custom_hid_class.c
deleted file mode 100644
index 1f46388100..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/custom_hid/usb_dev_custom_hid_class.c
+++ /dev/null
@@ -1,380 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_custom_hid_class.c
- * @brief CUSTOM HID core functions.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_custom_hid_class.h"
-#include "usb_dev_desc.h"
-#include "usb_dev_stdreq.h"
-#include "usb_dev_driver.h"
-#include "usb_bsp.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CUSTOM_HID USB Device Custom HID
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-void usb_dev_hid_init(void *pdev);
-void usb_dev_hid_deinit(void *pdev);
-uint8_t usb_dev_hid_setup(void *pdev, USB_SETUP_REQ *req);
-uint8_t *usb_dev_hid_getcfgdesc(uint16_t *length);
-void usb_dev_hid_datain(void *pdev, uint8_t epnum);
-void usb_dev_hid_dataout(void *pdev, uint8_t epnum);
-void usb_dev_hid_ctrlep_rxready(void *pdev);
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-uint8_t Report_buf[64];
-uint8_t Send_Buf[64];
-static __IO uint32_t IsReportAvailable = 0UL;
-
-usb_dev_class_func class_customhid_cbk = {
- &usb_dev_hid_init,
- &usb_dev_hid_deinit,
- &usb_dev_hid_setup,
- NULL,
- &usb_dev_hid_ctrlep_rxready,
- &usb_dev_hid_getcfgdesc,
- NULL,
- &usb_dev_hid_datain,
- &usb_dev_hid_dataout,
- NULL,
- NULL,
-};
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-__USB_ALIGN_BEGIN static uint32_t USB_DEV_HID_AltSet = 0UL;
-
-__USB_ALIGN_BEGIN static uint32_t USB_DEV_HID_Protocol = 0UL;
-
-__USB_ALIGN_BEGIN static uint32_t USB_DEV_HID_IdleState = 0UL;
-
-__USB_ALIGN_BEGIN static uint8_t usb_dev_hid_cfgdesc[USB_CUSTOM_HID_CONFIG_DESC_SIZ] = {
- 0x09,
- USB_CFG_DESCRIPTOR_TYPE,
- USB_CUSTOM_HID_CONFIG_DESC_SIZ,
- 0x00,
- 0x01,
- 0x01,
- 0x00,
- 0xC0,
- 0x32,
-
- 0x09,
- USB_INTERFACE_DESCRIPTOR_TYPE,
- 0x00,
- 0x00,
- 0x02,
- 0x03,
- 0x00,
- 0x00,
- 0x00,
-
- 0x09,
- CUSTOM_HID_DESCRIPTOR_TYPE,
- 0x10,
- 0x01,
- 0x21,
- 0x01,
- 0x22,
- CUSTOM_HID_REPORT_DESC_SIZE,
- 0x00,
-
- 0x07,
- USB_ENDPOINT_DESCRIPTOR_TYPE,
- HID_IN_EP,
- 0x03,
- HID_IN_PACKET,
- 0x00,
- 0x0A,
-
- 0x07,
- USB_ENDPOINT_DESCRIPTOR_TYPE,
-
- HID_OUT_EP,
- 0x03,
- HID_OUT_PACKET,
- 0x00,
- 0x0A,
-} ;
-
-__USB_ALIGN_BEGIN static uint8_t CUSTOM_HID_ReportDesc[CUSTOM_HID_REPORT_DESC_SIZE] = {
- 0x05, 0x8C, 0x09, 0x06, 0xA1, 0x01, 0x09, 0x06, 0x15, 0x00, 0x26, 0x00,
- 0xFF, 0x75, 0x08, 0x95, 0x40, 0x91, 0x82, 0x09, 0x06, 0x15, 0x00, 0x26,
- 0x00, 0xFF, 0x75, 0x08, 0x95, 0X40, 0x81, 0x82, 0xC0
-};
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @brief Initialize the HID application
- * @param [in] pdev Device instance
- * @retval None
- */
-void usb_dev_hid_init(void *pdev)
-{
- usb_opendevep(pdev, HID_IN_EP, HID_IN_PACKET, EP_TYPE_INTR);
- usb_opendevep(pdev, HID_OUT_EP, HID_OUT_PACKET, EP_TYPE_INTR);
- usb_readytorx(pdev, HID_OUT_EP, Report_buf, HID_OUT_PACKET);
- usb_devepstatusset(pdev, HID_OUT_EP, USB_EP_RX_VALID);
-}
-
-/**
- * @brief Deinitialize the HID application
- * @param [in] pdev Device instance
- * @retval None
- */
-void usb_dev_hid_deinit(void *pdev)
-{
- usb_shutdevep(pdev, HID_IN_EP);
- usb_shutdevep(pdev, HID_OUT_EP);
-}
-
-/**
- * @brief Handle the setup requests
- * @param [in] pdev Device instance
- * @param [in] req usb requests
- * @retval status
- */
-uint8_t usb_dev_hid_setup(void *pdev, USB_SETUP_REQ *req)
-{
- uint8_t hid_report_length;
- uint16_t len = 0U;
- uint8_t *pbuf = NULL;
- uint8_t u8Ret = USB_DEV_OK;
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK) {
- case USB_REQ_TYPE_CLASS :
- switch (req->bRequest) {
- case CUSTOM_HID_REQ_SET_PROTOCOL:
- USB_DEV_HID_Protocol = (uint8_t)(req->wValue);
- break;
- case CUSTOM_HID_REQ_GET_PROTOCOL:
- usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_HID_Protocol, 1U);
- break;
- case CUSTOM_HID_REQ_SET_IDLE:
- USB_DEV_HID_IdleState = (uint8_t)(req->wValue >> 8);
- break;
- case CUSTOM_HID_REQ_GET_IDLE:
- usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_HID_IdleState, 1U);
- break;
- case CUSTOM_HID_REQ_SET_REPORT:
- IsReportAvailable = 1UL;
- hid_report_length = (uint8_t)(req->wLength);
- usb_ctrldatarx(pdev, Report_buf, (uint16_t)hid_report_length);
- break;
- default:
- usb_ctrlerr(pdev);
- u8Ret = USB_DEV_FAIL;
- break;
- }
- break;
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest) {
- case USB_REQ_GET_DESCRIPTOR:
- if (req->wValue >> 8U == CUSTOM_HID_REPORT_DESC) {
- len = LL_MIN((uint16_t)CUSTOM_HID_REPORT_DESC_SIZE, req->wLength);
- pbuf = (uint8_t *)CUSTOM_HID_ReportDesc;
- } else if (req->wValue >> 8U == CUSTOM_HID_DESCRIPTOR_TYPE) {
- pbuf = (uint8_t *)usb_dev_hid_cfgdesc + 0x12U;
- len = LL_MIN(USB_CUSTOM_HID_DESC_SIZ, req->wLength);
- } else {
- ;
- }
-
- usb_ctrldatatx(pdev, pbuf, len);
- break;
- case USB_REQ_GET_INTERFACE :
- usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_HID_AltSet, 1U);
- break;
- case USB_REQ_SET_INTERFACE :
- USB_DEV_HID_AltSet = (uint8_t)(req->wValue);
- break;
- default:
- break;
- }
- break;
- default:
- break;
- }
- return u8Ret;
-}
-
-/**
- * @brief Send HID Report
- * @param [in] pdev Device instance
- * @param [in] report pointer to report
- * @param [in] len the length in bytes would be sent
- * @retval status
- */
-uint8_t usb_dev_hid_txreport(usb_core_instance *pdev, uint8_t *report, uint16_t len)
-{
- if (pdev->dev.device_cur_status == USB_DEV_CONFIGURED) {
- usb_deveptx(pdev, HID_IN_EP, report, (uint32_t)len);
- }
- return USB_DEV_OK;
-}
-
-/**
- * @brief return configuration descriptor
- * @param [in] length length of configuration descriptor in bytes
- * @retval pointer to configuration descriptor buffer
- */
-uint8_t *usb_dev_hid_getcfgdesc(uint16_t *length)
-{
- *length = (uint8_t)sizeof(usb_dev_hid_cfgdesc);
- return usb_dev_hid_cfgdesc;
-}
-
-/**
- * @brief processing for data in
- * @param [in] pdev Device instance
- * @param [in] epnum endpoint index
- * @retval None
- */
-void usb_dev_hid_datain(void *pdev, uint8_t epnum)
-{
- usb_flsdevep(pdev, HID_IN_EP);
-
- if (epnum == (HID_IN_EP & (uint8_t)~0x80U)) {
- PrevXferDone = 1U;
- }
-}
-
-/**
- * @brief processing for data out
- * @param [in] pdev Device instance
- * @param [in] epnum endpoint index
- * @retval None
- */
-void usb_dev_hid_dataout(void *pdev, uint8_t epnum)
-{
- if (epnum == HID_OUT_EP) {
- switch (Report_buf[0]) {
- case 1: /* Led 1 */
- if (Report_buf[1U] == 0U) {
- /* RED LED on */
- BSP_LED_Off(LED_RED);
- } else {
- /* RED LED off */
- BSP_LED_On(LED_RED);
- }
- break;
-
- case 2: /* Led 2 */
- if (Report_buf[1U] == 0U) {
- /* BLUE LED on */
- BSP_LED_Off(LED_BLUE);
- } else {
- /* BLUE LED off */
- BSP_LED_On(LED_BLUE);
- }
- break;
- default:
- BSP_LED_Off(LED_RED);
- BSP_LED_Off(LED_BLUE);
- break;
- }
- }
-
- usb_readytorx(pdev, HID_OUT_EP, Report_buf, 2U);
- usb_devepstatusset(pdev, HID_OUT_EP, USB_EP_RX_VALID);
- usb_deveptx(pdev, HID_IN_EP, Report_buf, 2);
-}
-
-/**
- * @brief processing for request data in control endpoint
- * @param [in] pdev Device instance
- * @retval None
- */
-void usb_dev_hid_ctrlep_rxready(void *pdev)
-{
- if (IsReportAvailable == 1UL) {
- IsReportAvailable = 0UL;
- switch (Report_buf[0]) {
- case 1: /* Led 1 */
- if (Report_buf[1] == 0U) {
- /* RED LED on */
- BSP_LED_Off(LED_RED);
- } else {
- /* RED LED off */
- BSP_LED_On(LED_RED);
- }
- break;
-
- case 2: /* Led 2 */
- if (Report_buf[1] == 0U) {
- /* BLUE LED on */
- BSP_LED_Off(LED_BLUE);
- } else {
- /* BLUE LED off */
- BSP_LED_On(LED_BLUE);
- }
- break;
- default:
- BSP_LED_Off(LED_RED);
- BSP_LED_Off(LED_BLUE);
- break;
- }
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/custom_hid/usb_dev_custom_hid_class.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/custom_hid/usb_dev_custom_hid_class.h
deleted file mode 100644
index daa5d5b7ed..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/custom_hid/usb_dev_custom_hid_class.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_custom_hid_class.h
- * @brief Head file for usb_dev_custom_hid_class.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_DEV_CUSTOMHID_HID_CORE_H__
-#define __USB_DEV_CUSTOMHID_HID_CORE_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_ctrleptrans.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CUSTOM_HID
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#define CUSTOM_HID_REPORT_DESC_SIZE (0x21)
-
-#define USB_CUSTOM_HID_CONFIG_DESC_SIZ (41U)
-#define USB_CUSTOM_HID_DESC_SIZ (9U)
-
-#define CUSTOM_HID_DESCRIPTOR_TYPE (0x21U)
-#define CUSTOM_HID_REPORT_DESC (0x22U)
-
-#define CUSTOM_HID_REQ_SET_PROTOCOL (0x0BU)
-#define CUSTOM_HID_REQ_GET_PROTOCOL (0x03U)
-
-#define CUSTOM_HID_REQ_SET_IDLE (0x0AU)
-#define CUSTOM_HID_REQ_GET_IDLE (0x02U)
-
-#define CUSTOM_HID_REQ_SET_REPORT (0x09U)
-#define CUSTOM_HID_REQ_GET_REPORT (0x01U)
-
-#define LED1_REPORT_ID (0x01U)
-#define LED1_REPORT_COUNT (0x01U)
-
-#define LED2_REPORT_ID (0x02U)
-#define LED2_REPORT_COUNT (0x01U)
-
-#define LED3_REPORT_ID (0x03U)
-#define LED3_REPORT_COUNT (0x01U)
-
-#define LED4_REPORT_ID (0x04U)
-#define LED4_REPORT_COUNT (0x01U)
-
-#define KEY_REPORT_ID (0x05U)
-#define TAMPER_REPORT_ID (0x06U)
-#define ADC_REPORT_ID (0x07U)
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-extern usb_dev_class_func class_customhid_cbk;
-extern uint8_t Report_buf[64];
-extern uint8_t Send_Buf[64];
-extern uint8_t usb_dev_hid_txreport(usb_core_instance *pdev, uint8_t *report, uint16_t len);
-
-/* HID Device library callbacks */
-extern void usb_dev_hid_init(void *pdev);
-extern void usb_dev_hid_deinit(void *pdev);
-extern uint8_t usb_dev_hid_setup(void *pdev, USB_SETUP_REQ *req);
-extern uint8_t *usb_dev_hid_getcfgdesc(uint16_t *length);
-extern void usb_dev_hid_datain(void *pdev, uint8_t epnum);
-extern void usb_dev_hid_dataout(void *pdev, uint8_t epnum);
-extern void usb_dev_hid_ctrlep_rxready(void *pdev);
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_DEV_CUSTOMHID_HID_CORE_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_cdc_composite/usb_dev_hid_cdc_wrapper.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_cdc_composite/usb_dev_hid_cdc_wrapper.c
deleted file mode 100644
index 51de72fb09..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_cdc_composite/usb_dev_hid_cdc_wrapper.c
+++ /dev/null
@@ -1,362 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_hid_cdc_wrapper.c
- * @brief HID CDC composite functions.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_custom_hid_class.h"
-#include "usb_dev_cdc_class.h"
-#include "usb_dev_hid_cdc_wrapper.h"
-#include "usb_dev_desc.h"
-#include "usb_dev_stdreq.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_HID_CDC_COMPOSITE USB Device HID CDC Composite
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#define USB_COMPOSITE_CFGDESC_SIZE (USB_CUSTOM_HID_CONFIG_DESC_SIZ - 9U + USB_CDC_CONFIG_DESC_SIZ + 8U)
-
-#define HID_INTERFACE (0x0U)
-#define CDC_COM_INTERFACE (0x1U)
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-void usb_dev_composite_init(void *pdev);
-void usb_dev_composite_deinit(void *pdev);
-uint8_t usb_dev_composite_setup(void *pdev, USB_SETUP_REQ *req);
-void usb_dev_composite_rxready(void *pdev);
-void usb_dev_composite_datain(void *pdev, uint8_t epnum);
-void usb_dev_composite_dataout(void *pdev, uint8_t epnum);
-uint8_t usb_dev_composite_sof(void *pdev);
-uint8_t *usb_dev_composite_getcfgdesc(uint16_t *length);
-
-/*******************************************************************************
- * Global variable definitions
- ******************************************************************************/
-usb_dev_class_func class_composite_cbk = {
- &usb_dev_composite_init,
- &usb_dev_composite_deinit,
- &usb_dev_composite_setup,
- NULL,
- &usb_dev_composite_rxready,
- &usb_dev_composite_getcfgdesc,
- &usb_dev_composite_sof,
- &usb_dev_composite_datain,
- &usb_dev_composite_dataout,
- NULL,
- NULL,
-};
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-__USB_ALIGN_BEGIN static uint8_t usb_dev_composite_cfgdesc[USB_COMPOSITE_CFGDESC_SIZE] = {
- 0x09, /* bLength: Configuration Descriptor size */
- USB_CFG_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */
- USB_COMPOSITE_CFGDESC_SIZE, /* wTotalLength: Bytes returned */
- 0x00,
- 0x03, /* bNumInterfaces: 3 interfaces (2 for CDC, 1 for HID) */
- 0x01, /* bConfigurationValue: Configuration value */
- 0x00, /* iConfiguration: Index of string descriptor describing the configuration */
- 0xE0, /* bmAttributes: bus powered and Support Remote Wake-up */
- 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */
- /* 09 */
- /************** Descriptor of HID interface ****************/
- 0x09, /* bLength: Interface Descriptor size */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface descriptor type */
- HID_INTERFACE, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x02, /* bNumEndpoints */
- 0x03, /* bInterfaceClass: HID */
- 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */
- 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */
- 0x00, /* iInterface: Index of string descriptor */
- /* 18 */
- /******************** Descriptor of HID ********************/
- 0x09, /* bLength: HID Descriptor size */
- CUSTOM_HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID*/
- 0x11, /* bcdHID: HID Class Spec release number */
- 0x01,
- 0x00, /* bCountryCode: Hardware target country */
- 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */
- 0x22, /* bDescriptorType */
- CUSTOM_HID_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */
- 0x00,
- /* 27 */
- /******************** Descriptor of HID endpoint ********************/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */
- HID_IN_EP, /* bEndpointAddress: Endpoint Address (IN) */
- 0x03, /* bmAttributes: Interrupt endpoint */
- HID_IN_PACKET, /* wMaxPacketSize: 64 Byte max */
- 0x00,
- 0x0A, /* bInterval: Polling Interval (10 ms) */
- /* 34 */
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */
- HID_OUT_EP, /* bEndpointAddress: Endpoint Address (IN) */
- 0x03, /* bmAttributes: Interrupt endpoint */
- HID_OUT_PACKET, /* wMaxPacketSize: 64 Byte max */
- 0x00,
- 0x0A, /* bInterval: Polling Interval (10 ms) */
- /* 41 */
- /******** IAD should be positioned just before the CDC interfaces *******/
- 0x08, /* bLength */
- 0x0B, /* bDescriptorType */
- 0x01, /* bFirstInterface */
- 0x02, /* bInterfaceCount */
- 0x02, /* bFunctionClass */
- 0x02, /* bFunctionSubClass */
- 0x01, /* bFunctionProtocol */
- 0x00, /* iFunction (Index of string descriptor describing this function) */
- /*49*/
- /*Interface Descriptor */
- 0x09, /* bLength: Interface Descriptor size */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */
- CDC_COM_INTERFACE, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x01, /* bNumEndpoints: One endpoints used */
- 0x02, /* bInterfaceClass: Communication Interface Class */
- 0x02, /* bInterfaceSubClass: Abstract Control Model */
- 0x01, /* bInterfaceProtocol: Common AT commands */
- 0x01, /* iInterface: */
- /*58*/
- /*Header Functional Descriptor*/
- 0x05, /* bLength: Endpoint Descriptor size */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x00, /* bDescriptorSubtype: Header Func Desc */
- 0x10, /* bcdCDC: spec release number */
- 0x01,
- /*63*/
- /*Call Management Functional Descriptor*/
- 0x05, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x01, /* bDescriptorSubtype: Call Management Func Desc */
- 0x00, /* bmCapabilities: D0+D1 */
- 0x02, /* bDataInterface: 2 */
- /*68*/
- /*ACM Functional Descriptor*/
- 0x04, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x02, /* bDescriptorSubtype: Abstract Control Management desc */
- 0x02, /* bmCapabilities */
- /*72*/
- /*Union Functional Descriptor*/
- 0x05, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x06, /* bDescriptorSubtype: Union func desc */
- 0x01, /* bMasterInterface: Communication class interface */
- 0x02, /* bSlaveInterface0: Data Class Interface */
- /*77*/
- /*Endpoint 2 Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
- CDC_CMD_EP, /* bEndpointAddress */
- 0x03, /* bmAttributes: Interrupt */
- LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */
- HIBYTE(CDC_CMD_PACKET_SIZE),
- 0xFF, /* bInterval: */
- /*84*/
- /*---------------------------------------------------------------------------*/
-
- /*Data class interface descriptor*/
- 0x09, /* bLength: Endpoint Descriptor size */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */
- 0x02, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x02, /* bNumEndpoints: Two endpoints used */
- 0x0A, /* bInterfaceClass: CDC */
- 0x00, /* bInterfaceSubClass: */
- 0x00, /* bInterfaceProtocol: */
- 0x00, /* iInterface: */
- /*93*/
- /*Endpoint OUT Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
- CDC_OUT_EP, /* bEndpointAddress */
- 0x02, /* bmAttributes: Bulk */
- LOBYTE(MAX_CDC_PACKET_SIZE), /* wMaxPacketSize: */
- HIBYTE(MAX_CDC_PACKET_SIZE),
- 0x00, /* bInterval: ignore for Bulk transfer */
- /*100*/
- /*Endpoint IN Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
- CDC_IN_EP, /* bEndpointAddress */
- 0x02, /* bmAttributes: Bulk */
- LOBYTE(MAX_CDC_PACKET_SIZE), /* wMaxPacketSize: */
- HIBYTE(MAX_CDC_PACKET_SIZE),
- 0x00, /* bInterval */
- /*107*/
-} ;
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @brief Initialize the composite app
- * @param [in] pdev Device instance
- * @retval None
- */
-void usb_dev_composite_init(void *pdev)
-{
- usb_dev_hid_init(pdev);
- usb_dev_cdc_init(pdev);
-}
-
-/**
- * @brief Deinitialize the composite app
- * @param [in] pdev Device instance
- * @retval None
- */
-void usb_dev_composite_deinit(void *pdev)
-{
- usb_dev_hid_deinit(pdev);
- usb_dev_cdc_deinit(pdev);
-}
-
-/**
- * @brief Handle the setup requests
- * @param [in] pdev Device instance
- * @param [in] req usb requests
- * @retval status
- */
-uint8_t usb_dev_composite_setup(void *pdev, USB_SETUP_REQ *req)
-{
- uint8_t u8Res = USB_DEV_OK;
- switch (req->bmRequest & USB_REQ_RECIPIENT_MASK) {
- case USB_REQ_RECIPIENT_INTERFACE:
- if (req->wIndex == HID_INTERFACE) {
- u8Res = usb_dev_hid_setup(pdev, req);
- } else {
- u8Res = usb_dev_cdc_setup(pdev, req);
- }
- break;
-
- case USB_REQ_RECIPIENT_ENDPOINT:
- if (req->wIndex == HID_IN_EP) {
- u8Res = usb_dev_hid_setup(pdev, req);
- } else {
- u8Res = usb_dev_cdc_setup(pdev, req);
- }
- break;
- default:
- break;
- }
- return u8Res;
-}
-
-/**
- * @brief get the configuration descriptor and return the its pointer
- * @param [in] length length of configuration descriptor
- * @retval the pointer of configuration descriptor buffer
- */
-uint8_t *usb_dev_composite_getcfgdesc(uint16_t *length)
-{
- *length = (uint16_t)sizeof(usb_dev_composite_cfgdesc);
- return usb_dev_composite_cfgdesc;
-}
-
-/**
- * @brief processing for data in
- * @param [in] pdev Device instance
- * @param [in] epnum endpoint index
- * @retval None
- */
-void usb_dev_composite_datain(void *pdev, uint8_t epnum)
-{
- if (epnum == ((uint8_t)CDC_IN_EP & ((uint8_t)~0x80U))) {
- usb_dev_cdc_datain(pdev, epnum);
- } else {
- usb_dev_hid_datain(pdev, epnum);
- }
-}
-
-/**
- * @brief processing for data out
- * @param [in] pdev Device instance
- * @param [in] epnum endpoint index
- * @retval None
- */
-void usb_dev_composite_dataout(void *pdev, uint8_t epnum)
-{
- if (epnum == ((uint8_t)CDC_OUT_EP & (uint8_t)~0x80U)) {
- usb_dev_cdc_dataout(pdev, epnum);
- } else {
- usb_dev_hid_dataout(pdev, epnum);
- }
-}
-
-/**
- * @brief processing for sof
- * @param [in] pdev Device instance
- * @retval status
- */
-uint8_t usb_dev_composite_sof(void *pdev)
-
-{
- return (usb_dev_cdc_sof(pdev));
-}
-
-/**
- * @brief processing for rxready of control endpoint
- * @param [in] pdev Device instance
- * @retval None
- */
-void usb_dev_composite_rxready(void *pdev)
-{
- usb_dev_cdc_ctrlep_rxready(pdev);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_cdc_composite/usb_dev_hid_cdc_wrapper.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_cdc_composite/usb_dev_hid_cdc_wrapper.h
deleted file mode 100644
index a7acd98829..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_cdc_composite/usb_dev_hid_cdc_wrapper.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_hid_cdc_wrapper.h
- * @brief Head file for usb_dev_hid_cdc_wrapper.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_DEV_HID_CDC_WRAPPER_H_
-#define __USB_DEV_HID_CDC_WRAPPER_H_
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_ctrleptrans.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_HID_CDC_COMPOSITE
- * @{
- */
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-extern usb_dev_class_func class_composite_cbk;
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_DEV_HID_CDC_WRAPPER_H_ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_keyboard/usb_dev_keyboard_class.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_keyboard/usb_dev_keyboard_class.c
deleted file mode 100644
index 5857b0331b..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_keyboard/usb_dev_keyboard_class.c
+++ /dev/null
@@ -1,330 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_keyboard_class.c
- * @brief HID keyboard functions.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_keyboard_class.h"
-#include "usb_dev_desc.h"
-#include "usb_dev_stdreq.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_HID_KEYBOARD USB Device HID Keyboard
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-void usb_dev_keyboard_init(void *pdev);
-void usb_dev_keyboard_deinit(void *pdev);
-uint8_t usb_dev_keyboard_setup(void *pdev, USB_SETUP_REQ *req);
-uint8_t *usb_dev_keyboard_getcfgdesc(uint16_t *length);
-void usb_dev_keyboard_datain(void *pdev, uint8_t epnum);
-void usb_dev_keyboard_dataout(void *pdev, uint8_t epnum);
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-usb_dev_class_func usb_dev_keyboard_cbk = {
- &usb_dev_keyboard_init,
- &usb_dev_keyboard_deinit,
- &usb_dev_keyboard_setup,
- NULL,
- NULL,
- &usb_dev_keyboard_getcfgdesc,
- NULL,
- &usb_dev_keyboard_datain,
- &usb_dev_keyboard_dataout,
- NULL,
- NULL
-};
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-__USB_ALIGN_BEGIN static uint32_t USB_DEV_KEYBOARD_AltSet = 0UL;
-__USB_ALIGN_BEGIN static uint32_t USB_DEV_KEYBOARD_Protocol = 0UL;
-__USB_ALIGN_BEGIN static uint32_t USB_DEV_KEYBOARD_IdleState = 0UL;
-
-/* USB HID device Configuration Descriptor */
-__USB_ALIGN_BEGIN static uint8_t USB_DEV_KEYBOARD_CfgDesc[KEYBOARD_CFGDESC_SIZE] = {
- 0x09, /* bLength: Configuration Descriptor size */
- USB_CFG_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */
- KEYBOARD_CFGDESC_SIZE, /* wTotalLength: Bytes returned */
- 0x00,
- 0x01, /* bNumInterfaces: 1 interface */
- 0x01, /* bConfigurationValue: Configuration value */
- 0x00, /* iConfiguration: Index of string descriptor describing the configuration */
- 0x80, /* bmAttributes: bus powered and Support Remote Wake-up */
- 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus*/
- /************** Descriptor of Joystick Mouse interface ****************/
- /* 09 */
- 0x09, /* bLength: Interface Descriptor size */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface descriptor type */
- 0x00, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x02, /* bNumEndpoints */
- 0x03, /* bInterfaceClass: HID */
- 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */
- 0x01, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */
- 0x00, /* iInterface: Index of string descriptor */
- /******************** Descriptor of Joystick Mouse HID ********************/
- /* 18 */
- 0x09, /* bLength: HID Descriptor size */
- KEYBOARD_DESCRIPTOR_TYPE, /* bDescriptorType: HID */
- 0x10, /* bcdHID: HID Class Spec release number */
- 0x01,
- 0x21, /* bCountryCode: Hardware target country */
- 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */
- 0x22, /* bDescriptorType */
- KEYBOARD_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */
- 0x00,
- /******************** Descriptor of Mouse endpoint ********************/
- /* 27 */
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */
- HID_IN_EP, /* bEndpointAddress: Endpoint Address (IN) */
- 0x03, /* bmAttributes: Interrupt endpoint */
- 0x08, /* wMaxPacketSize: 4 Byte max */
- 0x00,
- 0x0A, /* bInterval: Polling Interval (10 ms)*/
- /* 34 */
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType:*/
- HID_OUT_EP, /* bEndpointAddress: Endpoint Address (IN) */
- 0x03, /* bmAttributes: Interrupt endpoint */
- HID_OUT_PACKET, /* wMaxPacketSize: 4 Byte max */
- 0x00,
- 0x0A, /* bInterval: Polling Interval (10 ms)*/
- /* 41 */
-} ;
-
-__USB_ALIGN_BEGIN static uint8_t HID_KEYBOARD_ReportDesc[KEYBOARD_REPORT_DESC_SIZE] = {
- 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */
- 0x09, 0x06, /* USAGE (Keyboard) */
- 0xA1, 0x01, /* COLLECTION (Application) */
- 0x05, 0x07, /* USAGE_PAGE (Keyboard) */
- 0x19, 0x00, /* USAGE_MINIMUM (Reserved (no event indicated)) */
- 0x29, 0x00, /* USAGE_MAXIMUM (Reserved (no event indicated)) */
- 0x15, 0x00, /* LOGICAL_MINIMUM (0) */
- 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */
- 0x95, 0x01, /* REPORT_COUNT (1) */
- 0x75, 0x08, /* REPORT_SIZE (8) */
- 0x81, 0x02, /* INPUT (Data,Var,Abs) */
- 0x95, 0x01, /* REPORT_COUNT (1) */
- 0x75, 0x08, /* REPORT_SIZE (8) */
- 0x81, 0x03, /* INPUT (Cnst,Var,Abs) */
- 0x95, 0x06, /* REPORT_COUNT (6) */
- 0x75, 0x08, /* REPORT_SIZE (8) */
- 0x15, 0x00, /* LOGICAL_MINIMUM (0) */
- 0x26, 0xFF, 0x00, /* LOGICAL_MAXIMUM (255) */
- 0x05, 0x07, /* USAGE_PAGE (Keyboard) */
- 0x19, 0x00, /* USAGE_MINIMUM (Reserved (no event indicated)) */
- 0x29, 0xE7, /* USAGE_MAXIMUM (Keyboard Right GUI) */
- 0x81, 0x00, /* INPUT (Data,Ary,Abs) */
- 0x15, 0x01, /* LOGICAL_MINIMUM (1) */
- 0x95, 0x05, /* REPORT_COUNT (5) */
- 0x75, 0x01, /* REPORT_SIZE (1) */
- 0x05, 0x08, /* USAGE_PAGE (LEDs) */
- 0x19, 0x01, /* USAGE_MINIMUM (Num Lock) */
- 0x29, 0x05, /* USAGE_MAXIMUM (Kana) */
- 0x91, 0x02, /* OUTPUT (Data,Var,Abs) */
- 0x95, 0x01, /* REPORT_COUNT (1) */
- 0x75, 0x03, /* REPORT_SIZE (3) */
- 0x91, 0x03, /* OUTPUT (Cnst,Var,Abs) */
- 0xC0 /* END_COLLECTION */
-};
-
-__IO static uint8_t u8KeyRevBuf[64];
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @brief Initialize the interface of KEYBOARD HID
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_dev_keyboard_init(void *pdev)
-{
- usb_opendevep(pdev, HID_IN_EP, 8U, EP_TYPE_INTR);
- usb_opendevep(pdev, HID_OUT_EP, HID_OUT_PACKET, EP_TYPE_INTR);
- usb_readytorx(pdev, HID_OUT_EP, (uint8_t *)u8KeyRevBuf, 64U);
- usb_devepstatusset(pdev, HID_OUT_EP, USB_EP_RX_VALID);
-}
-
-/**
- * @brief DeInitialize the interface of KEYBOARD HID
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_dev_keyboard_deinit(void *pdev)
-{
- usb_shutdevep(pdev, HID_IN_EP);
- usb_shutdevep(pdev, HID_OUT_EP);
-}
-
-/**
- * @brief Handle the KEYBOARD HID SETUP request
- * @param [in] pdev device instance
- * @param [in] req usb requests
- * @retval status
- */
-uint8_t usb_dev_keyboard_setup(void *pdev, USB_SETUP_REQ *req)
-{
- uint16_t len = 0U;
- uint8_t *pbuf = NULL;
- uint8_t u8Res = USB_DEV_OK;
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK) {
- case USB_REQ_TYPE_CLASS :
- switch (req->bRequest) {
- case KEYBOARD_REQ_SET_PROTOCOL:
- USB_DEV_KEYBOARD_Protocol = (uint8_t)(req->wValue);
- break;
- case KEYBOARD_REQ_GET_PROTOCOL:
- usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_KEYBOARD_Protocol, 1U);
- break;
- case KEYBOARD_REQ_SET_IDLE:
- USB_DEV_KEYBOARD_IdleState = (uint8_t)(req->wValue >> 8U);
- break;
- case KEYBOARD_REQ_GET_IDLE:
- usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_KEYBOARD_IdleState, 1U);
- break;
- default:
- usb_ctrlerr(pdev);
- u8Res = USB_DEV_FAIL;
- break;
- }
- break;
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest) {
- case USB_REQ_GET_DESCRIPTOR:
- if ((req->wValue >> 8U) == (uint16_t)KEYBOARD_REPORT_DESC) {
- len = (uint16_t)LL_MIN(KEYBOARD_REPORT_DESC_SIZE, req->wLength);
- pbuf = HID_KEYBOARD_ReportDesc;
- } else if ((req->wValue >> 8U) == (uint16_t)KEYBOARD_DESCRIPTOR_TYPE) {
- pbuf = USB_DEV_KEYBOARD_CfgDesc + 0x12;
- len = (uint16_t)LL_MIN(KEYBOARD_DESC_SIZE, req->wLength);
- } else {
- ;
- }
- usb_ctrldatatx(pdev, pbuf, len);
- break;
- case USB_REQ_GET_INTERFACE :
- usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_KEYBOARD_AltSet, 1U);
- break;
- case USB_REQ_SET_INTERFACE :
- USB_DEV_KEYBOARD_AltSet = (uint8_t)(req->wValue);
- break;
- default:
- break;
- }
- break;
- default:
- break;
- }
- return u8Res;
-}
-
-/**
- * @brief Send KEYBOARD HID report to the host
- * @param [in] pdev device instance
- * @param [in] report pointer to the report buffer
- * @param [in] len the length of the report buffer in bytes
- * @retval status
- */
-uint8_t usb_dev_mouse_txreport(usb_core_instance *pdev, uint8_t *report, uint16_t len)
-{
- if (pdev->dev.device_cur_status == USB_DEV_CONFIGURED) {
- usb_deveptx(pdev, HID_IN_EP, report, (uint32_t)len);
- }
- return USB_DEV_OK;
-}
-
-/**
- * @brief get the configuration descriptor
- * @param [in] length pointer data length of the configuration descriptor in bytes
- * @retval pointer of configuration descriptor buffer
- */
-uint8_t *usb_dev_keyboard_getcfgdesc(uint16_t *length)
-{
- *length = (uint16_t)sizeof(USB_DEV_KEYBOARD_CfgDesc);
- return USB_DEV_KEYBOARD_CfgDesc;
-}
-
-/**
- * @brief handle the IN data Stage
- * @param [in] pdev Device instance
- * @param [in] epnum endpoint index
- * @retval None
- */
-void usb_dev_keyboard_datain(void *pdev, uint8_t epnum)
-{
- usb_flsdevep(pdev, HID_IN_EP);
-}
-
-/**
- * @brief handle the OUT data Stage
- * @param [in] pdev Device instance
- * @param [in] epnum endpoint index
- * @retval None
- */
-void usb_dev_keyboard_dataout(void *pdev, uint8_t epnum)
-{
- usb_readytorx(pdev, HID_OUT_EP, (uint8_t *)u8KeyRevBuf, 64U);
- usb_devepstatusset(pdev, HID_OUT_EP, USB_EP_RX_VALID);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_keyboard/usb_dev_keyboard_class.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_keyboard/usb_dev_keyboard_class.h
deleted file mode 100644
index dea33977bf..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_keyboard/usb_dev_keyboard_class.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_keyboard_class.h
- * @brief Head file for usb_dev_keyboard_class.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_DEV_KEYBOARD_CLASS_H__
-#define __USB_DEV_KEYBOARD_CLASS_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_ctrleptrans.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_HID_KEYBOARD
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#define KEYBOARD_CFGDESC_SIZE (41U)
-#define KEYBOARD_DESC_SIZE (9U)
-#define KEYBOARD_REPORT_DESC_SIZE (66U)
-
-#define KEYBOARD_DESCRIPTOR_TYPE (0x21U)
-#define KEYBOARD_REPORT_DESC (0x22U)
-
-#define KEYBOARD_REQ_SET_PROTOCOL (0x0BU)
-#define KEYBOARD_REQ_GET_PROTOCOL (0x03U)
-
-#define KEYBOARD_REQ_SET_IDLE (0x0AU)
-#define KEYBOARD_REQ_GET_IDLE (0x02U)
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-extern usb_dev_class_func usb_dev_keyboard_cbk;
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-extern uint8_t usb_dev_mouse_txreport(usb_core_instance *pdev, uint8_t *report, uint16_t len);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_DEV_KEYBOARD_CLASS_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_mouse/usb_dev_mouse_class.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_mouse/usb_dev_mouse_class.c
deleted file mode 100644
index fe3fd29762..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_mouse/usb_dev_mouse_class.c
+++ /dev/null
@@ -1,346 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_mouse_class.c
- * @brief HID mouse functions.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2023-06-30 CDT Modify for variable alignment
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_mouse_class.h"
-#include "usb_dev_driver.h"
-#include "usb_dev_ctrleptrans.h"
-#include "usb_dev_stdreq.h"
-#include "usb_dev_desc.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_HID_MOUSE USB Device HID Mouse
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-void usb_dev_mouse_init(void *pdev);
-void usb_dev_mouse_deinit(void *pdev);
-uint8_t usb_dev_mouse_setup(void *pdev, USB_SETUP_REQ *req);
-uint8_t *usb_dev_mouse_getcfgdesc(uint16_t *length);
-void usb_dev_mouse_datain(void *pdev, uint8_t epnum);
-void usb_dev_mouse_dataout(void *pdev, uint8_t epnum);
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-usb_dev_class_func usb_dev_mouse_cbk = {
- &usb_dev_mouse_init,
- &usb_dev_mouse_deinit,
- &usb_dev_mouse_setup,
- NULL,
- NULL,
- &usb_dev_mouse_getcfgdesc,
- NULL,
- &usb_dev_mouse_datain,
- &usb_dev_mouse_dataout,
- NULL,
- NULL
-};
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-__USB_ALIGN_BEGIN static uint32_t USB_DEV_MOUSE_AltSet = 0UL;
-__USB_ALIGN_BEGIN static uint32_t USB_DEV_MOUSE_Protocol = 0UL;
-__USB_ALIGN_BEGIN static uint32_t USB_DEV_MOUSE_IdleState = 0UL;
-
-/* USB HID device Configuration Descriptor */
-__USB_ALIGN_BEGIN static uint8_t USB_DEV_MOUSE_CfgDesc[MOUSE_CFGDESC_SIZE] = {
- 0x09, /* bLength: Configuration Descriptor size */
- USB_CFG_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */
- MOUSE_CFGDESC_SIZE, /* wTotalLength: Bytes returned */
- 0x00,
- 0x01, /* bNumInterfaces: 1 interface */
- 0x01, /* bConfigurationValue: Configuration value */
- 0x00, /* iConfiguration: Index of string descriptor describing the configuration */
- 0x80, /* bmAttributes: bus powered and Support Remote Wake-up */
- 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */
- /************** Descriptor of Joystick Mouse interface ****************/
- /* 09 */
- 0x09, /* bLength: Interface Descriptor size */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface descriptor type */
- 0x00, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x02, /* bNumEndpoints */
- 0x03, /* bInterfaceClass: HID */
- 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */
- 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */
- 0x00, /* iInterface: Index of string descriptor */
- /******************** Descriptor of Joystick Mouse HID ********************/
- /* 18 */
- 0x09, /* bLength: HID Descriptor size */
- MOUSE_DESCRIPTOR_TYPE, /* bDescriptorType: HID */
- 0x11, /* bcdHID: HID Class Spec release number */
- 0x01,
- 0x00, /* bCountryCode: Hardware target country */
- 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */
- 0x22, /* bDescriptorType */
- MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */
- 0x00,
- /******************** Descriptor of Mouse endpoint ********************/
- /* 27 */
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */
- HID_IN_EP, /* bEndpointAddress: Endpoint Address (IN) */
- 0x03, /* bmAttributes: Interrupt endpoint */
- HID_IN_PACKET, /* wMaxPacketSize: 4 Byte max */
- 0x00,
- 0x0A, /* bInterval: Polling Interval (10 ms) */
- /* 34 */
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */
- HID_OUT_EP, /* bEndpointAddress: Endpoint Address (IN) */
- 0x03, /* bmAttributes: Interrupt endpoint */
- HID_OUT_PACKET, /* wMaxPacketSize: 4 Byte max */
- 0x00,
- 0x0A, /* bInterval: Polling Interval (10 ms) */
- /* 41 */
-} ;
-
-__USB_ALIGN_BEGIN static uint8_t HID_MOUSE_ReportDesc[MOUSE_REPORT_DESC_SIZE] = {
- 0x05, 0x01,
- 0x09, 0x02,
- 0xA1, 0x01,
- 0x09, 0x01,
-
- 0xA1, 0x00,
- 0x05, 0x09,
- 0x19, 0x01,
- 0x29, 0x03,
-
- 0x15, 0x00,
- 0x25, 0x01,
- 0x95, 0x03,
- 0x75, 0x01,
-
- 0x81, 0x02,
- 0x95, 0x01,
- 0x75, 0x05,
- 0x81, 0x01,
-
- 0x05, 0x01,
- 0x09, 0x30,
- 0x09, 0x31,
- 0x09, 0x38,
-
- 0x15, 0x81,
- 0x25, 0x7F,
- 0x75, 0x08,
- 0x95, 0x03,
-
- 0x81, 0x06,
- 0xC0, 0x09,
- 0x3C, 0x05,
- 0xFF, 0x09,
-
- 0x01, 0x15,
- 0x00, 0x25,
- 0x01, 0x75,
- 0x01, 0x95,
-
- 0x02, 0xB1,
- 0x22, 0x75,
- 0x06, 0x95,
- 0x01, 0xB1,
-
- 0x01, 0xC0
-};
-
-__USB_ALIGN_BEGIN static uint8_t u8HidRevBuf[4];
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @brief Initialize the interface of MOUSE HID
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_dev_mouse_init(void *pdev)
-{
- usb_opendevep(pdev, HID_IN_EP, HID_IN_PACKET, EP_TYPE_INTR);
- usb_opendevep(pdev, HID_OUT_EP, HID_OUT_PACKET, EP_TYPE_INTR);
- usb_readytorx(pdev, HID_OUT_EP, u8HidRevBuf, (uint16_t)(sizeof(u8HidRevBuf) / sizeof(uint8_t)));
- usb_devepstatusset(pdev, HID_OUT_EP, USB_EP_RX_VALID);
-}
-
-/**
- * @brief DeInitialize the interface of MOUSE HID
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_dev_mouse_deinit(void *pdev)
-{
- usb_shutdevep(pdev, HID_IN_EP);
- usb_shutdevep(pdev, HID_OUT_EP);
-}
-
-/**
- * @brief Handle the MOUSE HID SETUP request
- * @param [in] pdev device instance
- * @param [in] req: usb requests
- * @retval status
- */
-uint8_t usb_dev_mouse_setup(void *pdev, USB_SETUP_REQ *req)
-{
- uint16_t len = 0U;
- uint8_t *pbuf = NULL;
- uint8_t u8Res = USB_DEV_OK;
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK) {
- case USB_REQ_TYPE_CLASS :
- switch (req->bRequest) {
- case MOUSE_REQ_SET_PROTOCOL:
- USB_DEV_MOUSE_Protocol = (uint8_t)(req->wValue);
- break;
- case MOUSE_REQ_GET_PROTOCOL:
- usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_MOUSE_Protocol, 1U);
- break;
- case MOUSE_REQ_SET_IDLE:
- USB_DEV_MOUSE_IdleState = (uint8_t)(req->wValue >> 8U);
- break;
- case MOUSE_REQ_GET_IDLE:
- usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_MOUSE_IdleState, 1U);
- break;
- default:
- usb_ctrlerr(pdev);
- u8Res = USB_DEV_FAIL;
- break;
- }
- break;
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest) {
- case USB_REQ_GET_DESCRIPTOR:
- if ((req->wValue >> 8U) == (uint16_t)MOUSE_REPORT_DESC) {
- len = (uint16_t)LL_MIN(MOUSE_REPORT_DESC_SIZE, req->wLength);
- pbuf = HID_MOUSE_ReportDesc;
- } else if ((req->wValue >> 8U) == (uint16_t)MOUSE_DESCRIPTOR_TYPE) {
- pbuf = USB_DEV_MOUSE_CfgDesc + 0x12;
- len = (uint16_t)LL_MIN(MOUSE_DESC_SIZE, req->wLength);
- } else {
- ;
- }
- usb_ctrldatatx(pdev, pbuf, len);
- break;
- case USB_REQ_GET_INTERFACE :
- usb_ctrldatatx(pdev, (uint8_t *)&USB_DEV_MOUSE_AltSet, 1U);
- break;
- case USB_REQ_SET_INTERFACE :
- USB_DEV_MOUSE_AltSet = (uint8_t)(req->wValue);
- break;
- default:
- break;
- }
- break;
- default:
- break;
- }
- return u8Res;
-}
-
-/**
- * @brief Send MOUSE HID report to the host
- * @param [in] pdev device instance
- * @param [in] report pointer to the report buffer
- * @param [in] length the length of the report buffer in bytes
- * @retval status
- */
-uint8_t usb_dev_mouse_txreport(usb_core_instance *pdev, uint8_t *report, uint16_t length)
-{
- if (pdev->dev.device_cur_status == USB_DEV_CONFIGURED) {
- usb_deveptx(pdev, HID_IN_EP, report, (uint32_t)length);
- }
- return USB_DEV_OK;
-}
-
-/**
- * @brief get the configuration descriptor
- * @param [in] length pointer data length of the configuration descriptor in bytes
- * @retval pointer of configuration descriptor buffer
- */
-uint8_t *usb_dev_mouse_getcfgdesc(uint16_t *length)
-{
- *length = (uint16_t)sizeof(USB_DEV_MOUSE_CfgDesc);
- return USB_DEV_MOUSE_CfgDesc;
-}
-
-/**
- * @brief handle the IN data Stage
- * @param [in] pdev device instance
- * @param [in] epnum endpoint index
- * @retval None
- */
-void usb_dev_mouse_datain(void *pdev, uint8_t epnum)
-{
- usb_flsdevep(pdev, HID_IN_EP);
-}
-
-/**
- * @brief handle the OUT data Stage
- * @param [in] pdev device instance
- * @param [in] epnum endpoint index
- * @retval None
- */
-void usb_dev_mouse_dataout(void *pdev, uint8_t epnum)
-{
- usb_readytorx(pdev, HID_OUT_EP, u8HidRevBuf, (uint16_t)(sizeof(u8HidRevBuf) / sizeof(uint8_t)));
- usb_devepstatusset(pdev, HID_OUT_EP, USB_EP_RX_VALID);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_mouse/usb_dev_mouse_class.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_mouse/usb_dev_mouse_class.h
deleted file mode 100644
index 929a917087..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_mouse/usb_dev_mouse_class.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_mouse_class.h
- * @brief header file for the usb_dev_mouse_class.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_DEV_MOUSE_CLASS_H__
-#define __USB_DEV_MOUSE_CLASS_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_def.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_HID_MOUSE
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#define MOUSE_CFGDESC_SIZE (41U)
-#define MOUSE_DESC_SIZE (9U)
-#define MOUSE_REPORT_DESC_SIZE (74U)
-
-#define MOUSE_DESCRIPTOR_TYPE (0x21U)
-#define MOUSE_REPORT_DESC (0x22U)
-
-#define MOUSE_REQ_SET_PROTOCOL (0x0BU)
-#define MOUSE_REQ_GET_PROTOCOL (0x03U)
-
-#define MOUSE_REQ_SET_IDLE (0x0AU)
-#define MOUSE_REQ_GET_IDLE (0x02U)
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-extern usb_dev_class_func usb_dev_mouse_cbk;
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-extern uint8_t usb_dev_mouse_txreport(usb_core_instance *pdev, uint8_t *report, uint16_t len);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_DEV_MOUSE_CLASS_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_msc_composite/usb_dev_hid_msc_wrapper.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_msc_composite/usb_dev_hid_msc_wrapper.c
deleted file mode 100644
index 3a8fddd780..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_msc_composite/usb_dev_hid_msc_wrapper.c
+++ /dev/null
@@ -1,273 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_hid_msc_wrapper.c
- * @brief MSC_HID composite functions.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_custom_hid_class.h"
-#include "usb_dev_msc_class.h"
-#include "usb_dev_hid_msc_wrapper.h"
-#include "usb_dev_desc.h"
-#include "usb_dev_stdreq.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_HID_MSC_COMPOSITE USB Device HID MSC Composite
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-void usb_dev_msc_hid_init(void *pdev);
-void usb_dev_msc_hid_deinit(void *pdev);
-uint8_t usb_dev_msc_hid_setup(void *pdev, USB_SETUP_REQ *req);
-void usb_dev_msc_hid_datain(void *pdev, uint8_t epnum);
-void usb_dev_msc_hid_dataout(void *pdev, uint8_t epnum);
-uint8_t *usb_dev_msc_hid_getcfgdesc(uint16_t *length);
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-usb_dev_class_func usb_dev_composite_cbk = {
- &usb_dev_msc_hid_init,
- &usb_dev_msc_hid_deinit,
- &usb_dev_msc_hid_setup,
- NULL,
- NULL,
- &usb_dev_msc_hid_getcfgdesc,
- NULL,
- &usb_dev_msc_hid_datain,
- &usb_dev_msc_hid_dataout,
- NULL,
- NULL,
-};
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-__USB_ALIGN_BEGIN static uint8_t usb_dev_msc_hid_cfgdesc[USB_MSC_HID_CONFIG_DESC_SIZ] = {
- 0x09, /* bLength: Configuration Descriptor size */
- USB_CFG_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */
- USB_MSC_HID_CONFIG_DESC_SIZ, /* wTotalLength: Bytes returned */
- 0x00,
- 0x02, /* bNumInterfaces: 2 interface */
- 0x01, /* bConfigurationValue: Configuration value */
- 0x00, /* iConfiguration: Index of string descriptor describing the configuration */
- 0xE0, /* bmAttributes: bus powered and Support Remote Wake-up */
- 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */
- /************** Descriptor of HID interface ****************/
- /* 09 */
- 0x09, /* bLength: Interface Descriptor size */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface descriptor type */
- 0x00, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x02, /* bNumEndpoints */
- 0x03, /* bInterfaceClass: HID */
- 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */
- 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */
- 0, /* iInterface: Index of string descriptor */
- /******************** Descriptor of HID ********************/
- /* 18 */
- 0x09, /* bLength: HID Descriptor size */
- CUSTOM_HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID */
- 0x11, /* bcdHID: HID Class Spec release number */
- 0x01,
- 0x00, /* bCountryCode: Hardware target country */
- 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */
- 0x22, /* bDescriptorType */
- CUSTOM_HID_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */
- 0x00,
- /******************** Descriptor of HID endpoint ********************/
- /* 27 */
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */
- HID_IN_EP, /* bEndpointAddress: Endpoint Address (IN) */
- 0x03, /* bmAttributes: Interrupt endpoint */
- HID_IN_PACKET, /* wMaxPacketSize: 4 Byte max */
- 0x00,
- 0x0A, /* bInterval: Polling Interval (10 ms) */
- /* 34 */
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */
- HID_OUT_EP, /* bEndpointAddress: Endpoint Address (IN) */
- 0x03, /* bmAttributes: Interrupt endpoint */
- HID_OUT_PACKET, /* wMaxPacketSize: 4 Byte max */
- 0x00,
- 0x0A, /*bInterval: Polling Interval (10 ms)*/
- /* 41 */
- /******************** Mass Storage interface ********************/
- 0x09, /* bLength: Interface Descriptor size */
- 0x04, /* bDescriptorType: */
- 0x01, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x02, /* bNumEndpoints*/
- 0x08, /* bInterfaceClass: MSC Class */
- 0x06, /* bInterfaceSubClass : SCSI transparent*/
- 0x50, /* nInterfaceProtocol */
- 0x05, /* iInterface: */
- /******************** Mass Storage Endpoints ********************/
- 0x07, /* Endpoint descriptor length = 7 */
- 0x05, /* Endpoint descriptor type */
- MSC_IN_EP, /* Endpoint address (IN, address 1) */
- 0x02, /* Bulk endpoint type */
- LOBYTE(MSC_MAX_PACKET),
- HIBYTE(MSC_MAX_PACKET),
- 0x00, /* Polling interval in milliseconds */
-
- 0x07, /* Endpoint descriptor length = 7 */
- 0x05, /* Endpoint descriptor type */
- MSC_OUT_EP, /* Endpoint address (OUT, address 1) */
- 0x02, /* Bulk endpoint type */
- LOBYTE(MSC_MAX_PACKET),
- HIBYTE(MSC_MAX_PACKET),
- 0x00 /* Polling interval in milliseconds */
-} ;
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @brief Initialize the composite device of MSC-HID interface
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_dev_msc_hid_init(void *pdev)
-{
- usb_dev_hid_init(pdev);
- usb_dev_msc_init(pdev);
-}
-
-/**
- * @brief de-initialize the composite device of MSC-HID interface
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_dev_msc_hid_deinit(void *pdev)
-{
- usb_dev_hid_deinit(pdev);
- usb_dev_msc_deinit(pdev);
-}
-
-/**
- * @brief process the setup requests
- * @param [in] pdev device instance
- * @param [in] req setup request
- * @retval status
- */
-uint8_t usb_dev_msc_hid_setup(void *pdev, USB_SETUP_REQ *req)
-{
- uint8_t u8Res = USB_DEV_OK;
- switch (req->bmRequest & USB_REQ_RECIPIENT_MASK) {
- case USB_REQ_RECIPIENT_INTERFACE:
- if (req->wIndex == 0U) {
- u8Res = usb_dev_hid_setup(pdev, req);
- } else {
- u8Res = usb_dev_msc_setup(pdev, req);
- }
- break;
-
- case USB_REQ_RECIPIENT_ENDPOINT:
- if (req->wIndex == HID_IN_EP) {
- u8Res = usb_dev_hid_setup(pdev, req);
- } else {
- u8Res = usb_dev_msc_setup(pdev, req);
- }
- break;
- default:
- break;
- }
- return u8Res;
-}
-
-/**
- * @brief process data IN DATA
- * @param [in] pdev device instance
- * @param [in] epnum endpoint index
- * @retval None
- */
-void usb_dev_msc_hid_datain(void *pdev, uint8_t epnum)
-{
- if (epnum == (uint8_t)(MSC_IN_EP & ((uint8_t)~0x80U))) {
- usb_dev_msc_datain(pdev, epnum);
- } else {
- usb_dev_hid_datain(pdev, epnum);
- }
-}
-
-/**
- * @brief process data OUT DATA
- * @param [in] pdev device instance
- * @param [in] epnum endpoint index
- * @retval None
- */
-void usb_dev_msc_hid_dataout(void *pdev, uint8_t epnum)
-{
- if (epnum == (uint8_t)(MSC_OUT_EP & ((uint8_t)~0x80U))) {
- usb_dev_msc_dataout(pdev, epnum);
- } else {
- usb_dev_hid_dataout(pdev, epnum);
- }
-}
-
-/**
- * @brief get the configuration descriptor
- * @param [in] length length of data butter in bytes
- * @retval buffer pointer
- */
-uint8_t *usb_dev_msc_hid_getcfgdesc(uint16_t *length)
-{
- *length = (uint16_t)sizeof(usb_dev_msc_hid_cfgdesc);
- return usb_dev_msc_hid_cfgdesc;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_msc_composite/usb_dev_hid_msc_wrapper.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_msc_composite/usb_dev_hid_msc_wrapper.h
deleted file mode 100644
index e849984a83..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_msc_composite/usb_dev_hid_msc_wrapper.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_hid_msc_wrapper.h
- * @brief header file for the usb_dev_hid_msc_wrapper.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_DEV_HID_MSC_WRAPPER_H__
-#define __USB_DEV_HID_MSC_WRAPPER_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_ctrleptrans.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_HID_MSC_COMPOSITE
- * @{
- */
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-#define USB_MSC_HID_CONFIG_DESC_SIZ (USB_CUSTOM_HID_CONFIG_DESC_SIZ - 9U + USB_MSC_CONFIG_DESC_SIZ)
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-extern usb_dev_class_func usb_dev_composite_cbk;
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_DEV_HID_MSC_WRAPPER_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_bot.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_bot.c
deleted file mode 100644
index ebcd1fe23d..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_bot.c
+++ /dev/null
@@ -1,267 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_msc_bot.c
- * @brief USB DEV bulk only transfer functions.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_msc_bot.h"
-#include "usb_dev_msc_scsi.h"
-#include "usb_dev_ctrleptrans.h"
-#include "usb_dev_msc_mem.h"
-#include "usb_dev_driver.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_MSC USB Device MSC
- * @{
- */
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-
-uint16_t MSC_BOT_DataLen;
-uint8_t MSC_BOT_State;
-static uint8_t MSC_BOT_Status;
-
-__USB_ALIGN_BEGIN uint8_t MSC_BOT_Data[MSC_MEDIA_PACKET];
-
-__USB_ALIGN_BEGIN MSC_BOT_CBW_TypeDef MSC_BOT_cbw;
-
-__USB_ALIGN_BEGIN MSC_BOT_CSW_TypeDef MSC_BOT_csw;
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @brief Send the requested data
- * @param [in] pdev device instance
- * @param [in] buf pointer for data buffer
- * @param [in] length data Length in bytes
- * @retval None
- */
-static void msc_bot_txdata(usb_core_instance *pdev, uint8_t *buf, uint16_t length)
-{
- length = (uint16_t)LL_MIN(MSC_BOT_cbw.dDataLength, length);
- MSC_BOT_csw.dDataResidue -= length;
- MSC_BOT_csw.bStatus = CSW_CMD_PASSED;
- MSC_BOT_State = BOT_SEND_DATA;
- usb_deveptx(pdev, MSC_IN_EP, buf, (uint32_t)length);
-}
-
-/**
- * @brief abort current transfer
- * @param [in] pdev device instance
- * @retval None
- */
-static void msc_bot_abort(usb_core_instance *pdev)
-{
- if ((MSC_BOT_cbw.bmFlags == (uint8_t)0) &&
- (MSC_BOT_cbw.dDataLength != (uint32_t)0) &&
- (MSC_BOT_Status == BOT_STATE_NORMAL)) {
- usb_stalldevep(pdev, MSC_OUT_EP);
- }
- usb_stalldevep(pdev, MSC_IN_EP);
- if (MSC_BOT_Status == BOT_STATE_ERROR) {
- usb_readytorx(pdev, MSC_OUT_EP, (uint8_t *)&MSC_BOT_cbw, BOT_CBW_LENGTH);
- }
-}
-
-/**
- * @brief decodes the CBW command and set the BOT state machine accordingly
- * @param [in] pdev device instance
- * @retval None
- */
-static void msc_bot_decode_cbw(usb_core_instance *pdev)
-{
-
- MSC_BOT_csw.dTag = MSC_BOT_cbw.dTag;
- MSC_BOT_csw.dDataResidue = MSC_BOT_cbw.dDataLength;
-
- if ((usb_getrxcnt(pdev, MSC_OUT_EP) != BOT_CBW_LENGTH) ||
- (MSC_BOT_cbw.dSignature != BOT_CBW_SIGNATURE) ||
- (MSC_BOT_cbw.bLUN > 1U) ||
- (MSC_BOT_cbw.bCBLength < 1U) ||
- (MSC_BOT_cbw.bCBLength > 16U)) {
- scsi_sensecode(ILLEGAL_REQUEST, INVALID_CDB);
- MSC_BOT_Status = BOT_STATE_ERROR;
- msc_bot_abort(pdev);
-
- } else {
- if (scsi_cmdprocess(pdev, MSC_BOT_cbw.bLUN, &MSC_BOT_cbw.CB[0]) < 0) {
- msc_bot_abort(pdev);
- } else if ((MSC_BOT_State != BOT_DATA_IN) &&
- (MSC_BOT_State != BOT_DATA_OUT) &&
- (MSC_BOT_State != BOT_LAST_DATA_IN)) {
- if (MSC_BOT_DataLen > (uint16_t)0) {
- msc_bot_txdata(pdev, MSC_BOT_Data, MSC_BOT_DataLen);
- } else {
- msc_bot_txcsw(pdev, CSW_CMD_PASSED);
- }
- } else {
- ;
- }
- }
-}
-
-/**
- * @brief initialize the BOT Process
- * @param [in] pdev device instance
- * @retval None
- */
-void msc_bot_init(usb_core_instance *pdev)
-{
- MSC_BOT_State = BOT_IDLE;
- MSC_BOT_Status = BOT_STATE_NORMAL;
- msc_fops->Init(0U);
-
- usb_flsdevep(pdev, MSC_OUT_EP);
- usb_flsdevep(pdev, MSC_IN_EP);
- /* Prapare EP to Receive First BOT command */
- usb_readytorx(pdev, MSC_OUT_EP, (uint8_t *)&MSC_BOT_cbw, BOT_CBW_LENGTH);
-}
-
-/**
- * @brief resets the BOT Machine
- * @param [in] pdev device instance
- * @retval None
- */
-void msc_bot_rst(usb_core_instance *pdev)
-{
- MSC_BOT_State = BOT_IDLE;
- MSC_BOT_Status = BOT_STATE_RECOVERY;
- /* Prapare OUT EP to Receive First BOT command */
- usb_readytorx(pdev, MSC_OUT_EP, (uint8_t *)&MSC_BOT_cbw, BOT_CBW_LENGTH);
-}
-
-/**
- * @brief deinitialize the BOT Machine
- * @param [in] pdev device instance
- * @retval None
- */
-void msc_bot_deinit(usb_core_instance *pdev)
-{
- MSC_BOT_State = BOT_IDLE;
-}
-
-/**
- * @brief process BOT IN data stage
- * @param [in] pdev device instance
- * @param [in] epnum endpoint index
- * @retval None
- */
-void msc_bot_datain(usb_core_instance *pdev, uint8_t epnum)
-{
- switch (MSC_BOT_State) {
- case BOT_DATA_IN:
- if (scsi_cmdprocess(pdev, MSC_BOT_cbw.bLUN, &MSC_BOT_cbw.CB[0]) < 0) {
- msc_bot_txcsw(pdev, CSW_CMD_FAILED);
- }
- break;
- case BOT_SEND_DATA:
- case BOT_LAST_DATA_IN:
- msc_bot_txcsw(pdev, CSW_CMD_PASSED);
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief proccess MSC OUT data stage
- * @param [in] pdev device instance
- * @param [in] epnum endpoint number
- * @retval None
- */
-void msc_bot_dataout(usb_core_instance *pdev, uint8_t epnum)
-{
- switch (MSC_BOT_State) {
- case BOT_IDLE:
- msc_bot_decode_cbw(pdev);
- break;
- case BOT_DATA_OUT:
- if (scsi_cmdprocess(pdev, MSC_BOT_cbw.bLUN, &MSC_BOT_cbw.CB[0]) < 0) {
- msc_bot_txcsw(pdev, CSW_CMD_FAILED);
- }
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief send the Command Status Wrapper
- * @param [in] pdev device instance
- * @param [in] CSW_Status CSW status
- * @retval None
- */
-void msc_bot_txcsw(usb_core_instance *pdev, uint8_t CSW_Status)
-{
- MSC_BOT_csw.dSignature = BOT_CSW_SIGNATURE;
- MSC_BOT_csw.bStatus = CSW_Status;
- MSC_BOT_State = BOT_IDLE;
- usb_deveptx(pdev, MSC_IN_EP, (uint8_t *)&MSC_BOT_csw, BOT_CSW_LENGTH);
- /* Prapare EP to Receive next Cmd */
- usb_readytorx(pdev, MSC_OUT_EP, (uint8_t *)&MSC_BOT_cbw, BOT_CBW_LENGTH);
-}
-
-/**
- * @brief Complete the clear feature request
- * @param [in] pdev device instance
- * @param [in] epnum endpoint number
- * @retval None
- */
-void msc_bot_complete_clearfeature(usb_core_instance *pdev, uint8_t epnum)
-{
- if (MSC_BOT_Status == BOT_STATE_ERROR) {
- usb_stalldevep(pdev, MSC_IN_EP);
- MSC_BOT_Status = BOT_STATE_NORMAL;
- } else if (((epnum & 0x80U) == 0x80U) && (MSC_BOT_Status != BOT_STATE_RECOVERY)) {
- msc_bot_txcsw(pdev, CSW_CMD_FAILED);
- } else {
- ;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_bot.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_bot.h
deleted file mode 100644
index 72a352c42b..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_bot.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_msc_bot.h
- * @brief header file for the usb_dev_msc_bot.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_DEV_MSC_BOT_H__
-#define __USB_DEV_MSC_BOT_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_core.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_MSC
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-typedef struct {
- uint32_t dSignature;
- uint32_t dTag;
- uint32_t dDataLength;
- uint8_t bmFlags;
- uint8_t bLUN;
- uint8_t bCBLength;
- uint8_t CB[16];
-} MSC_BOT_CBW_TypeDef;
-
-typedef struct {
- uint32_t dSignature;
- uint32_t dTag;
- uint32_t dDataResidue;
- uint8_t bStatus;
-} MSC_BOT_CSW_TypeDef;
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#define BOT_IDLE (0U) /* Idle state */
-#define BOT_DATA_OUT (1U) /* Data Out state */
-#define BOT_DATA_IN (2U) /* Data In state */
-#define BOT_LAST_DATA_IN (3U) /* Last Data In Last */
-#define BOT_SEND_DATA (4U) /* Send Immediate data */
-
-#define BOT_CBW_SIGNATURE (0x43425355UL)
-#define BOT_CSW_SIGNATURE (0x53425355UL)
-#define BOT_CBW_LENGTH (31U)
-#define BOT_CSW_LENGTH (13U)
-
-/* CSW Status Definitions */
-#define CSW_CMD_PASSED (0x00U)
-#define CSW_CMD_FAILED (0x01U)
-#define CSW_PHASE_ERROR (0x02U)
-
-/* BOT Status */
-#define BOT_STATE_NORMAL (0U)
-#define BOT_STATE_RECOVERY (1U)
-#define BOT_STATE_ERROR (2U)
-
-#define DIR_IN (0U)
-#define DIR_OUT (1U)
-#define BOTH_DIR (2U)
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-extern uint8_t MSC_BOT_Data[MSC_MEDIA_PACKET];
-extern uint16_t MSC_BOT_DataLen;
-extern uint8_t MSC_BOT_State;
-extern MSC_BOT_CBW_TypeDef MSC_BOT_cbw;
-extern MSC_BOT_CSW_TypeDef MSC_BOT_csw;
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-extern void msc_bot_init(usb_core_instance *pdev);
-extern void msc_bot_rst(usb_core_instance *pdev);
-extern void msc_bot_deinit(usb_core_instance *pdev);
-extern void msc_bot_datain(usb_core_instance *pdev, uint8_t epnum);
-extern void msc_bot_dataout(usb_core_instance *pdev, uint8_t epnum);
-extern void msc_bot_txcsw(usb_core_instance *pdev, uint8_t CSW_Status);
-extern void msc_bot_complete_clearfeature(usb_core_instance *pdev, uint8_t epnum);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_DEV_MSC_BOT_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_class.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_class.c
deleted file mode 100644
index 6d69ea9b83..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_class.c
+++ /dev/null
@@ -1,264 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_msc_class.c
- * @brief USB MSC device class
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_msc_mem.h"
-#include "usb_dev_msc_class.h"
-#include "usb_dev_msc_bot.h"
-#include "usb_dev_stdreq.h"
-#include "usb_dev_driver.h"
-#include "usb_dev_ctrleptrans.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_MSC
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-uint8_t *usb_dev_msc_getcfgdesc(uint16_t *length);
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-usb_dev_class_func usb_dev_msc_cbk = {
- &usb_dev_msc_init,
- &usb_dev_msc_deinit,
- &usb_dev_msc_setup,
- NULL,
- NULL,
- &usb_dev_msc_getcfgdesc,
- NULL,
- &usb_dev_msc_datain,
- &usb_dev_msc_dataout,
- NULL,
- NULL,
-};
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-static uint8_t dev_msc_maxlun = 0U;
-static uint8_t dev_msc_altset = 0U;
-
-__USB_ALIGN_BEGIN static uint8_t usb_dev_msc_cfgdesc[USB_MSC_CONFIG_DESC_SIZ] = {
- 0x09, /* bLength: Configuation Descriptor size */
- USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */
- USB_MSC_CONFIG_DESC_SIZ,
- 0x00,
- 0x01, /* bNumInterfaces: 1 interface */
- 0x01, /* bConfigurationValue: */
- 0x04, /* iConfiguration: */
- 0xC0, /* bmAttributes: */
- 0x32, /* MaxPower 100 mA */
- /******************** Mass Storage interface descriptor**********/
- 0x09, /* bLength: Interface Descriptor size */
- 0x04, /* bDescriptorType: */
- 0x00, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x02, /* bNumEndpoints*/
- 0x08, /* bInterfaceClass: MSC Class */
- 0x06, /* bInterfaceSubClass : SCSI transparent*/
- 0x50, /* nInterfaceProtocol */
- 0x05, /* iInterface: */
- /******************** Mass Storage Endpoints descriptor**********/
- 0x07, /* Endpoint descriptor length = 7 */
- 0x05, /* Endpoint descriptor type */
- MSC_IN_EP, /* Endpoint address (IN, address 1) */
- 0x02, /* Bulk endpoint type */
- LOBYTE(MSC_MAX_PACKET),
- HIBYTE(MSC_MAX_PACKET),
- 0x00, /* Polling interval in milliseconds */
-
- 0x07, /* Endpoint descriptor length = 7 */
- 0x05, /* Endpoint descriptor type */
- MSC_OUT_EP, /* Endpoint address (OUT, address 1) */
- 0x02, /* Bulk endpoint type */
- LOBYTE(MSC_MAX_PACKET),
- HIBYTE(MSC_MAX_PACKET),
- 0x00 /* Polling interval in milliseconds */
-};
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @brief Initialize the mass storage interface configuration
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_dev_msc_init(void *pdev)
-{
- usb_dev_msc_deinit(pdev);
- usb_opendevep(pdev, MSC_IN_EP, MSC_EPIN_SIZE, EP_TYPE_BULK);
- usb_opendevep(pdev, MSC_OUT_EP, MSC_EPOUT_SIZE, EP_TYPE_BULK);
- msc_bot_init(pdev);
-}
-
-/**
- * @brief deinitilaize the mass storage interface configuration
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_dev_msc_deinit(void *pdev)
-{
- usb_shutdevep(pdev, MSC_IN_EP);
- usb_shutdevep(pdev, MSC_OUT_EP);
- msc_bot_deinit(pdev);
-}
-
-/**
- * @brief process the msc setup requests
- * @param [in] pdev device instance
- * @param [in] req setup request
- * @retval status
- */
-uint8_t usb_dev_msc_setup(void *pdev, USB_SETUP_REQ *req)
-{
- uint8_t u8Res = USB_DEV_OK;
- switch (req->bmRequest & USB_REQ_TYPE_MASK) {
- case USB_REQ_TYPE_CLASS:
- switch (req->bRequest) {
- case BOT_GET_MAX_LUN:
- if ((req->wValue == (uint16_t)0) &&
- (req->wLength == (uint16_t)1) &&
- ((req->bmRequest & 0x80U) == (uint8_t)0x80)) {
- dev_msc_maxlun = msc_fops->GetMaxLun();
- if (dev_msc_maxlun > 0U) {
- usb_ctrldatatx(pdev, &dev_msc_maxlun, 1U);
- } else {
- usb_ctrlerr(pdev);
- u8Res = USB_DEV_FAIL;
- }
- } else {
- usb_ctrlerr(pdev);
- u8Res = USB_DEV_FAIL;
- }
- break;
- case BOT_RESET:
- if ((req->wValue == (uint16_t)0) &&
- (req->wLength == (uint16_t)0) &&
- ((req->bmRequest & 0x80U) != (uint8_t)0x80)) {
- msc_bot_rst(pdev);
- } else {
- usb_ctrlerr(pdev);
- u8Res = USB_DEV_FAIL;
- }
- break;
- default:
- usb_ctrlerr(pdev);
- u8Res = USB_DEV_FAIL;
- break;
- }
- break;
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest) {
- case USB_REQ_GET_INTERFACE:
- usb_ctrldatatx(pdev, &dev_msc_altset, 1U);
- break;
- case USB_REQ_SET_INTERFACE:
- dev_msc_altset = (uint8_t)(req->wValue);
- break;
- case USB_REQ_CLEAR_FEATURE:
- usb_flsdevep(pdev, (uint8_t)req->wIndex);
- usb_shutdevep(pdev, (uint8_t)req->wIndex);
- if ((((uint8_t)req->wIndex) & (uint16_t)0x80U) == (uint16_t)0x80) {
- usb_opendevep(pdev, ((uint8_t)req->wIndex), MSC_EPIN_SIZE, EP_TYPE_BULK);
- } else {
- usb_opendevep(pdev, ((uint8_t)req->wIndex), MSC_EPOUT_SIZE, EP_TYPE_BULK);
- }
- msc_bot_complete_clearfeature(pdev, (uint8_t)req->wIndex);
- break;
- default:
- break;
- }
- break;
- default:
- break;
- }
- return u8Res;
-}
-
-/**
- * @brief process data IN DATA
- * @param [in] pdev device instance
- * @param [in] epnum endpoint index
- * @retval None
- */
-void usb_dev_msc_datain(void *pdev, uint8_t epnum)
-{
- msc_bot_datain(pdev, epnum);
-}
-
-/**
- * @brief process data OUT DATA
- * @param [in] pdev device instance
- * @param [in] epnum endpoint index
- * @retval None
- */
-void usb_dev_msc_dataout(void *pdev, uint8_t epnum)
-{
- msc_bot_dataout(pdev, epnum);
-}
-
-/**
- * @brief get the configuration descriptor
- * @param [in] length length of data butter in bytes
- * @retval buffer pointer
- */
-uint8_t *usb_dev_msc_getcfgdesc(uint16_t *length)
-{
- *length = (uint16_t)sizeof(usb_dev_msc_cfgdesc);
- return usb_dev_msc_cfgdesc;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_class.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_class.h
deleted file mode 100644
index 0b6078307b..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_class.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_msc_class.h
- * @brief header file for the usb_dev_msc_class.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_DEV_MSC_CLASS_H__
-#define __USB_DEV_MSC_CLASS_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_MSC
- * @{
- */
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#define BOT_GET_MAX_LUN (0xFEU)
-#define BOT_RESET (0xFFU)
-#define USB_MSC_CONFIG_DESC_SIZ (32U)
-
-#define MSC_EPIN_SIZE (MSC_MAX_PACKET)
-#define MSC_EPOUT_SIZE (MSC_MAX_PACKET)
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-extern usb_dev_class_func usb_dev_msc_cbk;
-
-/* MSC Device library callbacks */
-extern void usb_dev_msc_init(void *pdev);
-extern void usb_dev_msc_deinit(void *pdev);
-extern uint8_t usb_dev_msc_setup(void *pdev, USB_SETUP_REQ *req);
-extern void usb_dev_msc_datain(void *pdev, uint8_t epnum);
-extern void usb_dev_msc_dataout(void *pdev, uint8_t epnum);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_DEV_MSC_CLASS_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_data.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_data.c
deleted file mode 100644
index 1ee2837705..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_data.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_msc_data.c
- * @brief This file provides all the vital inquiry pages and sense data.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_msc_data.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_MSC
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-/* USB Mass storage Page 0 Inquiry Data */
-const uint8_t MSC_Page00_Inquiry_Data[] = { /* 7 */
- 0x00,
- 0x00,
- 0x00,
- (LENGTH_INQUIRY_PAGE00 - 4U),
- 0x00,
- 0x80,
- 0x83
-};
-/* USB Mass storage sense 6 Data */
-const uint8_t MSC_Mode_Sense6_data[] = {
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00
-};
-/* USB Mass storage sense 10 Data */
-const uint8_t MSC_Mode_Sense10_data[] = {
- 0x00,
- 0x06,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00
-};
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_data.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_data.h
deleted file mode 100644
index 24ac1f2bcf..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_data.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_msc_data.h
- * @brief header file for the usb_dev_msc_data.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_DEV_MSC_DATA_H__
-#define __USB_DEV_MSC_DATA_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_def.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_MSC
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#define MODE_SENSE6_LEN (8U)
-#define MODE_SENSE10_LEN (8U)
-#define LENGTH_INQUIRY_PAGE00 (7U)
-#define LENGTH_FORMAT_CAPACITIES (20U)
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-extern const uint8_t MSC_Page00_Inquiry_Data[LENGTH_INQUIRY_PAGE00];
-extern const uint8_t MSC_Mode_Sense6_data[MODE_SENSE6_LEN];
-extern const uint8_t MSC_Mode_Sense10_data[MODE_SENSE10_LEN];
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_DEV_MSC_DATA_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_mem.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_mem.h
deleted file mode 100644
index 76dda049b6..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_mem.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_msc_mem.h
- * @brief header file for the usb_dev_msc_mem.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_DEV_MSC_MEM_H__
-#define __USB_DEV_MSC_MEM_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_def.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_MSC
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-typedef struct {
- int8_t (* Init)(uint8_t lun);
- int8_t (* GetCapacity)(uint8_t lun, uint32_t *block_num, uint32_t *block_size);
- int8_t (* GetMaxLun)(void);
- int8_t (* IsReady)(uint8_t lun);
- int8_t (* Read)(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len);
- int8_t (* Write)(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len);
- int8_t (* IsWriteProtected)(uint8_t lun);
- int8_t *pInquiry;
-} USB_DEV_MSC_cbk_TypeDef;
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#define USB_DEV_INQUIRY_LENGTH (36U)
-
-extern USB_DEV_MSC_cbk_TypeDef *msc_fops;
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_DEV_MSC_MEM_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_scsi.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_scsi.c
deleted file mode 100644
index 05227225a1..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_scsi.c
+++ /dev/null
@@ -1,552 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_msc_scsi.c
- * @brief This file provides all the USBD SCSI layer functions.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_msc_bot.h"
-#include "usb_dev_msc_scsi.h"
-#include "usb_dev_msc_mem.h"
-#include "usb_dev_msc_data.h"
-#include "usb_dev_driver.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_MSC
- * @{
- */
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-static uint32_t SCSI_blk_size;
-static uint32_t SCSI_blk_nbr;
-static uint64_t SCSI_blk_addr;
-static uint32_t SCSI_blk_len;
-static usb_core_instance *cdev;
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-SCSI_Sense_TypeDef SCSI_Sense[SENSE_LIST_DEEPTH];
-uint8_t SCSI_Sense_Head;
-uint8_t SCSI_Sense_Tail;
-
-/*******************************************************************************
- * Local function prototypes
- ******************************************************************************/
-int8_t scsi_testunitready(uint8_t lun);
-int8_t scsi_inquiry(uint8_t lun, uint8_t *params);
-int8_t scsi_readformatcapacity(uint8_t lun);
-int8_t scsi_readcapacity10(uint8_t lun);
-int8_t scsi_requestsense(uint8_t *params);
-int8_t scsi_startstopuint(void);
-int8_t scsi_modesense6(uint8_t lun);
-int8_t scsi_modesense10(void);
-int8_t scsi_write10(uint8_t lun, uint8_t *params);
-int8_t scsi_read10(uint8_t lun, uint8_t *params);
-int8_t scsi_verify10(uint8_t lun, uint8_t *params);
-int8_t scsi_addressrangecheck(uint32_t blk_offset, uint16_t blk_nbr);
-int8_t scsi_processread(uint8_t lun);
-int8_t scsi_processwrite(uint8_t lun);
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @brief Processes SCSI commands
- * @param [in] pdev device instance
- * @param [in] lun number of logical unit
- * @param [in] params command
- * @retval status
- */
-int8_t scsi_cmdprocess(usb_core_instance *pdev, uint8_t lun, uint8_t *params)
-{
- int8_t Res;
- cdev = pdev;
-
- if (params[0] == SCSI_TEST_UNIT_READY) {
- Res = scsi_testunitready(lun);
- } else if (params[0] == SCSI_REQUEST_SENSE) {
- Res = scsi_requestsense(params);
- } else if (params[0] == SCSI_INQUIRY) {
- Res = scsi_inquiry(lun, params);
- } else if (params[0] == SCSI_START_STOP_UNIT) {
- Res = scsi_startstopuint();
- } else if (params[0] == SCSI_ALLOW_MEDIUM_REMOVAL) {
- Res = scsi_startstopuint();
- } else if (params[0] == SCSI_MODE_SENSE6) {
- Res = scsi_modesense6(lun);
- } else if (params[0] == SCSI_MODE_SENSE10) {
- Res = scsi_modesense10();
- } else if (params[0] == SCSI_READ_FORMAT_CAPACITIES) {
- Res = scsi_readformatcapacity(lun);
- } else if (params[0] == SCSI_READ_CAPACITY10) {
- Res = scsi_readcapacity10(lun);
- } else if (params[0] == SCSI_READ10) {
- Res = scsi_read10(lun, params);
- } else if (params[0] == SCSI_WRITE10) {
- Res = scsi_write10(lun, params);
- } else if (params[0] == SCSI_VERIFY10) {
- Res = scsi_verify10(lun, params);
- } else {
- scsi_sensecode(ILLEGAL_REQUEST, INVALID_CDB);
- Res = (int8_t) -1;
- }
- return Res;
-}
-
-/**
- * @brief Processes SCSI Test Unit Ready Command
- * @param [in] lun number of logical unit
- * @retval status
- */
-int8_t scsi_testunitready(uint8_t lun)
-{
- int8_t i8Ret;
- i8Ret = (int8_t)0;
- /* case 9 : Hi > D0 */
- if (MSC_BOT_cbw.dDataLength != 0U) {
- scsi_sensecode(ILLEGAL_REQUEST, INVALID_CDB);
- i8Ret = (int8_t) -1;
- } else {
- if (msc_fops->IsReady(lun) != 0U) {
- scsi_sensecode(NOT_READY, MEDIUM_NOT_PRESENT);
- i8Ret = (int8_t) -1;
- } else {
- MSC_BOT_DataLen = 0U;
- }
- }
- return i8Ret;
-}
-
-/**
- * @brief Processes inquiry command
- * @param [in] lun number of logical unit
- * @param [in] params command
- * @retval status
- */
-int8_t scsi_inquiry(uint8_t lun, uint8_t *params)
-{
- const uint8_t *pPage;
- uint16_t len;
-
- if ((params[1] & 0x01U) != 0U) {
- pPage = (const uint8_t *)MSC_Page00_Inquiry_Data;
- len = LENGTH_INQUIRY_PAGE00;
- } else {
-
- pPage = (uint8_t *)&msc_fops->pInquiry[lun * USB_DEV_INQUIRY_LENGTH];
- len = (uint16_t)pPage[4] + (uint16_t)5;
-
- if (params[4] <= len) {
- len = params[4];
- }
- }
- MSC_BOT_DataLen = len;
-
- while (len != 0U) {
- len--;
- MSC_BOT_Data[len] = pPage[len];
- }
- return (int8_t)0;
-}
-
-/**
- * @brief Processes Read Capacity10 command
- * @param [in] lun number of logical unit
- * @retval status
- */
-int8_t scsi_readcapacity10(uint8_t lun)
-{
- int8_t i8Ret = (int8_t)0;
- if (msc_fops->GetCapacity(lun, &SCSI_blk_nbr, &SCSI_blk_size) != 0U) {
- scsi_sensecode(NOT_READY, MEDIUM_NOT_PRESENT);
- i8Ret = (int8_t) -1;
- } else {
- MSC_BOT_Data[0] = (uint8_t)((SCSI_blk_nbr - 1U) >> 24U);
- MSC_BOT_Data[1] = (uint8_t)((SCSI_blk_nbr - 1U) >> 16U);
- MSC_BOT_Data[2] = (uint8_t)((SCSI_blk_nbr - 1U) >> 8U);
- MSC_BOT_Data[3] = (uint8_t)(SCSI_blk_nbr - 1U);
-
- MSC_BOT_Data[4] = (uint8_t)(SCSI_blk_size >> 24U);
- MSC_BOT_Data[5] = (uint8_t)(SCSI_blk_size >> 16U);
- MSC_BOT_Data[6] = (uint8_t)(SCSI_blk_size >> 8U);
- MSC_BOT_Data[7] = (uint8_t)(SCSI_blk_size);
- MSC_BOT_DataLen = 8U;
- }
- return i8Ret;
-}
-
-/**
- * @brief Processes Read Format Capacity command
- * @param [in] lun number of logical unit
- * @retval status
- */
-int8_t scsi_readformatcapacity(uint8_t lun)
-{
- int8_t i8Ret = (int8_t)0;
- uint32_t blk_size;
- uint32_t blk_nbr;
- uint16_t i;
-
- i = 0U;
- while (i < 12U) {
- MSC_BOT_Data[i++] = 0U;
- }
-
- if (msc_fops->GetCapacity(lun, &blk_nbr, &blk_size) != 0U) {
- scsi_sensecode(NOT_READY, MEDIUM_NOT_PRESENT);
- i8Ret = (int8_t) -1;
- } else {
- MSC_BOT_Data[3] = 0x08U;
- MSC_BOT_Data[4] = (uint8_t)((blk_nbr - 1U) >> 24U);
- MSC_BOT_Data[5] = (uint8_t)((blk_nbr - 1U) >> 16U);
- MSC_BOT_Data[6] = (uint8_t)((blk_nbr - 1U) >> 8U);
- MSC_BOT_Data[7] = (uint8_t)(blk_nbr - 1U);
-
- MSC_BOT_Data[8] = 0x02U;
- MSC_BOT_Data[9] = (uint8_t)(blk_size >> 16U);
- MSC_BOT_Data[10] = (uint8_t)(blk_size >> 8U);
- MSC_BOT_Data[11] = (uint8_t)(blk_size);
-
- MSC_BOT_DataLen = 12U;
- }
- return i8Ret;
-}
-
-/**
- * @brief Processes Mode Sense6 command
- * @param [in] lun number of logical unit
- * @retval status
- */
-int8_t scsi_modesense6(uint8_t lun)
-{
- uint16_t len;
- len = 8U;
- MSC_BOT_DataLen = len;
- while (0U != len) {
- len--;
- MSC_BOT_Data[len] = MSC_Mode_Sense6_data[len];
- }
- return (int8_t)0;
-}
-
-/**
- * @brief processes Mode Sense10 command
- * @param None
- * @retval status
- */
-int8_t scsi_modesense10(void)
-{
- uint16_t len = 8U;
-
- MSC_BOT_DataLen = len;
- while (0U != len) {
- len--;
- MSC_BOT_Data[len] = MSC_Mode_Sense10_data[len];
- }
- return (int8_t)0;
-}
-
-/**
- * @brief processes Request Sense command
- * @param [in] params command
- * @retval status
- */
-int8_t scsi_requestsense(uint8_t *params)
-{
- uint8_t i;
-
- i = 0U;
- while (i < REQUEST_SENSE_DATA_LEN) {
- MSC_BOT_Data[i++] = 0U;
- }
- MSC_BOT_Data[0] = 0x70U;
- MSC_BOT_Data[7] = REQUEST_SENSE_DATA_LEN - 6U;
- if ((SCSI_Sense_Head != SCSI_Sense_Tail)) {
- MSC_BOT_Data[2] = (uint8_t)SCSI_Sense[SCSI_Sense_Head].Skey;
- MSC_BOT_Data[12] = (uint8_t)SCSI_Sense[SCSI_Sense_Head].w.b.ASCQ;
- MSC_BOT_Data[13] = (uint8_t)SCSI_Sense[SCSI_Sense_Head].w.b.ASC;
- SCSI_Sense_Head++;
- if (SCSI_Sense_Head == SENSE_LIST_DEEPTH) {
- SCSI_Sense_Head = 0U;
- }
- }
- MSC_BOT_DataLen = REQUEST_SENSE_DATA_LEN;
- if (params[4] <= REQUEST_SENSE_DATA_LEN) {
- MSC_BOT_DataLen = params[4];
- }
- return (int8_t)0;
-}
-
-/**
- * @brief Loads the last error code in the error list
- * @param [in] sKey Sense Key
- * @param [in] ASC Additional Sense Key
- * @retval None
- */
-void scsi_sensecode(uint8_t sKey, uint8_t ASC)
-{
- SCSI_Sense[SCSI_Sense_Tail].Skey = (char)sKey;
- SCSI_Sense[SCSI_Sense_Tail].w.ASC = (uint32_t)ASC << 8U;
- SCSI_Sense_Tail++;
- if (SCSI_Sense_Tail == SENSE_LIST_DEEPTH) {
- SCSI_Sense_Tail = 0U;
- }
-}
-
-/**
- * @brief processes Start Stop Unit command
- * @param None
- * @retval status
- */
-int8_t scsi_startstopuint(void)
-{
- MSC_BOT_DataLen = 0U;
- return (int8_t)0;
-}
-
-/**
- * @brief processes Read10 command
- * @param [in] lun number of logical unit
- * @param [in] params command
- * @retval status
- */
-int8_t scsi_read10(uint8_t lun, uint8_t *params)
-{
- int8_t i8Ret = (int8_t)0;
- if (MSC_BOT_State == BOT_IDLE) {
- /* case 10 : Ho <> Di */
- if ((MSC_BOT_cbw.bmFlags & 0x80U) != 0x80U) {
- scsi_sensecode(ILLEGAL_REQUEST, INVALID_CDB);
- i8Ret = (int8_t) -1;
- } else if (msc_fops->IsReady(lun) != 0U) {
- scsi_sensecode(NOT_READY, MEDIUM_NOT_PRESENT);
- i8Ret = (int8_t) -1;
- } else {
- SCSI_blk_addr = ((uint64_t)params[2] << 24U) | \
- ((uint64_t)params[3] << 16U) | \
- ((uint64_t)params[4] << 8U) | \
- (uint64_t)params[5];
-
- SCSI_blk_len = ((uint32_t)params[7] << 8U) | \
- (uint32_t)params[8];
-
- if (scsi_addressrangecheck((uint32_t)SCSI_blk_addr, (uint16_t)SCSI_blk_len) < 0) {
- i8Ret = (int8_t) -1; /* error */
- } else {
- MSC_BOT_State = BOT_DATA_IN;
- SCSI_blk_addr *= SCSI_blk_size;
- SCSI_blk_len *= SCSI_blk_size;
- /* cases 4,5 : Hi <> Dn */
- if (MSC_BOT_cbw.dDataLength != SCSI_blk_len) {
- scsi_sensecode(ILLEGAL_REQUEST, INVALID_CDB);
- i8Ret = (int8_t) -1;
- }
- }
- }
- }
- if (((int8_t) -1) != i8Ret) {
- MSC_BOT_DataLen = (uint16_t)MSC_MEDIA_PACKET;
- i8Ret = scsi_processread(lun);
- }
- return i8Ret;
-}
-
-/**
- * @brief processes Write10 command
- * @param [in] lun number of logical unit
- * @param [in] params command
- * @retval status
- */
-int8_t scsi_write10(uint8_t lun, uint8_t *params)
-{
- int8_t i8Ret = (int8_t)0;
- if (MSC_BOT_State == BOT_IDLE) {
- /* case 8 : Hi <> Do */
- if ((MSC_BOT_cbw.bmFlags & 0x80U) == 0x80U) {
- scsi_sensecode(ILLEGAL_REQUEST, INVALID_CDB);
- i8Ret = (int8_t) -1;
- } else {
- if (msc_fops->IsReady(lun) != 0U) {
- scsi_sensecode(NOT_READY, MEDIUM_NOT_PRESENT);
- i8Ret = (int8_t) -1;
- }
- /* Check If media is write-protected */
- else if (msc_fops->IsWriteProtected(lun) != 0U) {
- scsi_sensecode(NOT_READY, WRITE_PROTECTED);
- i8Ret = (int8_t) -1;
- } else {
- SCSI_blk_addr = ((uint64_t)params[2] << 24U) | \
- ((uint64_t)params[3] << 16U) | \
- ((uint64_t)params[4] << 8U) | \
- (uint64_t)params[5];
- SCSI_blk_len = ((uint32_t)params[7] << 8U) | \
- (uint32_t)params[8];
- /* check if LBA address is in the right range */
- if (scsi_addressrangecheck((uint32_t)SCSI_blk_addr, (uint16_t)SCSI_blk_len) < 0) {
- i8Ret = (int8_t) -1; /* error */
- } else {
- SCSI_blk_addr *= SCSI_blk_size;
- SCSI_blk_len *= SCSI_blk_size;
- /* cases 3,11,13 : Hn,Ho <> D0 */
- if (MSC_BOT_cbw.dDataLength != SCSI_blk_len) {
- scsi_sensecode(ILLEGAL_REQUEST, INVALID_CDB);
- i8Ret = (int8_t) -1;
- } else {
- /* Prepare EP to receive first data packet */
- MSC_BOT_State = BOT_DATA_OUT;
- usb_readytorx(cdev, MSC_OUT_EP, MSC_BOT_Data, (uint16_t)LL_MIN(SCSI_blk_len, MSC_MEDIA_PACKET));
- }
- }
- }
- }
- } else { /* Write Process ongoing */
- i8Ret = scsi_processwrite(lun);
- }
- return i8Ret;
-}
-
-/**
- * @brief processes Verify10 command
- * @param [in] lun number of logical unit
- * @param [in] params command
- * @retval status
- */
-int8_t scsi_verify10(uint8_t lun, uint8_t *params)
-{
- int8_t i8Ret;
-
- i8Ret = (int8_t)0;
- if ((params[1] & 0x02U) == 0x02U) {
- scsi_sensecode(ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND);
- i8Ret = (int8_t) -1; /* Error, Verify Mode Not supported */
- } else if (scsi_addressrangecheck((uint32_t)SCSI_blk_addr, (uint16_t)SCSI_blk_len) < (int8_t)0) {
- i8Ret = (int8_t) -1; /* error */
- } else {
- MSC_BOT_DataLen = 0U;
- }
- return i8Ret;
-}
-
-/**
- * @brief checks the address range
- * @param [in] blk_offset first block address
- * @param [in] blk_nbr number of block to be processed
- * @retval status
- */
-int8_t scsi_addressrangecheck(uint32_t blk_offset, uint16_t blk_nbr)
-{
- int8_t i8Ret = (int8_t)0;
- if ((blk_offset + blk_nbr) > SCSI_blk_nbr) {
- scsi_sensecode(ILLEGAL_REQUEST, ADDRESS_OUT_OF_RANGE);
- i8Ret = (int8_t) -1;
- }
- return i8Ret;
-}
-
-/**
- * @brief handles Read Process
- * @param [in] lun number of logical unit
- * @retval status
- */
-int8_t scsi_processread(uint8_t lun)
-{
- uint32_t len;
- int8_t i8Ret = (int8_t)0;
-
- len = LL_MIN(SCSI_blk_len, MSC_MEDIA_PACKET);
-
- if (SCSI_blk_size == 0U) {
- i8Ret = (int8_t) -1;
- } else if (msc_fops->Read(lun, MSC_BOT_Data, SCSI_blk_addr / SCSI_blk_size, len / SCSI_blk_size) < 0) {
- scsi_sensecode(HARDWARE_ERROR, UNRECOVERED_READ_ERROR);
- i8Ret = (int8_t) -1;
- } else {
- usb_deveptx(cdev, MSC_IN_EP, MSC_BOT_Data, len);
- SCSI_blk_addr += len;
- SCSI_blk_len -= len;
- /* case 6 : Hi = Di */
- MSC_BOT_csw.dDataResidue -= len;
- if (SCSI_blk_len == 0U) {
- MSC_BOT_State = BOT_LAST_DATA_IN;
- }
- }
- return i8Ret;
-}
-
-/**
- * @brief handles Write Process
- * @param [in] lun number of logical unit
- * @retval status
- */
-int8_t scsi_processwrite(uint8_t lun)
-{
- uint32_t len;
- int8_t i8Ret = (int8_t)0;
-
- len = LL_MIN(SCSI_blk_len, MSC_MEDIA_PACKET);
-
- if (SCSI_blk_size == 0U) {
- i8Ret = (int8_t) -1;
- } else if (msc_fops->Write(lun, MSC_BOT_Data, SCSI_blk_addr / SCSI_blk_size, len / SCSI_blk_size) < 0) {
- scsi_sensecode(HARDWARE_ERROR, WRITE_FAULT);
- i8Ret = (int8_t) -1;
- } else {
- SCSI_blk_addr += len;
- SCSI_blk_len -= len;
- /* case 12 : Ho = Do */
- MSC_BOT_csw.dDataResidue -= len;
- if (SCSI_blk_len == 0U) {
- msc_bot_txcsw(cdev, CSW_CMD_PASSED);
- } else {
- /* Prapare EP to Receive next packet */
- usb_readytorx(cdev, MSC_OUT_EP, MSC_BOT_Data, (uint16_t)LL_MIN(SCSI_blk_len, MSC_MEDIA_PACKET));
- }
- }
- return i8Ret;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_scsi.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_scsi.h
deleted file mode 100644
index bbf33536e4..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_scsi.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_msc_scsi.h
- * @brief header file for the usb_dev_msc_scsi.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_DEV_MSC_SCSI_H__
-#define __USB_DEV_MSC_SCSI_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_def.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_MSC
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-typedef struct _SENSE_ITEM {
- char Skey;
- union {
- struct _ASCs {
- char ASC;
- char ASCQ;
- } b;
- unsigned int ASC;
- char *pData;
- } w;
-} SCSI_Sense_TypeDef;
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#define SENSE_LIST_DEEPTH (4U)
-
-/* SCSI Commands */
-#define SCSI_FORMAT_UNIT (0x04U)
-#define SCSI_INQUIRY (0x12U)
-#define SCSI_MODE_SELECT6 (0x15U)
-#define SCSI_MODE_SELECT10 (0x55U)
-#define SCSI_MODE_SENSE6 (0x1AU)
-#define SCSI_MODE_SENSE10 (0x5AU)
-#define SCSI_ALLOW_MEDIUM_REMOVAL (0x1EU)
-#define SCSI_READ6 (0x08U)
-#define SCSI_READ10 (0x28U)
-#define SCSI_READ12 (0xA8U)
-#define SCSI_READ16 (0x88U)
-
-#define SCSI_READ_CAPACITY10 (0x25U)
-#define SCSI_READ_CAPACITY16 (0x9EU)
-
-#define SCSI_REQUEST_SENSE (0x03U)
-#define SCSI_START_STOP_UNIT (0x1BU)
-#define SCSI_TEST_UNIT_READY (0x00U)
-#define SCSI_WRITE6 (0x0AU)
-#define SCSI_WRITE10 (0x2AU)
-#define SCSI_WRITE12 (0xAAU)
-#define SCSI_WRITE16 (0x8AU)
-
-#define SCSI_VERIFY10 (0x2FU)
-#define SCSI_VERIFY12 (0xAFU)
-#define SCSI_VERIFY16 (0x8FU)
-
-#define SCSI_SEND_DIAGNOSTIC (0x1DU)
-#define SCSI_READ_FORMAT_CAPACITIES (0x23U)
-
-#define NO_SENSE (0U)
-#define RECOVERED_ERROR (1U)
-#define NOT_READY (2U)
-#define MEDIUM_ERROR (3U)
-#define HARDWARE_ERROR (4U)
-#define ILLEGAL_REQUEST (5U)
-#define UNIT_ATTENTION (6U)
-#define DATA_PROTECT (7U)
-#define BLANK_CHECK (8U)
-#define VENDOR_SPECIFIC (9U)
-#define COPY_ABORTED (10U)
-#define ABORTED_COMMAND (11U)
-#define VOLUME_OVERFLOW (13U)
-#define MISCOMPARE (14U)
-
-#define INVALID_CDB (0x20U)
-#define INVALID_FIELED_IN_COMMAND (0x24U)
-#define PARAMETER_LIST_LENGTH_ERROR (0x1AU)
-#define INVALID_FIELD_IN_PARAMETER_LIST (0x26U)
-#define ADDRESS_OUT_OF_RANGE (0x21U)
-#define MEDIUM_NOT_PRESENT (0x3AU)
-#define MEDIUM_HAVE_CHANGED (0x28U)
-#define WRITE_PROTECTED (0x27U)
-#define UNRECOVERED_READ_ERROR (0x11U)
-#define WRITE_FAULT (0x03U)
-
-#define READ_FORMAT_CAPACITY_DATA_LEN (0x0Cu)
-#define READ_CAPACITY10_DATA_LEN (0x08U)
-#define MODE_SENSE10_DATA_LEN (0x08U)
-#define MODE_SENSE6_DATA_LEN (0x04U)
-#define REQUEST_SENSE_DATA_LEN (0x12U)
-#define STANDARD_INQUIRY_DATA_LEN (0x24U)
-#define BLKVFY (0x04U)
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-extern SCSI_Sense_TypeDef SCSI_Sense [SENSE_LIST_DEEPTH];
-extern uint8_t SCSI_Sense_Head;
-extern uint8_t SCSI_Sense_Tail;
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-extern int8_t scsi_cmdprocess(usb_core_instance *pdev, uint8_t lun, uint8_t *params);
-extern void scsi_sensecode(uint8_t sKey, uint8_t ASC);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_DEV_MSC_SCSI_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/single_cdc/usb_dev_cdc_class.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/single_cdc/usb_dev_cdc_class.c
deleted file mode 100644
index 014770ff50..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/single_cdc/usb_dev_cdc_class.c
+++ /dev/null
@@ -1,427 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_cdc_class.c
- * @brief The CDC VCP core functions.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_cdc_class.h"
-#include "usb_dev_driver.h"
-#include "usb_dev_ctrleptrans.h"
-#include "usb_dev_stdreq.h"
-#include "usb_dev_desc.h"
-#include "cdc_data_process.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_SINGLE_CDC USB Device CDC
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-uint8_t *usb_dev_cdc_getcfgdesc(uint16_t *length);
-void process_asynchdata_uart2usb(void *pdev);
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-usb_dev_class_func class_cdc_cbk = {
- &usb_dev_cdc_init,
- &usb_dev_cdc_deinit,
- &usb_dev_cdc_setup,
- NULL,
- &usb_dev_cdc_ctrlep_rxready,
- &usb_dev_cdc_getcfgdesc,
- &usb_dev_cdc_sof,
- &usb_dev_cdc_datain,
- &usb_dev_cdc_dataout,
- NULL,
- NULL,
-};
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-__USB_ALIGN_BEGIN static uint32_t alternate_setting = 0UL;
-__USB_ALIGN_BEGIN static uint8_t usb_rx_buffer[MAX_CDC_PACKET_SIZE];
-uint8_t uart_rx_buffer[APP_RX_DATA_SIZE]; /* used as a buffer for receiving data from uart port */
-__USB_ALIGN_BEGIN static uint8_t CmdBuff[CDC_CMD_PACKET_SIZE];
-uint32_t APP_Rx_ptr_in = 0UL;
-uint32_t APP_Rx_ptr_out = 0UL;
-static uint32_t APP_Rx_length = 0UL;
-static uint8_t USB_Tx_State = 0U;
-static uint32_t cdcCmd = 0xFFUL;
-static uint32_t cdcLen = 0UL;
-static uint32_t LastPackLen = 0UL;
-
-__USB_ALIGN_BEGIN static uint8_t usb_dev_cdc_cfgdesc[USB_CDC_CONFIG_DESC_SIZ] = {
- 0x09,
- USB_CFG_DESCRIPTOR_TYPE,
- USB_CDC_CONFIG_DESC_SIZ,
- 0x00,
- 0x02,
- 0x01,
- 0x00,
- 0xC0,
- 0x32,
-
- 0x08,
- 0x0B,
- 0x00,
- 0x02,
- 0x02,
- 0x02,
- 0x01,
- 0x04,
-
- 0x09,
- USB_INTERFACE_DESCRIPTOR_TYPE,
- 0x00,
- 0x00,
- 0x01,
- 0x02,
- 0x02,
- 0x01,
- 0x00,
-
- 0x05,
- 0x24,
- 0x00,
- 0x10,
- 0x01,
-
- 0x05,
- 0x24,
- 0x01,
- 0x00,
- 0x01,
-
- 0x04,
- 0x24,
- 0x02,
- 0x02,
-
- 0x05,
- 0x24,
- 0x06,
- 0x00,
- 0x01,
-
- 0x07,
- USB_ENDPOINT_DESCRIPTOR_TYPE,
- CDC_CMD_EP,
- 0x03,
- LOBYTE(CDC_CMD_PACKET_SIZE),
- HIBYTE(CDC_CMD_PACKET_SIZE),
- 0xFF,
-
- 0x09,
- USB_INTERFACE_DESCRIPTOR_TYPE,
- 0x01,
- 0x00,
- 0x02,
- 0x0A,
- 0x00,
- 0x00,
- 0x00,
-
- 0x07,
- USB_ENDPOINT_DESCRIPTOR_TYPE,
- CDC_OUT_EP,
- 0x02,
- LOBYTE(MAX_CDC_PACKET_SIZE),
- HIBYTE(MAX_CDC_PACKET_SIZE),
- 0x00,
-
- 0x07,
- USB_ENDPOINT_DESCRIPTOR_TYPE,
- CDC_IN_EP,
- 0x02,
- LOBYTE(MAX_CDC_PACKET_SIZE),
- HIBYTE(MAX_CDC_PACKET_SIZE),
- 0x00
-} ;
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-/**
- * @brief Initilaize the CDC application
- * @param [in] pdev Device instance
- * @retval None
- */
-void usb_dev_cdc_init(void *pdev)
-{
- usb_opendevep(pdev, CDC_IN_EP, MAX_CDC_IN_PACKET_SIZE, EP_TYPE_BULK);
- usb_opendevep(pdev, CDC_OUT_EP, MAX_CDC_OUT_PACKET_SIZE, EP_TYPE_BULK);
- usb_opendevep(pdev, CDC_CMD_EP, CDC_CMD_PACKET_SIZE, EP_TYPE_INTR);
- vcp_init();
- usb_readytorx(pdev, CDC_OUT_EP, (uint8_t *)(usb_rx_buffer), MAX_CDC_OUT_PACKET_SIZE);
-}
-
-/**
- * @brief Deinitialize the CDC application
- * @param [in] pdev Device instance
- * @retval None
- */
-void usb_dev_cdc_deinit(void *pdev)
-{
- usb_shutdevep(pdev, CDC_IN_EP);
- usb_shutdevep(pdev, CDC_OUT_EP);
- usb_shutdevep(pdev, CDC_CMD_EP);
- vcp_deinit();
-}
-
-/**
- * @brief Handle the setup requests
- * @param [in] pdev Device instance
- * @param [in] req usb requests
- * @retval status
- */
-uint8_t usb_dev_cdc_setup(void *pdev, USB_SETUP_REQ *req)
-{
- uint16_t len = USB_CDC_DESC_SIZ;
- uint8_t *pbuf = usb_dev_cdc_cfgdesc + 9;
- uint8_t u8Res = USB_DEV_OK;
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK) {
- case USB_REQ_TYPE_CLASS :
- if (req->wLength != 0U) {
- if ((req->bmRequest & 0x80U) != 0U) {
- vcp_ctrlpare(req->bRequest, CmdBuff, req->wLength);
- usb_ctrldatatx(pdev, CmdBuff, req->wLength);
- } else {
- cdcCmd = req->bRequest;
- cdcLen = req->wLength;
- usb_ctrldatarx(pdev, CmdBuff, req->wLength);
- }
- } else {
- vcp_ctrlpare(req->bRequest, NULL, 0UL);
- }
- break;
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest) {
- case USB_REQ_GET_DESCRIPTOR:
- if ((req->wValue >> 8) == CDC_DESCRIPTOR_TYPE) {
- pbuf = usb_dev_cdc_cfgdesc + 9U + (9U * USBD_ITF_MAX_NUM);
- len = LL_MIN(USB_CDC_DESC_SIZ, req->wLength);
- }
- usb_ctrldatatx(pdev, pbuf, len);
- break;
-
- case USB_REQ_GET_INTERFACE :
- usb_ctrldatatx(pdev, (uint8_t *)&alternate_setting, 1U);
- break;
-
- case USB_REQ_SET_INTERFACE :
- if ((uint8_t)(req->wValue) < USBD_ITF_MAX_NUM) {
- alternate_setting = (uint8_t)(req->wValue);
- } else {
- usb_ctrlerr(pdev);
- }
- break;
- default:
- break;
- }
- break;
-
- default:
- usb_ctrlerr(pdev);
- u8Res = USB_DEV_FAIL;
- break;
- }
- return u8Res;
-}
-
-/**
- * @brief Data received on control endpoint
- * @param [in] pdev device device instance
- * @retval None
- */
-void usb_dev_cdc_ctrlep_rxready(void *pdev)
-{
- if (cdcCmd != NO_CMD) {
- vcp_ctrlpare(cdcCmd, CmdBuff, cdcLen);
- cdcCmd = NO_CMD;
- }
-}
-
-/**
- * @brief Data sent on non-control IN endpoint
- * @param [in] pdev Device instance
- * @param [in] epnum endpoint index
- * @retval None
- */
-void usb_dev_cdc_datain(void *pdev, uint8_t epnum)
-{
- uint16_t tx2usb_ptr;
- uint16_t tx2usb_length;
-
- if (USB_Tx_State == 1U) {
- if (APP_Rx_length == 0U) {
- if (LastPackLen == MAX_CDC_IN_PACKET_SIZE) {
- usb_deveptx(pdev, CDC_IN_EP, NULL, 0UL);
- LastPackLen = 0UL;
- } else {
- USB_Tx_State = 0U;
- }
- } else {
- if (APP_Rx_length >= MAX_CDC_IN_PACKET_SIZE) {
- tx2usb_ptr = (uint16_t)APP_Rx_ptr_out;
- tx2usb_length = (uint16_t)MAX_CDC_IN_PACKET_SIZE - 1U;
- APP_Rx_ptr_out += MAX_CDC_IN_PACKET_SIZE - 1U;
- APP_Rx_length -= MAX_CDC_IN_PACKET_SIZE - 1U;
- } else {
- tx2usb_ptr = (uint16_t)APP_Rx_ptr_out;
- tx2usb_length = (uint16_t)APP_Rx_length;
- APP_Rx_ptr_out += APP_Rx_length;
- APP_Rx_length = 0U;
- }
- usb_deveptx(pdev,
- CDC_IN_EP,
- (uint8_t *)&uart_rx_buffer[tx2usb_ptr],
- (uint32_t)tx2usb_length);
- LastPackLen = (uint32_t)tx2usb_length;
- }
- }
-}
-
-/**
- * @brief Data received on non-control Out endpoint
- * @param [in] pdev device instance
- * @param [in] epnum endpoint index
- * @retval None
- */
-void usb_dev_cdc_dataout(void *pdev, uint8_t epnum)
-{
- uint16_t usb_rx_cnt;
-
- usb_rx_cnt = (uint16_t)((usb_core_instance *)pdev)->dev.out_ep[epnum].xfer_count;
- vcp_rxdata(usb_rx_buffer, usb_rx_cnt);
- usb_readytorx(pdev, CDC_OUT_EP, (uint8_t *)(usb_rx_buffer), MAX_CDC_OUT_PACKET_SIZE);
-}
-
-/**
- * @brief Start Of Frame event management
- * @param [in] pdev Device instance
- * @retval status
- */
-uint8_t usb_dev_cdc_sof(void *pdev)
-{
- static uint32_t FrameCount = 0UL;
-
- if (FrameCount++ == CDC_IN_FRAME_INTERVAL) {
- FrameCount = 0UL;
- process_asynchdata_uart2usb(pdev);
- }
- return USB_DEV_OK;
-}
-
-/**
- * @brief process the data received from usart and send through USB to host
- * @param [in] pdev device instance
- * @retval None
- */
-void process_asynchdata_uart2usb(void *pdev)
-{
- uint16_t tx2usb_ptr; /* the location of the pointer in buffer that would be sent to USB */
- uint16_t tx2usb_length; /* the length in bytes that would be sent to USB */
-
- if (USB_Tx_State != 1U) {
- if (APP_Rx_ptr_out == APP_RX_DATA_SIZE) {
- APP_Rx_ptr_out = 0UL;
- }
- if (APP_Rx_ptr_out == APP_Rx_ptr_in) {
- USB_Tx_State = 0U;
- } else {
- if (APP_Rx_ptr_out > APP_Rx_ptr_in) {
- APP_Rx_length = APP_RX_DATA_SIZE - APP_Rx_ptr_out;
- } else {
- APP_Rx_length = APP_Rx_ptr_in - APP_Rx_ptr_out;
- }
-
- if (APP_Rx_length >= MAX_CDC_IN_PACKET_SIZE) {
- tx2usb_ptr = (uint16_t)APP_Rx_ptr_out;
- tx2usb_length = MAX_CDC_IN_PACKET_SIZE - 1U;
-
- APP_Rx_ptr_out += MAX_CDC_IN_PACKET_SIZE - 1UL;
- APP_Rx_length -= MAX_CDC_IN_PACKET_SIZE - 1UL;
- } else {
- tx2usb_ptr = (uint16_t)APP_Rx_ptr_out;
- tx2usb_length = (uint16_t)APP_Rx_length;
-
- APP_Rx_ptr_out += APP_Rx_length;
- APP_Rx_length = 0UL;
- }
- USB_Tx_State = 1U;
-
- usb_deveptx(pdev,
- CDC_IN_EP,
- (uint8_t *)&uart_rx_buffer[tx2usb_ptr],
- (uint32_t)tx2usb_length);
- LastPackLen = (uint32_t)tx2usb_length;
- }
- }
-}
-
-/**
- * @brief get the configuration descriptor
- * @param [in] length length of configuration descriptor in bytes
- * @retval the pointer to configuration descriptor buffer
- */
-uint8_t *usb_dev_cdc_getcfgdesc(uint16_t *length)
-{
- *length = (uint16_t)sizeof(usb_dev_cdc_cfgdesc);
- return usb_dev_cdc_cfgdesc;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/single_cdc/usb_dev_cdc_class.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/single_cdc/usb_dev_cdc_class.h
deleted file mode 100644
index 63e93d378f..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/single_cdc/usb_dev_cdc_class.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_cdc_class.h
- * @brief Head file for usb_dev_cdc_class.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_DEV_CDC_CLASS_H__
-#define __USB_DEV_CDC_CLASS_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_def.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_SINGLE_CDC
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#define USB_CDC_CONFIG_DESC_SIZ (75U)
-#define USB_CDC_DESC_SIZ (75U-9U)
-
-#define CDC_DESCRIPTOR_TYPE (0x21U)
-
-#define DEVICE_CLASS_CDC (0x02U)
-#define DEVICE_SUBCLASS_CDC (0x00U)
-
-#define STANDARD_ENDPOINT_DESC_SIZE (0x09U)
-
-#define MAX_CDC_IN_PACKET_SIZE (MAX_CDC_PACKET_SIZE)
-
-#define MAX_CDC_OUT_PACKET_SIZE (MAX_CDC_PACKET_SIZE)
-
-/**************************************************/
-/* CDC Requests */
-/**************************************************/
-#define SEND_ENCAPSULATED_COMMAND (0x00U)
-#define GET_ENCAPSULATED_RESPONSE (0x01U)
-#define SET_COMM_FEATURE (0x02U)
-#define GET_COMM_FEATURE (0x03U)
-#define CLEAR_COMM_FEATURE (0x04U)
-#define SET_LINE_CODING (0x20U)
-#define GET_LINE_CODING (0x21U)
-#define SET_CONTROL_LINE_STATE (0x22U)
-#define SEND_BREAK (0x23U)
-#define NO_CMD (0xFFU)
-
-extern uint8_t uart_rx_buffer[APP_RX_DATA_SIZE];
-extern uint32_t APP_Rx_ptr_in;
-extern uint32_t APP_Rx_ptr_out;
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-extern usb_dev_class_func class_cdc_cbk;
-
-/* CDC Device library callbacks */
-extern void usb_dev_cdc_init(void *pdev);;
-extern void usb_dev_cdc_deinit(void *pdev);
-extern uint8_t usb_dev_cdc_setup(void *pdev, USB_SETUP_REQ *req);
-extern void usb_dev_cdc_datain(void *pdev, uint8_t epnum);
-extern void usb_dev_cdc_dataout(void *pdev, uint8_t epnum);
-extern void usb_dev_cdc_ctrlep_rxready(void *pdev);
-extern uint8_t usb_dev_cdc_sof(void *pdev);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_DEV_CDC_CLASS_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_core.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_core.c
deleted file mode 100644
index 61c80009cb..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_core.c
+++ /dev/null
@@ -1,344 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_core.c
- * @brief USBD core functions.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2022-06-30 CDT Add USB core ID select function
- Modify for MISRAC
- 2023-06-30 CDT Typo: Initailizes -> Initializes
- 2023-09-30 CDT Modify API usb_dev_resume()
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_core.h"
-#include "usb_dev_stdreq.h"
-#include "usb_dev_ctrleptrans.h"
-#include "usb_dev_driver.h"
-#include "usb_dev_int.h"
-#include "usb_bsp.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CORE LL USB Device Core
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-void usb_setup_process(usb_core_instance *pdev);
-void usb_dataout_process(usb_core_instance *pdev, uint8_t epnum);
-void usb_datain_process(usb_core_instance *pdev, uint8_t epnum);
-void usb_sof_process(usb_core_instance *pdev);
-void usb_dev_rst(usb_core_instance *pdev);
-void usb_dev_susp(usb_core_instance *pdev);
-void usb_dev_resume(usb_core_instance *pdev);
-void usb_ctrlconn(usb_core_instance *pdev, uint8_t conn);
-void usb_isoinincomplt_process(usb_core_instance *pdev);
-void usb_isooutincomplt_process(usb_core_instance *pdev);
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-__IO uint32_t SET_TEST_MODE;
-static usb_dev_int_cbk_typedef dev_int_cbk = {
- &usb_dev_rst,
- &usb_ctrlconn,
- &usb_dev_susp,
- &usb_dev_resume,
- &usb_sof_process,
- &usb_setup_process,
- &usb_dataout_process,
- &usb_datain_process,
- &usb_isoinincomplt_process,
- &usb_isooutincomplt_process
-};
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-usb_dev_int_cbk_typedef *dev_int_cbkpr = &dev_int_cbk;
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @brief Initializes the device stack and load the class driver
- * @param [in] pdev device instance
- * @param [in] pstcPortIdentify usb core and phy select
- * @param [in] pdesc Device Descriptor
- * @param [in] class_cb Class callback structure address
- * @param [in] usr_cb User callback structure address
- * @retval None
- */
-void usb_dev_init(usb_core_instance *pdev,
- stc_usb_port_identify *pstcPortIdentify,
- usb_dev_desc_func *pdesc,
- usb_dev_class_func *class_cb,
- usb_dev_user_func *usr_cb)
-{
- usb_bsp_init(pdev, pstcPortIdentify);
- pdev->dev.class_callback = class_cb;
- pdev->dev.user_callback = usr_cb;
- pdev->dev.desc_callback = pdesc;
- usb_initdev(pdev, pstcPortIdentify);
- pdev->dev.user_callback->user_init();
- pdev->dev.device_state = USB_EP0_IDLE;
- usb_bsp_nvicconfig(pdev);
-}
-
-/**
- * @brief De-Initializes the device stack and load the class driver
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_dev_deinit(usb_core_instance *pdev)
-{
- (void)(pdev);
-}
-
-/**
- * @brief Handle Reset event
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_dev_rst(usb_core_instance *pdev)
-{
- usb_opendevep(pdev, 0x00U, USB_MAX_EP0_SIZE, EP_TYPE_CTRL);
- usb_opendevep(pdev, 0x80U, USB_MAX_EP0_SIZE, EP_TYPE_CTRL);
- pdev->dev.device_cur_status = USB_DEV_DEFAULT;
- pdev->dev.user_callback->user_devrst();
-}
-
-/**
- * @brief Handle device connection and disconnection event
- * @param [in] pdev device instance
- * @param [in] conn 1 or 0
- * @retval None
- */
-void usb_ctrlconn(usb_core_instance *pdev, uint8_t conn)
-{
- __IO uint8_t tmp_1;
- tmp_1 = conn;
- if (tmp_1 != 0U) {
- pdev->dev.user_callback->user_devconn();
- pdev->dev.connection_status = 1U;
- } else {
- pdev->dev.user_callback->user_devdisconn();
- pdev->dev.class_callback->class_deinit(pdev);
- pdev->dev.connection_status = 0U;
- }
-}
-
-/**
- * @brief Handle Suspend event
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_dev_susp(usb_core_instance *pdev)
-{
- pdev->dev.device_old_status = pdev->dev.device_cur_status;
- pdev->dev.device_cur_status = USB_DEV_SUSPENDED;
- pdev->dev.user_callback->user_devsusp();
-}
-
-/**
- * @brief Handle Resume event
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_dev_resume(usb_core_instance *pdev)
-{
- pdev->dev.user_callback->user_devresume();
- pdev->dev.device_cur_status = pdev->dev.device_old_status;
-}
-
-/**
- * @brief Handle SOF event
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_sof_process(usb_core_instance *pdev)
-{
- if (0U != pdev->dev.class_callback->class_sof) {
- pdev->dev.class_callback->class_sof(pdev);
- }
-}
-
-/**
- * @brief Handle the setup stage
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_setup_process(usb_core_instance *pdev)
-{
- USB_SETUP_REQ req;
-
- usb_parsesetupreq(pdev, &req);
-
- switch (req.bmRequest & 0x1FU) {
- case USB_REQ_RECIPIENT_DEVICE:
- usb_standarddevreq(pdev, &req);
- break;
-
- case USB_REQ_RECIPIENT_INTERFACE:
- usb_standarditfreq(pdev, &req);
- break;
-
- case USB_REQ_RECIPIENT_ENDPOINT:
- usb_standardepreq(pdev, &req);
- break;
-
- default:
- usb_stalldevep(pdev, req.bmRequest & 0x80U);
- break;
- }
-}
-
-/**
- * @brief Handle data out stage
- * @param [in] pdev device instance
- * @param [in] epnum endpoint index
- * @retval None
- */
-void usb_dataout_process(usb_core_instance *pdev, uint8_t epnum)
-{
- USB_DEV_EP *ep;
-
- if (epnum == 0U) {
- ep = &pdev->dev.out_ep[0];
- if (pdev->dev.device_state == USB_EP0_DATA_OUT) {
- if (ep->rem_data_len > ep->maxpacket) {
- ep->rem_data_len -= ep->maxpacket;
-
- if (pdev->basic_cfgs.dmaen == 1U) {
- /* in slave mode this, is handled by the RxSTSQLvl ISR */
- ep->xfer_buff += ep->maxpacket;
- }
- usb_readytorx(pdev, 0U, ep->xfer_buff, (uint16_t)LL_MIN(ep->rem_data_len, ep->maxpacket));
- } else {
- if (ep->xfer_count > ep->rem_data_len) {
-
- }
- ep->rem_data_len = 0UL;
- if ((pdev->dev.device_cur_status == USB_DEV_CONFIGURED) &&
- (pdev->dev.class_callback->ep0_dataout != NULL)) {
- pdev->dev.class_callback->ep0_dataout(pdev);
- }
- usb_ctrlstatustx(pdev);
- }
- }
- } else if ((pdev->dev.device_cur_status == USB_DEV_CONFIGURED) && (pdev->dev.class_callback->class_dataout != NULL)) {
- pdev->dev.class_callback->class_dataout(pdev, epnum);
- } else {
- ;
- }
-}
-
-/**
- * @brief Handle data in stage
- * @param [in] pdev device instance
- * @param [in] epnum endpoint index
- * @retval None
- */
-void usb_datain_process(usb_core_instance *pdev, uint8_t epnum)
-{
- USB_DEV_EP *ep;
-
- if (epnum == 0U) {
- ep = &pdev->dev.in_ep[0];
- if (pdev->dev.device_state == USB_EP0_DATA_IN) {
- if (ep->rem_data_len > ep->maxpacket) {
- ep->rem_data_len -= ep->maxpacket;
- if (pdev->basic_cfgs.dmaen == 1U) {
- /* in slave mode this, is handled by the TxFifoEmpty ISR */
- ep->xfer_buff += ep->maxpacket;
- }
- usb_deveptx(pdev, 0U, ep->xfer_buff, ep->rem_data_len);
- } else {
- /* last packet is MPS multiple, so send ZLP packet */
- if ((ep->total_data_len % ep->maxpacket == 0U) &&
- (ep->total_data_len >= ep->maxpacket) &&
- (ep->total_data_len < ep->ctl_data_len)) {
- usb_deveptx(pdev, 0U, NULL, 0UL);
- ep->ctl_data_len = 0UL;
- } else {
- if ((pdev->dev.device_cur_status == USB_DEV_CONFIGURED) &&
- (pdev->dev.class_callback->ep0_datain != NULL)) {
- pdev->dev.class_callback->ep0_datain(pdev);
- }
- usb_ctrlstatusrx(pdev);
- }
- }
- }
- if (pdev->dev.test_mode == 1U) {
- usb_runtestmode(&pdev->regs, SET_TEST_MODE);
- pdev->dev.test_mode = 0U;
- } else {
- }
- } else if ((pdev->dev.device_cur_status == USB_DEV_CONFIGURED) && (pdev->dev.class_callback->class_datain != NULL)) {
- pdev->dev.class_callback->class_datain(pdev, epnum);
- } else {
- ;
- }
-}
-
-/**
- * @brief Handle iso in incomplete event
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_isoinincomplt_process(usb_core_instance *pdev)
-{
- pdev->dev.class_callback->class_syn_in_incomplt(pdev);
-}
-
-/**
- * @brief Handle iso out incomplete event
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_isooutincomplt_process(usb_core_instance *pdev)
-{
- pdev->dev.class_callback->class_syn_out_incomplt(pdev);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_core.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_core.h
deleted file mode 100644
index 2bdca3b650..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_core.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_core.h
- * @brief header file for the usb_dev_core.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2022-06-30 CDT Add USB core ID select function
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_DEV_CORE_H__
-#define __USB_DEV_CORE_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_def.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CORE
- * @{
- */
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-extern __IO uint32_t SET_TEST_MODE;
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-extern void usb_dev_init(usb_core_instance *pdev,
- stc_usb_port_identify *pstcPortIdentify,
- usb_dev_desc_func *pdesc,
- usb_dev_class_func *class_cb,
- usb_dev_user_func *usr_cb);
-extern void usb_dev_deinit(usb_core_instance *pdev);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_DEV_CORE_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_ctrleptrans.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_ctrleptrans.c
deleted file mode 100644
index e3cc60763c..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_ctrleptrans.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_ctrleptrans.c
- * @brief The IO requests APIs for control endpoints.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_ctrleptrans.h"
-#include "usb_dev_driver.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CORE
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @brief send data on the ctl pipe
- * @param [in] pdev device instance
- * @param [in] pbuf pointer to data buffer
- * @param [in] len length of data to be sent
- * @retval None
- */
-void usb_ctrldatatx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len)
-{
- pdev->dev.in_ep[0].total_data_len = (uint32_t)len;
- pdev->dev.in_ep[0].rem_data_len = (uint32_t)len;
- pdev->dev.device_state = USB_EP0_DATA_IN;
-
- usb_deveptx(pdev, 0U, pbuf, (uint32_t)len);
-}
-
-/**
- * @brief continue sending data on the ctl pipe
- * @param [in] pdev device instance
- * @param [in] pbuf pointer to data buffer
- * @param [in] len length of data to be sent
- * @retval None
- */
-void usb_ctrldatacontinuetx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len)
-{
- usb_deveptx(pdev, 0U, pbuf, (uint32_t)len);
-}
-
-/**
- * @brief receive data on the ctl pipe
- * @param [in] pdev device instance
- * @param [in] pbuf pointer to data buffer
- * @param [in] len length of data to be received
- * @retval status
- */
-void usb_ctrldatarx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len)
-{
- pdev->dev.out_ep[0].total_data_len = len;
- pdev->dev.out_ep[0].rem_data_len = len;
- pdev->dev.device_state = USB_EP0_DATA_OUT;
-
- usb_readytorx(pdev, 0U, pbuf, len);
-}
-
-/**
- * @brief continue receive data on the ctl pipe
- * @param [in] pdev device instance
- * @param [in] pbuf pointer to data buffer
- * @param [in] len length of data to be received
- * @retval status
- */
-void usb_ctrldatacontinuerx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len)
-{
- usb_readytorx(pdev, 0U, pbuf, len);
-}
-/**
- * @brief send zero lzngth packet on the ctl pipe
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_ctrlstatustx(usb_core_instance *pdev)
-{
- pdev->dev.device_state = USB_EP0_STATUS_IN;
- usb_deveptx(pdev, 0U, pdev->dev.setup_pkt_buf, 0U);
-}
-
-/**
- * @brief receive zero lzngth packet on the ctl pipe
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_ctrlstatusrx(usb_core_instance *pdev)
-{
- pdev->dev.device_state = USB_EP0_STATUS_OUT;
- usb_readytorx(pdev, 0U, pdev->dev.setup_pkt_buf, 0U);
-}
-
-/**
- * @brief get the received data length
- * @param [in] pdev device instance
- * @param [in] epnum endpoint index
- * @retval Rx Data blength
- */
-uint16_t usb_getrxcnt(usb_core_instance *pdev, uint8_t epnum)
-{
- return (uint16_t)pdev->dev.out_ep[epnum].xfer_count;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_ctrleptrans.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_ctrleptrans.h
deleted file mode 100644
index a39ae818c2..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_ctrleptrans.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_ctrleptrans.h
- * @brief header file for the usb_dev_ctrleptrans.c file
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_DEV_CTRLEPTRANS_H__
-#define __USB_DEV_CTRLEPTRANS_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_def.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CORE
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-extern void usb_ctrldatatx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len);
-extern void usb_ctrldatacontinuetx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len);
-extern void usb_ctrldatarx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len);
-extern void usb_ctrldatacontinuerx(usb_core_instance *pdev, uint8_t *pbuf, uint16_t len);
-extern void usb_ctrlstatustx(usb_core_instance *pdev);
-extern void usb_ctrlstatusrx(usb_core_instance *pdev);
-extern uint16_t usb_getrxcnt(usb_core_instance *pdev, uint8_t epnum);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_DEV_CTRLEPTRANS_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_def.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_def.h
deleted file mode 100644
index 03b61538f1..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_def.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_def.h
- * @brief general defines for the usb device library
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_DEV_DEF_H__
-#define __USB_DEV_DEF_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_lib.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CORE
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#ifndef NULL
-#define NULL (0U)
-#endif
-
-/* Function return status */
-#define USB_DEV_OK (0U)
-#define USB_DEV_BUSY (1U)
-#define USB_DEV_FAIL (2U)
-
-/* Device Status */
-#define USB_DEV_DEFAULT (1U)
-#define USB_DEV_ADDRESSED (2U)
-#define USB_DEV_CONFIGURED (3U)
-#define USB_DEV_SUSPENDED (4U)
-
-/* String descriptor type */
-#define LANGID_STR_IDX (0x00U)
-#define MFC_STR_IDX (0x01U)
-#define PRODUCT_STR_IDX (0x02U)
-#define SERIAL_STR_IDX (0x03U)
-#define CONFIG_STR_IDX (0x04U)
-#define INTERFACE_STR_IDX (0x05U)
-
-/* Request type */
-#define USB_REQ_TYPE_STANDARD (0x00U)
-#define USB_REQ_TYPE_CLASS (0x20U)
-#define USB_REQ_TYPE_VENDOR (0x40U)
-#define USB_REQ_TYPE_MASK (0x60U)
-
-/* Request recipient */
-#define USB_REQ_RECIPIENT_DEVICE (0x00U)
-#define USB_REQ_RECIPIENT_INTERFACE (0x01U)
-#define USB_REQ_RECIPIENT_ENDPOINT (0x02U)
-#define USB_REQ_RECIPIENT_MASK (0x03U)
-
-/* Standart request type */
-#define USB_REQ_GET_STATUS (0x00U)
-#define USB_REQ_CLEAR_FEATURE (0x01U)
-#define USB_REQ_SET_FEATURE (0x03U)
-#define USB_REQ_SET_ADDRESS (0x05U)
-#define USB_REQ_GET_DESCRIPTOR (0x06U)
-#define USB_REQ_SET_DESCRIPTOR (0x07U)
-#define USB_REQ_GET_CONFIGURATION (0x08U)
-#define USB_REQ_SET_CONFIGURATION (0x09U)
-#define USB_REQ_GET_INTERFACE (0x0AU)
-#define USB_REQ_SET_INTERFACE (0x0BU)
-#define USB_REQ_SYNCH_FRAME (0x0CU)
-
-/* Descriptor type */
-#define USB_DESC_TYPE_DEVICE (1U)
-#define USB_DESC_TYPE_CONFIGURATION (2U)
-#define USB_DESC_TYPE_STRING (3U)
-#define USB_DESC_TYPE_INTERFACE (4U)
-#define USB_DESC_TYPE_ENDPOINT (5U)
-#define USB_DESC_TYPE_DEVICE_QUALIFIER (6U)
-#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION (7U)
-
-/* Configuration status */
-#define USB_CONFIG_REMOTE_WAKEUP (2U)
-#define USB_CONFIG_SELF_POWERED (1U)
-
-/* USB device feature */
-#define USB_FEATURE_EP_HALT (0U)
-#define USB_FEATURE_REMOTE_WAKEUP (1U)
-#define USB_FEATURE_TEST_MODE (2U)
-
-/* USB device configuration status */
-#define USB_DEV_CONFIG_CLEAR (0U)
-#define USB_DEV_CONFIG_SET (1U)
-#define USB_DEV_CONFIG_GET (2U)
-
-/* USB EP0 state */
-#define USB_EP0_IDLE (0U)
-#define USB_EP0_SETUP (1U)
-#define USB_EP0_DATA_IN (2U)
-#define USB_EP0_DATA_OUT (3U)
-#define USB_EP0_STATUS_IN (4U)
-#define USB_EP0_STATUS_OUT (5U)
-#define USB_EP0_STALL (6U)
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_DEV_DEF_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_driver.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_driver.c
deleted file mode 100644
index eb60aba741..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_driver.c
+++ /dev/null
@@ -1,402 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_driver.c
- * @brief Peripheral Device Interface Layer
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2022-06-30 CDT Add USB core ID select function
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_driver.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CORE
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-/**
- * @brief Device intialize
- * @param [in] pdev device instance
- * @param [in] pstcPortIdentify usb core and phy select
- * @retval None
- */
-void usb_initdev(usb_core_instance *pdev, stc_usb_port_identify *pstcPortIdentify)
-{
- uint32_t tmp_1;
- USB_DEV_EP *iep, *oep;
-
- usb_setregaddr(&pdev->regs, pstcPortIdentify, &pdev->basic_cfgs);
- pdev->dev.device_cur_status = (uint8_t)USB_DEV_DEFAULT;
- pdev->dev.device_address = 0U;
- tmp_1 = 0UL;
- do {
- iep = &pdev->dev.in_ep[tmp_1];
- oep = &pdev->dev.out_ep[tmp_1];
- iep->ep_dir = 1U;
- oep->ep_dir = 0U;
- iep->epidx = (uint8_t)tmp_1;
- oep->epidx = iep->epidx;
- iep->tx_fifo_num = (uint16_t)tmp_1;
- oep->tx_fifo_num = iep->tx_fifo_num;
- iep->trans_type = EP_TYPE_CTRL;
- oep->trans_type = iep->trans_type;
- iep->maxpacket = USB_MAX_EP0_SIZE;
- oep->maxpacket = iep->maxpacket;
- iep->xfer_buff = 0U;
- oep->xfer_buff = iep->xfer_buff;
- iep->xfer_len = 0UL;
- oep->xfer_len = iep->xfer_len;
- tmp_1++;
- } while (tmp_1 < pdev->basic_cfgs.dev_epnum);
-
- usb_gintdis(&pdev->regs);
- /*Init the Core (common init.) */
- usb_initusbcore(&pdev->regs, &pdev->basic_cfgs);
- /* Force Device Mode*/
- usb_modeset(&pdev->regs, DEVICE_MODE);
- /* Init Device */
- usb_devmodeinit(&pdev->regs, &pdev->basic_cfgs);
- /* Enable USB Global interrupt */
- usb_ginten(&pdev->regs);
-}
-
-/**
- * @brief Configure and open an endpoint
- * @param [in] pdev device instance
- * @param [in] ep_addr endpoint address
- * @param [in] ep_mps endpoint mps
- * @param [in] ep_type endpoint type
- * @retval None
- */
-void usb_opendevep(usb_core_instance *pdev, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
-{
- USB_DEV_EP *ep;
- __IO uint8_t tmp_1, tmp_2;
-
- tmp_1 = ep_addr >> 7; /* EP type, it is IN(=1) or OUT(=0) */
- tmp_2 = ep_addr & 0x7FU; /* EP number */
- if (tmp_1 == 1U) {
- ep = &pdev->dev.in_ep[tmp_2];
- } else {
- ep = &pdev->dev.out_ep[tmp_2];
- }
-
- ep->epidx = tmp_2;
-
- ep->ep_dir = tmp_1;
- ep->maxpacket = ep_mps;
- ep->trans_type = ep_type;
- if (tmp_1 == 1U) {
- /* Assign a Tx FIFO */
- ep->tx_fifo_num = tmp_2;
- }
- /* Set initial data PID. */
- if (ep_type == EP_TYPE_BULK) {
- ep->data_pid_start = 0U;
- }
- usb_epactive(&pdev->regs, ep);
-}
-
-/**
- * @brief called when an EP is disabled
- * @param [in] pdev device instance
- * @param [in] ep_addr endpoint address
- * @retval None
- */
-void usb_shutdevep(usb_core_instance *pdev, uint8_t ep_addr)
-{
- USB_DEV_EP *ep;
- __IO uint8_t tmp_1, tmp_2;
-
- tmp_1 = ep_addr >> 7; /* EP type, it is IN(=1) or OUT(=0) */
- tmp_2 = ep_addr & 0x7FU; /* EP number */
- if (tmp_1 == 1U) {
- ep = &pdev->dev.in_ep[tmp_2];
- } else {
- ep = &pdev->dev.out_ep[tmp_2];
- }
- ep->epidx = tmp_2;
- ep->ep_dir = tmp_1;
- usb_epdeactive(&pdev->regs, ep);
-}
-
-/**
- * @brief usb_readytorx
- * @param [in] pdev device instance
- * @param [in] ep_addr endpoint address
- * @param [out] pbuf pointer to Rx buffer
- * @param [in] buf_len data length
- * @retval status
- */
-void usb_readytorx(usb_core_instance *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
-{
- USB_DEV_EP *ep;
- __IO uint8_t tmp_1;
-
- tmp_1 = ep_addr & 0x7FU; /* EP number */
- ep = &pdev->dev.out_ep[tmp_1];
- /*setup and start the Xfer */
- ep->xfer_buff = pbuf;
- ep->xfer_len = (uint32_t)buf_len;
- ep->xfer_count = 0UL;
- ep->ep_dir = 0U;
- ep->epidx = tmp_1;
-
- if (pdev->basic_cfgs.dmaen == 1U) {
- ep->dma_addr = (uint32_t)pbuf;
- }
-
- if (tmp_1 == 0U) {
- usb_ep0transbegin(&pdev->regs, ep, pdev->basic_cfgs.dmaen);
- } else {
- usb_epntransbegin(&pdev->regs, ep, pdev->basic_cfgs.dmaen);
- }
-}
-
-/**
- * @brief configures EPO to receive SETUP packets from host
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_ep0outstart(usb_core_instance *pdev)
-{
- pdev->dev.out_ep[0].xfer_len = 64U;
- pdev->dev.out_ep[0].rem_data_len = 64U;
- pdev->dev.out_ep[0].total_data_len = 64U;
- usb_ep0revcfg(&pdev->regs, pdev->basic_cfgs.dmaen, pdev->dev.setup_pkt_buf);
-}
-
-/**
- * @brief Transmit data over USB
- * @param [in] pdev device instance
- * @param [in] ep_addr endpoint address
- * @param [in] pbuf pointer to Tx buffer
- * @param [in] buf_len data length
- * @retval None
- */
-void usb_deveptx(usb_core_instance *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len)
-{
- USB_DEV_EP *ep;
- __IO uint8_t tmp_1;
-
- tmp_1 = ep_addr & 0x7FU; /* EP number */
- ep = &pdev->dev.in_ep[tmp_1];
-
- /* Setup and start the Transfer */
- ep->ep_dir = 1U;
- ep->epidx = tmp_1;
- ep->xfer_buff = pbuf;
- ep->dma_addr = (uint32_t)pbuf;
- ep->xfer_count = 0UL;
- ep->xfer_len = buf_len;
-
- if (tmp_1 == 0U) {
- usb_ep0transbegin(&pdev->regs, ep, pdev->basic_cfgs.dmaen);
- } else {
- usb_epntransbegin(&pdev->regs, ep, pdev->basic_cfgs.dmaen);
- }
-}
-
-/**
- * @brief Stall an endpoint.
- * @param [in] pdev device instance
- * @param [in] epnum endpoint address
- * @retval None
- */
-void usb_stalldevep(usb_core_instance *pdev, uint8_t epnum)
-{
- USB_DEV_EP *ep;
- __IO uint8_t tmp_1, tmp_2;
-
- tmp_1 = epnum >> 7; /* EP type, it is IN(=1) or OUT(=0) */
- tmp_2 = epnum & 0x7FU; /* EP number */
-
- if (tmp_1 != 0U) {
- ep = &pdev->dev.in_ep[tmp_2];
- } else {
- ep = &pdev->dev.out_ep[tmp_2];
- }
-
- ep->ep_stall = 1U;
- ep->epidx = tmp_2;
- if (tmp_1 != 0U) {
- ep->ep_dir = 1U;
- } else {
- ep->ep_dir = 0U;
- }
-
- usb_setepstall(&pdev->regs, ep);
-}
-
-/**
- * @brief Clear stall condition on endpoints.
- * @param [in] pdev device instance
- * @param [in] epnum endpoint address
- * @retval status
- */
-void usb_clrstall(usb_core_instance *pdev, uint8_t epnum)
-{
- USB_DEV_EP *ep;
- __IO uint8_t tmp_1, tmp_2;
-
- tmp_1 = epnum >> 7; /* EP type, it is IN(=1) or OUT(=0) */
- tmp_2 = epnum & 0x7FU; /* EP number */
- if (tmp_1 != 0U) {
- ep = &pdev->dev.in_ep[tmp_2];
- } else {
- ep = &pdev->dev.out_ep[tmp_2];
- }
-
- ep->ep_stall = 0U;
- ep->epidx = tmp_2;
- if (tmp_1 != 0U) {
- ep->ep_dir = 1U;
- } else {
- ep->ep_dir = 0U;
- }
-
- usb_clearepstall(&pdev->regs, ep);
-}
-
-/**
- * @brief This Function flushes the FIFOs.
- * @param [in] pdev device instance
- * @param [in] epnum endpoint address
- * @retval status
- */
-void usb_flsdevep(usb_core_instance *pdev, uint8_t epnum)
-{
- __IO uint8_t tmp_1;
-
- tmp_1 = epnum >> 7; /* EP type, it is IN(=1) or OUT(=0) */
- if (tmp_1 != 0U) {
- usb_txfifoflush(&pdev->regs, (uint32_t)epnum & (uint32_t)0x7F);
- } else {
- usb_rxfifoflush(&pdev->regs);
- }
-}
-
-/**
- * @brief This Function set USB device address
- * @param [in] pdev device instance
- * @param [in] devaddr new device address
- * @retval None
- */
-void usb_addrset(usb_core_instance *pdev, uint8_t devaddr)
-{
- usb_devaddrset(&pdev->regs, devaddr);
-}
-
-/**
- * @brief control device connect or disconnect
- * @param [in] pdev device instance
- * @param [in] link 0(conn) or 1(disconn)
- * @retval None
- */
-void usb_conndevctrl(usb_core_instance *pdev, uint8_t link)
-{
- usb_ctrldevconnect(&pdev->regs, link);
-}
-
-/**
- * @brief returns the EP Status
- * @param [in] pdev device instance
- * @param [in] epnum endpoint address
- * @retval EP status
- */
-uint32_t usb_devepstatusget(usb_core_instance *pdev, uint8_t epnum)
-{
- USB_DEV_EP *ep;
- uint32_t Status;
- __IO uint8_t tmp_1, tmp_2;
-
- tmp_1 = epnum >> 7; /* EP type, it is IN(=1) or OUT(=0) */
- tmp_2 = epnum & 0x7FU; /* EP number */
- if (tmp_1 != 0U) {
- ep = &pdev->dev.in_ep[tmp_2];
- } else {
- ep = &pdev->dev.out_ep[tmp_2];
- }
-
- Status = usb_epstatusget(&pdev->regs, ep);
- /* Return the current status */
- return Status;
-}
-
-/**
- * @brief Set the EP Status
- * @param [in] pdev device instance
- * @param [in] status new Status
- * @param [in] epnum EP address
- * @retval None
- */
-void usb_devepstatusset(usb_core_instance *pdev, uint8_t epnum, uint32_t status)
-{
- USB_DEV_EP *ep;
- __IO uint8_t tmp_1, tmp_2;
-
- tmp_1 = epnum >> 7; /* EP type, it is IN(=1) or OUT(=0) */
- tmp_2 = epnum & 0x7FU; /* EP number */
- if (tmp_1 != 0U) {
- ep = &pdev->dev.in_ep[tmp_2];
- } else {
- ep = &pdev->dev.out_ep[tmp_2];
- }
-
- usb_epstatusset(&pdev->regs, ep, status);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_driver.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_driver.h
deleted file mode 100644
index 5d0e20ca45..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_driver.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_driver.h
- * @brief Peripheral Driver Header file
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2022-06-30 CDT Add USB core ID select function
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_DEV_DRIVER_H__
-#define __USB_DEV_DRIVER_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_def.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CORE
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-extern void usb_initdev(usb_core_instance *pdev, stc_usb_port_identify *pstcPortIdentify);
-extern void usb_conndevctrl(usb_core_instance *pdev, uint8_t link);
-extern void usb_addrset(usb_core_instance *pdev, uint8_t devaddr);
-extern void usb_opendevep(usb_core_instance *pdev, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
-extern void usb_shutdevep(usb_core_instance *pdev, uint8_t ep_addr);
-extern void usb_readytorx(usb_core_instance *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len);
-extern void usb_ep0outstart(usb_core_instance *pdev);
-extern void usb_deveptx(usb_core_instance *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len);
-extern void usb_stalldevep(usb_core_instance *pdev, uint8_t epnum);
-extern void usb_clrstall(usb_core_instance *pdev, uint8_t epnum);
-extern void usb_flsdevep(usb_core_instance *pdev, uint8_t epnum);
-extern uint32_t usb_devepstatusget(usb_core_instance *pdev, uint8_t epnum);
-extern void usb_devepstatusset(usb_core_instance *pdev, uint8_t epnum, uint32_t status);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_DEV_DRIVER_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_int.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_int.c
deleted file mode 100644
index 8adc22e57c..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_int.c
+++ /dev/null
@@ -1,458 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_int.c
- * @brief Peripheral Device interrupt subroutines.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2022-06-30 CDT Modify for MISRAC
- Delete comment
- 2023-09-30 CDT Modify function usb_susp_isr()
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_int.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CORE
- * @{
- */
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @brief read the endpoint flags
- * @param [in] pdev device instance
- * @param [in] epnum endpoint number
- * @retval status
- */
-static uint32_t usb_rddevinep(usb_core_instance *pdev, uint8_t epnum)
-{
- uint32_t u32diepmsk;
- uint32_t u32diepempmsk;
- u32diepmsk = READ_REG32(pdev->regs.DREGS->DIEPMSK);
- u32diepempmsk = READ_REG32(pdev->regs.DREGS->DIEPEMPMSK);
- u32diepmsk |= (((u32diepempmsk >> epnum) & 0x1UL) << 7U);
- return (READ_REG32(pdev->regs.INEP_REGS[epnum]->DIEPINT) & u32diepmsk);
-}
-
-/**
- * @brief check FIFO for the next packet to be loaded
- * @param [in] pdev device instance
- * @param [in] epnum endpoint number
- * @retval None
- */
-static void usb_wrblanktxfifo(usb_core_instance *pdev, uint32_t epnum)
-{
- USB_DEV_EP *ep;
- uint32_t u32Len;
- uint32_t u32Len32b;
- uint16_t u16spclen;
- uint32_t u32diepempmsk;
-
- ep = &pdev->dev.in_ep[epnum];
- u32Len = ep->xfer_len - ep->xfer_count;
- if (u32Len > ep->maxpacket) {
- u32Len = ep->maxpacket;
- }
- u32Len32b = (u32Len + 3UL) >> 2;
- u16spclen = usb_rdineptxfspcavail(pdev, epnum);
- while ((u16spclen >= u32Len32b) && (ep->xfer_count < ep->xfer_len)) {
- u32Len = ep->xfer_len - ep->xfer_count;
-
- if (u32Len > ep->maxpacket) {
- u32Len = ep->maxpacket;
- }
- u32Len32b = (u32Len + 3UL) >> 2;
- usb_wrpkt(&pdev->regs, ep->xfer_buff, (uint8_t)epnum, (uint16_t)u32Len, pdev->basic_cfgs.dmaen);
- ep->xfer_buff += u32Len;
- ep->xfer_count += u32Len;
- u16spclen = usb_rdineptxfspcavail(pdev, epnum);
- }
-
- if (u32Len == 0UL) {
- u32diepempmsk = 0x01UL << epnum;
- CLR_REG32_BIT(pdev->regs.DREGS->DIEPEMPMSK, u32diepempmsk);
- }
-}
-
-#ifdef VBUS_SENSING_ENABLED
-/**
- * @brief Indicates that the USB_OTG controller has detected a connection
- * @param [in] pdev device instance
- * @retval None
- */
-static void usb_sessionrequest_isr(usb_core_instance *pdev)
-{
- dev_int_cbkpr->devctrlconnect(pdev, 1U);
-
- WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_VBUSVINT);
-
- if (0U != pdev->basic_cfgs.low_power) {
- CLR_REG32_BIT(*pdev->regs.GCCTL, USBFS_GCCTL_STPPCLK | USBFS_GCCTL_GATEHCLK);
- }
-}
-#endif
-
-/**
- * @brief Indicates that the controller has detected a resume or remote Wake-up sequence
- * @param [in] pdev device instance
- * @retval None
- */
-static void usb_resume_isr(usb_core_instance *pdev)
-{
- if (0U != pdev->basic_cfgs.low_power) {
- CLR_REG32_BIT(*pdev->regs.GCCTL, USBFS_GCCTL_STPPCLK | USBFS_GCCTL_GATEHCLK);
- }
-
- CLR_REG32_BIT(pdev->regs.DREGS->DCTL, USBFS_DCTL_RWUSIG);
-
- dev_int_cbkpr->Resume(pdev);
-
- WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_WKUINT);
-}
-
-/**
- * @brief Indicates that SUSPEND state has been detected on the USB
- * @param [in] pdev device instance
- * @retval None
- */
-static void usb_susp_isr(usb_core_instance *pdev)
-{
- uint32_t u32dsts;
- uint8_t u8PrevStatus;
-
- dev_int_cbkpr->Suspend(pdev);
- u32dsts = READ_REG32(pdev->regs.DREGS->DSTS);
- WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_USBSUSP);
-
- u8PrevStatus = pdev->dev.device_old_status;
- if ((pdev->dev.connection_status == 1U) && (u8PrevStatus == USB_DEV_CONFIGURED) &&
- (0U != pdev->basic_cfgs.low_power) && ((u32dsts & 1UL) != 0UL)) {
- SET_REG32_BIT(*pdev->regs.GCCTL, USBFS_GCCTL_STPPCLK);
- SET_REG32_BIT(*pdev->regs.GCCTL, USBFS_GCCTL_GATEHCLK);
- }
-}
-
-/**
- * @brief Indicates that at leadt one IN EP has a pending interrupt
- * @param [in] pdev device instance
- * @retval None
- */
-static void usb_inep_isr(usb_core_instance *pdev)
-{
- uint32_t u32diepint;
- uint32_t u32EpIntr;
- uint8_t u8epnum;
- uint32_t u32diepempmsk;
-
- u32EpIntr = usb_getalliepintr(&pdev->regs);
- u8epnum = 0U;
- while ((0U != u32EpIntr) && (u8epnum < USB_MAX_TX_FIFOS)) {
- if ((u32EpIntr & 0x1UL) != 0UL) {
- u32diepint = usb_rddevinep(pdev, u8epnum);
- if ((u32diepint & XFER_COMPL) != 0UL) {
- u32diepempmsk = 1UL << u8epnum;
- CLR_REG32_BIT(pdev->regs.DREGS->DIEPEMPMSK, u32diepempmsk);
- WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, XFER_COMPL);
- dev_int_cbkpr->DataInStage(pdev, u8epnum);
- if (pdev->basic_cfgs.dmaen == 1U) {
- if ((pdev->dev.device_state == USB_EP0_STATUS_IN) && (u8epnum == 0U)) {
- pdev->dev.out_ep[0].xfer_len = 64U;
- pdev->dev.out_ep[0].rem_data_len = 64U;
- pdev->dev.out_ep[0].total_data_len = 64U;
- usb_ep0revcfg(&pdev->regs, pdev->basic_cfgs.dmaen, pdev->dev.setup_pkt_buf);
- pdev->dev.device_state = USB_EP0_IDLE;
- }
- }
- }
- if ((u32diepint & EPDISABLED) != 0UL) {
- WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, EPDISABLED);
- }
- if ((u32diepint & TIME_OUT) != 0UL) {
- WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, TIME_OUT);
- }
- if ((u32diepint & INTKNTXFEMP) != 0UL) {
- WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, INTKNTXFEMP);
- }
- if ((u32diepint & INEPNAKEFF) != 0UL) {
- WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, INEPNAKEFF);
- }
- if ((u32diepint & TXFEMP) != 0UL) {
- usb_wrblanktxfifo(pdev, u8epnum);
- WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, TXFEMP);
- }
- }
- u8epnum++;
- u32EpIntr >>= 1U;
- }
-}
-
-/**
- * @brief Indicates that an OUT EP has a pending Interrupt
- * @param [in] pdev device instance
- * @retval None
- */
-static void usb_outep_isr(usb_core_instance *pdev)
-{
- uint32_t u32EpIntr;
- uint32_t u32doepint;
- uint8_t u8epnum = 0U;
- uint32_t u8Xfer;
- uint32_t u32ReadEpSize;
-
- u32EpIntr = usb_getalloepintr(&pdev->regs);
- while ((u32EpIntr != 0UL) && (u8epnum < USB_MAX_TX_FIFOS)) {
- if ((u32EpIntr & 0x1UL) != 0UL) {
- u32doepint = usb_getoepintbit(&pdev->regs, u8epnum);
- if ((u32doepint & XFER_COMPL) != 0UL) {
- WRITE_REG32(pdev->regs.OUTEP_REGS[u8epnum]->DOEPINT, XFER_COMPL);
- if (pdev->basic_cfgs.dmaen == 1U) {
- u32ReadEpSize = (READ_REG32(pdev->regs.OUTEP_REGS[u8epnum]->DOEPTSIZ) & USBFS_DOEPTSIZ_XFRSIZ);
- u8Xfer = LL_MIN(pdev->dev.out_ep[u8epnum].maxpacket, pdev->dev.out_ep[u8epnum].xfer_len);
- pdev->dev.out_ep[u8epnum].xfer_count = u8Xfer - u32ReadEpSize;
- if (u8epnum != 0U) {
- pdev->dev.out_ep[u8epnum].xfer_count = pdev->dev.out_ep[u8epnum].xfer_len - u32ReadEpSize;
- }
- }
- dev_int_cbkpr->DataOutStage(pdev, u8epnum);
- if (pdev->basic_cfgs.dmaen == 1U) {
- if ((pdev->dev.device_state == USB_EP0_STATUS_OUT) && (u8epnum == 0U)) {
- pdev->dev.out_ep[0].xfer_len = 64U;
- pdev->dev.out_ep[0].rem_data_len = 64U;
- pdev->dev.out_ep[0].total_data_len = 64U;
- usb_ep0revcfg(&pdev->regs, pdev->basic_cfgs.dmaen, pdev->dev.setup_pkt_buf);
- pdev->dev.device_state = USB_EP0_IDLE;
- }
- }
- }
- if ((u32doepint & EPDISABLED) != 0UL) {
- WRITE_REG32(pdev->regs.OUTEP_REGS[u8epnum]->DOEPINT, EPDISABLED);
- }
- if (u8epnum == 0U) {
- u32doepint = usb_getoepintbit(&pdev->regs, u8epnum);
- if ((u32doepint & SETUP_BIT) != 0UL) {
- dev_int_cbkpr->SetupStage(pdev);
- WRITE_REG32(pdev->regs.OUTEP_REGS[u8epnum]->DOEPINT, SETUP_BIT);
- }
- }
- }
- u8epnum++;
- u32EpIntr >>= 1U;
- }
-}
-
-/**
- * @brief Handles the SOF Interrupts
- * @param [in] pdev device instance
- * @retval None
- */
-static void usb_sof_isr(usb_core_instance *pdev)
-{
- dev_int_cbkpr->SOF(pdev);
- WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_SOF);
-}
-
-/**
- * @brief Handles the Rx Status Queue Level Interrupt
- * @param [in] pdev device instance
- * @retval status
- */
-static void usb_rxstsqlvl_isr(usb_core_instance *pdev)
-{
- uint32_t u32grxsts;
- USB_DEV_EP *ep;
- uint8_t u8epnum;
- uint8_t u8PktStatus;
- uint16_t u16ByteCnt;
-
- CLR_REG32_BIT(pdev->regs.GREGS->GINTMSK, USBFS_GINTMSK_RXFNEM);
-
- u32grxsts = READ_REG32(pdev->regs.GREGS->GRXSTSP);
- u8epnum = (uint8_t)(u32grxsts & USBFS_GRXSTSP_CHNUM_EPNUM);
- u8PktStatus = (uint8_t)((u32grxsts & USBFS_GRXSTSP_PKTSTS) >> USBFS_GRXSTSP_PKTSTS_POS);
- u16ByteCnt = (uint16_t)((u32grxsts & USBFS_GRXSTSP_BCNT) >> USBFS_GRXSTSP_BCNT_POS);
- ep = &pdev->dev.out_ep[u8epnum];
- switch (u8PktStatus) {
- case STS_DATA_UPDT:
- if (0U != u16ByteCnt) {
- usb_rdpkt(&pdev->regs, ep->xfer_buff, u16ByteCnt);
- ep->xfer_buff += u16ByteCnt;
- ep->xfer_count += u16ByteCnt;
- } else {
- ;
- }
- break;
- case STS_SETUP_UPDT:
- /* Copy the setup packet received in FIFO into the setup buffer in RAM */
- usb_rdpkt(&pdev->regs, pdev->dev.setup_pkt_buf, 8U);
- ep->xfer_count += u16ByteCnt;
- break;
- case STS_GOUT_NAK:
- case STS_XFER_COMP:
- case STS_SETUP_COMP:
- break;
- default:
- break;
- }
- SET_REG32_BIT(pdev->regs.GREGS->GINTMSK, USBFS_GINTMSK_RXFNEM);
-}
-
-/**
- * @brief This interrupt occurs when a USB Reset is detected
- * @param [in] pdev device instance
- * @retval None
- */
-static void usb_reset_isr(usb_core_instance *pdev)
-{
- uint32_t i;
-
- CLR_REG32_BIT(pdev->regs.DREGS->DCTL, USBFS_DCTL_RWUSIG);
- usb_txfifoflush(&pdev->regs, 0UL);
- for (i = 0UL; i < pdev->basic_cfgs.dev_epnum ; i++) {
- WRITE_REG32(pdev->regs.INEP_REGS[i]->DIEPINT, 0xFFUL);
- WRITE_REG32(pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFFUL);
- }
- WRITE_REG32(pdev->regs.DREGS->DAINT, 0xFFFFFFFFUL);
- WRITE_REG32(pdev->regs.DREGS->DAINTMSK, 1UL | (1UL << USBFS_DAINTMSK_OEPINTM_POS));
-
- WRITE_REG32(pdev->regs.DREGS->DOEPMSK, USBFS_DOEPMSK_STUPM | USBFS_DOEPMSK_XFRCM | USBFS_DOEPMSK_EPDM);
-#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
- WRITE_REG32(pdev->regs.DREGS->DOUTEP1MSK, USBFS_DOEPMSK_STUPM | USBFS_DOEPMSK_XFRCM | USBFS_DOEPMSK_EPDM);
-#endif
-
- WRITE_REG32(pdev->regs.DREGS->DIEPMSK, USBFS_DIEPMSK_XFRCM | USBFS_DIEPMSK_TOM | USBFS_DIEPMSK_EPDM);
-#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
- WRITE_REG32(pdev->regs.DREGS->DINEP1MSK, USBFS_DIEPMSK_XFRCM | USBFS_DIEPMSK_TOM | USBFS_DIEPMSK_EPDM);
-#endif
-
- CLR_REG32_BIT(pdev->regs.DREGS->DCFG, USBFS_DCFG_DAD);
- pdev->dev.out_ep[0].xfer_len = 64U;
- pdev->dev.out_ep[0].rem_data_len = 64U;
- pdev->dev.out_ep[0].total_data_len = 64U;
- usb_ep0revcfg(&pdev->regs, pdev->basic_cfgs.dmaen, pdev->dev.setup_pkt_buf);
- WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_USBRST);
-
- dev_int_cbkpr->Reset(pdev);
-}
-
-/**
- * @brief Read the device status register and set the device speed
- * @param [in] pdev device instance
- * @retval None
- */
-static void usb_enumfinish_isr(usb_core_instance *pdev)
-{
- usb_ep0activate(&pdev->regs);
- usb_setaroundtim(pdev);
- WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_ENUMDNE);
-}
-
-/**
- * @brief handle the ISO IN incomplete interrupt
- * @param [in] pdev device instance
- * @retval None
- */
-static void usb_isoinincomplt_isr(usb_core_instance *pdev)
-{
- dev_int_cbkpr->IsoINIncomplete(pdev);
- WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_IISOIXFR);
-}
-
-/**
- * @brief handle the ISO OUT incomplete interrupt
- * @param [in] pdev device instance
- * @retval None
- */
-static void usb_isooutincomplt_isr(usb_core_instance *pdev)
-{
- dev_int_cbkpr->IsoOUTIncomplete(pdev);
- WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_IPXFR_INCOMPISOOUT);
-}
-
-/**
- * @brief handles all USB Interrupts
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_isr_handler(usb_core_instance *pdev)
-{
- uint32_t u32gintsts;
-
- if (0U == usb_getcurmod(&pdev->regs)) {
- u32gintsts = usb_getcoreintr(&pdev->regs);
- if (u32gintsts == 0UL) {
- return;
- }
- if ((u32gintsts & OUTEP_INT) != 0UL) {
- usb_outep_isr(pdev);
- }
- if ((u32gintsts & INEP_INT) != 0UL) {
- usb_inep_isr(pdev);
- }
- if ((u32gintsts & MODEMIS_INT) != 0UL) {
- WRITE_REG32(pdev->regs.GREGS->GINTSTS, MODEMIS_INT);
- }
- if ((u32gintsts & WAKEUP_INT) != 0UL) {
- usb_resume_isr(pdev);
- }
- if ((u32gintsts & USBSUSP_INT) != 0UL) {
- usb_susp_isr(pdev);
- }
- if ((u32gintsts & SOF_INT) != 0UL) {
- usb_sof_isr(pdev);
- }
- if ((u32gintsts & RXFLVL_INT) != 0UL) {
- usb_rxstsqlvl_isr(pdev);
- }
- if ((u32gintsts & USBRST_INT) != 0UL) {
- usb_reset_isr(pdev);
- }
- if ((u32gintsts & ENUMDONE_INT) != 0UL) {
- usb_enumfinish_isr(pdev);
- }
- if ((u32gintsts & INCOMPLSOIN) != 0UL) {
- usb_isoinincomplt_isr(pdev);
- }
- if ((u32gintsts & INCOMPLSOOUT) != 0UL) {
- usb_isooutincomplt_isr(pdev);
- }
-#ifdef VBUS_SENSING_ENABLED
- if ((u32gintsts & VBUSV_INT) != 0UL) {
- usb_sessionrequest_isr(pdev);
- }
-#endif
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************************************************************************
- * EOF (not truncated)
- *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_int.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_int.h
deleted file mode 100644
index 78b3fc639d..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_int.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_int.h
- * @brief Peripheral Device Interface Layer
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_DEV_INT_H__
-#define __USB_DEV_INT_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_def.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CORE
- * @{
- */
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-/* The bit of the diepint/doepint */
-#define XFER_COMPL (1UL)
-#define EPDISABLED (1UL<<1)
-#define TIME_OUT (1UL<<3)
-#define SETUP_BIT (1UL<<3)
-#define INTKNTXFEMP (1UL<<4)
-#define INEPNAKEFF (1UL<<6)
-#define TXFEMP (1UL<<7)
-
-/* The bit of the GINTSTS */
-#define MODEMIS_INT (1UL<<1)
-#define SOF_INT (1UL<<3)
-#define RXFLVL_INT (1UL<<4)
-#define USBSUSP_INT (1UL<<11)
-#define USBRST_INT (1UL<<12)
-#define ENUMDONE_INT (1UL<<13)
-#define INEP_INT (1UL<<18)
-#define OUTEP_INT (1UL<<19)
-#define INCOMPLSOIN (1UL<<20)
-#define INCOMPLSOOUT (1UL<<21)
-#define VBUSV_INT (1UL<<30)
-#define WAKEUP_INT (1UL<<31)
-
-/* Data packet status for device mode */
-#define STS_GOUT_NAK (1U)
-#define STS_DATA_UPDT (2U)
-#define STS_XFER_COMP (3U)
-#define STS_SETUP_COMP (4U)
-#define STS_SETUP_UPDT (6U)
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-typedef struct {
- void (* Reset)(usb_core_instance *pdev);
- void (* devctrlconnect)(usb_core_instance *pdev, uint8_t conn);
- void (* Suspend)(usb_core_instance *pdev);
- void (* Resume)(usb_core_instance *pdev);
- void (* SOF)(usb_core_instance *pdev);
- void (* SetupStage)(usb_core_instance *pdev);
- void (* DataOutStage)(usb_core_instance *pdev, uint8_t epnum);
- void (* DataInStage)(usb_core_instance *pdev, uint8_t epnum);
- void (* IsoINIncomplete)(usb_core_instance *pdev);
- void (* IsoOUTIncomplete)(usb_core_instance *pdev);
-} usb_dev_int_cbk_typedef;
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-/**
- * @brief get the IN Endpoint TxFIFO avail space
- * @param [in] pdev device instance
- * @param [in] epnum endpoint number
- * @retval the avail space in 32-bit words
- */
-__STATIC_INLINE uint16_t usb_rdineptxfspcavail(usb_core_instance *pdev, uint32_t epnum)
-{
- return (uint16_t)(READ_REG32(pdev->regs.INEP_REGS[epnum]->DTXFSTS) & USBFS_DTXFSTS_INEPTFSAV);
-}
-
-/**
- * @brief set the USB turn around time
- * @param [in] pdev device instance
- * @retval None
- */
-__STATIC_INLINE void usb_setaroundtim(usb_core_instance *pdev)
-{
- SET_REG32_BIT(pdev->regs.GREGS->GUSBCFG, USBFS_GUSBCFG_TRDT);
-}
-
-extern usb_dev_int_cbk_typedef *dev_int_cbkpr;
-extern void usb_isr_handler(usb_core_instance *pdev);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_DEV_INT_H__ */
-
-/******************************************************************************
- * EOF (not truncated)
- *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_stdreq.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_stdreq.c
deleted file mode 100644
index c18d10769b..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_stdreq.c
+++ /dev/null
@@ -1,609 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_stdreq.c
- * @brief The standard USB requests following chapter 9.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2022-10-31 CDT Modify for MISRAC
- Fix bug for USB endpoint GET_STATUS request
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include
-#include "usb_dev_core.h"
-#include "usb_dev_stdreq.h"
-#include "usb_dev_driver.h"
-#include "usb_dev_ctrleptrans.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CORE
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-static __USB_ALIGN_BEGIN uint32_t dev_ep_status = 0UL;
-static __USB_ALIGN_BEGIN uint32_t dev_default_cfg = 0UL;
-static __USB_ALIGN_BEGIN uint32_t dev_cfg_status = 0UL;
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-void usb_getdesc(usb_core_instance *pdev, const USB_SETUP_REQ *req);
-void usb_setaddr(usb_core_instance *pdev, const USB_SETUP_REQ *req);
-void usb_setconfig(usb_core_instance *pdev, const USB_SETUP_REQ *req);
-void usb_getconfig(usb_core_instance *pdev, const USB_SETUP_REQ *req);
-void usb_getstatus(usb_core_instance *pdev, const USB_SETUP_REQ *req);
-void usb_getintf(usb_core_instance *pdev);
-void usb_setfeature(usb_core_instance *pdev, USB_SETUP_REQ *req);
-void usb_clrfeature(usb_core_instance *pdev, USB_SETUP_REQ *req);
-uint8_t usb_getlength(uint8_t *buf);
-void usb_dev_ctrlconfig(usb_core_instance *pdev, uint8_t cfgidx, uint8_t action);
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @brief Handle standard usb device requests
- * @param [in] pdev device instance
- * @param [in] req usb request
- * @retval None
- */
-void usb_standarddevreq(usb_core_instance *pdev, USB_SETUP_REQ *req)
-{
- if (req->bRequest == USB_REQ_GET_DESCRIPTOR) {
- usb_getdesc(pdev, req) ;
- } else if (req->bRequest == USB_REQ_SET_ADDRESS) {
- usb_setaddr(pdev, req);
- } else if (req->bRequest == USB_REQ_SET_CONFIGURATION) {
- usb_setconfig(pdev, req);
- } else if (req->bRequest == USB_REQ_GET_CONFIGURATION) {
- usb_getconfig(pdev, req);
- } else if (req->bRequest == USB_REQ_GET_STATUS) {
- usb_getstatus(pdev, req);
- } else if (req->bRequest == USB_REQ_SET_FEATURE) {
- usb_setfeature(pdev, req);
- } else if (req->bRequest == USB_REQ_CLEAR_FEATURE) {
- usb_clrfeature(pdev, req);
- } else {
- if (0U != pdev->dev.class_callback->ep0_setup(pdev, req)) {
- usb_ctrlerr(pdev);
- }
- }
-}
-
-/**
- * @brief Handle standard usb interface requests
- * @param [in] pdev device instance
- * @param [in] req usb request
- * @retval None
- */
-void usb_standarditfreq(usb_core_instance *pdev, USB_SETUP_REQ *req)
-{
- uint8_t u8RetFlag = 0U;
-
- if (req->bRequest == USB_REQ_GET_STATUS) {
- usb_getstatus(pdev, req);
- u8RetFlag = 1U;
- } else if (req->bRequest == USB_REQ_GET_INTERFACE) {
- if (req->bmRequest != 0x21U) {
- usb_getintf(pdev);
- u8RetFlag = 1U;
- }
- } else if (req->bRequest == 0xFEU) {
- usb_getintf(pdev);
- u8RetFlag = 1U;
- } else {
- ;
- }
-
- if (1U != u8RetFlag) {
- if (pdev->dev.device_cur_status == USB_DEV_CONFIGURED) {
- if (LOBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) {
- pdev->dev.class_callback->ep0_setup(pdev, req);
- if (req->wLength == 0U) {
- usb_ctrlstatustx(pdev);
- }
- } else {
- usb_ctrlerr(pdev);
- }
- } else {
- usb_ctrlerr(pdev);
- }
- }
-}
-
-/**
- * @brief Handle standard usb endpoint requests
- * @param [in] pdev device instance
- * @param [in] req usb request
- * @retval None
- */
-void usb_standardepreq(usb_core_instance *pdev, USB_SETUP_REQ *req)
-{
- __IO uint8_t ep_addr;
- ep_addr = LOBYTE(req->wIndex);
-
- switch (req->bRequest) {
- case USB_REQ_SET_FEATURE :
- switch (pdev->dev.device_cur_status) {
- case USB_DEV_ADDRESSED:
- if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) {
- usb_stalldevep(pdev, ep_addr);
- }
- break;
- case USB_DEV_CONFIGURED:
- if (req->wValue == USB_FEATURE_EP_HALT) {
- if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) {
- usb_stalldevep(pdev, ep_addr);
- }
- }
- pdev->dev.class_callback->ep0_setup(pdev, req);
- usb_ctrlstatustx(pdev);
- break;
- default:
- usb_ctrlerr(pdev);
- break;
- }
- break;
- case USB_REQ_CLEAR_FEATURE :
- switch (pdev->dev.device_cur_status) {
- case USB_DEV_ADDRESSED:
- if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) {
- usb_stalldevep(pdev, ep_addr);
- }
- break;
- case USB_DEV_CONFIGURED:
- if (req->wValue == USB_FEATURE_EP_HALT) {
- if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) {
- usb_clrstall(pdev, ep_addr);
- pdev->dev.class_callback->ep0_setup(pdev, req);
- }
- usb_ctrlstatustx(pdev);
- }
- break;
- default:
- usb_ctrlerr(pdev);
- break;
- }
- break;
- case USB_REQ_GET_STATUS:
- switch (pdev->dev.device_cur_status) {
- case USB_DEV_ADDRESSED:
- if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) {
- usb_stalldevep(pdev, ep_addr);
- }
- break;
- case USB_DEV_CONFIGURED:
- if ((ep_addr & 0x80U) == 0x80U) {
- if (0U != pdev->dev.in_ep[(ep_addr & 0x7FU) % USB_MAX_TX_FIFOS].ep_stall) {
- dev_ep_status = 0x0001U;
- } else {
- dev_ep_status = 0x0000U;
- }
- } else if ((ep_addr & 0x80U) == 0x00U) {
- if (0U != pdev->dev.out_ep[(ep_addr & 0x7FU) % USB_MAX_TX_FIFOS].ep_stall) {
- dev_ep_status = 0x0001U;
- } else {
- dev_ep_status = 0x0000U;
- }
- } else {
- ;
- }
- usb_ctrldatatx(pdev, (uint8_t *)&dev_ep_status, 2U);
- break;
-
- default:
- usb_ctrlerr(pdev);
- break;
- }
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Handle Get Descriptor requests
- * @param [in] pdev device instance
- * @param [in] req usb request
- * @retval status
- */
-void usb_getdesc(usb_core_instance *pdev, const USB_SETUP_REQ *req)
-{
- uint16_t len = 0U;
- uint8_t *pbuf = NULL;
- uint8_t u8ErrFlag = 0U;
-
- switch (req->wValue >> 8U) {
- case USB_DESC_TYPE_DEVICE:
- pbuf = pdev->dev.desc_callback->get_dev_desc(&len);
- break;
- case USB_DESC_TYPE_CONFIGURATION:
- pbuf = (uint8_t *)pdev->dev.class_callback->class_getconfigdesc(&len);
- pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
- break;
- case USB_DESC_TYPE_STRING:
- switch ((uint8_t)(req->wValue)) {
- case LANGID_STR_IDX:
- pbuf = pdev->dev.desc_callback->get_dev_langiddesc(&len);
- break;
- case MFC_STR_IDX:
- pbuf = pdev->dev.desc_callback->get_dev_manufacturerstr(&len);
- break;
- case PRODUCT_STR_IDX:
- pbuf = pdev->dev.desc_callback->get_dev_productstr(&len);
- break;
- case SERIAL_STR_IDX:
- pbuf = pdev->dev.desc_callback->get_dev_serialstr(&len);
- break;
- case CONFIG_STR_IDX:
- pbuf = pdev->dev.desc_callback->get_dev_configstr(&len);
- break;
- case INTERFACE_STR_IDX:
- pbuf = pdev->dev.desc_callback->get_dev_interfacestr(&len);
- break;
- default:
- usb_ctrlerr(pdev);
- u8ErrFlag = 1U;
- break;
- }
- break;
- case USB_DESC_TYPE_DEVICE_QUALIFIER:
- usb_ctrlerr(pdev);
- u8ErrFlag = 1U;
- break;
- case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
- usb_ctrlerr(pdev);
- u8ErrFlag = 1U;
- break;
- default:
- usb_ctrlerr(pdev);
- u8ErrFlag = 1U;
- break;
- }
-
- if (0U == u8ErrFlag) {
- if ((len != 0U) && (req->wLength != 0U)) {
- len = LL_MIN(len, req->wLength);
- usb_ctrldatatx(pdev, pbuf, len);
- }
- }
-}
-
-/**
- * @brief Set device address
- * @param [in] pdev device instance
- * @param [in] req usb request
- * @retval None
- */
-void usb_setaddr(usb_core_instance *pdev, const USB_SETUP_REQ *req)
-{
- uint8_t dev_addr;
-
- if ((req->wIndex == 0U) && (req->wLength == 0U)) {
- dev_addr = (uint8_t)(req->wValue) & 0x7FU;
-
- if (pdev->dev.device_cur_status == USB_DEV_CONFIGURED) {
- usb_ctrlerr(pdev);
- } else {
- pdev->dev.device_address = dev_addr;
- usb_addrset(pdev, dev_addr);
- usb_ctrlstatustx(pdev);
-
- if (dev_addr != 0U) {
- pdev->dev.device_cur_status = USB_DEV_ADDRESSED;
- } else {
- pdev->dev.device_cur_status = USB_DEV_DEFAULT;
- }
- }
- } else {
- usb_ctrlerr(pdev);
- }
-}
-
-/**
- * @brief Handle Set device configuration request
- * @param [in] pdev device instance
- * @param [in] req usb request
- * @retval None
- */
-void usb_setconfig(usb_core_instance *pdev, const USB_SETUP_REQ *req)
-{
- static uint8_t tmp_cfgidx;
-
- tmp_cfgidx = (uint8_t)(req->wValue);
-
- if (tmp_cfgidx > DEV_MAX_CFG_NUM) {
- usb_ctrlerr(pdev);
- } else {
- switch (pdev->dev.device_cur_status) {
- case USB_DEV_ADDRESSED:
- if (0U != tmp_cfgidx) {
- pdev->dev.device_config = tmp_cfgidx;
- pdev->dev.device_cur_status = USB_DEV_CONFIGURED;
- usb_dev_ctrlconfig(pdev, tmp_cfgidx, USB_DEV_CONFIG_SET);
- usb_ctrlstatustx(pdev);
- } else {
- usb_ctrlstatustx(pdev);
- }
- break;
- case USB_DEV_CONFIGURED:
- if (tmp_cfgidx == 0U) {
- pdev->dev.device_cur_status = USB_DEV_ADDRESSED;
- pdev->dev.device_config = tmp_cfgidx;
- usb_dev_ctrlconfig(pdev, tmp_cfgidx, USB_DEV_CONFIG_CLEAR);
- usb_ctrlstatustx(pdev);
- } else if (tmp_cfgidx != pdev->dev.device_config) {
- /* Clear old configuration */
- usb_dev_ctrlconfig(pdev, pdev->dev.device_config, USB_DEV_CONFIG_CLEAR);
- /* set new configuration */
- pdev->dev.device_config = tmp_cfgidx;
- usb_dev_ctrlconfig(pdev, tmp_cfgidx, USB_DEV_CONFIG_SET);
- usb_ctrlstatustx(pdev);
- } else {
- usb_ctrlstatustx(pdev);
- }
- break;
- case USB_DEV_SUSPENDED:
-
- break;
- default:
- usb_ctrlerr(pdev);
- break;
- }
- }
-}
-
-/**
- * @brief Handle Get device configuration request
- * @param [in] pdev device instance
- * @param [in] req usb request
- * @retval None
- */
-void usb_getconfig(usb_core_instance *pdev, const USB_SETUP_REQ *req)
-{
- if (req->wLength != 1U) {
- usb_ctrlerr(pdev);
- } else {
- switch (pdev->dev.device_cur_status) {
- case USB_DEV_ADDRESSED:
- usb_ctrldatatx(pdev, (uint8_t *)&dev_default_cfg, 1U);
- break;
- case USB_DEV_CONFIGURED:
- usb_ctrldatatx(pdev, (uint8_t *)&pdev->dev.device_config, 1U);
- break;
- default:
- usb_ctrlerr(pdev);
- break;
- }
- }
-}
-
-/**
- * @brief Handle Get Status request
- * @param [in] pdev device instance
- * @param [in] req usb request
- * @retval None
- */
-void usb_getstatus(usb_core_instance *pdev, const USB_SETUP_REQ *req)
-{
- (void)(req);
- switch (pdev->dev.device_cur_status) {
- case USB_DEV_ADDRESSED:
- case USB_DEV_CONFIGURED:
-#ifdef SELF_POWER
- dev_cfg_status = USB_CONFIG_SELF_POWERED;
-#else
- dev_cfg_status = 0x00U;
-#endif
- if (0U != pdev->dev.device_remote_wakeup) {
- dev_cfg_status |= USB_CONFIG_REMOTE_WAKEUP;
- }
- usb_ctrldatatx(pdev, (uint8_t *)&dev_cfg_status, 2U);
- break;
- default :
- usb_ctrlerr(pdev);
- break;
- }
-}
-
-/**
- * @brief usb_getintf
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_getintf(usb_core_instance *pdev)
-{
- dev_cfg_status = 0U;
- usb_ctrldatatx(pdev, (uint8_t *)&dev_cfg_status, 1U);
-}
-
-/**
- * @brief Handle Set device feature request
- * @param [in] pdev device instance
- * @param [in] req usb request
- * @retval None
- */
-void usb_setfeature(usb_core_instance *pdev, USB_SETUP_REQ *req)
-{
- uint32_t dctl;
- uint8_t test_mode;
-
- if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) {
- pdev->dev.device_remote_wakeup = 1U;
- pdev->dev.class_callback->ep0_setup(pdev, req);
- usb_ctrlstatustx(pdev);
- } else if ((req->wValue == USB_FEATURE_TEST_MODE) && ((req->wIndex & 0xFFU) == 0U)) {
- dctl = READ_REG32(pdev->regs.DREGS->DCTL);
- (void)(dctl);
- test_mode = (uint8_t)req->wIndex >> 8U;
- test_mode = test_mode & (uint8_t)(~0xF8U);
- dctl = (uint32_t)test_mode << 4U;
- SET_TEST_MODE = dctl;
- pdev->dev.test_mode = 1U;
- usb_ctrlstatustx(pdev);
- } else {
- ;
- }
-}
-
-/**
- * @brief Handle clear device feature request
- * @param [in] pdev device instance
- * @param [in] req usb request
- * @retval None
- */
-void usb_clrfeature(usb_core_instance *pdev, USB_SETUP_REQ *req)
-{
- switch (pdev->dev.device_cur_status) {
- case USB_DEV_ADDRESSED:
- case USB_DEV_CONFIGURED:
- if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) {
- pdev->dev.device_remote_wakeup = 0U;
- pdev->dev.class_callback->ep0_setup(pdev, req);
- usb_ctrlstatustx(pdev);
- }
- break;
- default :
- usb_ctrlerr(pdev);
- break;
- }
-}
-
-/**
- * @brief Copy buffer into setup structure
- * @param [in] pdev device instance
- * @param [in] req usb request
- * @retval None
- */
-void usb_parsesetupreq(usb_core_instance *pdev, USB_SETUP_REQ *req)
-{
- req->bmRequest = *(uint8_t *)(pdev->dev.setup_pkt_buf);
- req->bRequest = *(uint8_t *)(pdev->dev.setup_pkt_buf + 1U);
- req->wValue = SWAPBYTE(pdev->dev.setup_pkt_buf + 2U);
- req->wIndex = SWAPBYTE(pdev->dev.setup_pkt_buf + 4U);
- req->wLength = SWAPBYTE(pdev->dev.setup_pkt_buf + 6U);
-
- pdev->dev.in_ep[0].ctl_data_len = req->wLength;
- pdev->dev.device_state = USB_EP0_SETUP;
-}
-
-/**
- * @brief Handle USB low level Error
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_ctrlerr(usb_core_instance *pdev)
-{
- usb_stalldevep(pdev, 0x80U);
- usb_stalldevep(pdev, 0U);
- usb_ep0outstart(pdev);
-}
-
-/**
- * @brief Convert Ascii string into unicode one
- * @param [in] desc descriptor buffer
- * @param [in] unicode Formatted string buffer (unicode)
- * @param [in] len descriptor length
- * @retval None
- */
-void usb_getstring(uint8_t *desc, uint8_t *unicode, uint16_t *len)
-{
- uint8_t tmp_idx = 0U;
-
- if (desc != NULL) {
- *len = (uint16_t)usb_getlength(desc) * 2U + 2U;
- unicode[tmp_idx++] = (uint8_t) * len;
- unicode[tmp_idx++] = USB_DESC_TYPE_STRING;
-
- while (*desc != (uint8_t)0U) {
- unicode[tmp_idx++] = *desc++;
- unicode[tmp_idx++] = 0x00U;
- }
- }
-}
-
-/**
- * @brief get the string length
- * @param [in] buf pointer to the ascii string buffer
- * @retval string length
- */
-uint8_t usb_getlength(uint8_t *buf)
-{
- uint8_t tmp_len = 0U;
-
- while (*buf != (uint8_t)0U) {
- tmp_len++;
- buf++;
- }
- return tmp_len;
-}
-
-/**
- * @brief set current configuration or clear current configuration
- * @param [in] pdev device instance
- * @param [in] cfgidx configuration index
- * @param [in] action USB_DEV_CONFIG_SET or USB_DEV_CONFIG_CLEAR
- * @retval None
- */
-void usb_dev_ctrlconfig(usb_core_instance *pdev, uint8_t cfgidx, uint8_t action)
-{
- __IO uint8_t tmp_1;
-
- (void)(cfgidx);
- tmp_1 = action;
- if (tmp_1 == USB_DEV_CONFIG_SET) { /* set configuration */
- pdev->dev.class_callback->class_init(pdev);
- pdev->dev.user_callback->user_devconfig();
- } else if (tmp_1 == USB_DEV_CONFIG_CLEAR) { /* clear configuration */
- pdev->dev.class_callback->class_deinit(pdev);
- } else {
- ;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************************************************************************
- * EOF (not truncated)
- *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_stdreq.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_stdreq.h
deleted file mode 100644
index 2e97905cd4..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_stdreq.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_dev_stdreq.h
- * @brief header file for the usb_dev_stdreq.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_DEV_STDREQ_H__
-#define __USB_DEV_STDREQ_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_dev_def.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_DEV_CORE
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-void usb_standarddevreq(usb_core_instance *pdev, USB_SETUP_REQ *req);
-void usb_standarditfreq(usb_core_instance *pdev, USB_SETUP_REQ *req);
-void usb_standardepreq(usb_core_instance *pdev, USB_SETUP_REQ *req);
-void usb_parsesetupreq(usb_core_instance *pdev, USB_SETUP_REQ *req);
-void usb_ctrlerr(usb_core_instance *pdev);
-void usb_getstring(uint8_t *desc, uint8_t *unicode, uint16_t *len);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_DEV_STDREQ_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_class.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_class.c
deleted file mode 100644
index 5e6e1bc341..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_class.c
+++ /dev/null
@@ -1,681 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_cdc_class.c
- * @brief cdc class related functions
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2023-06-30 CDT Modify for variable alignment
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_cdc_class.h"
-#include "usb_host_driver.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CDC USB Host CDC
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-CDC_Requests CDC_ReqState;
-CDC_Usercb_TypeDef UserCb;
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-__USB_ALIGN_BEGIN static CDC_Machine_TypeDef CDC_Machine;
-
-__USB_ALIGN_BEGIN static CDC_Xfer_TypeDef CDC_TxParam;
-__USB_ALIGN_BEGIN static CDC_Xfer_TypeDef CDC_RxParam;
-
-__USB_ALIGN_BEGIN static uint8_t TxBuf[CDC_BUFFER_SIZE];
-__USB_ALIGN_BEGIN static uint8_t RxBuf[CDC_BUFFER_SIZE];
-
-static uint8_t RX_Enabled = 0;
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-static void usb_host_cdc_txrxparam_init(void);
-
-static void usb_host_cdc_receivedata(CDC_Xfer_TypeDef *cdc_Data);
-
-static void usb_host_cdc_senddata_process(usb_core_instance *pdev, USBH_HOST *phost);
-
-static void usb_host_cdc_receivedata_process(usb_core_instance *pdev, USBH_HOST *phost);
-
-static HOST_STATUS usb_host_cdc_interface_init(usb_core_instance *pdev, void *phost);
-
-void usb_host_cdc_interface_deinit(usb_core_instance *pdev);
-
-static HOST_STATUS usb_host_cdc_class_process(usb_core_instance *pdev, void *phost);
-
-static HOST_STATUS usb_host_cdc_class_request(usb_core_instance *pdev, void *phost);
-
-usb_host_class_callback_func CDC_cb = {
- usb_host_cdc_interface_init,
- usb_host_cdc_interface_deinit,
- usb_host_cdc_class_request,
- usb_host_cdc_class_process
-};
-
-/**
- * @brief init the vendor interface
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval status defined by HOST_STATUS
- */
-static HOST_STATUS usb_host_cdc_vendor_interface_init(usb_core_instance *pdev, void *phost)
-{
- USBH_HOST *pphost = phost;
- HOST_STATUS status = HSTATUS_UNSUPPORTED;
- uint8_t idxep;
- uint8_t bulk_inep_cnt, bulk_inep_idx = 0U;
- uint8_t bulk_outep_cnt, bulk_outep_idx = 0U;
- uint8_t intr_inep_cnt = 0U, intr_inep_idx = 0U;
- /* try to support vendor cdc device */
- if (pphost->device_prop.devitfdesc[0].bInterfaceClass == VENDOR_SPECIFIC) {
- if (pphost->device_prop.devitfdesc[0].bNumEndpoints < 2U) {
- return HSTATUS_UNSUPPORTED;
- }
- bulk_inep_cnt = 0;
- bulk_outep_cnt = 0;
- for (idxep = 0; idxep < pphost->device_prop.devitfdesc[0].bNumEndpoints; idxep++) {
- if ((pphost->device_prop.devepdesc[0][idxep].bmAttributes & EP_TYPE_MSK) == EP_TYPE_BULK) {
- if (0U != (pphost->device_prop.devepdesc[0][idxep].bEndpointAddress & 0x80U)) {
- bulk_inep_cnt++;
- bulk_inep_idx = idxep;
- } else {
- bulk_outep_cnt++;
- bulk_outep_idx = idxep;
- }
- } else if ((pphost->device_prop.devepdesc[0][idxep].bmAttributes & EP_TYPE_MSK) == EP_TYPE_INTR) {
- if (0U != (pphost->device_prop.devepdesc[0][idxep].bEndpointAddress & 0x80U)) {
- intr_inep_cnt++;
- intr_inep_idx = idxep;
- }
- } else {
- ;
- }
- }
- if ((bulk_inep_cnt != 1U) || (bulk_outep_cnt != 1U)) {
- return HSTATUS_UNSUPPORTED;
- }
-
- if (bulk_inep_cnt == 1U) {
- /* fill the communication endpoint address and length */
- CDC_Machine.CDC_CommItf.ep_addr = pphost->device_prop.devepdesc[0][intr_inep_idx].bEndpointAddress;
- CDC_Machine.CDC_CommItf.length = pphost->device_prop.devepdesc[0][intr_inep_idx].wMaxPacketSize;
-
- if (0U != (pphost->device_prop.devepdesc[0][intr_inep_idx].bEndpointAddress & 0x80U)) {
- CDC_Machine.CDC_CommItf.notificationEp =
- (pphost->device_prop.devepdesc[0][intr_inep_idx].bEndpointAddress);
- }
- /* distribute a channel for communication endpoint */
- CDC_Machine.CDC_CommItf.hc_num_in = usb_host_distrch(pdev,
- CDC_Machine.CDC_CommItf.notificationEp);
-
- /* open channel for communication endpoint */
- usb_host_chopen(pdev,
- CDC_Machine.CDC_CommItf.hc_num_in,
- pphost->device_prop.devaddr,
- pphost->device_prop.devspeed,
- EP_TYPE_INTR,
- CDC_Machine.CDC_CommItf.length);
- }
-
- /* fill cdc data endpoint address and length */
- CDC_Machine.CDC_DataItf.ep_addr = pphost->device_prop.devepdesc[0][bulk_inep_idx].bEndpointAddress;
- CDC_Machine.CDC_DataItf.length = pphost->device_prop.devepdesc[0][bulk_inep_idx].wMaxPacketSize;
-
- CDC_Machine.CDC_DataItf.cdcInEp = (pphost->device_prop.devepdesc[0][bulk_inep_idx].bEndpointAddress);
- CDC_Machine.CDC_DataItf.cdcOutEp = (pphost->device_prop.devepdesc[0][bulk_outep_idx].bEndpointAddress);
-
- /* distribute channels for cdc data endpoints */
- CDC_Machine.CDC_DataItf.hc_num_out = usb_host_distrch(pdev,
- CDC_Machine.CDC_DataItf.cdcOutEp);
-
- CDC_Machine.CDC_DataItf.hc_num_in = usb_host_distrch(pdev,
- CDC_Machine.CDC_DataItf.cdcInEp);
-
- /* open cdc data endpoints */
- usb_host_chopen(pdev,
- CDC_Machine.CDC_DataItf.hc_num_out,
- pphost->device_prop.devaddr,
- pphost->device_prop.devspeed,
- EP_TYPE_BULK,
- CDC_Machine.CDC_DataItf.length);
-
- usb_host_chopen(pdev,
- CDC_Machine.CDC_DataItf.hc_num_in,
- pphost->device_prop.devaddr,
- pphost->device_prop.devspeed,
- EP_TYPE_BULK,
- CDC_Machine.CDC_DataItf.length);
-
- /* txrx parms init */
- usb_host_cdc_txrxparam_init();
-
- /* host next state is HOST_CLASS_REQ, so set cdc request to GET_LINE_CODING */
- CDC_ReqState = CDC_GET_LINE_CODING_RQUEST;
-
- status = HSTATUS_OK;
- }
- return status;
-}
-
-/**
- * @brief init the std cdc interface
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval status defined by HOST_STATUS
- */
-static HOST_STATUS usb_host_cdc_interface_init(usb_core_instance *pdev, void *phost)
-{
- USBH_HOST *pphost = phost;
- HOST_STATUS status = HSTATUS_OK;
- uint8_t unsupport_cnt = 0;
-
- /* Communication Interface */
- if ((pphost->device_prop.devitfdesc[0].bInterfaceClass == COMMUNICATION_DEVICE_CLASS_CODE) &&
- (pphost->device_prop.devitfdesc[0].bInterfaceSubClass == ABSTRACT_CONTROL_MODEL) &&
- (pphost->device_prop.devitfdesc[0].bInterfaceProtocol == COMMON_AT_COMMAND)) {
- /* fill the communication endpoint address and length */
- CDC_Machine.CDC_CommItf.ep_addr = pphost->device_prop.devepdesc[0][0].bEndpointAddress;
- CDC_Machine.CDC_CommItf.length = pphost->device_prop.devepdesc[0][0].wMaxPacketSize;
-
- if (0U != (pphost->device_prop.devepdesc[0][0].bEndpointAddress & 0x80U)) {
- CDC_Machine.CDC_CommItf.notificationEp =
- (pphost->device_prop.devepdesc[0][0].bEndpointAddress);
- }
- /* distribute a channel for communication endpoint */
- CDC_Machine.CDC_CommItf.hc_num_in = usb_host_distrch(pdev,
- CDC_Machine.CDC_CommItf.notificationEp);
-
- /* open channel for communication endpoint */
- usb_host_chopen(pdev,
- CDC_Machine.CDC_CommItf.hc_num_in,
- pphost->device_prop.devaddr,
- pphost->device_prop.devspeed,
- EP_TYPE_INTR,
- CDC_Machine.CDC_CommItf.length);
- } else {
- pphost->user_callbk->huser_devunsupported();
- unsupport_cnt++;
- }
-
- /* Data Interface */
- if ((pphost->device_prop.devitfdesc[1].bInterfaceClass == DATA_INTERFACE_CLASS_CODE) &&
- (pphost->device_prop.devitfdesc[1].bInterfaceSubClass == RESERVED) &&
- (pphost->device_prop.devitfdesc[1].bInterfaceProtocol == NO_CLASS_SPECIFIC_PROTOCOL_CODE)) {
- /* fill cdc data endpoint address and length */
- CDC_Machine.CDC_DataItf.ep_addr = pphost->device_prop.devepdesc[1][0].bEndpointAddress;
- CDC_Machine.CDC_DataItf.length = pphost->device_prop.devepdesc[1][0].wMaxPacketSize;
-
- if (0U != (pphost->device_prop.devepdesc[1][0].bEndpointAddress & 0x80U)) {
- CDC_Machine.CDC_DataItf.cdcInEp = (pphost->device_prop.devepdesc[1][0].bEndpointAddress);
- } else {
- CDC_Machine.CDC_DataItf.cdcOutEp = (pphost->device_prop.devepdesc[1][0].bEndpointAddress);
- }
-
- if (0U != (pphost->device_prop.devepdesc[1][1].bEndpointAddress & 0x80U)) {
- CDC_Machine.CDC_DataItf.cdcInEp = (pphost->device_prop.devepdesc[1][1].bEndpointAddress);
- } else {
- CDC_Machine.CDC_DataItf.cdcOutEp = (pphost->device_prop.devepdesc[1][1].bEndpointAddress);
- }
-
- /* distribute channels for cdc data endpoints */
- CDC_Machine.CDC_DataItf.hc_num_out = usb_host_distrch(pdev,
- CDC_Machine.CDC_DataItf.cdcOutEp);
-
- CDC_Machine.CDC_DataItf.hc_num_in = usb_host_distrch(pdev,
- CDC_Machine.CDC_DataItf.cdcInEp);
-
- /* open cdc data endpoints */
- usb_host_chopen(pdev,
- CDC_Machine.CDC_DataItf.hc_num_out,
- pphost->device_prop.devaddr,
- pphost->device_prop.devspeed,
- EP_TYPE_BULK,
- CDC_Machine.CDC_DataItf.length);
-
- usb_host_chopen(pdev,
- CDC_Machine.CDC_DataItf.hc_num_in,
- pphost->device_prop.devaddr,
- pphost->device_prop.devspeed,
- EP_TYPE_BULK,
- CDC_Machine.CDC_DataItf.length);
-
- /* txrx parms init */
- usb_host_cdc_txrxparam_init();
-
- /* host next state is HOST_CLASS_REQ, so set cdc request to GET_LINE_CODING */
- CDC_ReqState = CDC_GET_LINE_CODING_RQUEST;
- } else {
- pphost->user_callbk->huser_devunsupported();
- unsupport_cnt++;
- }
-
- /* not a stand CDC ACM device */
- if (2U == unsupport_cnt) {
- if (HSTATUS_OK != usb_host_cdc_vendor_interface_init(pdev, phost)) {
- pphost->user_callbk->huser_devunsupported();
- }
- }
-
- return status;
-}
-
-/**
- * @brief deinit the cdc interface
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_host_cdc_interface_deinit(usb_core_instance *pdev)
-{
- /* halt and free all channels */
- if (0U != CDC_Machine.CDC_CommItf.hc_num_in) {
- usb_hchstop(&pdev->regs, CDC_Machine.CDC_CommItf.hc_num_in);
- (void)usb_host_freech(pdev, CDC_Machine.CDC_CommItf.hc_num_in);
- CDC_Machine.CDC_CommItf.hc_num_in = 0;
- }
-
- if (0U != CDC_Machine.CDC_DataItf.hc_num_out) {
- usb_hchstop(&pdev->regs, CDC_Machine.CDC_DataItf.hc_num_out);
- (void)usb_host_freech(pdev, CDC_Machine.CDC_DataItf.hc_num_out);
- CDC_Machine.CDC_DataItf.hc_num_out = 0;
- }
-
- if (0U != CDC_Machine.CDC_DataItf.hc_num_in) {
- usb_hchstop(&pdev->regs, CDC_Machine.CDC_DataItf.hc_num_in);
- (void)usb_host_freech(pdev, CDC_Machine.CDC_DataItf.hc_num_in);
- CDC_Machine.CDC_DataItf.hc_num_in = 0;
- }
-}
-
-/**
- * @brief handing host class request state
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval status defined by HOST_STATUS
- */
-static HOST_STATUS usb_host_cdc_class_request(usb_core_instance *pdev, void *phost)
-{
- USBH_HOST *pphost = phost;
-
- HOST_STATUS status = HSTATUS_BUSY;
- HOST_STATUS ClassReqStatus;
-
- switch (CDC_ReqState) {
-
- case CDC_GET_LINE_CODING_RQUEST:
-
- ClassReqStatus = usb_host_cdc_getlinecoding(pdev, phost);
- if (ClassReqStatus == HSTATUS_OK) {
- CDC_ReqState = CDC_SET_CONTROL_LINE_STATE_REQUEST;
- }
- break;
-
- case CDC_SET_LINE_CODING_RQUEST:
-
- ClassReqStatus = usb_host_cdc_setlinecoding(pdev, phost);
- if (ClassReqStatus == HSTATUS_OK) {
- CDC_ReqState = CDC_GET_LINE_CODING_RQUEST;
- }
- if (ClassReqStatus == HSTATUS_UNSUPPORTED) {
- /* Clear Feature should be issued */
- CDC_ReqState = CDC_ERROR_STATE;
- }
- break;
-
- case CDC_SET_CONTROL_LINE_STATE_REQUEST:
-
- ClassReqStatus = usb_host_cdc_setcontrollinestate(pdev, phost);
- if (ClassReqStatus == HSTATUS_OK) {
- /* change state to itself */
- CDC_ReqState = CDC_SET_CONTROL_LINE_STATE_REQUEST;
- /* change rx state to CDC_IDLE */
- CDC_RxParam.CDCState = CDC_IDLE;
-
- status = HSTATUS_OK;
- }
- break;
-
- case CDC_ERROR_STATE:
-
- ClassReqStatus = usb_host_clrfeature(pdev,
- phost,
- 0x00,
- pphost->ctrlparam.hc_num_out);
-
- if (ClassReqStatus == HSTATUS_OK) {
- /* change state to GET_LINE_CODING */
- CDC_ReqState = CDC_GET_LINE_CODING_RQUEST;
- }
- break;
- default:
- break;
- }
-
- return status;
-}
-
-/**
- * @brief process the cdc data send/receive state machine and user application
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval status defined by HOST_STATUS
- */
-static HOST_STATUS usb_host_cdc_class_process(usb_core_instance *pdev, void *phost)
-{
- HOST_STATUS status = HSTATUS_OK;
- USBH_HOST *pphost = phost;
-
- /* application process */
- pphost->user_callbk->huser_application();
-
- if (CDC_ReqState == CDC_SET_LINE_CODING_RQUEST) {
- return status;
- }
- /* send data process */
- usb_host_cdc_senddata_process(pdev, pphost);
-
- /* receive data process */
- usb_host_cdc_receivedata_process(pdev, pphost);
-
- return status;
-}
-
-/**
- * @brief process the cdc data send state machine
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval None
- */
-void usb_host_cdc_senddata_process(usb_core_instance *pdev, USBH_HOST *phost)
-{
- static uint16_t len;
- HOST_CH_XFER_STATE URB_StatusTx;
-
- URB_StatusTx = host_driver_getxferstate(pdev, CDC_Machine.CDC_DataItf.hc_num_out);
-
- switch (CDC_TxParam.CDCState) {
- case CDC_IDLE:
- break;
-
- case CDC_SEND_DATA:
-
- if ((URB_StatusTx == HOST_CH_XFER_DONE) || (URB_StatusTx == HOST_CH_XFER_IDLE)) {
- /* check if send data len exceed CDC_DataItf.length */
- if (CDC_TxParam.DataLength > CDC_Machine.CDC_DataItf.length) {
-
- len = CDC_Machine.CDC_DataItf.length;
- /* send data */
- usb_host_sendbulkdata(pdev,
- CDC_TxParam.pRxTxBuff,
- len,
- CDC_Machine.CDC_DataItf.hc_num_out);
- } else {
- len = CDC_TxParam.DataLength;
- /* send all the remaining data */
- usb_host_sendbulkdata(pdev,
- CDC_TxParam.pRxTxBuff,
- len,
- CDC_Machine.CDC_DataItf.hc_num_out);
- }
- CDC_TxParam.CDCState = CDC_DATA_SENT;
- }
-
- break;
-
- case CDC_DATA_SENT:
- /* check send complete */
- if (URB_StatusTx == HOST_CH_XFER_DONE) {
- /* move txbuffer point */
- CDC_TxParam.pRxTxBuff += len;
-
- /* ecrease data length */
- CDC_TxParam.DataLength -= len;
-
- if (CDC_TxParam.DataLength == 0U) {
- CDC_TxParam.CDCState = CDC_IDLE;
- } else {
- CDC_TxParam.CDCState = CDC_SEND_DATA;
- }
- } else if (URB_StatusTx == HOST_CH_XFER_UNREADY) {
- /* send again */
- usb_host_sendbulkdata(pdev,
- (CDC_TxParam.pRxTxBuff),
- len,
- CDC_Machine.CDC_DataItf.hc_num_out);
- } else {
- ;
- }
-
- break;
-
- case CDC_READ_DATA:
- break;
-
- case CDC_BUSY:
- break;
-
- case CDC_GET_DATA:
- break;
-
- case CDC_POLL:
- break;
-
- case CDC_CTRL_STATE:
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief process the cdc data receive state machine
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval None
- */
-static void usb_host_cdc_receivedata_process(usb_core_instance *pdev, USBH_HOST *phost)
-{
-
- if (RX_Enabled == 1U) {
- HOST_CH_XFER_STATE URB_StatusRx = host_driver_getxferstate(pdev, CDC_Machine.CDC_DataItf.hc_num_in);
-
- switch (CDC_RxParam.CDCState) {
-
- case CDC_IDLE:
-
- /* check if free rxbuf exceed CDC_DataItf.length */
- if (CDC_RxParam.DataLength < (CDC_RxParam.BufferLen - CDC_Machine.CDC_DataItf.length)) {
- /* receive data */
- usb_host_recvbulkdata(pdev,
- CDC_RxParam.pFillBuff,
- CDC_Machine.CDC_DataItf.length,
- CDC_Machine.CDC_DataItf.hc_num_in);
-
- /* change sate to wait receive complete */
- CDC_RxParam.CDCState = CDC_GET_DATA;
- }
- break;
-
- case CDC_GET_DATA:
- /* check XFER_DONE */
- if (URB_StatusRx == HOST_CH_XFER_DONE) {
- /* increase rx data len */
- CDC_RxParam.DataLength += (uint16_t)pdev->host.hc[CDC_Machine.CDC_DataItf.hc_num_in].xfer_count;
- /* move rxbuff poinit */
- CDC_RxParam.pFillBuff += pdev->host.hc[CDC_Machine.CDC_DataItf.hc_num_in].xfer_count;
-
- /* process the received data */
- usb_host_cdc_receivedata(&CDC_RxParam);
-
- /* chage state back to CDC_IDLE */
- CDC_RxParam.CDCState = CDC_IDLE;
- }
- break;
-
- case CDC_READ_DATA:
-
- break;
-
- case CDC_BUSY:
-
- break;
-
- case CDC_SEND_DATA:
-
- break;
-
- case CDC_DATA_SENT:
-
- break;
-
- case CDC_POLL:
-
- break;
-
- case CDC_CTRL_STATE:
-
- break;
- default:
- break;
- }
- }
-}
-
-/**
- * @brief init tx rx buffer for cdc
- * @param None
- * @retval None
- */
-static void usb_host_cdc_txrxparam_init(void)
-{
- /* init tx buffer */
- CDC_TxParam.CDCState = CDC_IDLE;
- CDC_TxParam.DataLength = 0;
- CDC_TxParam.pRxTxBuff = TxBuf;
-
- /* init rx buffer */
- CDC_RxParam.CDCState = CDC_IDLE;
- CDC_RxParam.DataLength = 0;
- CDC_RxParam.pFillBuff = RxBuf;
- CDC_RxParam.pEmptyBuff = RxBuf;
- CDC_RxParam.BufferLen = sizeof(RxBuf);
-}
-
-/**
- * @brief call user callback fucntion to process the received data
- * @param [in] cdc_Data type of CDC_Xfer_TypeDef
- * @retval None
- */
-static void usb_host_cdc_receivedata(CDC_Xfer_TypeDef *cdc_Data)
-{
- uint8_t *ptr;
-
- if (cdc_Data->pEmptyBuff < cdc_Data->pFillBuff) {
- ptr = cdc_Data->pFillBuff;
- *ptr = 0x00;
-
- /* callback user function to process received data */
- UserCb.Receive(cdc_Data->pEmptyBuff, cdc_Data->DataLength);
-
- cdc_Data->pFillBuff = cdc_Data->pEmptyBuff;
- cdc_Data->DataLength = 0;
- }
-}
-
-/**
- * @brief user call this function to send data to cdc device
- * @param [in] data send data buffer
- * @param [in] length send length
- * @retval None
- */
-void usb_host_cdc_senddata(uint8_t *data, uint16_t length)
-{
-
- if (CDC_TxParam.CDCState == CDC_IDLE) {
- CDC_TxParam.pRxTxBuff = data;
- CDC_TxParam.DataLength = length;
- CDC_TxParam.CDCState = CDC_SEND_DATA;
- }
-}
-
-/**
- * @brief user call this function to enable receive data from device
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_host_cdc_enable_receive(usb_core_instance *pdev)
-{
- RX_Enabled = 1;
-}
-
-/**
- * @brief user call this function to disable receive data from device
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_host_cdc_disable_receive(usb_core_instance *pdev)
-{
- RX_Enabled = 0;
- usb_hchstop(&pdev->regs, CDC_Machine.CDC_DataItf.hc_num_in);
- (void)usb_host_freech(pdev, CDC_Machine.CDC_DataItf.hc_num_in);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_class.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_class.h
deleted file mode 100644
index 1aa0d62d28..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_class.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_cdc_class.h
- * @brief Head file for usb_host_cdc_class.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_HOST_CDC_CLASS_H__
-#define __USB_HOST_CDC_CLASS_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_cdc_ctrl.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CDC
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-typedef enum {
- CDC_IDLE = 0,
- CDC_READ_DATA,
- CDC_SEND_DATA,
- CDC_DATA_SENT,
- CDC_BUSY,
- CDC_GET_DATA,
- CDC_POLL,
- CDC_CTRL_STATE
-}
-CDC_State;
-
-typedef struct _CDCXfer {
- volatile CDC_State CDCState;
- uint8_t *pRxTxBuff;
- uint8_t *pFillBuff;
- uint8_t *pEmptyBuff;
- uint32_t BufferLen;
- uint16_t DataLength;
-} CDC_Xfer_TypeDef;
-
-typedef struct CDC_UserCb {
- void (*Send)(uint8_t *);
- void (*Receive)(uint8_t *, uint32_t len);
-
-} CDC_Usercb_TypeDef;
-
-typedef struct _CDC_CommInterface {
- uint8_t hc_num_in;
- uint8_t hc_num_out;
- uint8_t notificationEp;
- CDC_State state;
- uint8_t buff[8];
- uint16_t length;
- uint8_t ep_addr;
-}
-CDC_CommInterface_Typedef ;
-
-typedef struct _CDC_DataInterface {
- uint8_t hc_num_in;
- uint8_t hc_num_out;
- uint8_t cdcOutEp;
- uint8_t cdcInEp;
- CDC_State state;
- uint8_t buff[8];
- uint16_t length;
- uint8_t ep_addr;
-}
-CDC_DataInterface_Typedef ;
-
-typedef struct _CDC_Process {
- CDC_CommInterface_Typedef CDC_CommItf;
- CDC_DataInterface_Typedef CDC_DataItf;
-}
-CDC_Machine_TypeDef;
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#define COMMUNICATION_DEVICE_CLASS_CODE (0x02U)
-#define COMMUNICATION_INTERFACE_CLASS_CODE (0x02U)
-
-#define DATA_INTERFACE_CLASS_CODE (0x0AU)
-
-#define RESERVED (0x00U)
-#define DIRECT_LINE_CONTROL_MODEL (0x01U)
-#define ABSTRACT_CONTROL_MODEL (0x02U)
-#define TELEPHONE_CONTROL_MODEL (0x03U)
-#define MULTICHANNEL_CONTROL_MODEL (0x04U)
-#define CAPI_CONTROL_MODEL (0x05U)
-#define ETHERNET_NETWORKING_CONTROL_MODEL (0x06U)
-#define ATM_NETWORKING_CONTROL_MODEL (0x07U)
-
-#define NO_CLASS_SPECIFIC_PROTOCOL_CODE (0x00U)
-#define COMMON_AT_COMMAND (0x01U)
-#define VENDOR_SPECIFIC (0xFFU)
-
-#define CS_INTERFACE (0x24U)
-#define CDC_PAGE_SIZE_64 (0x40U)
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-extern usb_host_class_callback_func CDC_cb;
-extern CDC_Usercb_TypeDef UserCb;
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-void usb_host_cdc_senddata(uint8_t *data, uint16_t length);
-void usb_host_cdc_enable_receive(usb_core_instance *pdev);
-void usb_host_cdc_disable_receive(usb_core_instance *pdev);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_HOST_CDC_CLASS_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_ctrl.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_ctrl.c
deleted file mode 100644
index 4ce61715e2..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_ctrl.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_cdc_ctrl.c
- * @brief The CDC ctrl functions
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_cdc_ctrl.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CDC
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-extern CDC_Requests CDC_ReqState;
-CDC_LineCodingTypeDef CDC_SetLineCode;
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-static CDC_InterfaceDesc_Typedef CDC_Desc;
-static CDC_LineCodingTypeDef CDC_GetLineCode;
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-/**
- * @brief host send ctrl request to get line coding
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval status define by HOST_STATUS
- */
-HOST_STATUS usb_host_cdc_getlinecoding(usb_core_instance *pdev, USBH_HOST *phost)
-{
- phost->ctrlparam.setup.b.bmRequestType = USB_D2H | USB_REQ_TYPE_CLASS | \
- USB_REQ_RECIPIENT_INTERFACE;
-
- phost->ctrlparam.setup.b.bRequest = CDC_GET_LINE_CODING;
- phost->ctrlparam.setup.b.wValue.w = 0;
- phost->ctrlparam.setup.b.wIndex.w = CDC_Desc.CDC_UnionFuncDesc.bControlInterface;
- phost->ctrlparam.setup.b.wLength.w = LINE_CODING_STRUCTURE_SIZE;
-
- return usb_host_ctrlreq(pdev, phost, CDC_GetLineCode.Array, LINE_CODING_STRUCTURE_SIZE);
-}
-
-/**
- * @brief host send ctrl request to set line coding
- * to config Baud rate/Stop bits/Parity/Data bits
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval status define by HOST_STATUS
- */
-HOST_STATUS usb_host_cdc_setlinecoding(usb_core_instance *pdev, USBH_HOST *phost)
-{
-
- phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_TYPE_CLASS | \
- USB_REQ_RECIPIENT_INTERFACE;
-
- phost->ctrlparam.setup.b.bRequest = CDC_SET_LINE_CODING;
- phost->ctrlparam.setup.b.wValue.w = 0;
-
- phost->ctrlparam.setup.b.wIndex.w = CDC_Desc.CDC_UnionFuncDesc.bControlInterface;
-
- phost->ctrlparam.setup.b.wLength.w = LINE_CODING_STRUCTURE_SIZE;
-
- return usb_host_ctrlreq(pdev, phost, CDC_SetLineCode.Array, LINE_CODING_STRUCTURE_SIZE);
-}
-
-/**
- * @brief host send ctrl request to set control line state
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval status define by HOST_STATUS
- */
-HOST_STATUS usb_host_cdc_setcontrollinestate(usb_core_instance *pdev, USBH_HOST *phost)
-{
- phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_TYPE_CLASS | \
- USB_REQ_RECIPIENT_INTERFACE;
-
- phost->ctrlparam.setup.b.bRequest = CDC_SET_CONTROL_LINE_STATE;
-
- phost->ctrlparam.setup.b.wValue.w = CDC_DEACTIVATE_CARRIER_SIGNAL_RTS | \
- CDC_DEACTIVATE_SIGNAL_DTR;
-
- phost->ctrlparam.setup.b.wIndex.w = CDC_Desc.CDC_UnionFuncDesc.bControlInterface;
-
- phost->ctrlparam.setup.b.wLength.w = 0;
-
- return usb_host_ctrlreq(pdev, phost, NULL, 0U);
-}
-
-/**
- * @brief user call this function to issue set line coding request
- * before call this funtion user need fill CDC_SetLineCode with config params
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval None
- */
-void usb_host_cdc_issue_setlinecoding(usb_core_instance *pdev, USBH_HOST *phost)
-{
- phost->host_state_backup = phost->host_state ;
- phost->host_state = HOST_CLASS_REQ;
- CDC_ReqState = CDC_SET_LINE_CODING_RQUEST;
-}
-
-/**
- * @brief user call this function to issue get line coding request
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval None
- */
-void usb_host_cdc_issue_getlinecoding(usb_core_instance *pdev, USBH_HOST *phost)
-{
- phost->host_state_backup = phost->host_state ;
- phost->host_state = HOST_CLASS_REQ;
- CDC_ReqState = CDC_GET_LINE_CODING_RQUEST;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_ctrl.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_ctrl.h
deleted file mode 100644
index 0c1e1e7dc9..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_ctrl.h
+++ /dev/null
@@ -1,221 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_cdc_ctrl.h
- * @brief Head file for usb_host_cdc_ctrl.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __USB_HOST_CDC_CTRL_H__
-#define __USB_HOST_CDC_CTRL_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_core.h"
-#include "usb_host_stdreq.h"
-#include "usb_host_ctrltrans.h"
-#include "usb_host_cfgch.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CDC
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-typedef enum {
- CDC_SET_LINE_CODING_RQUEST = 0,
- CDC_GET_LINE_CODING_RQUEST,
- CDC_SET_CONTROL_LINE_STATE_REQUEST,
- CDC_ERROR_STATE
-}
-CDC_Requests;
-
-#define LINE_CODING_STRUCTURE_SIZE (0x07U)
-typedef union _CDC_LineCodingStructure {
- uint8_t Array[LINE_CODING_STRUCTURE_SIZE];
-
- struct {
-
- uint32_t dwDTERate; /* Data terminal rate, in bits per second */
- /* Data terminal rate:
- such as 9600, 115200, ... */
-
- uint8_t bCharFormat; /* Stop bits */
- /* Stop bits:
- 0 - 1 Stop bit
- 1 - 1.5 Stop bits
- 2 - 2 Stop bits */
-
- uint8_t bParityType; /* Parity */
- /* Parity:
- 0 - None
- 1 - Odd
- 2 - Even
- 3 - Mark
- 4 - Space */
-
- uint8_t bDataBits; /* Data bits */
- /* Data bits:
- (5, 6, 7, 8 or 16) */
- } b;
-}
-CDC_LineCodingTypeDef;
-
-typedef struct _FunctionalDescriptorHeader {
- uint8_t bLength; /* Size of this descriptor in bytes */
- uint8_t bDescriptorType; /* CS_INTERFACE(24h) descriptor type */
- uint8_t bDescriptorSubType; /* Header functional descriptor subtype */
- uint16_t bcdCDC; /* USB Class Definitions for Communications
- Devices Specification release number in
- binary-coded decima */
-}
-CDC_HeaderFuncDesc_TypeDef;
-
-typedef struct _CallMgmtFunctionalDescriptor {
- uint8_t bLength; /* Size of this functional descriptor, in bytes */
- uint8_t bDescriptorType; /* CS_INTERFACE(24h) */
- uint8_t bDescriptorSubType; /* Call Management functional descriptor subtype */
- uint8_t bmCapabilities; /* The capabilities that this configuration supports */
- /* capabilities:
- D7..D2: RESERVED (Reset to zero)
- D1: 0 - Device sends/receives call management
- information only over the Communications Class
- interface.
- 1 - Device can send/receive call management
- information over a Data Class interface.
- D0: 0 - Device does not handle call management
- itself.
- 1 - Device handles call management itself
- The previous bits, in combination, identify which call
- management scenario is used. If bit D0 is reset to 0, then the
- value of bit D1 is ignored. In this case, bit D1 is reset to zero
- for future compatibility.*/
- uint8_t bDataInterface; /* Interface number of Data Class interface optionally used for call management */
- /* Interface number:
- Zero based index of the interface in this configuration */
-}
-CDC_CallMgmtFuncDesc_TypeDef;
-
-typedef struct _AbstractCntrlMgmtFunctionalDescriptor {
- uint8_t bLength; /* Size of this functional descriptor, in bytes */
- uint8_t bDescriptorType; /* CS_INTERFACE(24h) */
- uint8_t bDescriptorSubType; /* Abstract Control Management functional descriptor subtype */
- uint8_t bmCapabilities; /* The capabilities that this configuration supports */
- /* capabilities:(A bit valueof zero means that the request is not supported)
- D7..D4: RESERVED (Reset to zero)
- D3: 1 - Device supports the notification
- Network_Connection.
- D2: 1 - Device supports the request Send_Break
- D1: 1 - Device supports the request combination of
- Set_Line_Coding, Set_Control_Line_State,
- Get_Line_Coding, and the notification
- Serial_State.
- D0: 1 - Device supports the request combination of
- Set_Comm_Feature, Clear_Comm_Feature, and
- Get_Comm_Feature.
- The previous bits, in combination, identify which
- requests/notifications are supported by a
- CommunicationsClass interface with the SubClass code of
- Abstract Control Model. */
-}
-CDC_AbstCntrlMgmtFuncDesc_TypeDef;
-
-typedef struct _UnionFunctionalDescriptor {
- uint8_t bLength; /* Size of this functional descriptor, in bytes */
- uint8_t bDescriptorType; /* CS_INTERFACE(24h) */
- uint8_t bDescriptorSubType; /* Union Functional Descriptor SubType */
- uint8_t bControlInterface; /* The interface number of the Communications
- or Data Class interface, designated as the
- controlling interface for the union.*/
- uint8_t bSubordinateInterface0; /* Interface number of first subordinate interfacein the union. */
- /* ... */
- /* uint8_t bSubordinateInterfaceN-1; */ /* Interface number of N-1 subordinate interfacein the union. */
-}
-CDC_UnionFuncDesc_TypeDef;
-
-typedef struct _USBH_CDCInterfaceDesc {
- CDC_HeaderFuncDesc_TypeDef CDC_HeaderFuncDesc;
- CDC_CallMgmtFuncDesc_TypeDef CDC_CallMgmtFuncDesc;
- CDC_AbstCntrlMgmtFuncDesc_TypeDef CDC_AbstCntrlMgmtFuncDesc;
- CDC_UnionFuncDesc_TypeDef CDC_UnionFuncDesc;
-}
-CDC_InterfaceDesc_Typedef;
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#define CDC_SET_LINE_CODING (0x20U)
-#define CDC_GET_LINE_CODING (0x21U)
-#define CDC_SET_CONTROL_LINE_STATE (0x22U)
-
-#define CDC_ACTIVATE_CARRIER_SIGNAL_RTS (0x0002U)
-#define CDC_DEACTIVATE_CARRIER_SIGNAL_RTS (0x0000U)
-#define CDC_ACTIVATE_SIGNAL_DTR (0x0001U)
-#define CDC_DEACTIVATE_SIGNAL_DTR (0x0000U)
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-extern CDC_LineCodingTypeDef CDC_SetLineCode;
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-HOST_STATUS usb_host_cdc_getlinecoding(usb_core_instance *pdev, USBH_HOST *phost);
-HOST_STATUS usb_host_cdc_setlinecoding(usb_core_instance *pdev, USBH_HOST *phost);
-HOST_STATUS usb_host_cdc_setcontrollinestate(usb_core_instance *pdev, USBH_HOST *phost);
-void usb_host_cdc_issue_setlinecoding(usb_core_instance *pdev, USBH_HOST *phost);
-void usb_host_cdc_issue_getlinecoding(usb_core_instance *pdev, USBH_HOST *phost);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_HOST_CDC_CTRL_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_class.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_class.c
deleted file mode 100644
index 1499ca22cd..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_class.c
+++ /dev/null
@@ -1,434 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_hid_class.c
- * @brief The HID Layer Handlers for USB Host HID class.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2022-06-30 CDT Modify for MISRAC
- Modify for variable alignment
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_hid_class.h"
-#include "usb_host_hid_mouseapp.h"
-#include "usb_host_hid_keyboardapp.h"
-#include "usb_host_driver.h"
-#include "usb_host_cfgch.h"
-#include "usb_host_ctrltrans.h"
-#include "usb_host_stdreq.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CLASS LL USB Host Class
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_HID USB Host HID
- * @{
- */
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-HOST_STATUS usb_host_hid_itfinit(usb_core_instance *pdev, void *phost);
-void usb_host_hid_itfdeinit(usb_core_instance *pdev);
-void usb_host_parse_hiddesc(USB_HOST_HIDDesc_TypeDef *desc, uint8_t *buf);
-HOST_STATUS usb_host_hid_process(usb_core_instance *pdev, void *phost);
-HOST_STATUS usb_host_hid_classreq(usb_core_instance *pdev, void *phost);
-HOST_STATUS usb_host_get_hidreportdesc(usb_core_instance *pdev, USBH_HOST *phost, uint16_t length);
-HOST_STATUS usb_host_get_hiddesc(usb_core_instance *pdev, USBH_HOST *phost, uint16_t length);
-HOST_STATUS usb_host_set_hididle(usb_core_instance *pdev,
- USBH_HOST *phost,
- uint8_t duration,
- uint8_t reportId);
-HOST_STATUS usb_host_set_hidprotocol(usb_core_instance *pdev, USBH_HOST *phost, uint8_t protocol);
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-usb_host_class_callback_func USBH_HID_cb = {
- usb_host_hid_itfinit,
- usb_host_hid_itfdeinit,
- usb_host_hid_classreq,
- usb_host_hid_process
-};
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-
-__USB_ALIGN_BEGIN static HID_Machine_TypeDef HID_Machine;
-__USB_ALIGN_BEGIN static USB_HOST_HIDDesc_TypeDef HID_Desc;
-
-__IO static uint8_t start_toggle = 0U;
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @brief initialize the hid class
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval status defination by HOST_STATUS
- */
-HOST_STATUS usb_host_hid_itfinit(usb_core_instance *pdev, void *phost)
-{
- uint8_t maxEP;
- USBH_HOST *pphost = phost;
-
- uint8_t epnum;
- HOST_STATUS status = HSTATUS_BUSY ;
- HID_Machine.state = HID_ERROR;
-
- if (pphost->device_prop.devitfdesc[0].bInterfaceSubClass == HID_BOOT_CODE) {
- switch (pphost->device_prop.devitfdesc[0].bInterfaceProtocol) {
- case HID_MOUSE_BOOT_CODE:
- HID_Machine.cb = &HID_MOUSE_cb;
- break;
- case HID_KEYBRD_BOOT_CODE:
- HID_Machine.cb = &HID_KEYBRD_cb;
- break;
- default:
- break;
- }
- HID_Machine.state = HID_IDLE;
- HID_Machine.ctl_state = HID_REQ_IDLE;
- HID_Machine.ep_addr = pphost->device_prop.devepdesc[0][0].bEndpointAddress;
- HID_Machine.length = pphost->device_prop.devepdesc[0][0].wMaxPacketSize;
- HID_Machine.poll = pphost->device_prop.devepdesc[0][0].bInterval ;
-
- if (HID_Machine.poll < HID_MIN_POLL) {
- HID_Machine.poll = HID_MIN_POLL;
- }
-
- /* Check fo available number of endpoints */
- /* Find the number of EPs in the Interface Descriptor */
- /* Choose the lower number in order not to overrun the buffer allocated */
- maxEP = ((pphost->device_prop.devitfdesc[0].bNumEndpoints <= USBH_MAX_NUM_ENDPOINTS) ?
- pphost->device_prop.devitfdesc[0].bNumEndpoints :
- USBH_MAX_NUM_ENDPOINTS);
-
- /* Decode endpoint IN and OUT address from interface descriptor */
- for (epnum = 0U; epnum < maxEP; epnum++) {
- if (0U != (pphost->device_prop.devepdesc[0][epnum].bEndpointAddress & 0x80U)) {
- HID_Machine.HIDIntInEp = (pphost->device_prop.devepdesc[0][epnum].bEndpointAddress);
- HID_Machine.hc_num_in = usb_host_distrch(pdev,
- pphost->device_prop.devepdesc[0][epnum].bEndpointAddress);
- usb_host_chopen(pdev,
- HID_Machine.hc_num_in,
- pphost->device_prop.devaddr,
- pphost->device_prop.devspeed,
- EP_TYPE_INTR,
- HID_Machine.length);
- } else {
- HID_Machine.HIDIntOutEp = (pphost->device_prop.devepdesc[0][epnum].bEndpointAddress);
- HID_Machine.hc_num_out = usb_host_distrch(pdev,
- pphost->device_prop.devepdesc[0][epnum].bEndpointAddress);
- usb_host_chopen(pdev,
- HID_Machine.hc_num_out,
- pphost->device_prop.devaddr,
- pphost->device_prop.devspeed,
- EP_TYPE_INTR,
- HID_Machine.length);
- }
- }
- start_toggle = 0U;
- status = HSTATUS_OK;
- } else {
- pphost->user_callbk->huser_devunsupported();
- }
- return status;
-}
-
-/**
- * @brief deinitialize the channels for the hid class
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_host_hid_itfdeinit(usb_core_instance *pdev)
-{
- if (HID_Machine.hc_num_in != 0x00U) {
- usb_hchstop(&pdev->regs, HID_Machine.hc_num_in);
- (void)usb_host_freech(pdev, HID_Machine.hc_num_in);
- HID_Machine.hc_num_in = 0U;
- }
-
- if (HID_Machine.hc_num_out != 0x00U) {
- usb_hchstop(&pdev->regs, HID_Machine.hc_num_out);
- (void)usb_host_freech(pdev, HID_Machine.hc_num_out);
- HID_Machine.hc_num_out = 0U;
- }
- start_toggle = 0U;
-}
-
-/**
- * @brief This function is responsible for handling requests about HID class.
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval status defined by HOST_STATUS
- */
-HOST_STATUS usb_host_hid_classreq(usb_core_instance *pdev, void *phost)
-{
- HOST_STATUS status;
- HOST_STATUS classReqStatus;
- USBH_HOST *pphost = phost;
- status = HSTATUS_BUSY;
- switch (HID_Machine.ctl_state) {
- case HID_IDLE:
- case HID_REQ_GET_HID_DESC:
- if (usb_host_get_hiddesc(pdev, pphost, USB_HID_DESC_SIZE) == HSTATUS_OK) {
- usb_host_parse_hiddesc(&HID_Desc, pdev->host.Rx_Buffer);
- HID_Machine.ctl_state = HID_REQ_GET_REPORT_DESC;
- }
- break;
- case HID_REQ_GET_REPORT_DESC:
- if (usb_host_get_hidreportdesc(pdev, pphost, HID_Desc.wItemLength) == HSTATUS_OK) {
- HID_Machine.ctl_state = HID_REQ_SET_IDLE;
- }
- break;
- case HID_REQ_SET_IDLE:
- classReqStatus = usb_host_set_hididle(pdev, pphost, 0U, 0U);
- if (classReqStatus == HSTATUS_OK) {
- HID_Machine.ctl_state = HID_REQ_SET_PROTOCOL;
- } else if (classReqStatus == HSTATUS_UNSUPPORTED) {
- HID_Machine.ctl_state = HID_REQ_SET_PROTOCOL;
- } else {
- /*reserved*/
- }
- break;
- case HID_REQ_SET_PROTOCOL:
- if (usb_host_set_hidprotocol(pdev, pphost, 0U) == HSTATUS_OK) {
- HID_Machine.ctl_state = HID_REQ_IDLE;
- status = HSTATUS_OK;
- }
- break;
- default:
- break;
- }
- return status;
-}
-
-/**
- * @brief This function is to process the state machine for HID data transmitting
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval status defined by HOST_STATUS
- */
-HOST_STATUS usb_host_hid_process(usb_core_instance *pdev, void *phost)
-{
- HOST_STATUS status;
- USBH_HOST *pphost = phost;
- status = HSTATUS_OK;
- switch (HID_Machine.state) {
- case HID_IDLE:
- HID_Machine.cb->Init();
- HID_Machine.state = HID_SYNC;
- case HID_SYNC:
- if (usb_ifevenframe(&pdev->regs) == TRUE) {
- HID_Machine.state = HID_GET_DATA;
- }
- break;
- case HID_GET_DATA:
- usb_host_recvintdata(pdev,
- HID_Machine.buff,
- HID_Machine.length,
- HID_Machine.hc_num_in);
- start_toggle = 1U;
- HID_Machine.state = HID_POLL;
- HID_Machine.timer = (uint16_t)host_driver_getcurrentfrm(pdev);
- break;
- case HID_POLL:
- if ((host_driver_getcurrentfrm(pdev) - HID_Machine.timer) >= HID_Machine.poll) {
- HID_Machine.state = HID_GET_DATA;
- } else if (host_driver_getxferstate(pdev, HID_Machine.hc_num_in) == HOST_CH_XFER_DONE) {
- if (start_toggle == 1U) {
- start_toggle = 0U;
- HID_Machine.cb->Decode(HID_Machine.buff);
- }
- } else if (host_driver_getxferstate(pdev, HID_Machine.hc_num_in) == HOST_CH_XFER_STALL) {
- /* Issue Clear Feature on interrupt IN endpoint */
- if ((usb_host_clrfeature(pdev,
- pphost,
- HID_Machine.ep_addr,
- HID_Machine.hc_num_in)) == HSTATUS_OK) {
- HID_Machine.state = HID_GET_DATA;
- }
- } else {
- /*reserved*/
- }
- break;
- default:
- break;
- }
- return status;
-}
-
-/**
- * @brief Issue hid report descriptor command to the device, parse the report
- * descriptor and update the status once the response received.
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @param [in] length the length of the hid descriptor in bytes
- * @retval status defined by HOST_STATUS
- */
-HOST_STATUS usb_host_get_hidreportdesc(usb_core_instance *pdev, USBH_HOST *phost, uint16_t length)
-{
- HOST_STATUS status;
- status = usb_host_getdesc(pdev,
- phost,
- USB_REQ_RECIPIENT_INTERFACE | USB_REQ_TYPE_STANDARD,
- USB_DESC_HID_REPORT,
- pdev->host.Rx_Buffer,
- length);
- return status;
-}
-
-/**
- * @brief Issue HID descriptor command to the device, parse the descriptor
- * and update the status once the response received.
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @param [in] length length of HID descriptor in bytes
- * @retval status defined by HOST_STATUS
- */
-HOST_STATUS usb_host_get_hiddesc(usb_core_instance *pdev, USBH_HOST *phost, uint16_t length)
-{
- HOST_STATUS status;
- status = usb_host_getdesc(pdev,
- phost,
- USB_REQ_RECIPIENT_INTERFACE
- | USB_REQ_TYPE_STANDARD,
- USB_DESC_HID,
- pdev->host.Rx_Buffer,
- length);
- return status;
-}
-
-/**
- * @brief Set hid application to be idle status.
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @param [in] duration Duration for HID Idle request
- * @param [in] reportId Targetted report ID for Set Idle request
- * @retval status defined by HOST_STATUS
- */
-HOST_STATUS usb_host_set_hididle(usb_core_instance *pdev,
- USBH_HOST *phost,
- uint8_t duration,
- uint8_t reportId)
-{
- phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE | USB_REQ_TYPE_CLASS;
-
- phost->ctrlparam.setup.b.bRequest = USB_HID_SET_IDLE;
- phost->ctrlparam.setup.b.wValue.w = ((uint16_t)duration << 8) | (uint16_t)reportId;
-
- phost->ctrlparam.setup.b.wIndex.w = 0U;
- phost->ctrlparam.setup.b.wLength.w = 0U;
-
- return usb_host_ctrlreq(pdev, phost, NULL, 0U);
-}
-
-/**
- * @brief Issues a command to set report
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @param [in] reportType the report type to be sent
- * @param [in] reportId target report ID for set report request
- * @param [in] reportLen length of data of report to be sent in bytes
- * @param [in] reportBuff report buffer
- * @retval status defined by HOST_STATUS
- */
-HOST_STATUS usb_host_set_hidreport(usb_core_instance *pdev,
- USBH_HOST *phost,
- uint8_t reportType,
- uint8_t reportId,
- uint8_t reportLen,
- uint8_t *reportBuff)
-{
- phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE | USB_REQ_TYPE_CLASS;
- phost->ctrlparam.setup.b.bRequest = USB_HID_SET_REPORT;
- phost->ctrlparam.setup.b.wValue.w = ((uint16_t)reportType << 8) | (uint16_t)reportId;
- phost->ctrlparam.setup.b.wIndex.w = 0U;
- phost->ctrlparam.setup.b.wLength.w = reportLen;
- return usb_host_ctrlreq(pdev, phost, reportBuff, reportLen);
-}
-
-/**
- * @brief Set protocol state of the hid application.
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @param [in] protocol protocol for HID application
- * @retval status defined by HOST_STATUS
- */
-HOST_STATUS usb_host_set_hidprotocol(usb_core_instance *pdev, USBH_HOST *phost, uint8_t protocol)
-{
- phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE | USB_REQ_TYPE_CLASS;
- phost->ctrlparam.setup.b.bRequest = USB_HID_SET_PROTOCOL;
- if (protocol != 0U) {
- /* Boot Protocol */
- phost->ctrlparam.setup.b.wValue.w = 0U;
- } else {
- /* Report Protocol */
- phost->ctrlparam.setup.b.wValue.w = 1U;
- }
- phost->ctrlparam.setup.b.wIndex.w = 0U;
- phost->ctrlparam.setup.b.wLength.w = 0U;
- return usb_host_ctrlreq(pdev, phost, NULL, 0U);
-}
-
-/**
- * @brief parse the HID descriptor
- * @param [in] desc used to get the fields parsed from the data buffer
- * @param [in] buf Buffer where the source descriptor is available
- * @retval None
- */
-void usb_host_parse_hiddesc(USB_HOST_HIDDesc_TypeDef *desc, uint8_t *buf)
-{
- desc->bLength = buf[0];
- desc->bDescriptorType = buf[1];
- desc->bcdHID = SMALL_END(&buf[2]);
- desc->bCountryCode = buf[4];
- desc->bNumDescriptors = buf[5];
- desc->bReportDescriptorType = buf[6];
- desc->wItemLength = SMALL_END(&buf[7]);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************************************************************************
- * EOF (not truncated)
- *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_class.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_class.h
deleted file mode 100644
index a87687acf6..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_class.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_hid_class.h
- * @brief header file for the usb_host_hid_class.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_HOST_HID_CLASS_H__
-#define __USB_HOST_HID_CLASS_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_def.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_HID
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-
-/* States for HID State Machine */
-typedef enum {
- HID_IDLE = 0,
- HID_SEND_DATA,
- HID_BUSY,
- HID_GET_DATA,
- HID_SYNC,
- HID_POLL,
- HID_ERROR,
-}
-HID_State;
-
-typedef enum {
- HID_REQ_IDLE = 0,
- HID_REQ_GET_REPORT_DESC,
- HID_REQ_GET_HID_DESC,
- HID_REQ_SET_IDLE,
- HID_REQ_SET_PROTOCOL,
- HID_REQ_SET_REPORT,
-
-}
-HID_CtlState;
-
-typedef struct {
- void (*Init)(void);
- void (*Decode)(uint8_t *data);
-
-} HID_cb_TypeDef;
-
-typedef struct {
- uint8_t ReportID;
- uint8_t ReportType;
- uint16_t UsagePage;
- uint32_t Usage[2];
- uint32_t NbrUsage;
- uint32_t UsageMin;
- uint32_t UsageMax;
- int32_t LogMin;
- int32_t LogMax;
- int32_t PhyMin;
- int32_t PhyMax;
- int32_t UnitExp;
- uint32_t Unit;
- uint32_t ReportSize;
- uint32_t ReportCnt;
- uint32_t Flag;
- uint32_t PhyUsage;
- uint32_t AppUsage;
- uint32_t LogUsage;
-} HID_Report_TypeDef;
-
-/* Structure for HID process */
-typedef struct {
- uint8_t buff[64];
- uint8_t hc_num_in;
- uint8_t hc_num_out;
- HID_State state;
- uint8_t HIDIntOutEp;
- uint8_t HIDIntInEp;
- HID_CtlState ctl_state;
- uint16_t length;
- uint8_t ep_addr;
- uint16_t poll;
- __IO uint16_t timer;
- HID_cb_TypeDef *cb;
-} HID_Machine_TypeDef;
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#define USB_HID_REQ_GET_REPORT (0x01)
-#define USB_HID_GET_IDLE (0x02)
-#define USB_HID_GET_PROTOCOL (0x03)
-#define USB_HID_SET_REPORT (0x09)
-#define USB_HID_SET_IDLE (0x0A)
-#define USB_HID_SET_PROTOCOL (0x0B)
-
-#define HID_MIN_POLL (10U)
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-extern usb_host_class_callback_func USBH_HID_cb;
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-extern HOST_STATUS usb_host_set_hidreport(usb_core_instance *pdev,
- USBH_HOST *phost,
- uint8_t reportType,
- uint8_t reportId,
- uint8_t reportLen,
- uint8_t *reportBuff);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_HOST_HID_CLASS_H__ */
-
-/******************************************************************************
- * EOF (not truncated)
- *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.c
deleted file mode 100644
index 33cffddb9b..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_hid_keyboardapp.c
- * @brief The application layer for USB Host HID Keyboard handling
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2023-06-30 CDT Modify for variable alignment
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_hid_keyboardapp.h"
-#include "usb_host_user.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_HID
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-void keyboard_init(void);
-void keyboard_decode(uint8_t *pbuf);
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-HID_cb_TypeDef HID_KEYBRD_cb = {
- keyboard_init,
- keyboard_decode
-};
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-__USB_ALIGN_BEGIN static const uint8_t HID_KEYBRD_Codes[] = {
- 0, 0, 0, 0, 31, 50, 48, 33,
- 19, 34, 35, 36, 24, 37, 38, 39, /* 0x00 - 0x0F */
- 52, 51, 25, 26, 17, 20, 32, 21,
- 23, 49, 18, 47, 22, 46, 2, 3, /* 0x10 - 0x1F */
- 4, 5, 6, 7, 8, 9, 10, 11,
- 43, 110, 15, 16, 61, 12, 13, 27, /* 0x20 - 0x2F */
- 28, 29, 42, 40, 41, 1, 53, 54,
- 55, 30, 112, 113, 114, 115, 116, 117, /* 0x30 - 0x3F */
- 118, 119, 120, 121, 122, 123, 124, 125,
- 126, 75, 80, 85, 76, 81, 86, 89, /* 0x40 - 0x4F */
- 79, 84, 83, 90, 95, 100, 105, 106,
- 108, 93, 98, 103, 92, 97, 102, 91, /* 0x50 - 0x5F */
- 96, 101, 99, 104, 45, 129, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, /* 0x60 - 0x6F */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, /* 0x70 - 0x7F */
- 0, 0, 0, 0, 0, 107, 0, 56,
- 0, 0, 0, 0, 0, 0, 0, 0, /* 0x80 - 0x8F */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, /* 0x90 - 0x9F */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, /* 0xA0 - 0xAF */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, /* 0xB0 - 0xBF */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, /* 0xC0 - 0xCF */
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, /* 0xD0 - 0xDF */
- 58, 44, 60, 127, 64, 57, 62, 128 /* 0xE0 - 0xE7 */
-};
-
-#ifdef QWERTY_KEYBOARD
-__USB_ALIGN_BEGIN static const uint8_t HID_KEYBRD_Key[] = {
- '\0', '`', '1', '2', '3', '4', '5', '6',
- '7', '8', '9', '0', '-', '=', '\0', '\r',
- '\t', 'q', 'w', 'e', 'r', 't', 'y', 'u',
- 'i', 'o', 'p', '[', ']', '\\',
- '\0', 'a', 's', 'd', 'f', 'g', 'h', 'j',
- 'k', 'l', ';', '\'', '\0', '\n',
- '\0', '\0', 'z', 'x', 'c', 'v', 'b', 'n',
- 'm', ',', '.', '/', '\0', '\0',
- '\0', '\0', '\0', ' ', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '7', '4', '1',
- '\0', '/', '8', '5', '2',
- '0', '*', '9', '6', '3',
- '.', '-', '+', '\0', '\n', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0'
-};
-
-__USB_ALIGN_BEGIN static const uint8_t HID_KEYBRD_ShiftKey[] = {
- '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')',
- '_', '+', '\0', '\0', '\0', 'Q', 'W', 'E', 'R', 'T', 'Y', 'U',
- 'I', 'O', 'P', '{', '}', '|', '\0', 'A', 'S', 'D', 'F', 'G',
- 'H', 'J', 'K', 'L', ':', '"', '\0', '\n', '\0', '\0', 'Z', 'X',
- 'C', 'V', 'B', 'N', 'M', '<', '>', '?', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0'
-};
-
-#else
-
-__USB_ALIGN_BEGIN static const uint8_t HID_KEYBRD_Key[] = {
- '\0', '`', '1', '2', '3', '4', '5', '6', '7', '8', '9', '0',
- '-', '=', '\0', '\r', '\t', 'a', 'z', 'e', 'r', 't', 'y', 'u',
- 'i', 'o', 'p', '[', ']', '\\', '\0', 'q', 's', 'd', 'f', 'g',
- 'h', 'j', 'k', 'l', 'm', '\0', '\0', '\n', '\0', '\0', 'w', 'x',
- 'c', 'v', 'b', 'n', ',', ';', ':', '!', '\0', '\0', '\0', '\0',
- '\0', ' ', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '7', '4', '1', '\0', '/',
- '8', '5', '2', '0', '*', '9', '6', '3', '.', '-', '+', '\0',
- '\n', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0'
-};
-
-__USB_ALIGN_BEGIN static const uint8_t HID_KEYBRD_ShiftKey[] = {
- '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_',
- '+', '\0', '\0', '\0', 'A', 'Z', 'E', 'R', 'T', 'Y', 'U', 'I', 'O',
- 'P', '{', '}', '*', '\0', 'Q', 'S', 'D', 'F', 'G', 'H', 'J', 'K',
- 'L', 'M', '%', '\0', '\n', '\0', '\0', 'W', 'X', 'C', 'V', 'B', 'N',
- '?', '.', '/', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0',
- '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0'
-};
-#endif
-
-/**
- * @brief Initialize the keyboard function.
- * @param None
- * @retval None
- */
-void keyboard_init(void)
-{
- user_keyboard_init();
-}
-
-/**
- * @brief The function is to decode the pressed keys when receives key value.
- * @param [in] pbuf buffer contain the HID IN report data.
- * @retval None
- */
-void keyboard_decode(uint8_t *pbuf)
-{
- static uint8_t shift;
- static uint8_t keys[KBR_MAX_NBR_PRESSED];
- static uint8_t keys_new[KBR_MAX_NBR_PRESSED];
- static uint8_t keys_last[KBR_MAX_NBR_PRESSED];
- static uint8_t key_newest;
- static uint8_t nbr_keys;
- static uint8_t nbr_keys_new;
- static uint8_t nbr_keys_last;
- uint8_t ix;
- uint8_t jx;
- uint8_t error;
- uint8_t output;
-
- nbr_keys = 0U;
- nbr_keys_new = 0U;
- nbr_keys_last = 0U;
- key_newest = 0U;
-
- /* Check if Shift key is pressed */
- if ((pbuf[0] == KBD_LEFT_SHIFT) || (pbuf[0] == KBD_RIGHT_SHIFT)) {
- shift = TRUE;
- } else {
- shift = FALSE;
- }
-
- error = FALSE;
- /* Check for the value of pressed key */
- for (ix = 2U; ix < 2U + KBR_MAX_NBR_PRESSED; ix++) {
- if ((pbuf[ix] == 0x01U) || (pbuf[ix] == 0x02U) || (pbuf[ix] == 0x03U)) {
- error = TRUE;
- }
- }
- if (error == TRUE) {
- return;
- }
- nbr_keys = 0U;
- nbr_keys_new = 0U;
- for (ix = 2U; ix < 2U + KBR_MAX_NBR_PRESSED; ix++) {
- if (pbuf[ix] != 0U) {
- keys[nbr_keys] = pbuf[ix];
- nbr_keys++;
- for (jx = 0U; jx < nbr_keys_last; jx++) {
- if (pbuf[ix] == keys_last[jx]) {
- break;
- }
- }
- if (jx == nbr_keys_last) {
- keys_new[nbr_keys_new] = pbuf[ix];
- nbr_keys_new++;
- }
- }
- }
- if (nbr_keys_new == 1U) {
- key_newest = keys_new[0];
-
- if (shift == TRUE) {
- output = HID_KEYBRD_ShiftKey[HID_KEYBRD_Codes[key_newest]];
- } else {
- output = HID_KEYBRD_Key[HID_KEYBRD_Codes[key_newest]];
- }
- /* call user process handle */
- user_keyboard_dataprocess(output);
- } else {
- key_newest = 0x00U;
- }
- nbr_keys_last = nbr_keys;
- for (ix = 0U; ix < KBR_MAX_NBR_PRESSED; ix++) {
- keys_last[ix] = keys[ix];
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.h
deleted file mode 100644
index ca45cc2054..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_hid_keyboardapp.h
- * @brief Head file for usb_host_hid_keyboardapp.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_HOST_HID_KEYBOARDAPP_H__
-#define __USB_HOST_HID_KEYBOARDAPP_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_hid_class.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_HID
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#define QWERTY_KEYBOARD
-/* #define AZERTY_KEYBOARD */
-
-#define KBD_LEFT_CTRL (0x01U)
-#define KBD_LEFT_SHIFT (0x02U)
-#define KBD_LEFT_ALT (0x04U)
-#define KBD_LEFT_GUI (0x08U)
-#define KBD_RIGHT_CTRL (0x10U)
-#define KBD_RIGHT_SHIFT (0x20U)
-#define KBD_RIGHT_ALT (0x40U)
-#define KBD_RIGHT_GUI (0x80U)
-
-#define KBR_MAX_NBR_PRESSED (6U)
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-extern HID_cb_TypeDef HID_KEYBRD_cb;
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_HOST_HID_KEYBOARDAPP_H__ */
-
-/******************************************************************************
- * EOF (not truncated)
- *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_mouseapp.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_mouseapp.c
deleted file mode 100644
index 94698785f0..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_mouseapp.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_hid_mouseapp.c
- * @brief The application layer for USB Host HID Mouse Handling.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2023-06-30 CDT Modify for variable alignment
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_hid_mouseapp.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_HID
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-void mouse_init(void);
-void mouse_decode(uint8_t *data);
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-HID_MOUSE_Data_TypeDef HID_MOUSE_Data;
-HID_cb_TypeDef HID_MOUSE_cb = {
- mouse_init,
- mouse_decode,
-};
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @brief initialize the mouse application of the hid class
- * @param None
- * @retval None
- */
-void mouse_init(void)
-{
- /* Call User Init*/
- user_mouse_init();
-}
-
-/**
- * @brief decode the mouse report data
- * @param [in] data buffer of the hid report data
- * @retval None
- */
-void mouse_decode(uint8_t *data)
-{
- HID_MOUSE_Data.button = data[0];
- HID_MOUSE_Data.x = data[1];
- HID_MOUSE_Data.y = data[2];
- user_mouse_dataprocess(&HID_MOUSE_Data);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_mouseapp.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_mouseapp.h
deleted file mode 100644
index 4402376b99..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_mouseapp.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_hid_mouseapp.h
- * @brief Head file for usb_host_hid_mouseapp.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_HOST_HID_MOUSEAPP_H__
-#define __USB_HOST_HID_MOUSEAPP_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_hid_class.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_HID
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-typedef struct _HID_MOUSE_Data {
- uint8_t z;
- uint8_t button;
- uint8_t x; /* Not Supported */
- uint8_t y;
-}
-HID_MOUSE_Data_TypeDef;
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-extern HID_cb_TypeDef HID_MOUSE_cb;
-extern HID_MOUSE_Data_TypeDef HID_MOUSE_Data;
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-void user_mouse_init(void);
-void user_mouse_dataprocess(HID_MOUSE_Data_TypeDef *data);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_HOST_HID_MOUSEAPP_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.c
deleted file mode 100644
index 082f942c9b..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.c
+++ /dev/null
@@ -1,466 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_msc_bot.c
- * @brief mass storage related functions
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2022-06-30 CDT Add bot xfer error processing
- Modify for variable alignment
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_msc_class.h"
-#include "usb_host_msc_scsi.h"
-#include "usb_host_msc_bot.h"
-#include "usb_host_ctrltrans.h"
-#include "usb_host_def.h"
-#include "usb_host_int.h"
-#include "usb_host_driver.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_MSC USB Host MSC
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-__USB_ALIGN_BEGIN HOST_CSW_PACKET_TypeDef USBH_MSC_CSWData;
-
-__USB_ALIGN_BEGIN USB_HOST_BOTXFER_TypeDef USBH_MSC_BOTXferParam;
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-__USB_ALIGN_BEGIN HostCBWPkt_TypeDef USBH_MSC_CBWData;
-
-static uint32_t BOTStallErrorCount; /* Keeps count of STALL Error Cases*/
-static uint8_t u8BotXferErrorCount;
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @brief initializes original state of the mass storage parameters
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_host_msc_init(usb_core_instance *pdev)
-{
- if (host_driver_ifdevconnected(pdev) != 0UL) {
- USBH_MSC_CBWData.field.CBWSignature = HOST_MSC_BOT_CBW_SIGNATURE;
- USBH_MSC_CBWData.field.CBWTag = HOST_MSC_BOT_CBW_TAG;
- USBH_MSC_CBWData.field.CBWLUN = 0U;
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND;
- }
- BOTStallErrorCount = 0UL;
- MSCErrorCount = 0U;
-}
-
-/**
- * @brief manages the different states of BOT transfer and updates the
- * status for the upper layer.
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval None
- */
-void usb_host_msc_botxferprocess(usb_core_instance *pdev, USBH_HOST *phost)
-{
- uint8_t xferDirection, index;
- static uint32_t remainingDataLength;
- static uint8_t *datapointer, *datapointer_prev;
- static uint8_t error_direction;
- HOST_STATUS status;
-
- HOST_CH_XFER_STATE URB_Status;
-
- if (host_driver_ifdevconnected(pdev) != 0UL) {
-
- switch (USBH_MSC_BOTXferParam.BOTState) {
- case HOST_MSC_SEND_CBW:
- /* send a CBW */
- usb_host_sendbulkdata(pdev,
- &USBH_MSC_CBWData.CBWArray[0],
- HOST_MSC_BOT_CBW_PACKET_LENGTH,
- MSC_Machine.hc_num_out);
- USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_SEND_CBW;
- USBH_MSC_BOTXferParam.BOTState = HOST_MSC_SENT_CBW;
- u8BotXferErrorCount = 0U;
- break;
- case HOST_MSC_SENT_CBW:
- URB_Status = host_driver_getxferstate(pdev, MSC_Machine.hc_num_out);
- switch (URB_Status) {
- case HOST_CH_XFER_DONE:
- BOTStallErrorCount = 0U;
- USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_SENT_CBW;
- /* If the CBW packet is sent successful, then update the state */
- xferDirection = (USBH_MSC_CBWData.field.CBWFlags & USB_REQ_DIR_MASK);
- if (USBH_MSC_CBWData.field.CBWTransferLength != 0UL) {
- remainingDataLength = USBH_MSC_CBWData.field.CBWTransferLength ;
- datapointer = USBH_MSC_BOTXferParam.pRxTxBuff;
- datapointer_prev = datapointer;
- /* If there has data transfer stage, update the direction whether it is D2H or H2D */
- if (xferDirection == USB_D2H) {
- USBH_MSC_BOTXferParam.BOTState = HOST_MSC_BOT_DATAIN_STATE;
- } else {
- USBH_MSC_BOTXferParam.BOTState = HOST_MSC_BOT_DATAOUT_STATE;
- }
- } else {
- /* If there has not data transfer stage also update the state */
- USBH_MSC_BOTXferParam.BOTState = HOST_MSC_RECEIVE_CSW_STATE;
- }
- break;
- case HOST_CH_XFER_UNREADY:
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp;
- break;
- case HOST_CH_XFER_STALL:
- error_direction = HOST_MSC_DIR_OUT;
- USBH_MSC_BOTXferParam.BOTState = HOST_MSC_BOT_ERROR_OUT;
- break;
- case HOST_CH_XFER_ERROR:
- u8BotXferErrorCount++;
- if (u8BotXferErrorCount < 3U) {
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp;
- } else {
- USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_PHASE_ERROR;
- }
- break;
- default:
- break;
- }
- break;
-
- case HOST_MSC_BOT_DATAIN_STATE:
- URB_Status = host_driver_getxferstate(pdev, MSC_Machine.hc_num_in);
- if ((URB_Status == HOST_CH_XFER_DONE) \
- || (USBH_MSC_BOTXferParam.BOTStateBkp != HOST_MSC_BOT_DATAIN_STATE)) {
- BOTStallErrorCount = 0U;
- USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_BOT_DATAIN_STATE;
-
- if (remainingDataLength > MSC_Machine.MSC_BulkInEpSize) {
- usb_host_recvbulkdata(pdev,
- datapointer,
- MSC_Machine.MSC_BulkInEpSize,
- MSC_Machine.hc_num_in);
- remainingDataLength -= MSC_Machine.MSC_BulkInEpSize;
- datapointer = datapointer + MSC_Machine.MSC_BulkInEpSize;
- } else if (remainingDataLength == 0UL) {
- /* If value was 0, and successful transfer, then change the state */
- USBH_MSC_BOTXferParam.BOTState = HOST_MSC_RECEIVE_CSW_STATE;
- } else {
- usb_host_recvbulkdata(pdev,
- datapointer,
- (uint16_t)remainingDataLength,
- MSC_Machine.hc_num_in);
- remainingDataLength = 0UL;
- }
- } else if (URB_Status == HOST_CH_XFER_STALL) {
- error_direction = HOST_MSC_DIR_IN;
- USBH_MSC_BOTXferParam.BOTState = HOST_MSC_BOT_ERROR_IN;
- USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_RECEIVE_CSW_STATE;
- } else if (URB_Status == HOST_CH_XFER_ERROR) {
- error_direction = HOST_MSC_DIR_IN;
- USBH_MSC_BOTXferParam.BOTState = HOST_MSC_BOT_ERROR_IN;
- USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_RECEIVE_CSW_STATE;
- } else {
- ;
- }
- break;
- case HOST_MSC_BOT_DATAOUT_STATE:
- URB_Status = host_driver_getxferstate(pdev, MSC_Machine.hc_num_out);
- if (URB_Status == HOST_CH_XFER_DONE) {
- BOTStallErrorCount = 0UL;
- USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_BOT_DATAOUT_STATE;
- if (remainingDataLength > MSC_Machine.MSC_BulkOutEpSize) {
- usb_host_sendbulkdata(pdev,
- datapointer,
- MSC_Machine.MSC_BulkOutEpSize,
- MSC_Machine.hc_num_out);
- datapointer_prev = datapointer;
- datapointer = datapointer + MSC_Machine.MSC_BulkOutEpSize;
-
- remainingDataLength = remainingDataLength - MSC_Machine.MSC_BulkOutEpSize;
- } else if (remainingDataLength == 0UL) {
- USBH_MSC_BOTXferParam.BOTState = HOST_MSC_RECEIVE_CSW_STATE;
- } else {
- usb_host_sendbulkdata(pdev,
- datapointer,
- (uint16_t)remainingDataLength,
- MSC_Machine.hc_num_out);
- remainingDataLength = 0UL;
- }
- } else if (URB_Status == HOST_CH_XFER_UNREADY) {
- if (datapointer != datapointer_prev) {
- usb_host_sendbulkdata(pdev,
- (datapointer - MSC_Machine.MSC_BulkOutEpSize),
- MSC_Machine.MSC_BulkOutEpSize,
- MSC_Machine.hc_num_out);
- } else {
- usb_host_sendbulkdata(pdev,
- datapointer,
- MSC_Machine.MSC_BulkOutEpSize,
- MSC_Machine.hc_num_out);
- }
- } else if (URB_Status == HOST_CH_XFER_STALL) {
- error_direction = HOST_MSC_DIR_OUT;
- USBH_MSC_BOTXferParam.BOTState = HOST_MSC_BOT_ERROR_OUT;
- USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_RECEIVE_CSW_STATE;
- } else if (URB_Status == HOST_CH_XFER_ERROR) {
- error_direction = HOST_MSC_DIR_OUT;
- USBH_MSC_BOTXferParam.BOTState = HOST_MSC_BOT_ERROR_OUT;
- USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_RECEIVE_CSW_STATE;
- } else {
- ;
- }
- break;
-
- case HOST_MSC_RECEIVE_CSW_STATE:
- USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_RECEIVE_CSW_STATE;
- USBH_MSC_BOTXferParam.pRxTxBuff = USBH_MSC_CSWData.CSWArray;
- USBH_MSC_BOTXferParam.DataLength = HOST_MSC_CSW_MAX_LENGTH;
- for (index = 0U; index < HOST_MSC_CSW_LENGTH; index++) {
- USBH_MSC_CSWData.CSWArray[index] = 0U;
- }
-
- USBH_MSC_CSWData.CSWArray[0] = 0U;
- usb_host_recvbulkdata(pdev,
- USBH_MSC_BOTXferParam.pRxTxBuff,
- HOST_MSC_CSW_MAX_LENGTH,
- MSC_Machine.hc_num_in);
- USBH_MSC_BOTXferParam.BOTState = HOST_MSC_DECODE_CSW;
- u8BotXferErrorCount = 0U;
- break;
-
- case HOST_MSC_DECODE_CSW:
- URB_Status = host_driver_getxferstate(pdev, MSC_Machine.hc_num_in);
- if (URB_Status == HOST_CH_XFER_DONE) {
- BOTStallErrorCount = 0UL;
- USBH_MSC_BOTXferParam.BOTStateBkp = HOST_MSC_RECEIVE_CSW_STATE;
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOTXferParam.MSCStateCurrent ;
- USBH_MSC_BOTXferParam.BOTXferStatus = usb_host_msc_cswdecode(pdev, phost);
- } else if (URB_Status == HOST_CH_XFER_STALL) {
- error_direction = HOST_MSC_DIR_IN;
- USBH_MSC_BOTXferParam.BOTState = HOST_MSC_BOT_ERROR_IN;
- } else if (URB_Status == HOST_CH_XFER_ERROR) {
- u8BotXferErrorCount++;
- if (u8BotXferErrorCount < 3U) {
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp;
- } else {
- USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_PHASE_ERROR;
- }
- } else {
- ;
- }
- break;
-
- case HOST_MSC_BOT_ERROR_IN:
- status = usb_host_msc_botabort(pdev, phost, HOST_MSC_DIR_IN);
- if (status == HSTATUS_OK) {
- if (error_direction == HOST_MSC_BOTH_DIR) {
- USBH_MSC_BOTXferParam.BOTState = HOST_MSC_BOT_ERROR_OUT;
- } else {
- /* switch back to the original state */
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp;
- }
- } else if (status == HSTATUS_UNRECOVERED_ERROR) {
- /* This means that there is a STALL Error limit, Do Reset Recovery */
- USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_PHASE_ERROR;
- } else {
- ;
- }
- break;
- case HOST_MSC_BOT_ERROR_OUT:
- status = usb_host_msc_botabort(pdev, phost, HOST_MSC_DIR_OUT);
- if (status == HSTATUS_OK) {
- /* switch back to the original state */
- USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp;
- } else if (status == HSTATUS_UNRECOVERED_ERROR) {
- /* This means that there is a STALL Error limit, Do Reset Recovery */
- USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_PHASE_ERROR;
- } else {
- ;
- }
- break;
-
- default:
- break;
- }
- }
-}
-
-/**
- * @brief manages the different Error handling for STALL
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @param [in] direction IN / OUT
- * @retval None
- */
-HOST_STATUS usb_host_msc_botabort(usb_core_instance *pdev, USBH_HOST *phost, uint8_t direction)
-{
- HOST_STATUS status;
-
- status = HSTATUS_BUSY;
-
- switch (direction) {
- case HOST_MSC_DIR_IN:
- /* send ClrFeture on Bulk IN endpoint */
- status = usb_host_clrfeature(pdev,
- phost,
- MSC_Machine.MSC_BulkInEp,
- MSC_Machine.hc_num_in);
- break;
- case HOST_MSC_DIR_OUT:
- /* send ClrFeature on Bulk OUT endpoint */
- status = usb_host_clrfeature(pdev,
- phost,
- MSC_Machine.MSC_BulkOutEp,
- MSC_Machine.hc_num_out);
- break;
- default:
- break;
- }
- BOTStallErrorCount++;
- if (BOTStallErrorCount > 4UL) {
- status = HSTATUS_UNRECOVERED_ERROR;
- }
- return status;
-}
-
-/**
- * @brief Decodes the CSW received by the device and updates the same to upper layer
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval On success USB_HOST_MSC_OK, on failure USB_HOST_MSC_FAIL
- */
-uint8_t usb_host_msc_cswdecode(usb_core_instance *pdev, USBH_HOST *phost)
-{
- USB_HOST_MSC_STATUS status;
- uint32_t dataXferCount;
- status = USB_HOST_MSC_FAIL;
-
- if (host_driver_ifdevconnected(pdev) != 0UL) {
- dataXferCount = host_driver_getxfercnt(pdev, MSC_Machine.hc_num_in);
- if (dataXferCount != HOST_MSC_CSW_LENGTH) {
- /*(4) Hi > Dn (Host expects to receive data from the device,
- Device intends to transfer no data)
- (5) Hi > Di (Host expects to receive data from the device,
- Device intends to send data to the host)
- (9) Ho > Dn (Host expects to send data to the device,
- Device intends to transfer no data)
- (11) Ho > Do (Host expects to send data to the device,
- Device intends to receive data from the host)*/
- status = USB_HOST_MSC_PHASE_ERROR;
- } else {
- /* CSW length is Correct */
-
- /* Check validity of the CSW Signature and CSWStatus */
- if (USBH_MSC_CSWData.field.dCSWSignature == HOST_MSC_BOT_CSW_SIGNATURE) {
- /* Check Condition 1. dCSWSignature is equal to 53425355h */
- if (USBH_MSC_CSWData.field.dCSWTag == USBH_MSC_CBWData.field.CBWTag) {
- /* Check Condition 3. dCSWTag matches the dCBWTag from the
- corresponding CBW */
- if (USBH_MSC_CSWData.field.dCSWStatus == (uint8_t)USB_HOST_MSC_OK) {
- /* Refer to USB Mass-Storage Class : BOT (www.usb.org)
-
- Hn Host expects no data transfers
- Hi Host expects to receive data from the device
- Ho Host expects to send data to the device
-
- Dn Device intends to transfer no data
- Di Device intends to send data to the host
- Do Device intends to receive data from the host
-
- Section 6.7
- (1) Hn = Dn (Host expects no data transfers,
- Device intends to transfer no data)
- (6) Hi = Di (Host expects to receive data from the device,
- Device intends to send data to the host)
- (12) Ho = Do (Host expects to send data to the device,
- Device intends to receive data from the host)
- */
- status = USB_HOST_MSC_OK;
- } else if (USBH_MSC_CSWData.field.dCSWStatus == (uint8_t)USB_HOST_MSC_FAIL) {
- status = USB_HOST_MSC_FAIL;
- } else if (USBH_MSC_CSWData.field.dCSWStatus == (uint8_t)USB_HOST_MSC_PHASE_ERROR) {
- /* Refer to USB Mass-Storage Class : BOT (www.usb.org)
- Section 6.7
- (2) Hn < Di ( Host expects no data transfers,
- Device intends to send data to the host)
- (3) Hn < Do ( Host expects no data transfers,
- Device intends to receive data from the host)
- (7) Hi < Di ( Host expects to receive data from the device,
- Device intends to send data to the host)
- (8) Hi <> Do ( Host expects to receive data from the device,
- Device intends to receive data from the host)
- (10) Ho <> Di (Host expects to send data to the device,
- Di Device intends to send data to the host)
- (13) Ho < Do (Host expects to send data to the device,
- Device intends to receive data from the host)
- */
- status = USB_HOST_MSC_PHASE_ERROR;
- } else {
- ;
- }
- }
- } else {
- status = USB_HOST_MSC_PHASE_ERROR;
- }
- }
- }
-
- USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)status;
- return (uint8_t)status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.h
deleted file mode 100644
index 510dde01b1..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_msc_bot.h
- * @brief Head file for usb_host_msc_bot.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_HOST_MSC_BOT_H__
-#define __USB_HOST_MSC_BOT_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_stdreq.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_MSC
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-typedef union _USBH_CBW_Block {
- struct __CBW {
- uint32_t CBWSignature;
- uint32_t CBWTag;
- uint32_t CBWTransferLength;
- uint8_t CBWFlags;
- uint8_t CBWLUN;
- uint8_t CBWLength;
- uint8_t CBWCB[16];
- } field;
- uint8_t CBWArray[31];
-} HostCBWPkt_TypeDef;
-
-typedef struct {
- uint8_t MSCState;
- uint8_t MSCStateBkp;
- uint8_t MSCStateCurrent;
- uint8_t CmdStateMachine;
- uint8_t BOTState;
- uint8_t BOTStateBkp;
- uint8_t *pRxTxBuff;
- uint16_t DataLength;
- uint8_t BOTXferStatus;
-} USB_HOST_BOTXFER_TypeDef;
-
-typedef union {
- struct {
- uint32_t dCSWSignature;
- uint32_t dCSWTag;
- uint32_t dCSWDataResidue;
- uint8_t dCSWStatus;
- } field;
- uint8_t CSWArray[13];
-} HOST_CSW_PACKET_TypeDef;
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#define HOST_MSC_BOT_INIT_STATE (0U)
-#define HOST_MSC_BOT_RESET (1U)
-#define HOST_MSC_GET_MAX_LUN (2U)
-#define HOST_MSC_TEST_UNIT_READY (3U)
-#define HOST_MSC_READ_CAPACITY10 (4U)
-#define HOST_MSC_MODE_SENSE6 (5U)
-#define HOST_MSC_REQUEST_SENSE (6U)
-#define HOST_MSC_BOT_USB_TRANSFERS (7U)
-#define HOST_MSC_DEFAULT_APPLI_STATE (8U)
-#define HOST_MSC_CTRL_ERROR_STATE (9U)
-#define HOST_MSC_UNRECOVERED_STATE (10U)
-
-#define HOST_MSC_SEND_CBW (1U)
-#define HOST_MSC_SENT_CBW (2U)
-#define HOST_MSC_BOT_DATAIN_STATE (3U)
-#define HOST_MSC_BOT_DATAOUT_STATE (4U)
-#define HOST_MSC_RECEIVE_CSW_STATE (5U)
-#define HOST_MSC_DECODE_CSW (6U)
-#define HOST_MSC_BOT_ERROR_IN (7U)
-#define HOST_MSC_BOT_ERROR_OUT (8U)
-
-#define HOST_MSC_BOT_CBW_SIGNATURE (0x43425355UL)
-#define HOST_MSC_BOT_CBW_TAG (0x20304050UL)
-#define HOST_MSC_BOT_CSW_SIGNATURE (0x53425355UL)
-#define HOST_MSC_CSW_DATA_LENGTH (13U)
-#define HOST_MSC_BOT_CBW_PACKET_LENGTH (31U)
-#define HOST_MSC_CSW_LENGTH (13U)
-#define HOST_MSC_CSW_MAX_LENGTH (63U)
-#define HOST_MSC_DIR_IN (0U)
-#define HOST_MSC_DIR_OUT (1U)
-#define HOST_MSC_BOTH_DIR (2U)
-#define HOST_MSC_PAGE_LENGTH (512UL)
-
-#define CBW_CB_LENGTH (16U)
-#define CBW_LENGTH (10U)
-#define CBW_LENGTH_TEST_UNIT_READY (6U)
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-extern USB_HOST_BOTXFER_TypeDef USBH_MSC_BOTXferParam;
-extern HostCBWPkt_TypeDef USBH_MSC_CBWData;
-extern HOST_CSW_PACKET_TypeDef USBH_MSC_CSWData;
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-extern void usb_host_msc_init(usb_core_instance *pdev);
-extern void usb_host_msc_botxferprocess(usb_core_instance *pdev, USBH_HOST *phost);
-extern uint8_t usb_host_msc_cswdecode(usb_core_instance *pdev, USBH_HOST *phost);
-extern HOST_STATUS usb_host_msc_botabort(usb_core_instance *pdev, USBH_HOST *phost, uint8_t direction);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_HOST_MSC_BOT_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.c
deleted file mode 100644
index 0f79e7ec9d..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.c
+++ /dev/null
@@ -1,377 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_msc_class.c
- * @brief The MSC class driver functions
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2022-06-30 CDT Remove msc bot reset operation
- Modify for variable alignment
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_msc_class.h"
-#include "usb_host_msc_scsi.h"
-#include "usb_host_msc_bot.h"
-#include "usb_host_core.h"
-#include "usb_host_driver.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_MSC
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#define USBH_MSC_ERROR_RETRY_LIMIT (10U)
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-HOST_STATUS usb_host_msc_itfinit(usb_core_instance *pdev, void *phost);
-void usb_host_msc_itfdeinit(usb_core_instance *pdev);
-HOST_STATUS usb_host_msc_process(usb_core_instance *pdev, void *phost);
-HOST_STATUS usb_host_msc_classreq(usb_core_instance *pdev, void *phost);
-
-HOST_STATUS usb_host_msc_bot_reset(usb_core_instance *pdev, USBH_HOST *phost);
-HOST_STATUS usb_host_msc_maxlun_get(usb_core_instance *pdev, USBH_HOST *phost);
-void usb_host_msc_error_process(USB_HOST_MSC_STATUS status);
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-__USB_ALIGN_BEGIN MSC_Machine_TypeDef MSC_Machine;
-uint8_t MSCErrorCount = 0U;
-
-usb_host_class_callback_func USBH_MSC_cb = {
- &usb_host_msc_itfinit,
- &usb_host_msc_itfdeinit,
- &usb_host_msc_classreq,
- &usb_host_msc_process,
-};
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-/**
- * @brief This request is used to issue a request to reset the msc device and
- * its related interface. This class-specific request shall prepare the
- * device for the next CBW from the host.
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval status define by HOST_STATUS
- */
-HOST_STATUS usb_host_msc_bot_reset(usb_core_instance *pdev, USBH_HOST *phost)
-{
- phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_TYPE_CLASS | \
- USB_REQ_RECIPIENT_INTERFACE;
- phost->ctrlparam.setup.b.bRequest = USB_REQ_BOT_RESET;
- phost->ctrlparam.setup.b.wValue.w = 0U;
- phost->ctrlparam.setup.b.wIndex.w = 0U;
- phost->ctrlparam.setup.b.wLength.w = 0U;
- return usb_host_ctrlreq(pdev, phost, NULL, 0U);
-}
-
-/**
- * @brief this request is used to issue a request to get the max logic unit of
- * the msc device.
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval status defined by HOST_STATUS
- */
-HOST_STATUS usb_host_msc_maxlun_get(usb_core_instance *pdev, USBH_HOST *phost)
-{
- phost->ctrlparam.setup.b.bmRequestType = USB_D2H | USB_REQ_TYPE_CLASS | \
- USB_REQ_RECIPIENT_INTERFACE;
-
- phost->ctrlparam.setup.b.bRequest = USB_REQ_GET_MAX_LUN;
- phost->ctrlparam.setup.b.wValue.w = 0U;
- phost->ctrlparam.setup.b.wIndex.w = 0U;
- phost->ctrlparam.setup.b.wLength.w = 1U;
- return usb_host_ctrlreq(pdev, phost, MSC_Machine.buff, 1U);
-}
-
-/**
- * @brief The function is used for handling errors during processing the MSC
- * state machine
- * @param [in] status
- * @retval None
- */
-void usb_host_msc_error_process(USB_HOST_MSC_STATUS status)
-{
- switch (status) {
- case USB_HOST_MSC_FAIL:
- MSCErrorCount++;
- if (MSCErrorCount < USBH_MSC_ERROR_RETRY_LIMIT) {
- /* Try MSC level error recovery, Issue the request Sense to get
- driver error reason */
- USBH_MSC_BOTXferParam.MSCState = HOST_MSC_REQUEST_SENSE;
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND;
- } else {
- /* Error trials exceeded the limit, go to unrecovered state */
- USBH_MSC_BOTXferParam.MSCState = HOST_MSC_UNRECOVERED_STATE;
- }
- break;
- case USB_HOST_MSC_PHASE_ERROR:
- /* Phase error, Go to Unrecoovered state */
- USBH_MSC_BOTXferParam.MSCState = HOST_MSC_UNRECOVERED_STATE;
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief Interface initialization for msc class application, the channels for
- * the IN and OUT EP will be distributed.
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval status defined by HOST_STATUS
- */
-HOST_STATUS usb_host_msc_itfinit(usb_core_instance *pdev, void *phost)
-{
- USBH_HOST *pphost = phost;
-
- if ((pphost->device_prop.devitfdesc[0].bInterfaceClass == MSC_CLASS) && \
- (pphost->device_prop.devitfdesc[0].bInterfaceProtocol == MSC_PROTOCOL)) {
- if ((pphost->device_prop.devepdesc[0][0].bEndpointAddress & 0x80U) == 0x80U) {
- MSC_Machine.MSC_BulkInEp = (pphost->device_prop.devepdesc[0][0].bEndpointAddress);
- MSC_Machine.MSC_BulkInEpSize = pphost->device_prop.devepdesc[0][0].wMaxPacketSize;
- } else {
- MSC_Machine.MSC_BulkOutEp = (pphost->device_prop.devepdesc[0][0].bEndpointAddress);
- MSC_Machine.MSC_BulkOutEpSize = pphost->device_prop.devepdesc[0] [0].wMaxPacketSize;
- }
- if ((pphost->device_prop.devepdesc[0][1].bEndpointAddress & 0x80U) == 0x80U) {
- MSC_Machine.MSC_BulkInEp = (pphost->device_prop.devepdesc[0][1].bEndpointAddress);
- MSC_Machine.MSC_BulkInEpSize = pphost->device_prop.devepdesc[0][1].wMaxPacketSize;
- } else {
- MSC_Machine.MSC_BulkOutEp = (pphost->device_prop.devepdesc[0][1].bEndpointAddress);
- MSC_Machine.MSC_BulkOutEpSize = pphost->device_prop.devepdesc[0][1].wMaxPacketSize;
- }
- /* distribute the channels for the EPs */
- MSC_Machine.hc_num_out = usb_host_distrch(pdev, MSC_Machine.MSC_BulkOutEp);
- MSC_Machine.hc_num_in = usb_host_distrch(pdev, MSC_Machine.MSC_BulkInEp);
- /* open the channels that have distributed */
- usb_host_chopen(pdev,
- MSC_Machine.hc_num_out,
- pphost->device_prop.devaddr,
- pphost->device_prop.devspeed,
- EP_TYPE_BULK,
- MSC_Machine.MSC_BulkOutEpSize);
- usb_host_chopen(pdev,
- MSC_Machine.hc_num_in,
- pphost->device_prop.devaddr,
- pphost->device_prop.devspeed,
- EP_TYPE_BULK,
- MSC_Machine.MSC_BulkInEpSize);
- } else {
- pphost->user_callbk->huser_devunsupported();
- }
- return HSTATUS_OK ;
-}
-
-/**
- * @brief deinitialize interface of msc class by freeing host channels
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_host_msc_itfdeinit(usb_core_instance *pdev)
-{
- if (MSC_Machine.hc_num_out != 0U) {
- usb_hchstop(&pdev->regs, MSC_Machine.hc_num_out);
- (void)usb_host_freech(pdev, MSC_Machine.hc_num_out);
- MSC_Machine.hc_num_out = 0U;
- }
- if (MSC_Machine.hc_num_in != 0U) {
- usb_hchstop(&pdev->regs, MSC_Machine.hc_num_in);
- (void)usb_host_freech(pdev, MSC_Machine.hc_num_in);
- MSC_Machine.hc_num_in = 0U;
- }
-}
-
-/**
- * @brief initialize the msc state machine
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval status defined by HOST_STATUS
- */
-HOST_STATUS usb_host_msc_classreq(usb_core_instance *pdev, void *phost)
-{
- USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_INIT_STATE;
- return HSTATUS_OK;
-}
-
-/**
- * @brief process the msc state machine
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval status defined by HOST_STATUS
- */
-HOST_STATUS usb_host_msc_process(usb_core_instance *pdev, void *phost)
-{
- USBH_HOST *pphost = phost;
- HOST_STATUS status = HSTATUS_BUSY;
- USB_HOST_MSC_STATUS mscStatus;
- uint8_t appliStatus;
- static uint8_t maxLunExceed = FALSE;
-
- if (host_driver_ifdevconnected(pdev) != 0UL) {
- switch (USBH_MSC_BOTXferParam.MSCState) {
- case HOST_MSC_BOT_INIT_STATE:
- usb_host_msc_init(pdev);
- USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_RESET;
- break;
- case HOST_MSC_BOT_RESET:
- /* donot issue a request to reset the bot here, only when bot unrecovered error. */
- USBH_MSC_BOTXferParam.MSCState = HOST_MSC_GET_MAX_LUN;
- break;
- case HOST_MSC_GET_MAX_LUN:
- /* issue a request to get the max logical unit(MAXLUN). */
- status = usb_host_msc_maxlun_get(pdev, phost);
- if (status == HSTATUS_OK) {
- MSC_Machine.maxLun = *(MSC_Machine.buff) ;
- if ((MSC_Machine.maxLun > 0U) && (maxLunExceed == FALSE)) {
- maxLunExceed = TRUE;
- pphost->user_callbk->huser_devunsupported();
- break;
- }
- USBH_MSC_BOTXferParam.MSCState = HOST_MSC_TEST_UNIT_READY;
- }
-
- if (status == HSTATUS_UNSUPPORTED) {
- /* if the request fails, it needs to move to next state and should save the next state as backup */
- USBH_MSC_BOTXferParam.MSCStateBkp = HOST_MSC_TEST_UNIT_READY;
- /* a clear feature should be issued if the request fails. */
- USBH_MSC_BOTXferParam.MSCState = HOST_MSC_CTRL_ERROR_STATE;
- }
- break;
- case HOST_MSC_CTRL_ERROR_STATE:
- /* issue a request to clear feature */
- status = usb_host_clrfeature(pdev,
- phost,
- 0x00U,
- pphost->ctrlparam.hc_num_out);
- if (status == HSTATUS_OK) {
- /* If GetMaxLun Request not support, assume Single LUN configuration */
- MSC_Machine.maxLun = 0U;
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOTXferParam.MSCStateBkp;
- }
- break;
- case HOST_MSC_TEST_UNIT_READY:
- /* issue the request Test Unit Ready[0] of SCSI command */
- mscStatus = usb_host_msc_TestUnitReady(pdev);
-
- if (mscStatus == USB_HOST_MSC_OK) {
- USBH_MSC_BOTXferParam.MSCState = HOST_MSC_READ_CAPACITY10;
- MSCErrorCount = 0U;
- status = HSTATUS_OK;
- } else {
- usb_host_msc_error_process(mscStatus);
- }
- break;
-
- case HOST_MSC_READ_CAPACITY10:
- /* issue the request Read Capacity[0] of SCSI command. */
- mscStatus = usb_host_msc_ReadCapacity10(pdev);
- if (mscStatus == USB_HOST_MSC_OK) {
- USBH_MSC_BOTXferParam.MSCState = HOST_MSC_MODE_SENSE6;
- MSCErrorCount = 0U;
- status = HSTATUS_OK;
- } else {
- usb_host_msc_error_process(mscStatus);
- }
- break;
- case HOST_MSC_MODE_SENSE6:
- /* issue the request ModeSense6 of SCSI command for detecting whelth the deviec is write-protected. */
- mscStatus = usb_host_msc_ModeSense6(pdev);
- if (mscStatus == USB_HOST_MSC_OK) {
- USBH_MSC_BOTXferParam.MSCState = HOST_MSC_DEFAULT_APPLI_STATE;
- MSCErrorCount = 0U;
- status = HSTATUS_OK;
- } else {
- usb_host_msc_error_process(mscStatus);
- }
- break;
- case HOST_MSC_REQUEST_SENSE:
- /* issue the request RequestSense of SCSI command for retreiving error code. */
- mscStatus = usb_host_msc_RequestSense(pdev);
- if (mscStatus == USB_HOST_MSC_OK) {
- USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOTXferParam.MSCStateBkp;
- status = HSTATUS_OK;
- } else {
- usb_host_msc_error_process(mscStatus);
- }
- break;
- case HOST_MSC_BOT_USB_TRANSFERS:
- /* handle the BOT state machine. */
- usb_host_msc_botxferprocess(pdev, phost);
- break;
- case HOST_MSC_DEFAULT_APPLI_STATE:
- /* handle the user callback for the msc application. */
- appliStatus = pphost->user_callbk->huser_application();
- if (appliStatus == 0U) {
- USBH_MSC_BOTXferParam.MSCState = HOST_MSC_DEFAULT_APPLI_STATE;
- } else if (appliStatus == 1U) {
- /* deinit requested from the application layer. */
- status = HSTATUS_APP_DEINIT;
- } else {
- ;
- }
- break;
- case HOST_MSC_UNRECOVERED_STATE:
- status = HSTATUS_UNRECOVERED_ERROR;
- break;
- default:
- break;
- }
- }
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.h
deleted file mode 100644
index 783f12d39c..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_msc_class.h
- * @brief Head file for usb_host_msc_class.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_HOST_MSC_CLASS_H__
-#define __USB_HOST_MSC_CLASS_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_core.h"
-#include "usb_host_stdreq.h"
-#include "usb_bsp.h"
-#include "usb_host_ctrltrans.h"
-#include "usb_host_cfgch.h"
-#include "usb_host_msc_class.h"
-#include "usb_host_msc_scsi.h"
-#include "usb_host_msc_bot.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_MSC
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-
-/* Structure for MSC process */
-typedef struct {
- uint8_t hc_num_in;
- uint8_t hc_num_out;
- uint8_t MSC_BulkOutEp;
- uint8_t MSC_BulkInEp;
- uint16_t MSC_BulkInEpSize;
- uint16_t MSC_BulkOutEpSize;
- uint8_t buff[USBH_MSC_MPS_SIZE];
- uint8_t maxLun;
-} MSC_Machine_TypeDef;
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#define USB_REQ_BOT_RESET (0xFFU)
-#define USB_REQ_GET_MAX_LUN (0xFEU)
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-extern usb_host_class_callback_func USBH_MSC_cb;
-extern MSC_Machine_TypeDef MSC_Machine;
-extern uint8_t MSCErrorCount;
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_HOST_MSC_CLASS_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
-
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_fatfs.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_fatfs.c
deleted file mode 100644
index 5db87bed6e..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_fatfs.c
+++ /dev/null
@@ -1,240 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_msc_fatfs.c
- * @brief The fatfs functions.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2023-09-30 CDT Modify for doxygen
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_app_conf.h"
-#include "usb_host_driver.h"
-#ifdef USB_MSC_FAT_VALID
-#include "ff.h"
-#include "diskio.h"
-#include "usb_host_msc_class.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_MSC
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-static volatile DSTATUS Stat = STA_NOINIT; /* Disk status */
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-extern usb_core_instance usb_app_instance;
-extern USBH_HOST usb_app_host;
-
-/**
- * @brief Initialize Disk Drive
- * @param [in] pdrv Physical drive number (0)
- * @retval DSTATUS
- */
-DSTATUS disk_initialize(BYTE pdrv)
-{
- if (host_driver_ifdevconnected(&usb_app_instance) != 0UL) {
- Stat &= (DSTATUS)~STA_NOINIT;
- }
- return Stat;
-}
-
-/**
- * @brief Get Disk Status
- * @param [in] pdrv Physical drive number (0)
- * @retval DSTATUS
- */
-DSTATUS disk_status(BYTE pdrv)
-{
- DSTATUS status = Stat;
- if (pdrv != 0U) {
- status = STA_NOINIT; /* Supports only single drive */
- }
- return status;
-}
-
-/**
- * @brief Read Sector(s)
- * @param [in] pdrv Physical drive number (0)
- * @param [in] buff Pointer to the data buffer to store read data
- * @param [in] sector Start sector number (LBA)
- * @param [in] count Sector count (1..255)
- * @retval DSTATUS
- */
-DRESULT disk_read(BYTE pdrv, BYTE *buff, LBA_t sector, UINT count)
-{
- USB_HOST_MSC_STATUS status = USB_HOST_MSC_OK;
-
- if ((pdrv != 0U) || (count == 0UL)) {
- return RES_PARERR;
- }
- if ((Stat & STA_NOINIT) == STA_NOINIT) {
- return RES_NOTRDY;
- }
-
- if (host_driver_ifdevconnected(&usb_app_instance) != 0UL) {
-
- do {
- status = usb_host_msc_Read10(&usb_app_instance, buff, sector, 512UL * (uint32_t)count);
- usb_host_msc_botxferprocess(&usb_app_instance, &usb_app_host);
-
- if (host_driver_ifdevconnected(&usb_app_instance) == 0UL) {
- return RES_ERROR;
- }
- } while (status == USB_HOST_MSC_BUSY);
- }
-
- if (status == USB_HOST_MSC_OK) {
- return RES_OK;
- }
- return RES_ERROR;
-
-}
-
-#if _READONLY == 0
-/**
- * @brief Write Sector(s)
- * @param [in] pdrv Physical drive number (0)
- * @param [in] buff Pointer to the data to be written
- * @param [in] sector Start sector number (LBA)
- * @param [in] count Sector count (1..255)
- * @retval DSTATUS
- */
-DRESULT disk_write(BYTE pdrv, const BYTE *buff, LBA_t sector, UINT count)
-{
- USB_HOST_MSC_STATUS status = USB_HOST_MSC_OK;
-
- if ((pdrv != 0U) || (count == 0UL)) {
- return RES_PARERR;
- }
- if ((Stat & STA_NOINIT) == STA_NOINIT) {
- return RES_NOTRDY;
- }
- if ((Stat & STA_PROTECT) == STA_PROTECT) {
- return RES_WRPRT;
- }
- if (host_driver_ifdevconnected(&usb_app_instance) != 0UL) {
- do {
- status = usb_host_msc_Write10(&usb_app_instance, (BYTE *)buff, sector, 512UL * (uint32_t)count);
- usb_host_msc_botxferprocess(&usb_app_instance, &usb_app_host);
-
- if (host_driver_ifdevconnected(&usb_app_instance) == 0UL) {
- return RES_ERROR;
- }
- } while (status == USB_HOST_MSC_BUSY);
- }
-
- if (status == USB_HOST_MSC_OK) {
- return RES_OK;
- }
- return RES_ERROR;
-}
-#endif /* _READONLY == 0 */
-
-/**
- * @brief Miscellaneous Functions
- * @param [in] pdrv Physical drive number (0)
- * @param [in] cmd Command code
- * @param [in] buff Buffer to send/receive control data
- **
- * @retval DSTATUS
- */
-DRESULT disk_ioctl(BYTE pdrv, BYTE cmd, void *buff)
-{
- DRESULT res;
-
- if (pdrv != 0U) {
- return RES_PARERR;
- }
-
- res = RES_ERROR;
-
- if ((Stat & STA_NOINIT) == STA_NOINIT) {
- return RES_NOTRDY;
- }
-
- switch (cmd) {
- case CTRL_SYNC : /* Make sure that no pending write process */
- res = RES_OK;
- break;
- case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */
- *(DWORD *)buff = (DWORD) USB_HOST_MSC_Param.MSC_Capacity;
- res = RES_OK;
- break;
- case GET_SECTOR_SIZE : /* Get R/W sector size (WORD) */
- *(WORD *)buff = 512U;
- res = RES_OK;
- break;
- case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */
- *(DWORD *)buff = 512UL;
- break;
- default:
- res = RES_PARERR;
- break;
- }
- return res;
-}
-
-#endif /* #ifdef USB_MSC_FAT_VALID */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.c
deleted file mode 100644
index 168e4bd0d8..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.c
+++ /dev/null
@@ -1,524 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_msc_scsi.c
- * @brief The SCSI commands。
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2023-06-30 CDT Modify for variable alignment
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_msc_class.h"
-#include "usb_host_msc_scsi.h"
-#include "usb_host_msc_bot.h"
-#include "usb_host_ctrltrans.h"
-#include "usb_host_def.h"
-#include "usb_host_driver.h"
-#include
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_MSC
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-MSC_PARAMETER USB_HOST_MSC_Param;
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-__USB_ALIGN_BEGIN static uint8_t USB_HOST_DataInBuf[512];
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @brief Issues 'Test Unit Ready' command to the device. Once the response
- * received, it updates the status to upper layer, the length of the
- * command are 31bytes.
- * @param [in] pdev device instance
- * @retval status define by USB_HOST_MSC_STATUS
- */
-USB_HOST_MSC_STATUS usb_host_msc_TestUnitReady(usb_core_instance *pdev)
-{
- uint8_t index;
- USB_HOST_MSC_STATUS status = USB_HOST_MSC_BUSY;
-
- if (host_driver_ifdevconnected(pdev) != 0UL) {
- switch (USBH_MSC_BOTXferParam.CmdStateMachine) {
- case USB_HOST_MSC_CMD_SEND:
- USBH_MSC_CBWData.field.CBWTransferLength = 0UL;
- USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_OUT;
- USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH_TEST_UNIT_READY;
- USBH_MSC_BOTXferParam.pRxTxBuff = USBH_MSC_CSWData.CSWArray;
- USBH_MSC_BOTXferParam.DataLength = HOST_MSC_CSW_MAX_LENGTH;
- USBH_MSC_BOTXferParam.MSCStateCurrent = HOST_MSC_TEST_UNIT_READY;
- for (index = 0U; index < CBW_CB_LENGTH; index++) {
- USBH_MSC_CBWData.field.CBWCB[index] = 0x00U;
- }
- USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_TEST_UNIT_READY;
- USBH_MSC_BOTXferParam.BOTState = HOST_MSC_SEND_CBW;
- /* Start the transfer, then let the state machine magage the other transactions */
- USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_USB_TRANSFERS;
- USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_BUSY;
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_WAIT;
-
- status = USB_HOST_MSC_BUSY;
- break;
-
- case USB_HOST_MSC_CMD_WAIT:
- switch (USBH_MSC_BOTXferParam.BOTXferStatus) {
- case USB_HOST_MSC_OK:
- /* Commands successfully sent and Response Received */
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND;
- status = USB_HOST_MSC_OK;
- break;
- case USB_HOST_MSC_FAIL:
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND;
- status = USB_HOST_MSC_FAIL;
- break;
- case USB_HOST_MSC_PHASE_ERROR:
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND;
- status = USB_HOST_MSC_PHASE_ERROR;
- break;
- default:
- break;
- }
- break;
- default:
- break;
- }
- }
- return status;
-}
-
-/**
- * @brief Issue the 'Read capacity10' command to the device. Once the response
- * received, it updates the status to upper layer
- * @param [in] pdev device instance
- * @retval status define by USB_HOST_MSC_STATUS
- */
-USB_HOST_MSC_STATUS usb_host_msc_ReadCapacity10(usb_core_instance *pdev)
-{
- uint8_t index;
- USB_HOST_MSC_STATUS status = USB_HOST_MSC_BUSY;
-
- if (host_driver_ifdevconnected(pdev) != 0UL) {
- switch (USBH_MSC_BOTXferParam.CmdStateMachine) {
- case USB_HOST_MSC_CMD_SEND:
- /*Prepare the CBW and relevent field*/
- USBH_MSC_CBWData.field.CBWTransferLength = XFER_LEN_READ_CAPACITY10;
- USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN;
- USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH;
- USBH_MSC_BOTXferParam.pRxTxBuff = USB_HOST_DataInBuf;
- USBH_MSC_BOTXferParam.MSCStateCurrent = HOST_MSC_READ_CAPACITY10;
- for (index = 0U; index < CBW_CB_LENGTH; index++) {
- USBH_MSC_CBWData.field.CBWCB[index] = 0x00U;
- }
- USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_READ_CAPACITY10;
- USBH_MSC_BOTXferParam.BOTState = HOST_MSC_SEND_CBW;
- /* Start the transfer, then let the state machine manage the other
- transactions */
- USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_USB_TRANSFERS;
- USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_BUSY;
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_WAIT;
- status = USB_HOST_MSC_BUSY;
- break;
-
- case USB_HOST_MSC_CMD_WAIT:
- switch (USBH_MSC_BOTXferParam.BOTXferStatus) {
- case USB_HOST_MSC_OK:
- /*assign the capacity*/
- (((uint8_t *)&USB_HOST_MSC_Param.MSC_Capacity)[3]) = USB_HOST_DataInBuf[0];
- (((uint8_t *)&USB_HOST_MSC_Param.MSC_Capacity)[2]) = USB_HOST_DataInBuf[1];
- (((uint8_t *)&USB_HOST_MSC_Param.MSC_Capacity)[1]) = USB_HOST_DataInBuf[2];
- (((uint8_t *)&USB_HOST_MSC_Param.MSC_Capacity)[0]) = USB_HOST_DataInBuf[3];
- /*assign the page length*/
- (((uint8_t *)&USB_HOST_MSC_Param.MSC_PageLength)[1]) = USB_HOST_DataInBuf[6];
- (((uint8_t *)&USB_HOST_MSC_Param.MSC_PageLength)[0]) = USB_HOST_DataInBuf[7];
- /* Commands successfully sent and Response Received */
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND;
- status = USB_HOST_MSC_OK;
- break;
- case USB_HOST_MSC_FAIL:
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND;
- status = USB_HOST_MSC_FAIL;
- break;
- case USB_HOST_MSC_PHASE_ERROR:
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND;
- status = USB_HOST_MSC_PHASE_ERROR;
- break;
- default:
- break;
- }
- break;
-
- default:
- break;
- }
- }
- return status;
-}
-
-/**
- * @brief Issue the 'Mode Sense6' Command to the device. This function is used
- * for reading the WriteProtect Status of the MSC device.
- * @param [in] pdev device instance
- * @retval status by USB_HOST_MSC_STATUS
- */
-USB_HOST_MSC_STATUS usb_host_msc_ModeSense6(usb_core_instance *pdev)
-{
- uint8_t index;
- USB_HOST_MSC_STATUS status = USB_HOST_MSC_BUSY;
-
- if (host_driver_ifdevconnected(pdev) != 0UL) {
- switch (USBH_MSC_BOTXferParam.CmdStateMachine) {
- case USB_HOST_MSC_CMD_SEND:
- /*Prepare the CBW and relevent field*/
- USBH_MSC_CBWData.field.CBWTransferLength = XFER_LEN_MODE_SENSE6;
- USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN;
- USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH;
-
- USBH_MSC_BOTXferParam.pRxTxBuff = USB_HOST_DataInBuf;
- USBH_MSC_BOTXferParam.MSCStateCurrent = HOST_MSC_MODE_SENSE6;
-
- for (index = 0U; index < CBW_CB_LENGTH; index++) {
- USBH_MSC_CBWData.field.CBWCB[index] = 0x00U;
- }
-
- USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_MODE_SENSE6;
- USBH_MSC_CBWData.field.CBWCB[2] = MODE_SENSE_PAGE_CONTROL_FIELD | \
- MODE_SENSE_PAGE_CODE;
-
- USBH_MSC_CBWData.field.CBWCB[4] = XFER_LEN_MODE_SENSE6;
-
- USBH_MSC_BOTXferParam.BOTState = HOST_MSC_SEND_CBW;
-
- /* Start the transfer, then let the state machine manage the other
- transactions */
- USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_USB_TRANSFERS;
- USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_BUSY;
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_WAIT;
-
- status = USB_HOST_MSC_BUSY;
- break;
-
- case USB_HOST_MSC_CMD_WAIT:
- switch (USBH_MSC_BOTXferParam.BOTXferStatus) {
- case USB_HOST_MSC_OK:
- /* Assign the Write Protect status */
- /* If WriteProtect = 0, Writing is allowed
- If WriteProtect != 0, Disk is Write Protected */
- if (0U != (USB_HOST_DataInBuf[2] & MASK_MODE_SENSE_WRITE_PROTECT)) {
- USB_HOST_MSC_Param.MSC_WriteProtect = DISK_WRITE_PROTECTED;
- } else {
- USB_HOST_MSC_Param.MSC_WriteProtect = 0U;
- }
-
- /* Commands successfully sent and Response Received */
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND;
- status = USB_HOST_MSC_OK;
- break;
- case USB_HOST_MSC_FAIL:
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND;
- status = USB_HOST_MSC_FAIL;
- break;
- case USB_HOST_MSC_PHASE_ERROR:
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND;
- status = USB_HOST_MSC_PHASE_ERROR;
- break;
- default:
- break;
- }
- break;
-
- default:
- break;
- }
- }
- return status;
-}
-
-/**
- * @brief usb_host_msc_RequestSense
- * Issues the Request Sense command to the device. Once the response
- * received, it updates the status to upper layer
- * @param [in] pdev device instance
- * @retval status defined by USB_HOST_MSC_STATUS
- */
-USB_HOST_MSC_STATUS usb_host_msc_RequestSense(usb_core_instance *pdev)
-{
- USB_HOST_MSC_STATUS status = USB_HOST_MSC_BUSY;
- uint8_t index;
-
- if (host_driver_ifdevconnected(pdev) != 0UL) {
- switch (USBH_MSC_BOTXferParam.CmdStateMachine) {
- case USB_HOST_MSC_CMD_SEND:
- /*Prepare the CBW and relevent field*/
- USBH_MSC_CBWData.field.CBWTransferLength = \
- ALLOCATION_LENGTH_REQUEST_SENSE;
- USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN;
- USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH;
-
- USBH_MSC_BOTXferParam.pRxTxBuff = USB_HOST_DataInBuf;
- USBH_MSC_BOTXferParam.MSCStateBkp = USBH_MSC_BOTXferParam.MSCStateCurrent;
- USBH_MSC_BOTXferParam.MSCStateCurrent = HOST_MSC_REQUEST_SENSE;
-
- for (index = 0U; index < CBW_CB_LENGTH; index++) {
- USBH_MSC_CBWData.field.CBWCB[index] = 0x00U;
- }
-
- USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_REQUEST_SENSE;
- USBH_MSC_CBWData.field.CBWCB[1] = DESC_REQUEST_SENSE;
- USBH_MSC_CBWData.field.CBWCB[4] = ALLOCATION_LENGTH_REQUEST_SENSE;
-
- USBH_MSC_BOTXferParam.BOTState = HOST_MSC_SEND_CBW;
- /* Start the transfer, then let the state machine magage
- the other transactions */
- USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_USB_TRANSFERS;
- USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_BUSY;
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_WAIT;
- status = USB_HOST_MSC_BUSY;
- break;
-
- case USB_HOST_MSC_CMD_WAIT:
- switch (USBH_MSC_BOTXferParam.BOTXferStatus) {
- case USB_HOST_MSC_OK:
- /* Get Sense data*/
- (((uint8_t *)&USB_HOST_MSC_Param.MSC_Sense)[3]) = USB_HOST_DataInBuf[0];
- (((uint8_t *)&USB_HOST_MSC_Param.MSC_Sense)[2]) = USB_HOST_DataInBuf[1];
- (((uint8_t *)&USB_HOST_MSC_Param.MSC_Sense)[1]) = USB_HOST_DataInBuf[2];
- (((uint8_t *)&USB_HOST_MSC_Param.MSC_Sense)[0]) = USB_HOST_DataInBuf[3];
-
- /* Commands successfully sent and Response Received */
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND;
- status = USB_HOST_MSC_OK;
- break;
- case USB_HOST_MSC_FAIL:
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND;
- status = USB_HOST_MSC_FAIL;
- break;
- case USB_HOST_MSC_PHASE_ERROR:
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND;
- status = USB_HOST_MSC_PHASE_ERROR;
- break;
- default:
- break;
- }
- break;
-
- default:
- break;
- }
- }
- return status;
-}
-
-/**
- * @brief issue the 'Write10 ' command to the device. Once the response received,
- * it updates the status to upper layer
- * @param [in] pdev device instance
- * @param [in] dataBuffer data buffer contains the data to write
- * @param [in] address address to which the data will be written
- * @param [in] nbOfbytes NbOfbytes to be written
- * @retval status define by USB_HOST_MSC_STATUS
- */
-USB_HOST_MSC_STATUS usb_host_msc_Write10(usb_core_instance *pdev,
- uint8_t *dataBuffer,
- uint32_t address,
- uint32_t nbOfbytes)
-{
- uint8_t index;
- USB_HOST_MSC_STATUS status = USB_HOST_MSC_BUSY;
- uint16_t nbOfPages;
-
- if (host_driver_ifdevconnected(pdev) != 0UL) {
- switch (USBH_MSC_BOTXferParam.CmdStateMachine) {
- case USB_HOST_MSC_CMD_SEND:
- USBH_MSC_CBWData.field.CBWTransferLength = nbOfbytes;
- USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_OUT;
- USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH;
- USBH_MSC_BOTXferParam.pRxTxBuff = dataBuffer;
-
- for (index = 0U; index < CBW_CB_LENGTH; index++) {
- USBH_MSC_CBWData.field.CBWCB[index] = 0x00U;
- }
-
- USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_WRITE10;
- /*logical block address*/
- USBH_MSC_CBWData.field.CBWCB[2] = (((uint8_t *)&address)[3]) ;
- USBH_MSC_CBWData.field.CBWCB[3] = (((uint8_t *)&address)[2]);
- USBH_MSC_CBWData.field.CBWCB[4] = (((uint8_t *)&address)[1]);
- USBH_MSC_CBWData.field.CBWCB[5] = (((uint8_t *)&address)[0]);
-
- /*HOST_MSC_PAGE_LENGTH = 512*/
- nbOfPages = (uint16_t)(nbOfbytes / HOST_MSC_PAGE_LENGTH);
-
- /*Tranfer length */
- USBH_MSC_CBWData.field.CBWCB[7] = (((uint8_t *)&nbOfPages)[1]) ;
- USBH_MSC_CBWData.field.CBWCB[8] = (((uint8_t *)&nbOfPages)[0]) ;
-
- USBH_MSC_BOTXferParam.BOTState = HOST_MSC_SEND_CBW;
- /* Start the transfer, then let the state machine
- magage the other transactions */
- USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_USB_TRANSFERS;
- USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_BUSY;
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_WAIT;
-
- status = USB_HOST_MSC_BUSY;
- break;
-
- case USB_HOST_MSC_CMD_WAIT:
- switch (USBH_MSC_BOTXferParam.BOTXferStatus) {
- case USB_HOST_MSC_OK:
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND;
- status = USB_HOST_MSC_OK;
- break;
- case USB_HOST_MSC_FAIL:
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND;
- break;
- case USB_HOST_MSC_PHASE_ERROR:
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND;
- status = USB_HOST_MSC_PHASE_ERROR;
- break;
- default:
- break;
- }
- break;
-
- default:
- break;
- }
- }
- return status;
-}
-
-/**
- * @brief issue the read command to the device. Once the response received,
- * it updates the status to upper layer
- * @param [in] pdev device instance
- * @param [in] dataBuffer data buffer will contain the data to be read
- * @param [in] address Address from which the data will be read
- * @param [in] nbOfbytes number of bytes to be read
- * @retval status defined by USB_HOST_MSC_STATUS
- */
-USB_HOST_MSC_STATUS usb_host_msc_Read10(usb_core_instance *pdev,
- uint8_t *dataBuffer,
- uint32_t address,
- uint32_t nbOfbytes)
-{
- uint8_t index;
- static USB_HOST_MSC_STATUS status = USB_HOST_MSC_BUSY;
- uint16_t nbOfPages;
- status = USB_HOST_MSC_BUSY;
-
- if (host_driver_ifdevconnected(pdev) != 0UL) {
- switch (USBH_MSC_BOTXferParam.CmdStateMachine) {
- case USB_HOST_MSC_CMD_SEND:
- /*Prepare the CBW and relevent field*/
- USBH_MSC_CBWData.field.CBWTransferLength = nbOfbytes;
- USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN;
- USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH;
-
- USBH_MSC_BOTXferParam.pRxTxBuff = dataBuffer;
-
- for (index = 0U; index < CBW_CB_LENGTH; index++) {
- USBH_MSC_CBWData.field.CBWCB[index] = 0x00U;
- }
-
- USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_READ10;
-
- /*logical block address*/
- USBH_MSC_CBWData.field.CBWCB[2] = (((uint8_t *)&address)[3]);
- USBH_MSC_CBWData.field.CBWCB[3] = (((uint8_t *)&address)[2]);
- USBH_MSC_CBWData.field.CBWCB[4] = (((uint8_t *)&address)[1]);
- USBH_MSC_CBWData.field.CBWCB[5] = (((uint8_t *)&address)[0]);
- /*HOST_MSC_PAGE_LENGTH = 512*/
- nbOfPages = (uint16_t)(nbOfbytes / HOST_MSC_PAGE_LENGTH);
- /*Tranfer length */
- USBH_MSC_CBWData.field.CBWCB[7] = (((uint8_t *)&nbOfPages)[1]) ;
- USBH_MSC_CBWData.field.CBWCB[8] = (((uint8_t *)&nbOfPages)[0]) ;
- USBH_MSC_BOTXferParam.BOTState = HOST_MSC_SEND_CBW;
- /* Start the transfer, then let the state machine
- magage the other transactions */
- USBH_MSC_BOTXferParam.MSCState = HOST_MSC_BOT_USB_TRANSFERS;
- USBH_MSC_BOTXferParam.BOTXferStatus = (uint8_t)USB_HOST_MSC_BUSY;
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_WAIT;
- status = USB_HOST_MSC_BUSY;
- break;
-
- case USB_HOST_MSC_CMD_WAIT:
- switch (USBH_MSC_BOTXferParam.BOTXferStatus) {
- case USB_HOST_MSC_OK:
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND;
- status = USB_HOST_MSC_OK;
- break;
- case USB_HOST_MSC_FAIL:
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND;
- break;
- case USB_HOST_MSC_PHASE_ERROR:
- USBH_MSC_BOTXferParam.CmdStateMachine = USB_HOST_MSC_CMD_SEND;
- status = USB_HOST_MSC_PHASE_ERROR;
- break;
- default:
- break;
- }
- break;
-
- default:
- break;
- }
- }
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************************************************************************
- * EOF (not truncated)
- *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.h
deleted file mode 100644
index 66f562dfa7..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_msc_scsi.h
- * @brief Head file for usb_host_msc_scsi.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_HOST_MSC_SCSI_H__
-#define __USB_HOST_MSC_SCSI_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_stdreq.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CLASS
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_MSC
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-
-/* USBH_MSC_SCSI_Exported_Types */
-typedef enum {
- USB_HOST_MSC_OK = 0U,
- USB_HOST_MSC_FAIL,
- USB_HOST_MSC_PHASE_ERROR,
- USB_HOST_MSC_BUSY
-} USB_HOST_MSC_STATUS;
-
-typedef struct {
- uint32_t MSC_Capacity;
- uint32_t MSC_Sense;
- uint16_t MSC_PageLength;
- uint8_t MSC_BulkOutEP;
- uint8_t MSC_BulkInEP;
- uint8_t MSC_WriteProtect;
-} MSC_PARAMETER;
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#define USB_HOST_MSC_CMD_SEND (1)
-#define USB_HOST_MSC_CMD_WAIT (2)
-
-#define OPCODE_TEST_UNIT_READY (0x00U)
-#define OPCODE_READ_CAPACITY10 (0x25U)
-#define OPCODE_MODE_SENSE6 (0x1AU)
-#define OPCODE_READ10 (0x28U)
-#define OPCODE_WRITE10 (0x2AU)
-#define OPCODE_REQUEST_SENSE (0x03U)
-
-#define DESC_REQUEST_SENSE (0x00U)
-#define ALLOCATION_LENGTH_REQUEST_SENSE (63U)
-#define XFER_LEN_READ_CAPACITY10 (8U)
-#define XFER_LEN_MODE_SENSE6 (63U)
-
-#define MASK_MODE_SENSE_WRITE_PROTECT (0x80U)
-#define MODE_SENSE_PAGE_CONTROL_FIELD (0x00U)
-#define MODE_SENSE_PAGE_CODE (0x3FU)
-#define DISK_WRITE_PROTECTED (0x01U)
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-extern MSC_PARAMETER USB_HOST_MSC_Param;
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-extern USB_HOST_MSC_STATUS usb_host_msc_TestUnitReady(usb_core_instance *pdev);
-extern USB_HOST_MSC_STATUS usb_host_msc_ReadCapacity10(usb_core_instance *pdev);
-extern USB_HOST_MSC_STATUS usb_host_msc_ModeSense6(usb_core_instance *pdev);
-extern USB_HOST_MSC_STATUS usb_host_msc_RequestSense(usb_core_instance *pdev);
-extern USB_HOST_MSC_STATUS usb_host_msc_Write10(usb_core_instance *pdev,
- uint8_t *dataBuffer,
- uint32_t address,
- uint32_t nbOfbytes);
-extern USB_HOST_MSC_STATUS usb_host_msc_Read10(usb_core_instance *pdev,
- uint8_t *dataBuffer,
- uint32_t address,
- uint32_t nbOfbytes);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_HOST_MSC_SCSI_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
-
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.c
deleted file mode 100644
index 826b942690..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_cfgch.c
- * @brief Functions for opening and closing host channels
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2023-06-30 CDT Replace MAX_CHNUM by USB_MAX_CH_NUM
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_cfgch.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CORE LL USB Host Core
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-uint16_t usb_host_getfreech(usb_core_instance *pdev);
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @brief configure and open a pipe
- * @param [in] pdev device instance
- * @param [in] hc_num host channel index
- * @param [in] dev_address USB Device address allocated to attached device
- * @param [in] speed core speed
- * @param [in] ep_type communication type of the EP
- * @param [in] mps max size of the packet
- * @retval None
- */
-void usb_host_chopen(usb_core_instance *pdev,
- uint8_t hc_num,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps)
-{
- pdev->host.hc[hc_num].ep_idx = (uint8_t) pdev->host.channel[hc_num] & 0x7FU;
- pdev->host.hc[hc_num].is_epin = (uint8_t)((pdev->host.channel[hc_num] & 0x80U) == 0x80U);
- pdev->host.hc[hc_num].dev_addr = dev_address;
- pdev->host.hc[hc_num].ep_type = ep_type;
- pdev->host.hc[hc_num].max_packet = mps;
- pdev->host.hc[hc_num].ch_speed = speed;
- pdev->host.hc[hc_num].in_toggle = 0U;
- pdev->host.hc[hc_num].out_toggle = 0U;
-
- (void)usb_inithch(&pdev->regs, hc_num, &pdev->host.hc[hc_num], pdev->basic_cfgs.dmaen);
-}
-
-/**
- * @brief change a pipe on host
- * @param [in] pdev device instance
- * @param [in] hc_num host channel index
- * @param [in] dev_address USB Device address allocated to attached device
- * @param [in] speed core speed
- * @param [in] ep_type communication type of EP
- * @param [in] mps max size of packet
- * @retval None
- */
-void usb_host_mdfch(usb_core_instance *pdev,
- uint8_t hc_num,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps)
-{
- (void)(ep_type);
- if (dev_address != 0U) {
- pdev->host.hc[hc_num].dev_addr = dev_address;
- }
- if ((pdev->host.hc[hc_num].max_packet != mps) && (mps != 0U)) {
- pdev->host.hc[hc_num].max_packet = mps;
- }
- if ((pdev->host.hc[hc_num].ch_speed != speed) && (speed != 0U)) {
- pdev->host.hc[hc_num].ch_speed = speed;
- }
-
- (void)usb_inithch(&pdev->regs, hc_num, &pdev->host.hc[hc_num], pdev->basic_cfgs.dmaen);
-}
-
-/**
- * @brief distribute a new channel for the pipe
- * @param [in] pdev device instance
- * @param [in] ep_addr EP index the channel distributed for
- * @retval hc_num host channel index
- */
-uint8_t usb_host_distrch(usb_core_instance *pdev, uint8_t ep_addr)
-{
- __IO uint16_t hc_num;
-
- hc_num = usb_host_getfreech(pdev);
- if (hc_num != HC_ERROR) {
- pdev->host.channel[hc_num & (USB_MAX_TX_FIFOS - 1U)] = HC_USED | ep_addr;
- }
- return (uint8_t)hc_num;
-}
-
-/**
- * @brief free the USB host channel assigned by idx
- * @param [in] pdev device instance
- * @param [in] idx Channel number to be freed
- * @retval Status
- */
-uint8_t usb_host_freech(usb_core_instance *pdev, uint8_t idx)
-{
- if (idx < USB_MAX_CH_NUM) {
- pdev->host.channel[idx & (USB_MAX_TX_FIFOS - 1U)] &= HC_USED_MASK;
- }
- return (uint8_t)HSTATUS_OK;
-}
-
-/**
- * @brief free all the USB host channels
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_host_dedistrallch(usb_core_instance *pdev)
-{
- uint8_t idx;
-
- for (idx = 2U; idx < USB_MAX_CH_NUM ; idx ++) {
- pdev->host.channel[idx & (USB_MAX_TX_FIFOS - 1U)] = 0U;
- }
-}
-
-/**
- * @brief Get a free channel number so that can be distributed to a device endpoint
- * @param [in] pdev device instance
- * @retval idx the free channel index
- */
-uint16_t usb_host_getfreech(usb_core_instance *pdev)
-{
- uint8_t tmp_idx;
- uint16_t u16Ret = HC_ERROR;
-
- for (tmp_idx = 0U ; tmp_idx < USB_MAX_CH_NUM ; tmp_idx++) {
- if ((pdev->host.channel[tmp_idx & (USB_MAX_TX_FIFOS - 1U)] & HC_USED) == 0U) {
- u16Ret = HC_OK;
- break;
- }
- }
-
- if (u16Ret == HC_OK) {
- u16Ret = tmp_idx;
- } else {
- u16Ret = HC_ERROR;
- }
-
- return u16Ret;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************************************************************************
- * EOF (not truncated)
- *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.h
deleted file mode 100644
index 57ae579cdd..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_cfgch.h
- * @brief header file for the usb_host_cfgch.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2023-06-30 CDT Delete micro define MAX_CHNUM
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_HOST_CFGCH_H__
-#define __USB_HOST_CFGCH_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_def.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CORE
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-#define HC_OK (0x0000U)
-#define HC_USED (0x8000U)
-#define HC_ERROR (0xFFFFU)
-#define HC_USED_MASK (0x7FFFU)
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-extern uint8_t usb_host_distrch(usb_core_instance *pdev, uint8_t ep_addr);
-
-extern uint8_t usb_host_freech(usb_core_instance *pdev, uint8_t idx);
-
-extern void usb_host_dedistrallch(usb_core_instance *pdev);
-
-extern void usb_host_chopen(usb_core_instance *pdev,
- uint8_t hc_num,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps);
-
-extern void usb_host_mdfch(usb_core_instance *pdev,
- uint8_t hc_num,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_HOST_CFGCH_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.c
deleted file mode 100644
index d944fb953d..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.c
+++ /dev/null
@@ -1,549 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_core.c
- * @brief The core state machine process the enumeration and the control transfer process
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2022-06-30 CDT Add USB core ID select function
- 2023-01-15 CDT Optimize for device insert detection
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include
-#include "usb_host_core.h"
-#include "usb_host_cfgch.h"
-#include "usb_host_ctrltrans.h"
-#include "usb_host_driver.h"
-#include "usb_host_stdreq.h"
-#include "usb_host_int.h"
-#include "usb_bsp.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CORE
- * @{
- */
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-HOST_STATUS usb_host_ctrlprocess(usb_core_instance *pdev, USBH_HOST *phost);
-HOST_STATUS usb_host_enumprocess(usb_core_instance *pdev, USBH_HOST *phost);
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-static uint8_t Local_Buffer[ENUM_LOCAL_BUF];
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @brief initialization for the host application
- * @param [in] pdev device instance
- * @param [in] pstcPortIdentify usb core and phy select
- * @param [in] phost host state set
- * @param [in] class_cbk the call back function for the class application
- * @param [in] user_cbk the call back function for user
- * @retval None
- */
-void usb_host_init(usb_core_instance *pdev,
- stc_usb_port_identify *pstcPortIdentify,
- USBH_HOST *phost,
- usb_host_class_callback_func *class_cbk,
- usb_host_user_callback_func *user_cbk)
-{
- usb_bsp_init(pdev, pstcPortIdentify);
- usb_host_deinit(pdev, phost);
- phost->class_callbk = class_cbk;
- phost->user_callbk = user_cbk;
- host_driver_init(pdev, pstcPortIdentify);
- phost->user_callbk->huser_init();
- usb_bsp_nvicconfig(pdev);
-}
-
-/**
- * @brief deinitialize the host application
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval None
- */
-void usb_host_deinit(usb_core_instance *pdev, USBH_HOST *phost)
-{
- phost->host_state = HOST_IDLE;
- phost->host_state_backup = HOST_IDLE;
- phost->enum_state = ENUM_IDLE;
- phost->req_state = REQ_CMD_TX;
-
- phost->ctrlparam.ctrl_state = CTRL_SETUP;
- phost->ctrlparam.ctrlmaxsize = USB_MAX_EP0_SIZE;
-
- phost->device_prop.devaddr = DEV_DEFAULT_ADDRESS;
- phost->device_prop.devspeed = PRTSPD_FULL_SPEED;
-
- (void)usb_host_freech(pdev, phost->ctrlparam.hc_num_in);
- (void)usb_host_freech(pdev, phost->ctrlparam.hc_num_out);
-}
-
-/**
- * @brief This is the main process function for the host core, it will process
- * the main machine, such as connect,disconnect, emunation etc.
- * @param [in] pdev device instance
- * @param [in] pstcPortIdentify usb core and phy select
- * @param [in] phost host state set
- * @retval None
- */
-void usb_host_mainprocess(usb_core_instance *pdev, stc_usb_port_identify *pstcPortIdentify, USBH_HOST *phost)
-{
- __IO HOST_STATUS tmp_status;
- tmp_status = HSTATUS_FAIL;
- HOST_HANDLE_STATE tmp_host_state;
-
- if ((host_driver_ifdevconnected(pdev) == 0UL) && (phost->host_state != HOST_IDLE)) {
- if (phost->host_state != HOST_DEV_DISCONNECTED) {
- phost->host_state = HOST_DEV_DISCONNECTED;
- }
- }
-
- if ((host_driver_ifdevconnected(pdev) == 0UL) && (phost->host_state == HOST_IDLE)
- && (host_driver_getvbusdrivestate(pdev) == 0UL)) {
- phost->host_state = HOST_DEV_DISCONNECTED;
- }
-
- tmp_host_state = phost->host_state;
- if (tmp_host_state == HOST_IDLE) {
- if (0U != host_driver_ifdevconnected(pdev)) {
- phost->host_state = HOST_DEV_CONNECTED;
- usb_mdelay(50UL);
- }
- } else if (tmp_host_state == HOST_DEV_CONNECTED) {
-#ifdef MSC_HID_COMPOSITE
- if (host_driver_getcurrentspd(pdev) == 2) {
- host_driver_init(pdev, pstcPortIdentify);
- }
-#endif /* MSC_HID_COMPOSITE */
-
- phost->user_callbk->huser_devattached();
- phost->ctrlparam.hc_num_out = usb_host_distrch(pdev, 0x00U);
- phost->ctrlparam.hc_num_in = usb_host_distrch(pdev, 0x80U);
-
- /* Wait DP DM stable */
- usb_udelay(10UL);
- while (host_driver_getdmdpstate(pdev) == 0UL) {
- usb_mdelay(5UL);
- }
-
- host_driver_portrst(pdev);
- phost->user_callbk->huser_devreset();
- phost->device_prop.devspeed = (uint8_t)host_driver_getcurrentspd(pdev);
- phost->host_state = HOST_ENUM;
- phost->user_callbk->huser_devspddetected(phost->device_prop.devspeed);
- usb_host_chopen(pdev,
- phost->ctrlparam.hc_num_in,
- phost->device_prop.devaddr,
- phost->device_prop.devspeed,
- EP_TYPE_CTRL,
- (uint16_t)phost->ctrlparam.ctrlmaxsize);
- usb_host_chopen(pdev,
- phost->ctrlparam.hc_num_out,
- phost->device_prop.devaddr,
- phost->device_prop.devspeed,
- EP_TYPE_CTRL,
- (uint16_t)phost->ctrlparam.ctrlmaxsize);
- } else if (tmp_host_state == HOST_ENUM) {
- if (usb_host_enumprocess(pdev, phost) == HSTATUS_OK) {
- phost->user_callbk->huser_enumcompl();
- phost->host_state = HOST_USER_INPUT;
- }
- } else if (tmp_host_state == HOST_USER_INPUT) {
- if ((phost->class_callbk->host_class_init(pdev, phost)) == HSTATUS_OK) {
- phost->host_state = HOST_CLASS_REQ;
- }
- } else if (tmp_host_state == HOST_CLASS_REQ) {
- tmp_status = phost->class_callbk->host_class_request(pdev, phost);
- if (tmp_status == HSTATUS_OK) {
- phost->host_state = HOST_CLASS_PROCESS;
- } else {
- usb_host_errorprocess(phost, tmp_status);
- }
- } else if (tmp_host_state == HOST_CLASS_PROCESS) {
- tmp_status = phost->class_callbk->host_class_process(pdev, phost);
- usb_host_errorprocess(phost, tmp_status);
- } else if (tmp_host_state == HOST_CTRL_TRANSMIT) {
- (void)usb_host_ctrlprocess(pdev, phost);
- } else if (tmp_host_state == HOST_ERROR_STATE) {
- usb_host_deinit(pdev, phost);
- phost->user_callbk->huser_deinit();
- phost->class_callbk->host_class_deinit(pdev);
- } else if (tmp_host_state == HOST_DEV_DISCONNECTED) {
- phost->user_callbk->huser_devdisconn();
- usb_host_deinit(pdev, phost);
- phost->user_callbk->huser_deinit();
- phost->class_callbk->host_class_deinit(pdev);
- usb_host_dedistrallch(pdev);
- phost->host_state = HOST_IDLE;
-
- host_driver_init(pdev, pstcPortIdentify);
- } else {
- ;
- }
-}
-
-/**
- * @brief process the status when related error status happens.
- * @param [in] phost host state set
- * @param [in] errType host status
- * @retval None
- */
-void usb_host_errorprocess(USBH_HOST *phost, HOST_STATUS errType)
-{
- switch (errType) {
- case HSTATUS_APP_DEINIT:
- phost->host_state = HOST_ERROR_STATE;
- phost->user_callbk->huser_init();
- break;
- case HSTATUS_SPEED_UNKNOWN:
- case HSTATUS_UNRECOVERED_ERROR:
- phost->user_callbk->huser_unrecoverederror();
- phost->host_state = HOST_ERROR_STATE;
- break;
- default:
- break;
- }
-}
-
-/**
- * @brief this function process all the emunation steps.
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval status
- */
-HOST_STATUS usb_host_enumprocess(usb_core_instance *pdev, USBH_HOST *phost)
-{
- HOST_STATUS tmp_status;
-
- ENUM_HANDLE_STATE tmp_enum_state;
- tmp_status = HSTATUS_BUSY;
- tmp_enum_state = phost->enum_state;
- if (tmp_enum_state == ENUM_IDLE) {
- if (usb_host_getdevdesc(pdev, phost, 8U) == HSTATUS_OK) {
- phost->ctrlparam.ctrlmaxsize = phost->device_prop.devdesc.bMaxPacketSize0;
- host_driver_portrst(pdev);
- phost->enum_state = ENUM_GET_FULL_DEVDESC;
- usb_host_mdfch(pdev,
- phost->ctrlparam.hc_num_out,
- 0U,
- 0U,
- 0U,
- (uint16_t)phost->ctrlparam.ctrlmaxsize);
- usb_host_mdfch(pdev,
- phost->ctrlparam.hc_num_in,
- 0U,
- 0U,
- 0U,
- (uint16_t)phost->ctrlparam.ctrlmaxsize);
- }
- }
- if (tmp_enum_state == ENUM_GET_FULL_DEVDESC) {
- if (usb_host_getdevdesc(pdev, phost, USB_DEVICE_DESC_SIZE) == HSTATUS_OK) {
- phost->user_callbk->huser_devdescavailable(&phost->device_prop.devdesc);
- phost->enum_state = ENUM_SET_DEVADDR;
- }
- }
- if (tmp_enum_state == ENUM_SET_DEVADDR) {
- if (usb_host_setdevaddr(pdev, phost, DEV_ASSIGNED_ADDRESS) == HSTATUS_OK) {
- usb_mdelay(2UL);
- phost->device_prop.devaddr = DEV_ASSIGNED_ADDRESS;
- phost->user_callbk->huser_devaddrdistributed();
- phost->enum_state = ENUM_GET_CFGDESC;
- usb_host_mdfch(pdev,
- phost->ctrlparam.hc_num_in,
- phost->device_prop.devaddr,
- 0U,
- 0U,
- 0U);
-
- usb_host_mdfch(pdev,
- phost->ctrlparam.hc_num_out,
- phost->device_prop.devaddr,
- 0U,
- 0U,
- 0U);
- }
- }
- if (tmp_enum_state == ENUM_GET_CFGDESC) {
- if (usb_host_getcfgdesc(pdev, phost, USB_CONFIGURATION_DESC_SIZE) == HSTATUS_OK) {
- phost->enum_state = ENUM_GET_FULL_CFGDESC;
- }
- }
- if (tmp_enum_state == ENUM_GET_FULL_CFGDESC) {
- if (usb_host_getcfgdesc(pdev, phost, phost->device_prop.devcfgdesc.wTotalLength) == HSTATUS_OK) {
- phost->user_callbk->huser_cfgdescavailable(&phost->device_prop.devcfgdesc,
- phost->device_prop.devitfdesc,
- phost->device_prop.devepdesc[0]);
- phost->enum_state = ENUM_GET_MFCSTRINGDESC;
- }
- }
- if (tmp_enum_state == ENUM_GET_MFCSTRINGDESC) {
- if (phost->device_prop.devdesc.iManufacturer != (uint8_t)0) {
- if (usb_host_getstringdesc(pdev,
- phost,
- phost->device_prop.devdesc.iManufacturer,
- Local_Buffer,
- 0xFFU) == HSTATUS_OK) {
- phost->user_callbk->huser_mfcstring(Local_Buffer);
- phost->enum_state = ENUM_GET_PRODUCT_STRINGDESC;
- }
- } else {
- phost->user_callbk->huser_mfcstring("N/A");
- phost->enum_state = ENUM_GET_PRODUCT_STRINGDESC;
- }
- }
- if (tmp_enum_state == ENUM_GET_PRODUCT_STRINGDESC) {
- if (phost->device_prop.devdesc.iProduct != (uint8_t)0) {
- if (usb_host_getstringdesc(pdev,
- phost,
- phost->device_prop.devdesc.iProduct,
- Local_Buffer,
- 0xFFU) == HSTATUS_OK) {
- phost->user_callbk->huser_productstring(Local_Buffer);
- phost->enum_state = ENUM_GET_SERIALNUM_STRINGDESC;
- }
- } else {
- phost->user_callbk->huser_productstring("N/A");
- phost->enum_state = ENUM_GET_SERIALNUM_STRINGDESC;
- }
- }
- if (tmp_enum_state == ENUM_GET_SERIALNUM_STRINGDESC) {
- if (phost->device_prop.devdesc.iSerialNumber != (uint8_t)0) {
- if (usb_host_getstringdesc(pdev,
- phost,
- phost->device_prop.devdesc.iSerialNumber,
- Local_Buffer,
- 0xFFU) == HSTATUS_OK) {
- phost->user_callbk->huser_serialnum(Local_Buffer);
- phost->enum_state = ENUM_SET_CFG;
- }
- } else {
- phost->user_callbk->huser_serialnum("N/A");
- phost->enum_state = ENUM_SET_CFG;
- }
- }
- if (tmp_enum_state == ENUM_SET_CFG) {
- if (usb_host_setconfig(pdev, phost,
- (uint16_t)phost->device_prop.devcfgdesc.bConfigurationValue) == HSTATUS_OK) {
- phost->enum_state = ENUM_DEV_CFG_OVER;
- }
- }
- if (tmp_enum_state == ENUM_DEV_CFG_OVER) {
- tmp_status = HSTATUS_OK;
- } else {
- ;
- }
- return tmp_status;
-}
-
-/**
- * @brief process the state machine of control transfer
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @retval status
- */
-HOST_STATUS usb_host_ctrlprocess(usb_core_instance *pdev, USBH_HOST *phost)
-{
- uint8_t direction;
- CTRL_HANDLE_STATE tmp_ctrl_state;
- static uint16_t timeout = 0;
- HOST_STATUS status = HSTATUS_OK;
- HOST_CH_XFER_STATE URB_Status;
-
- phost->ctrlparam.ctrl_status = CTRL_START;
- tmp_ctrl_state = phost->ctrlparam.ctrl_state;
-
- if (tmp_ctrl_state == CTRL_SETUP) {
- /* transmit a setup packet to the device */
- usb_host_sendctrlsetup(pdev, phost->ctrlparam.setup.d8, phost->ctrlparam.hc_num_out);
- phost->ctrlparam.ctrl_state = CTRL_SETUP_WAIT;
- timeout = DATA_STAGE_TIMEOUT * 6U;
- phost->ctrlparam.sof_num = (uint16_t)host_driver_getcurrentfrm(pdev);
- } else if (tmp_ctrl_state == CTRL_SETUP_WAIT) {
- URB_Status = host_driver_getxferstate(pdev, phost->ctrlparam.hc_num_out);
- /* case SETUP packet sent successfully */
- if (URB_Status == HOST_CH_XFER_DONE) {
- /* parse the direction of the request from the setup just sent */
- direction = (phost->ctrlparam.setup.b.bmRequestType & USB_REQ_DIR_MASK);
- /* judge if there is a data stage, if wLength is not zero, there may be a in or out
- data stage */
- if (phost->ctrlparam.setup.b.wLength.w != 0U) {
- timeout = DATA_STAGE_TIMEOUT;
- if (direction == USB_D2H) {
- /* Data Direction is IN, device should send data in */
- phost->ctrlparam.ctrl_state = CTRL_DATA_IN;
- } else {
- /* Data Direction is OUT, host will send data out for device */
- phost->ctrlparam.ctrl_state = CTRL_DATA_OUT;
- }
- }
- /* No DATA stage */
- else {
- timeout = NODATA_STAGE_TIMEOUT;
- /* If there is No Data Transfer Stage */
- if (direction == USB_D2H) {
- /* Data Direction is IN */
- phost->ctrlparam.ctrl_state = CTRL_STATUS_OUT;
- } else {
- /* Data Direction is OUT */
- phost->ctrlparam.ctrl_state = CTRL_STATUS_IN;
- }
- }
- /* Set the delay timer to enable timeout for data stage completion */
- phost->ctrlparam.sof_num = (uint16_t)host_driver_getcurrentfrm(pdev);
- } else if (URB_Status == HOST_CH_XFER_ERROR) {
- phost->ctrlparam.ctrl_state = CTRL_ERROR;
- phost->ctrlparam.ctrl_status = CTRL_XACTERR;
- } else if ((host_driver_getcurrentfrm(pdev) - phost->ctrlparam.sof_num) > timeout) {
-#if (LL_PRINT_ENABLE == DDL_ON)
- DDL_Printf("Device not responding\r\n");
-#endif
- } else {
- ;
- }
- } else if (tmp_ctrl_state == CTRL_DATA_IN) {
- /* Issue an IN token */
- usb_host_recvctrldata(pdev, phost->ctrlparam.buff, phost->ctrlparam.length, phost->ctrlparam.hc_num_in);
- phost->ctrlparam.ctrl_state = CTRL_DATA_IN_WAIT;
- } else if (tmp_ctrl_state == CTRL_DATA_IN_WAIT) {
- URB_Status = host_driver_getxferstate(pdev, phost->ctrlparam.hc_num_in);
- /* check is DATA packet transfered successfully */
- if (URB_Status == HOST_CH_XFER_DONE) {
- phost->ctrlparam.ctrl_state = CTRL_STATUS_OUT;
- }
- /* manage error cases*/
- if (URB_Status == HOST_CH_XFER_STALL) {
- /* In stall case, return to previous machine state*/
- phost->host_state = phost->host_state_backup;
- } else if (URB_Status == HOST_CH_XFER_ERROR) {
- /* Device error */
- phost->ctrlparam.ctrl_state = CTRL_ERROR;
- } else if ((host_driver_getcurrentfrm(pdev) - phost->ctrlparam.sof_num) > timeout) {
- /* timeout for IN transfer */
- phost->ctrlparam.ctrl_state = CTRL_ERROR;
- } else {
- ;
- }
- } else if (tmp_ctrl_state == CTRL_DATA_OUT) {
- /* Start DATA out transfer (only one DATA packet)*/
- pdev->host.hc[phost->ctrlparam.hc_num_out].out_toggle = 1;
-
- usb_host_sendctrldata(pdev,
- phost->ctrlparam.buff,
- phost->ctrlparam.length,
- phost->ctrlparam.hc_num_out);
- phost->ctrlparam.ctrl_state = CTRL_DATA_OUT_WAIT;
- } else if (tmp_ctrl_state == CTRL_DATA_OUT_WAIT) {
- URB_Status = host_driver_getxferstate(pdev, phost->ctrlparam.hc_num_out);
- switch (URB_Status) {
- case HOST_CH_XFER_DONE:
- phost->ctrlparam.ctrl_state = CTRL_STATUS_IN;
- break;
- case HOST_CH_XFER_STALL:
- phost->host_state = phost->host_state_backup;
- phost->ctrlparam.ctrl_state = CTRL_STALLED;
- break;
- case HOST_CH_XFER_UNREADY:
- phost->ctrlparam.ctrl_state = CTRL_DATA_OUT;
- break;
- case HOST_CH_XFER_ERROR:
- phost->ctrlparam.ctrl_state = CTRL_ERROR;
- break;
- default:
- break;
- }
- } else if (tmp_ctrl_state == CTRL_STATUS_IN) {
- /* receive a packet with 0 byte */
- usb_host_recvctrldata(pdev, NULL, 0U, phost->ctrlparam.hc_num_in);
- phost->ctrlparam.ctrl_state = CTRL_STATUS_IN_WAIT;
- } else if (tmp_ctrl_state == CTRL_STATUS_IN_WAIT) {
- URB_Status = host_driver_getxferstate(pdev, phost->ctrlparam.hc_num_in);
- if (URB_Status == HOST_CH_XFER_DONE) {
- /* Control transfers completed, Exit the State Machine */
- phost->host_state = phost->host_state_backup;
- phost->ctrlparam.ctrl_state = CTRL_COMPLETE;
- } else if (URB_Status == HOST_CH_XFER_ERROR) {
- phost->ctrlparam.ctrl_state = CTRL_ERROR;
- } else if ((host_driver_getcurrentfrm(pdev) - phost->ctrlparam.sof_num) > timeout) {
- phost->ctrlparam.ctrl_state = CTRL_ERROR;
- } else if (URB_Status == HOST_CH_XFER_STALL) {
- /* Control transfers completed, Exit the State Machine */
- phost->host_state = phost->host_state_backup;
- phost->ctrlparam.ctrl_status = CTRL_STALL;
- status = HSTATUS_UNSUPPORTED;
- } else {
- ;
- }
- } else if (tmp_ctrl_state == CTRL_STATUS_OUT) {
- pdev->host.hc[phost->ctrlparam.hc_num_out].out_toggle ^= 1U;
- usb_host_sendctrldata(pdev, NULL, 0U, phost->ctrlparam.hc_num_out);
- phost->ctrlparam.ctrl_state = CTRL_STATUS_OUT_WAIT;
- } else if (tmp_ctrl_state == CTRL_STATUS_OUT_WAIT) {
- URB_Status = host_driver_getxferstate(pdev, phost->ctrlparam.hc_num_out);
- switch (URB_Status) {
- case HOST_CH_XFER_DONE:
- phost->host_state = phost->host_state_backup;
- phost->ctrlparam.ctrl_state = CTRL_COMPLETE;
- break;
- case HOST_CH_XFER_UNREADY:
- phost->ctrlparam.ctrl_state = CTRL_STATUS_OUT;
- break;
- case HOST_CH_XFER_ERROR:
- phost->ctrlparam.ctrl_state = CTRL_ERROR;
- break;
- default:
- break;
- }
- } else if (tmp_ctrl_state == CTRL_ERROR) {
- if (++ phost->ctrlparam.err_cnt <= HOST_MAX_ERROR_CNT) {
- /* re-start the transmission, starting from SETUP packet */
- phost->ctrlparam.ctrl_state = CTRL_SETUP;
- } else {
- phost->ctrlparam.ctrl_status = CTRL_FAIL;
- phost->host_state = phost->host_state_backup;
-
- status = HSTATUS_FAIL;
- }
- } else {
- ;
- }
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.h
deleted file mode 100644
index 92e0d71c8f..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_core.h
- * @brief header file for the usb_host_core.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2022-06-30 CDT Add USB core ID select function
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_HOST_CORE_H__
-#define __USB_HOST_CORE_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_def.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CORE
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-/* USBH_CORE_Exported_Defines */
-#define MSC_CLASS (0x08U)
-#define HID_CLASS (0x03U)
-#define MSC_PROTOCOL (0x50U)
-#define CBI_PROTOCOL (0x01U)
-
-#define DEV_DEFAULT_ADDRESS (0U)
-#define DEV_ASSIGNED_ADDRESS (1U)
-
-#define HOST_MAX_ERROR_CNT (2U)
-
-#define ENUM_LOCAL_BUF (256U)
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-extern void usb_host_init(usb_core_instance *pdev,
- stc_usb_port_identify *pstcPortIdentify,
- USBH_HOST *phost,
- usb_host_class_callback_func *class_cbk,
- usb_host_user_callback_func *user_cbk);
-extern void usb_host_deinit(usb_core_instance *pdev, USBH_HOST *phost);
-extern void usb_host_mainprocess(usb_core_instance *pdev, stc_usb_port_identify *pstcPortIdentify, USBH_HOST *phost);
-extern void usb_host_errorprocess(USBH_HOST *phost, HOST_STATUS errType);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_HOST_CORE_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.c
deleted file mode 100644
index a777db28ee..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.c
+++ /dev/null
@@ -1,319 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_ctrltrans.c
- * @brief This file handles the issuing of the USB transactions
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_ctrltrans.h"
-#include "usb_host_driver.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CORE
- * @{
- */
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-void usb_host_submitsetupreq(USBH_HOST *phost, uint8_t *buff, uint16_t length);
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-/**
- * @brief Start a setup transfer by changing the state-machine and
- * initializing the required variables needed for the Control Transfer
- * @param [in] phost host state set
- * @param [in] buff data buffer used for setup request
- * @param [in] length data length in byte
- * @retval status
- */
-void usb_host_submitsetupreq(USBH_HOST *phost, uint8_t *buff, uint16_t length)
-{
- /* Save Global State */
- phost->host_state_backup = phost->host_state;
- /* Prepare the Transactions */
- phost->host_state = HOST_CTRL_TRANSMIT;
- phost->ctrlparam.buff = buff;
- phost->ctrlparam.length = length;
- phost->ctrlparam.ctrl_state = CTRL_SETUP;
-}
-
-/**
- * @brief send a control request and update the status after the request sent.
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @param [in] buff data buffer whose data will be sent in the control pipe.
- * @param [in] length length of the data sent.
- * @retval status
- */
-HOST_STATUS usb_host_ctrlreq(usb_core_instance *pdev,
- USBH_HOST *phost,
- uint8_t *buff,
- uint16_t length)
-{
- HOST_STATUS status;
- REQ_HANDLE_STATE tmp_req_state;
- (void)(pdev);
- status = HSTATUS_BUSY;
- tmp_req_state = phost->req_state;
- if (tmp_req_state == REQ_CMD_TX) {
- /* prepare a setup packet for transferring */
- usb_host_submitsetupreq(phost, buff, length);
- /* update the request state */
- phost->req_state = REQ_CMD_WAIT;
- /* The status would be returned in this function */
- status = HSTATUS_BUSY;
- } else if (tmp_req_state == REQ_CMD_WAIT) {
- switch (phost->ctrlparam.ctrl_state) {
- case CTRL_COMPLETE:
- /* Commands have been successfully sent and Responses have been Received */
- phost->req_state = REQ_CMD_TX;
- /* update the control state */
- phost->ctrlparam.ctrl_state = CTRL_IDLE;
- status = HSTATUS_OK;
- break;
- case CTRL_ERROR:
- /* fail transfer */
- phost->req_state = REQ_CMD_TX;
- status = HSTATUS_FAIL;
- break;
- case CTRL_STALLED:
- /* Commands have been successfully sent and Responses have been Received */
- phost->req_state = REQ_CMD_TX;
- status = HSTATUS_UNSUPPORTED;
- break;
- default:
- break;
- }
- } else {
- ;
- }
- return status;
-}
-
-/**
- * @brief sends a setup packet to the control EP of the USB device
- * @param [in] pdev device instance
- * @param [in] buff data buffer whose data will be sent in the control pipe to the control EP of the device.
- * @param [in] hc_num host channel index
- * @retval None
- */
-void usb_host_sendctrlsetup(usb_core_instance *pdev, uint8_t *buff, uint8_t hc_num)
-{
- pdev->host.hc[hc_num].is_epin = 0U;
- pdev->host.hc[hc_num].pid_type = PID_SETUP;
- pdev->host.hc[hc_num].xfer_buff = buff;
- pdev->host.hc[hc_num].xfer_len = 8;
- (void)host_driver_submitrequest(pdev, hc_num);
-}
-
-/**
- * @brief sends a data packet to the USB device
- * @param [in] pdev device instance
- * @param [in] buff data buffer whose data will be sent to the USB device
- * @param [in] length the data length in byte that would be sent
- * @param [in] hc_num host channel index
- * @retval None
- */
-void usb_host_sendctrldata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num)
-{
- pdev->host.hc[hc_num].is_epin = 0;
- pdev->host.hc[hc_num].xfer_buff = buff;
- pdev->host.hc[hc_num].xfer_len = length;
- if (length == 0U) {
- /* For Status OUT stage, Length==0, Status Out PID = 1 always */
- pdev->host.hc[hc_num].out_toggle = 1;
- }
- /* Set the Data Toggle bit */
- if (pdev->host.hc[hc_num].out_toggle == 0U) {
- pdev->host.hc[hc_num].pid_type = PID_DATA0;
- } else {
- pdev->host.hc[hc_num].pid_type = PID_DATA1 ;
- }
- (void)host_driver_submitrequest(pdev, hc_num);
-}
-
-/**
- * @brief Receives the response data to the setup packet
- * @param [in] pdev device instance
- * @param [in] buff data buffer when received data.
- * @param [in] length the length data in byte have received.
- * @param [in] hc_num host channel index
- * @retval None
- */
-void usb_host_recvctrldata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num)
-{
- pdev->host.hc[hc_num].is_epin = (uint8_t)1;
- pdev->host.hc[hc_num].pid_type = PID_DATA1;
- pdev->host.hc[hc_num].xfer_buff = buff;
- pdev->host.hc[hc_num].xfer_len = length;
-
- (void)host_driver_submitrequest(pdev, hc_num);
-}
-
-/**
- * @brief sent the bulk packet to the device
- * @param [in] pdev device instance
- * @param [in] buff data buffer whose data will be sent
- * @param [in] length data length in byte
- * @param [in] hc_num host channel index
- * @retval None
- */
-void usb_host_sendbulkdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num)
-{
- pdev->host.hc[hc_num].is_epin = 0;
- pdev->host.hc[hc_num].xfer_buff = buff;
- pdev->host.hc[hc_num].xfer_len = length;
- /* Set the Data Toggle bit */
- if (pdev->host.hc[hc_num].out_toggle == 0U) {
- pdev->host.hc[hc_num].pid_type = PID_DATA0;
- } else {
- pdev->host.hc[hc_num].pid_type = PID_DATA1 ;
- }
-
- (void)host_driver_submitrequest(pdev, hc_num);
-}
-
-/**
- * @brief receives bulk packet from device
- * @param [in] pdev device instance
- * @param [in] buff buffer to save the data received from the device
- * @param [in] length data length in byte
- * @param [in] hc_num host channel index
- * @retval status
- */
-void usb_host_recvbulkdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num)
-{
- pdev->host.hc[hc_num].is_epin = (uint8_t)1;
- pdev->host.hc[hc_num].xfer_buff = buff;
- pdev->host.hc[hc_num].xfer_len = length;
-
- if (pdev->host.hc[hc_num].in_toggle == (uint8_t)0) {
- pdev->host.hc[hc_num].pid_type = PID_DATA0;
- } else {
- pdev->host.hc[hc_num].pid_type = PID_DATA1;
- }
-
- (void)host_driver_submitrequest(pdev, hc_num);
-}
-
-/**
- * @brief receives the device response to the Interrupt IN token
- * @param [in] pdev device instance
- * @param [in] buff buffer to save the data received from the device
- * @param [in] length data length in byte
- * @param [in] hc_num host channel index
- * @retval None
- */
-void usb_host_recvintdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num)
-{
- pdev->host.hc[hc_num].is_epin = (uint8_t)1;
- pdev->host.hc[hc_num].xfer_buff = buff;
- pdev->host.hc[hc_num].xfer_len = length;
- if (pdev->host.hc[hc_num].in_toggle == (uint8_t)0) {
- pdev->host.hc[hc_num].pid_type = PID_DATA0;
- } else {
- pdev->host.hc[hc_num].pid_type = PID_DATA1;
- }
- /* toggle the DATA PID */
- pdev->host.hc[hc_num].in_toggle ^= (uint8_t)1;
- (void)host_driver_submitrequest(pdev, hc_num);
-}
-
-/**
- * @brief send the data on Interrupt OUT Endpoint
- * @param [in] pdev device instance
- * @param [in] buff data buffer whose data will be sent
- * @param [in] length data length in byte
- * @param [in] hc_num host channel index
- * @retval None
- */
-void usb_host_sentintdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num)
-{
- pdev->host.hc[hc_num].is_epin = (uint8_t)0;
- pdev->host.hc[hc_num].xfer_buff = buff;
- pdev->host.hc[hc_num].xfer_len = length;
-
- if (pdev->host.hc[hc_num].in_toggle == (uint8_t)0) {
- pdev->host.hc[hc_num].pid_type = PID_DATA0;
- } else {
- pdev->host.hc[hc_num].pid_type = PID_DATA1;
- }
-
- pdev->host.hc[hc_num].in_toggle ^= (uint8_t)1;
- (void)host_driver_submitrequest(pdev, hc_num);
-}
-
-/**
- * @brief receives the Device Response to the Isochronous IN token
- * @param [in] pdev device instance
- * @param [in] buff buffer to save the data received from the device
- * @param [in] length data length in byte
- * @param [in] hc_num host channel index
- * @retval None
- */
-void usb_host_recvisocdata(usb_core_instance *pdev, uint8_t *buff, uint32_t length, uint8_t hc_num)
-{
- pdev->host.hc[hc_num].is_epin = (uint8_t)1;
- pdev->host.hc[hc_num].xfer_buff = buff;
- pdev->host.hc[hc_num].xfer_len = length;
- pdev->host.hc[hc_num].pid_type = PID_DATA0;
-
- (void)host_driver_submitrequest(pdev, hc_num);
-}
-
-/**
- * @brief Sends the data through Isochronous OUT Endpoint
- * @param [in] pdev device instance
- * @param [in] buff data buffer whose data will be sent
- * @param [in] length data length in byte
- * @param [in] hc_num host channel index
- * @retval None
- */
-void usb_host_sendisocdata(usb_core_instance *pdev, uint8_t *buff, uint32_t length, uint8_t hc_num)
-{
- pdev->host.hc[hc_num].is_epin = (uint8_t)0;
- pdev->host.hc[hc_num].xfer_buff = buff;
- pdev->host.hc[hc_num].xfer_len = length;
- pdev->host.hc[hc_num].pid_type = PID_DATA0;
- (void)host_driver_submitrequest(pdev, hc_num);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************************************************************************
- * EOF (not truncated)
- *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.h
deleted file mode 100644
index f7a50f97a8..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_ctrltrans.h
- * @brief header file for the usb_host_ctrltrans.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_HOST_CTRLTRANS_H__
-#define __USB_HOST_CTRLTRANS_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_def.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CORE
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-extern void usb_host_sendctrlsetup(usb_core_instance *pdev, uint8_t *buff, uint8_t hc_num);
-extern void usb_host_sendctrldata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num);
-extern void usb_host_recvctrldata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num);
-extern void usb_host_recvbulkdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num);
-extern void usb_host_sendbulkdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num);
-extern void usb_host_recvintdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num);
-extern void usb_host_sentintdata(usb_core_instance *pdev, uint8_t *buff, uint16_t length, uint8_t hc_num);
-extern HOST_STATUS usb_host_ctrlreq(usb_core_instance *pdev, USBH_HOST *phost, uint8_t *buff, uint16_t length);
-extern void usb_host_recvisocdata(usb_core_instance *pdev, uint8_t *buff, uint32_t length, uint8_t hc_num);
-extern void usb_host_sendisocdata(usb_core_instance *pdev, uint8_t *buff, uint32_t length, uint8_t hc_num);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_HOST_CTRLTRANS_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_def.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_def.h
deleted file mode 100644
index a8037f78a4..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_def.h
+++ /dev/null
@@ -1,430 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_def.h
- * @brief Definitions used in the USB host library
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_HOST_DEF_H__
-#define __USB_HOST_DEF_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include
-#include "usb_app_conf.h"
-#include "usb_lib.h"
-#include "hc32_ll.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CORE
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-/* This Union is copied from usb_core.h */
-typedef union {
- uint16_t w;
- struct BW {
- uint8_t msb;
- uint8_t lsb;
- }
- bw;
-} uint16_t_uint8_t;
-/* standard setup packet defination */
-typedef union {
- uint8_t d8[8];
- struct _SetupPkt_Struc {
- uint8_t bmRequestType;
- uint8_t bRequest;
- uint16_t_uint8_t wValue;
- uint16_t_uint8_t wIndex;
- uint16_t_uint8_t wLength;
- } b;
-} usb_setup_typedef;
-
-typedef struct {
- uint8_t bLength;
- uint8_t bDescriptorType;
-} USB_HOST_DescHeader_TypeDef;
-
-/* Standard Device Descriptor */
-typedef struct {
- uint8_t bLength; /* Size of this descriptor in bytes */
- uint8_t bDescriptorType; /* Device descriptor type */
- uint16_t bcdUSB; /* USB Specification Release Numbrer in Binary-Coded Decimal(i.e.,2.10 is 210H) */
- uint8_t bDeviceClass; /* Class code(assigned by the USB-IF) */
- uint8_t bDeviceSubClass; /* Subclass code(assigned by the USB-IF) this code is qualified by the value of the \
- bDeviceClass field. */
- uint8_t bDeviceProtocol; /* Protocol code(assigned by the USB-IF), this code is qualified by the value of the \
- bDeviceClass and the bDeviceSubClass fields. */
- uint8_t bMaxPacketSize0; /* Maximum packet size for EP0 */
- uint16_t idVendor; /* Vendor ID (assigned by the USB-IF) */
- uint16_t idProduct; /* Product ID (assigned by manufacturer) */
- uint16_t bcdDevice; /* Device Release Number in binary-coded decimal */
- uint8_t iManufacturer; /* Index of string descriptor describing manufacturer */
- uint8_t iProduct; /* Index of string descriptor describing product */
- uint8_t iSerialNumber; /* Index of string descriptor describing the device's serial number */
- uint8_t bNumConfigurations; /* Number of possible configurations */
-} usb_host_devdesc_typedef;
-
-/* Standard Configuration Descriptor */
-typedef struct {
- uint8_t bLength; /* Size of this descriptor in bytes */
- uint8_t bDescriptorType; /* CONFIGURATION descriptor type */
- uint16_t wTotalLength; /* Total length of data returned for this configuration */
- uint8_t bNumInterfaces; /* Number of interfaces supported by this configuration */
- uint8_t bConfigurationValue; /* Value to use as an argument to the SetConfiguration() request to select this configuration */
- uint8_t iConfiguration; /* Index of string descriptor describing this configuration */
- uint8_t bmAttributes; /* Configuration characteristics: D7:Reserved(set to one) D6:Self-powered D5:Remote Wakeup D4..0 Reserved(set to zero) */
- uint8_t bMaxPower; /* Maximum power consumption of the device from the bus in this specific configuration when the device is fully operational */
-} usb_host_cfgdesc_typedef;
-
-typedef struct {
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint16_t bcdHID; /* indicates what endpoint this descriptor is describing */
- uint8_t bCountryCode; /* specifies the transfer type. */
- uint8_t bNumDescriptors; /* specifies the transfer type. */
- uint8_t bReportDescriptorType; /* Maximum Packet Size this endpoint is capable of sending or receiving */
- uint16_t wItemLength; /* is used to specify the polling interval of certain transfers. */
-} USB_HOST_HIDDesc_TypeDef;
-
-/* Standard Interface Descriptor */
-typedef struct {
- uint8_t bLength; /* Size of this descriptor in bytes */
- uint8_t bDescriptorType; /* INTERFACE Descriptor Type */
- uint8_t bInterfaceNumber; /* Number of this interface */
- uint8_t bAlternateSetting; /* Value used to select this alternate setting for the interface identifiled in the \
- prior field */
- uint8_t bNumEndpoints; /* Number of Endpoints used by this interface */
- uint8_t bInterfaceClass; /* Class code (assigned by the USB-IF) */
- uint8_t bInterfaceSubClass; /* Subclass code (assigned by the USB-IF) */
- uint8_t bInterfaceProtocol; /* Protocol code (assigned by the USB) */
- uint8_t iInterface; /* Index of string descriptor describing this interface */
-} usb_host_itfdesc_typedef;
-
-/* Standard Endpoint Descriptor */
-typedef struct {
- uint8_t bLength; /* Size of this descriptor in bytes */
- uint8_t bDescriptorType; /* ENDPOINT descriptor type */
- uint8_t bEndpointAddress; /* The address of the endpoint on the device described by this descriptor */
- uint8_t bmAttributes; /* refer to the related standard of USB 2.0 */
- uint16_t wMaxPacketSize; /* Maximum Packet Size this endpoint is capable of sending or receiving when this \
- configuration is selected */
- uint8_t bInterval; /* Interval for servicing the endpoint for data transfers */
-} USB_HOST_EPDesc_TypeDef;
-
-/* USBH_CORE_Exported_Types */
-/* Host status */
-typedef enum {
- HSTATUS_OK = 0,
- HSTATUS_BUSY,
- HSTATUS_FAIL,
- HSTATUS_UNSUPPORTED,
- HSTATUS_UNRECOVERED_ERROR,
- HSTATUS_SPEED_UNKNOWN,
- HSTATUS_APP_DEINIT
-} HOST_STATUS;
-
-/* states about the handle stages on the host side */
-typedef enum {
- HOST_IDLE = 0,
- HOST_DEV_CONNECTED,
- HOST_DEV_DISCONNECTED,
- HOST_GET_DEVSPEED,
- HOST_ENUM,
- HOST_CLASS_REQ,
- HOST_CLASS_PROCESS,
- HOST_CTRL_TRANSMIT,
- HOST_USER_INPUT,
- HOST_SUSPENDED,
- HOST_ERROR_STATE
-} HOST_HANDLE_STATE;
-
-/* states of the enumeration stage on the host side */
-typedef enum {
- ENUM_IDLE = 0,
- ENUM_GET_FULL_DEVDESC,
- ENUM_SET_DEVADDR,
- ENUM_GET_CFGDESC,
- ENUM_GET_FULL_CFGDESC,
- ENUM_GET_MFCSTRINGDESC,
- ENUM_GET_PRODUCT_STRINGDESC,
- ENUM_GET_SERIALNUM_STRINGDESC,
- ENUM_SET_CFG,
- ENUM_DEV_CFG_OVER
-} ENUM_HANDLE_STATE;
-
-/* states of the control stages on the host side */
-typedef enum {
- CTRL_IDLE = 0,
- CTRL_SETUP,
- CTRL_SETUP_WAIT,
- CTRL_DATA_IN,
- CTRL_DATA_IN_WAIT,
- CTRL_DATA_OUT,
- CTRL_DATA_OUT_WAIT,
- CTRL_STATUS_IN,
- CTRL_STATUS_IN_WAIT,
- CTRL_STATUS_OUT,
- CTRL_STATUS_OUT_WAIT,
- CTRL_ERROR,
- CTRL_STALLED,
- CTRL_COMPLETE
-} CTRL_HANDLE_STATE;
-
-/* Following states are state machine for the request transferring */
-typedef enum {
- REQ_CMD_IDLE = 0,
- REQ_CMD_TX,
- REQ_CMD_WAIT
-} REQ_HANDLE_STATE;
-
-typedef enum {
- USER_HAVE_RESP = 0,
- USER_NONE_RESP
-} HOST_USER_STATUS;
-
-typedef struct {
- uint8_t hc_num_in; /* channel number for the IN EP */
- uint8_t hc_num_out; /* channel number for the OUT EP */
- uint8_t ctrlmaxsize; /* the max size of EP0 parsed from the device descriptor */
- uint8_t err_cnt; /* the error counter */
- uint16_t sof_num; /* the frame number for sof packet */
- uint16_t length; /* length of data in byte */
- uint8_t *buff; /* data buffer */
- CTRL_HANDLE_STATUS ctrl_status; /* status of control pipe */
- CTRL_HANDLE_STATE ctrl_state; /* running state of the control transfer */
- uint8_t Rev[2];
- usb_setup_typedef setup; /* setup packet */
-} usb_host_ctrl_param;
-
-/* Device information parsed from the related descriptors requested from the connected device
- the following data are all parsed from the data sent by the connnected device */
-typedef struct {
- uint8_t devaddr; /* the address of the connected device */
- uint8_t devspeed; /* the core speed of the connected device */
- usb_host_devdesc_typedef devdesc; /* the device descriptor parsed from the data sent by device */
- usb_host_cfgdesc_typedef devcfgdesc; /* the device configuration descriptor parsed from the data sent by device */
- usb_host_itfdesc_typedef devitfdesc[USBH_MAX_NUM_INTERFACES]; /* the interface descritpor */
- USB_HOST_EPDesc_TypeDef devepdesc[USBH_MAX_NUM_INTERFACES][USBH_MAX_NUM_ENDPOINTS]; /* the endpoint descriptor */
- USB_HOST_HIDDesc_TypeDef hiddesc; /* the hid descriptor */
-} usb_host_devinformation;
-
-typedef struct {
- HOST_STATUS(*host_class_init)(usb_core_instance *pdev, void *phost);
- void (*host_class_deinit)(usb_core_instance *pdev);
- HOST_STATUS(*host_class_request)(usb_core_instance *pdev, void *phost);
- HOST_STATUS(*host_class_process)(usb_core_instance *pdev, void *phost);
-} usb_host_class_callback_func;
-
-typedef struct {
- void (*huser_init)(void);
- void (*huser_deinit)(void);
- void (*huser_devattached)(void);
- void (*huser_devreset)(void);
- void (*huser_devdisconn)(void);
- void (*huser_overcurrent)(void);
- void (*huser_devspddetected)(uint8_t DeviceSpeed);
- void (*huser_devdescavailable)(void *);
- void (*huser_devaddrdistributed)(void);
- void (*huser_cfgdescavailable)(usb_host_cfgdesc_typedef *,
- usb_host_itfdesc_typedef *,
- USB_HOST_EPDesc_TypeDef *);
- /* Configuration Descriptor available */
- void (*huser_mfcstring)(void *);
- void (*huser_productstring)(void *);
- void (*huser_serialnum)(void *);
- void (*huser_enumcompl)(void);
- HOST_USER_STATUS(*huser_userinput)(void);
- int (*huser_application)(void);
- void (*huser_devunsupported)(void);
- void (*huser_unrecoverederror)(void);
-} usb_host_user_callback_func;
-
-typedef struct {
- /* states for the host, enumeration, request */
- REQ_HANDLE_STATE req_state; /* value of state machine about the request */
- ENUM_HANDLE_STATE enum_state; /* state machine while enumerating */
- HOST_HANDLE_STATE host_state_backup; /* backup value of state machine about the host */
- HOST_HANDLE_STATE host_state; /* value of state machine about the host */
- /* control informations */
- usb_host_ctrl_param ctrlparam; /* values about the control parameters */
- /* device information parsed from the descriptors from the device */
- usb_host_devinformation device_prop;
- /* functions: call back functions for the class and user */
- usb_host_class_callback_func *class_callbk;
- usb_host_user_callback_func *user_callbk;
-} USBH_HOST;
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-#ifndef FALSE
-#define FALSE 0U
-#endif
-
-#ifndef TRUE
-#define TRUE 1U
-#endif
-
-/* Get a 16bits data from buffer in little end mode. */
-#define SMALL_END(addr) (((uint16_t)(*((uint8_t *)(addr)))) + (((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U))
-
-#define USB_LEN_CFG_DESC (0x09U)
-
-/* bmRequestType
-D7: Data transfer direction
- 0 = Host-to-device
- 1 = Device-to-host
-*/
-#define USB_REQ_DIR_MASK (0x80U)
-#define USB_H2D (0x00U)
-#define USB_D2H (0x80U)
-
-/* bmRequestType
-D6...5: Type
- 0 = Standard
- 1 = Class
- 2 = Vendor
- 3 = Reserved
-*/
-#define USB_REQ_TYPE_STANDARD (0x00U)
-#define USB_REQ_TYPE_CLASS (0x20U)
-#define USB_REQ_TYPE_VENDOR (0x40U)
-#define USB_REQ_TYPE_RESERVED (0x60U)
-
-/* bmRequestType
-D4...0: Recipient
- 0 = Device
- 1 = Interface
- 2 = Endpoint
- 3 = Other
- 4...31 = Reserved
-*/
-#define USB_REQ_RECIPIENT_DEVICE (0x00U)
-#define USB_REQ_RECIPIENT_INTERFACE (0x01U)
-#define USB_REQ_RECIPIENT_ENDPOINT (0x02U)
-#define USB_REQ_RECIPIENT_OTHER (0x03U)
-
-/* Table 9-4. Standard Request Codes [USB Specification] */
-/* bRequest Value */
-#define USB_REQ_GET_STATUS (0x00U)
-#define USB_REQ_CLEAR_FEATURE (0x01U)
-#define USB_REQ_SET_FEATURE (0x03U)
-#define USB_REQ_SET_ADDRESS (0x05U)
-#define USB_REQ_GET_DESCRIPTOR (0x06U)
-#define USB_REQ_SET_DESCRIPTOR (0x07U)
-#define USB_REQ_GET_CONFIGURATION (0x08U)
-#define USB_REQ_SET_CONFIGURATION (0x09U)
-#define USB_REQ_GET_INTERFACE (0x0AU)
-#define USB_REQ_SET_INTERFACE (0x0BU)
-#define USB_REQ_SYNCH_FRAME (0x0Cu)
-
-/* Table 9-5. Descriptor Types [USB Specification] */
-/* Descriptor Types Value */
-#define USB_DESC_TYPE_DEVICE (1U)
-#define USB_DESC_TYPE_CONFIGURATION (2U)
-#define USB_DESC_TYPE_STRING (3U)
-#define USB_DESC_TYPE_INTERFACE (4U)
-#define USB_DESC_TYPE_ENDPOINT (5U)
-#define USB_DESC_TYPE_DEVICE_QUALIFIER (6U)
-#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION (7U)
-#define USB_DESC_TYPE_INTERFACE_POWER (8U)
-#define USB_DESC_TYPE_HID (0x21U)
-#define USB_DESC_TYPE_HID_REPORT (0x22U)
-
-#define USB_DEVICE_DESC_SIZE (18U)
-#define USB_CONFIGURATION_DESC_SIZE (9U)
-#define USB_HID_DESC_SIZE (9U)
-#define USB_INTERFACE_DESC_SIZE (9U)
-#define USB_ENDPOINT_DESC_SIZE (7U)
-
-/* Descriptor Type and Descriptor Index */
-/* Use the following values when calling the function usb_host_getdesc */
-#define USB_DESC_DEVICE (((uint16_t)USB_DESC_TYPE_DEVICE << 8U) & 0xFF00U)
-#define USB_DESC_CONFIGURATION (((uint16_t)USB_DESC_TYPE_CONFIGURATION << 8U) & 0xFF00U)
-#define USB_DESC_STRING (((uint16_t)USB_DESC_TYPE_STRING << 8U) & 0xFF00U)
-#define USB_DESC_INTERFACE (((uint16_t)USB_DESC_TYPE_INTERFACE << 8U) & 0xFF00U)
-#define USB_DESC_ENDPOINT (((uint16_t)USB_DESC_TYPE_INTERFACE << 8U) & 0xFF00U)
-#define USB_DESC_DEVICE_QUALIFIER (((uint16_t)USB_DESC_TYPE_DEVICE_QUALIFIER << 8U) & 0xFF00U)
-#define USB_DESC_OTHER_SPEED_CONFIGURATION (((uint16_t)USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION << 8U) & 0xFF00U)
-#define USB_DESC_INTERFACE_POWER (((uint16_t)USB_DESC_TYPE_INTERFACE_POWER << 8U) & 0xFF00U)
-#define USB_DESC_HID_REPORT (((uint16_t)USB_DESC_TYPE_HID_REPORT << 8U) & 0xFF00U)
-#define USB_DESC_HID (((uint16_t)USB_DESC_TYPE_HID << 8U) & 0xFF00U)
-
-#define USB_EP_DIR_OUT (0x00U)
-#define USB_EP_DIR_IN (0x80U)
-#define USB_EP_DIR_MSK (0x80U)
-
-/* supported classes */
-#define USB_MSC_CLASS (0x08U)
-#define USB_HID_CLASS (0x03U)
-
-/* Interface Descriptor field values for HID Boot Protocol */
-#define HID_BOOT_CODE (0x01U)
-#define HID_KEYBRD_BOOT_CODE (0x01U)
-#define HID_MOUSE_BOOT_CODE (0x02U)
-
-/* As per USB specs 9.2.6.4 :Standard request with data request timeout: 5sec
- Standard request with no data stage timeout : 50ms */
-#define DATA_STAGE_TIMEOUT (5000U)
-#define NODATA_STAGE_TIMEOUT (50U)
-
-/* Macro definations for host mode */
-#define PID_DATA0 (0U)
-#define PID_DATA2 (1U)
-#define PID_DATA1 (2U)
-#define PID_SETUP (3U)
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_HOST_DEF_H__ */
-
-/******************************************************************************
- * EOF (not truncated)
- *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.c
deleted file mode 100644
index 52cbc53876..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.c
+++ /dev/null
@@ -1,235 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_driver.c
- * @brief Host Interface Layer.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2022-06-30 CDT Add USB core ID select function
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_driver.h"
-#include "usb_bsp.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CORE
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-/**
- * @brief Initialize the driver for the host mode
- * @param [in] pdev device instance
- * @param [in] pstcPortIdentify usb core and phy select
- * @retval None
- */
-void host_driver_init(usb_core_instance *pdev, stc_usb_port_identify *pstcPortIdentify)
-{
- uint8_t i;
-
- pdev->host.is_dev_connect = 0U;
- for (i = 0U; i < USB_MAX_TX_FIFOS; i++) {
- pdev->host.ErrCnt[i] = 0U;
- pdev->host.XferCnt[i] = 0U;
- pdev->host.HC_Status[i] = HOST_CH_IDLE;
- }
- pdev->host.hc[0].max_packet = 8U;
-
- usb_setregaddr(&pdev->regs, pstcPortIdentify, &pdev->basic_cfgs);
-
- usb_gintdis(&pdev->regs);
- usb_initusbcore(&pdev->regs, &pdev->basic_cfgs);
- /* force to work in host mode*/
- usb_modeset(&pdev->regs, HOST_MODE);
- /* configure charge pump IO */
- usb_bsp_cfgvbus(pdev);
- /* enable or disable the external charge pump */
- usb_bsp_drivevbus(pdev, 1U);
- usb_vbusctrl(&pdev->regs, 1U);
- usb_mdelay(50UL);
-
- usb_hostmodeinit(&pdev->regs, &pdev->basic_cfgs);
- usb_ginten(&pdev->regs);
-}
-
-/**
- * @brief get current speed when in host mode
- * @param [in] pdev device instance
- * @retval current speed
- */
-uint32_t host_driver_getcurrentspd(usb_core_instance *pdev)
-{
- uint32_t u32hppt;
- u32hppt = READ_REG32(*pdev->regs.HPRT);
- return ((u32hppt & USBFS_HPRT_PSPD) >> USBFS_HPRT_PSPD_POS);
-}
-
-/**
- * @brief get current DM DP state
- * @param [in] pdev device instance
- * @retval DM DP state
- * 0x00 DM L, DP L
- * 0x01 DM L, DP H
- * 0x02 DM H, DP L
- * 0x03 DM H, DP H
- */
-uint32_t host_driver_getdmdpstate(usb_core_instance *pdev)
-{
- uint32_t u32hppt;
- u32hppt = READ_REG32(*pdev->regs.HPRT);
- return ((u32hppt & USBFS_HPRT_PLSTS) >> USBFS_HPRT_PLSTS_POS);
-}
-
-/**
- * @brief get vbus drive state
- * @param [in] pdev device instance
- * @retval vbus driver state
- * 0x00 vbus driver disable
- * 0x01 vbus driver enable
- */
-uint32_t host_driver_getvbusdrivestate(usb_core_instance *pdev)
-{
- uint32_t u32hppt;
- u32hppt = READ_REG32(*pdev->regs.HPRT);
- return ((u32hppt & USBFS_HPRT_PWPR) >> USBFS_HPRT_PWPR_POS);
-}
-
-/**
- * @brief reset the port
- * @param [in] pdev device instance
- * @retval None
- */
-void host_driver_portrst(usb_core_instance *pdev)
-{
- usb_hprtrst(&pdev->regs);
-}
-
-/**
- * @brief get the connected status of the device
- * @param [in] pdev device instance
- * @retval 1 connected or 0 disconnected
- */
-uint32_t host_driver_ifdevconnected(usb_core_instance *pdev)
-{
- return (pdev->host.is_dev_connect);
-}
-
-/**
- * @brief gets the frame number for of sof packet
- * @param [in] pdev device instance
- * @retval number of frame
- */
-uint32_t host_driver_getcurrentfrm(usb_core_instance *pdev)
-{
- return (READ_REG32(pdev->regs.HREGS->HFNUM) & 0xFFFFUL) ;
-}
-
-/**
- * @brief gets the last xfer state
- * @param [in] pdev device instance
- * @param [in] ch_num channel number
- * @retval HOST_CH_XFER_STATE
- */
-HOST_CH_XFER_STATE host_driver_getxferstate(usb_core_instance *pdev, uint8_t ch_num)
-{
- return pdev->host.URB_State[ch_num] ;
-}
-
-/**
- * @brief gets the xfer count
- * @param [in] pdev device instance
- * @param [in] ch_num channel number
- * @retval number of data trandmitted in bytes
- */
-uint32_t host_driver_getxfercnt(usb_core_instance *pdev, uint8_t ch_num)
-{
- return pdev->host.XferCnt[ch_num] ;
-}
-
-/**
- * @brief gets the host channel status
- * @param [in] pdev device instance
- * @param [in] ch_num channel number
- * @retval HOST_CH_STATUS
- */
-HOST_CH_STATUS host_driver_gethostchstate(usb_core_instance *pdev, uint8_t ch_num)
-{
- return pdev->host.HC_Status[ch_num] ;
-}
-
-/**
- * @brief prepare a host channel and start a transfer
- * @param [in] pdev device instance
- * @param [in] hc_num channel number
- * @retval status
- */
-uint32_t host_driver_hostch_init(usb_core_instance *pdev, uint8_t hc_num)
-{
- return usb_inithch(&pdev->regs, hc_num, &pdev->host.hc[hc_num], pdev->basic_cfgs.dmaen);
-}
-
-/**
- * @brief prepare a host channel and start a transfer
- * @param [in] pdev device instance
- * @param [in] hc_num channel number
- * @retval status
- */
-uint32_t host_driver_submitrequest(usb_core_instance *pdev, uint8_t hc_num)
-{
- pdev->host.URB_State[hc_num] = HOST_CH_XFER_IDLE;
- pdev->host.hc[hc_num].xfer_count = 0U ;
- return usb_hchtransbegin(&pdev->regs, hc_num, &pdev->host.hc[hc_num], pdev->basic_cfgs.dmaen);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.h
deleted file mode 100644
index a6d658b073..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_driver.h
- * @brief Head file for usb_host_driver.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2022-06-30 CDT Add USB core ID select function
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_HOST_DRIVER_H__
-#define __USB_HOST_DRIVER_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_def.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CORE
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-extern void host_driver_init(usb_core_instance *pdev, stc_usb_port_identify *pstcPortIdentify);
-extern uint32_t host_driver_hostch_init(usb_core_instance *pdev, uint8_t hc_num);
-extern uint32_t host_driver_submitrequest(usb_core_instance *pdev, uint8_t hc_num);
-extern uint32_t host_driver_getcurrentspd(usb_core_instance *pdev);
-extern uint32_t host_driver_getdmdpstate(usb_core_instance *pdev);
-extern uint32_t host_driver_getvbusdrivestate(usb_core_instance *pdev);
-extern void host_driver_portrst(usb_core_instance *pdev);
-extern uint32_t host_driver_ifdevconnected(usb_core_instance *pdev);
-extern uint32_t host_driver_getcurrentfrm(usb_core_instance *pdev);
-extern HOST_CH_XFER_STATE host_driver_getxferstate(usb_core_instance *pdev, uint8_t ch_num);
-extern uint32_t host_driver_getxfercnt(usb_core_instance *pdev, uint8_t ch_num);
-extern HOST_CH_STATUS host_driver_gethostchstate(usb_core_instance *pdev, uint8_t ch_num);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_HOST_DRIVER_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
-
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_int.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_int.c
deleted file mode 100644
index dea52eaaca..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_int.c
+++ /dev/null
@@ -1,572 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_int.c
- * @brief Host driver interrupt subroutines.
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2022-06-30 CDT Remove the judgment of ErrCnt when xfer error
- Add USB core ID select function
- Modify for MISRAC
- Delete comment
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_int.h"
-#include "usb_host_driver.h"
-#include "usb_bsp.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CORE
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-void usb_host_hc_isr(usb_core_instance *pdev);
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @brief processes interrupt for a specific host channel which is used for OUT EP
- * @param [in] pdev device instance
- * @param [in] chnum channel index
- * @retval None
- */
-static void usb_host_chx_out_isr(usb_core_instance *pdev, uint8_t chnum)
-{
- uint32_t u32hcchar;
- uint32_t u32hcint;
- uint32_t u32hcintmsk;
-
- u32hcchar = READ_REG32(pdev->regs.HC_REGS[chnum]->HCCHAR);
- u32hcint = READ_REG32(pdev->regs.HC_REGS[chnum]->HCINT);
- u32hcintmsk = READ_REG32(pdev->regs.HC_REGS[chnum]->HCINTMSK);
- u32hcint = u32hcint & u32hcintmsk;
-
- if (0UL != (u32hcint & USBFS_HCINT_ACK)) {
- usb_host_clrint(pdev, chnum, USBFS_HCINT_ACK);
- } else if (0UL != (u32hcint & USBFS_HCINT_AHBERR)) {
- usb_host_clrint(pdev, chnum, USBFS_HCINT_AHBERR);
- usb_host_int_unmskchhltd(pdev, chnum);
- } else if (0UL != (u32hcint & USBFS_HCINT_FRMOR)) {
- usb_host_int_unmskchhltd(pdev, chnum);
- usb_hchstop(&pdev->regs, chnum);
- usb_host_clrint(pdev, chnum, USBFS_HCINT_FRMOR);
- } else if (0UL != (u32hcint & USBFS_HCINT_XFRC)) {
- pdev->host.ErrCnt[chnum] = 0U;
- usb_host_int_unmskchhltd(pdev, chnum);
- usb_hchstop(&pdev->regs, chnum);
- usb_host_clrint(pdev, chnum, USBFS_HCINT_XFRC);
- pdev->host.HC_Status[chnum] = HOST_CH_XFERCOMPL;
- } else if (0UL != (u32hcint & USBFS_HCINT_STALL)) {
- usb_host_clrint(pdev, chnum, USBFS_HCINT_STALL);
- usb_host_int_unmskchhltd(pdev, chnum);
- usb_hchstop(&pdev->regs, chnum);
- pdev->host.HC_Status[chnum] = HOST_CH_STALL;
- } else if (0UL != (u32hcint & USBFS_HCINT_NAK)) {
- pdev->host.ErrCnt[chnum] = 0U;
- usb_host_int_unmskchhltd(pdev, chnum);
- usb_hchstop(&pdev->regs, chnum);
- usb_host_clrint(pdev, chnum, USBFS_HCINT_NAK);
- pdev->host.HC_Status[chnum] = HOST_CH_NAK;
- } else if (0UL != (u32hcint & USBFS_HCINT_TXERR)) {
- usb_host_int_unmskchhltd(pdev, chnum);
- usb_hchstop(&pdev->regs, chnum);
- pdev->host.ErrCnt[chnum] ++;
- pdev->host.HC_Status[chnum] = HOST_CH_XACTERR;
- usb_host_clrint(pdev, chnum, USBFS_HCINT_TXERR);
- } else if (0UL != (u32hcint & HCINT_NYET)) {
- pdev->host.ErrCnt[chnum] = 0U;
- usb_host_int_unmskchhltd(pdev, chnum);
- usb_hchstop(&pdev->regs, chnum);
- usb_host_clrint(pdev, chnum, HCINT_NYET);
- pdev->host.HC_Status[chnum] = HOST_CH_NYET;
- } else if (0UL != (u32hcint & USBFS_HCINT_DTERR)) {
- usb_host_int_unmskchhltd(pdev, chnum);
- usb_hchstop(&pdev->regs, chnum);
- usb_host_clrint(pdev, chnum, USBFS_HCINT_NAK);
- pdev->host.HC_Status[chnum] = HOST_CH_DATATGLERR;
- usb_host_clrint(pdev, chnum, USBFS_HCINT_DTERR);
- } else if (0UL != (u32hcint & USBFS_HCINT_CHH)) {
- usb_host_int_mskchhltd(pdev, chnum);
- if (pdev->host.HC_Status[chnum] == HOST_CH_XFERCOMPL) {
- pdev->host.URB_State[chnum] = HOST_CH_XFER_DONE;
-
- if (((u32hcchar & USBFS_HCCHAR_EPTYP) >> USBFS_HCCHAR_EPTYP_POS) == EP_TYPE_BULK) {
- pdev->host.hc[chnum].out_toggle ^= 1U;
- }
- } else if (pdev->host.HC_Status[chnum] == HOST_CH_NAK) {
- pdev->host.URB_State[chnum] = HOST_CH_XFER_UNREADY;
- } else if (pdev->host.HC_Status[chnum] == HOST_CH_NYET) {
- if (pdev->host.hc[chnum].do_ping == 1U) {
- usb_pingtokenissue(&pdev->regs, chnum);
- }
- pdev->host.URB_State[chnum] = HOST_CH_XFER_UNREADY;
- } else if (pdev->host.HC_Status[chnum] == HOST_CH_STALL) {
- pdev->host.URB_State[chnum] = HOST_CH_XFER_STALL;
- } else if (pdev->host.HC_Status[chnum] == HOST_CH_XACTERR) {
- pdev->host.URB_State[chnum] = HOST_CH_XFER_ERROR;
- pdev->host.ErrCnt[chnum] = 0UL;
- } else {
- ;
- }
- usb_host_clrint(pdev, chnum, USBFS_HCINT_CHH);
- } else {
- ;
- }
-}
-
-/**
- * @brief processes interrupt for a specific host Channel which is used for IN EP
- * @param [in] pdev device instance
- * @param [in] chnum channel index
- * @retval None
- */
-static void usb_host_chx_in_isr(usb_core_instance *pdev, uint8_t chnum)
-{
- uint32_t u32hcchar;
- uint32_t u32hctsiz;
- uint32_t u32eptypetmp;
- uint32_t u32hcint;
- uint32_t u32hcintmsk;
-
- u32hcchar = READ_REG32(pdev->regs.HC_REGS[chnum]->HCCHAR);
- u32hcint = READ_REG32(pdev->regs.HC_REGS[chnum]->HCINT);
- u32hcintmsk = READ_REG32(pdev->regs.HC_REGS[chnum]->HCINTMSK);
- u32hcint = u32hcint & u32hcintmsk;
-
- u32eptypetmp = (u32hcchar & USBFS_HCCHAR_EPTYP) >> USBFS_HCCHAR_EPTYP_POS;
- if (0UL != (u32hcint & USBFS_HCINT_ACK)) {
- usb_host_clrint(pdev, chnum, USBFS_HCINT_ACK);
- } else if (0UL != (u32hcint & USBFS_HCINT_AHBERR)) {
- usb_host_clrint(pdev, chnum, USBFS_HCINT_AHBERR);
- usb_host_int_unmskchhltd(pdev, chnum);
- } else if (0UL != (u32hcint & USBFS_HCINT_STALL)) {
- usb_host_int_unmskchhltd(pdev, chnum);
- pdev->host.HC_Status[chnum] = HOST_CH_STALL;
- usb_host_clrint(pdev, chnum, USBFS_HCINT_NAK);
- usb_host_clrint(pdev, chnum, USBFS_HCINT_STALL);
- usb_hchstop(&pdev->regs, chnum);
- } else if (0UL != (u32hcint & USBFS_HCINT_DTERR)) {
- usb_host_int_unmskchhltd(pdev, chnum);
- usb_hchstop(&pdev->regs, chnum);
- usb_host_clrint(pdev, chnum, USBFS_HCINT_NAK);
- pdev->host.HC_Status[chnum] = HOST_CH_DATATGLERR;
- usb_host_clrint(pdev, chnum, USBFS_HCINT_DTERR);
- } else if (0UL != (u32hcint & USBFS_HCINT_FRMOR)) {
- usb_host_int_unmskchhltd(pdev, chnum);
- usb_hchstop(&pdev->regs, chnum);
- usb_host_clrint(pdev, chnum, USBFS_HCINT_FRMOR);
- } else if (0UL != (u32hcint & USBFS_HCINT_XFRC)) {
- if (pdev->basic_cfgs.dmaen == 1U) {
- u32hctsiz = READ_REG32(pdev->regs.HC_REGS[chnum]->HCTSIZ);
- pdev->host.XferCnt[chnum] = pdev->host.hc[chnum].xfer_len - (u32hctsiz & USBFS_HCTSIZ_XFRSIZ);
- pdev->host.hc[chnum].xfer_count += pdev->host.XferCnt[chnum];
- }
- pdev->host.HC_Status[chnum] = HOST_CH_XFERCOMPL;
- pdev->host.ErrCnt [chnum] = 0U;
- usb_host_clrint(pdev, chnum, USBFS_HCINT_XFRC);
- switch (u32eptypetmp) {
- case EP_TYPE_CTRL:
- case EP_TYPE_BULK:
- usb_host_int_unmskchhltd(pdev, chnum);
- usb_hchstop(&pdev->regs, chnum);
- usb_host_clrint(pdev, chnum, USBFS_HCINT_NAK);
- pdev->host.hc[chnum].in_toggle ^= (uint8_t)1;
- break;
- case EP_TYPE_INTR:
- u32hcchar |= USBFS_HCCHAR_ODDFRM;
- WRITE_REG32(pdev->regs.HC_REGS[chnum]->HCCHAR, u32hcchar);
- pdev->host.URB_State[chnum] = HOST_CH_XFER_DONE;
- break;
- case EP_TYPE_ISOC:
- if (pdev->host.HC_Status[chnum] == HOST_CH_XFERCOMPL) {
- pdev->host.URB_State[chnum] = HOST_CH_XFER_DONE;
- }
- break;
- default:
- break;
- }
- } else if (0UL != (u32hcint & USBFS_HCINT_CHH)) {
- usb_host_int_mskchhltd(pdev, chnum);
- if (pdev->host.HC_Status[chnum] == HOST_CH_XFERCOMPL) {
- pdev->host.URB_State[chnum] = HOST_CH_XFER_DONE;
- } else if (pdev->host.HC_Status[chnum] == HOST_CH_STALL) {
- pdev->host.URB_State[chnum] = HOST_CH_XFER_STALL;
- } else if (pdev->host.HC_Status[chnum] == HOST_CH_XACTERR) {
- pdev->host.ErrCnt[chnum] = 0U;
- pdev->host.URB_State[chnum] = HOST_CH_XFER_ERROR;
- } else if (pdev->host.HC_Status[chnum] == HOST_CH_DATATGLERR) {
- pdev->host.ErrCnt[chnum] = 0U;
- pdev->host.URB_State[chnum] = HOST_CH_XFER_ERROR;
- } else if (u32eptypetmp == EP_TYPE_INTR) {
- pdev->host.hc[chnum].in_toggle ^= (uint8_t)1;
- } else {
- ;
- }
- usb_host_clrint(pdev, chnum, USBFS_HCINT_CHH);
- } else if (0UL != (u32hcint & USBFS_HCINT_TXERR)) {
- usb_host_int_unmskchhltd(pdev, chnum);
- pdev->host.ErrCnt[chnum] ++;
- pdev->host.HC_Status[chnum] = HOST_CH_XACTERR;
- usb_hchstop(&pdev->regs, chnum);
- usb_host_clrint(pdev, chnum, USBFS_HCINT_TXERR);
- } else if (0UL != (u32hcint & USBFS_HCINT_NAK)) {
- if (u32eptypetmp == EP_TYPE_INTR) {
- usb_host_int_unmskchhltd(pdev, chnum);
- usb_hchstop(&pdev->regs, chnum);
- } else if ((u32eptypetmp == EP_TYPE_CTRL) || (u32eptypetmp == EP_TYPE_BULK)) {
- u32hcchar |= USBFS_HCCHAR_CHENA;
- u32hcchar &= ~USBFS_HCCHAR_CHDIS;
- WRITE_REG32(pdev->regs.HC_REGS[chnum]->HCCHAR, u32hcchar);
- } else {
- ;
- }
- pdev->host.HC_Status[chnum] = HOST_CH_NAK;
- usb_host_clrint(pdev, chnum, USBFS_HCINT_NAK);
- } else {
- ;
- }
-}
-
-/**
- * @brief this function processes the channel interrupt
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_host_hc_isr(usb_core_instance *pdev)
-{
- uint32_t u32hcchar;
- uint8_t u8Cnt;
- uint32_t u32haint;
-
- u32haint = READ_REG32(pdev->regs.HREGS->HAINT);
- for (u8Cnt = 0U; u8Cnt < pdev->basic_cfgs.host_chnum; u8Cnt++) {
- if (0UL != (u32haint & (1UL << u8Cnt))) {
- u32hcchar = READ_REG32(pdev->regs.HC_REGS[u8Cnt]->HCCHAR);
- if (0UL != ((u32hcchar & USBFS_HCCHAR_EPDIR) >> USBFS_HCCHAR_EPDIR_POS)) {
- usb_host_chx_in_isr(pdev, u8Cnt);
- } else {
- usb_host_chx_out_isr(pdev, u8Cnt);
- }
- }
- }
-}
-
-/**
- * @brief process the start-of-frame interrupt in host mode.
- * @param [in] pdev device instance
- * @retval None
- */
-static void usb_host_sof_isr(usb_core_instance *pdev)
-{
- WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_SOF);
-}
-
-/**
- * @brief processes disconnect interrupt
- * @param [in] pdev device instance
- * @retval None
- */
-static void usb_host_disconn_isr(usb_core_instance *pdev)
-{
- usb_gintdis(&pdev->regs);
- /* enable or disable the external charge pump */
- usb_bsp_drivevbus(pdev, 0U);
- usb_vbusctrl(&pdev->regs, 0U);
- WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_DISCINT);
-
- pdev->host.is_dev_connect = 0U;
-}
-
-#define USBFS_HNPTXSTS_NPTXQTOP_CHEPNUM_POS (27U)
-#define USBFS_HNPTXSTS_NPTXQTOP_CHEPNUM (0x78000000UL)
-/**
- * @brief processes non-periodic txFIFO empty interrupt.
- * @param [in] pdev device instance
- * @retval None
- */
-static void usb_host_nptxfifoempty_isr(usb_core_instance *pdev)
-{
- uint32_t u32hnptxsts;
- uint16_t u16LenWord;
- uint16_t u16Len;
- uint8_t u8ChNum;
-
- u32hnptxsts = READ_REG32(pdev->regs.GREGS->HNPTXSTS);
- u8ChNum = (uint8_t)((u32hnptxsts & USBFS_HNPTXSTS_NPTXQTOP_CHEPNUM) >> USBFS_HNPTXSTS_NPTXQTOP_CHEPNUM_POS) % USB_MAX_TX_FIFOS;
-
- u16LenWord = (uint16_t)((pdev->host.hc[u8ChNum].xfer_len + 3UL) / 4UL);
- while (((u32hnptxsts & USBFS_HNPTXSTS_NPTXFSAV) > u16LenWord) && (pdev->host.hc[u8ChNum].xfer_len != 0U)) {
- u16Len = (uint16_t)((u32hnptxsts & USBFS_HNPTXSTS_NPTXFSAV) * 4UL);
- if (u16Len > pdev->host.hc[u8ChNum].xfer_len) {
- u16Len = (uint16_t)pdev->host.hc[u8ChNum].xfer_len;
- CLR_REG32_BIT(pdev->regs.GREGS->GINTMSK, USBFS_GINTSTS_NPTXFE);
- }
- u16LenWord = (uint16_t)((pdev->host.hc[u8ChNum].xfer_len + 3UL) / 4UL);
- usb_wrpkt(&pdev->regs, pdev->host.hc[u8ChNum].xfer_buff, u8ChNum, u16Len, pdev->basic_cfgs.dmaen);
- pdev->host.hc[u8ChNum].xfer_buff += u16Len;
- pdev->host.hc[u8ChNum].xfer_len -= u16Len;
- pdev->host.hc[u8ChNum].xfer_count += u16Len;
- u32hnptxsts = READ_REG32(pdev->regs.GREGS->HNPTXSTS);
- }
-}
-#define USBFS_HPTXSTS_PTXQTOP_CHNUM_POS (27U)
-#define USBFS_HPTXSTS_PTXQTOP_CHNUM (0x78000000UL)
-/**
- * @brief processes periodic txFIFO empty interrupt
- * @param [in] pdev device instance
- * @retval None
- */
-static void usb_host_ptxfifoempty_isr(usb_core_instance *pdev)
-{
- uint32_t u32hptxsts;
- uint16_t u16LenWord;
- uint16_t u16Len;
- uint8_t u8ChNum;
-
- u32hptxsts = READ_REG32(pdev->regs.HREGS->HPTXSTS);
- u8ChNum = (uint8_t)((u32hptxsts & USBFS_HPTXSTS_PTXQTOP_CHNUM) >> USBFS_HPTXSTS_PTXQTOP_CHNUM_POS) % USB_MAX_TX_FIFOS;
- u16LenWord = (uint16_t)((pdev->host.hc[u8ChNum].xfer_len + 3UL) / 4UL);
- while ((((u32hptxsts & USBFS_HPTXSTS_PTXFSAVL)) > u16LenWord) && (pdev->host.hc[u8ChNum].xfer_len != 0U)) {
- u16Len = (uint16_t)((u32hptxsts & USBFS_HPTXSTS_PTXFSAVL) * 4UL);
- if (u16Len > pdev->host.hc[u8ChNum].xfer_len) {
- u16Len = (uint16_t)pdev->host.hc[u8ChNum].xfer_len;
- CLR_REG32_BIT(pdev->regs.GREGS->GINTMSK, USBFS_GINTMSK_PTXFEM);
- }
- u16LenWord = (uint16_t)((pdev->host.hc[u8ChNum].xfer_len + 3UL) / 4UL);
- usb_wrpkt(&pdev->regs, pdev->host.hc[u8ChNum].xfer_buff, u8ChNum, u16Len, pdev->basic_cfgs.dmaen);
- pdev->host.hc[u8ChNum].xfer_buff += u16Len;
- pdev->host.hc[u8ChNum].xfer_len -= u16Len;
- pdev->host.hc[u8ChNum].xfer_count += u16Len;
- u32hptxsts = READ_REG32(pdev->regs.HREGS->HPTXSTS);
- }
-}
-
-/**
- * @brief This function determines which interrupt conditions have occurred
- * @param [in] pdev device instance
- * @retval None
- */
-static void usb_host_port_isr(usb_core_instance *pdev)
-{
- uint32_t u32hprt;
- uint32_t u32hprt_bk;
- uint8_t u8fslspclksel;
- uint32_t do_reset = 0UL;
- uint8_t u8PortSpeed;
-
- u32hprt = READ_REG32(*pdev->regs.HPRT);
- u32hprt_bk = u32hprt;
- /* Clear the interrupt bits in GINTSTS */
- //tmp_hprt_bk.b.prtovrcurrchng = 0U;
- u32hprt_bk &= ~(USBFS_HPRT_PENA | USBFS_HPRT_PCDET | USBFS_HPRT_PENCHNG);
-
- /* check if a port connect have been detected */
- if ((u32hprt & USBFS_HPRT_PCDET) != 0UL) {
- u32hprt_bk |= USBFS_HPRT_PCDET;
- if (host_driver_getvbusdrivestate(pdev) != 0UL) {
- pdev->host.is_dev_connect = 1U;
- }
- }
- /* check if port enable or disable change */
- if ((u32hprt & USBFS_HPRT_PENCHNG) != 0UL) {
- u32hprt_bk |= USBFS_HPRT_PENCHNG;
-
- if ((u32hprt & USBFS_HPRT_PENA) != 0UL) {
- u8PortSpeed = (uint8_t)((u32hprt & USBFS_HPRT_PSPD) >> USBFS_HPRT_PSPD_POS);
- if ((u8PortSpeed == PRTSPD_LOW_SPEED) || (u8PortSpeed == PRTSPD_FULL_SPEED)) {
- u8fslspclksel = (uint8_t)(READ_REG32(pdev->regs.HREGS->HCFG) & USBFS_HCFG_FSLSPCS);
- if (u8PortSpeed == PRTSPD_LOW_SPEED) {
- if (u8fslspclksel != HCFG_6_MHZ) {
- do_reset = 1U;
- }
- } else {
- /* 1ms*(PHY clock frequency for FS/LS)-1 */
- WRITE_REG32(pdev->regs.HREGS->HFIR, 48000UL);
- if (u8fslspclksel != HCFG_48_MHZ) {
- usb_fslspclkselset(&pdev->regs, HCFG_48_MHZ);
- do_reset = 1U;
- }
- }
- } else {
- do_reset = 1U;
- }
- }
- }
-
- //if ((u32hprt & USBFS_HPRT_PRTOVRCURRCHNG) != 0UL) {
- // u32hprt_bk |= USBFS_HPRT_PRTOVRCURRCHNG;
- //}
-
- if (0UL != do_reset) {
- usb_hprtrst(&pdev->regs);
- }
- WRITE_REG32(*pdev->regs.HPRT, u32hprt_bk);
-}
-
-/**
- * @brief processes the rxFIFO non-empty interrupt
- * @param [in] pdev device instance
- * @retval None
- */
-static void usb_host_rxflvl_isr(usb_core_instance *pdev)
-{
- uint32_t u32grxsts;
- uint32_t u32hctsiz;
- uint32_t u32hcchar;
- uint8_t u8chnum;
- uint8_t *pu8Tmp;
- uint16_t u16bcnt;
-
- CLR_REG32_BIT(pdev->regs.GREGS->GINTMSK, USBFS_GINTSTS_RXFNE);
-
- u32grxsts = READ_REG32(pdev->regs.GREGS->GRXSTSP);
- u8chnum = (uint8_t)(u32grxsts & USBFS_GRXSTSP_CHNUM_EPNUM) % USB_MAX_TX_FIFOS;
- u16bcnt = (uint16_t)((u32grxsts & USBFS_GRXSTSP_BCNT) >> USBFS_GRXSTSP_BCNT_POS);
- u32hcchar = READ_REG32(pdev->regs.HC_REGS[u8chnum]->HCCHAR);
-
- switch ((u32grxsts & USBFS_GRXSTSP_PKTSTS) >> USBFS_GRXSTSP_PKTSTS_POS) {
- case 2: /* IN dat packet received */
- pu8Tmp = pdev->host.hc[u8chnum].xfer_buff;
- if ((u16bcnt > 0U) && (pu8Tmp != (void *)0U)) {
- usb_rdpkt(&pdev->regs, pdev->host.hc[u8chnum].xfer_buff, u16bcnt);
- pdev->host.hc[u8chnum].xfer_buff += u16bcnt;
- pdev->host.hc[u8chnum].xfer_count += u16bcnt;
- pdev->host.XferCnt[u8chnum] = pdev->host.hc[u8chnum].xfer_count;
-
- u32hctsiz = READ_REG32(pdev->regs.HC_REGS[u8chnum]->HCTSIZ);
- if (((u32hctsiz & USBFS_HCTSIZ_PKTCNT) >> USBFS_HCTSIZ_PKTCNT_POS) > 0U) {
- u32hcchar |= USBFS_HCCHAR_CHENA;
- u32hcchar &= ~USBFS_HCCHAR_CHDIS;
- WRITE_REG32(pdev->regs.HC_REGS[u8chnum]->HCCHAR, u32hcchar);
- }
- }
- break;
-
- case 3: /* IN transfer completed(trigger an interrupt) */
- break;
- case 5: /* Daat toggle error(trigger an interrupt) */
- break;
- case 7: /* Channel halted(trigger an interrupt) */
- break;
- default:
- break;
- }
-
- SET_REG32_BIT(pdev->regs.GREGS->GINTMSK, USBFS_GINTSTS_RXFNE);
-}
-
-/**
- * @brief process the incomplete periodic transfer interrupt(incompIP)
- * @param [in] pdev device instance
- * @retval None
- */
-static void usb_host_incomplisoout_isr(usb_core_instance *pdev)
-{
- SET_REG32_BIT(pdev->regs.HC_REGS[0]->HCCHAR, USBFS_HCCHAR_CHENA | USBFS_HCCHAR_CHDIS);
- WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_IPXFR_INCOMPISOOUT);
-}
-
-/**
- * @brief process the resume/remote wakeup detected interrupt(WkUpInt)
- * @param [in] pdev device instance
- * @retval None
- */
-static void usb_host_wkupint_isr(usb_core_instance *pdev)
-{
- uint32_t u32hprt;
- u32hprt = usb_rdhprt(&pdev->regs);
- u32hprt &= ~USBFS_HPRT_PRES;
- WRITE_REG32(*pdev->regs.HPRT, u32hprt);
-}
-
-/**
- * @brief This function process all interrupt of USB in host mode
- * @param [in] pdev device instance
- * @retval None
- */
-void usb_host_isr(usb_core_instance *pdev)
-{
- uint32_t gintstsval;
- if (0U != usb_getcurmod(&pdev->regs)) {
- gintstsval = usb_getcoreintr(&pdev->regs);
- if (0UL != (gintstsval & USBFS_GINTSTS_SOF)) {
- usb_host_sof_isr(pdev);
- }
- if (0UL != (gintstsval & USBFS_GINTSTS_RXFNE)) {
- usb_host_rxflvl_isr(pdev);
- }
- if (0UL != (gintstsval & USBFS_GINTSTS_NPTXFE)) {
- usb_host_nptxfifoempty_isr(pdev);
- }
- if (0UL != (gintstsval & USBFS_GINTSTS_PTXFE)) {
- usb_host_ptxfifoempty_isr(pdev);
- }
- if (0UL != (gintstsval & USBFS_GINTSTS_HCINT)) {
- usb_host_hc_isr(pdev);
- }
- if (0UL != (gintstsval & USBFS_GINTSTS_HPRTINT)) {
- usb_host_port_isr(pdev);
- }
- if (0UL != (gintstsval & USBFS_GINTSTS_DISCINT)) {
- usb_host_disconn_isr(pdev);
- }
- if (0UL != (gintstsval & USBFS_GINTSTS_IPXFR_INCOMPISOOUT)) {
- usb_host_incomplisoout_isr(pdev);
- }
- if (0UL != (gintstsval & USBFS_GINTSTS_WKUINT)) {
- usb_host_wkupint_isr(pdev);
- }
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************************************************************************
- * EOF (not truncated)
- *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_int.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_int.h
deleted file mode 100644
index 76b15dc130..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_int.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_int.h
- * @brief Head file for usb_host_int.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_HOST_INT_H__
-#define __USB_HOST_INT_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_def.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CORE
- * @{
- */
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#define HCINT_NYET (1UL << 6)
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-/**
- * @brief clear the interrupt flag bit
- * @param [in] pdev device instance
- * @param [in] ch_num the channel index
- * @param [in] intbit the interrupt bit of the register HCINTn
- * @retval None
- */
-__STATIC_INLINE void usb_host_clrint(usb_core_instance *pdev, uint32_t ch_num, uint32_t intbit)
-{
- WRITE_REG32(pdev->regs.HC_REGS[ch_num]->HCINT, intbit);
-}
-
-/**
- * @brief mask the interrupt of ChHltd
- * @param [in] pdev device instance
- * @param [in] ch_num channel index of the host application
- * @retval None
- */
-__STATIC_INLINE void usb_host_int_mskchhltd(usb_core_instance *pdev, uint32_t ch_num)
-{
- CLR_REG32_BIT(pdev->regs.HC_REGS[ch_num]->HCINTMSK, USBFS_HCINTMSK_CHHM);
-}
-
-/**
- * @brief unmask the interrupt of ChHltd
- * @param [in] pdev device instance
- * @param [in] ch_num channel index of the host application
- * @retval None
- */
-__STATIC_INLINE void usb_host_int_unmskchhltd(usb_core_instance *pdev, uint32_t ch_num)
-{
- SET_REG32_BIT(pdev->regs.HC_REGS[ch_num]->HCINTMSK, USBFS_HCINTMSK_CHHM);
-}
-
-/**
- * @brief mask the interrupt of ACK
- * @param [in] pdev device instance
- * @param [in] ch_num channel index of the host application
- * @retval None
- */
-__STATIC_INLINE void usb_host_int_mskack(usb_core_instance *pdev, uint32_t ch_num)
-{
- CLR_REG32_BIT(pdev->regs.HC_REGS[ch_num]->HCINTMSK, USBFS_HCINTMSK_ACKM);
-}
-
-/**
- * @brief unmask the interrupt of ACK
- * @param [in] pdev device instance
- * @param [in] ch_num channel index of the host application
- * @retval None
- */
-__STATIC_INLINE void usb_host_int_unmskack(usb_core_instance *pdev, uint32_t ch_num)
-{
- SET_REG32_BIT(pdev->regs.HC_REGS[ch_num]->HCINTMSK, USBFS_HCINTMSK_ACKM);
-}
-
-void usb_host_isr(usb_core_instance *pdev);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_HOST_INT_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
-
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.c b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.c
deleted file mode 100644
index a2eb252cea..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.c
+++ /dev/null
@@ -1,483 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_stdreq.c
- * @brief Standard requests for device enumeration
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- 2022-06-30 CDT Modify for MISRAC
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_stdreq.h"
-#include "usb_host_ctrltrans.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CORE
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes declared in the last part.
- ******************************************************************************/
-void usb_host_parsedevdesc(usb_host_devdesc_typedef *, uint8_t *buf, uint16_t length);
-
-void usb_host_parsecfgdesc(usb_host_cfgdesc_typedef *cfg_desc,
- usb_host_itfdesc_typedef *itf_desc,
- USB_HOST_EPDesc_TypeDef ep_desc[][USBH_MAX_NUM_ENDPOINTS],
- uint8_t *buf,
- uint16_t length);
-void usb_host_parseitfdesc(usb_host_itfdesc_typedef *if_descriptor, uint8_t *buf);
-void usb_host_parseepdesc(USB_HOST_EPDesc_TypeDef *ep_descriptor, uint8_t *buf);
-void usb_host_parsestringdesc(uint8_t *psrc, uint8_t *pdest, uint16_t length);
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-/**
- * @brief issue a command descriptor from the connected device. parses the
- * descriptor and updates the status once the response has been received.
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @param [in] req_type type of the descriptor
- * @param [in] value_idx wValue of setup for the request to get Descriptr
- * @param [in] buff: buffer to save the the descriptor
- * @param [in] length the length of the description.
- * @retval status
- */
-HOST_STATUS usb_host_getdesc(usb_core_instance *pdev,
- USBH_HOST *phost,
- uint8_t req_type,
- uint16_t value_idx,
- uint8_t *buff,
- uint16_t length)
-{
- phost->ctrlparam.setup.b.bmRequestType = USB_D2H | req_type;
- phost->ctrlparam.setup.b.bRequest = USB_REQ_GET_DESCRIPTOR;
- phost->ctrlparam.setup.b.wValue.w = value_idx;
-
- if ((value_idx & 0xff00U) == USB_DESC_STRING) {
- phost->ctrlparam.setup.b.wIndex.w = 0x0409U;
- } else {
- phost->ctrlparam.setup.b.wIndex.w = 0U;
- }
- phost->ctrlparam.setup.b.wLength.w = length;
- return usb_host_ctrlreq(pdev, phost, buff, length);
-}
-
-/**
- * @brief Issue command to the device to get the device discription. it parses
- * the device descriptor and updates the status once getting the device
- * description.
- * @param [in] pdev device instance
- * @param [in] phost host state set.
- * @param [in] length the length of the description.
- * @retval status
- */
-HOST_STATUS usb_host_getdevdesc(usb_core_instance *pdev,
- USBH_HOST *phost,
- uint8_t length)
-{
- HOST_STATUS status;
- status = usb_host_getdesc(pdev,
- phost,
- (uint8_t)(USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD),
- USB_DESC_DEVICE,
- pdev->host.Rx_Buffer,
- (uint16_t)length);
- if (status == HSTATUS_OK) {
- /* Commands successfully sent and Response Received */
- usb_host_parsedevdesc(&phost->device_prop.devdesc, pdev->host.Rx_Buffer, (uint16_t)length);
- }
- return status;
-}
-
-/**
- * @brief Issue a command to get the configuration description from the device
- * connected, parse the configuration descriptor and update the
- * status once the response has been received.
- * @param [in] pdev device instance
- * @param [in] phost host state set.
- * @param [in] length the length of the description.
- * @retval status
- */
-HOST_STATUS usb_host_getcfgdesc(usb_core_instance *pdev,
- USBH_HOST *phost,
- uint16_t length)
-{
- HOST_STATUS status;
-
- status = usb_host_getdesc(pdev,
- phost,
- USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD,
- USB_DESC_CONFIGURATION,
- pdev->host.Rx_Buffer,
- length);
- if (status == HSTATUS_OK) {
- usb_host_parsecfgdesc(&phost->device_prop.devcfgdesc,
- phost->device_prop.devitfdesc,
- phost->device_prop.devepdesc,
- pdev->host.Rx_Buffer,
- length);
- }
- return status;
-}
-
-/**
- * @brief Issues string Descriptor command to the device. Once the response
- * received, it parses the string descriptor and updates the status.
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @param [in] string_index the index for the string
- * @param [in] buff buffer to save the the string descriptor
- * @param [in] length the length of the description.
- * @retval status
- */
-HOST_STATUS usb_host_getstringdesc(usb_core_instance *pdev,
- USBH_HOST *phost,
- uint8_t string_index,
- uint8_t *buff,
- uint16_t length)
-{
- HOST_STATUS status;
- status = usb_host_getdesc(pdev,
- phost,
- USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD,
- USB_DESC_STRING | string_index,
- pdev->host.Rx_Buffer,
- length);
- if (status == HSTATUS_OK) {
- usb_host_parsestringdesc(pdev->host.Rx_Buffer, buff, length);
- }
- return status;
-}
-
-/**
- * @brief issue a command to set the address for the device that have connected.
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @param [in] DeviceAddress Device address which would be set to the conected device
- * @retval status
- */
-HOST_STATUS usb_host_setdevaddr(usb_core_instance *pdev,
- USBH_HOST *phost,
- uint8_t DeviceAddress)
-{
- /*
- Refer to table9-3 of 9.4
- */
- phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD;
- phost->ctrlparam.setup.b.bRequest = USB_REQ_SET_ADDRESS;
- phost->ctrlparam.setup.b.wValue.w = (uint16_t)DeviceAddress;
- phost->ctrlparam.setup.b.wIndex.w = 0U;
- phost->ctrlparam.setup.b.wLength.w = 0U;
-
- return usb_host_ctrlreq(pdev, phost, NULL, 0U);
-}
-
-/**
- * @brief issue a command to set the configuration to the connected device.
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @param [in] cfg_idx value for the configuration setup
- * @retval status
- */
-HOST_STATUS usb_host_setconfig(usb_core_instance *pdev,
- USBH_HOST *phost,
- uint16_t cfg_idx)
-{
- phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD;
- phost->ctrlparam.setup.b.bRequest = USB_REQ_SET_CONFIGURATION;
- phost->ctrlparam.setup.b.wValue.w = cfg_idx;
- phost->ctrlparam.setup.b.wIndex.w = 0U;
- phost->ctrlparam.setup.b.wLength.w = 0U;
-
- return usb_host_ctrlreq(pdev, phost, NULL, 0U);
-}
-
-/**
- * @brief issue a command to set the Interface value to the connected device
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @param [in] ep_num the index of the endpoint
- * @param [in] altSetting the value for the setup of set interface
- * @retval status
- */
-HOST_STATUS usb_host_setintf(usb_core_instance *pdev,
- USBH_HOST *phost,
- uint8_t ep_num,
- uint8_t altSetting)
-{
- phost->ctrlparam.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE | USB_REQ_TYPE_STANDARD;
-
- phost->ctrlparam.setup.b.bRequest = USB_REQ_SET_INTERFACE;
- phost->ctrlparam.setup.b.wValue.w = altSetting;
- phost->ctrlparam.setup.b.wIndex.w = ep_num;
- phost->ctrlparam.setup.b.wLength.w = 0U;
-
- return usb_host_ctrlreq(pdev, phost, NULL, 0U);
-}
-
-/**
- * @brief issue a comman to clear or disable a specific feature in the device.
- * @param [in] pdev device instance
- * @param [in] phost host state set
- * @param [in] ep_num index of the endpoint
- * @param [in] hc_num host channel index
- * @retval status
- */
-HOST_STATUS usb_host_clrfeature(usb_core_instance *pdev,
- USBH_HOST *phost,
- uint8_t ep_num,
- uint8_t hc_num)
-{
- phost->ctrlparam.setup.b.bmRequestType = USB_H2D |
- USB_REQ_RECIPIENT_ENDPOINT |
- USB_REQ_TYPE_STANDARD;
-
- phost->ctrlparam.setup.b.bRequest = USB_REQ_CLEAR_FEATURE;
- phost->ctrlparam.setup.b.wValue.w = FEATURE_SELECTOR_ENDPOINT;
- phost->ctrlparam.setup.b.wIndex.w = ep_num;
- phost->ctrlparam.setup.b.wLength.w = 0U;
-
- if ((ep_num & USB_REQ_DIR_MASK) == USB_D2H) {
- pdev->host.hc[hc_num].in_toggle = 0U;
- } else {
- pdev->host.hc[hc_num].out_toggle = 0U;
- }
-
- return usb_host_ctrlreq(pdev, phost, NULL, 0U);
-}
-
-/**
- * @brief parse the data frame of device descriptor
- * @param [in] dev_desc the structure of the device descriptor
- * @param [in] buf buffer where the source descriptor is save
- * @param [in] length Length of the descriptor in byte
- * @retval None
- */
-void usb_host_parsedevdesc(usb_host_devdesc_typedef *dev_desc,
- uint8_t *buf,
- uint16_t length)
-{
- dev_desc->bLength = buf[0];
- dev_desc->bDescriptorType = buf[1];
- dev_desc->bcdUSB = SMALL_END(&buf[2]);
- dev_desc->bDeviceClass = buf[4];
- dev_desc->bDeviceSubClass = buf[5];
- dev_desc->bDeviceProtocol = buf[6];
- dev_desc->bMaxPacketSize0 = buf[7];
-
- if (length > (uint16_t)8) {
- dev_desc->idVendor = SMALL_END(&buf[8]);
- dev_desc->idProduct = SMALL_END(&buf[10]);
- dev_desc->bcdDevice = SMALL_END(&buf[12]);
- dev_desc->iManufacturer = buf[14];
- dev_desc->iProduct = buf[15];
- dev_desc->iSerialNumber = buf[16];
- dev_desc->bNumConfigurations = buf[17];
- }
-}
-
-/**
- * @brief This function Parses the configuration descriptor from the received buffer
- * @param [in] cfg_desc the structure of configuration descriptor
- * @param [in] itf_desc the structure of interface descriptor
- * @param [in] ep_desc the structure of endpoint descriptor
- * @param [in] buf buffer where the source descriptor is save
- * @param [in] length Length of the descriptor in byte
- * @retval None
- */
-void usb_host_parsecfgdesc(usb_host_cfgdesc_typedef *cfg_desc,
- usb_host_itfdesc_typedef *itf_desc,
- USB_HOST_EPDesc_TypeDef ep_desc[][USBH_MAX_NUM_ENDPOINTS],
- uint8_t *buf,
- uint16_t length)
-{
- usb_host_itfdesc_typedef *pif ;
- usb_host_itfdesc_typedef temp_pif ;
- USB_HOST_EPDesc_TypeDef *pep;
- USB_HOST_DescHeader_TypeDef *pdesc = (USB_HOST_DescHeader_TypeDef *)buf;
- uint16_t ptr;
- int8_t if_ix;
- int8_t ep_ix;
- static uint16_t prev_ep_size = 0U;
- static uint8_t prev_itf = 0U;
-
- /* Parse the configuration descriptor */
- cfg_desc->bLength = buf[0];
- cfg_desc->bDescriptorType = buf[1];
- cfg_desc->wTotalLength = SMALL_END(&buf[2]);
- cfg_desc->bNumInterfaces = buf[4];
- cfg_desc->bConfigurationValue = buf[5];
- cfg_desc->iConfiguration = buf[6];
- cfg_desc->bmAttributes = buf[7];
- cfg_desc->bMaxPower = buf[8];
-
- if (length > USB_CONFIGURATION_DESC_SIZE) {
- ptr = USB_LEN_CFG_DESC;
-
- if (cfg_desc->bNumInterfaces <= USBH_MAX_NUM_INTERFACES) {
-
- while (ptr < cfg_desc->wTotalLength) {
- pdesc = usb_host_getnextdesc((uint8_t *)pdesc, &ptr);
- if (pdesc->bDescriptorType == USB_DESC_TYPE_INTERFACE) {
- if_ix = (int8_t) * (((uint8_t *)pdesc) + 2U);
- pif = &itf_desc[if_ix];
-
- if ((*((uint8_t *)pdesc + 3U)) < 3U) {
- usb_host_parseitfdesc(&temp_pif, (uint8_t *)pdesc);
- ep_ix = (int8_t)0;
-
- /* Parse Ep descriptors relative to the current interface */
- if (temp_pif.bNumEndpoints <= USBH_MAX_NUM_ENDPOINTS) {
- while (ep_ix < (int8_t)temp_pif.bNumEndpoints) {
- pdesc = usb_host_getnextdesc((void *)pdesc, &ptr);
- if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT) {
- pep = &ep_desc[if_ix][ep_ix];
-
- if (prev_itf != (uint8_t)if_ix) {
- prev_itf = (uint8_t)if_ix;
- usb_host_parseitfdesc(pif, (uint8_t *)&temp_pif);
- } else {
- if (prev_ep_size > SMALL_END((uint8_t *)pdesc + 4U)) {
- break;
- } else {
- usb_host_parseitfdesc(pif, (uint8_t *)&temp_pif);
- }
- }
- usb_host_parseepdesc(pep, (uint8_t *)pdesc);
- prev_ep_size = SMALL_END((uint8_t *)pdesc + 4U);
- ep_ix++;
- }
- }
- }
- }
- }
- }
- }
- prev_ep_size = 0U;
- prev_itf = 0U;
- }
-}
-
-/**
- * @brief This function parses the interface descriptor from the received buffer.
- * @param [in] if_descriptor structure of interface descriptor
- * @param [in] buf buffer where the source descriptor is save
- * @retval None
- */
-void usb_host_parseitfdesc(usb_host_itfdesc_typedef *if_descriptor, uint8_t *buf)
-{
- if_descriptor->bLength = buf[0];
- if_descriptor->bDescriptorType = buf[1];
- if_descriptor->bInterfaceNumber = buf[2];
- if_descriptor->bAlternateSetting = buf[3];
- if_descriptor->bNumEndpoints = buf[4];
- if_descriptor->bInterfaceClass = buf[5];
- if_descriptor->bInterfaceSubClass = buf[6];
- if_descriptor->bInterfaceProtocol = buf[7];
- if_descriptor->iInterface = buf[8];
-}
-
-/**
- * @brief This function parses the endpoint descriptor from the received buffer.
- * @param [in] ep_descriptor the structure of endpoint descriptor.
- * @param [in] buf buffer where the source descriptor is save
- * @retval None
- */
-void usb_host_parseepdesc(USB_HOST_EPDesc_TypeDef *ep_descriptor, uint8_t *buf)
-{
- ep_descriptor->bLength = buf[0];
- ep_descriptor->bDescriptorType = buf[1];
- ep_descriptor->bEndpointAddress = buf[2];
- ep_descriptor->bmAttributes = buf[3];
- ep_descriptor->wMaxPacketSize = SMALL_END(&buf[4]);
- ep_descriptor->bInterval = buf[6];
-}
-
-/**
- * @brief This function parses the string descriptor from the received buffer.
- * @param [in] psrc source data
- * @param [in] pdest destination data
- * @param [in] length Length of the descriptor in byte
- * @retval None
- */
-void usb_host_parsestringdesc(uint8_t *psrc, uint8_t *pdest, uint16_t length)
-{
- uint16_t strlength;
- uint16_t tmp_idx;
- /*
- The describ of String Desctipor refers to 9.6.8
- psrc[0] = bLength bLength = N+2
- psrc[1] = bDescriptorType STRING Descriptor Type
- ...
- */
- if (psrc[1] == USB_DESC_TYPE_STRING) {
- strlength = ((((uint16_t)psrc[0]) - 2U) <= length) ? (((uint16_t)psrc[0]) - 2U) : length;
- psrc += 2U;
- for (tmp_idx = 0U; tmp_idx < strlength; tmp_idx += 2U) {
- *pdest = psrc[tmp_idx];
- pdest++;
- }
- *pdest = 0U;
- }
-}
-
-/**
- * @brief This function gets the header of next descriptor.
- * @param [in] pbuf buffer where the configuration descriptor is contained.
- * @param [in] ptr data popinter inside the cfg descriptor
- * @retval header of next descriptor
- */
-USB_HOST_DescHeader_TypeDef *usb_host_getnextdesc(uint8_t *pbuf, uint16_t *ptr)
-{
- USB_HOST_DescHeader_TypeDef *pnext;
-
- *ptr += ((USB_HOST_DescHeader_TypeDef *)pbuf)->bLength;
- pnext = (USB_HOST_DescHeader_TypeDef *)((uint8_t *)pbuf + ((USB_HOST_DescHeader_TypeDef *)pbuf)->bLength);
-
- return (pnext);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/******************************************************************************
- * EOF (not truncated)
- *****************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.h
deleted file mode 100644
index 6593bc541c..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_host_stdreq.h
- * @brief Header file for usb_host_stdreq.c
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_HOST_STDREQ_H__
-#define __USB_HOST_STDREQ_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "usb_host_def.h"
-
-/**
- * @addtogroup LL_USB_LIB
- * @{
- */
-
-/**
- * @addtogroup LL_USB_HOST_CORE
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/* USBH_STDREQ_Exported_Defines */
-/* Standard Feature Selector for clear feature command */
-#define FEATURE_SELECTOR_ENDPOINT (0x00U)
-#define FEATURE_SELECTOR_DEVICE (0x01U)
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-extern HOST_STATUS usb_host_getdesc(usb_core_instance *pdev,
- USBH_HOST *phost,
- uint8_t req_type,
- uint16_t value_idx,
- uint8_t *buff,
- uint16_t length);
-
-extern HOST_STATUS usb_host_getdevdesc(usb_core_instance *pdev, USBH_HOST *phost, uint8_t length);
-
-HOST_STATUS usb_host_getstringdesc(usb_core_instance *pdev,
- USBH_HOST *phost,
- uint8_t string_index,
- uint8_t *buff,
- uint16_t length);
-
-extern HOST_STATUS usb_host_setconfig(usb_core_instance *pdev, USBH_HOST *phost, uint16_t cfg_idx);
-
-extern HOST_STATUS usb_host_getcfgdesc(usb_core_instance *pdev, USBH_HOST *phost, uint16_t length);
-
-extern HOST_STATUS usb_host_setdevaddr(usb_core_instance *pdev, USBH_HOST *phost, uint8_t DeviceAddress);
-
-extern HOST_STATUS usb_host_clrfeature(usb_core_instance *pdev, USBH_HOST *phost, uint8_t ep_num, uint8_t hc_num);
-
-extern HOST_STATUS usb_host_setintf(usb_core_instance *pdev, USBH_HOST *phost, uint8_t ep_num, uint8_t altSetting);
-
-extern USB_HOST_DescHeader_TypeDef *usb_host_getnextdesc(uint8_t *pbuf, uint16_t *ptr);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_HOST_STDREQ_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_lib.h b/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_lib.h
deleted file mode 100644
index 4d7d5ba9d9..0000000000
--- a/bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_lib.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/**
- *******************************************************************************
- * @file usb_lib.h
- * @brief Header of the Core Layer Driver
- @verbatim
- Change Logs:
- Date Author Notes
- 2022-03-31 CDT First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-#ifndef __USB_LIB_H__
-#define __USB_LIB_H__
-
-/* C binding of definitions if building with C++ compiler */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "hc32_ll_usb.h"
-#include "hc32_ll.h"
-
-/**
- * @addtogroup LL_USB_LIB LL USB Lib
- * @{
- */
-
-/**
- * @addtogroup LL_USB_LIB_DEF LL USB Lib Define
- * @{
- */
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#define MAX_DATA_LENGTH (0x200U)
-
-/*******************************************************************************
- * Global type definitions ('typedef')
- ******************************************************************************/
-
-/* status of the host channel */
-typedef enum {
- HOST_CH_IDLE = 0U,
- HOST_CH_XFERCOMPL,
- HOST_CH_CHHLTD,
- HOST_CH_NAK,
- HOST_CH_NYET,
- HOST_CH_STALL,
- HOST_CH_XACTERR,
- HOST_CH_BBLERR,
- HOST_CH_DATATGLERR,
- HOST_CH_AHBERR,
- HOST_CH_FRMOVRUN,
- HOST_CH_BNAINTR,
- HOST_CH_XCS_XACT_ERR,
- HOST_CH_DESC_LST_ROLLINTR
-} HOST_CH_STATUS;
-
-typedef enum {
- HOST_CH_XFER_IDLE = 0U,
- HOST_CH_XFER_DONE,
- HOST_CH_XFER_UNREADY,
- HOST_CH_XFER_ERROR,
- HOST_CH_XFER_STALL
-} HOST_CH_XFER_STATE;
-
-typedef enum {
- CTRL_START = 0U,
- CTRL_XFRC,
- CTRL_HALTED,
- CTRL_NAK,
- CTRL_STALL,
- CTRL_XACTERR,
- CTRL_BBLERR,
- CTRL_DATATGLERR,
- CTRL_FAIL
-} CTRL_HANDLE_STATUS;
-
-typedef struct {
- uint8_t bmRequest;
- uint8_t bRequest;
- uint16_t wValue;
- uint16_t wIndex;
- uint16_t wLength;
-} USB_SETUP_REQ;
-
-typedef struct {
- uint8_t *(*get_dev_desc)(uint16_t *length);
- uint8_t *(*get_dev_langiddesc)(uint16_t *length);
- uint8_t *(*get_dev_manufacturerstr)(uint16_t *length);
- uint8_t *(*get_dev_productstr)(uint16_t *length);
- uint8_t *(*get_dev_serialstr)(uint16_t *length);
- uint8_t *(*get_dev_configstr)(uint16_t *length);
- uint8_t *(*get_dev_interfacestr)(uint16_t *length);
-} usb_dev_desc_func;
-
-typedef struct {
- void (*class_init)(void *pdev);
- void (*class_deinit)(void *pdev);
- uint8_t (*ep0_setup)(void *pdev, USB_SETUP_REQ *req);
- void (*ep0_datain)(void *pdev);
- void (*ep0_dataout)(void *pdev);
- uint8_t *(*class_getconfigdesc)(uint16_t *length);
- uint8_t (*class_sof)(void *pdev);
- void (*class_datain)(void *pdev, uint8_t epnum);
- void (*class_dataout)(void *pdev, uint8_t epnum);
- void (*class_syn_in_incomplt)(void *pdev);
- void (*class_syn_out_incomplt)(void *pdev);
-} usb_dev_class_func;
-
-typedef struct {
- void (*user_init)(void);
- void (*user_devrst)(void);
- void (*user_devconfig)(void);
- void (*user_devsusp)(void);
- void (*user_devresume)(void);
- void (*user_devconn)(void);
- void (*user_devdisconn)(void);
-} usb_dev_user_func;
-
-typedef struct {
- __IO uint8_t device_config;
- __IO uint8_t device_address;
- __IO uint8_t device_state;
- __IO uint8_t device_old_status;
- __IO uint8_t device_cur_status;
- __IO uint8_t connection_status;
- __IO uint8_t device_remote_wakeup;
- __IO uint8_t test_mode;
- USB_DEV_EP in_ep[USB_MAX_TX_FIFOS];
- USB_DEV_EP out_ep[USB_MAX_TX_FIFOS];
- uint8_t setup_pkt_buf[24];
- usb_dev_class_func *class_callback;
- usb_dev_user_func *user_callback;
- usb_dev_desc_func *desc_callback;
-} USB_DEV_PARAM;
-
-typedef struct {
- uint16_t channel[USB_MAX_TX_FIFOS];
- USB_HOST_CH hc[USB_MAX_TX_FIFOS];
- __IO uint32_t is_dev_connect;
- uint8_t Rx_Buffer[MAX_DATA_LENGTH];
- __IO uint32_t ErrCnt[USB_MAX_TX_FIFOS];
- __IO uint32_t XferCnt[USB_MAX_TX_FIFOS];
- __IO HOST_CH_STATUS HC_Status[USB_MAX_TX_FIFOS];
- __IO HOST_CH_XFER_STATE URB_State[USB_MAX_TX_FIFOS];
-} USB_HOST_PARAM;
-
-typedef struct {
- USB_CORE_BASIC_CFGS basic_cfgs;
- LL_USB_TypeDef regs;
-#ifdef USE_DEVICE_MODE
- USB_DEV_PARAM dev;
-#endif
-#ifdef USE_HOST_MODE
- USB_HOST_PARAM host;
-#endif
-} usb_core_instance;
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- Global function prototypes (definition in C source)
- ******************************************************************************/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __USB_LIB_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/
diff --git a/bsp/hc32/platform/SConscript b/bsp/hc32/platform/SConscript
new file mode 100644
index 0000000000..3c57bc9c6d
--- /dev/null
+++ b/bsp/hc32/platform/SConscript
@@ -0,0 +1,12 @@
+import os
+from building import *
+
+objs = []
+cwd = GetCurrentDir()
+
+list = os.listdir(cwd)
+for item in list:
+ if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+ objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/hc32/platform/fal/SConscript b/bsp/hc32/platform/fal/SConscript
new file mode 100644
index 0000000000..3bb0d42c9d
--- /dev/null
+++ b/bsp/hc32/platform/fal/SConscript
@@ -0,0 +1,19 @@
+
+from building import *
+import rtconfig
+
+cwd = GetCurrentDir()
+src = []
+
+src += Glob('*.c')
+CPPPATH = [cwd]
+LOCAL_CFLAGS = ''
+
+if rtconfig.PLATFORM in ['gcc', 'armclang']:
+ LOCAL_CFLAGS += ' -std=c99'
+elif rtconfig.PLATFORM in ['armcc']:
+ LOCAL_CFLAGS += ' --c99'
+
+group = DefineGroup('Fal', src, depend = ['RT_USING_FAL'], CPPPATH = CPPPATH, LOCAL_CFLAGS = LOCAL_CFLAGS)
+
+Return('group')
diff --git a/bsp/hc32/platform/fal/fal_flash_sfud_nor.c b/bsp/hc32/platform/fal/fal_flash_sfud_nor.c
new file mode 100644
index 0000000000..fc003e559d
--- /dev/null
+++ b/bsp/hc32/platform/fal/fal_flash_sfud_nor.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2022-04-28 CDT first version
+ */
+
+#include
+#include
+#ifdef RT_USING_SFUD
+ #include
+#endif
+
+#ifndef FAL_USING_NOR_FLASH_DEV_NAME
+ #define FAL_USING_NOR_FLASH_DEV_NAME "w25q64"
+#endif
+
+#define EXT_NOR_FLASH_START_ADDR 0
+#define EXT_NOR_FLASH_CHIP_SIZE 8 * 1024 * 1024
+#define EXT_NOR_FLASH_BLOCK_SIZE 4096
+#define EXT_NOR_FLASH_WR_MIN_GRAN 1
+
+
+static int init(void);
+static int read(long offset, uint8_t *buf, size_t size);
+static int write(long offset, const uint8_t *buf, size_t size);
+static int erase(long offset, size_t size);
+
+
+static sfud_flash_t sfud_dev = NULL;
+struct fal_flash_dev ext_nor_flash0 =
+{
+ .name = FAL_USING_NOR_FLASH_DEV_NAME,
+ .addr = EXT_NOR_FLASH_START_ADDR,
+ .len = EXT_NOR_FLASH_CHIP_SIZE,
+ .blk_size = EXT_NOR_FLASH_BLOCK_SIZE,
+ .ops = {init, read, write, erase},
+ .write_gran = EXT_NOR_FLASH_WR_MIN_GRAN,
+};
+
+
+static int init(void)
+{
+ /* RT-Thread RTOS platform */
+ sfud_dev = rt_sfud_flash_find_by_dev_name(FAL_USING_NOR_FLASH_DEV_NAME);
+ if (NULL == sfud_dev)
+ {
+ return -1;
+ }
+ /* update the flash chip information */
+ ext_nor_flash0.blk_size = sfud_dev->chip.erase_gran;
+ ext_nor_flash0.len = sfud_dev->chip.capacity;
+
+ return 0;
+}
+
+static int read(long offset, uint8_t *buf, size_t size)
+{
+ assert(sfud_dev);
+ assert(sfud_dev->init_ok);
+ sfud_read(sfud_dev, ext_nor_flash0.addr + offset, size, buf);
+
+ return size;
+}
+
+static int write(long offset, const uint8_t *buf, size_t size)
+{
+ assert(sfud_dev);
+ assert(sfud_dev->init_ok);
+ if (sfud_write(sfud_dev, ext_nor_flash0.addr + offset, size, buf) != SFUD_SUCCESS)
+ {
+ return -1;
+ }
+
+ return size;
+}
+
+static int erase(long offset, size_t size)
+{
+ assert(sfud_dev);
+ assert(sfud_dev->init_ok);
+ if (sfud_erase(sfud_dev, ext_nor_flash0.addr + offset, size) != SFUD_SUCCESS)
+ {
+ return -1;
+ }
+
+ return size;
+}
diff --git a/bsp/hc32/platform/sfud/SConscript b/bsp/hc32/platform/sfud/SConscript
new file mode 100644
index 0000000000..b40316bdd7
--- /dev/null
+++ b/bsp/hc32/platform/sfud/SConscript
@@ -0,0 +1,18 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = []
+path = [cwd]
+
+if GetDepend(['BSP_USING_SPI_FLASH']):
+ src += Glob('drv_spi_flash.c')
+
+group = DefineGroup('PLATFORM', src, depend = ['RT_USING_SFUD'], CPPPATH = path)
+
+Return('group')
diff --git a/bsp/hc32/platform/sfud/drv_spi_flash.c b/bsp/hc32/platform/sfud/drv_spi_flash.c
new file mode 100644
index 0000000000..531e543833
--- /dev/null
+++ b/bsp/hc32/platform/sfud/drv_spi_flash.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2022-04-28 CDT first version
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#ifdef BSP_USING_SPI_FLASH
+
+#include "spi_flash.h"
+#ifdef RT_USING_SFUD
+ #include "spi_flash_sfud.h"
+#endif
+
+#if defined(HC32F4A0) || defined(HC32F448)
+ #define SPI_BUS_NAME "spi1"
+ #define SPI_FLASH_DEVICE_NAME "spi10"
+ #define SPI_FLASH_CHIP "w25q64"
+ #define SPI_FLASH_SS_PORT GPIO_PORT_C
+ #define SPI_FLASH_SS_PIN GPIO_PIN_07
+#elif defined(HC32F460)
+ #define SPI_BUS_NAME "spi3"
+ #define SPI_FLASH_DEVICE_NAME "spi30"
+ #define SPI_FLASH_CHIP "w25q64"
+ #define SPI_FLASH_SS_PORT GPIO_PORT_C
+ #define SPI_FLASH_SS_PIN GPIO_PIN_07
+#elif defined(HC32F472)
+ #define SPI_BUS_NAME "spi1"
+ #define SPI_FLASH_DEVICE_NAME "spi10"
+ #define SPI_FLASH_CHIP "w25q64"
+ #define SPI_FLASH_SS_PORT GPIO_PORT_B
+ #define SPI_FLASH_SS_PIN GPIO_PIN_12
+#endif
+#define SPI_FLASH_CMD_ENABLE_RESET 0x66
+#define SPI_FLASH_CMD_RESET_DEVICE 0x99
+
+/* Partition Name */
+#define FS_PARTITION_NAME "filesystem"
+
+
+#ifdef RT_USING_SFUD
+static void rt_hw_spi_flash_reset(char *spi_dev_name)
+{
+ struct rt_spi_device *spi_dev_w25;
+ rt_uint8_t w25_en_reset = SPI_FLASH_CMD_ENABLE_RESET;
+ rt_uint8_t w25_reset_dev = SPI_FLASH_CMD_RESET_DEVICE;
+
+ spi_dev_w25 = (struct rt_spi_device *)rt_device_find(spi_dev_name);
+ if (!spi_dev_w25)
+ {
+ rt_kprintf("Can't find %s device!\n", spi_dev_name);
+ }
+ else
+ {
+ rt_spi_send(spi_dev_w25, &w25_en_reset, 1U);
+ rt_spi_send(spi_dev_w25, &w25_reset_dev, 1U);
+ DDL_DelayMS(1U);
+ rt_kprintf("Reset ext flash!\n");
+ }
+}
+
+static int rt_hw_spi_flash_with_sfud_init(void)
+{
+ rt_hw_spi_device_attach(SPI_BUS_NAME, SPI_FLASH_DEVICE_NAME, SPI_FLASH_SS_PORT, SPI_FLASH_SS_PIN);
+
+ if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME))
+ {
+ rt_hw_spi_flash_reset(SPI_FLASH_DEVICE_NAME);
+ if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME))
+ {
+ return -RT_ERROR;
+ }
+ }
+
+ return RT_EOK;
+}
+INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init);
+
+static int rt_hw_fs_init(void)
+{
+ struct rt_device *mtd_dev = RT_NULL;
+
+ /* 初始化 fal */
+ fal_init();
+ /* 生成 mtd 设备 */
+ mtd_dev = fal_mtd_nor_device_create(FS_PARTITION_NAME);
+ if (!mtd_dev)
+ {
+ LOG_E("Can't create a mtd device on '%s' partition.", FS_PARTITION_NAME);
+ return -RT_ERROR;
+ }
+ else
+ {
+ /* 挂载 littlefs */
+ if (RT_EOK == dfs_mount(FS_PARTITION_NAME, "/", "lfs", 0, 0))
+ {
+ LOG_I("Filesystem initialized!");
+ return RT_EOK;
+ }
+ else
+ {
+ /* 格式化文件系统 */
+ if (RT_EOK == dfs_mkfs("lfs", FS_PARTITION_NAME))
+ {
+ /* 挂载 littlefs */
+ if (RT_EOK == dfs_mount(FS_PARTITION_NAME, "/", "lfs", 0, 0))
+ {
+ LOG_I("Filesystem initialized!");
+ return RT_EOK;
+ }
+ else
+ {
+ LOG_E("Failed to initialize filesystem!");
+ return -RT_ERROR;
+ }
+ }
+ else
+ {
+ LOG_E("Failed to Format fs!");
+ return -RT_ERROR;
+ }
+ }
+ }
+}
+INIT_APP_EXPORT(rt_hw_fs_init);
+
+#endif /* RT_USING_SFUD */
+
+#endif /* BSP_USING_SPI_FLASH */
diff --git a/bsp/hc32/platform/tca9539/SConscript b/bsp/hc32/platform/tca9539/SConscript
new file mode 100644
index 0000000000..d6c6568bbf
--- /dev/null
+++ b/bsp/hc32/platform/tca9539/SConscript
@@ -0,0 +1,18 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = []
+path = [cwd]
+
+if GetDepend(['BSP_USING_TCA9539']):
+ src += Glob('tca9539.c')
+
+group = DefineGroup('PLATFORM', src, depend = ['BSP_USING_TCA9539'], CPPPATH = path)
+
+Return('group')
diff --git a/bsp/hc32/platform/tca9539/tca9539.c b/bsp/hc32/platform/tca9539/tca9539.c
new file mode 100644
index 0000000000..e9c6e57f8c
--- /dev/null
+++ b/bsp/hc32/platform/tca9539/tca9539.c
@@ -0,0 +1,325 @@
+/*
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-02-20 CDT first version
+ */
+
+#include
+#include
+#include
+
+#ifdef BSP_USING_TCA9539
+
+#include "tca9539.h"
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/* Define for TCA9539 */
+#define BSP_TCA9539_I2C_BUS_NAME "i2c1"
+#define BSP_TCA9539_DEV_ADDR (0x74U)
+
+#if defined(HC32F4A0)
+ #define TCA9539_RST_PIN (45) /* PC13 */
+#elif defined(HC32F448)
+ #define TCA9539_RST_PIN (31) /* PB15 */
+#elif defined(HC32F472)
+ #define TCA9539_RST_PIN (44) /* PC12 */
+#endif
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+static struct rt_i2c_bus_device *i2c_bus = RT_NULL;
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @brief BSP TCA9539 write data.
+ * @param [in] bus: Pointer to the i2c bus device.
+ * @param [in] reg: Register to be written.
+ * @param [in] data: The pointer to the buffer contains the data to be written.
+ * @param [in] len: Buffer size in byte.
+ * @retval rt_err_t:
+ * - RT_EOK
+ * - -RT_ERROR
+ */
+static rt_err_t BSP_TCA9539_I2C_Write(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t *data, rt_uint16_t len)
+{
+ struct rt_i2c_msg msgs;
+ rt_uint8_t buf[6];
+
+ buf[0] = reg;
+ if (len > 0)
+ {
+ if (len < 6)
+ {
+ rt_memcpy(buf + 1, data, len);
+ }
+ else
+ {
+ return -RT_ERROR;
+ }
+ }
+ msgs.addr = BSP_TCA9539_DEV_ADDR;
+ msgs.flags = RT_I2C_WR;
+ msgs.buf = buf;
+ msgs.len = len + 1;
+ if (rt_i2c_transfer(bus, &msgs, 1) == 1)
+ {
+ return RT_EOK;
+ }
+ else
+ {
+ return -RT_ERROR;
+ }
+}
+
+/**
+ * @brief BSP TCA9539 Read data.
+ * @param [in] bus: Pointer to the i2c bus device.
+ * @param [in] reg: Register to be read.
+ * @param [out] data: The pointer to the buffer contains the data to be read.
+ * @param [in] len: Buffer size in byte.
+ * @retval rt_err_t:
+ * - RT_EOK
+ * - -RT_ERROR
+ */
+static rt_err_t BSP_TCA9539_I2C_Read(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t *data, rt_uint16_t len)
+{
+ struct rt_i2c_msg msgs;
+
+ if (RT_EOK != BSP_TCA9539_I2C_Write(bus, reg, RT_NULL, 0))
+ {
+ return -RT_ERROR;
+ }
+ msgs.addr = BSP_TCA9539_DEV_ADDR;
+ msgs.flags = RT_I2C_RD;
+ msgs.buf = data;
+ msgs.len = len;
+ if (rt_i2c_transfer(bus, &msgs, 1) == 1)
+ {
+ return RT_EOK;
+ }
+ else
+ {
+ return -RT_ERROR;
+ }
+}
+
+
+/**
+ * @brief Reset TCA9539.
+ * @param [in] None
+ * @retval None
+ */
+static void TCA9539_Reset(void)
+{
+ rt_pin_mode(TCA9539_RST_PIN, PIN_MODE_OUTPUT);
+ /* Reset the device */
+ rt_pin_write(TCA9539_RST_PIN, PIN_LOW);
+ rt_thread_mdelay(3U);
+ rt_pin_write(TCA9539_RST_PIN, PIN_HIGH);
+}
+
+/**
+ * @brief Write TCA9539 pin output value.
+ * @param [in] u8Port Port number.
+ * This parameter can be one of the following values:
+ * @arg @ref TCA9539_Port_Definition
+ * @param [in] u8Pin Pin number.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref TCA9539_Pin_Definition
+ * @param [in] u8PinState Pin state to be written.
+ * This parameter can be one of the following values:
+ * @arg @ref TCA9539_Pin_State_Definition
+ * @retval rt_err_t:
+ * - RT_ERROR
+ * - RT_EOK
+ */
+rt_err_t TCA9539_WritePin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState)
+{
+ uint8_t u8TempData[2];
+
+ u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0;
+ if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+ {
+ return -RT_ERROR;
+ }
+ if (0U == u8PinState)
+ {
+ u8TempData[1] &= (uint8_t)(~u8Pin);
+ }
+ else
+ {
+ u8TempData[1] |= u8Pin;
+ }
+ if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+ {
+ return -RT_ERROR;
+ }
+
+ return RT_EOK;
+}
+
+/**
+ * @brief Read TCA9539 pin input value.
+ * @param [in] u8Port Port number.
+ * This parameter can be one of the following values:
+ * @arg @ref TCA9539_Port_Definition
+ * @param [in] u8Pin Pin number.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref TCA9539_Pin_Definition
+ * @param [in] u8PinState Pin state to be written.
+ * This parameter can be one of the following values:
+ * @arg @ref TCA9539_Pin_State_Definition
+ * @retval rt_err_t:
+ * - RT_ERROR
+ * - RT_EOK
+ */
+rt_err_t TCA9539_ReadPin(uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState)
+{
+ uint8_t u8TempData[2];
+
+ u8TempData[0] = u8Port + TCA9539_REG_INPUT_PORT0;
+ if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+ {
+ return -RT_ERROR;
+ }
+ if (0U != (u8TempData[1] & u8Pin))
+ {
+ *pu8PinState = TCA9539_PIN_SET;
+ }
+ else
+ {
+ *pu8PinState = TCA9539_PIN_RESET;
+ }
+
+ return RT_EOK;
+}
+
+/**
+ * @brief Toggle TCA9539 pin output value.
+ * @param [in] u8Port Port number.
+ * This parameter can be one of the following values:
+ * @arg @ref TCA9539_Port_Definition
+ * @param [in] u8Pin Pin number.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref TCA9539_Pin_Definition
+ * @retval rt_err_t:
+ * - -RT_ERROR
+ * - RT_EOK
+ */
+rt_err_t TCA9539_TogglePin(uint8_t u8Port, uint8_t u8Pin)
+{
+ uint8_t u8TempData[2];
+
+ u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0;
+ if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+ {
+ return -RT_ERROR;
+ }
+ u8TempData[1] ^= u8Pin;
+ if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+ {
+ return -RT_ERROR;
+ }
+
+ return RT_EOK;
+}
+
+/**
+ * @brief Configuration TCA9539 pin.
+ * @param [in] u8Port Port number.
+ * This parameter can be one of the following values:
+ * @arg @ref TCA9539_Port_Definition
+ * @param [in] u8Pin Pin number.
+ * This parameter can be one or any combination of the following values:
+ * @arg @ref TCA9539_Pin_Definition
+ * @param [in] u8Dir Pin output direction.
+ * This parameter can be one of the following values:
+ * @arg @ref TCA9539_Direction_Definition
+ * @retval rt_err_t:
+ * - -RT_ERROR
+ * - RT_EOK
+ */
+rt_err_t TCA9539_ConfigPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir)
+{
+ uint8_t u8TempData[2];
+
+ u8TempData[0] = u8Port + TCA9539_REG_CONFIG_PORT0;
+ if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+ {
+ return -RT_ERROR;
+ }
+ if (TCA9539_DIR_OUT == u8Dir)
+ {
+ u8TempData[1] &= (uint8_t)(~u8Pin);
+ }
+ else
+ {
+ u8TempData[1] |= u8Pin;
+ }
+ if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+ {
+ return -RT_ERROR;
+ }
+
+ return RT_EOK;
+}
+
+/**
+ * @brief Initialize TCA9539.
+ * @param [in] None
+ * @retval rt_err_t:
+ * - -RT_ERROR
+ * - RT_EOK
+ */
+int TCA9539_Init(void)
+{
+ char name[RT_NAME_MAX];
+ uint8_t u8TempData[2];
+
+ TCA9539_Reset();
+ rt_strncpy(name, BSP_TCA9539_I2C_BUS_NAME, RT_NAME_MAX);
+ i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(name);
+ if (i2c_bus == RT_NULL)
+ {
+ rt_kprintf("can't find %s device!\n", BSP_TCA9539_I2C_BUS_NAME);
+ return -RT_ERROR;
+ }
+ /* All Pins are input as default */
+ u8TempData[0] = TCA9539_REG_CONFIG_PORT0;
+ u8TempData[1] = 0xFFU;
+ if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+ {
+ return -RT_ERROR;
+ }
+ u8TempData[0] = TCA9539_REG_CONFIG_PORT1;
+ if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+ {
+ return -RT_ERROR;
+ }
+
+ return RT_EOK;
+}
+INIT_PREV_EXPORT(TCA9539_Init);
+
+#endif /* BSP_USING_TCA9539 */
diff --git a/bsp/hc32/platform/tca9539/tca9539.h b/bsp/hc32/platform/tca9539/tca9539.h
new file mode 100644
index 0000000000..76ed6ed3d4
--- /dev/null
+++ b/bsp/hc32/platform/tca9539/tca9539.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-02-20 CDT first version
+ */
+
+#ifndef __TCA9539_H__
+#define __TCA9539_H__
+
+#include
+
+/**
+ * @defgroup TCA9539_REGISTER_Definition TCA9539 Register Definition
+ * @{
+ */
+#define TCA9539_REG_INPUT_PORT0 (0x00U)
+#define TCA9539_REG_INPUT_PORT1 (0x01U)
+#define TCA9539_REG_OUTPUT_PORT0 (0x02U)
+#define TCA9539_REG_OUTPUT_PORT1 (0x03U)
+#define TCA9539_REG_INVERT_PORT0 (0x04U)
+#define TCA9539_REG_INVERT_PORT1 (0x05U)
+#define TCA9539_REG_CONFIG_PORT0 (0x06U)
+#define TCA9539_REG_CONFIG_PORT1 (0x07U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TCA9539_Port_Definition TCA9539 Port Definition
+ * @{
+ */
+#define TCA9539_IO_PORT0 (0x00U)
+#define TCA9539_IO_PORT1 (0x01U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TCA9539_Pin_Definition TCA9539 Pin Definition
+ * @{
+ */
+#define TCA9539_IO_PIN0 (0x01U)
+#define TCA9539_IO_PIN1 (0x02U)
+#define TCA9539_IO_PIN2 (0x04U)
+#define TCA9539_IO_PIN3 (0x08U)
+#define TCA9539_IO_PIN4 (0x10U)
+#define TCA9539_IO_PIN5 (0x20U)
+#define TCA9539_IO_PIN6 (0x40U)
+#define TCA9539_IO_PIN7 (0x80U)
+#define TCA9539_IO_PIN_ALL (0xFFU)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TCA9539_Direction_Definition TCA9539 Direction Definition
+ * @{
+ */
+#define TCA9539_DIR_OUT (0x00U)
+#define TCA9539_DIR_IN (0x01U)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup TCA9539_Pin_State_Definition TCA9539 Pin State Definition
+ * @{
+ */
+#define TCA9539_PIN_RESET (0x00U)
+#define TCA9539_PIN_SET (0x01U)
+/**
+ * @}
+ */
+
+int TCA9539_Init(void);
+rt_err_t TCA9539_WritePin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState);
+rt_err_t TCA9539_ReadPin(uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState);
+rt_err_t TCA9539_TogglePin(uint8_t u8Port, uint8_t u8Pin);
+rt_err_t TCA9539_ConfigPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir);
+
+#endif
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