From 40e26f4909fa61ada775ba86b44d8300aaf5d250 Mon Sep 17 00:00:00 2001 From: flyingcys Date: Thu, 28 Mar 2024 23:35:54 +0800 Subject: support cv181x c906_little (#8680) --- bsp/cvitek/.gitignore | 6 +- bsp/cvitek/README.md | 38 +- bsp/cvitek/c906_little/.config | 3 + bsp/cvitek/c906_little/Kconfig | 12 +- bsp/cvitek/c906_little/README.md | 23 +- bsp/cvitek/c906_little/SConstruct | 4 + .../board/script/cv180x/cv180x_lscript.ld | 225 ++++ .../board/script/cv180x/cvi_board_memmap.ld | 30 + .../board/script/cv181x/cv181x_lscript.ld | 225 ++++ .../board/script/cv181x/cvi_board_memmap.ld | 32 + bsp/cvitek/c906_little/cv180x_lscript.ld | 226 ---- bsp/cvitek/c906_little/rtconfig.h | 1 + bsp/cvitek/c906_little/rtconfig.py | 7 +- bsp/cvitek/combine-fip.sh | 103 +- bsp/cvitek/cv1800b/.config | 1137 ------------------- bsp/cvitek/cv1800b/.gitignore | 5 - bsp/cvitek/cv1800b/Kconfig | 47 - bsp/cvitek/cv1800b/README.md | 131 --- bsp/cvitek/cv1800b/README_en.md | 130 --- bsp/cvitek/cv1800b/SConscript | 14 - bsp/cvitek/cv1800b/SConstruct | 48 - bsp/cvitek/cv1800b/applications/SConscript | 9 - bsp/cvitek/cv1800b/applications/main.c | 19 - bsp/cvitek/cv1800b/board/Kconfig | 64 -- bsp/cvitek/cv1800b/board/SConscript | 9 - bsp/cvitek/cv1800b/board/board.c | 111 -- bsp/cvitek/cv1800b/board/board.h | 32 - bsp/cvitek/cv1800b/cv1800b_milkv_duo_sd.dtb | Bin 19297 -> 0 bytes bsp/cvitek/cv1800b/link.lds | 197 ---- bsp/cvitek/cv1800b/link_stacksize.lds | 1 - bsp/cvitek/cv1800b/mkimage | Bin 366496 -> 0 bytes bsp/cvitek/cv1800b/mksdimg.sh | 7 - bsp/cvitek/cv1800b/multi.its | 56 - bsp/cvitek/cv1800b/rtconfig.h | 320 ------ bsp/cvitek/cv1800b/rtconfig.py | 59 - bsp/cvitek/cv180x/.config | 1139 ++++++++++++++++++++ bsp/cvitek/cv180x/.gitignore | 5 + bsp/cvitek/cv180x/Kconfig | 55 + bsp/cvitek/cv180x/README.md | 132 +++ bsp/cvitek/cv180x/README_en.md | 130 +++ bsp/cvitek/cv180x/SConscript | 14 + bsp/cvitek/cv180x/SConstruct | 48 + bsp/cvitek/cv180x/applications/SConscript | 9 + bsp/cvitek/cv180x/applications/main.c | 19 + bsp/cvitek/cv180x/board/Kconfig | 64 ++ bsp/cvitek/cv180x/board/SConscript | 9 + bsp/cvitek/cv180x/board/board.c | 111 ++ bsp/cvitek/cv180x/board/board.h | 32 + bsp/cvitek/cv180x/cv1800b_milkv_duo_sd.dtb | Bin 0 -> 19297 bytes bsp/cvitek/cv180x/link.lds | 197 ++++ bsp/cvitek/cv180x/link_stacksize.lds | 1 + bsp/cvitek/cv180x/multi.its | 56 + bsp/cvitek/cv180x/rtconfig.h | 321 ++++++ bsp/cvitek/cv180x/rtconfig.py | 61 ++ bsp/cvitek/drivers/.ignore_format.yml | 6 + bsp/cvitek/drivers/SConscript | 19 +- .../drivers/cv1800b/cv180x_pinlist_swconfig.h | 407 ------- bsp/cvitek/drivers/cv1800b/cv180x_pinmux.h | 51 - bsp/cvitek/drivers/cv1800b/cv180x_reg_fmux_gpio.h | 337 ------ bsp/cvitek/drivers/cv1800b/mmio.h | 150 --- bsp/cvitek/drivers/cv1800b/pinctrl.h | 34 - bsp/cvitek/drivers/cv1800b/pwm/cvi_pwm.h | 266 ----- bsp/cvitek/drivers/cv1800b/types.h | 43 - .../libraries/cv180x/cv180x_pinlist_swconfig.h | 407 +++++++ .../drivers/libraries/cv180x/cv180x_pinmux.h | 51 + .../libraries/cv180x/cv180x_reg_fmux_gpio.h | 337 ++++++ bsp/cvitek/drivers/libraries/cv180x/pinctrl.h | 34 + bsp/cvitek/drivers/libraries/cv180x/pwm/cvi_pwm.h | 266 +++++ .../libraries/cv181x/cv181x_pinlist_swconfig.h | 653 +++++++++++ .../drivers/libraries/cv181x/cv181x_pinmux.h | 46 + .../libraries/cv181x/cv181x_reg_fmux_gpio.h | 475 ++++++++ bsp/cvitek/drivers/libraries/cv181x/pinctrl.h | 35 + bsp/cvitek/drivers/libraries/mmio.h | 150 +++ bsp/cvitek/drivers/libraries/types.h | 43 + bsp/cvitek/mkimage | Bin 0 -> 366496 bytes bsp/cvitek/mksdimg.sh | 37 + .../fsbl/build/cv1800b_milkv_duo_sd/bl2.bin | Bin 47152 -> 0 bytes .../fsbl/build/cv1800b_milkv_duo_sd/blmacros.bin | 1 - .../fsbl/build/cv1800b_milkv_duo_sd/blmacros.env | 2 - .../fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin | Bin 24 -> 0 bytes bsp/cvitek/pre-build/fsbl/build/cvi_board_memmap.h | 35 - bsp/cvitek/pre-build/fsbl/plat/cv180x/chip_conf.py | 38 - bsp/cvitek/pre-build/fsbl/plat/cv180x/fipsign.py | 252 ----- bsp/cvitek/pre-build/fsbl/plat/cv180x/fiptool.py | 802 -------------- bsp/cvitek/pre-build/fsbl/plat/cv180x/platform.mk | 85 -- bsp/cvitek/pre-build/fsbl/test/cv181x/blcp.bin | Bin 16384 -> 0 bytes .../pre-build/fsbl/test/cv181x/blcp_param.bin | Bin 504 -> 0 bytes .../fsbl/test/cv181x/cmm/cv181x_clear_rom.cmm | 16 - .../fsbl/test/cv181x/cmm/cv181x_fpga_bl1_c906.cmm | 14 - .../fsbl/test/cv181x/cmm/cv181x_fpga_bl1_ca53.cmm | 13 - bsp/cvitek/pre-build/fsbl/test/cv181x/cmm/up.cmm | 40 - .../fsbl/test/cv181x/cv181x_c906b_bl1.bin | Bin 98306 -> 0 bytes .../pre-build/fsbl/test/cv181x/cv181x_ca53_bl1.bin | Bin 98306 -> 0 bytes .../pre-build/fsbl/test/cv181x/ddr_param.bin | Bin 8192 -> 0 bytes bsp/cvitek/pre-build/fsbl/test/empty.bin | 0 bsp/cvitek/pre-build/fw_dynamic.bin | Bin 110472 -> 0 bytes bsp/cvitek/pre-build/u-boot-raw.bin | Bin 273429 -> 0 bytes 97 files changed, 5633 insertions(+), 5246 deletions(-) create mode 100755 bsp/cvitek/c906_little/board/script/cv180x/cv180x_lscript.ld create mode 100755 bsp/cvitek/c906_little/board/script/cv180x/cvi_board_memmap.ld create mode 100755 bsp/cvitek/c906_little/board/script/cv181x/cv181x_lscript.ld create mode 100755 bsp/cvitek/c906_little/board/script/cv181x/cvi_board_memmap.ld delete mode 100755 bsp/cvitek/c906_little/cv180x_lscript.ld delete mode 100644 bsp/cvitek/cv1800b/.config delete mode 100755 bsp/cvitek/cv1800b/.gitignore delete mode 100755 bsp/cvitek/cv1800b/Kconfig delete mode 100755 bsp/cvitek/cv1800b/README.md delete mode 100755 bsp/cvitek/cv1800b/README_en.md delete mode 100755 bsp/cvitek/cv1800b/SConscript delete mode 100755 bsp/cvitek/cv1800b/SConstruct delete mode 100755 bsp/cvitek/cv1800b/applications/SConscript delete mode 100755 bsp/cvitek/cv1800b/applications/main.c delete mode 100755 bsp/cvitek/cv1800b/board/Kconfig delete mode 100755 bsp/cvitek/cv1800b/board/SConscript delete mode 100755 bsp/cvitek/cv1800b/board/board.c delete mode 100755 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create mode 100755 bsp/cvitek/cv180x/board/board.c create mode 100755 bsp/cvitek/cv180x/board/board.h create mode 100755 bsp/cvitek/cv180x/cv1800b_milkv_duo_sd.dtb create mode 100755 bsp/cvitek/cv180x/link.lds create mode 100755 bsp/cvitek/cv180x/link_stacksize.lds create mode 100755 bsp/cvitek/cv180x/multi.its create mode 100755 bsp/cvitek/cv180x/rtconfig.h create mode 100755 bsp/cvitek/cv180x/rtconfig.py create mode 100755 bsp/cvitek/drivers/.ignore_format.yml delete mode 100755 bsp/cvitek/drivers/cv1800b/cv180x_pinlist_swconfig.h delete mode 100755 bsp/cvitek/drivers/cv1800b/cv180x_pinmux.h delete mode 100755 bsp/cvitek/drivers/cv1800b/cv180x_reg_fmux_gpio.h delete mode 100644 bsp/cvitek/drivers/cv1800b/mmio.h delete mode 100755 bsp/cvitek/drivers/cv1800b/pinctrl.h delete mode 100644 bsp/cvitek/drivers/cv1800b/pwm/cvi_pwm.h delete mode 100755 bsp/cvitek/drivers/cv1800b/types.h create mode 100755 bsp/cvitek/drivers/libraries/cv180x/cv180x_pinlist_swconfig.h create mode 100755 bsp/cvitek/drivers/libraries/cv180x/cv180x_pinmux.h create mode 100755 bsp/cvitek/drivers/libraries/cv180x/cv180x_reg_fmux_gpio.h create mode 100755 bsp/cvitek/drivers/libraries/cv180x/pinctrl.h create mode 100755 bsp/cvitek/drivers/libraries/cv180x/pwm/cvi_pwm.h create mode 100755 bsp/cvitek/drivers/libraries/cv181x/cv181x_pinlist_swconfig.h create mode 100755 bsp/cvitek/drivers/libraries/cv181x/cv181x_pinmux.h create mode 100755 bsp/cvitek/drivers/libraries/cv181x/cv181x_reg_fmux_gpio.h create mode 100755 bsp/cvitek/drivers/libraries/cv181x/pinctrl.h create mode 100755 bsp/cvitek/drivers/libraries/mmio.h create mode 100755 bsp/cvitek/drivers/libraries/types.h create mode 100755 bsp/cvitek/mkimage create mode 100755 bsp/cvitek/mksdimg.sh delete mode 100755 bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin delete mode 100755 bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.bin delete mode 100755 bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env delete mode 100755 bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin delete mode 100755 bsp/cvitek/pre-build/fsbl/build/cvi_board_memmap.h delete mode 100755 bsp/cvitek/pre-build/fsbl/plat/cv180x/chip_conf.py delete mode 100755 bsp/cvitek/pre-build/fsbl/plat/cv180x/fipsign.py delete mode 100755 bsp/cvitek/pre-build/fsbl/plat/cv180x/fiptool.py delete mode 100755 bsp/cvitek/pre-build/fsbl/plat/cv180x/platform.mk delete mode 100755 bsp/cvitek/pre-build/fsbl/test/cv181x/blcp.bin delete mode 100755 bsp/cvitek/pre-build/fsbl/test/cv181x/blcp_param.bin delete mode 100755 bsp/cvitek/pre-build/fsbl/test/cv181x/cmm/cv181x_clear_rom.cmm delete mode 100755 bsp/cvitek/pre-build/fsbl/test/cv181x/cmm/cv181x_fpga_bl1_c906.cmm delete mode 100755 bsp/cvitek/pre-build/fsbl/test/cv181x/cmm/cv181x_fpga_bl1_ca53.cmm delete mode 100755 bsp/cvitek/pre-build/fsbl/test/cv181x/cmm/up.cmm delete mode 100755 bsp/cvitek/pre-build/fsbl/test/cv181x/cv181x_c906b_bl1.bin delete mode 100755 bsp/cvitek/pre-build/fsbl/test/cv181x/cv181x_ca53_bl1.bin delete mode 100755 bsp/cvitek/pre-build/fsbl/test/cv181x/ddr_param.bin delete mode 100755 bsp/cvitek/pre-build/fsbl/test/empty.bin delete mode 100755 bsp/cvitek/pre-build/fw_dynamic.bin delete mode 100755 bsp/cvitek/pre-build/u-boot-raw.bin diff --git a/bsp/cvitek/.gitignore b/bsp/cvitek/.gitignore index 97d926d957..93694d216f 100755 --- a/bsp/cvitek/.gitignore +++ b/bsp/cvitek/.gitignore @@ -1,2 +1,6 @@ +cvitek_bootloader fip.bin -boot.sd \ No newline at end of file +boot.sd +output +c906_little/board/script +Image.lzma \ No newline at end of file diff --git a/bsp/cvitek/README.md b/bsp/cvitek/README.md index d9c7ae1077..a343b557ce 100755 --- a/bsp/cvitek/README.md +++ b/bsp/cvitek/README.md @@ -8,7 +8,7 @@ | 芯片名称 | 芯片架构 | 内存大小 | 默认日志串口 | 备注 | | ------- | ------- |------- | -------- | -------- | -| cv1800b | RISC-V C906 | 64MByte | uart0 | 默认开启 MMU，运行 RT-SMART 模式 | +| cv180x | RISC-V C906 | 64MByte | uart0 | 默认开启 MMU，运行 RT-SMART 模式 | - 小核 @@ -18,10 +18,30 @@ > 注：异构芯片需单独编译每个核的 OS +## 编译 +异构芯片需单独编译每个核的 OS，在大/小核对应的目录下，依次执行: + +1. 开发板选择 +Linux平台下，可以先执行： +```shell +$ scons --menuconfig +``` + +选择当前需要编译的目标开发板类型 +```shell +Board Type (milkv-duo) ---> + ( ) milkv-duo + (X) milkv-duo256m +``` + +2. 编译 +```shell +$ scons +``` ## 运行 -编译成功后，会在 `bsp/cvitek` 目录下自动生成 `fip.bin` 和 `boot.sd` 文件，其中大核运行文件在 `boot.sd` 中，小核的运行文件在 `fip.bin` 中。 +编译成功后，会在 `bsp/cvitek/output` 对应开发板型号目录下自动生成 `fip.bin` 和 `boot.sd` 文件，其中大核运行文件在 `boot.sd` 中，小核的运行文件在 `fip.bin` 中。 1. 将 SD 卡分为 2 个分区，第 1 个分区用于存放 bin 文件，第 2 个分区用于作为数据存储分区，分区格式为 `FAT32`。 2. 将根目录下的 `fip.bin` 和 `boot.sd` 复制 SD 卡第一个分区中。 @@ -39,10 +59,22 @@ ## 支持开发板 - milk-v duo: [https://milkv.io/duo](https://milkv.io/duo) +- milk-v duo256m: [https://milkv.io/duo256m](https://milkv.io/docs/duo/getting-started/duo256m) ## FAQ 1. 如遇到不能正常编译，请先使用 `scons --menuconfig` 重新生成配置。 +2. 错误：./mkimage: error while loading shared libraries: libssl.so.1.1: cannot open shared object file: No such file or directory + +可在 [http://security.ubuntu.com/ubuntu/pool/main/o/openssl](http://security.ubuntu.com/ubuntu/pool/main/o/openssl) 下载 `libssl1.1_1.1.1f-1ubuntu2_amd64.deb` 文件后安装即可解决。 +或使用以下命令下载安装: +```shell +$ wget http://security.ubuntu.com/ubuntu/pool/main/o/openssl/libssl1.1_1.1.1f-1ubuntu2_amd64.deb +$ sudo dpkg -i libssl1.1_1.1.1f-1ubuntu2_amd64.deb +``` + ## 联系人信息 -维护人：[flyingcys](https://github.com/flyingcys) \ No newline at end of file +维护人：[flyingcys](https://github.com/flyingcys) + +更多信息请参考 [https://riscv-rtthread-programming-manual.readthedocs.io](https://riscv-rtthread-programming-manual.readthedocs.io) \ No newline at end of file diff --git a/bsp/cvitek/c906_little/.config b/bsp/cvitek/c906_little/.config index 56756b1f7d..4e65cfbb5f 100644 --- a/bsp/cvitek/c906_little/.config +++ b/bsp/cvitek/c906_little/.config @@ -1001,6 +1001,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set # CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set # # Display @@ -1087,3 +1088,5 @@ CONFIG_BSP_USING_C906_LITTLE=y CONFIG_PLIC_PHY_ADDR=0x70000000 CONFIG_IRQ_MAX_NR=128 CONFIG_TIMER_CLK_FREQ=25000000 +# CONFIG_BOARD_TYPE_MILKV_DUO is not set +CONFIG_BOARD_TYPE_MILKV_DUO256M=y diff --git a/bsp/cvitek/c906_little/Kconfig b/bsp/cvitek/c906_little/Kconfig index 2e6980adea..a759cc313d 100755 --- a/bsp/cvitek/c906_little/Kconfig +++ b/bsp/cvitek/c906_little/Kconfig @@ -37,4 +37,14 @@ config IRQ_MAX_NR config TIMER_CLK_FREQ int - default 25000000 \ No newline at end of file + default 25000000 + +choice + prompt "Board Type" + default BOARD_TYPE_MILKV_DUO256M + + config BOARD_TYPE_MILKV_DUO + bool "milkv-duo" + config BOARD_TYPE_MILKV_DUO256M + bool "milkv-duo256m" +endchoice diff --git a/bsp/cvitek/c906_little/README.md b/bsp/cvitek/c906_little/README.md index 71a3d6135d..5f7e0e8591 100755 --- a/bsp/cvitek/c906_little/README.md +++ b/bsp/cvitek/c906_little/README.md @@ -17,20 +17,37 @@ $ export RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin ``` ## 编译 -1. Linux平台下，可以先执行： +1. 依赖安装 + +```shell +$ sudo apt install -y scons libncurses5-dev wget flex bison +``` + + +2. Linux平台下，先执行： ```shell $ scons --menuconfig ``` -它会自动下载env相关脚本到~/.env目录，然后执行 +选择当前需要编译的目标开发板类型 +```shell +Board Type (milkv-duo) ---> + ( ) milkv-duo + (X) milkv-duo256m +``` + +它会自动下载 env 相关脚本到 ~/.env 目录，然后执行 ```shell $ source ~/.env/env.sh $ pkgs --update ``` -更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。编译正确无误，会产生rtthread.elf文件。 +更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。编译正确无误，会产生rtthread.elf 文件。 编译完成后脚本自动调用 `combine-fip.sh` 脚本进行打包，并生成 `fip.sd`, 该文件即为 SD 卡启动的 c906_little 文件。 +第一次调用 `combine-fip.sh` 脚本时会自动下载打包需要的 `opsbsbi`、`fsbl`、`uboot` 等相关文件至 `bsp/cvitek/cvitek_bootloader` 目录，请耐心等待。 + +下载完成后会自动解压、编译，后续再次编译同一类型开发板只会调用相关文件打包合成 `fip.bin`。如需手工编译相关 `cvitek_bootloader` 文件，可在 `bsp/cvitek/cvitek_bootloader` 目录下执行 `bash build.sh lunch` 选择对应的开发板编译。 ## 运行 1. 将 SD 卡分为 2 个分区，第 1 个分区用于存放 bin 文件，第 2 个分区用于作为数据存储分区，分区格式为 `FAT32`。 diff --git a/bsp/cvitek/c906_little/SConstruct b/bsp/cvitek/c906_little/SConstruct index b331ef4db8..0a1878479d 100755 --- a/bsp/cvitek/c906_little/SConstruct +++ b/bsp/cvitek/c906_little/SConstruct @@ -37,5 +37,9 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False) # include libraries objs.extend(SConscript(drivers_path_prefix + '/SConscript', variant_dir='build/drivers', duplicate=0)) +if GetDepend('BOARD_TYPE_MILKV_DUO256M'): + env['LINKFLAGS'] = env['LINKFLAGS'].replace('cv180x_lscript.ld', 'cv181x_lscript.ld') + env['LINKFLAGS'] = env['LINKFLAGS'].replace('-L board/script/cv180x', '-L board/script/cv181x') + # make a building DoBuilding(TARGET, objs) diff --git a/bsp/cvitek/c906_little/board/script/cv180x/cv180x_lscript.ld b/bsp/cvitek/c906_little/board/script/cv180x/cv180x_lscript.ld new file mode 100755 index 0000000000..a91067f725 --- /dev/null +++ b/bsp/cvitek/c906_little/board/script/cv180x/cv180x_lscript.ld @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024/01/11 flyingcys The first version + */ +INCLUDE ./cvi_board_memmap.ld + +_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x20000; +/* _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x1000000; */ +/*_HEAP_SIZE = 0x20000;*/ + +_EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024; +_EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048; +_EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024; + +/* Define Memories in the system */ + +MEMORY +{ + psu_ddr_0_MEM_0 : ORIGIN = CVIMMAP_FREERTOS_ADDR , LENGTH = CVIMMAP_FREERTOS_SIZE +} + +/* Specify the default entry point to the program */ + +/*ENTRY(_vector_table)*/ +ENTRY(_start) + +/* Define the sections, and where they are mapped in memory */ + +SECTIONS +{ +.text : { + KEEP (*(.vectors)) + *(.boot) + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + *(.plt) + *(.gnu_warning) + *(.gcc_execpt_table) + *(.glue_7) + *(.glue_7t) + *(.ARM.extab) + *(.gnu.linkonce.armextab.*) + + /* section information for finsh shell */ + . = ALIGN(8); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(8); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(8); + + /* section information for initial. */ + . = ALIGN(8); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(8); + + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; +} > psu_ddr_0_MEM_0 + +.init (ALIGN(64)) : { + KEEP (*(.init)) +} > psu_ddr_0_MEM_0 + +.fini (ALIGN(64)) : { + KEEP (*(.fini)) +} > psu_ddr_0_MEM_0 + +.interp : { + KEEP (*(.interp)) +} > psu_ddr_0_MEM_0 + +.note-ABI-tag : { + KEEP (*(.note-ABI-tag)) +} > psu_ddr_0_MEM_0 + +.rodata : { + . = ALIGN(64); + __rodata_start = .; + *(.rodata) + *(.rodata.*) + *(.srodata*) + *(.gnu.linkonce.r.*) + __rodata_end = .; +} > psu_ddr_0_MEM_0 + +.rodata1 : { + . = ALIGN(64); + __rodata1_start = .; + *(.rodata1) + *(.rodata1.*) + __rodata1_end = .; +} > psu_ddr_0_MEM_0 + +.data : { + . = ALIGN(64); + _data = .; + *(.data) + *(.data.*) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.d.*) + *(.jcr) + *(.got) + *(.got.plt) + _edata = .; +} > psu_ddr_0_MEM_0 + +.data1 : { + . = ALIGN(64); + __data1_start = .; + *(.data1) + *(.data1.*) + __data1_end = .; +} > psu_ddr_0_MEM_0 + +.got : { + *(.got) +} > psu_ddr_0_MEM_0 + +.got1 : { + *(.got1) +} > psu_ddr_0_MEM_0 + +.got2 : { + *(.got2) +} > psu_ddr_0_MEM_0 + +.ctors : { + . = ALIGN(64); + __CTOR_LIST__ = .; + ___CTORS_LIST___ = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + ___CTORS_END___ = .; +} > psu_ddr_0_MEM_0 + +.dtors : { + . = ALIGN(64); + __DTOR_LIST__ = .; + ___DTORS_LIST___ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + ___DTORS_END___ = .; +} > psu_ddr_0_MEM_0 + +.fixup : { + __fixup_start = .; + *(.fixup) + __fixup_end = .; +} > psu_ddr_0_MEM_0 + +.eh_frame : { + *(.eh_frame) +} > psu_ddr_0_MEM_0 + +.eh_framehdr : { + __eh_framehdr_start = .; + *(.eh_framehdr) + __eh_framehdr_end = .; +} > psu_ddr_0_MEM_0 + +.gcc_except_table : { + *(.gcc_except_table) +} > psu_ddr_0_MEM_0 + +.bss (NOLOAD) : { + . = ALIGN(64); + _bss = .; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(64); + _ebss = .; +} > psu_ddr_0_MEM_0 + +/*_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );*/ + _data_lma = LOADADDR(.data); + +/* Generate Stack and Heap definitions */ +.stack (NOLOAD) : { + . = ALIGN(64); + _stack_end_end = .; + . += _STACK_SIZE; + _stack_top = .; + __rt_rvstack = .; +} > psu_ddr_0_MEM_0 + +.heap (NOLOAD) : { + . = ALIGN(64); + _heap = .; + HeapBase = .; + _heap_start = .; + *(.heap*) + /*. += _HEAP_SIZE;*/ + /*_heap_size = _HEAP_SIZE; */ + _heap_end = .; + HeapLimit = .; +} > psu_ddr_0_MEM_0 + +HeapLimit = ORIGIN(psu_ddr_0_MEM_0) + LENGTH(psu_ddr_0_MEM_0); +_end = .; +} + diff --git a/bsp/cvitek/c906_little/board/script/cv180x/cvi_board_memmap.ld b/bsp/cvitek/c906_little/board/script/cv180x/cvi_board_memmap.ld new file mode 100755 index 0000000000..9f2f155826 --- /dev/null +++ b/bsp/cvitek/c906_little/board/script/cv180x/cvi_board_memmap.ld @@ -0,0 +1,30 @@ +CONFIG_SYS_TEXT_BASE = 0x80200000; +CVIMMAP_ATF_SIZE = 0x80000; +CVIMMAP_BOOTLOGO_ADDR = 0x82473000; +CVIMMAP_BOOTLOGO_SIZE = 0x0; +CVIMMAP_CONFIG_SYS_INIT_SP_ADDR = 0x82300000; +CVIMMAP_CVI_UPDATE_HEADER_ADDR = 0x813ffc00; +CVIMMAP_CVI_UPDATE_HEADER_SIZE = 0x400; +CVIMMAP_DRAM_BASE = 0x80000000; +CVIMMAP_DRAM_SIZE = 0x4000000; +CVIMMAP_FREERTOS_ADDR = 0x83f40000; +CVIMMAP_FREERTOS_RESERVED_ION_SIZE = 0x0; +CVIMMAP_FREERTOS_SIZE = 0xc0000; +CVIMMAP_FSBL_C906L_START_ADDR = 0x83f40000; +CVIMMAP_FSBL_UNZIP_ADDR = 0x81400000; +CVIMMAP_FSBL_UNZIP_SIZE = 0xf00000; +CVIMMAP_H26X_BITSTREAM_ADDR = 0x82473000; +CVIMMAP_H26X_BITSTREAM_SIZE = 0x0; +CVIMMAP_H26X_ENC_BUFF_ADDR = 0x82473000; +CVIMMAP_H26X_ENC_BUFF_SIZE = 0x0; +CVIMMAP_ION_ADDR = 0x82473000; +CVIMMAP_ION_SIZE = 0x1acd000; +CVIMMAP_ISP_MEM_BASE_ADDR = 0x82473000; +CVIMMAP_ISP_MEM_BASE_SIZE = 0x0; +CVIMMAP_KERNEL_MEMORY_ADDR = 0x80000000; +CVIMMAP_KERNEL_MEMORY_SIZE = 0x3f40000; +CVIMMAP_MONITOR_ADDR = 0x80000000; +CVIMMAP_OPENSBI_FDT_ADDR = 0x80080000; +CVIMMAP_OPENSBI_SIZE = 0x80000; +CVIMMAP_UIMAG_ADDR = 0x81400000; +CVIMMAP_UIMAG_SIZE = 0xf00000; \ No newline at end of file diff --git a/bsp/cvitek/c906_little/board/script/cv181x/cv181x_lscript.ld b/bsp/cvitek/c906_little/board/script/cv181x/cv181x_lscript.ld new file mode 100755 index 0000000000..a91067f725 --- /dev/null +++ b/bsp/cvitek/c906_little/board/script/cv181x/cv181x_lscript.ld @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024/01/11 flyingcys The first version + */ +INCLUDE ./cvi_board_memmap.ld + +_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x20000; +/* _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x1000000; */ +/*_HEAP_SIZE = 0x20000;*/ + +_EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024; +_EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048; +_EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024; + +/* Define Memories in the system */ + +MEMORY +{ + psu_ddr_0_MEM_0 : ORIGIN = CVIMMAP_FREERTOS_ADDR , LENGTH = CVIMMAP_FREERTOS_SIZE +} + +/* Specify the default entry point to the program */ + +/*ENTRY(_vector_table)*/ +ENTRY(_start) + +/* Define the sections, and where they are mapped in memory */ + +SECTIONS +{ +.text : { + KEEP (*(.vectors)) + *(.boot) + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + *(.plt) + *(.gnu_warning) + *(.gcc_execpt_table) + *(.glue_7) + *(.glue_7t) + *(.ARM.extab) + *(.gnu.linkonce.armextab.*) + + /* section information for finsh shell */ + . = ALIGN(8); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(8); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(8); + + /* section information for initial. */ + . = ALIGN(8); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(8); + + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; +} > psu_ddr_0_MEM_0 + +.init (ALIGN(64)) : { + KEEP (*(.init)) +} > psu_ddr_0_MEM_0 + +.fini (ALIGN(64)) : { + KEEP (*(.fini)) +} > psu_ddr_0_MEM_0 + +.interp : { + KEEP (*(.interp)) +} > psu_ddr_0_MEM_0 + +.note-ABI-tag : { + KEEP (*(.note-ABI-tag)) +} > psu_ddr_0_MEM_0 + +.rodata : { + . = ALIGN(64); + __rodata_start = .; + *(.rodata) + *(.rodata.*) + *(.srodata*) + *(.gnu.linkonce.r.*) + __rodata_end = .; +} > psu_ddr_0_MEM_0 + +.rodata1 : { + . = ALIGN(64); + __rodata1_start = .; + *(.rodata1) + *(.rodata1.*) + __rodata1_end = .; +} > psu_ddr_0_MEM_0 + +.data : { + . = ALIGN(64); + _data = .; + *(.data) + *(.data.*) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.d.*) + *(.jcr) + *(.got) + *(.got.plt) + _edata = .; +} > psu_ddr_0_MEM_0 + +.data1 : { + . = ALIGN(64); + __data1_start = .; + *(.data1) + *(.data1.*) + __data1_end = .; +} > psu_ddr_0_MEM_0 + +.got : { + *(.got) +} > psu_ddr_0_MEM_0 + +.got1 : { + *(.got1) +} > psu_ddr_0_MEM_0 + +.got2 : { + *(.got2) +} > psu_ddr_0_MEM_0 + +.ctors : { + . = ALIGN(64); + __CTOR_LIST__ = .; + ___CTORS_LIST___ = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + ___CTORS_END___ = .; +} > psu_ddr_0_MEM_0 + +.dtors : { + . = ALIGN(64); + __DTOR_LIST__ = .; + ___DTORS_LIST___ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + ___DTORS_END___ = .; +} > psu_ddr_0_MEM_0 + +.fixup : { + __fixup_start = .; + *(.fixup) + __fixup_end = .; +} > psu_ddr_0_MEM_0 + +.eh_frame : { + *(.eh_frame) +} > psu_ddr_0_MEM_0 + +.eh_framehdr : { + __eh_framehdr_start = .; + *(.eh_framehdr) + __eh_framehdr_end = .; +} > psu_ddr_0_MEM_0 + +.gcc_except_table : { + *(.gcc_except_table) +} > psu_ddr_0_MEM_0 + +.bss (NOLOAD) : { + . = ALIGN(64); + _bss = .; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(64); + _ebss = .; +} > psu_ddr_0_MEM_0 + +/*_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );*/ + _data_lma = LOADADDR(.data); + +/* Generate Stack and Heap definitions */ +.stack (NOLOAD) : { + . = ALIGN(64); + _stack_end_end = .; + . += _STACK_SIZE; + _stack_top = .; + __rt_rvstack = .; +} > psu_ddr_0_MEM_0 + +.heap (NOLOAD) : { + . = ALIGN(64); + _heap = .; + HeapBase = .; + _heap_start = .; + *(.heap*) + /*. += _HEAP_SIZE;*/ + /*_heap_size = _HEAP_SIZE; */ + _heap_end = .; + HeapLimit = .; +} > psu_ddr_0_MEM_0 + +HeapLimit = ORIGIN(psu_ddr_0_MEM_0) + LENGTH(psu_ddr_0_MEM_0); +_end = .; +} + diff --git a/bsp/cvitek/c906_little/board/script/cv181x/cvi_board_memmap.ld b/bsp/cvitek/c906_little/board/script/cv181x/cvi_board_memmap.ld new file mode 100755 index 0000000000..d2b8744044 --- /dev/null +++ b/bsp/cvitek/c906_little/board/script/cv181x/cvi_board_memmap.ld @@ -0,0 +1,32 @@ +CONFIG_SYS_TEXT_BASE = 0x80200000; +CVIMMAP_ATF_SIZE = 0x80000; +CVIMMAP_BOOTLOGO_ADDR = 0x8b13e000; +CVIMMAP_BOOTLOGO_SIZE = 0x1c2000; +CVIMMAP_CONFIG_SYS_INIT_SP_ADDR = 0x82800000; +CVIMMAP_CVI_UPDATE_HEADER_ADDR = 0x817ffc00; +CVIMMAP_CVI_UPDATE_HEADER_SIZE = 0x400; +CVIMMAP_DRAM_BASE = 0x80000000; +CVIMMAP_DRAM_SIZE = 0x10000000; +CVIMMAP_FRAMEBUFFER_ADDR = 0x8b13e000; +CVIMMAP_FRAMEBUFFER_SIZE = 0x1c2000; +CVIMMAP_FREERTOS_ADDR = 0x8fe00000; +CVIMMAP_FREERTOS_RESERVED_ION_SIZE = 0x1600000; +CVIMMAP_FREERTOS_SIZE = 0x200000; +CVIMMAP_FSBL_C906L_START_ADDR = 0x8fe00000; +CVIMMAP_FSBL_UNZIP_ADDR = 0x81800000; +CVIMMAP_FSBL_UNZIP_SIZE = 0x1000000; +CVIMMAP_H26X_BITSTREAM_ADDR = 0x8b300000; +CVIMMAP_H26X_BITSTREAM_SIZE = 0x200000; +CVIMMAP_H26X_ENC_BUFF_ADDR = 0x8b500000; +CVIMMAP_H26X_ENC_BUFF_SIZE = 0x0; +CVIMMAP_ION_ADDR = 0x8b300000; +CVIMMAP_ION_SIZE = 0x4b00000; +CVIMMAP_ISP_MEM_BASE_ADDR = 0x8b500000; +CVIMMAP_ISP_MEM_BASE_SIZE = 0x1400000; +CVIMMAP_KERNEL_MEMORY_ADDR = 0x80000000; +CVIMMAP_KERNEL_MEMORY_SIZE = 0xfe00000; +CVIMMAP_MONITOR_ADDR = 0x80000000; +CVIMMAP_OPENSBI_FDT_ADDR = 0x80080000; +CVIMMAP_OPENSBI_SIZE = 0x80000; +CVIMMAP_UIMAG_ADDR = 0x81800000; +CVIMMAP_UIMAG_SIZE = 0x1000000; \ No newline at end of file diff --git a/bsp/cvitek/c906_little/cv180x_lscript.ld b/bsp/cvitek/c906_little/cv180x_lscript.ld deleted file mode 100755 index 180e319311..0000000000 --- a/bsp/cvitek/c906_little/cv180x_lscript.ld +++ /dev/null @@ -1,226 +0,0 @@ -/* - * Copyright (c) 2006-2024, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2024/01/11 flyingcys The first version - */ -_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x20000; -/* _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x1000000; */ -/*_HEAP_SIZE = 0x20000;*/ - -_EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024; -_EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048; -_EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024; - -CVIMMAP_FREERTOS_ADDR = 0x83f40000; -CVIMMAP_FREERTOS_SIZE = 0xc0000; - -/* Define Memories in the system */ - -MEMORY -{ - psu_ddr_0_MEM_0 : ORIGIN = CVIMMAP_FREERTOS_ADDR , LENGTH = CVIMMAP_FREERTOS_SIZE -} - -/* Specify the default entry point to the program */ - -/*ENTRY(_vector_table)*/ -ENTRY(_start) - -/* Define the sections, and where they are mapped in memory */ - -SECTIONS -{ -.text : { - KEEP (*(.vectors)) - *(.boot) - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - *(.plt) - *(.gnu_warning) - *(.gcc_execpt_table) - *(.glue_7) - *(.glue_7t) - *(.ARM.extab) - *(.gnu.linkonce.armextab.*) - - /* section information for finsh shell */ - . = ALIGN(8); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(8); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(8); - - /* section information for initial. */ - . = ALIGN(8); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(8); - - __rt_utest_tc_tab_start = .; - KEEP(*(UtestTcTab)) - __rt_utest_tc_tab_end = .; -} > psu_ddr_0_MEM_0 - -.init (ALIGN(64)) : { - KEEP (*(.init)) -} > psu_ddr_0_MEM_0 - -.fini (ALIGN(64)) : { - KEEP (*(.fini)) -} > psu_ddr_0_MEM_0 - -.interp : { - KEEP (*(.interp)) -} > psu_ddr_0_MEM_0 - -.note-ABI-tag : { - KEEP (*(.note-ABI-tag)) -} > psu_ddr_0_MEM_0 - -.rodata : { - . = ALIGN(64); - __rodata_start = .; - *(.rodata) - *(.rodata.*) - *(.srodata*) - *(.gnu.linkonce.r.*) - __rodata_end = .; -} > psu_ddr_0_MEM_0 - -.rodata1 : { - . = ALIGN(64); - __rodata1_start = .; - *(.rodata1) - *(.rodata1.*) - __rodata1_end = .; -} > psu_ddr_0_MEM_0 - -.data : { - . = ALIGN(64); - _data = .; - *(.data) - *(.data.*) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.d.*) - *(.jcr) - *(.got) - *(.got.plt) - _edata = .; -} > psu_ddr_0_MEM_0 - -.data1 : { - . = ALIGN(64); - __data1_start = .; - *(.data1) - *(.data1.*) - __data1_end = .; -} > psu_ddr_0_MEM_0 - -.got : { - *(.got) -} > psu_ddr_0_MEM_0 - -.got1 : { - *(.got1) -} > psu_ddr_0_MEM_0 - -.got2 : { - *(.got2) -} > psu_ddr_0_MEM_0 - -.ctors : { - . = ALIGN(64); - __CTOR_LIST__ = .; - ___CTORS_LIST___ = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - __CTOR_END__ = .; - ___CTORS_END___ = .; -} > psu_ddr_0_MEM_0 - -.dtors : { - . = ALIGN(64); - __DTOR_LIST__ = .; - ___DTORS_LIST___ = .; - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - __DTOR_END__ = .; - ___DTORS_END___ = .; -} > psu_ddr_0_MEM_0 - -.fixup : { - __fixup_start = .; - *(.fixup) - __fixup_end = .; -} > psu_ddr_0_MEM_0 - -.eh_frame : { - *(.eh_frame) -} > psu_ddr_0_MEM_0 - -.eh_framehdr : { - __eh_framehdr_start = .; - *(.eh_framehdr) - __eh_framehdr_end = .; -} > psu_ddr_0_MEM_0 - -.gcc_except_table : { - *(.gcc_except_table) -} > psu_ddr_0_MEM_0 - -.bss (NOLOAD) : { - . = ALIGN(64); - _bss = .; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(64); - _ebss = .; -} > psu_ddr_0_MEM_0 - -/*_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );*/ - _data_lma = LOADADDR(.data); - -/* Generate Stack and Heap definitions */ -.stack (NOLOAD) : { - . = ALIGN(64); - _stack_end_end = .; - . += _STACK_SIZE; - _stack_top = .; - __rt_rvstack = .; -} > psu_ddr_0_MEM_0 - -.heap (NOLOAD) : { - . = ALIGN(64); - _heap = .; - HeapBase = .; - _heap_start = .; - *(.heap*) - /*. += _HEAP_SIZE;*/ - /*_heap_size = _HEAP_SIZE; */ - _heap_end = .; - HeapLimit = .; -} > psu_ddr_0_MEM_0 - -HeapLimit = ORIGIN(psu_ddr_0_MEM_0) + LENGTH(psu_ddr_0_MEM_0); -_end = .; -} - diff --git a/bsp/cvitek/c906_little/rtconfig.h b/bsp/cvitek/c906_little/rtconfig.h index 40db54549b..d4fced8b33 100755 --- a/bsp/cvitek/c906_little/rtconfig.h +++ b/bsp/cvitek/c906_little/rtconfig.h @@ -268,5 +268,6 @@ #define PLIC_PHY_ADDR 0x70000000 #define IRQ_MAX_NR 128 #define TIMER_CLK_FREQ 25000000 +#define BOARD_TYPE_MILKV_DUO256M #endif diff --git a/bsp/cvitek/c906_little/rtconfig.py b/bsp/cvitek/c906_little/rtconfig.py index dd7ed95f05..50c32d5561 100755 --- a/bsp/cvitek/c906_little/rtconfig.py +++ b/bsp/cvitek/c906_little/rtconfig.py @@ -18,7 +18,7 @@ if os.getenv('RTT_CC'): if CROSS_TOOL == 'gcc': PLATFORM = 'gcc' - EXEC_PATH = r'/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.0/bin' + EXEC_PATH = r'/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin' else: print('Please make sure your toolchains is GNU GCC!') exit(0) @@ -47,9 +47,10 @@ if PLATFORM == 'gcc': CFLAGS += ' -DCONFIG_64BIT' LINKER_SCRIPTS = r'cv180x_lscript.ld' + LINKER_SCRIPTS_PATH = r' -L board/script/cv180x' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' - LFLAGS = DEVICE + ' -nostartfiles -fms-extensions -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS + LFLAGS = DEVICE + ' -nostartfiles -fms-extensions -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS + LINKER_SCRIPTS_PATH CPATH = '' LPATH = '' @@ -63,4 +64,4 @@ if PLATFORM == 'gcc': DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' -POST_ACTION += 'cd .. && ./combine-fip.sh c906_little/rtthread.bin\n' \ No newline at end of file +POST_ACTION += 'cd .. && bash combine-fip.sh ' + os.getcwd() + ' rtthread.bin' + ' \n' \ No newline at end of file diff --git a/bsp/cvitek/combine-fip.sh b/bsp/cvitek/combine-fip.sh index fee521077c..82e2edf5b1 100755 --- a/bsp/cvitek/combine-fip.sh +++ b/bsp/cvitek/combine-fip.sh @@ -1,23 +1,84 @@ #!/bin/bash -set -e - -LITTLE_BIN=$1 - -. ./pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env && \ -./pre-build/fsbl/plat/cv180x/fiptool.py -v genfip \ - 'fip.bin' \ - --MONITOR_RUNADDR="${MONITOR_RUNADDR}" \ - --BLCP_2ND_RUNADDR="${BLCP_2ND_RUNADDR}" \ - --CHIP_CONF='./pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin' \ - --NOR_INFO='FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' \ - --NAND_INFO='00000000'\ - --BL2='pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin' \ - --BLCP_IMG_RUNADDR=0x05200200 \ - --BLCP_PARAM_LOADADDR=0 \ - --BLCP=pre-build/fsbl/test/empty.bin \ - --DDR_PARAM='pre-build/fsbl/test/cv181x/ddr_param.bin' \ - --BLCP_2ND=$LITTLE_BIN \ - --MONITOR='pre-build/fw_dynamic.bin' \ - --LOADER_2ND='pre-build/u-boot-raw.bin' \ - --compress='lzma' \ No newline at end of file +PROJECT_PATH=$1 +IMAGE_NAME=$2 + +if [ -z "$PROJECT_PATH" ] || [ -z "$IMAGE_NAME" ]; then + echo "Usage: $0 " + exit 1 +fi + +ROOT_PATH=$(pwd) +echo $ROOT_PATH + +function get_board_type() +{ + BOARD_CONFIG=("CONFIG_BOARD_TYPE_MILKV_DUO" "CONFIG_BOARD_TYPE_MILKV_DUO_SPINOR" "CONFIG_BOARD_TYPE_MILKV_DUO_SPINAND" "CONFIG_BOARD_TYPE_MILKV_DUO256M") + BOARD_VALUE=("milkv-duo" "milkv-duo-spinor" "milkv-duo-spinand" "milkv-duo256m") + + for ((i=0;i<${#BOARD_CONFIG[@]};i++)) + do + config_value=$(grep -w "${BOARD_CONFIG[i]}" ${PROJECT_PATH}/.config | cut -d= -f2) + if [ "$config_value" == "y" ]; then + BOARD_TYPE=${BOARD_VALUE[i]} + break + fi + done +} + +get_board_type +echo "board_type: ${BOARD_TYPE}" + +COUNTRY=China +function get_country() +{ + restult=$(curl -m 10 -s http://www.ip-api.com/json) + COUNTRY=$(echo $restult | sed 's/.*"country":"\([^"]*\)".*/\1/') + echo "Country: $COUNTRY" +} + +if [ "$COUNTRY" == "China" ]; then + cvitek_bootloader_url=https://gitee.com/flyingcys/cvitek_bootloader +else + cvitek_bootloader_url=https://github.com/flyingcys/cvitek_bootloader +fi + +if [ ! -d cvitek_bootloader ]; then + echo "cvitek_bootloader not exist, clone it from ${cvitek_bootloader_url}" + git clone ${cvitek_bootloader_url} + + if [ $? -ne 0 ]; then + echo "Failed to clone ${cvitek_bootloader_url} !" + exit 1 + fi +fi + +export BLCP_2ND_PATH=${PROJECT_PATH}/${IMAGE_NAME} + +pushd cvitek_bootloader + +. env.sh + +get_build_board ${BOARD_TYPE} + +echo "board: ${MV_BOARD_LINK}" + +if [ ! -d opensbi/build/platform/generic ] || [ ! -d fsbl/build/${MV_BOARD_LINK} ] || [ ! -d u-boot-2021.10/build/${MV_BOARD_LINK} ]; then + do_build + + CHIP_ARCH_L=$(echo $CHIP_ARCH | tr '[:upper:]' '[:lower:]') + cp -rf build/output/${MV_BOARD_LINK}/cvi_board_memmap.ld ${ROOT_PATH}/c906_little/board/script/${CHIP_ARCH_L} +else + echo "Build already done, skip build" + + do_combine + + if [ $? -ne 0 ]; then + do_build + fi +fi + +popd + +mkdir -p output/${MV_BOARD} +cp -rf cvitek_bootloader/install/soc_${MV_BOARD_LINK}/fip.bin output/${MV_BOARD}/fip.bin \ No newline at end of file diff --git a/bsp/cvitek/cv1800b/.config b/bsp/cvitek/cv1800b/.config deleted file mode 100644 index fd58346a23..0000000000 --- a/bsp/cvitek/cv1800b/.config +++ /dev/null @@ -1,1137 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Project Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=8 -# CONFIG_RT_USING_ARCH_DATA_TYPE is not set -CONFIG_RT_USING_SMART=y -# CONFIG_RT_USING_NANO is not set -# CONFIG_RT_USING_AMP is not set -# CONFIG_RT_USING_SMP is not set -CONFIG_RT_CPUS_NR=1 -CONFIG_RT_ALIGN_SIZE=8 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_USING_HOOK=y -CONFIG_RT_HOOK_USING_FUNC_PTR=y -# CONFIG_RT_USING_HOOKLIST is not set -CONFIG_RT_USING_IDLE_HOOK=y -CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=1024 -CONFIG_RT_USING_TIMER_SOFT=y -CONFIG_RT_TIMER_THREAD_PRIO=4 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048 - -# -# kservice optimization -# -CONFIG_RT_KSERVICE_USING_STDLIB=y -# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set -# CONFIG_RT_USING_TINY_FFS is not set -CONFIG_RT_KPRINTF_USING_LONGLONG=y -CONFIG_RT_USING_DEBUG=y -CONFIG_RT_DEBUGING_COLOR=y -CONFIG_RT_DEBUGING_CONTEXT=y -# CONFIG_RT_DEBUGING_AUTO_INIT is not set -# CONFIG_RT_DEBUGING_PAGE_LEAK is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set -# CONFIG_RT_USING_SIGNALS is not set - -# -# Memory Management -# -CONFIG_RT_PAGE_MAX_ORDER=11 -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMHEAP is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y -# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set -# CONFIG_RT_USING_USERHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set -# CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set -CONFIG_RT_USING_HEAP=y -CONFIG_RT_USING_DEVICE=y -CONFIG_RT_USING_DEVICE_OPS=y -# CONFIG_RT_USING_INTERRUPT_INFO is not set -# CONFIG_RT_USING_THREADSAFE_PRINTF is not set -# CONFIG_RT_USING_SCHED_THREAD_CTX is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=256 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x50100 -CONFIG_RT_USING_STDC_ATOMIC=y -CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 -CONFIG_ARCH_CPU_64BIT=y -CONFIG_RT_USING_CACHE=y -# CONFIG_RT_USING_HW_ATOMIC is not set -# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set -# CONFIG_RT_USING_CPU_FFS is not set -CONFIG_ARCH_MM_MMU=y -CONFIG_KERNEL_VADDR_START=0x80000000 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_RISCV64=y - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=6144 -CONFIG_RT_MAIN_THREAD_PRIORITY=10 -# CONFIG_RT_USING_LEGACY is not set -CONFIG_RT_USING_MSH=y -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_CMD_SIZE=80 -CONFIG_MSH_USING_BUILT_IN_COMMANDS=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_ARG_MAX=10 -CONFIG_FINSH_USING_OPTION_COMPLETION=y - -# -# DFS: device virtual file system -# -CONFIG_RT_USING_DFS=y -CONFIG_DFS_USING_POSIX=y -CONFIG_DFS_USING_WORKDIR=y -CONFIG_DFS_FD_MAX=16 -CONFIG_RT_USING_DFS_V2=y -# CONFIG_RT_USING_DFS_ELMFAT is not set -CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_ROMFS is not set -# CONFIG_RT_USING_DFS_CROMFS is not set -# CONFIG_RT_USING_DFS_TMPFS is not set -# CONFIG_RT_USING_DFS_MQUEUE is not set -CONFIG_RT_USING_PAGECACHE=y - -# -# page cache config -# -CONFIG_RT_PAGECACHE_COUNT=4096 -CONFIG_RT_PAGECACHE_ASPACE_COUNT=1024 -CONFIG_RT_PAGECACHE_PRELOAD=4 -CONFIG_RT_PAGECACHE_HASH_NR=1024 -CONFIG_RT_PAGECACHE_GC_WORK_LEVEL=90 -CONFIG_RT_PAGECACHE_GC_STOP_LEVEL=70 -# CONFIG_RT_USING_FAL is not set - -# -# Device Drivers -# -# CONFIG_RT_USING_DM is not set -CONFIG_RT_USING_DEVICE_IPC=y -CONFIG_RT_UNAMED_PIPE_NUMBER=64 -CONFIG_RT_USING_SYSTEM_WORKQUEUE=y -CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 -CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 -CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set -CONFIG_RT_SERIAL_USING_DMA=y -CONFIG_RT_SERIAL_RB_BUFSZ=64 -CONFIG_RT_USING_TTY=y -# CONFIG_RT_TTY_DEBUG is not set -# CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_CPUTIME is not set -# CONFIG_RT_USING_I2C is not set -# CONFIG_RT_USING_PHY is not set -# CONFIG_RT_USING_ADC is not set -# CONFIG_RT_USING_DAC is not set -CONFIG_RT_USING_NULL=y -CONFIG_RT_USING_ZERO=y -CONFIG_RT_USING_RANDOM=y -# CONFIG_RT_USING_PWM is not set -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_PM is not set -CONFIG_RT_USING_RTC=y -# CONFIG_RT_USING_ALARM is not set -# CONFIG_RT_USING_SOFT_RTC is not set -# CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set -# CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_AUDIO is not set -# CONFIG_RT_USING_SENSOR is not set -# CONFIG_RT_USING_TOUCH is not set -# CONFIG_RT_USING_LCD is not set -# CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set -# CONFIG_RT_USING_WIFI is not set -# CONFIG_RT_USING_VIRTIO is not set -CONFIG_RT_USING_PIN=y -CONFIG_RT_USING_KTIME=y -# CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# C/C++ and POSIX layer -# - -# -# ISO-ANSI C layer -# - -# -# Timezone and Daylight Saving Time -# -# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set -CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y -CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 -CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 -CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 - -# -# POSIX (Portable Operating System Interface) layer -# -CONFIG_RT_USING_POSIX_FS=y -CONFIG_RT_USING_POSIX_DEVIO=y -CONFIG_RT_USING_POSIX_STDIO=y -# CONFIG_RT_USING_POSIX_POLL is not set -# CONFIG_RT_USING_POSIX_SELECT is not set -# CONFIG_RT_USING_POSIX_EVENTFD is not set -# CONFIG_RT_USING_POSIX_EPOLL is not set -# CONFIG_RT_USING_POSIX_SIGNALFD is not set -# CONFIG_RT_USING_POSIX_TIMERFD is not set -# CONFIG_RT_USING_POSIX_SOCKET is not set -CONFIG_RT_USING_POSIX_TERMIOS=y -# CONFIG_RT_USING_POSIX_AIO is not set -# CONFIG_RT_USING_POSIX_MMAN is not set -CONFIG_RT_USING_POSIX_DELAY=y -CONFIG_RT_USING_POSIX_CLOCK=y -CONFIG_RT_USING_POSIX_TIMER=y -# CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_MODULE is not set - -# -# Interprocess Communication (IPC) -# -# CONFIG_RT_USING_POSIX_PIPE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set - -# -# Socket is in the 'Network' category -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Network -# -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set -# CONFIG_RT_USING_AT is not set - -# -# Memory protection -# -# CONFIG_RT_USING_MEM_PROTECTION is not set -# CONFIG_RT_USING_HW_STACK_GUARD is not set - -# -# Utilities -# -# CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set -# CONFIG_RT_USING_UTEST is not set -# CONFIG_RT_USING_VAR_EXPORT is not set -CONFIG_RT_USING_RESOURCE_ID=y -CONFIG_RT_USING_ADT=y -CONFIG_RT_USING_ADT_AVL=y -CONFIG_RT_USING_ADT_BITMAP=y -CONFIG_RT_USING_ADT_HASHMAP=y -CONFIG_RT_USING_ADT_REF=y -# CONFIG_RT_USING_RT_LINK is not set -# CONFIG_RT_USING_VBUS is not set -CONFIG_RT_USING_LWP=y -# CONFIG_LWP_DEBUG is not set -CONFIG_RT_LWP_MAX_NR=30 -CONFIG_LWP_TASK_STACK_SIZE=16384 -CONFIG_RT_CH_MSG_MAX_NR=1024 -CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 -CONFIG_LWP_TID_MAX_NR=64 -CONFIG_RT_LWP_SHM_MAX_NR=64 -# CONFIG_LWP_UNIX98_PTY is not set -CONFIG_RT_USING_LDSO=y -# CONFIG_ELF_DEBUG_ENABLE is not set -# CONFIG_ELF_LOAD_RANDOMIZE is not set - -# -# Memory management -# -# CONFIG_RT_USING_MEMBLOCK is not set - -# -# RT-Thread Utestcases -# -# CONFIG_RT_USING_UTESTCASES is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_LWIP is not set -# CONFIG_PKG_USING_LORAWAN_DRIVER is not set -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_UMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_WEBNET is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_MYMQTT is not set -# CONFIG_PKG_USING_KAWAII_MQTT is not set -# CONFIG_PKG_USING_BC28_MQTT is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_FREEMODBUS is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_RW007 is not set - -# -# CYW43012 WiFi -# -# CONFIG_PKG_USING_WLAN_CYW43012 is not set - -# -# BL808 WiFi -# -# CONFIG_PKG_USING_WLAN_BL808 is not set - -# -# CYW43439 WiFi -# -# CONFIG_PKG_USING_WLAN_CYW43439 is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_CMUX is not set -# CONFIG_PKG_USING_PPP_DEVICE is not set -# CONFIG_PKG_USING_AT_DEVICE is not set -# CONFIG_PKG_USING_ATSRV_SOCKET is not set -# CONFIG_PKG_USING_WIZNET is not set -# CONFIG_PKG_USING_ZB_COORDINATOR is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set -# CONFIG_PKG_USING_JIOT-C-SDK is not set -# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set -# CONFIG_PKG_USING_JOYLINK is not set -# CONFIG_PKG_USING_IOTSHARP_SDK is not set -# CONFIG_PKG_USING_NIMBLE is not set -# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set -# CONFIG_PKG_USING_OTA_DOWNLOADER is not set -# CONFIG_PKG_USING_IPMSG is not set -# CONFIG_PKG_USING_LSSDP is not set -# CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set -# CONFIG_PKG_USING_TCPSERVER is not set -# CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_DLT645 is not set -# CONFIG_PKG_USING_QXWZ is not set -# CONFIG_PKG_USING_SMTP_CLIENT is not set -# CONFIG_PKG_USING_ABUP_FOTA is not set -# CONFIG_PKG_USING_LIBCURL2RTT is not set -# CONFIG_PKG_USING_CAPNP is not set -# CONFIG_PKG_USING_AGILE_TELNET is not set -# CONFIG_PKG_USING_NMEALIB is not set -# CONFIG_PKG_USING_PDULIB is not set -# CONFIG_PKG_USING_BTSTACK is not set -# CONFIG_PKG_USING_BT_CYW43012 is not set -# CONFIG_PKG_USING_CYW43XX is not set -# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set -# CONFIG_PKG_USING_WAYZ_IOTKIT is not set -# CONFIG_PKG_USING_MAVLINK is not set -# CONFIG_PKG_USING_BSAL is not set -# CONFIG_PKG_USING_AGILE_MODBUS is not set -# CONFIG_PKG_USING_AGILE_FTP is not set -# CONFIG_PKG_USING_EMBEDDEDPROTO is not set -# CONFIG_PKG_USING_RT_LINK_HW is not set -# CONFIG_PKG_USING_RYANMQTT is not set -# CONFIG_PKG_USING_RYANW5500 is not set -# CONFIG_PKG_USING_LORA_PKT_FWD is not set -# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set -# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set -# CONFIG_PKG_USING_HM is not set -# CONFIG_PKG_USING_SMALL_MODBUS is not set -# CONFIG_PKG_USING_NET_SERVER is not set -# CONFIG_PKG_USING_ZFTP is not set -# CONFIG_PKG_USING_WOL is not set -# CONFIG_PKG_USING_ZEPHYR_POLLING is not set -# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set -# CONFIG_PKG_USING_LHC_MODBUS is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_LIBSODIUM is not set -# CONFIG_PKG_USING_LIBHYDROGEN is not set -# CONFIG_PKG_USING_TINYCRYPT is not set -# CONFIG_PKG_USING_TFM is not set -# CONFIG_PKG_USING_YD_CRYPTO is not set - -# -# language packages -# - -# -# JSON: JavaScript Object Notation, a lightweight data-interchange format -# -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set -# CONFIG_PKG_USING_RAPIDJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_AGILE_JSMN is not set -# CONFIG_PKG_USING_PARSON is not set - -# -# XML: Extensible Markup Language -# -# CONFIG_PKG_USING_SIMPLE_XML is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_LUATOS_SOC is not set -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set -# CONFIG_PKG_USING_PIKASCRIPT is not set -# CONFIG_PKG_USING_RTT_RUST is not set - -# -# multimedia packages -# - -# -# LVGL: powerful and easy-to-use embedded GUI library -# -# CONFIG_PKG_USING_LVGL is not set -# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set -# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set - -# -# u8g2: a monochrome graphic library -# -# CONFIG_PKG_USING_U8G2_OFFICIAL is not set -# CONFIG_PKG_USING_U8G2 is not set -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_STEMWIN is not set -# CONFIG_PKG_USING_WAVPLAYER is not set -# CONFIG_PKG_USING_TJPGD is not set -# CONFIG_PKG_USING_PDFGEN is not set -# CONFIG_PKG_USING_HELIX is not set -# CONFIG_PKG_USING_AZUREGUIX is not set -# CONFIG_PKG_USING_TOUCHGFX2RTT is not set -# CONFIG_PKG_USING_NUEMWIN is not set -# CONFIG_PKG_USING_MP3PLAYER is not set -# CONFIG_PKG_USING_TINYJPEG is not set -# CONFIG_PKG_USING_UGUI is not set -# CONFIG_PKG_USING_MCURSES is not set -# CONFIG_PKG_USING_TERMBOX is not set -# CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_3GPP_AMRNB is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_SEGGER_RTT is not set -# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_LOGMGR is not set -# CONFIG_PKG_USING_ADBD is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_DHRYSTONE is not set -# CONFIG_PKG_USING_MEMORYPERF is not set -# CONFIG_PKG_USING_NR_MICRO_SHELL is not set -# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set -# CONFIG_PKG_USING_LUNAR_CALENDAR is not set -# CONFIG_PKG_USING_BS8116A is not set -# CONFIG_PKG_USING_GPS_RMC is not set -# CONFIG_PKG_USING_URLENCODE is not set -# CONFIG_PKG_USING_UMCN is not set -# CONFIG_PKG_USING_LWRB2RTT is not set -# CONFIG_PKG_USING_CPU_USAGE is not set -# CONFIG_PKG_USING_GBK2UTF8 is not set -# CONFIG_PKG_USING_VCONSOLE is not set -# CONFIG_PKG_USING_KDB is not set -# CONFIG_PKG_USING_WAMR is not set -# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set -# CONFIG_PKG_USING_LWLOG is not set -# CONFIG_PKG_USING_ANV_TRACE is not set -# CONFIG_PKG_USING_ANV_MEMLEAK is not set -# CONFIG_PKG_USING_ANV_TESTSUIT is not set -# CONFIG_PKG_USING_ANV_BENCH is not set -# CONFIG_PKG_USING_DEVMEM is not set -# CONFIG_PKG_USING_REGEX is not set -# CONFIG_PKG_USING_MEM_SANDBOX is not set -# CONFIG_PKG_USING_SOLAR_TERMS is not set -# CONFIG_PKG_USING_GAN_ZHI is not set -# CONFIG_PKG_USING_FDT is not set -# CONFIG_PKG_USING_CBOX is not set -# CONFIG_PKG_USING_SNOWFLAKE is not set -# CONFIG_PKG_USING_HASH_MATCH is not set -# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set -# CONFIG_PKG_USING_VOFA_PLUS is not set -# CONFIG_PKG_USING_ZDEBUG is not set - -# -# system packages -# - -# -# enhanced kernel services -# -# CONFIG_PKG_USING_RT_MEMCPY_CM is not set -# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set -# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set - -# -# acceleration: Assembly language or algorithmic acceleration packages -# -# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set -# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set -# CONFIG_PKG_USING_QFPLIB_M3 is not set - -# -# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard -# -# CONFIG_PKG_USING_CMSIS_5 is not set -# CONFIG_PKG_USING_CMSIS_CORE is not set -# CONFIG_PKG_USING_CMSIS_DSP is not set -# CONFIG_PKG_USING_CMSIS_NN is not set -# CONFIG_PKG_USING_CMSIS_RTOS1 is not set -# CONFIG_PKG_USING_CMSIS_RTOS2 is not set - -# -# Micrium: Micrium software products porting for RT-Thread -# -# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set -# CONFIG_PKG_USING_UCOSII_WRAPPER is not set -# CONFIG_PKG_USING_UC_CRC is not set -# CONFIG_PKG_USING_UC_CLK is not set -# CONFIG_PKG_USING_UC_COMMON is not set -# CONFIG_PKG_USING_UC_MODBUS is not set -# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set -# CONFIG_PKG_USING_LITEOS_SDK is not set -# CONFIG_PKG_USING_TZ_DATABASE is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_PERF_COUNTER is not set -# CONFIG_PKG_USING_FILEX is not set -# CONFIG_PKG_USING_LEVELX is not set -# CONFIG_PKG_USING_FLASHDB is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_DFS_JFFS2 is not set -# CONFIG_PKG_USING_DFS_UFFS is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set -# CONFIG_PKG_USING_EV is not set -# CONFIG_PKG_USING_SYSWATCH is not set -# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set -# CONFIG_PKG_USING_PLCCORE is not set -# CONFIG_PKG_USING_RAMDISK is not set -# CONFIG_PKG_USING_MININI is not set -# CONFIG_PKG_USING_QBOOT is not set -# CONFIG_PKG_USING_PPOOL is not set -# CONFIG_PKG_USING_OPENAMP is not set -# CONFIG_PKG_USING_RPMSG_LITE is not set -# CONFIG_PKG_USING_LPM is not set -# CONFIG_PKG_USING_TLSF is not set -# CONFIG_PKG_USING_EVENT_RECORDER is not set -# CONFIG_PKG_USING_ARM_2D is not set -# CONFIG_PKG_USING_MCUBOOT is not set -# CONFIG_PKG_USING_TINYUSB is not set -# CONFIG_PKG_USING_CHERRYUSB is not set -# CONFIG_PKG_USING_KMULTI_RTIMER is not set -# CONFIG_PKG_USING_TFDB is not set -# CONFIG_PKG_USING_QPC is not set -# CONFIG_PKG_USING_AGILE_UPGRADE is not set -# CONFIG_PKG_USING_FLASH_BLOB is not set -# CONFIG_PKG_USING_MLIBC is not set -# CONFIG_PKG_USING_TASK_MSG_BUS is not set -# CONFIG_PKG_USING_SFDB is not set -# CONFIG_PKG_USING_RTP is not set -# CONFIG_PKG_USING_REB is not set -# CONFIG_PKG_USING_R_RHEALSTONE is not set - -# -# peripheral libraries and drivers -# - -# -# HAL & SDK Drivers -# - -# -# STM32 HAL & SDK Drivers -# -# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_BLUETRUM_SDK is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set -# CONFIG_PKG_USING_ESP_IDF is not set - -# -# Kendryte SDK -# -# CONFIG_PKG_USING_K210_SDK is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set -# CONFIG_PKG_USING_NUCLEI_SDK is not set -# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set - -# -# sensors drivers -# -# CONFIG_PKG_USING_LSM6DSM is not set -# CONFIG_PKG_USING_LSM6DSL is not set -# CONFIG_PKG_USING_LPS22HB is not set -# CONFIG_PKG_USING_HTS221 is not set -# CONFIG_PKG_USING_LSM303AGR is not set -# CONFIG_PKG_USING_BME280 is not set -# CONFIG_PKG_USING_BME680 is not set -# CONFIG_PKG_USING_BMA400 is not set -# CONFIG_PKG_USING_BMI160_BMX160 is not set -# CONFIG_PKG_USING_SPL0601 is not set -# CONFIG_PKG_USING_MS5805 is not set -# CONFIG_PKG_USING_DA270 is not set -# CONFIG_PKG_USING_DF220 is not set -# CONFIG_PKG_USING_HSHCAL001 is not set -# CONFIG_PKG_USING_BH1750 is not set -# CONFIG_PKG_USING_MPU6XXX is not set -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set -# CONFIG_PKG_USING_TSL4531 is not set -# CONFIG_PKG_USING_DS18B20 is not set -# CONFIG_PKG_USING_DHT11 is not set -# CONFIG_PKG_USING_DHTXX is not set -# CONFIG_PKG_USING_GY271 is not set -# CONFIG_PKG_USING_GP2Y10 is not set -# CONFIG_PKG_USING_SGP30 is not set -# CONFIG_PKG_USING_HDC1000 is not set -# CONFIG_PKG_USING_BMP180 is not set -# CONFIG_PKG_USING_BMP280 is not set -# CONFIG_PKG_USING_SHTC1 is not set -# CONFIG_PKG_USING_BMI088 is not set -# CONFIG_PKG_USING_HMC5883 is not set -# CONFIG_PKG_USING_MAX6675 is not set -# CONFIG_PKG_USING_TMP1075 is not set -# CONFIG_PKG_USING_SR04 is not set -# CONFIG_PKG_USING_CCS811 is not set -# CONFIG_PKG_USING_PMSXX is not set -# CONFIG_PKG_USING_RT3020 is not set -# CONFIG_PKG_USING_MLX90632 is not set -# CONFIG_PKG_USING_MLX90393 is not set -# CONFIG_PKG_USING_MLX90392 is not set -# CONFIG_PKG_USING_MLX90397 is not set -# CONFIG_PKG_USING_MS5611 is not set -# CONFIG_PKG_USING_MAX31865 is not set -# CONFIG_PKG_USING_VL53L0X is not set -# CONFIG_PKG_USING_INA260 is not set -# CONFIG_PKG_USING_MAX30102 is not set -# CONFIG_PKG_USING_INA226 is not set -# CONFIG_PKG_USING_LIS2DH12 is not set -# CONFIG_PKG_USING_HS300X is not set -# CONFIG_PKG_USING_ZMOD4410 is not set -# CONFIG_PKG_USING_ISL29035 is not set -# CONFIG_PKG_USING_MMC3680KJ is not set -# CONFIG_PKG_USING_QMP6989 is not set -# CONFIG_PKG_USING_BALANCE is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_SHT4X is not set -# CONFIG_PKG_USING_AD7746 is not set -# CONFIG_PKG_USING_ADT74XX is not set -# CONFIG_PKG_USING_MAX17048 is not set -# CONFIG_PKG_USING_AS7341 is not set -# CONFIG_PKG_USING_CW2015 is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_PAJ7620 is not set -# CONFIG_PKG_USING_STHS34PF80 is not set - -# -# touch drivers -# -# CONFIG_PKG_USING_GT9147 is not set -# CONFIG_PKG_USING_GT1151 is not set -# CONFIG_PKG_USING_GT917S is not set -# CONFIG_PKG_USING_GT911 is not set -# CONFIG_PKG_USING_FT6206 is not set -# CONFIG_PKG_USING_FT5426 is not set -# CONFIG_PKG_USING_FT6236 is not set -# CONFIG_PKG_USING_XPT2046_TOUCH is not set -# CONFIG_PKG_USING_CST816X is not set -# CONFIG_PKG_USING_CST812T is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_LITTLED is not set -# CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_MULTI_INFRARED is not set -# CONFIG_PKG_USING_AGILE_BUTTON is not set -# CONFIG_PKG_USING_AGILE_LED is not set -# CONFIG_PKG_USING_AT24CXX is not set -# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_ILI9341 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set -# CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_RPLIDAR is not set -# CONFIG_PKG_USING_AS608 is not set -# CONFIG_PKG_USING_RC522 is not set -# CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set -# CONFIG_PKG_USING_MULTI_RTIMER is not set -# CONFIG_PKG_USING_MAX7219 is not set -# CONFIG_PKG_USING_BEEP is not set -# CONFIG_PKG_USING_EASYBLINK is not set -# CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_CAN_YMODEM is not set -# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set -# CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_AGILE_CONSOLE is not set -# CONFIG_PKG_USING_LD3320 is not set -# CONFIG_PKG_USING_WK2124 is not set -# CONFIG_PKG_USING_LY68L6400 is not set -# CONFIG_PKG_USING_DM9051 is not set -# CONFIG_PKG_USING_SSD1306 is not set -# CONFIG_PKG_USING_QKEY is not set -# CONFIG_PKG_USING_RS485 is not set -# CONFIG_PKG_USING_RS232 is not set -# CONFIG_PKG_USING_NES is not set -# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set -# CONFIG_PKG_USING_VDEVICE is not set -# CONFIG_PKG_USING_SGM706 is not set -# CONFIG_PKG_USING_RDA58XX is not set -# CONFIG_PKG_USING_LIBNFC is not set -# CONFIG_PKG_USING_MFOC is not set -# CONFIG_PKG_USING_TMC51XX is not set -# CONFIG_PKG_USING_TCA9534 is not set -# CONFIG_PKG_USING_KOBUKI is not set -# CONFIG_PKG_USING_ROSSERIAL is not set -# CONFIG_PKG_USING_MICRO_ROS is not set -# CONFIG_PKG_USING_MCP23008 is not set -# CONFIG_PKG_USING_MISAKA_AT24CXX is not set -# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set -# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_SOFT_SERIAL is not set -# CONFIG_PKG_USING_MB85RS16 is not set -# CONFIG_PKG_USING_RFM300 is not set -# CONFIG_PKG_USING_IO_INPUT_FILTER is not set -# CONFIG_PKG_USING_LRF_NV7LIDAR is not set -# CONFIG_PKG_USING_AIP650 is not set -# CONFIG_PKG_USING_FINGERPRINT is not set -# CONFIG_PKG_USING_BT_ECB02C is not set -# CONFIG_PKG_USING_UAT is not set -# CONFIG_PKG_USING_ST7789 is not set -# CONFIG_PKG_USING_VS1003 is not set -# CONFIG_PKG_USING_X9555 is not set -# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set -# CONFIG_PKG_USING_BT_MX01 is not set -# CONFIG_PKG_USING_RGPOWER is not set -# CONFIG_PKG_USING_SPI_TOOLS is not set - -# -# AI packages -# -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set -# CONFIG_PKG_USING_ELAPACK is not set -# CONFIG_PKG_USING_ULAPACK is not set -# CONFIG_PKG_USING_QUEST is not set -# CONFIG_PKG_USING_NAXOS is not set -# CONFIG_PKG_USING_R_TINYMAIX is not set - -# -# Signal Processing and Control Algorithm Packages -# -# CONFIG_PKG_USING_FIRE_PID_CURVE is not set -# CONFIG_PKG_USING_QPID is not set -# CONFIG_PKG_USING_UKAL is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set -# CONFIG_PKG_USING_KISSFFT is not set - -# -# miscellaneous packages -# - -# -# project laboratory -# - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# entertainment: terminal games and other interesting software packages -# -# CONFIG_PKG_USING_CMATRIX is not set -# CONFIG_PKG_USING_SL is not set -# CONFIG_PKG_USING_CAL is not set -# CONFIG_PKG_USING_ACLOCK is not set -# CONFIG_PKG_USING_THREES is not set -# CONFIG_PKG_USING_2048 is not set -# CONFIG_PKG_USING_SNAKE is not set -# CONFIG_PKG_USING_TETRIS is not set -# CONFIG_PKG_USING_DONUT is not set -# CONFIG_PKG_USING_COWSAY is not set -# CONFIG_PKG_USING_MORSE is not set -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_LZMA is not set -# CONFIG_PKG_USING_RALARAM is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_MINIZIP is not set -# CONFIG_PKG_USING_HEATSHRINK is not set -# CONFIG_PKG_USING_DSTR is not set -# CONFIG_PKG_USING_TINYFRAME is not set -# CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_UPACKER is not set -# CONFIG_PKG_USING_UPARAM is not set -# CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_CRCLIB is not set -# CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_STATE_MACHINE is not set -# CONFIG_PKG_USING_DESIGN_PATTERN is not set -# CONFIG_PKG_USING_CONTROLLER is not set -# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set -# CONFIG_PKG_USING_MFBD is not set -# CONFIG_PKG_USING_SLCAN2RTT is not set -# CONFIG_PKG_USING_SOEM is not set -# CONFIG_PKG_USING_QPARAM is not set -# CONFIG_PKG_USING_CorevMCU_CLI is not set - -# -# Arduino libraries -# -# CONFIG_PKG_USING_RTDUINO is not set - -# -# Projects and Demos -# -# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set -# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set -# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set -# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set -# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set -# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set - -# -# Sensors -# -# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set -# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set - -# -# Display -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_U8G2 is not set -# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set -# CONFIG_PKG_USING_SEEED_TM1637 is not set - -# -# Timing -# -# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set -# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set -# CONFIG_PKG_USING_ARDUINO_TICKER is not set -# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set - -# -# Data Processing -# -# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set -# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set -# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set - -# -# Data Storage -# - -# -# Communication -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set - -# -# Device Control -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set - -# -# Other -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set - -# -# Signal IO -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set - -# -# Uncategorized -# - -# -# General Drivers Configuration -# -CONFIG_BSP_USING_UART=y -CONFIG_RT_USING_UART0=y -CONFIG_UART_IRQ_BASE=44 -# CONFIG_RT_USING_UART1 is not set -# CONFIG_RT_USING_UART2 is not set -# CONFIG_RT_USING_UART3 is not set -# CONFIG_RT_USING_UART4 is not set -# CONFIG_BSP_USING_ADC is not set -# CONFIG_BSP_USING_PWM is not set -CONFIG_BSP_USING_CV1800B=y -CONFIG_C906_PLIC_PHY_ADDR=0x70000000 -CONFIG_IRQ_MAX_NR=64 -CONFIG_TIMER_CLK_FREQ=25000000 -CONFIG___STACKSIZE__=4096 diff --git a/bsp/cvitek/cv1800b/.gitignore b/bsp/cvitek/cv1800b/.gitignore deleted file mode 100755 index f58350d6cf..0000000000 --- a/bsp/cvitek/cv1800b/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -cv1800b_milkv_duo_sd.dtb -Image -Image.lzma -multi.its -boot.sd \ No newline at end of file diff --git a/bsp/cvitek/cv1800b/Kconfig b/bsp/cvitek/cv1800b/Kconfig deleted file mode 100755 index 18394dca61..0000000000 --- a/bsp/cvitek/cv1800b/Kconfig +++ /dev/null @@ -1,47 +0,0 @@ -mainmenu "RT-Thread Project Configuration" - -config BSP_DIR - string - option env="BSP_ROOT" - default "." - -config RTT_DIR - string - option env="RTT_ROOT" - default "../../.." - -config PKGS_DIR - string - option env="PKGS_ROOT" - default "packages" - -source "$RTT_DIR/Kconfig" -source "$PKGS_DIR/Kconfig" -source "board/Kconfig" - -config BSP_USING_CV1800B - bool - select ARCH_RISCV64 - select RT_USING_SYSTEM_WORKQUEUE - select RT_USING_COMPONENTS_INIT - select RT_USING_USER_MAIN - select RT_USING_CACHE - select ARCH_MM_MMU - select RT_USING_DEVICE_OPS - default y - -config C906_PLIC_PHY_ADDR - hex - default 0x70000000 - -config IRQ_MAX_NR - int - default 64 - -config TIMER_CLK_FREQ - int - default 25000000 - -config __STACKSIZE__ - int "stack size for interrupt" - default 4096 diff --git a/bsp/cvitek/cv1800b/README.md b/bsp/cvitek/cv1800b/README.md deleted file mode 100755 index 9293cf2e29..0000000000 --- a/bsp/cvitek/cv1800b/README.md +++ /dev/null @@ -1,131 +0,0 @@ - **中文** | [English](README_en.md) - -## 概述 -CV180ZB/CV1800B/CV1801B 是面向民用消费监控 IP 摄像机、居家智能等多项产品领域而推出的高性能、低功耗芯片，集成了 H.264/H.265 视频压缩编码器和 ISP；支持数字寛动态、 3D 降噪、除雾、镜头畸变校正等多种图像增强和矫正算法，为客户提供专业级的视频图像质量。 - -1. 处理器内核 - -- 主处理器 RISCV C906 @ 1.0Ghz - - 32KB I-cache, 64KB D-Cache - - 集成矢量(Vector)及浮点运算单元 (FPU) . -- 协处理器 RISCV C906 @ 700Mhz - - 集成浮点运算单元 (FPU) - -2. 存储器接口 -- 内建 DRAM : DDR2 16bitx1, 最高速率达 1333Mbps , 容量512Mbit (64MB) -- 支持SPI NOR flash 接口 (1.8V / 3.0V) - - 支持 1, 2, 4 线模式 - - 最大支持 256MByte -- 支持 SPI Nand flash 接口 (1.8V / 3.0V) - - 支持 1KB/2KB/4KB page (对应的最大容量 16GB/32GB/64GB) - - 使用器件本身内建的 ECC 模块 - -3. 外设 -- Up to 26 GPIO pins on the MilkV-Duo 40-pin header provide access to internal peripherals such as SDIO, I2C, PWM, SPI, J-TAG, and UART -- Up to 3x I2C -- Up to 5x UART -- Up to 1x SDIO1 -- Up to 1x SPI -- Up to 2x ADC -- Up to 7x PWM -- Up to 1x RUN -- Up to 1x JTAG -- 集成 MAC PHY 支持 10/100Mbps 全双工或半双工模式 -- 一个 USB Host / device 接口 - -## Toolchain 下载 -下载 `riscv64-unknown-linux-musl-gcc` 的工具链: [https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2](https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2) - -> 注： -当前 bsp 只支持 Linux 编译 - -正确解压后，在`rtconfig.py`中将 `riscv64-unknown-linux-musl-gcc` 工具链的本地路径加入 `EXEC_PATH` 或通过 `RTT_EXEC_PATH` 环境变量指定路径。 - -```shell -$ export RTT_EXEC_PATH=/opt/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu/bin -``` - -## 编译 -1. 依赖安装 - -```shell -$ sudo apt install -y device-tree-compiler -``` -2. Linux平台下，可以先执行： -```shell -$ scons --menuconfig -``` - -它会自动下载env相关脚本到~/.env目录，然后执行 -```shell -$ source ~/.env/env.sh -$ pkgs --update -``` -更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。编译正确无误，会产生rtthread.elf文件。 - -编译完成后脚本自动调用 `./mksdimg.sh` 脚本进行打包，并生成 `boot.sd`, 该文件即为 SD 卡启动的 kernel 文件。 - - -## 运行 -1. 将 SD 卡分为 2 个分区，第 1 个分区用于存放 bin 文件，第 2 个分区用于作为数据存储分区，分区格式为 `FAT32`。 -2. 将根目录下的 `fip.bin` 和 `boot.sd` 复制 SD 卡第一个分区中。后续更新固件只需要复制 `boot.sd` 文件即可。 -其中： -- fip.bin：fsbl、 opensbi 和 uboot 打包后的 bin 文件 -- boot.sd：kernel 打包后的 bin 文件 - -更新完 `boot.sd` 后， 重新上电可以看到串口的输出信息： -```shell -U-Boot 2021.10 (Jun 26 2023 - 14:09:06 +0800)cvitek_cv180x - -DRAM: 63.3 MiB -gd->relocaddr=0x82435000. offset=0x2235000 -MMC: cv-sd@4310000: 0 -Loading Environment from ... OK -In: serial -Out: serial -Err: serial -Net: -Warning: ethernet@4070000 (eth0) using random MAC address - 62:80:19:6c:d4:64 -eth0: ethernet@4070000 -Hit any key to stop autoboot: 0 -Boot from SD ... -switch to partitions #0, OK -mmc0 is current device -132692 bytes read in 12 ms (10.5 MiB/s) -## Loading kernel from FIT Image at 81400000 ... - Using 'config-cv1800b_milkv_duo_sd' configuration - Trying 'kernel-1' kernel subimage - Verifying Hash Integrity ... crc32+ OK -## Loading fdt from FIT Image at 81400000 ... - Using 'config-cv1800b_milkv_duo_sd' configuration - Trying 'fdt-cv1800b_milkv_duo_sd' fdt subimage - Verifying Hash Integrity ... sha256+ OK - Booting using the fdt blob at 0x8141b590 - Uncompressing Kernel Image - Decompressing 296768 bytes used 42ms - Loading Device Tree to 0000000081be5000, end 0000000081becb60 ... OK - -Starting kernel ... - -heap: [0x802766b0 - 0x812766b0] - - \ | / -- RT - Thread Smart Operating System - / | \ 5.0.1 build Jun 28 2023 23:44:36 - 2006 - 2022 Copyright by RT-Thread team -Hello RT-Smart! -msh /> -``` -## 驱动支持列表 - -| 驱动 | 支持情况 | 备注 | -| :--- | :------- | :---------------- | -| UART | 支持 | 默认波特率115200 | - - -## 支持开发板 -- milk-v duo: [https://milkv.io/duo](https://milkv.io/duo) - -## 联系人信息 - -维护人：[flyingcys](https://github.com/flyingcys) \ No newline at end of file diff --git a/bsp/cvitek/cv1800b/README_en.md b/bsp/cvitek/cv1800b/README_en.md deleted file mode 100755 index 19da2982c8..0000000000 --- a/bsp/cvitek/cv1800b/README_en.md +++ /dev/null @@ -1,130 +0,0 @@ -[中文](README.md) | **English** - -## Overview -CV180ZB/CV1800B/CV1801B are high-performance, low-power chips designed for consumer surveillance IP cameras, smart home devices, and other product areas. They integrate H.264/H.265 video compression encoders and ISPs, and support various image enhancement and correction algorithms such as digital wide dynamic range, 3D noise reduction, defogging, and lens distortion correction, providing professional-grade video image quality to customers. - -1. Processor Core -- Main processor: RISCV C906 @ 1.0Ghz - - 32KB I-cache, 64KB D-Cache - - Integrated vector and floating-point units (FPU). -- Coprocessor: RISCV C906 @ 700Mhz - - Integrated floating-point unit (FPU). - -2. Memory Interface -- Built-in DRAM: DDR2 16bitx1, with a maximum speed of 1333Mbps, capacity of 512Mbit (64MB). -- Support for SPI NOR flash interface (1.8V / 3.0V) - - Support for 1, 2, 4-wire modes - - Maximum support of 256MBytes -- Support for SPI Nand flash interface (1.8V / 3.0V) - - Support for 1KB/2KB/4KB page (corresponding to a maximum capacity of 16GB/32GB/64GB) - - Use the built-in ECC module of the device itself - -3. Peripherals -- Up to 26 GPIO pins on the MilkV-Duo 40-pin header provide access to internal peripherals such as SDIO, I2C, PWM, SPI, J-TAG, and UART. -- Up to 3x I2C -- Up to 5x UART -- Up to 1x SDIO1 -- Up to 1x SPI -- Up to 2x ADC -- Up to 7x PWM -- Up to 1x RUN -- Up to 1x JTAG -- Integrated MAC PHY supporting 10/100Mbps full-duplex or half-duplex mode -- One USB Host / device interface - -## Toolchain Download -Download the `riscv64-unknown-linux-musl-gcc` toolchain from: [https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2](https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2) - -> Note: -The current BSP only supports Linux compilation. - -After correct extraction, add the local path of the `riscv64-unknown-linux-musl-gcc` toolchain to `EXEC_PATH` in `rtconfig.py`, or specify the path through the `RTT_EXEC_PATH` environment variable. - -```shell -$ export RTT_EXEC_PATH=/opt/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu/bin -``` - -## Compilation -1. Installing Dependencies -```shell -$ sudo apt install -y device-tree-compiler -``` -On the Linux platform, you can execute: - -```shell -$ scons --menuconfig -``` -It will automatically download environment-related scripts to the ~/.env directory, and then execute -```shell -$ source ~/.env/env.sh -$ pkgs --update -``` - -After updating the software packages, use `scons -j10` or `scons -j10 --verbose` to compile this board support package. Alternatively, you can use the command `scons --exec-path="GCC_toolchain_path"` to specify the toolchain location for compilation. If the compilation is successful, an rtthread.elf file will be generated. - -After the compilation is completed, the script automatically calls the `./mksdimg.sh` script to package and generate the `boot.sd` file, which is the kernel file for SD card boot. - -## Running -1. Divide the SD card into 2 partitions, with the first partition used to store bin files and the second partition used as a data storage partition. The partition format is FAT32. - -2. Copy the `fip.bin` and `boot.sd` files from the root directory to the first partition of the SD card. For subsequent firmware updates, you only need to copy the `boot.sd` file. -Where: -- fip.bin: the bin file after fsbl、opensbi and U-Boot are packaged -- boot.sd: the bin file after the kernel is packaged - -After updating `boot.sd`, power on again and you will see the serial output information: - -```shell -U-Boot 2021.10 (Jun 26 2023 - 14:09:06 +0800)cvitek_cv180x - -DRAM: 63.3 MiB -gd->relocaddr=0x82435000. offset=0x2235000 -MMC: cv-sd@4310000: 0 -Loading Environment from ... OK -In: serial -Out: serial -Err: serial -Net: -Warning: ethernet@4070000 (eth0) using random MAC address - 62:80:19:6c:d4:64 -eth0: ethernet@4070000 -Hit any key to stop autoboot: 0 -Boot from SD ... -switch to partitions #0, OK -mmc0 is current device -132692 bytes read in 12 ms (10.5 MiB/s) -## Loading kernel from FIT Image at 81400000 ... - Using 'config-cv1800b_milkv_duo_sd' configuration - Trying 'kernel-1' kernel subimage - Verifying Hash Integrity ... crc32+ OK -## Loading fdt from FIT Image at 81400000 ... - Using 'config-cv1800b_milkv_duo_sd' configuration - Trying 'fdt-cv1800b_milkv_duo_sd' fdt subimage - Verifying Hash Integrity ... sha256+ OK - Booting using the fdt blob at 0x8141b590 - Uncompressing Kernel Image - Decompressing 296768 bytes used 42ms - Loading Device Tree to 0000000081be5000, end 0000000081becb60 ... OK - -Starting kernel ... - -heap: [0x802766b0 - 0x812766b0] - - \ | / -- RT - Thread Smart Operating System - / | \ 5.0.1 build Jun 28 2023 23:44:36 - 2006 - 2022 Copyright by RT-Thread team -Hello RT-Smart! -msh /> -``` -## Driver Support List - -| Driver | Support Status | Remarks | -| :----- | :------------- | :--------------------- | -| UART | Supported | Default baud rate 115200 | - -## Supported Development Boards -- milk-v duo: [https://milkv.io/duo](https://milkv.io/duo) - -## Contact information - -Maintenance person：[flyingcys](https://github.com/flyingcys) diff --git a/bsp/cvitek/cv1800b/SConscript b/bsp/cvitek/cv1800b/SConscript deleted file mode 100755 index c7ef7659ec..0000000000 --- a/bsp/cvitek/cv1800b/SConscript +++ /dev/null @@ -1,14 +0,0 @@ -# for module compiling -import os -from building import * - -cwd = GetCurrentDir() -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/cvitek/cv1800b/SConstruct b/bsp/cvitek/cv1800b/SConstruct deleted file mode 100755 index 6ffc4cd71a..0000000000 --- a/bsp/cvitek/cv1800b/SConstruct +++ /dev/null @@ -1,48 +0,0 @@ -import os -import sys -import rtconfig - -from rtconfig import RTT_ROOT - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -from building import * - -TARGET = 'rtthread.' + rtconfig.TARGET_EXT - -DefaultEnvironment(tools=[]) -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, - CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) -env['ASCOM'] = env['ASPPCOM'] - -Export('RTT_ROOT') -Export('rtconfig') -rtconfig.CPU='virt64' -rtconfig.ARCH='risc-v' - -stack_size = 4096 - -stack_lds = open('link_stacksize.lds', 'w') -if GetDepend('__STACKSIZE__'): stack_size = GetDepend('__STACKSIZE__') -stack_lds.write('__STACKSIZE__ = %d;\n' % stack_size) -stack_lds.close() - -SDK_ROOT = os.path.abspath('./') - -if os.path.exists(SDK_ROOT + '/drivers'): - drivers_path_prefix = SDK_ROOT + '/drivers' -else: - drivers_path_prefix = os.path.dirname(SDK_ROOT) + '/drivers' - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False) - -# include libraries -objs.extend(SConscript(drivers_path_prefix + '/SConscript', variant_dir='build/drivers', duplicate=0)) - -# make a building -DoBuilding(TARGET, objs) diff --git a/bsp/cvitek/cv1800b/applications/SConscript b/bsp/cvitek/cv1800b/applications/SConscript deleted file mode 100755 index c583d3016e..0000000000 --- a/bsp/cvitek/cv1800b/applications/SConscript +++ /dev/null @@ -1,9 +0,0 @@ -from building import * - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd] - -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/cvitek/cv1800b/applications/main.c b/bsp/cvitek/cv1800b/applications/main.c deleted file mode 100755 index a8afc8b0f9..0000000000 --- a/bsp/cvitek/cv1800b/applications/main.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2023/06/25 flyingcys first version - */ - -#include -#include - -int main(void) -{ - rt_kprintf("Hello RT-Smart!\n"); - - return 0; -} diff --git a/bsp/cvitek/cv1800b/board/Kconfig b/bsp/cvitek/cv1800b/board/Kconfig deleted file mode 100755 index 82f7886f09..0000000000 --- a/bsp/cvitek/cv1800b/board/Kconfig +++ /dev/null @@ -1,64 +0,0 @@ -menu "General Drivers Configuration" - - menuconfig BSP_USING_UART - bool "Using UART" - select RT_USING_SERIAL - default y - - if BSP_USING_UART - config RT_USING_UART0 - bool "Enable UART 0" - default y - - config UART_IRQ_BASE - int - default 44 - - config RT_USING_UART1 - bool "Enable UART 1" - default n - - config RT_USING_UART2 - bool "Enable UART 2" - default n - - config RT_USING_UART3 - bool "Enable UART 3" - default n - - config RT_USING_UART4 - bool "Enable UART 4" - default n - - endif - - config BSP_USING_ADC - bool "Using ADC" - select RT_USING_ADC - default n - - menuconfig BSP_USING_PWM - bool "Using PWM" - select RT_USING_PWM - default n - - if BSP_USING_PWM - config BSP_USING_PWM0 - bool "Enable PWM 0" - default n - - config BSP_USING_PWM1 - bool "Enable PWM 1" - default n - - config BSP_USING_PWM2 - bool "Enable PWM 2" - default n - - config BSP_USING_PWM3 - bool "Enable PWM 3" - default n - - endif - -endmenu diff --git a/bsp/cvitek/cv1800b/board/SConscript b/bsp/cvitek/cv1800b/board/SConscript deleted file mode 100755 index 4488cae073..0000000000 --- a/bsp/cvitek/cv1800b/board/SConscript +++ /dev/null @@ -1,9 +0,0 @@ -from building import * - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') + Glob('*.S') -CPPPATH = [cwd] - -group = DefineGroup('Driver', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/cvitek/cv1800b/board/board.c b/bsp/cvitek/cv1800b/board/board.c deleted file mode 100755 index 6df8cd7a23..0000000000 --- a/bsp/cvitek/cv1800b/board/board.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2023/06/25 flyingcys first version - */ -#include -#include - -#include "board.h" - -#include "sbi.h" - -#ifdef RT_USING_SMART -#include "riscv_mmu.h" -#include "mmu.h" -#include "page.h" -#include "lwp_arch.h" - -rt_region_t init_page_region = {(rt_size_t)RT_HW_PAGE_START, (rt_size_t)RT_HW_PAGE_END}; - -extern size_t MMUTable[]; - -struct mem_desc platform_mem_desc[] = { - {KERNEL_VADDR_START, (rt_size_t)RT_HW_PAGE_END - 1, (rt_size_t)ARCH_MAP_FAILED, NORMAL_MEM}, - {0x1000, ((KERNEL_VADDR_START - 1) & 0xfffff000) - 1, (rt_size_t)ARCH_MAP_FAILED, DEVICE_MEM}, -}; - -#define NUM_MEM_DESC (sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0])) - -#endif /* RT_USING_SMART */ - -void init_bss(void) -{ - unsigned int *dst; - - dst = &__bss_start; - while (dst < &__bss_end) - { - *dst++ = 0; - } -} - -static void __rt_assert_handler(const char *ex_string, const char *func, rt_size_t line) -{ - rt_kprintf("(%s) assertion failed at function:%s, line number:%d \n", ex_string, func, line); - asm volatile("ebreak" :: - : "memory"); -} - -void primary_cpu_entry(void) -{ - /* disable global interrupt */ - rt_hw_interrupt_disable(); - rt_assert_set_hook(__rt_assert_handler); - - entry(); -} - -#define IOREMAP_SIZE (1ul << 30) - -#ifndef ARCH_KERNEL_IN_HIGH_VA -#define IOREMAP_VEND USER_VADDR_START -#else -#define IOREMAP_VEND 0ul -#endif - -void rt_hw_board_init(void) -{ -#ifdef RT_USING_SMART - /* init data structure */ - rt_hw_mmu_map_init(&rt_kernel_space, (void *)(IOREMAP_VEND - IOREMAP_SIZE), IOREMAP_SIZE, (rt_size_t *)MMUTable, PV_OFFSET); - - /* init page allocator */ - rt_page_init(init_page_region); - - /* setup region, and enable MMU */ - rt_hw_mmu_setup(&rt_kernel_space, platform_mem_desc, NUM_MEM_DESC); -#endif - - /* initialize memory system */ -#ifdef RT_USING_HEAP - rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); -#endif - - /* initalize interrupt */ - rt_hw_interrupt_init(); - - /* init rtthread hardware */ - rt_hw_tick_init(); - -#ifdef RT_USING_SERIAL - rt_hw_uart_init(); -#endif - -#ifdef RT_USING_CONSOLE - /* set console device */ - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); -#endif /* RT_USING_CONSOLE */ - -#ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); -#endif - -#ifdef RT_USING_HEAP - rt_kprintf("heap: [0x%08x - 0x%08x]\n", (rt_ubase_t)RT_HW_HEAP_BEGIN, (rt_ubase_t)RT_HW_HEAP_END); -#endif /* RT_USING_HEAP */ -} diff --git a/bsp/cvitek/cv1800b/board/board.h b/bsp/cvitek/cv1800b/board/board.h deleted file mode 100755 index efcfa3bd36..0000000000 --- a/bsp/cvitek/cv1800b/board/board.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2023/06/25 flyingcys first version - */ - -#ifndef BOARD_H__ -#define BOARD_H__ - -#include -#include "drv_uart.h" -#include "tick.h" - -extern unsigned int __bss_start; -extern unsigned int __bss_end; - -#ifndef RT_USING_SMART -#define KERNEL_VADDR_START 0x0 -#endif - -#define RT_HW_HEAP_BEGIN ((void *)&__bss_end) -#define RT_HW_HEAP_END ((void *)(RT_HW_HEAP_BEGIN + 16 * 1024 * 1024)) -#define RT_HW_PAGE_START RT_HW_HEAP_END -#define RT_HW_PAGE_END ((void *)(KERNEL_VADDR_START + 32 * 1024 * 1024)) - -void rt_hw_board_init(void); - -#endif diff --git a/bsp/cvitek/cv1800b/cv1800b_milkv_duo_sd.dtb b/bsp/cvitek/cv1800b/cv1800b_milkv_duo_sd.dtb deleted file mode 100755 index ff3823c663..0000000000 Binary files a/bsp/cvitek/cv1800b/cv1800b_milkv_duo_sd.dtb and /dev/null differ diff --git a/bsp/cvitek/cv1800b/link.lds b/bsp/cvitek/cv1800b/link.lds deleted file mode 100755 index 891669e03c..0000000000 --- a/bsp/cvitek/cv1800b/link.lds +++ /dev/null @@ -1,197 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020/12/12 bernard The first version - */ - -INCLUDE "link_stacksize.lds" - -OUTPUT_ARCH( "riscv" ) - -/* - * Memory layout: - * 0x10200000 - 0x10201000: Bootloader - * 0x10201000 - 0x10A00000: Kernel - * 0x10A00000 - 0x11200000: Heap - */ - -MEMORY -{ - SRAM : ORIGIN = 0x80200000, LENGTH = 32M -} - -ENTRY(_start) -SECTIONS -{ - . = 0x80200000 ; - - /* __STACKSIZE__ = 4096; */ - __text_start = .; - .start : - { - *(.start); - } > SRAM - - . = ALIGN(8); - - .text : - { - *(.text) /* remaining code */ - *(.text.*) /* remaining code */ - *(.rodata) /* read-only data (constants) */ - *(.rodata*) - *(.glue_7) - *(.glue_7t) - *(.gnu.linkonce.t*) - - /* section information for finsh shell */ - . = ALIGN(8); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(8); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(8); - - /* section information for initial. */ - . = ALIGN(8); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(8); - - __rt_utest_tc_tab_start = .; - KEEP(*(UtestTcTab)) - __rt_utest_tc_tab_end = .; - - . = ALIGN(8); - _etext = .; - } > SRAM - - .eh_frame_hdr : - { - *(.eh_frame_hdr) - *(.eh_frame_entry) - } > SRAM - .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM - - . = ALIGN(8); - __text_end = .; - __text_size = __text_end - __text_start; - - .data : - { - *(.data) - *(.data.*) - - *(.data1) - *(.data1.*) - - . = ALIGN(8); - PROVIDE( __global_pointer$ = . + 0x800 ); - - *(.sdata) - *(.sdata.*) - } > SRAM - - . = ALIGN(8); - .ctors : - { - PROVIDE(__ctors_start__ = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__ctors_end__ = .); - } > SRAM - - .dtors : - { - PROVIDE(__dtors_start__ = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE(__dtors_end__ = .); - } > SRAM - - /* stack for dual core */ - .stack : - { - . = ALIGN(64); - __stack_start__ = .; - - . += __STACKSIZE__; - __stack_cpu0 = .; - - . += __STACKSIZE__; - __stack_cpu1 = .; - } > SRAM - - . = ALIGN(8); - - .osdebug : - { - _osdebug_start = .; - . += 87K; - _osdebug_end = .; - } > SRAM - - . = ALIGN(8); - - .sbss : - { - __bss_start = .; - *(.sbss) - *(.sbss.*) - *(.dynsbss) - *(.scommon) - } > SRAM - - .bss : - { - *(.bss) - *(.bss.*) - *(.dynbss) - *(COMMON) - __bss_end = .; - } > SRAM - - _end = .; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/bsp/cvitek/cv1800b/link_stacksize.lds b/bsp/cvitek/cv1800b/link_stacksize.lds deleted file mode 100755 index 28438c7da1..0000000000 --- a/bsp/cvitek/cv1800b/link_stacksize.lds +++ /dev/null @@ -1 +0,0 @@ -__STACKSIZE__ = 4096; diff --git a/bsp/cvitek/cv1800b/mkimage b/bsp/cvitek/cv1800b/mkimage deleted file mode 100755 index 6a720c3fb0..0000000000 Binary files a/bsp/cvitek/cv1800b/mkimage and /dev/null differ diff --git a/bsp/cvitek/cv1800b/mksdimg.sh b/bsp/cvitek/cv1800b/mksdimg.sh deleted file mode 100755 index 60dd65a076..0000000000 --- a/bsp/cvitek/cv1800b/mksdimg.sh +++ /dev/null @@ -1,7 +0,0 @@ -#/bin/sh -set -e -echo "start compress kernel..." - -lzma -c -9 -f -k Image > Image.lzma - -./mkimage -f multi.its -r ../boot.sd \ No newline at end of file diff --git a/bsp/cvitek/cv1800b/multi.its b/bsp/cvitek/cv1800b/multi.its deleted file mode 100755 index 8403466927..0000000000 --- a/bsp/cvitek/cv1800b/multi.its +++ /dev/null @@ -1,56 +0,0 @@ -/* - * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs - */ - -/dts-v1/; - -/ { - description = "Various kernels, ramdisks and FDT blobs"; - #address-cells = <2>; - - images { - kernel-1 { - description = "cvitek kernel"; - data = /incbin/("./Image.lzma"); - type = "kernel"; - arch = "riscv"; - os = "linux"; - compression = "lzma"; - load = <0x0 0x80200000>; - entry = <0x0 0x80200000>; - hash-2 { - algo = "crc32"; - }; - }; - - - /*FDT*/ - - fdt-cv1800b_milkv_duo_sd { - description = "cvitek device tree - cv1800b_milkv_duo_sd"; - data = /incbin/("./cv1800b_milkv_duo_sd.dtb"); - type = "flat_dt"; - arch = "riscv"; - compression = "none"; - hash-1 { - algo = "sha256"; - }; - }; - - - - }; - - /*CFG*/ - configurations { - - config-cv1800b_milkv_duo_sd { - description = "boot cvitek system with board cv1800b_milkv_duo_sd"; - kernel = "kernel-1"; - fdt = "fdt-cv1800b_milkv_duo_sd"; - }; - - }; - - -}; diff --git a/bsp/cvitek/cv1800b/rtconfig.h b/bsp/cvitek/cv1800b/rtconfig.h deleted file mode 100755 index 236544eee3..0000000000 --- a/bsp/cvitek/cv1800b/rtconfig.h +++ /dev/null @@ -1,320 +0,0 @@ -#ifndef RT_CONFIG_H__ -#define RT_CONFIG_H__ - -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Project Configuration */ - -/* RT-Thread Kernel */ - -#define RT_NAME_MAX 8 -#define RT_USING_SMART -#define RT_CPUS_NR 1 -#define RT_ALIGN_SIZE 8 -#define RT_THREAD_PRIORITY_32 -#define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK -#define RT_USING_HOOK -#define RT_HOOK_USING_FUNC_PTR -#define RT_USING_IDLE_HOOK -#define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 1024 -#define RT_USING_TIMER_SOFT -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 2048 - -/* kservice optimization */ - -#define RT_KSERVICE_USING_STDLIB -#define RT_KPRINTF_USING_LONGLONG -#define RT_USING_DEBUG -#define RT_DEBUGING_COLOR -#define RT_DEBUGING_CONTEXT - -/* Inter-Thread communication */ - -#define RT_USING_SEMAPHORE -#define RT_USING_MUTEX -#define RT_USING_EVENT -#define RT_USING_MAILBOX -#define RT_USING_MESSAGEQUEUE - -/* Memory Management */ - -#define RT_PAGE_MAX_ORDER 11 -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM -#define RT_USING_SMALL_MEM_AS_HEAP -#define RT_USING_HEAP -#define RT_USING_DEVICE -#define RT_USING_DEVICE_OPS -#define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 256 -#define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x50100 -#define RT_USING_STDC_ATOMIC -#define RT_BACKTRACE_LEVEL_MAX_NR 32 -#define ARCH_CPU_64BIT -#define RT_USING_CACHE -#define ARCH_MM_MMU -#define KERNEL_VADDR_START 0x80000000 -#define ARCH_RISCV -#define ARCH_RISCV64 - -/* RT-Thread Components */ - -#define RT_USING_COMPONENTS_INIT -#define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 6144 -#define RT_MAIN_THREAD_PRIORITY 10 -#define RT_USING_MSH -#define RT_USING_FINSH -#define FINSH_USING_MSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 -#define FINSH_USING_HISTORY -#define FINSH_HISTORY_LINES 5 -#define FINSH_USING_SYMTAB -#define FINSH_CMD_SIZE 80 -#define MSH_USING_BUILT_IN_COMMANDS -#define FINSH_USING_DESCRIPTION -#define FINSH_ARG_MAX 10 -#define FINSH_USING_OPTION_COMPLETION - -/* DFS: device virtual file system */ - -#define RT_USING_DFS -#define DFS_USING_POSIX -#define DFS_USING_WORKDIR -#define DFS_FD_MAX 16 -#define RT_USING_DFS_V2 -#define RT_USING_DFS_DEVFS -#define RT_USING_PAGECACHE - -/* page cache config */ - -#define RT_PAGECACHE_COUNT 4096 -#define RT_PAGECACHE_ASPACE_COUNT 1024 -#define RT_PAGECACHE_PRELOAD 4 -#define RT_PAGECACHE_HASH_NR 1024 -#define RT_PAGECACHE_GC_WORK_LEVEL 90 -#define RT_PAGECACHE_GC_STOP_LEVEL 70 - -/* Device Drivers */ - -#define RT_USING_DEVICE_IPC -#define RT_UNAMED_PIPE_NUMBER 64 -#define RT_USING_SYSTEM_WORKQUEUE -#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 -#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 -#define RT_USING_SERIAL -#define RT_USING_SERIAL_V1 -#define RT_SERIAL_USING_DMA -#define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_TTY -#define RT_USING_NULL -#define RT_USING_ZERO -#define RT_USING_RANDOM -#define RT_USING_RTC -#define RT_USING_PIN -#define RT_USING_KTIME - -/* Using USB */ - - -/* C/C++ and POSIX layer */ - -/* ISO-ANSI C layer */ - -/* Timezone and Daylight Saving Time */ - -#define RT_LIBC_USING_LIGHT_TZ_DST -#define RT_LIBC_TZ_DEFAULT_HOUR 8 -#define RT_LIBC_TZ_DEFAULT_MIN 0 -#define RT_LIBC_TZ_DEFAULT_SEC 0 - -/* POSIX (Portable Operating System Interface) layer */ - -#define RT_USING_POSIX_FS -#define RT_USING_POSIX_DEVIO -#define RT_USING_POSIX_STDIO -#define RT_USING_POSIX_TERMIOS -#define RT_USING_POSIX_DELAY -#define RT_USING_POSIX_CLOCK -#define RT_USING_POSIX_TIMER - -/* Interprocess Communication (IPC) */ - - -/* Socket is in the 'Network' category */ - - -/* Network */ - - -/* Memory protection */ - - -/* Utilities */ - -#define RT_USING_RESOURCE_ID -#define RT_USING_ADT -#define RT_USING_ADT_AVL -#define RT_USING_ADT_BITMAP -#define RT_USING_ADT_HASHMAP -#define RT_USING_ADT_REF -#define RT_USING_LWP -#define RT_LWP_MAX_NR 30 -#define LWP_TASK_STACK_SIZE 16384 -#define RT_CH_MSG_MAX_NR 1024 -#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024 -#define LWP_TID_MAX_NR 64 -#define RT_LWP_SHM_MAX_NR 64 -#define RT_USING_LDSO - -/* Memory management */ - - -/* RT-Thread Utestcases */ - - -/* RT-Thread online packages */ - -/* IoT - internet of things */ - - -/* Wi-Fi */ - -/* Marvell WiFi */ - - -/* Wiced WiFi */ - - -/* CYW43012 WiFi */ - - -/* BL808 WiFi */ - - -/* CYW43439 WiFi */ - - -/* IoT Cloud */ - - -/* security packages */ - - -/* language packages */ - -/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ - - -/* XML: Extensible Markup Language */ - - -/* multimedia packages */ - -/* LVGL: powerful and easy-to-use embedded GUI library */ - - -/* u8g2: a monochrome graphic library */ - - -/* tools packages */ - - -/* system packages */ - -/* enhanced kernel services */ - - -/* acceleration: Assembly language or algorithmic acceleration packages */ - - -/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ - - -/* Micrium: Micrium software products porting for RT-Thread */ - - -/* peripheral libraries and drivers */ - -/* HAL & SDK Drivers */ - -/* STM32 HAL & SDK Drivers */ - - -/* Kendryte SDK */ - - -/* sensors drivers */ - - -/* touch drivers */ - - -/* AI packages */ - - -/* Signal Processing and Control Algorithm Packages */ - - -/* miscellaneous packages */ - -/* project laboratory */ - -/* samples: kernel and components samples */ - - -/* entertainment: terminal games and other interesting software packages */ - - -/* Arduino libraries */ - - -/* Projects and Demos */ - - -/* Sensors */ - - -/* Display */ - - -/* Timing */ - - -/* Data Processing */ - - -/* Data Storage */ - -/* Communication */ - - -/* Device Control */ - - -/* Other */ - - -/* Signal IO */ - - -/* Uncategorized */ - -/* General Drivers Configuration */ - -#define BSP_USING_UART -#define RT_USING_UART0 -#define UART_IRQ_BASE 44 -#define BSP_USING_CV1800B -#define C906_PLIC_PHY_ADDR 0x70000000 -#define IRQ_MAX_NR 64 -#define TIMER_CLK_FREQ 25000000 -#define __STACKSIZE__ 4096 - -#endif diff --git a/bsp/cvitek/cv1800b/rtconfig.py b/bsp/cvitek/cv1800b/rtconfig.py deleted file mode 100755 index 0914d5c010..0000000000 --- a/bsp/cvitek/cv1800b/rtconfig.py +++ /dev/null @@ -1,59 +0,0 @@ -import os - -# toolchains options -ARCH ='risc-v' -VENDOR ='t-head' -CPU ='c906' -CROSS_TOOL ='gcc' - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = r'../../..' - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') - -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'/opt/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu/bin' -else: - print('Please make sure your toolchains is GNU GCC!') - exit(0) - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # toolchains - #PREFIX = 'riscv64-unknown-elf-' - PREFIX = os.getenv('RTT_CC_PREFIX') or 'riscv64-unknown-linux-musl-' - CC = PREFIX + 'gcc' - CXX = PREFIX + 'g++' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcmodel=medany -march=rv64imafdc -mabi=lp64' - CFLAGS = DEVICE + ' -Wno-cpp -fvar-tracking -ffreestanding -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -D_POSIX_SOURCE ' - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__' - LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds' + ' -lsupc++ -lgcc -static' - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -ggdb' - AFLAGS += ' -ggdb' - else: - CFLAGS += ' -O2 -Os' - - CXXFLAGS = CFLAGS - -DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtthread.asm\n' -POST_ACTION = OBJCPY + ' -O binary $TARGET Image\n' + SIZE + ' $TARGET \n' + './mksdimg.sh\n' diff --git a/bsp/cvitek/cv180x/.config b/bsp/cvitek/cv180x/.config new file mode 100644 index 0000000000..306a0d77ca --- /dev/null +++ b/bsp/cvitek/cv180x/.config @@ -0,0 +1,1139 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +CONFIG_RT_USING_SMART=y +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048 + +# +# kservice optimization +# +CONFIG_RT_KSERVICE_USING_STDLIB=y +# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +CONFIG_RT_KPRINTF_USING_LONGLONG=y +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_DEBUGING_PAGE_LEAK is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_PAGE_MAX_ORDER=11 +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +CONFIG_RT_USING_DEVICE=y +CONFIG_RT_USING_DEVICE_OPS=y +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +# CONFIG_RT_USING_SCHED_THREAD_CTX is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=256 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50100 +CONFIG_RT_USING_STDC_ATOMIC=y +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +CONFIG_ARCH_CPU_64BIT=y +CONFIG_RT_USING_CACHE=y +# CONFIG_RT_USING_HW_ATOMIC is not set +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_MM_MMU=y +CONFIG_KERNEL_VADDR_START=0x80000000 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV64=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=6144 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FD_MAX=16 +CONFIG_RT_USING_DFS_V2=y +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_MQUEUE is not set +CONFIG_RT_USING_PAGECACHE=y + +# +# page cache config +# +CONFIG_RT_PAGECACHE_COUNT=4096 +CONFIG_RT_PAGECACHE_ASPACE_COUNT=1024 +CONFIG_RT_PAGECACHE_PRELOAD=4 +CONFIG_RT_PAGECACHE_HASH_NR=1024 +CONFIG_RT_PAGECACHE_GC_WORK_LEVEL=90 +CONFIG_RT_PAGECACHE_GC_STOP_LEVEL=70 +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +CONFIG_RT_USING_TTY=y +# CONFIG_RT_TTY_DEBUG is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +CONFIG_RT_USING_NULL=y +CONFIG_RT_USING_ZERO=y +CONFIG_RT_USING_RANDOM=y +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +CONFIG_RT_USING_KTIME=y +# CONFIG_RT_USING_HWTIMER is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 + +# +# POSIX (Portable Operating System Interface) layer +# +CONFIG_RT_USING_POSIX_FS=y +CONFIG_RT_USING_POSIX_DEVIO=y +CONFIG_RT_USING_POSIX_STDIO=y +# CONFIG_RT_USING_POSIX_POLL is not set +# CONFIG_RT_USING_POSIX_SELECT is not set +# CONFIG_RT_USING_POSIX_EVENTFD is not set +# CONFIG_RT_USING_POSIX_EPOLL is not set +# CONFIG_RT_USING_POSIX_SIGNALFD is not set +# CONFIG_RT_USING_POSIX_TIMERFD is not set +# CONFIG_RT_USING_POSIX_SOCKET is not set +CONFIG_RT_USING_POSIX_TERMIOS=y +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_POSIX_MMAN is not set +CONFIG_RT_USING_POSIX_DELAY=y +CONFIG_RT_USING_POSIX_CLOCK=y +CONFIG_RT_USING_POSIX_TIMER=y +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +CONFIG_RT_USING_RESOURCE_ID=y +CONFIG_RT_USING_ADT=y +CONFIG_RT_USING_ADT_AVL=y +CONFIG_RT_USING_ADT_BITMAP=y +CONFIG_RT_USING_ADT_HASHMAP=y +CONFIG_RT_USING_ADT_REF=y +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set +CONFIG_RT_USING_LWP=y +# CONFIG_LWP_DEBUG is not set +CONFIG_RT_LWP_MAX_NR=30 +CONFIG_LWP_TASK_STACK_SIZE=16384 +CONFIG_RT_CH_MSG_MAX_NR=1024 +CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 +CONFIG_LWP_TID_MAX_NR=64 +CONFIG_RT_LWP_SHM_MAX_NR=64 +# CONFIG_LWP_UNIX98_PTY is not set +CONFIG_RT_USING_LDSO=y +# CONFIG_ELF_DEBUG_ENABLE is not set +# CONFIG_ELF_LOAD_RANDOMIZE is not set + +# +# Memory management +# +# CONFIG_RT_USING_MEMBLOCK is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_NUCLEI_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# + +# +# General Drivers Configuration +# +CONFIG_BSP_USING_UART=y +CONFIG_RT_USING_UART0=y +CONFIG_UART_IRQ_BASE=44 +# CONFIG_RT_USING_UART1 is not set +# CONFIG_RT_USING_UART2 is not set +# CONFIG_RT_USING_UART3 is not set +# CONFIG_RT_USING_UART4 is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_PWM is not set +CONFIG_BSP_USING_CV180X=y +CONFIG_C906_PLIC_PHY_ADDR=0x70000000 +CONFIG_IRQ_MAX_NR=64 +CONFIG_TIMER_CLK_FREQ=25000000 +CONFIG___STACKSIZE__=4096 +CONFIG_BOARD_TYPE_MILKV_DUO=y diff --git a/bsp/cvitek/cv180x/.gitignore b/bsp/cvitek/cv180x/.gitignore new file mode 100755 index 0000000000..f58350d6cf --- /dev/null +++ b/bsp/cvitek/cv180x/.gitignore @@ -0,0 +1,5 @@ +cv1800b_milkv_duo_sd.dtb +Image +Image.lzma +multi.its +boot.sd \ No newline at end of file diff --git a/bsp/cvitek/cv180x/Kconfig b/bsp/cvitek/cv180x/Kconfig new file mode 100755 index 0000000000..2758a776fb --- /dev/null +++ b/bsp/cvitek/cv180x/Kconfig @@ -0,0 +1,55 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "board/Kconfig" + +config BSP_USING_CV180X + bool + select ARCH_RISCV64 + select RT_USING_SYSTEM_WORKQUEUE + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select RT_USING_CACHE + select ARCH_MM_MMU + select RT_USING_DEVICE_OPS + default y + +config C906_PLIC_PHY_ADDR + hex + default 0x70000000 + +config IRQ_MAX_NR + int + default 64 + +config TIMER_CLK_FREQ + int + default 25000000 + +config __STACKSIZE__ + int "stack size for interrupt" + default 4096 + +choice + prompt "Board Type" + default BOARD_TYPE_MILKV_DUO + + config BOARD_TYPE_MILKV_DUO + bool "milkv-duo" +endchoice diff --git a/bsp/cvitek/cv180x/README.md b/bsp/cvitek/cv180x/README.md new file mode 100755 index 0000000000..006c07ee1a --- /dev/null +++ b/bsp/cvitek/cv180x/README.md @@ -0,0 +1,132 @@ + **中文** | [English](README_en.md) + +## 概述 +CV180ZB/CV1800B/CV1801B 是面向民用消费监控 IP 摄像机、居家智能等多项产品领域而推出的高性能、低功耗芯片，集成了 H.264/H.265 视频压缩编码器和 ISP；支持数字寛动态、 3D 降噪、除雾、镜头畸变校正等多种图像增强和矫正算法，为客户提供专业级的视频图像质量。 + +1. 处理器内核 + +- 主处理器 RISCV C906 @ 1.0Ghz + - 32KB I-cache, 64KB D-Cache + - 集成矢量(Vector)及浮点运算单元 (FPU) . +- 协处理器 RISCV C906 @ 700Mhz + - 集成浮点运算单元 (FPU) + +2. 存储器接口 +- 内建 DRAM : DDR2 16bitx1, 最高速率达 1333Mbps , 容量512Mbit (64MB) +- 支持SPI NOR flash 接口 (1.8V / 3.0V) + - 支持 1, 2, 4 线模式 + - 最大支持 256MByte +- 支持 SPI Nand flash 接口 (1.8V / 3.0V) + - 支持 1KB/2KB/4KB page (对应的最大容量 16GB/32GB/64GB) + - 使用器件本身内建的 ECC 模块 + +3. 外设 +- Up to 26 GPIO pins on the MilkV-Duo 40-pin header provide access to internal peripherals such as SDIO, I2C, PWM, SPI, J-TAG, and UART +- Up to 3x I2C +- Up to 5x UART +- Up to 1x SDIO1 +- Up to 1x SPI +- Up to 2x ADC +- Up to 7x PWM +- Up to 1x RUN +- Up to 1x JTAG +- 集成 MAC PHY 支持 10/100Mbps 全双工或半双工模式 +- 一个 USB Host / device 接口 + +## Toolchain 下载 +下载 `riscv64-unknown-linux-musl-gcc` 的工具链: [https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2](https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2) + +> 注： +当前 bsp 只支持 Linux 编译 + +正确解压后，在`rtconfig.py`中将 `riscv64-unknown-linux-musl-gcc` 工具链的本地路径加入 `EXEC_PATH` 或通过 `RTT_EXEC_PATH` 环境变量指定路径。 + +```shell +$ export RTT_EXEC_PATH=/opt/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu/bin +``` + +## 编译 +1. 依赖安装 + +```shell +$ sudo apt install -y scons libncurses5-dev device-tree-compiler +``` + +2. Linux平台下，可以先执行： +```shell +$ scons --menuconfig +``` + +它会自动下载env相关脚本到~/.env目录，然后执行 +```shell +$ source ~/.env/env.sh +$ pkgs --update +``` +更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。编译正确无误，会产生 rtthread.elf 文件。 + +编译完成后脚本自动调用 `./mksdimg.sh` 脚本进行打包，并生成 `boot.sd`, 该文件即为 SD 卡启动的 kernel 文件。 + + +## 运行 +1. 将 SD 卡分为 2 个分区，第 1 个分区用于存放 bin 文件，第 2 个分区用于作为数据存储分区，分区格式为 `FAT32`。 +2. 将根目录下的 `fip.bin` 和 `boot.sd` 复制 SD 卡第一个分区中。后续更新固件只需要复制 `boot.sd` 文件即可。 +其中： +- fip.bin：fsbl、 opensbi 和 uboot 打包后的 bin 文件 +- boot.sd：kernel 打包后的 bin 文件 + +更新完 `boot.sd` 后， 重新上电可以看到串口的输出信息： +```shell +U-Boot 2021.10 (Jun 26 2023 - 14:09:06 +0800)cvitek_cv180x + +DRAM: 63.3 MiB +gd->relocaddr=0x82435000. offset=0x2235000 +MMC: cv-sd@4310000: 0 +Loading Environment from ... OK +In: serial +Out: serial +Err: serial +Net: +Warning: ethernet@4070000 (eth0) using random MAC address - 62:80:19:6c:d4:64 +eth0: ethernet@4070000 +Hit any key to stop autoboot: 0 +Boot from SD ... +switch to partitions #0, OK +mmc0 is current device +132692 bytes read in 12 ms (10.5 MiB/s) +## Loading kernel from FIT Image at 81400000 ... + Using 'config-cv1800b_milkv_duo_sd' configuration + Trying 'kernel-1' kernel subimage + Verifying Hash Integrity ... crc32+ OK +## Loading fdt from FIT Image at 81400000 ... + Using 'config-cv1800b_milkv_duo_sd' configuration + Trying 'fdt-cv1800b_milkv_duo_sd' fdt subimage + Verifying Hash Integrity ... sha256+ OK + Booting using the fdt blob at 0x8141b590 + Uncompressing Kernel Image + Decompressing 296768 bytes used 42ms + Loading Device Tree to 0000000081be5000, end 0000000081becb60 ... OK + +Starting kernel ... + +heap: [0x802766b0 - 0x812766b0] + + \ | / +- RT - Thread Smart Operating System + / | \ 5.0.1 build Jun 28 2023 23:44:36 + 2006 - 2022 Copyright by RT-Thread team +Hello RT-Smart! +msh /> +``` +## 驱动支持列表 + +| 驱动 | 支持情况 | 备注 | +| :--- | :------- | :---------------- | +| UART | 支持 | 默认波特率115200 | + + +## 支持开发板 +- milk-v duo: [https://milkv.io/duo](https://milkv.io/duo) + +## 联系人信息 + +维护人：[flyingcys](https://github.com/flyingcys) \ No newline at end of file diff --git a/bsp/cvitek/cv180x/README_en.md b/bsp/cvitek/cv180x/README_en.md new file mode 100755 index 0000000000..19da2982c8 --- /dev/null +++ b/bsp/cvitek/cv180x/README_en.md @@ -0,0 +1,130 @@ +[中文](README.md) | **English** + +## Overview +CV180ZB/CV1800B/CV1801B are high-performance, low-power chips designed for consumer surveillance IP cameras, smart home devices, and other product areas. They integrate H.264/H.265 video compression encoders and ISPs, and support various image enhancement and correction algorithms such as digital wide dynamic range, 3D noise reduction, defogging, and lens distortion correction, providing professional-grade video image quality to customers. + +1. Processor Core +- Main processor: RISCV C906 @ 1.0Ghz + - 32KB I-cache, 64KB D-Cache + - Integrated vector and floating-point units (FPU). +- Coprocessor: RISCV C906 @ 700Mhz + - Integrated floating-point unit (FPU). + +2. Memory Interface +- Built-in DRAM: DDR2 16bitx1, with a maximum speed of 1333Mbps, capacity of 512Mbit (64MB). +- Support for SPI NOR flash interface (1.8V / 3.0V) + - Support for 1, 2, 4-wire modes + - Maximum support of 256MBytes +- Support for SPI Nand flash interface (1.8V / 3.0V) + - Support for 1KB/2KB/4KB page (corresponding to a maximum capacity of 16GB/32GB/64GB) + - Use the built-in ECC module of the device itself + +3. Peripherals +- Up to 26 GPIO pins on the MilkV-Duo 40-pin header provide access to internal peripherals such as SDIO, I2C, PWM, SPI, J-TAG, and UART. +- Up to 3x I2C +- Up to 5x UART +- Up to 1x SDIO1 +- Up to 1x SPI +- Up to 2x ADC +- Up to 7x PWM +- Up to 1x RUN +- Up to 1x JTAG +- Integrated MAC PHY supporting 10/100Mbps full-duplex or half-duplex mode +- One USB Host / device interface + +## Toolchain Download +Download the `riscv64-unknown-linux-musl-gcc` toolchain from: [https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2](https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu_latest.tar.bz2) + +> Note: +The current BSP only supports Linux compilation. + +After correct extraction, add the local path of the `riscv64-unknown-linux-musl-gcc` toolchain to `EXEC_PATH` in `rtconfig.py`, or specify the path through the `RTT_EXEC_PATH` environment variable. + +```shell +$ export RTT_EXEC_PATH=/opt/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu/bin +``` + +## Compilation +1. Installing Dependencies +```shell +$ sudo apt install -y device-tree-compiler +``` +On the Linux platform, you can execute: + +```shell +$ scons --menuconfig +``` +It will automatically download environment-related scripts to the ~/.env directory, and then execute +```shell +$ source ~/.env/env.sh +$ pkgs --update +``` + +After updating the software packages, use `scons -j10` or `scons -j10 --verbose` to compile this board support package. Alternatively, you can use the command `scons --exec-path="GCC_toolchain_path"` to specify the toolchain location for compilation. If the compilation is successful, an rtthread.elf file will be generated. + +After the compilation is completed, the script automatically calls the `./mksdimg.sh` script to package and generate the `boot.sd` file, which is the kernel file for SD card boot. + +## Running +1. Divide the SD card into 2 partitions, with the first partition used to store bin files and the second partition used as a data storage partition. The partition format is FAT32. + +2. Copy the `fip.bin` and `boot.sd` files from the root directory to the first partition of the SD card. For subsequent firmware updates, you only need to copy the `boot.sd` file. +Where: +- fip.bin: the bin file after fsbl、opensbi and U-Boot are packaged +- boot.sd: the bin file after the kernel is packaged + +After updating `boot.sd`, power on again and you will see the serial output information: + +```shell +U-Boot 2021.10 (Jun 26 2023 - 14:09:06 +0800)cvitek_cv180x + +DRAM: 63.3 MiB +gd->relocaddr=0x82435000. offset=0x2235000 +MMC: cv-sd@4310000: 0 +Loading Environment from ... OK +In: serial +Out: serial +Err: serial +Net: +Warning: ethernet@4070000 (eth0) using random MAC address - 62:80:19:6c:d4:64 +eth0: ethernet@4070000 +Hit any key to stop autoboot: 0 +Boot from SD ... +switch to partitions #0, OK +mmc0 is current device +132692 bytes read in 12 ms (10.5 MiB/s) +## Loading kernel from FIT Image at 81400000 ... + Using 'config-cv1800b_milkv_duo_sd' configuration + Trying 'kernel-1' kernel subimage + Verifying Hash Integrity ... crc32+ OK +## Loading fdt from FIT Image at 81400000 ... + Using 'config-cv1800b_milkv_duo_sd' configuration + Trying 'fdt-cv1800b_milkv_duo_sd' fdt subimage + Verifying Hash Integrity ... sha256+ OK + Booting using the fdt blob at 0x8141b590 + Uncompressing Kernel Image + Decompressing 296768 bytes used 42ms + Loading Device Tree to 0000000081be5000, end 0000000081becb60 ... OK + +Starting kernel ... + +heap: [0x802766b0 - 0x812766b0] + + \ | / +- RT - Thread Smart Operating System + / | \ 5.0.1 build Jun 28 2023 23:44:36 + 2006 - 2022 Copyright by RT-Thread team +Hello RT-Smart! +msh /> +``` +## Driver Support List + +| Driver | Support Status | Remarks | +| :----- | :------------- | :--------------------- | +| UART | Supported | Default baud rate 115200 | + +## Supported Development Boards +- milk-v duo: [https://milkv.io/duo](https://milkv.io/duo) + +## Contact information + +Maintenance person：[flyingcys](https://github.com/flyingcys) diff --git a/bsp/cvitek/cv180x/SConscript b/bsp/cvitek/cv180x/SConscript new file mode 100755 index 0000000000..c7ef7659ec --- /dev/null +++ b/bsp/cvitek/cv180x/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/cvitek/cv180x/SConstruct b/bsp/cvitek/cv180x/SConstruct new file mode 100755 index 0000000000..6ffc4cd71a --- /dev/null +++ b/bsp/cvitek/cv180x/SConstruct @@ -0,0 +1,48 @@ +import os +import sys +import rtconfig + +from rtconfig import RTT_ROOT + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') +rtconfig.CPU='virt64' +rtconfig.ARCH='risc-v' + +stack_size = 4096 + +stack_lds = open('link_stacksize.lds', 'w') +if GetDepend('__STACKSIZE__'): stack_size = GetDepend('__STACKSIZE__') +stack_lds.write('__STACKSIZE__ = %d;\n' % stack_size) +stack_lds.close() + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/drivers'): + drivers_path_prefix = SDK_ROOT + '/drivers' +else: + drivers_path_prefix = os.path.dirname(SDK_ROOT) + '/drivers' + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False) + +# include libraries +objs.extend(SConscript(drivers_path_prefix + '/SConscript', variant_dir='build/drivers', duplicate=0)) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/cvitek/cv180x/applications/SConscript b/bsp/cvitek/cv180x/applications/SConscript new file mode 100755 index 0000000000..c583d3016e --- /dev/null +++ b/bsp/cvitek/cv180x/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/cvitek/cv180x/applications/main.c b/bsp/cvitek/cv180x/applications/main.c new file mode 100755 index 0000000000..a8afc8b0f9 --- /dev/null +++ b/bsp/cvitek/cv180x/applications/main.c @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023/06/25 flyingcys first version + */ + +#include +#include + +int main(void) +{ + rt_kprintf("Hello RT-Smart!\n"); + + return 0; +} diff --git a/bsp/cvitek/cv180x/board/Kconfig b/bsp/cvitek/cv180x/board/Kconfig new file mode 100755 index 0000000000..82f7886f09 --- /dev/null +++ b/bsp/cvitek/cv180x/board/Kconfig @@ -0,0 +1,64 @@ +menu "General Drivers Configuration" + + menuconfig BSP_USING_UART + bool "Using UART" + select RT_USING_SERIAL + default y + + if BSP_USING_UART + config RT_USING_UART0 + bool "Enable UART 0" + default y + + config UART_IRQ_BASE + int + default 44 + + config RT_USING_UART1 + bool "Enable UART 1" + default n + + config RT_USING_UART2 + bool "Enable UART 2" + default n + + config RT_USING_UART3 + bool "Enable UART 3" + default n + + config RT_USING_UART4 + bool "Enable UART 4" + default n + + endif + + config BSP_USING_ADC + bool "Using ADC" + select RT_USING_ADC + default n + + menuconfig BSP_USING_PWM + bool "Using PWM" + select RT_USING_PWM + default n + + if BSP_USING_PWM + config BSP_USING_PWM0 + bool "Enable PWM 0" + default n + + config BSP_USING_PWM1 + bool "Enable PWM 1" + default n + + config BSP_USING_PWM2 + bool "Enable PWM 2" + default n + + config BSP_USING_PWM3 + bool "Enable PWM 3" + default n + + endif + +endmenu diff --git a/bsp/cvitek/cv180x/board/SConscript b/bsp/cvitek/cv180x/board/SConscript new file mode 100755 index 0000000000..4488cae073 --- /dev/null +++ b/bsp/cvitek/cv180x/board/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*.S') +CPPPATH = [cwd] + +group = DefineGroup('Driver', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/cvitek/cv180x/board/board.c b/bsp/cvitek/cv180x/board/board.c new file mode 100755 index 0000000000..6df8cd7a23 --- /dev/null +++ b/bsp/cvitek/cv180x/board/board.c @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023/06/25 flyingcys first version + */ +#include +#include + +#include "board.h" + +#include "sbi.h" + +#ifdef RT_USING_SMART +#include "riscv_mmu.h" +#include "mmu.h" +#include "page.h" +#include "lwp_arch.h" + +rt_region_t init_page_region = {(rt_size_t)RT_HW_PAGE_START, (rt_size_t)RT_HW_PAGE_END}; + +extern size_t MMUTable[]; + +struct mem_desc platform_mem_desc[] = { + {KERNEL_VADDR_START, (rt_size_t)RT_HW_PAGE_END - 1, (rt_size_t)ARCH_MAP_FAILED, NORMAL_MEM}, + {0x1000, ((KERNEL_VADDR_START - 1) & 0xfffff000) - 1, (rt_size_t)ARCH_MAP_FAILED, DEVICE_MEM}, +}; + +#define NUM_MEM_DESC (sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0])) + +#endif /* RT_USING_SMART */ + +void init_bss(void) +{ + unsigned int *dst; + + dst = &__bss_start; + while (dst < &__bss_end) + { + *dst++ = 0; + } +} + +static void __rt_assert_handler(const char *ex_string, const char *func, rt_size_t line) +{ + rt_kprintf("(%s) assertion failed at function:%s, line number:%d \n", ex_string, func, line); + asm volatile("ebreak" :: + : "memory"); +} + +void primary_cpu_entry(void) +{ + /* disable global interrupt */ + rt_hw_interrupt_disable(); + rt_assert_set_hook(__rt_assert_handler); + + entry(); +} + +#define IOREMAP_SIZE (1ul << 30) + +#ifndef ARCH_KERNEL_IN_HIGH_VA +#define IOREMAP_VEND USER_VADDR_START +#else +#define IOREMAP_VEND 0ul +#endif + +void rt_hw_board_init(void) +{ +#ifdef RT_USING_SMART + /* init data structure */ + rt_hw_mmu_map_init(&rt_kernel_space, (void *)(IOREMAP_VEND - IOREMAP_SIZE), IOREMAP_SIZE, (rt_size_t *)MMUTable, PV_OFFSET); + + /* init page allocator */ + rt_page_init(init_page_region); + + /* setup region, and enable MMU */ + rt_hw_mmu_setup(&rt_kernel_space, platform_mem_desc, NUM_MEM_DESC); +#endif + + /* initialize memory system */ +#ifdef RT_USING_HEAP + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); +#endif + + /* initalize interrupt */ + rt_hw_interrupt_init(); + + /* init rtthread hardware */ + rt_hw_tick_init(); + +#ifdef RT_USING_SERIAL + rt_hw_uart_init(); +#endif + +#ifdef RT_USING_CONSOLE + /* set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif /* RT_USING_CONSOLE */ + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_HEAP + rt_kprintf("heap: [0x%08x - 0x%08x]\n", (rt_ubase_t)RT_HW_HEAP_BEGIN, (rt_ubase_t)RT_HW_HEAP_END); +#endif /* RT_USING_HEAP */ +} diff --git a/bsp/cvitek/cv180x/board/board.h b/bsp/cvitek/cv180x/board/board.h new file mode 100755 index 0000000000..efcfa3bd36 --- /dev/null +++ b/bsp/cvitek/cv180x/board/board.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023/06/25 flyingcys first version + */ + +#ifndef BOARD_H__ +#define BOARD_H__ + +#include +#include "drv_uart.h" +#include "tick.h" + +extern unsigned int __bss_start; +extern unsigned int __bss_end; + +#ifndef RT_USING_SMART +#define KERNEL_VADDR_START 0x0 +#endif + +#define RT_HW_HEAP_BEGIN ((void *)&__bss_end) +#define RT_HW_HEAP_END ((void *)(RT_HW_HEAP_BEGIN + 16 * 1024 * 1024)) +#define RT_HW_PAGE_START RT_HW_HEAP_END +#define RT_HW_PAGE_END ((void *)(KERNEL_VADDR_START + 32 * 1024 * 1024)) + +void rt_hw_board_init(void); + +#endif diff --git a/bsp/cvitek/cv180x/cv1800b_milkv_duo_sd.dtb b/bsp/cvitek/cv180x/cv1800b_milkv_duo_sd.dtb new file mode 100755 index 0000000000..ff3823c663 Binary files /dev/null and b/bsp/cvitek/cv180x/cv1800b_milkv_duo_sd.dtb differ diff --git a/bsp/cvitek/cv180x/link.lds b/bsp/cvitek/cv180x/link.lds new file mode 100755 index 0000000000..891669e03c --- /dev/null +++ b/bsp/cvitek/cv180x/link.lds @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/12/12 bernard The first version + */ + +INCLUDE "link_stacksize.lds" + +OUTPUT_ARCH( "riscv" ) + +/* + * Memory layout: + * 0x10200000 - 0x10201000: Bootloader + * 0x10201000 - 0x10A00000: Kernel + * 0x10A00000 - 0x11200000: Heap + */ + +MEMORY +{ + SRAM : ORIGIN = 0x80200000, LENGTH = 32M +} + +ENTRY(_start) +SECTIONS +{ + . = 0x80200000 ; + + /* __STACKSIZE__ = 4096; */ + __text_start = .; + .start : + { + *(.start); + } > SRAM + + . = ALIGN(8); + + .text : + { + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(8); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(8); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(8); + + /* section information for initial. */ + . = ALIGN(8); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(8); + + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + . = ALIGN(8); + _etext = .; + } > SRAM + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + *(.eh_frame_entry) + } > SRAM + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM + + . = ALIGN(8); + __text_end = .; + __text_size = __text_end - __text_start; + + .data : + { + *(.data) + *(.data.*) + + *(.data1) + *(.data1.*) + + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + + *(.sdata) + *(.sdata.*) + } > SRAM + + . = ALIGN(8); + .ctors : + { + PROVIDE(__ctors_start__ = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__ctors_end__ = .); + } > SRAM + + .dtors : + { + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__dtors_end__ = .); + } > SRAM + + /* stack for dual core */ + .stack : + { + . = ALIGN(64); + __stack_start__ = .; + + . += __STACKSIZE__; + __stack_cpu0 = .; + + . += __STACKSIZE__; + __stack_cpu1 = .; + } > SRAM + + . = ALIGN(8); + + .osdebug : + { + _osdebug_start = .; + . += 87K; + _osdebug_end = .; + } > SRAM + + . = ALIGN(8); + + .sbss : + { + __bss_start = .; + *(.sbss) + *(.sbss.*) + *(.dynsbss) + *(.scommon) + } > SRAM + + .bss : + { + *(.bss) + *(.bss.*) + *(.dynbss) + *(COMMON) + __bss_end = .; + } > SRAM + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/cvitek/cv180x/link_stacksize.lds b/bsp/cvitek/cv180x/link_stacksize.lds new file mode 100755 index 0000000000..28438c7da1 --- /dev/null +++ b/bsp/cvitek/cv180x/link_stacksize.lds @@ -0,0 +1 @@ +__STACKSIZE__ = 4096; diff --git a/bsp/cvitek/cv180x/multi.its b/bsp/cvitek/cv180x/multi.its new file mode 100755 index 0000000000..8403466927 --- /dev/null +++ b/bsp/cvitek/cv180x/multi.its @@ -0,0 +1,56 @@ +/* + * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs + */ + +/dts-v1/; + +/ { + description = "Various kernels, ramdisks and FDT blobs"; + #address-cells = <2>; + + images { + kernel-1 { + description = "cvitek kernel"; + data = /incbin/("./Image.lzma"); + type = "kernel"; + arch = "riscv"; + os = "linux"; + compression = "lzma"; + load = <0x0 0x80200000>; + entry = <0x0 0x80200000>; + hash-2 { + algo = "crc32"; + }; + }; + + + /*FDT*/ + + fdt-cv1800b_milkv_duo_sd { + description = "cvitek device tree - cv1800b_milkv_duo_sd"; + data = /incbin/("./cv1800b_milkv_duo_sd.dtb"); + type = "flat_dt"; + arch = "riscv"; + compression = "none"; + hash-1 { + algo = "sha256"; + }; + }; + + + + }; + + /*CFG*/ + configurations { + + config-cv1800b_milkv_duo_sd { + description = "boot cvitek system with board cv1800b_milkv_duo_sd"; + kernel = "kernel-1"; + fdt = "fdt-cv1800b_milkv_duo_sd"; + }; + + }; + + +}; diff --git a/bsp/cvitek/cv180x/rtconfig.h b/bsp/cvitek/cv180x/rtconfig.h new file mode 100755 index 0000000000..ea9b8dd4e5 --- /dev/null +++ b/bsp/cvitek/cv180x/rtconfig.h @@ -0,0 +1,321 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_USING_SMART +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 2048 + +/* kservice optimization */ + +#define RT_KSERVICE_USING_STDLIB +#define RT_KPRINTF_USING_LONGLONG +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_PAGE_MAX_ORDER 11 +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +#define RT_USING_DEVICE +#define RT_USING_DEVICE_OPS +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 256 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50100 +#define RT_USING_STDC_ATOMIC +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +#define ARCH_CPU_64BIT +#define RT_USING_CACHE +#define ARCH_MM_MMU +#define KERNEL_VADDR_START 0x80000000 +#define ARCH_RISCV +#define ARCH_RISCV64 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 6144 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_POSIX +#define DFS_USING_WORKDIR +#define DFS_FD_MAX 16 +#define RT_USING_DFS_V2 +#define RT_USING_DFS_DEVFS +#define RT_USING_PAGECACHE + +/* page cache config */ + +#define RT_PAGECACHE_COUNT 4096 +#define RT_PAGECACHE_ASPACE_COUNT 1024 +#define RT_PAGECACHE_PRELOAD 4 +#define RT_PAGECACHE_HASH_NR 1024 +#define RT_PAGECACHE_GC_WORK_LEVEL 90 +#define RT_PAGECACHE_GC_STOP_LEVEL 70 + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_TTY +#define RT_USING_NULL +#define RT_USING_ZERO +#define RT_USING_RANDOM +#define RT_USING_RTC +#define RT_USING_PIN +#define RT_USING_KTIME + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 + +/* POSIX (Portable Operating System Interface) layer */ + +#define RT_USING_POSIX_FS +#define RT_USING_POSIX_DEVIO +#define RT_USING_POSIX_STDIO +#define RT_USING_POSIX_TERMIOS +#define RT_USING_POSIX_DELAY +#define RT_USING_POSIX_CLOCK +#define RT_USING_POSIX_TIMER + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Memory protection */ + + +/* Utilities */ + +#define RT_USING_RESOURCE_ID +#define RT_USING_ADT +#define RT_USING_ADT_AVL +#define RT_USING_ADT_BITMAP +#define RT_USING_ADT_HASHMAP +#define RT_USING_ADT_REF +#define RT_USING_LWP +#define RT_LWP_MAX_NR 30 +#define LWP_TASK_STACK_SIZE 16384 +#define RT_CH_MSG_MAX_NR 1024 +#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024 +#define LWP_TID_MAX_NR 64 +#define RT_LWP_SHM_MAX_NR 64 +#define RT_USING_LDSO + +/* Memory management */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* CYW43012 WiFi */ + + +/* BL808 WiFi */ + + +/* CYW43439 WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + + +/* Kendryte SDK */ + + +/* sensors drivers */ + + +/* touch drivers */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects and Demos */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +/* General Drivers Configuration */ + +#define BSP_USING_UART +#define RT_USING_UART0 +#define UART_IRQ_BASE 44 +#define BSP_USING_CV180X +#define C906_PLIC_PHY_ADDR 0x70000000 +#define IRQ_MAX_NR 64 +#define TIMER_CLK_FREQ 25000000 +#define __STACKSIZE__ 4096 +#define BOARD_TYPE_MILKV_DUO + +#endif diff --git a/bsp/cvitek/cv180x/rtconfig.py b/bsp/cvitek/cv180x/rtconfig.py new file mode 100755 index 0000000000..4ca7b664bb --- /dev/null +++ b/bsp/cvitek/cv180x/rtconfig.py @@ -0,0 +1,61 @@ +import os + +# toolchains options +ARCH ='risc-v' +VENDOR ='t-head' +CPU ='c906' +CROSS_TOOL ='gcc' + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = r'../../..' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'/opt/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu/bin' +else: + print('Please make sure your toolchains is GNU GCC!') + exit(0) + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +CHIP_TYPE = 'cv180x' + +if PLATFORM == 'gcc': + # toolchains + #PREFIX = 'riscv64-unknown-elf-' + PREFIX = os.getenv('RTT_CC_PREFIX') or 'riscv64-unknown-linux-musl-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcmodel=medany -march=rv64imafdc -mabi=lp64' + CFLAGS = DEVICE + ' -Wno-cpp -fvar-tracking -ffreestanding -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -D_POSIX_SOURCE ' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__' + LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds' + ' -lsupc++ -lgcc -static' + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -ggdb' + AFLAGS += ' -ggdb' + else: + CFLAGS += ' -O2 -Os' + + CXXFLAGS = CFLAGS + +DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtthread.asm\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET Image \n' + SIZE + ' $TARGET \n' +POST_ACTION += 'cd .. && bash mksdimg.sh ' + os.getcwd() + ' Image \n' diff --git a/bsp/cvitek/drivers/.ignore_format.yml b/bsp/cvitek/drivers/.ignore_format.yml new file mode 100755 index 0000000000..821281b7e9 --- /dev/null +++ b/bsp/cvitek/drivers/.ignore_format.yml @@ -0,0 +1,6 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +dir_path: +- libraries \ No newline at end of file diff --git a/bsp/cvitek/drivers/SConscript b/bsp/cvitek/drivers/SConscript index 83c882470c..f5cde6b1e8 100755 --- a/bsp/cvitek/drivers/SConscript +++ b/bsp/cvitek/drivers/SConscript @@ -2,17 +2,23 @@ from building import * cwd = GetCurrentDir() src = Split(''' -drv_uart.c -drv_por.c + drv_uart.c + drv_por.c ''') CPPDEFINES = [] CPPPATH = [cwd] -if GetDepend('BSP_USING_CV1800B') or GetDepend('BSP_USING_C906_LITTLE'): - CPPPATH += [cwd + r'/cv1800b'] +CHIP_TYPE = 'cv180x' +if GetDepend('BOARD_TYPE_MILKV_DUO256M'): + CHIP_TYPE = 'cv181x' +elif GetDepend('BOARD_TYPE_MILKV_DUO') or GetDepend('BOARD_TYPE_MILKV_DUO_SPINOR') or GetDepend('BOARD_TYPE_MILKV_DUO_SPINAND'): + CHIP_TYPE = 'cv180x' -if GetDepend('BSP_USING_CV1800B'): +CPPPATH += [cwd + r'/libraries'] +CPPPATH += [cwd + r'/libraries/' + CHIP_TYPE] + +if GetDepend('BSP_USING_CV180X'): src += ['drv_gpio.c'] if GetDepend('BSP_USING_I2C'): @@ -26,7 +32,8 @@ if GetDepend('BSP_USING_WDT'): if GetDepend('BSP_USING_PWM'): src += ['drv_pwm.c'] - CPPPATH += [cwd + r'/cv1800b/pwm'] + CPPPATH += [cwd + r'/libraries/cv180x/pwm'] + CPPDEFINES += ['-DCONFIG_64BIT'] if GetDepend('BSP_USING_RTC'): diff --git a/bsp/cvitek/drivers/cv1800b/cv180x_pinlist_swconfig.h b/bsp/cvitek/drivers/cv1800b/cv180x_pinlist_swconfig.h deleted file mode 100755 index 2a13a616ea..0000000000 --- a/bsp/cvitek/drivers/cv1800b/cv180x_pinlist_swconfig.h +++ /dev/null @@ -1,407 +0,0 @@ -//##============================================================================== -//##=== This script is generate by genswconfig.pl from .\00_Phobos_Pinlist_20220315.xls -//##=== Generate Time stamp is : 2022-03-17 14:04:49 -//##============================================================================== - -#ifndef __CV180X_PINLIST_SWCONFIG_H__ -#define __CV180X_PINLIST_SWCONFIG_H__ - -#define SD0_CLK__SDIO0_CLK 0 -#define SD0_CLK__IIC1_SDA 1 -#define SD0_CLK__SPI0_SCK 2 -#define SD0_CLK__XGPIOA_7 3 -#define SD0_CLK__PWM_15 5 -#define SD0_CLK__EPHY_LNK_LED 6 -#define SD0_CLK__DBG_0 7 -#define SD0_CMD__SDIO0_CMD 0 -#define SD0_CMD__IIC1_SCL 1 -#define SD0_CMD__SPI0_SDO 2 -#define SD0_CMD__XGPIOA_8 3 -#define SD0_CMD__PWM_14 5 -#define SD0_CMD__EPHY_SPD_LED 6 -#define SD0_CMD__DBG_1 7 -#define SD0_D0__SDIO0_D_0 0 -#define SD0_D0__CAM_MCLK1 1 -#define SD0_D0__SPI0_SDI 2 -#define SD0_D0__XGPIOA_9 3 -#define SD0_D0__UART3_TX 4 -#define SD0_D0__PWM_13 5 -#define SD0_D0__WG0_D0 6 -#define SD0_D0__DBG_2 7 -#define SD0_D1__SDIO0_D_1 0 -#define SD0_D1__IIC1_SDA 1 -#define SD0_D1__AUX0 2 -#define SD0_D1__XGPIOA_10 3 -#define SD0_D1__UART1_TX 4 -#define SD0_D1__PWM_12 5 -#define SD0_D1__WG0_D1 6 -#define SD0_D1__DBG_3 7 -#define SD0_D2__SDIO0_D_2 0 -#define SD0_D2__IIC1_SCL 1 -#define SD0_D2__AUX1 2 -#define SD0_D2__XGPIOA_11 3 -#define SD0_D2__UART1_RX 4 -#define SD0_D2__PWM_11 5 -#define SD0_D2__WG1_D0 6 -#define SD0_D2__DBG_4 7 -#define SD0_D3__SDIO0_D_3 0 -#define SD0_D3__CAM_MCLK0 1 -#define SD0_D3__SPI0_CS_X 2 -#define SD0_D3__XGPIOA_12 3 -#define SD0_D3__UART3_RX 4 -#define SD0_D3__PWM_10 5 -#define SD0_D3__WG1_D1 6 -#define SD0_D3__DBG_5 7 -#define SD0_CD__SDIO0_CD 0 -#define SD0_CD__XGPIOA_13 3 -#define SD0_PWR_EN__SDIO0_PWR_EN 0 -#define SD0_PWR_EN__XGPIOA_14 3 -#define SPK_EN__XGPIOA_15 3 -#define UART0_TX__UART0_TX 0 -#define UART0_TX__CAM_MCLK1 1 -#define UART0_TX__PWM_4 2 -#define UART0_TX__XGPIOA_16 3 -#define UART0_TX__UART1_TX 4 -#define UART0_TX__AUX1 5 -#define UART0_TX__JTAG_TMS 6 -#define UART0_TX__DBG_6 7 -#define UART0_RX__UART0_RX 0 -#define UART0_RX__CAM_MCLK0 1 -#define UART0_RX__PWM_5 2 -#define UART0_RX__XGPIOA_17 3 -#define UART0_RX__UART1_RX 4 -#define UART0_RX__AUX0 5 -#define UART0_RX__JTAG_TCK 6 -#define UART0_RX__DBG_7 7 -#define SPINOR_HOLD_X__SPINOR_HOLD_X 1 -#define SPINOR_HOLD_X__SPINAND_HOLD 2 -#define SPINOR_HOLD_X__XGPIOA_26 3 -#define SPINOR_SCK__SPINOR_SCK 1 -#define SPINOR_SCK__SPINAND_CLK 2 -#define SPINOR_SCK__XGPIOA_22 3 -#define SPINOR_MOSI__SPINOR_MOSI 1 -#define SPINOR_MOSI__SPINAND_MOSI 2 -#define SPINOR_MOSI__XGPIOA_25 3 -#define SPINOR_WP_X__SPINOR_WP_X 1 -#define SPINOR_WP_X__SPINAND_WP 2 -#define SPINOR_WP_X__XGPIOA_27 3 -#define SPINOR_MISO__SPINOR_MISO 1 -#define SPINOR_MISO__SPINAND_MISO 2 -#define SPINOR_MISO__XGPIOA_23 3 -#define SPINOR_CS_X__SPINOR_CS_X 1 -#define SPINOR_CS_X__SPINAND_CS 2 -#define SPINOR_CS_X__XGPIOA_24 3 -#define JTAG_CPU_TMS__JTAG_TMS 0 -#define JTAG_CPU_TMS__CAM_MCLK0 1 -#define JTAG_CPU_TMS__PWM_7 2 -#define JTAG_CPU_TMS__XGPIOA_19 3 -#define JTAG_CPU_TMS__UART1_RTS 4 -#define JTAG_CPU_TMS__AUX0 5 -#define JTAG_CPU_TMS__UART1_TX 6 -#define JTAG_CPU_TCK__JTAG_TCK 0 -#define JTAG_CPU_TCK__CAM_MCLK1 1 -#define JTAG_CPU_TCK__PWM_6 2 -#define JTAG_CPU_TCK__XGPIOA_18 3 -#define JTAG_CPU_TCK__UART1_CTS 4 -#define JTAG_CPU_TCK__AUX1 5 -#define JTAG_CPU_TCK__UART1_RX 6 -#define IIC0_SCL__CV_SCL0__CR_4WTDI 0 -#define IIC0_SDA__CV_SDA0__CR_4WTDO 0 -#define IIC0_SCL__JTAG_TDI 0 -#define IIC0_SCL__UART1_TX 1 -#define IIC0_SCL__UART2_TX 2 -#define IIC0_SCL__XGPIOA_28 3 -#define IIC0_SCL__IIC0_SCL 4 -#define IIC0_SCL__WG0_D0 5 -#define IIC0_SCL__DBG_10 7 -#define IIC0_SDA__JTAG_TDO 0 -#define IIC0_SDA__UART1_RX 1 -#define IIC0_SDA__UART2_RX 2 -#define IIC0_SDA__XGPIOA_29 3 -#define IIC0_SDA__IIC0_SDA 4 -#define IIC0_SDA__WG0_D1 5 -#define IIC0_SDA__WG1_D0 6 -#define IIC0_SDA__DBG_11 7 -#define AUX0__AUX0 0 -#define AUX0__XGPIOA_30 3 -#define AUX0__IIS1_MCLK 4 -#define AUX0__WG1_D1 6 -#define AUX0__DBG_12 7 -#define GPIO_ZQ__PWR_GPIO_24 3 -#define GPIO_ZQ__PWM_2 4 -#define PWR_VBAT_DET__PWR_VBAT_DET 0 -#define PWR_RSTN__PWR_RSTN 0 -#define PWR_SEQ1__PWR_SEQ1 0 -#define PWR_SEQ1__PWR_GPIO_3 3 -#define PWR_SEQ2__PWR_SEQ2 0 -#define PWR_SEQ2__PWR_GPIO_4 3 -#define PTEST__PWR_PTEST 0 -#define PWR_WAKEUP0__PWR_WAKEUP0 0 -#define PWR_WAKEUP0__PWR_IR0 1 -#define PWR_WAKEUP0__PWR_UART0_TX 2 -#define PWR_WAKEUP0__PWR_GPIO_6 3 -#define PWR_WAKEUP0__UART1_TX 4 -#define PWR_WAKEUP0__IIC4_SCL 5 -#define PWR_WAKEUP0__EPHY_LNK_LED 6 -#define PWR_WAKEUP0__WG2_D0 7 -#define PWR_BUTTON1__PWR_BUTTON1 0 -#define PWR_BUTTON1__PWR_GPIO_8 3 -#define PWR_BUTTON1__UART1_RX 4 -#define PWR_BUTTON1__IIC4_SDA 5 -#define PWR_BUTTON1__EPHY_SPD_LED 6 -#define PWR_BUTTON1__WG2_D1 7 -#define XTAL_XIN__PWR_XTAL_CLKIN 0 -#define PWR_GPIO0__PWR_GPIO_0 0 -#define PWR_GPIO0__UART2_TX 1 -#define PWR_GPIO0__PWR_UART0_RX 2 -#define PWR_GPIO0__PWM_8 4 -#define PWR_GPIO1__PWR_GPIO_1 0 -#define PWR_GPIO1__UART2_RX 1 -#define PWR_GPIO1__EPHY_LNK_LED 3 -#define PWR_GPIO1__PWM_9 4 -#define PWR_GPIO1__PWR_IIC_SCL 5 -#define PWR_GPIO1__IIC2_SCL 6 -#define PWR_GPIO1__IIC0_SDA 7 -#define PWR_GPIO2__PWR_GPIO_2 0 -#define PWR_GPIO2__PWR_SECTICK 2 -#define PWR_GPIO2__EPHY_SPD_LED 3 -#define PWR_GPIO2__PWM_10 4 -#define PWR_GPIO2__PWR_IIC_SDA 5 -#define PWR_GPIO2__IIC2_SDA 6 -#define PWR_GPIO2__IIC0_SCL 7 -#define SD1_GPIO1__UART4_TX 1 -#define SD1_GPIO1__PWR_GPIO_26 3 -#define SD1_GPIO1__PWM_10 7 -#define SD1_GPIO0__UART4_RX 1 -#define SD1_GPIO0__PWR_GPIO_25 3 -#define SD1_GPIO0__PWM_11 7 -#define SD1_D3__PWR_SD1_D3 0 -#define SD1_D3__SPI2_CS_X 1 -#define SD1_D3__IIC1_SCL 2 -#define SD1_D3__PWR_GPIO_18 3 -#define SD1_D3__CAM_MCLK0 4 -#define SD1_D3__UART3_CTS 5 -#define SD1_D3__PWR_SPINOR1_CS_X 6 -#define SD1_D3__PWM_4 7 -#define SD1_D2__PWR_SD1_D2 0 -#define SD1_D2__IIC1_SCL 1 -#define SD1_D2__UART2_TX 2 -#define SD1_D2__PWR_GPIO_19 3 -#define SD1_D2__CAM_MCLK0 4 -#define SD1_D2__UART3_TX 5 -#define SD1_D2__PWR_SPINOR1_HOLD_X 6 -#define SD1_D2__PWM_5 7 -#define SD1_D1__PWR_SD1_D1 0 -#define SD1_D1__IIC1_SDA 1 -#define SD1_D1__UART2_RX 2 -#define SD1_D1__PWR_GPIO_20 3 -#define SD1_D1__CAM_MCLK1 4 -#define SD1_D1__UART3_RX 5 -#define SD1_D1__PWR_SPINOR1_WP_X 6 -#define SD1_D1__PWM_6 7 -#define SD1_D0__PWR_SD1_D0 0 -#define SD1_D0__SPI2_SDI 1 -#define SD1_D0__IIC1_SDA 2 -#define SD1_D0__PWR_GPIO_21 3 -#define SD1_D0__CAM_MCLK1 4 -#define SD1_D0__UART3_RTS 5 -#define SD1_D0__PWR_SPINOR1_MISO 6 -#define SD1_D0__PWM_7 7 -#define SD1_CMD__PWR_SD1_CMD 0 -#define SD1_CMD__SPI2_SDO 1 -#define SD1_CMD__IIC3_SCL 2 -#define SD1_CMD__PWR_GPIO_22 3 -#define SD1_CMD__CAM_VS0 4 -#define SD1_CMD__EPHY_LNK_LED 5 -#define SD1_CMD__PWR_SPINOR1_MOSI 6 -#define SD1_CMD__PWM_8 7 -#define SD1_CLK__PWR_SD1_CLK 0 -#define SD1_CLK__SPI2_SCK 1 -#define SD1_CLK__IIC3_SDA 2 -#define SD1_CLK__PWR_GPIO_23 3 -#define SD1_CLK__CAM_HS0 4 -#define SD1_CLK__EPHY_SPD_LED 5 -#define SD1_CLK__PWR_SPINOR1_SCK 6 -#define SD1_CLK__PWM_9 7 -#define PWM0_BUCK__PWM_0 0 -#define PWM0_BUCK__XGPIOB_0 3 -#define ADC1__XGPIOB_3 3 -#define ADC1__KEY_COL2 4 -#define ADC1__PWM_3 6 -#define USB_VBUS_DET__USB_VBUS_DET 0 -#define USB_VBUS_DET__XGPIOB_6 3 -#define USB_VBUS_DET__CAM_MCLK0 4 -#define USB_VBUS_DET__CAM_MCLK1 5 -#define USB_VBUS_DET__PWM_4 6 -#define MUX_SPI1_MISO__UART3_RTS 1 -#define MUX_SPI1_MISO__IIC1_SDA 2 -#define MUX_SPI1_MISO__XGPIOB_8 3 -#define MUX_SPI1_MISO__PWM_9 4 -#define MUX_SPI1_MISO__KEY_COL1 5 -#define MUX_SPI1_MISO__SPI1_SDI 6 -#define MUX_SPI1_MISO__DBG_14 7 -#define MUX_SPI1_MOSI__UART3_RX 1 -#define MUX_SPI1_MOSI__IIC1_SCL 2 -#define MUX_SPI1_MOSI__XGPIOB_7 3 -#define MUX_SPI1_MOSI__PWM_8 4 -#define MUX_SPI1_MOSI__KEY_COL0 5 -#define MUX_SPI1_MOSI__SPI1_SDO 6 -#define MUX_SPI1_MOSI__DBG_13 7 -#define MUX_SPI1_CS__UART3_CTS 1 -#define MUX_SPI1_CS__CAM_MCLK0 2 -#define MUX_SPI1_CS__XGPIOB_10 3 -#define MUX_SPI1_CS__PWM_11 4 -#define MUX_SPI1_CS__KEY_ROW3 5 -#define MUX_SPI1_CS__SPI1_CS_X 6 -#define MUX_SPI1_CS__DBG_16 7 -#define MUX_SPI1_SCK__UART3_TX 1 -#define MUX_SPI1_SCK__CAM_MCLK1 2 -#define MUX_SPI1_SCK__XGPIOB_9 3 -#define MUX_SPI1_SCK__PWM_10 4 -#define MUX_SPI1_SCK__KEY_ROW2 5 -#define MUX_SPI1_SCK__SPI1_SCK 6 -#define MUX_SPI1_SCK__DBG_15 7 -#define PAD_ETH_TXP__UART3_RX 1 -#define PAD_ETH_TXP__IIC1_SCL 2 -#define PAD_ETH_TXP__XGPIOB_25 3 -#define PAD_ETH_TXP__PWM_13 4 -#define PAD_ETH_TXP__CAM_MCLK0 5 -#define PAD_ETH_TXP__SPI1_SDO 6 -#define PAD_ETH_TXP__IIS2_LRCK 7 -#define PAD_ETH_TXM__UART3_RTS 1 -#define PAD_ETH_TXM__IIC1_SDA 2 -#define PAD_ETH_TXM__XGPIOB_24 3 -#define PAD_ETH_TXM__PWM_12 4 -#define PAD_ETH_TXM__CAM_MCLK1 5 -#define PAD_ETH_TXM__SPI1_SDI 6 -#define PAD_ETH_TXM__IIS2_BCLK 7 -#define PAD_ETH_RXP__UART3_TX 1 -#define PAD_ETH_RXP__CAM_MCLK1 2 -#define PAD_ETH_RXP__XGPIOB_27 3 -#define PAD_ETH_RXP__PWM_15 4 -#define PAD_ETH_RXP__CAM_HS0 5 -#define PAD_ETH_RXP__SPI1_SCK 6 -#define PAD_ETH_RXP__IIS2_DO 7 -#define PAD_ETH_RXM__UART3_CTS 1 -#define PAD_ETH_RXM__CAM_MCLK0 2 -#define PAD_ETH_RXM__XGPIOB_26 3 -#define PAD_ETH_RXM__PWM_14 4 -#define PAD_ETH_RXM__CAM_VS0 5 -#define PAD_ETH_RXM__SPI1_CS_X 6 -#define PAD_ETH_RXM__IIS2_DI 7 -#define GPIO_RTX__VI0_D_15 1 -#define GPIO_RTX__XGPIOB_23 3 -#define GPIO_RTX__PWM_1 4 -#define GPIO_RTX__CAM_MCLK0 5 -#define GPIO_RTX__IIS2_MCLK 7 -#define PAD_MIPIRX4N__VI0_CLK 1 -#define PAD_MIPIRX4N__IIC0_SCL 2 -#define PAD_MIPIRX4N__XGPIOC_2 3 -#define PAD_MIPIRX4N__IIC1_SDA 4 -#define PAD_MIPIRX4N__CAM_MCLK0 5 -#define PAD_MIPIRX4N__KEY_ROW0 6 -#define PAD_MIPIRX4N__MUX_SPI1_SCK 7 -#define PAD_MIPIRX4P__VI0_D_0 1 -#define PAD_MIPIRX4P__IIC0_SDA 2 -#define PAD_MIPIRX4P__XGPIOC_3 3 -#define PAD_MIPIRX4P__IIC1_SCL 4 -#define PAD_MIPIRX4P__CAM_MCLK1 5 -#define PAD_MIPIRX4P__KEY_ROW1 6 -#define PAD_MIPIRX4P__MUX_SPI1_CS 7 -#define PAD_MIPIRX3N__VI0_D_1 1 -#define PAD_MIPIRX3N__XGPIOC_4 3 -#define PAD_MIPIRX3N__CAM_MCLK0 4 -#define PAD_MIPIRX3N__MUX_SPI1_MISO 7 -#define PAD_MIPIRX3P__VI0_D_2 1 -#define PAD_MIPIRX3P__XGPIOC_5 3 -#define PAD_MIPIRX3P__MUX_SPI1_MOSI 7 -#define PAD_MIPIRX2N__VI0_D_3 1 -#define PAD_MIPIRX2N__XGPIOC_6 3 -#define PAD_MIPIRX2N__IIC4_SCL 5 -#define PAD_MIPIRX2N__DBG_6 7 -#define PAD_MIPIRX2P__VI0_D_4 1 -#define PAD_MIPIRX2P__XGPIOC_7 3 -#define PAD_MIPIRX2P__IIC4_SDA 5 -#define PAD_MIPIRX2P__DBG_7 7 -#define PAD_MIPIRX1N__VI0_D_5 1 -#define PAD_MIPIRX1N__XGPIOC_8 3 -#define PAD_MIPIRX1N__KEY_ROW3 6 -#define PAD_MIPIRX1N__DBG_8 7 -#define PAD_MIPIRX1P__VI0_D_6 1 -#define PAD_MIPIRX1P__XGPIOC_9 3 -#define PAD_MIPIRX1P__IIC1_SDA 4 -#define PAD_MIPIRX1P__KEY_ROW2 6 -#define PAD_MIPIRX1P__DBG_9 7 -#define PAD_MIPIRX0N__VI0_D_7 1 -#define PAD_MIPIRX0N__XGPIOC_10 3 -#define PAD_MIPIRX0N__IIC1_SCL 4 -#define PAD_MIPIRX0N__CAM_MCLK1 5 -#define PAD_MIPIRX0N__DBG_10 7 -#define PAD_MIPIRX0P__VI0_D_8 1 -#define PAD_MIPIRX0P__XGPIOC_11 3 -#define PAD_MIPIRX0P__CAM_MCLK0 4 -#define PAD_MIPIRX0P__DBG_11 7 -#define PAD_MIPI_TXM2__VI0_D_13 1 -#define PAD_MIPI_TXM2__IIC0_SDA 2 -#define PAD_MIPI_TXM2__XGPIOC_16 3 -#define PAD_MIPI_TXM2__IIC1_SDA 4 -#define PAD_MIPI_TXM2__PWM_8 5 -#define PAD_MIPI_TXM2__SPI0_SCK 6 -#define PAD_MIPI_TXP2__VI0_D_14 1 -#define PAD_MIPI_TXP2__IIC0_SCL 2 -#define PAD_MIPI_TXP2__XGPIOC_17 3 -#define PAD_MIPI_TXP2__IIC1_SCL 4 -#define PAD_MIPI_TXP2__PWM_9 5 -#define PAD_MIPI_TXP2__SPI0_CS_X 6 -#define PAD_MIPI_TXP2__IIS1_MCLK 7 -#define PAD_MIPI_TXM1__SPI3_SDO 0 -#define PAD_MIPI_TXM1__VI0_D_11 1 -#define PAD_MIPI_TXM1__IIS1_LRCK 2 -#define PAD_MIPI_TXM1__XGPIOC_14 3 -#define PAD_MIPI_TXM1__IIC2_SDA 4 -#define PAD_MIPI_TXM1__PWM_10 5 -#define PAD_MIPI_TXM1__SPI0_SDO 6 -#define PAD_MIPI_TXM1__DBG_14 7 -#define PAD_MIPI_TXP1__SPI3_SDI 0 -#define PAD_MIPI_TXP1__VI0_D_12 1 -#define PAD_MIPI_TXP1__IIS1_DO 2 -#define PAD_MIPI_TXP1__XGPIOC_15 3 -#define PAD_MIPI_TXP1__IIC2_SCL 4 -#define PAD_MIPI_TXP1__PWM_11 5 -#define PAD_MIPI_TXP1__SPI0_SDI 6 -#define PAD_MIPI_TXP1__DBG_15 7 -#define PAD_MIPI_TXM0__SPI3_SCK 0 -#define PAD_MIPI_TXM0__VI0_D_9 1 -#define PAD_MIPI_TXM0__IIS1_DI 2 -#define PAD_MIPI_TXM0__XGPIOC_12 3 -#define PAD_MIPI_TXM0__CAM_MCLK1 4 -#define PAD_MIPI_TXM0__PWM_14 5 -#define PAD_MIPI_TXM0__CAM_VS0 6 -#define PAD_MIPI_TXM0__DBG_12 7 -#define PAD_MIPI_TXP0__SPI3_CS_X 0 -#define PAD_MIPI_TXP0__VI0_D_10 1 -#define PAD_MIPI_TXP0__IIS1_BCLK 2 -#define PAD_MIPI_TXP0__XGPIOC_13 3 -#define PAD_MIPI_TXP0__CAM_MCLK0 4 -#define PAD_MIPI_TXP0__PWM_15 5 -#define PAD_MIPI_TXP0__CAM_HS0 6 -#define PAD_MIPI_TXP0__DBG_13 7 -#define PKG_TYPE0__PKG_TYPE0 0 -#define PKG_TYPE1__PKG_TYPE1 0 -#define PKG_TYPE2__PKG_TYPE2 0 -#define PAD_AUD_AINL_MIC__XGPIOC_23 3 -#define PAD_AUD_AINL_MIC__IIS1_BCLK 4 -#define PAD_AUD_AINL_MIC__IIS2_BCLK 5 -#define PAD_AUD_AINR_MIC__XGPIOC_22 3 -#define PAD_AUD_AINR_MIC__IIS1_DO 4 -#define PAD_AUD_AINR_MIC__IIS2_DI 5 -#define PAD_AUD_AINR_MIC__IIS1_DI 6 -#define PAD_AUD_AOUTL__XGPIOC_25 3 -#define PAD_AUD_AOUTL__IIS1_LRCK 4 -#define PAD_AUD_AOUTL__IIS2_LRCK 5 -#define PAD_AUD_AOUTR__XGPIOC_24 3 -#define PAD_AUD_AOUTR__IIS1_DI 4 -#define PAD_AUD_AOUTR__IIS2_DO 5 -#define PAD_AUD_AOUTR__IIS1_DO 6 - -#endif /* __CV180X_PINLIST_SWCONFIG_H__ */ diff --git a/bsp/cvitek/drivers/cv1800b/cv180x_pinmux.h b/bsp/cvitek/drivers/cv1800b/cv180x_pinmux.h deleted file mode 100755 index 1b72bc23ea..0000000000 --- a/bsp/cvitek/drivers/cv1800b/cv180x_pinmux.h +++ /dev/null @@ -1,51 +0,0 @@ -#ifndef _CV180X_PINMUX_H_ -#define _CV180X_PINMUX_H_ - -/* - * Pinmux definitions - */ -#define PINMUX_UART0 0 -#define PINMUX_UART1 1 -#define PINMUX_UART2 2 -#define PINMUX_UART3 3 -#define PINMUX_UART3_2 4 -#define PINMUX_I2C0 5 -#define PINMUX_I2C1 6 -#define PINMUX_I2C2 7 -#define PINMUX_I2C3 8 -#define PINMUX_I2C4 9 -#define PINMUX_I2C4_2 10 -#define PINMUX_SPI0 11 -#define PINMUX_SPI1 12 -#define PINMUX_SPI2 13 -#define PINMUX_SPI2_2 14 -#define PINMUX_SPI3 15 -#define PINMUX_SPI3_2 16 -#define PINMUX_I2S0 17 -#define PINMUX_I2S1 18 -#define PINMUX_I2S2 19 -#define PINMUX_I2S3 20 -#define PINMUX_USBID 21 -#define PINMUX_SDIO0 22 -#define PINMUX_SDIO1 23 -#define PINMUX_ND 24 -#define PINMUX_EMMC 25 -#define PINMUX_SPI_NOR 26 -#define PINMUX_SPI_NAND 27 -#define PINMUX_CAM0 28 -#define PINMUX_CAM1 29 -#define PINMUX_PCM0 30 -#define PINMUX_PCM1 31 -#define PINMUX_CSI0 32 -#define PINMUX_CSI1 33 -#define PINMUX_CSI2 34 -#define PINMUX_DSI 35 -#define PINMUX_VI0 36 -#define PINMUX_VO 37 -#define PINMUX_RMII1 38 -#define PINMUX_EPHY_LED 39 -#define PINMUX_I80 40 -#define PINMUX_LVDS 41 -#define PINMUX_USB 42 - -#endif // end of _CV180X_PINMUX_H_ diff --git a/bsp/cvitek/drivers/cv1800b/cv180x_reg_fmux_gpio.h b/bsp/cvitek/drivers/cv1800b/cv180x_reg_fmux_gpio.h deleted file mode 100755 index a07236fba3..0000000000 --- a/bsp/cvitek/drivers/cv1800b/cv180x_reg_fmux_gpio.h +++ /dev/null @@ -1,337 +0,0 @@ -// $Module: fmux_gpio $ -// $RegisterBank Version: V 1.0.00 $ -// $Author: ghost $ -// $Date: Thu, 17 Mar 2022 04:53:31 PM $ -// - -//GEN REG ADDR/OFFSET/MASK - -#ifndef __CV180X_REG_FMUX_GPIO_H__ -#define __CV180X_REG_FMUX_GPIO_H__ - -#define FMUX_GPIO_REG_IOCTRL_SD0_CLK 0x0 -#define FMUX_GPIO_REG_IOCTRL_SD0_CMD 0x4 -#define FMUX_GPIO_REG_IOCTRL_SD0_D0 0x8 -#define FMUX_GPIO_REG_IOCTRL_SD0_D1 0xc -#define FMUX_GPIO_REG_IOCTRL_SD0_D2 0x10 -#define FMUX_GPIO_REG_IOCTRL_SD0_D3 0x14 -#define FMUX_GPIO_REG_IOCTRL_SD0_CD 0x18 -#define FMUX_GPIO_REG_IOCTRL_SD0_PWR_EN 0x1c -#define FMUX_GPIO_REG_IOCTRL_SPK_EN 0x20 -#define FMUX_GPIO_REG_IOCTRL_UART0_TX 0x24 -#define FMUX_GPIO_REG_IOCTRL_UART0_RX 0x28 -#define FMUX_GPIO_REG_IOCTRL_SPINOR_HOLD_X 0x2c -#define FMUX_GPIO_REG_IOCTRL_SPINOR_SCK 0x30 -#define FMUX_GPIO_REG_IOCTRL_SPINOR_MOSI 0x34 -#define FMUX_GPIO_REG_IOCTRL_SPINOR_WP_X 0x38 -#define FMUX_GPIO_REG_IOCTRL_SPINOR_MISO 0x3c -#define FMUX_GPIO_REG_IOCTRL_SPINOR_CS_X 0x40 -#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TMS 0x44 -#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TCK 0x48 -#define FMUX_GPIO_REG_IOCTRL_IIC0_SCL 0x4c -#define FMUX_GPIO_REG_IOCTRL_IIC0_SDA 0x50 -#define FMUX_GPIO_REG_IOCTRL_AUX0 0x54 -#define FMUX_GPIO_REG_IOCTRL_GPIO_ZQ 0x58 -#define FMUX_GPIO_REG_IOCTRL_PWR_VBAT_DET 0x5c -#define FMUX_GPIO_REG_IOCTRL_PWR_RSTN 0x60 -#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ1 0x64 -#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ2 0x68 -#define FMUX_GPIO_REG_IOCTRL_PWR_WAKEUP0 0x6c -#define FMUX_GPIO_REG_IOCTRL_PWR_BUTTON1 0x70 -#define FMUX_GPIO_REG_IOCTRL_XTAL_XIN 0x74 -#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO0 0x78 -#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO1 0x7c -#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO2 0x80 -#define FMUX_GPIO_REG_IOCTRL_SD1_GPIO1 0x84 -#define FMUX_GPIO_REG_IOCTRL_SD1_GPIO0 0x88 -#define FMUX_GPIO_REG_IOCTRL_SD1_D3 0x8c -#define FMUX_GPIO_REG_IOCTRL_SD1_D2 0x90 -#define FMUX_GPIO_REG_IOCTRL_SD1_D1 0x94 -#define FMUX_GPIO_REG_IOCTRL_SD1_D0 0x98 -#define FMUX_GPIO_REG_IOCTRL_SD1_CMD 0x9c -#define FMUX_GPIO_REG_IOCTRL_SD1_CLK 0xa0 -#define FMUX_GPIO_REG_IOCTRL_PWM0_BUCK 0xa4 -#define FMUX_GPIO_REG_IOCTRL_ADC1 0xa8 -#define FMUX_GPIO_REG_IOCTRL_USB_VBUS_DET 0xac -#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MISO 0xb0 -#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MOSI 0xb4 -#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_CS 0xb8 -#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_SCK 0xbc -#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXP 0xc0 -#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXM 0xc4 -#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXP 0xc8 -#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXM 0xcc -#define FMUX_GPIO_REG_IOCTRL_GPIO_RTX 0xd0 -#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4N 0xd4 -#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4P 0xd8 -#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3N 0xdc -#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3P 0xe0 -#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2N 0xe4 -#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2P 0xe8 -#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1N 0xec -#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1P 0xf0 -#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0N 0xf4 -#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0P 0xf8 -#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM2 0xfc -#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP2 0x100 -#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM1 0x104 -#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP1 0x108 -#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM0 0x10c -#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP0 0x110 -#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE0 0x114 -#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE1 0x118 -#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE2 0x11c -#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINL_MIC 0x120 -#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINR_MIC 0x124 -#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTL 0x128 -#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTR 0x12c -#define FMUX_GPIO_REG_DEVMATRIX_UART0_IP_SEL 0x1d4 -#define FMUX_GPIO_REG_DEVMATRIX_UART1_IP_SEL 0x1d8 -#define FMUX_GPIO_REG_DEVMATRIX_UART2_IP_SEL 0x1dc -#define FMUX_GPIO_REG_DEVMATRIX_UART3_IP_SEL 0x1e0 -#define FMUX_GPIO_REG_DEVMATRIX_UART4_IP_SEL 0x1e4 -#define FMUX_GPIO_FUNCSEL_SD0_CLK 0x0 -#define FMUX_GPIO_FUNCSEL_SD0_CLK_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_SD0_CLK_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_SD0_CMD 0x4 -#define FMUX_GPIO_FUNCSEL_SD0_CMD_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_SD0_CMD_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_SD0_D0 0x8 -#define FMUX_GPIO_FUNCSEL_SD0_D0_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_SD0_D0_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_SD0_D1 0xc -#define FMUX_GPIO_FUNCSEL_SD0_D1_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_SD0_D1_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_SD0_D2 0x10 -#define FMUX_GPIO_FUNCSEL_SD0_D2_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_SD0_D2_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_SD0_D3 0x14 -#define FMUX_GPIO_FUNCSEL_SD0_D3_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_SD0_D3_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_SD0_CD 0x18 -#define FMUX_GPIO_FUNCSEL_SD0_CD_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_SD0_CD_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN 0x1c -#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_SPK_EN 0x20 -#define FMUX_GPIO_FUNCSEL_SPK_EN_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_SPK_EN_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_UART0_TX 0x24 -#define FMUX_GPIO_FUNCSEL_UART0_TX_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_UART0_TX_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_UART0_RX 0x28 -#define FMUX_GPIO_FUNCSEL_UART0_RX_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_UART0_RX_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_SPINOR_HOLD_X 0x2c -#define FMUX_GPIO_FUNCSEL_SPINOR_HOLD_X_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_SPINOR_HOLD_X_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_SPINOR_SCK 0x30 -#define FMUX_GPIO_FUNCSEL_SPINOR_SCK_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_SPINOR_SCK_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_SPINOR_MOSI 0x34 -#define FMUX_GPIO_FUNCSEL_SPINOR_MOSI_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_SPINOR_MOSI_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_SPINOR_WP_X 0x38 -#define FMUX_GPIO_FUNCSEL_SPINOR_WP_X_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_SPINOR_WP_X_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_SPINOR_MISO 0x3c -#define FMUX_GPIO_FUNCSEL_SPINOR_MISO_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_SPINOR_MISO_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_SPINOR_CS_X 0x40 -#define FMUX_GPIO_FUNCSEL_SPINOR_CS_X_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_SPINOR_CS_X_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS 0x44 -#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK 0x48 -#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_IIC0_SCL 0x4c -#define FMUX_GPIO_FUNCSEL_IIC0_SCL_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_IIC0_SCL_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_IIC0_SDA 0x50 -#define FMUX_GPIO_FUNCSEL_IIC0_SDA_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_IIC0_SDA_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_AUX0 0x54 -#define FMUX_GPIO_FUNCSEL_AUX0_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_AUX0_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_GPIO_ZQ 0x58 -#define FMUX_GPIO_FUNCSEL_GPIO_ZQ_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_GPIO_ZQ_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET 0x5c -#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PWR_RSTN 0x60 -#define FMUX_GPIO_FUNCSEL_PWR_RSTN_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PWR_RSTN_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PWR_SEQ1 0x64 -#define FMUX_GPIO_FUNCSEL_PWR_SEQ1_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PWR_SEQ1_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PWR_SEQ2 0x68 -#define FMUX_GPIO_FUNCSEL_PWR_SEQ2_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PWR_SEQ2_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0 0x6c -#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1 0x70 -#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_XTAL_XIN 0x74 -#define FMUX_GPIO_FUNCSEL_XTAL_XIN_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_XTAL_XIN_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PWR_GPIO0 0x78 -#define FMUX_GPIO_FUNCSEL_PWR_GPIO0_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PWR_GPIO0_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PWR_GPIO1 0x7c -#define FMUX_GPIO_FUNCSEL_PWR_GPIO1_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PWR_GPIO1_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PWR_GPIO2 0x80 -#define FMUX_GPIO_FUNCSEL_PWR_GPIO2_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PWR_GPIO2_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_SD1_GPIO1 0x84 -#define FMUX_GPIO_FUNCSEL_SD1_GPIO1_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_SD1_GPIO1_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_SD1_GPIO0 0x88 -#define FMUX_GPIO_FUNCSEL_SD1_GPIO0_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_SD1_GPIO0_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_SD1_D3 0x8c -#define FMUX_GPIO_FUNCSEL_SD1_D3_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_SD1_D3_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_SD1_D2 0x90 -#define FMUX_GPIO_FUNCSEL_SD1_D2_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_SD1_D2_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_SD1_D1 0x94 -#define FMUX_GPIO_FUNCSEL_SD1_D1_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_SD1_D1_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_SD1_D0 0x98 -#define FMUX_GPIO_FUNCSEL_SD1_D0_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_SD1_D0_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_SD1_CMD 0x9c -#define FMUX_GPIO_FUNCSEL_SD1_CMD_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_SD1_CMD_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_SD1_CLK 0xa0 -#define FMUX_GPIO_FUNCSEL_SD1_CLK_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_SD1_CLK_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PWM0_BUCK 0xa4 -#define FMUX_GPIO_FUNCSEL_PWM0_BUCK_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PWM0_BUCK_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_ADC1 0xa8 -#define FMUX_GPIO_FUNCSEL_ADC1_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_ADC1_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET 0xac -#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO 0xb0 -#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI 0xb4 -#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS 0xb8 -#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK 0xbc -#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP 0xc0 -#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM 0xc4 -#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP 0xc8 -#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM 0xcc -#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_GPIO_RTX 0xd0 -#define FMUX_GPIO_FUNCSEL_GPIO_RTX_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_GPIO_RTX_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N 0xd4 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P 0xd8 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N 0xdc -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P 0xe0 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N 0xe4 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P 0xe8 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N 0xec -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P 0xf0 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N 0xf4 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P 0xf8 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2 0xfc -#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2 0x100 -#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1 0x104 -#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1 0x108 -#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0 0x10c -#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0 0x110 -#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PKG_TYPE0 0x114 -#define FMUX_GPIO_FUNCSEL_PKG_TYPE0_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PKG_TYPE0_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PKG_TYPE1 0x118 -#define FMUX_GPIO_FUNCSEL_PKG_TYPE1_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PKG_TYPE1_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PKG_TYPE2 0x11c -#define FMUX_GPIO_FUNCSEL_PKG_TYPE2_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PKG_TYPE2_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC 0x120 -#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC 0x124 -#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL 0x128 -#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_MASK 0x7 -#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR 0x12c -#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_OFFSET 0 -#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_MASK 0x7 -#define FMUX_GPIO_MUX_UART0_IP_SEL 0x1d4 -#define FMUX_GPIO_MUX_UART0_IP_SEL_OFFSET 0 -#define FMUX_GPIO_MUX_UART0_IP_SEL_MASK 0x7 -#define FMUX_GPIO_MUX_UART1_IP_SEL 0x1d8 -#define FMUX_GPIO_MUX_UART1_IP_SEL_OFFSET 0 -#define FMUX_GPIO_MUX_UART1_IP_SEL_MASK 0x7 -#define FMUX_GPIO_MUX_UART2_IP_SEL 0x1dc -#define FMUX_GPIO_MUX_UART2_IP_SEL_OFFSET 0 -#define FMUX_GPIO_MUX_UART2_IP_SEL_MASK 0x7 -#define FMUX_GPIO_MUX_UART3_IP_SEL 0x1e0 -#define FMUX_GPIO_MUX_UART3_IP_SEL_OFFSET 0 -#define FMUX_GPIO_MUX_UART3_IP_SEL_MASK 0x7 -#define FMUX_GPIO_MUX_UART4_IP_SEL 0x1e4 -#define FMUX_GPIO_MUX_UART4_IP_SEL_OFFSET 0 -#define FMUX_GPIO_MUX_UART4_IP_SEL_MASK 0x7 - -#endif /* __CV180X_REG_FMUX_GPIO_H__ */ diff --git a/bsp/cvitek/drivers/cv1800b/mmio.h b/bsp/cvitek/drivers/cv1800b/mmio.h deleted file mode 100644 index bc36d5a3ca..0000000000 --- a/bsp/cvitek/drivers/cv1800b/mmio.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __MMIO_H__ -#define __MMIO_H__ -#include -#include "types.h" - -#define __raw_readb(a) (*(volatile unsigned char *)(a)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_readl(a) (*(volatile unsigned int *)(a)) -#define __raw_readq(a) (*(volatile unsigned long long *)(a)) - -#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) -#define __raw_writeq(v,a) (*(volatile unsigned long long *)(a) = (v)) - -/* - * I/O memory access primitives. Reads are ordered relative to any - * following Normal memory access. Writes are ordered relative to any prior - * Normal memory access. The memory barriers here are necessary as RISC-V - * doesn't define any ordering between the memory space and the I/O space. - */ -#define __io_br() do {} while (0) -#define __io_ar(v) __asm__ __volatile__ ("fence i,r" : : : "memory") -#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory") -//#define __io_aw() mmiowb_set_pending() -#define __io_aw() do {} while (0) - -#define readb(c) ({ u8 __v; __io_br(); __v = __raw_readb(c); __io_ar(__v); __v; }) -#define readw(c) ({ u16 __v; __io_br(); __v = __raw_readw(c); __io_ar(__v); __v; }) -#define readl(c) ({ u32 __v; __io_br(); __v = __raw_readl(c); __io_ar(__v); __v; }) - -#define writeb(v, c) ({ __io_bw(); __raw_writeb((v), (c)); __io_aw(); }) -#define writew(v, c) ({ __io_bw(); __raw_writew((v), (c)); __io_aw(); }) -#define writel(v, c) ({ __io_bw(); __raw_writel((v), (c)); __io_aw(); }) - - -#ifdef CONFIG_64BIT -#define readq(c) ({ u64 __v; __io_br(); __v = __raw_readq(c); __io_ar(__v); __v; }) -#define writeq(v, c) ({ __io_bw(); __raw_writeq((v), (c)); __io_aw(); }) -#endif // CONFIG_64BIT - -/* -#define __raw_readb(a) (*(volatile unsigned char *)(a)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_readl(a) (*(volatile unsigned int *)(a)) -#define __raw_readq(a) (*(volatile unsigned long long *)(a)) - -#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) -#define __raw_writeq(v,a) (*(volatile unsigned long long *)(a) = (v)) - -#define readb(a) __raw_readb(a) -#define readw(a) __raw_readw(a) -#define readl(a) __raw_readl(a) -#define readq(a) __raw_readq(a) - -#define writeb(v, a) __raw_writeb(v,a) -#define writew(v, a) __raw_writew(v,a) -#define writel(v, a) __raw_writel(v,a) -#define writeq(v, a) __raw_writeq(v,a) - -#define cpu_write8(a, v) writeb(a, v) -#define cpu_write16(a, v) writew(a, v) -#define cpu_write32(a, v) writel(a, v) -*/ - -#define mmio_wr32 mmio_write_32 -#define mmio_rd32 mmio_read_32 - -static inline void mmio_write_8(uintptr_t addr, uint8_t value) -{ - writeb(value, (void *) addr); -} - -static inline uint8_t mmio_read_8(uintptr_t addr) -{ - return readb((void *) addr); -} - -static inline void mmio_write_16(uintptr_t addr, uint16_t value) -{ - writew(value, (void *) addr); -} - -static inline uint16_t mmio_read_16(uintptr_t addr) -{ - return readw((void *) addr); -} - -static inline void mmio_write_32(uintptr_t addr, uint32_t value) -{ - writel(value, (void *) addr); -} - -static inline uint32_t mmio_read_32(uintptr_t addr) -{ - return readl((void *) addr); -} - -static inline void mmio_write_64(uintptr_t addr, uint64_t value) -{ - writeq(value, (void *) addr); -} - -static inline uint64_t mmio_read_64(uintptr_t addr) -{ - return readq((void *) addr); -} - -static inline void mmio_clrbits_32(uintptr_t addr, uint32_t clear) -{ - writel(readl((void *) addr) & ~clear , (void *) addr); -} - -static inline void mmio_setbits_32(uintptr_t addr, uint32_t set) -{ - writel(readl((void *) addr) | set , (void *) addr); -} - -static inline void mmio_clrsetbits_32(uintptr_t addr, uint32_t clear, - uint32_t set) -{ - writel((readl((void *) addr) & ~clear) | set , (void *) addr); -} - -/* from Linux usage */ -#define ioremap(a, l) (a) - -#define _reg_read(addr) mmio_read_32((addr)) -#define _reg_write(addr, data) mmio_write_32((addr), (data)) -#define _reg_write_mask(addr, mask, data) mmio_clrsetbits_32(addr, mask, data) - -#define ioread8 readb -#define ioread16 readw -#define ioread32 readl -#define ioread64 readq - -#define iowrite8 writeb -#define iowrite16 writew -#define iowrite32 writel -#define iowrite64 writeq - -#endif /* __MMIO_H__ */ diff --git a/bsp/cvitek/drivers/cv1800b/pinctrl.h b/bsp/cvitek/drivers/cv1800b/pinctrl.h deleted file mode 100755 index 0e5c3c911c..0000000000 --- a/bsp/cvitek/drivers/cv1800b/pinctrl.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved. - * - * File Name: pinctrl.h - * Description: - */ - -#ifndef __PINCTRL_CV180X_H__ -#define __PINCTRL_CV180X_H__ - -#include "cv180x_pinlist_swconfig.h" -#include "cv180x_reg_fmux_gpio.h" - -#define PAD_MIPI_TXM4__MIPI_TXM4 0 -#define PAD_MIPI_TXP4__MIPI_TXP4 0 -#define PAD_MIPI_TXM3__MIPI_TXM3 0 -#define PAD_MIPI_TXP3__MIPI_TXP3 0 -#define PAD_MIPI_TXM2__MIPI_TXM2 0 -#define PAD_MIPI_TXP2__MIPI_TXP2 0 -#define PAD_MIPI_TXM1__MIPI_TXM1 0 -#define PAD_MIPI_TXP1__MIPI_TXP1 0 -#define PAD_MIPI_TXM0__MIPI_TXM0 0 -#define PAD_MIPI_TXP0__MIPI_TXP0 0 - -#define PINMUX_BASE 0x03001000 -#define PINMUX_MASK(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_MASK -#define PINMUX_OFFSET(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET -#define PINMUX_VALUE(PIN_NAME, FUNC_NAME) PIN_NAME##__##FUNC_NAME -#define PINMUX_CONFIG(PIN_NAME, FUNC_NAME) \ - mmio_clrsetbits_32(PINMUX_BASE + FMUX_GPIO_FUNCSEL_##PIN_NAME, \ - FMUX_GPIO_FUNCSEL_##PIN_NAME##_MASK << FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET, \ - PIN_NAME##__##FUNC_NAME) - -#endif /* __PINCTRL_CV180X_H__ */ diff --git a/bsp/cvitek/drivers/cv1800b/pwm/cvi_pwm.h b/bsp/cvitek/drivers/cv1800b/pwm/cvi_pwm.h deleted file mode 100644 index 27d49df1a3..0000000000 --- a/bsp/cvitek/drivers/cv1800b/pwm/cvi_pwm.h +++ /dev/null @@ -1,266 +0,0 @@ -#ifndef __CVI_PWM_H__ -#define __CVI_PWM_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -#define CVI_PWM0_BASE 0x03060000 -#define CVI_PWM1_BASE 0x03061000 -#define CVI_PWM2_BASE 0x03062000 -#define CVI_PWM3_BASE 0x03063000 - -typedef enum { - PWM_CHANNEL_0 = 0U, - PWM_CHANNEL_1, - PWM_CHANNEL_2, - PWM_CHANNEL_3, - PWM_CHANNEL_4, - PWM_CHANNEL_5, - PWM_CHANNEL_6, - PWM_CHANNEL_7, - PWM_CHANNEL_8, - PWM_CHANNEL_9, - PWM_CHANNEL_10, - PWM_CHANNEL_11, - PWM_CHANNEL_12, - PWM_CHANNEL_13, - PWM_CHANNEL_14, - PWM_CHANNEL_15, - PWM_CHANNEL_NUM -} cvi_pwm_channel_t; - - -struct cvi_pwm_regs_t { - uint32_t HLPERIOD0; - uint32_t PERIOD0; - uint32_t HLPERIOD1; - uint32_t PERIOD1; - uint32_t HLPERIOD2; - uint32_t PERIOD2; - uint32_t HLPERIOD3; - uint32_t PERIOD3; - uint32_t CAP_FREQNUM; - uint32_t CAP_FREQDATA; - uint32_t POLARITY; - uint32_t PWMSTART; - uint32_t PWMDONE; - uint32_t PWMUPDATE; - uint32_t PCOUNT0; - uint32_t PCOUNT1; - uint32_t PCOUNT2; - uint32_t PCOUNT3; - uint32_t PULSECOUNT0; - uint32_t PULSECOUNT1; - uint32_t PULSECOUNT2; - uint32_t PULSECOUNT3; - uint32_t SHIFTCOUNT0; - uint32_t SHIFTCOUNT1; - uint32_t SHIFTCOUNT2; - uint32_t SHIFTCOUNT3; - uint32_t SHIFTSTART; - uint32_t CAP_FREQEN; - uint32_t CAP_FREQDONE_NUM; - uint32_t PWM_OE; -}; - - -static struct cvi_pwm_regs_t cv182x_pwm_reg = { - .HLPERIOD0 = 0x0, - .PERIOD0 = 0x4, - .HLPERIOD1 = 0x8, - .PERIOD1 = 0xc, - .HLPERIOD2 = 0x10, - .PERIOD2 = 0x14, - .HLPERIOD3 = 0x18, - .PERIOD3 = 0x1c, - .CAP_FREQNUM = 0x20, - .CAP_FREQDATA = 0x24, - .POLARITY = 0x40, - .PWMSTART = 0x44, - .PWMDONE = 0x48, - .PWMUPDATE = 0x4c, - .PCOUNT0 = 0x50, - .PCOUNT1 = 0x54, - .PCOUNT2 = 0x58, - .PCOUNT3 = 0x5c, - .PULSECOUNT0 = 0x60, - .PULSECOUNT1 = 0x64, - .PULSECOUNT2 = 0x68, - .PULSECOUNT3 = 0x6c, - .SHIFTCOUNT0 = 0x80, - .SHIFTCOUNT1 = 0x84, - .SHIFTCOUNT2 = 0x88, - .SHIFTCOUNT3 = 0x8c, - .SHIFTSTART = 0x90, - .CAP_FREQEN = 0x9c, - .CAP_FREQDONE_NUM = 0xC0, - .PWM_OE = 0xd0, -}; - -static struct cvi_pwm_regs_t *cvi_pwm_reg = &cv182x_pwm_reg; - -#define PWM_HLPERIOD0(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->HLPERIOD0)) -#define PWM_PERIOD0(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD0)) -#define PWM_HLPERIOD1(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->HLPERIOD1)) -#define PWM_PERIOD1(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD1)) -#define PWM_HLPERIOD2(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->HLPERIOD2)) -#define PWM_PERIOD2(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD2)) -#define PWM_HLPERIOD3(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->HLPERIOD3)) -#define PWM_PERIOD3(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD3)) -#define PWM_HLPERIODX(reg_base, _ch_) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->HLPERIOD0 + (_ch_ << 3))) -#define PWM_PERIODX(reg_base, _ch_) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD0 * (1 + (_ch_ << 1)))) - -#define CAP_FREQNUM(reg_base, _ch_) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->CAP_FREQNUM + _ch_ * 8)) -#define CAP_FREQDATA(reg_base, _ch_) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->CAP_FREQDATA + _ch_ * 8)) - -#define PWM_POLARITY(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->POLARITY)) -#define PWM_PWMSTART(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PWMSTART)) -#define PWM_PWMDONE(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PWMDONE)) -#define PWM_PWMUPDATE(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PWMUPDATE)) - -#define PWM_PCOUNT0(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PCOUNT0)) -#define PWM_PCOUNT1(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PCOUNT1)) -#define PWM_PCOUNT2(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PCOUNT2)) -#define PWM_PCOUNT3(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PCOUNT3)) - -#define PWM_PULSECOUNT0(reg_base) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->PULSECOUNT0)) -#define PWM_PULSECOUNT1(reg_base) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->PULSECOUNT1)) -#define PWM_PULSECOUNT2(reg_base) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->PULSECOUNT2)) -#define PWM_PULSECOUNT3(reg_base) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->PULSECOUNT3)) - -#define PWM_SHIFTCOUNT0(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->SHIFTCOUNT0)) -#define PWM_SHIFTCOUNT1(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->SHIFTCOUNT1)) -#define PWM_SHIFTCOUNT2(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->SHIFTCOUNT2)) -#define PWM_SHIFTCOUNT3(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->SHIFTCOUNT3)) -#define PWM_SHIFTSTART(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->SHIFTSTART)) - -#define CAP_FREQEN(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->CAP_FREQEN)) -#define CAP_FREQDONE_NUM(reg_base, _ch_) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->CAP_FREQDONE_NUM + _ch_ * 4)) - -#define PWM_PWM_OE(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PWM_OE)) - - -/*! PWM Configure Register, offset: 0x00 */ -#define CVI_PWM_HIGH_PERIOD_Pos (0U) -#define CVI_PWM_HIGH_PERIOD_Msk (0xffffffff) - -#define CVI_PWM_PERIOD_Pos (0U) -#define CVI_PWM_PERIOD_Msk (0xffffffff) - -#define CVI_PWM_POLARITY_CH_Pos(_ch_) (_ch_) -#define CVI_PWM_POLARITY_CH_Msk(_ch_) (1U << CVI_PWM_POLARITY_CH_Pos(_ch_)) -#define CVI_PWM_POLARITY_CH_HIGH(_ch_) CVI_PWM_POLARITY_CH_Msk(_ch_) - -#define CVI_PWM_START_CH_Pos(_ch_) (_ch_) -#define CVI_PWM_START_CH_Msk(_ch_) (1U << CVI_PWM_START_CH_Pos(_ch_)) -#define CVI_PWM_START_CH_EN(_ch_) CVI_PWM_START_CH_Msk(_ch_) - -#define CVI_PWM_OUTPUT_CH_Pos(_ch_) (_ch_) -#define CVI_PWM_OUTPUT_CH_Msk(_ch_) (1U << CVI_PWM_OUTPUT_CH_Pos(_ch_)) -#define CVI_PWM_OUTPUT_CH_EN(_ch_) CVI_PWM_OUTPUT_CH_Msk(_ch_) - -#define CVI_CAP_FREQNUM_CH_Pos (0U) -#define CVI_CAP_FREQNUM_CH_Msk (0xffffffff) - -#define CVI_CAP_FREQEN_Pos(_ch_) (_ch_) -#define CVI_CAP_FREQEN_Msk(_ch_) (1U << CVI_CAP_FREQEN_Pos(_ch_)) -#define CVI_CAP_FREQEN(_ch_) CVI_CAP_FREQEN_Msk(_ch_) - -#define CVI_CAP_FREQDONE_NUM_Poa (0U) -#define CVI_CAP_FREQDONE_NUM_Msk (0xffffffff) - -#define CVI_CAP_FREQDATA_pos (0U) -#define CVI_CAP_FREQDATA_msk (0xffffffff) - -static inline void cvi_pwm_set_high_period_ch(unsigned long reg_base, uint32_t ch, unsigned long long value) -{ - PWM_HLPERIODX(reg_base, ch) = value; -} - -static inline unsigned long long cvi_pwm_get_high_period_ch(unsigned long reg_base, uint32_t ch) -{ - return PWM_HLPERIODX(reg_base, ch); -} - -static inline void cvi_pwm_set_period_ch(unsigned long reg_base, uint32_t ch, unsigned long long value) -{ - PWM_PERIODX(reg_base, ch) = value; -} - -static inline unsigned long long cvi_pwm_get_period_ch(unsigned long reg_base, uint32_t ch) -{ - return PWM_PERIODX(reg_base, ch); -} - -static inline void cvi_pwm_set_polarity_high_ch(unsigned long reg_base, uint32_t ch) -{ - PWM_POLARITY(reg_base) |= CVI_PWM_POLARITY_CH_HIGH(ch); -} - -static inline void cvi_pwm_set_polarity_low_ch(unsigned long reg_base, uint32_t ch) -{ - PWM_POLARITY(reg_base) &= ~CVI_PWM_POLARITY_CH_HIGH(ch); -} - -static inline uint32_t cvi_pwm_get_polarity(unsigned long reg_base, uint32_t ch) -{ - return (PWM_POLARITY(reg_base) & CVI_PWM_POLARITY_CH_Msk(ch)); -} - -static inline void cvi_pwm_start_en_ch(unsigned long reg_base, uint32_t ch) -{ - PWM_PWMSTART(reg_base) |= CVI_PWM_START_CH_EN(ch); -} - -static inline void cvi_pwm_start_dis_ch(unsigned long reg_base, uint32_t ch) -{ - PWM_PWMSTART(reg_base) &= ~CVI_PWM_START_CH_EN(ch); -} - -static inline void cvi_pwm_output_en_ch(unsigned long reg_base, uint32_t ch) -{ - PWM_PWM_OE(reg_base) |= CVI_PWM_OUTPUT_CH_EN(ch); -} - -static inline void cvi_pwm_input_en_ch(unsigned long reg_base, uint32_t ch) -{ - PWM_PWM_OE(reg_base) &= ~CVI_PWM_OUTPUT_CH_EN(ch); -} - -static inline void cvi_cap_set_freqnum_ch(unsigned long reg_base, uint32_t ch, uint32_t value) -{ - CAP_FREQNUM(reg_base, ch) = value; -} - -static inline void cvi_cap_freq_en_ch(unsigned long reg_base, uint32_t ch) -{ - CAP_FREQEN(reg_base) |= CVI_CAP_FREQEN(ch); -} - -static inline void cvi_cap_freq_dis_ch(unsigned long reg_base, uint32_t ch) -{ - CAP_FREQEN(reg_base) &= ~CVI_CAP_FREQEN(ch); -} - -static inline uint32_t cvi_cap_get_freq_done_num_ch(unsigned long reg_base, uint32_t ch) -{ - return CAP_FREQDONE_NUM(reg_base, ch); -} - -static inline uint32_t cvi_cap_get_freq_data_ch(unsigned long reg_base, uint32_t ch) -{ - return CAP_FREQDATA(reg_base, ch); -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/cvitek/drivers/cv1800b/types.h b/bsp/cvitek/drivers/cv1800b/types.h deleted file mode 100755 index b6a8bc006c..0000000000 --- a/bsp/cvitek/drivers/cv1800b/types.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _LINUX_TYPES_H -#define _LINUX_TYPES_H - -#ifndef __ASSEMBLY__ -#ifdef CONFIG_64BIT -typedef unsigned long uintptr_t; -typedef unsigned long size_t; -/* bsd */ -typedef unsigned char u_char; -typedef unsigned short u_short; -typedef unsigned int u_int; -typedef unsigned long u_long; - -/* sysv */ -typedef unsigned char unchar; -typedef unsigned short ushort; -typedef unsigned int uint; -typedef unsigned long ulong; - -typedef signed char s8; -typedef signed short s16; -typedef signed int s32; -typedef signed long s64; - -typedef unsigned char u8; -typedef unsigned short u16; -typedef unsigned int u32; -typedef unsigned long u64; - -typedef signed char __s8; -typedef signed short __s16; -typedef signed int __s32; -typedef signed long __s64; - -typedef unsigned char __u8; -typedef unsigned short __u16; -typedef unsigned int __u32; -typedef unsigned long __u64; - -#endif /* CONFIG_64BIT */ -#endif /* __ASSEMBLY__ */ -#endif /* _LINUX_TYPES_H */ diff --git a/bsp/cvitek/drivers/libraries/cv180x/cv180x_pinlist_swconfig.h b/bsp/cvitek/drivers/libraries/cv180x/cv180x_pinlist_swconfig.h new file mode 100755 index 0000000000..2a13a616ea --- /dev/null +++ b/bsp/cvitek/drivers/libraries/cv180x/cv180x_pinlist_swconfig.h @@ -0,0 +1,407 @@ +//##============================================================================== +//##=== This script is generate by genswconfig.pl from .\00_Phobos_Pinlist_20220315.xls +//##=== Generate Time stamp is : 2022-03-17 14:04:49 +//##============================================================================== + +#ifndef __CV180X_PINLIST_SWCONFIG_H__ +#define __CV180X_PINLIST_SWCONFIG_H__ + +#define SD0_CLK__SDIO0_CLK 0 +#define SD0_CLK__IIC1_SDA 1 +#define SD0_CLK__SPI0_SCK 2 +#define SD0_CLK__XGPIOA_7 3 +#define SD0_CLK__PWM_15 5 +#define SD0_CLK__EPHY_LNK_LED 6 +#define SD0_CLK__DBG_0 7 +#define SD0_CMD__SDIO0_CMD 0 +#define SD0_CMD__IIC1_SCL 1 +#define SD0_CMD__SPI0_SDO 2 +#define SD0_CMD__XGPIOA_8 3 +#define SD0_CMD__PWM_14 5 +#define SD0_CMD__EPHY_SPD_LED 6 +#define SD0_CMD__DBG_1 7 +#define SD0_D0__SDIO0_D_0 0 +#define SD0_D0__CAM_MCLK1 1 +#define SD0_D0__SPI0_SDI 2 +#define SD0_D0__XGPIOA_9 3 +#define SD0_D0__UART3_TX 4 +#define SD0_D0__PWM_13 5 +#define SD0_D0__WG0_D0 6 +#define SD0_D0__DBG_2 7 +#define SD0_D1__SDIO0_D_1 0 +#define SD0_D1__IIC1_SDA 1 +#define SD0_D1__AUX0 2 +#define SD0_D1__XGPIOA_10 3 +#define SD0_D1__UART1_TX 4 +#define SD0_D1__PWM_12 5 +#define SD0_D1__WG0_D1 6 +#define SD0_D1__DBG_3 7 +#define SD0_D2__SDIO0_D_2 0 +#define SD0_D2__IIC1_SCL 1 +#define SD0_D2__AUX1 2 +#define SD0_D2__XGPIOA_11 3 +#define SD0_D2__UART1_RX 4 +#define SD0_D2__PWM_11 5 +#define SD0_D2__WG1_D0 6 +#define SD0_D2__DBG_4 7 +#define SD0_D3__SDIO0_D_3 0 +#define SD0_D3__CAM_MCLK0 1 +#define SD0_D3__SPI0_CS_X 2 +#define SD0_D3__XGPIOA_12 3 +#define SD0_D3__UART3_RX 4 +#define SD0_D3__PWM_10 5 +#define SD0_D3__WG1_D1 6 +#define SD0_D3__DBG_5 7 +#define SD0_CD__SDIO0_CD 0 +#define SD0_CD__XGPIOA_13 3 +#define SD0_PWR_EN__SDIO0_PWR_EN 0 +#define SD0_PWR_EN__XGPIOA_14 3 +#define SPK_EN__XGPIOA_15 3 +#define UART0_TX__UART0_TX 0 +#define UART0_TX__CAM_MCLK1 1 +#define UART0_TX__PWM_4 2 +#define UART0_TX__XGPIOA_16 3 +#define UART0_TX__UART1_TX 4 +#define UART0_TX__AUX1 5 +#define UART0_TX__JTAG_TMS 6 +#define UART0_TX__DBG_6 7 +#define UART0_RX__UART0_RX 0 +#define UART0_RX__CAM_MCLK0 1 +#define UART0_RX__PWM_5 2 +#define UART0_RX__XGPIOA_17 3 +#define UART0_RX__UART1_RX 4 +#define UART0_RX__AUX0 5 +#define UART0_RX__JTAG_TCK 6 +#define UART0_RX__DBG_7 7 +#define SPINOR_HOLD_X__SPINOR_HOLD_X 1 +#define SPINOR_HOLD_X__SPINAND_HOLD 2 +#define SPINOR_HOLD_X__XGPIOA_26 3 +#define SPINOR_SCK__SPINOR_SCK 1 +#define SPINOR_SCK__SPINAND_CLK 2 +#define SPINOR_SCK__XGPIOA_22 3 +#define SPINOR_MOSI__SPINOR_MOSI 1 +#define SPINOR_MOSI__SPINAND_MOSI 2 +#define SPINOR_MOSI__XGPIOA_25 3 +#define SPINOR_WP_X__SPINOR_WP_X 1 +#define SPINOR_WP_X__SPINAND_WP 2 +#define SPINOR_WP_X__XGPIOA_27 3 +#define SPINOR_MISO__SPINOR_MISO 1 +#define SPINOR_MISO__SPINAND_MISO 2 +#define SPINOR_MISO__XGPIOA_23 3 +#define SPINOR_CS_X__SPINOR_CS_X 1 +#define SPINOR_CS_X__SPINAND_CS 2 +#define SPINOR_CS_X__XGPIOA_24 3 +#define JTAG_CPU_TMS__JTAG_TMS 0 +#define JTAG_CPU_TMS__CAM_MCLK0 1 +#define JTAG_CPU_TMS__PWM_7 2 +#define JTAG_CPU_TMS__XGPIOA_19 3 +#define JTAG_CPU_TMS__UART1_RTS 4 +#define JTAG_CPU_TMS__AUX0 5 +#define JTAG_CPU_TMS__UART1_TX 6 +#define JTAG_CPU_TCK__JTAG_TCK 0 +#define JTAG_CPU_TCK__CAM_MCLK1 1 +#define JTAG_CPU_TCK__PWM_6 2 +#define JTAG_CPU_TCK__XGPIOA_18 3 +#define JTAG_CPU_TCK__UART1_CTS 4 +#define JTAG_CPU_TCK__AUX1 5 +#define JTAG_CPU_TCK__UART1_RX 6 +#define IIC0_SCL__CV_SCL0__CR_4WTDI 0 +#define IIC0_SDA__CV_SDA0__CR_4WTDO 0 +#define IIC0_SCL__JTAG_TDI 0 +#define IIC0_SCL__UART1_TX 1 +#define IIC0_SCL__UART2_TX 2 +#define IIC0_SCL__XGPIOA_28 3 +#define IIC0_SCL__IIC0_SCL 4 +#define IIC0_SCL__WG0_D0 5 +#define IIC0_SCL__DBG_10 7 +#define IIC0_SDA__JTAG_TDO 0 +#define IIC0_SDA__UART1_RX 1 +#define IIC0_SDA__UART2_RX 2 +#define IIC0_SDA__XGPIOA_29 3 +#define IIC0_SDA__IIC0_SDA 4 +#define IIC0_SDA__WG0_D1 5 +#define IIC0_SDA__WG1_D0 6 +#define IIC0_SDA__DBG_11 7 +#define AUX0__AUX0 0 +#define AUX0__XGPIOA_30 3 +#define AUX0__IIS1_MCLK 4 +#define AUX0__WG1_D1 6 +#define AUX0__DBG_12 7 +#define GPIO_ZQ__PWR_GPIO_24 3 +#define GPIO_ZQ__PWM_2 4 +#define PWR_VBAT_DET__PWR_VBAT_DET 0 +#define PWR_RSTN__PWR_RSTN 0 +#define PWR_SEQ1__PWR_SEQ1 0 +#define PWR_SEQ1__PWR_GPIO_3 3 +#define PWR_SEQ2__PWR_SEQ2 0 +#define PWR_SEQ2__PWR_GPIO_4 3 +#define PTEST__PWR_PTEST 0 +#define PWR_WAKEUP0__PWR_WAKEUP0 0 +#define PWR_WAKEUP0__PWR_IR0 1 +#define PWR_WAKEUP0__PWR_UART0_TX 2 +#define PWR_WAKEUP0__PWR_GPIO_6 3 +#define PWR_WAKEUP0__UART1_TX 4 +#define PWR_WAKEUP0__IIC4_SCL 5 +#define PWR_WAKEUP0__EPHY_LNK_LED 6 +#define PWR_WAKEUP0__WG2_D0 7 +#define PWR_BUTTON1__PWR_BUTTON1 0 +#define PWR_BUTTON1__PWR_GPIO_8 3 +#define PWR_BUTTON1__UART1_RX 4 +#define PWR_BUTTON1__IIC4_SDA 5 +#define PWR_BUTTON1__EPHY_SPD_LED 6 +#define PWR_BUTTON1__WG2_D1 7 +#define XTAL_XIN__PWR_XTAL_CLKIN 0 +#define PWR_GPIO0__PWR_GPIO_0 0 +#define PWR_GPIO0__UART2_TX 1 +#define PWR_GPIO0__PWR_UART0_RX 2 +#define PWR_GPIO0__PWM_8 4 +#define PWR_GPIO1__PWR_GPIO_1 0 +#define PWR_GPIO1__UART2_RX 1 +#define PWR_GPIO1__EPHY_LNK_LED 3 +#define PWR_GPIO1__PWM_9 4 +#define PWR_GPIO1__PWR_IIC_SCL 5 +#define PWR_GPIO1__IIC2_SCL 6 +#define PWR_GPIO1__IIC0_SDA 7 +#define PWR_GPIO2__PWR_GPIO_2 0 +#define PWR_GPIO2__PWR_SECTICK 2 +#define PWR_GPIO2__EPHY_SPD_LED 3 +#define PWR_GPIO2__PWM_10 4 +#define PWR_GPIO2__PWR_IIC_SDA 5 +#define PWR_GPIO2__IIC2_SDA 6 +#define PWR_GPIO2__IIC0_SCL 7 +#define SD1_GPIO1__UART4_TX 1 +#define SD1_GPIO1__PWR_GPIO_26 3 +#define SD1_GPIO1__PWM_10 7 +#define SD1_GPIO0__UART4_RX 1 +#define SD1_GPIO0__PWR_GPIO_25 3 +#define SD1_GPIO0__PWM_11 7 +#define SD1_D3__PWR_SD1_D3 0 +#define SD1_D3__SPI2_CS_X 1 +#define SD1_D3__IIC1_SCL 2 +#define SD1_D3__PWR_GPIO_18 3 +#define SD1_D3__CAM_MCLK0 4 +#define SD1_D3__UART3_CTS 5 +#define SD1_D3__PWR_SPINOR1_CS_X 6 +#define SD1_D3__PWM_4 7 +#define SD1_D2__PWR_SD1_D2 0 +#define SD1_D2__IIC1_SCL 1 +#define SD1_D2__UART2_TX 2 +#define SD1_D2__PWR_GPIO_19 3 +#define SD1_D2__CAM_MCLK0 4 +#define SD1_D2__UART3_TX 5 +#define SD1_D2__PWR_SPINOR1_HOLD_X 6 +#define SD1_D2__PWM_5 7 +#define SD1_D1__PWR_SD1_D1 0 +#define SD1_D1__IIC1_SDA 1 +#define SD1_D1__UART2_RX 2 +#define SD1_D1__PWR_GPIO_20 3 +#define SD1_D1__CAM_MCLK1 4 +#define SD1_D1__UART3_RX 5 +#define SD1_D1__PWR_SPINOR1_WP_X 6 +#define SD1_D1__PWM_6 7 +#define SD1_D0__PWR_SD1_D0 0 +#define SD1_D0__SPI2_SDI 1 +#define SD1_D0__IIC1_SDA 2 +#define SD1_D0__PWR_GPIO_21 3 +#define SD1_D0__CAM_MCLK1 4 +#define SD1_D0__UART3_RTS 5 +#define SD1_D0__PWR_SPINOR1_MISO 6 +#define SD1_D0__PWM_7 7 +#define SD1_CMD__PWR_SD1_CMD 0 +#define SD1_CMD__SPI2_SDO 1 +#define SD1_CMD__IIC3_SCL 2 +#define SD1_CMD__PWR_GPIO_22 3 +#define SD1_CMD__CAM_VS0 4 +#define SD1_CMD__EPHY_LNK_LED 5 +#define SD1_CMD__PWR_SPINOR1_MOSI 6 +#define SD1_CMD__PWM_8 7 +#define SD1_CLK__PWR_SD1_CLK 0 +#define SD1_CLK__SPI2_SCK 1 +#define SD1_CLK__IIC3_SDA 2 +#define SD1_CLK__PWR_GPIO_23 3 +#define SD1_CLK__CAM_HS0 4 +#define SD1_CLK__EPHY_SPD_LED 5 +#define SD1_CLK__PWR_SPINOR1_SCK 6 +#define SD1_CLK__PWM_9 7 +#define PWM0_BUCK__PWM_0 0 +#define PWM0_BUCK__XGPIOB_0 3 +#define ADC1__XGPIOB_3 3 +#define ADC1__KEY_COL2 4 +#define ADC1__PWM_3 6 +#define USB_VBUS_DET__USB_VBUS_DET 0 +#define USB_VBUS_DET__XGPIOB_6 3 +#define USB_VBUS_DET__CAM_MCLK0 4 +#define USB_VBUS_DET__CAM_MCLK1 5 +#define USB_VBUS_DET__PWM_4 6 +#define MUX_SPI1_MISO__UART3_RTS 1 +#define MUX_SPI1_MISO__IIC1_SDA 2 +#define MUX_SPI1_MISO__XGPIOB_8 3 +#define MUX_SPI1_MISO__PWM_9 4 +#define MUX_SPI1_MISO__KEY_COL1 5 +#define MUX_SPI1_MISO__SPI1_SDI 6 +#define MUX_SPI1_MISO__DBG_14 7 +#define MUX_SPI1_MOSI__UART3_RX 1 +#define MUX_SPI1_MOSI__IIC1_SCL 2 +#define MUX_SPI1_MOSI__XGPIOB_7 3 +#define MUX_SPI1_MOSI__PWM_8 4 +#define MUX_SPI1_MOSI__KEY_COL0 5 +#define MUX_SPI1_MOSI__SPI1_SDO 6 +#define MUX_SPI1_MOSI__DBG_13 7 +#define MUX_SPI1_CS__UART3_CTS 1 +#define MUX_SPI1_CS__CAM_MCLK0 2 +#define MUX_SPI1_CS__XGPIOB_10 3 +#define MUX_SPI1_CS__PWM_11 4 +#define MUX_SPI1_CS__KEY_ROW3 5 +#define MUX_SPI1_CS__SPI1_CS_X 6 +#define MUX_SPI1_CS__DBG_16 7 +#define MUX_SPI1_SCK__UART3_TX 1 +#define MUX_SPI1_SCK__CAM_MCLK1 2 +#define MUX_SPI1_SCK__XGPIOB_9 3 +#define MUX_SPI1_SCK__PWM_10 4 +#define MUX_SPI1_SCK__KEY_ROW2 5 +#define MUX_SPI1_SCK__SPI1_SCK 6 +#define MUX_SPI1_SCK__DBG_15 7 +#define PAD_ETH_TXP__UART3_RX 1 +#define PAD_ETH_TXP__IIC1_SCL 2 +#define PAD_ETH_TXP__XGPIOB_25 3 +#define PAD_ETH_TXP__PWM_13 4 +#define PAD_ETH_TXP__CAM_MCLK0 5 +#define PAD_ETH_TXP__SPI1_SDO 6 +#define PAD_ETH_TXP__IIS2_LRCK 7 +#define PAD_ETH_TXM__UART3_RTS 1 +#define PAD_ETH_TXM__IIC1_SDA 2 +#define PAD_ETH_TXM__XGPIOB_24 3 +#define PAD_ETH_TXM__PWM_12 4 +#define PAD_ETH_TXM__CAM_MCLK1 5 +#define PAD_ETH_TXM__SPI1_SDI 6 +#define PAD_ETH_TXM__IIS2_BCLK 7 +#define PAD_ETH_RXP__UART3_TX 1 +#define PAD_ETH_RXP__CAM_MCLK1 2 +#define PAD_ETH_RXP__XGPIOB_27 3 +#define PAD_ETH_RXP__PWM_15 4 +#define PAD_ETH_RXP__CAM_HS0 5 +#define PAD_ETH_RXP__SPI1_SCK 6 +#define PAD_ETH_RXP__IIS2_DO 7 +#define PAD_ETH_RXM__UART3_CTS 1 +#define PAD_ETH_RXM__CAM_MCLK0 2 +#define PAD_ETH_RXM__XGPIOB_26 3 +#define PAD_ETH_RXM__PWM_14 4 +#define PAD_ETH_RXM__CAM_VS0 5 +#define PAD_ETH_RXM__SPI1_CS_X 6 +#define PAD_ETH_RXM__IIS2_DI 7 +#define GPIO_RTX__VI0_D_15 1 +#define GPIO_RTX__XGPIOB_23 3 +#define GPIO_RTX__PWM_1 4 +#define GPIO_RTX__CAM_MCLK0 5 +#define GPIO_RTX__IIS2_MCLK 7 +#define PAD_MIPIRX4N__VI0_CLK 1 +#define PAD_MIPIRX4N__IIC0_SCL 2 +#define PAD_MIPIRX4N__XGPIOC_2 3 +#define PAD_MIPIRX4N__IIC1_SDA 4 +#define PAD_MIPIRX4N__CAM_MCLK0 5 +#define PAD_MIPIRX4N__KEY_ROW0 6 +#define PAD_MIPIRX4N__MUX_SPI1_SCK 7 +#define PAD_MIPIRX4P__VI0_D_0 1 +#define PAD_MIPIRX4P__IIC0_SDA 2 +#define PAD_MIPIRX4P__XGPIOC_3 3 +#define PAD_MIPIRX4P__IIC1_SCL 4 +#define PAD_MIPIRX4P__CAM_MCLK1 5 +#define PAD_MIPIRX4P__KEY_ROW1 6 +#define PAD_MIPIRX4P__MUX_SPI1_CS 7 +#define PAD_MIPIRX3N__VI0_D_1 1 +#define PAD_MIPIRX3N__XGPIOC_4 3 +#define PAD_MIPIRX3N__CAM_MCLK0 4 +#define PAD_MIPIRX3N__MUX_SPI1_MISO 7 +#define PAD_MIPIRX3P__VI0_D_2 1 +#define PAD_MIPIRX3P__XGPIOC_5 3 +#define PAD_MIPIRX3P__MUX_SPI1_MOSI 7 +#define PAD_MIPIRX2N__VI0_D_3 1 +#define PAD_MIPIRX2N__XGPIOC_6 3 +#define PAD_MIPIRX2N__IIC4_SCL 5 +#define PAD_MIPIRX2N__DBG_6 7 +#define PAD_MIPIRX2P__VI0_D_4 1 +#define PAD_MIPIRX2P__XGPIOC_7 3 +#define PAD_MIPIRX2P__IIC4_SDA 5 +#define PAD_MIPIRX2P__DBG_7 7 +#define PAD_MIPIRX1N__VI0_D_5 1 +#define PAD_MIPIRX1N__XGPIOC_8 3 +#define PAD_MIPIRX1N__KEY_ROW3 6 +#define PAD_MIPIRX1N__DBG_8 7 +#define PAD_MIPIRX1P__VI0_D_6 1 +#define PAD_MIPIRX1P__XGPIOC_9 3 +#define PAD_MIPIRX1P__IIC1_SDA 4 +#define PAD_MIPIRX1P__KEY_ROW2 6 +#define PAD_MIPIRX1P__DBG_9 7 +#define PAD_MIPIRX0N__VI0_D_7 1 +#define PAD_MIPIRX0N__XGPIOC_10 3 +#define PAD_MIPIRX0N__IIC1_SCL 4 +#define PAD_MIPIRX0N__CAM_MCLK1 5 +#define PAD_MIPIRX0N__DBG_10 7 +#define PAD_MIPIRX0P__VI0_D_8 1 +#define PAD_MIPIRX0P__XGPIOC_11 3 +#define PAD_MIPIRX0P__CAM_MCLK0 4 +#define PAD_MIPIRX0P__DBG_11 7 +#define PAD_MIPI_TXM2__VI0_D_13 1 +#define PAD_MIPI_TXM2__IIC0_SDA 2 +#define PAD_MIPI_TXM2__XGPIOC_16 3 +#define PAD_MIPI_TXM2__IIC1_SDA 4 +#define PAD_MIPI_TXM2__PWM_8 5 +#define PAD_MIPI_TXM2__SPI0_SCK 6 +#define PAD_MIPI_TXP2__VI0_D_14 1 +#define PAD_MIPI_TXP2__IIC0_SCL 2 +#define PAD_MIPI_TXP2__XGPIOC_17 3 +#define PAD_MIPI_TXP2__IIC1_SCL 4 +#define PAD_MIPI_TXP2__PWM_9 5 +#define PAD_MIPI_TXP2__SPI0_CS_X 6 +#define PAD_MIPI_TXP2__IIS1_MCLK 7 +#define PAD_MIPI_TXM1__SPI3_SDO 0 +#define PAD_MIPI_TXM1__VI0_D_11 1 +#define PAD_MIPI_TXM1__IIS1_LRCK 2 +#define PAD_MIPI_TXM1__XGPIOC_14 3 +#define PAD_MIPI_TXM1__IIC2_SDA 4 +#define PAD_MIPI_TXM1__PWM_10 5 +#define PAD_MIPI_TXM1__SPI0_SDO 6 +#define PAD_MIPI_TXM1__DBG_14 7 +#define PAD_MIPI_TXP1__SPI3_SDI 0 +#define PAD_MIPI_TXP1__VI0_D_12 1 +#define PAD_MIPI_TXP1__IIS1_DO 2 +#define PAD_MIPI_TXP1__XGPIOC_15 3 +#define PAD_MIPI_TXP1__IIC2_SCL 4 +#define PAD_MIPI_TXP1__PWM_11 5 +#define PAD_MIPI_TXP1__SPI0_SDI 6 +#define PAD_MIPI_TXP1__DBG_15 7 +#define PAD_MIPI_TXM0__SPI3_SCK 0 +#define PAD_MIPI_TXM0__VI0_D_9 1 +#define PAD_MIPI_TXM0__IIS1_DI 2 +#define PAD_MIPI_TXM0__XGPIOC_12 3 +#define PAD_MIPI_TXM0__CAM_MCLK1 4 +#define PAD_MIPI_TXM0__PWM_14 5 +#define PAD_MIPI_TXM0__CAM_VS0 6 +#define PAD_MIPI_TXM0__DBG_12 7 +#define PAD_MIPI_TXP0__SPI3_CS_X 0 +#define PAD_MIPI_TXP0__VI0_D_10 1 +#define PAD_MIPI_TXP0__IIS1_BCLK 2 +#define PAD_MIPI_TXP0__XGPIOC_13 3 +#define PAD_MIPI_TXP0__CAM_MCLK0 4 +#define PAD_MIPI_TXP0__PWM_15 5 +#define PAD_MIPI_TXP0__CAM_HS0 6 +#define PAD_MIPI_TXP0__DBG_13 7 +#define PKG_TYPE0__PKG_TYPE0 0 +#define PKG_TYPE1__PKG_TYPE1 0 +#define PKG_TYPE2__PKG_TYPE2 0 +#define PAD_AUD_AINL_MIC__XGPIOC_23 3 +#define PAD_AUD_AINL_MIC__IIS1_BCLK 4 +#define PAD_AUD_AINL_MIC__IIS2_BCLK 5 +#define PAD_AUD_AINR_MIC__XGPIOC_22 3 +#define PAD_AUD_AINR_MIC__IIS1_DO 4 +#define PAD_AUD_AINR_MIC__IIS2_DI 5 +#define PAD_AUD_AINR_MIC__IIS1_DI 6 +#define PAD_AUD_AOUTL__XGPIOC_25 3 +#define PAD_AUD_AOUTL__IIS1_LRCK 4 +#define PAD_AUD_AOUTL__IIS2_LRCK 5 +#define PAD_AUD_AOUTR__XGPIOC_24 3 +#define PAD_AUD_AOUTR__IIS1_DI 4 +#define PAD_AUD_AOUTR__IIS2_DO 5 +#define PAD_AUD_AOUTR__IIS1_DO 6 + +#endif /* __CV180X_PINLIST_SWCONFIG_H__ */ diff --git a/bsp/cvitek/drivers/libraries/cv180x/cv180x_pinmux.h b/bsp/cvitek/drivers/libraries/cv180x/cv180x_pinmux.h new file mode 100755 index 0000000000..1b72bc23ea --- /dev/null +++ b/bsp/cvitek/drivers/libraries/cv180x/cv180x_pinmux.h @@ -0,0 +1,51 @@ +#ifndef _CV180X_PINMUX_H_ +#define _CV180X_PINMUX_H_ + +/* + * Pinmux definitions + */ +#define PINMUX_UART0 0 +#define PINMUX_UART1 1 +#define PINMUX_UART2 2 +#define PINMUX_UART3 3 +#define PINMUX_UART3_2 4 +#define PINMUX_I2C0 5 +#define PINMUX_I2C1 6 +#define PINMUX_I2C2 7 +#define PINMUX_I2C3 8 +#define PINMUX_I2C4 9 +#define PINMUX_I2C4_2 10 +#define PINMUX_SPI0 11 +#define PINMUX_SPI1 12 +#define PINMUX_SPI2 13 +#define PINMUX_SPI2_2 14 +#define PINMUX_SPI3 15 +#define PINMUX_SPI3_2 16 +#define PINMUX_I2S0 17 +#define PINMUX_I2S1 18 +#define PINMUX_I2S2 19 +#define PINMUX_I2S3 20 +#define PINMUX_USBID 21 +#define PINMUX_SDIO0 22 +#define PINMUX_SDIO1 23 +#define PINMUX_ND 24 +#define PINMUX_EMMC 25 +#define PINMUX_SPI_NOR 26 +#define PINMUX_SPI_NAND 27 +#define PINMUX_CAM0 28 +#define PINMUX_CAM1 29 +#define PINMUX_PCM0 30 +#define PINMUX_PCM1 31 +#define PINMUX_CSI0 32 +#define PINMUX_CSI1 33 +#define PINMUX_CSI2 34 +#define PINMUX_DSI 35 +#define PINMUX_VI0 36 +#define PINMUX_VO 37 +#define PINMUX_RMII1 38 +#define PINMUX_EPHY_LED 39 +#define PINMUX_I80 40 +#define PINMUX_LVDS 41 +#define PINMUX_USB 42 + +#endif // end of _CV180X_PINMUX_H_ diff --git a/bsp/cvitek/drivers/libraries/cv180x/cv180x_reg_fmux_gpio.h b/bsp/cvitek/drivers/libraries/cv180x/cv180x_reg_fmux_gpio.h new file mode 100755 index 0000000000..a07236fba3 --- /dev/null +++ b/bsp/cvitek/drivers/libraries/cv180x/cv180x_reg_fmux_gpio.h @@ -0,0 +1,337 @@ +// $Module: fmux_gpio $ +// $RegisterBank Version: V 1.0.00 $ +// $Author: ghost $ +// $Date: Thu, 17 Mar 2022 04:53:31 PM $ +// + +//GEN REG ADDR/OFFSET/MASK + +#ifndef __CV180X_REG_FMUX_GPIO_H__ +#define __CV180X_REG_FMUX_GPIO_H__ + +#define FMUX_GPIO_REG_IOCTRL_SD0_CLK 0x0 +#define FMUX_GPIO_REG_IOCTRL_SD0_CMD 0x4 +#define FMUX_GPIO_REG_IOCTRL_SD0_D0 0x8 +#define FMUX_GPIO_REG_IOCTRL_SD0_D1 0xc +#define FMUX_GPIO_REG_IOCTRL_SD0_D2 0x10 +#define FMUX_GPIO_REG_IOCTRL_SD0_D3 0x14 +#define FMUX_GPIO_REG_IOCTRL_SD0_CD 0x18 +#define FMUX_GPIO_REG_IOCTRL_SD0_PWR_EN 0x1c +#define FMUX_GPIO_REG_IOCTRL_SPK_EN 0x20 +#define FMUX_GPIO_REG_IOCTRL_UART0_TX 0x24 +#define FMUX_GPIO_REG_IOCTRL_UART0_RX 0x28 +#define FMUX_GPIO_REG_IOCTRL_SPINOR_HOLD_X 0x2c +#define FMUX_GPIO_REG_IOCTRL_SPINOR_SCK 0x30 +#define FMUX_GPIO_REG_IOCTRL_SPINOR_MOSI 0x34 +#define FMUX_GPIO_REG_IOCTRL_SPINOR_WP_X 0x38 +#define FMUX_GPIO_REG_IOCTRL_SPINOR_MISO 0x3c +#define FMUX_GPIO_REG_IOCTRL_SPINOR_CS_X 0x40 +#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TMS 0x44 +#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TCK 0x48 +#define FMUX_GPIO_REG_IOCTRL_IIC0_SCL 0x4c +#define FMUX_GPIO_REG_IOCTRL_IIC0_SDA 0x50 +#define FMUX_GPIO_REG_IOCTRL_AUX0 0x54 +#define FMUX_GPIO_REG_IOCTRL_GPIO_ZQ 0x58 +#define FMUX_GPIO_REG_IOCTRL_PWR_VBAT_DET 0x5c +#define FMUX_GPIO_REG_IOCTRL_PWR_RSTN 0x60 +#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ1 0x64 +#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ2 0x68 +#define FMUX_GPIO_REG_IOCTRL_PWR_WAKEUP0 0x6c +#define FMUX_GPIO_REG_IOCTRL_PWR_BUTTON1 0x70 +#define FMUX_GPIO_REG_IOCTRL_XTAL_XIN 0x74 +#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO0 0x78 +#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO1 0x7c +#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO2 0x80 +#define FMUX_GPIO_REG_IOCTRL_SD1_GPIO1 0x84 +#define FMUX_GPIO_REG_IOCTRL_SD1_GPIO0 0x88 +#define FMUX_GPIO_REG_IOCTRL_SD1_D3 0x8c +#define FMUX_GPIO_REG_IOCTRL_SD1_D2 0x90 +#define FMUX_GPIO_REG_IOCTRL_SD1_D1 0x94 +#define FMUX_GPIO_REG_IOCTRL_SD1_D0 0x98 +#define FMUX_GPIO_REG_IOCTRL_SD1_CMD 0x9c +#define FMUX_GPIO_REG_IOCTRL_SD1_CLK 0xa0 +#define FMUX_GPIO_REG_IOCTRL_PWM0_BUCK 0xa4 +#define FMUX_GPIO_REG_IOCTRL_ADC1 0xa8 +#define FMUX_GPIO_REG_IOCTRL_USB_VBUS_DET 0xac +#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MISO 0xb0 +#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MOSI 0xb4 +#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_CS 0xb8 +#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_SCK 0xbc +#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXP 0xc0 +#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXM 0xc4 +#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXP 0xc8 +#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXM 0xcc +#define FMUX_GPIO_REG_IOCTRL_GPIO_RTX 0xd0 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4N 0xd4 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4P 0xd8 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3N 0xdc +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3P 0xe0 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2N 0xe4 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2P 0xe8 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1N 0xec +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1P 0xf0 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0N 0xf4 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0P 0xf8 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM2 0xfc +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP2 0x100 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM1 0x104 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP1 0x108 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM0 0x10c +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP0 0x110 +#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE0 0x114 +#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE1 0x118 +#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE2 0x11c +#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINL_MIC 0x120 +#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINR_MIC 0x124 +#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTL 0x128 +#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTR 0x12c +#define FMUX_GPIO_REG_DEVMATRIX_UART0_IP_SEL 0x1d4 +#define FMUX_GPIO_REG_DEVMATRIX_UART1_IP_SEL 0x1d8 +#define FMUX_GPIO_REG_DEVMATRIX_UART2_IP_SEL 0x1dc +#define FMUX_GPIO_REG_DEVMATRIX_UART3_IP_SEL 0x1e0 +#define FMUX_GPIO_REG_DEVMATRIX_UART4_IP_SEL 0x1e4 +#define FMUX_GPIO_FUNCSEL_SD0_CLK 0x0 +#define FMUX_GPIO_FUNCSEL_SD0_CLK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_CLK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_CMD 0x4 +#define FMUX_GPIO_FUNCSEL_SD0_CMD_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_CMD_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_D0 0x8 +#define FMUX_GPIO_FUNCSEL_SD0_D0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_D0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_D1 0xc +#define FMUX_GPIO_FUNCSEL_SD0_D1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_D1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_D2 0x10 +#define FMUX_GPIO_FUNCSEL_SD0_D2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_D2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_D3 0x14 +#define FMUX_GPIO_FUNCSEL_SD0_D3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_D3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_CD 0x18 +#define FMUX_GPIO_FUNCSEL_SD0_CD_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_CD_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN 0x1c +#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SPK_EN 0x20 +#define FMUX_GPIO_FUNCSEL_SPK_EN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SPK_EN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_UART0_TX 0x24 +#define FMUX_GPIO_FUNCSEL_UART0_TX_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_UART0_TX_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_UART0_RX 0x28 +#define FMUX_GPIO_FUNCSEL_UART0_RX_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_UART0_RX_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SPINOR_HOLD_X 0x2c +#define FMUX_GPIO_FUNCSEL_SPINOR_HOLD_X_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SPINOR_HOLD_X_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SPINOR_SCK 0x30 +#define FMUX_GPIO_FUNCSEL_SPINOR_SCK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SPINOR_SCK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SPINOR_MOSI 0x34 +#define FMUX_GPIO_FUNCSEL_SPINOR_MOSI_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SPINOR_MOSI_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SPINOR_WP_X 0x38 +#define FMUX_GPIO_FUNCSEL_SPINOR_WP_X_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SPINOR_WP_X_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SPINOR_MISO 0x3c +#define FMUX_GPIO_FUNCSEL_SPINOR_MISO_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SPINOR_MISO_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SPINOR_CS_X 0x40 +#define FMUX_GPIO_FUNCSEL_SPINOR_CS_X_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SPINOR_CS_X_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS 0x44 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK 0x48 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_IIC0_SCL 0x4c +#define FMUX_GPIO_FUNCSEL_IIC0_SCL_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_IIC0_SCL_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_IIC0_SDA 0x50 +#define FMUX_GPIO_FUNCSEL_IIC0_SDA_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_IIC0_SDA_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_AUX0 0x54 +#define FMUX_GPIO_FUNCSEL_AUX0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_AUX0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_GPIO_ZQ 0x58 +#define FMUX_GPIO_FUNCSEL_GPIO_ZQ_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_GPIO_ZQ_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET 0x5c +#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_RSTN 0x60 +#define FMUX_GPIO_FUNCSEL_PWR_RSTN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_RSTN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ1 0x64 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ2 0x68 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0 0x6c +#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1 0x70 +#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_XTAL_XIN 0x74 +#define FMUX_GPIO_FUNCSEL_XTAL_XIN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_XTAL_XIN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO0 0x78 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO1 0x7c +#define FMUX_GPIO_FUNCSEL_PWR_GPIO1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO2 0x80 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_GPIO1 0x84 +#define FMUX_GPIO_FUNCSEL_SD1_GPIO1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_GPIO1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_GPIO0 0x88 +#define FMUX_GPIO_FUNCSEL_SD1_GPIO0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_GPIO0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_D3 0x8c +#define FMUX_GPIO_FUNCSEL_SD1_D3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_D3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_D2 0x90 +#define FMUX_GPIO_FUNCSEL_SD1_D2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_D2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_D1 0x94 +#define FMUX_GPIO_FUNCSEL_SD1_D1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_D1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_D0 0x98 +#define FMUX_GPIO_FUNCSEL_SD1_D0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_D0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_CMD 0x9c +#define FMUX_GPIO_FUNCSEL_SD1_CMD_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_CMD_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_CLK 0xa0 +#define FMUX_GPIO_FUNCSEL_SD1_CLK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_CLK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWM0_BUCK 0xa4 +#define FMUX_GPIO_FUNCSEL_PWM0_BUCK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWM0_BUCK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_ADC1 0xa8 +#define FMUX_GPIO_FUNCSEL_ADC1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_ADC1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET 0xac +#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO 0xb0 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI 0xb4 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS 0xb8 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK 0xbc +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP 0xc0 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM 0xc4 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP 0xc8 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM 0xcc +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_GPIO_RTX 0xd0 +#define FMUX_GPIO_FUNCSEL_GPIO_RTX_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_GPIO_RTX_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N 0xd4 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P 0xd8 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N 0xdc +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P 0xe0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N 0xe4 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P 0xe8 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N 0xec +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P 0xf0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N 0xf4 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P 0xf8 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2 0xfc +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2 0x100 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1 0x104 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1 0x108 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0 0x10c +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0 0x110 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE0 0x114 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE1 0x118 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE2 0x11c +#define FMUX_GPIO_FUNCSEL_PKG_TYPE2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC 0x120 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC 0x124 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL 0x128 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR 0x12c +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_MASK 0x7 +#define FMUX_GPIO_MUX_UART0_IP_SEL 0x1d4 +#define FMUX_GPIO_MUX_UART0_IP_SEL_OFFSET 0 +#define FMUX_GPIO_MUX_UART0_IP_SEL_MASK 0x7 +#define FMUX_GPIO_MUX_UART1_IP_SEL 0x1d8 +#define FMUX_GPIO_MUX_UART1_IP_SEL_OFFSET 0 +#define FMUX_GPIO_MUX_UART1_IP_SEL_MASK 0x7 +#define FMUX_GPIO_MUX_UART2_IP_SEL 0x1dc +#define FMUX_GPIO_MUX_UART2_IP_SEL_OFFSET 0 +#define FMUX_GPIO_MUX_UART2_IP_SEL_MASK 0x7 +#define FMUX_GPIO_MUX_UART3_IP_SEL 0x1e0 +#define FMUX_GPIO_MUX_UART3_IP_SEL_OFFSET 0 +#define FMUX_GPIO_MUX_UART3_IP_SEL_MASK 0x7 +#define FMUX_GPIO_MUX_UART4_IP_SEL 0x1e4 +#define FMUX_GPIO_MUX_UART4_IP_SEL_OFFSET 0 +#define FMUX_GPIO_MUX_UART4_IP_SEL_MASK 0x7 + +#endif /* __CV180X_REG_FMUX_GPIO_H__ */ diff --git a/bsp/cvitek/drivers/libraries/cv180x/pinctrl.h b/bsp/cvitek/drivers/libraries/cv180x/pinctrl.h new file mode 100755 index 0000000000..0e5c3c911c --- /dev/null +++ b/bsp/cvitek/drivers/libraries/cv180x/pinctrl.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved. + * + * File Name: pinctrl.h + * Description: + */ + +#ifndef __PINCTRL_CV180X_H__ +#define __PINCTRL_CV180X_H__ + +#include "cv180x_pinlist_swconfig.h" +#include "cv180x_reg_fmux_gpio.h" + +#define PAD_MIPI_TXM4__MIPI_TXM4 0 +#define PAD_MIPI_TXP4__MIPI_TXP4 0 +#define PAD_MIPI_TXM3__MIPI_TXM3 0 +#define PAD_MIPI_TXP3__MIPI_TXP3 0 +#define PAD_MIPI_TXM2__MIPI_TXM2 0 +#define PAD_MIPI_TXP2__MIPI_TXP2 0 +#define PAD_MIPI_TXM1__MIPI_TXM1 0 +#define PAD_MIPI_TXP1__MIPI_TXP1 0 +#define PAD_MIPI_TXM0__MIPI_TXM0 0 +#define PAD_MIPI_TXP0__MIPI_TXP0 0 + +#define PINMUX_BASE 0x03001000 +#define PINMUX_MASK(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_MASK +#define PINMUX_OFFSET(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET +#define PINMUX_VALUE(PIN_NAME, FUNC_NAME) PIN_NAME##__##FUNC_NAME +#define PINMUX_CONFIG(PIN_NAME, FUNC_NAME) \ + mmio_clrsetbits_32(PINMUX_BASE + FMUX_GPIO_FUNCSEL_##PIN_NAME, \ + FMUX_GPIO_FUNCSEL_##PIN_NAME##_MASK << FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET, \ + PIN_NAME##__##FUNC_NAME) + +#endif /* __PINCTRL_CV180X_H__ */ diff --git a/bsp/cvitek/drivers/libraries/cv180x/pwm/cvi_pwm.h b/bsp/cvitek/drivers/libraries/cv180x/pwm/cvi_pwm.h new file mode 100755 index 0000000000..27d49df1a3 --- /dev/null +++ b/bsp/cvitek/drivers/libraries/cv180x/pwm/cvi_pwm.h @@ -0,0 +1,266 @@ +#ifndef __CVI_PWM_H__ +#define __CVI_PWM_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +#define CVI_PWM0_BASE 0x03060000 +#define CVI_PWM1_BASE 0x03061000 +#define CVI_PWM2_BASE 0x03062000 +#define CVI_PWM3_BASE 0x03063000 + +typedef enum { + PWM_CHANNEL_0 = 0U, + PWM_CHANNEL_1, + PWM_CHANNEL_2, + PWM_CHANNEL_3, + PWM_CHANNEL_4, + PWM_CHANNEL_5, + PWM_CHANNEL_6, + PWM_CHANNEL_7, + PWM_CHANNEL_8, + PWM_CHANNEL_9, + PWM_CHANNEL_10, + PWM_CHANNEL_11, + PWM_CHANNEL_12, + PWM_CHANNEL_13, + PWM_CHANNEL_14, + PWM_CHANNEL_15, + PWM_CHANNEL_NUM +} cvi_pwm_channel_t; + + +struct cvi_pwm_regs_t { + uint32_t HLPERIOD0; + uint32_t PERIOD0; + uint32_t HLPERIOD1; + uint32_t PERIOD1; + uint32_t HLPERIOD2; + uint32_t PERIOD2; + uint32_t HLPERIOD3; + uint32_t PERIOD3; + uint32_t CAP_FREQNUM; + uint32_t CAP_FREQDATA; + uint32_t POLARITY; + uint32_t PWMSTART; + uint32_t PWMDONE; + uint32_t PWMUPDATE; + uint32_t PCOUNT0; + uint32_t PCOUNT1; + uint32_t PCOUNT2; + uint32_t PCOUNT3; + uint32_t PULSECOUNT0; + uint32_t PULSECOUNT1; + uint32_t PULSECOUNT2; + uint32_t PULSECOUNT3; + uint32_t SHIFTCOUNT0; + uint32_t SHIFTCOUNT1; + uint32_t SHIFTCOUNT2; + uint32_t SHIFTCOUNT3; + uint32_t SHIFTSTART; + uint32_t CAP_FREQEN; + uint32_t CAP_FREQDONE_NUM; + uint32_t PWM_OE; +}; + + +static struct cvi_pwm_regs_t cv182x_pwm_reg = { + .HLPERIOD0 = 0x0, + .PERIOD0 = 0x4, + .HLPERIOD1 = 0x8, + .PERIOD1 = 0xc, + .HLPERIOD2 = 0x10, + .PERIOD2 = 0x14, + .HLPERIOD3 = 0x18, + .PERIOD3 = 0x1c, + .CAP_FREQNUM = 0x20, + .CAP_FREQDATA = 0x24, + .POLARITY = 0x40, + .PWMSTART = 0x44, + .PWMDONE = 0x48, + .PWMUPDATE = 0x4c, + .PCOUNT0 = 0x50, + .PCOUNT1 = 0x54, + .PCOUNT2 = 0x58, + .PCOUNT3 = 0x5c, + .PULSECOUNT0 = 0x60, + .PULSECOUNT1 = 0x64, + .PULSECOUNT2 = 0x68, + .PULSECOUNT3 = 0x6c, + .SHIFTCOUNT0 = 0x80, + .SHIFTCOUNT1 = 0x84, + .SHIFTCOUNT2 = 0x88, + .SHIFTCOUNT3 = 0x8c, + .SHIFTSTART = 0x90, + .CAP_FREQEN = 0x9c, + .CAP_FREQDONE_NUM = 0xC0, + .PWM_OE = 0xd0, +}; + +static struct cvi_pwm_regs_t *cvi_pwm_reg = &cv182x_pwm_reg; + +#define PWM_HLPERIOD0(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->HLPERIOD0)) +#define PWM_PERIOD0(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD0)) +#define PWM_HLPERIOD1(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->HLPERIOD1)) +#define PWM_PERIOD1(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD1)) +#define PWM_HLPERIOD2(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->HLPERIOD2)) +#define PWM_PERIOD2(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD2)) +#define PWM_HLPERIOD3(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->HLPERIOD3)) +#define PWM_PERIOD3(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD3)) +#define PWM_HLPERIODX(reg_base, _ch_) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->HLPERIOD0 + (_ch_ << 3))) +#define PWM_PERIODX(reg_base, _ch_) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PERIOD0 * (1 + (_ch_ << 1)))) + +#define CAP_FREQNUM(reg_base, _ch_) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->CAP_FREQNUM + _ch_ * 8)) +#define CAP_FREQDATA(reg_base, _ch_) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->CAP_FREQDATA + _ch_ * 8)) + +#define PWM_POLARITY(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->POLARITY)) +#define PWM_PWMSTART(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PWMSTART)) +#define PWM_PWMDONE(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PWMDONE)) +#define PWM_PWMUPDATE(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PWMUPDATE)) + +#define PWM_PCOUNT0(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PCOUNT0)) +#define PWM_PCOUNT1(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PCOUNT1)) +#define PWM_PCOUNT2(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PCOUNT2)) +#define PWM_PCOUNT3(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PCOUNT3)) + +#define PWM_PULSECOUNT0(reg_base) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->PULSECOUNT0)) +#define PWM_PULSECOUNT1(reg_base) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->PULSECOUNT1)) +#define PWM_PULSECOUNT2(reg_base) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->PULSECOUNT2)) +#define PWM_PULSECOUNT3(reg_base) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->PULSECOUNT3)) + +#define PWM_SHIFTCOUNT0(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->SHIFTCOUNT0)) +#define PWM_SHIFTCOUNT1(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->SHIFTCOUNT1)) +#define PWM_SHIFTCOUNT2(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->SHIFTCOUNT2)) +#define PWM_SHIFTCOUNT3(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->SHIFTCOUNT3)) +#define PWM_SHIFTSTART(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->SHIFTSTART)) + +#define CAP_FREQEN(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->CAP_FREQEN)) +#define CAP_FREQDONE_NUM(reg_base, _ch_) *((__IM uint32_t *)(reg_base + cvi_pwm_reg->CAP_FREQDONE_NUM + _ch_ * 4)) + +#define PWM_PWM_OE(reg_base) *((__IOM uint32_t *)(reg_base + cvi_pwm_reg->PWM_OE)) + + +/*! PWM Configure Register, offset: 0x00 */ +#define CVI_PWM_HIGH_PERIOD_Pos (0U) +#define CVI_PWM_HIGH_PERIOD_Msk (0xffffffff) + +#define CVI_PWM_PERIOD_Pos (0U) +#define CVI_PWM_PERIOD_Msk (0xffffffff) + +#define CVI_PWM_POLARITY_CH_Pos(_ch_) (_ch_) +#define CVI_PWM_POLARITY_CH_Msk(_ch_) (1U << CVI_PWM_POLARITY_CH_Pos(_ch_)) +#define CVI_PWM_POLARITY_CH_HIGH(_ch_) CVI_PWM_POLARITY_CH_Msk(_ch_) + +#define CVI_PWM_START_CH_Pos(_ch_) (_ch_) +#define CVI_PWM_START_CH_Msk(_ch_) (1U << CVI_PWM_START_CH_Pos(_ch_)) +#define CVI_PWM_START_CH_EN(_ch_) CVI_PWM_START_CH_Msk(_ch_) + +#define CVI_PWM_OUTPUT_CH_Pos(_ch_) (_ch_) +#define CVI_PWM_OUTPUT_CH_Msk(_ch_) (1U << CVI_PWM_OUTPUT_CH_Pos(_ch_)) +#define CVI_PWM_OUTPUT_CH_EN(_ch_) CVI_PWM_OUTPUT_CH_Msk(_ch_) + +#define CVI_CAP_FREQNUM_CH_Pos (0U) +#define CVI_CAP_FREQNUM_CH_Msk (0xffffffff) + +#define CVI_CAP_FREQEN_Pos(_ch_) (_ch_) +#define CVI_CAP_FREQEN_Msk(_ch_) (1U << CVI_CAP_FREQEN_Pos(_ch_)) +#define CVI_CAP_FREQEN(_ch_) CVI_CAP_FREQEN_Msk(_ch_) + +#define CVI_CAP_FREQDONE_NUM_Poa (0U) +#define CVI_CAP_FREQDONE_NUM_Msk (0xffffffff) + +#define CVI_CAP_FREQDATA_pos (0U) +#define CVI_CAP_FREQDATA_msk (0xffffffff) + +static inline void cvi_pwm_set_high_period_ch(unsigned long reg_base, uint32_t ch, unsigned long long value) +{ + PWM_HLPERIODX(reg_base, ch) = value; +} + +static inline unsigned long long cvi_pwm_get_high_period_ch(unsigned long reg_base, uint32_t ch) +{ + return PWM_HLPERIODX(reg_base, ch); +} + +static inline void cvi_pwm_set_period_ch(unsigned long reg_base, uint32_t ch, unsigned long long value) +{ + PWM_PERIODX(reg_base, ch) = value; +} + +static inline unsigned long long cvi_pwm_get_period_ch(unsigned long reg_base, uint32_t ch) +{ + return PWM_PERIODX(reg_base, ch); +} + +static inline void cvi_pwm_set_polarity_high_ch(unsigned long reg_base, uint32_t ch) +{ + PWM_POLARITY(reg_base) |= CVI_PWM_POLARITY_CH_HIGH(ch); +} + +static inline void cvi_pwm_set_polarity_low_ch(unsigned long reg_base, uint32_t ch) +{ + PWM_POLARITY(reg_base) &= ~CVI_PWM_POLARITY_CH_HIGH(ch); +} + +static inline uint32_t cvi_pwm_get_polarity(unsigned long reg_base, uint32_t ch) +{ + return (PWM_POLARITY(reg_base) & CVI_PWM_POLARITY_CH_Msk(ch)); +} + +static inline void cvi_pwm_start_en_ch(unsigned long reg_base, uint32_t ch) +{ + PWM_PWMSTART(reg_base) |= CVI_PWM_START_CH_EN(ch); +} + +static inline void cvi_pwm_start_dis_ch(unsigned long reg_base, uint32_t ch) +{ + PWM_PWMSTART(reg_base) &= ~CVI_PWM_START_CH_EN(ch); +} + +static inline void cvi_pwm_output_en_ch(unsigned long reg_base, uint32_t ch) +{ + PWM_PWM_OE(reg_base) |= CVI_PWM_OUTPUT_CH_EN(ch); +} + +static inline void cvi_pwm_input_en_ch(unsigned long reg_base, uint32_t ch) +{ + PWM_PWM_OE(reg_base) &= ~CVI_PWM_OUTPUT_CH_EN(ch); +} + +static inline void cvi_cap_set_freqnum_ch(unsigned long reg_base, uint32_t ch, uint32_t value) +{ + CAP_FREQNUM(reg_base, ch) = value; +} + +static inline void cvi_cap_freq_en_ch(unsigned long reg_base, uint32_t ch) +{ + CAP_FREQEN(reg_base) |= CVI_CAP_FREQEN(ch); +} + +static inline void cvi_cap_freq_dis_ch(unsigned long reg_base, uint32_t ch) +{ + CAP_FREQEN(reg_base) &= ~CVI_CAP_FREQEN(ch); +} + +static inline uint32_t cvi_cap_get_freq_done_num_ch(unsigned long reg_base, uint32_t ch) +{ + return CAP_FREQDONE_NUM(reg_base, ch); +} + +static inline uint32_t cvi_cap_get_freq_data_ch(unsigned long reg_base, uint32_t ch) +{ + return CAP_FREQDATA(reg_base, ch); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinlist_swconfig.h b/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinlist_swconfig.h new file mode 100755 index 0000000000..64d4ec9cdb --- /dev/null +++ b/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinlist_swconfig.h @@ -0,0 +1,653 @@ + +#define CAM_MCLK0__CAM_MCLK0 0 +#define CAM_MCLK0__AUX1 2 +#define CAM_MCLK0__XGPIOA_0 3 +#define CAM_PD0__IIS1_MCLK 1 +#define CAM_PD0__XGPIOA_1 3 +#define CAM_PD0__CAM_HS0 4 +#define CAM_RST0__XGPIOA_2 3 +#define CAM_RST0__CAM_VS0 4 +#define CAM_RST0__IIC4_SCL 6 +#define CAM_MCLK1__CAM_MCLK1 0 +#define CAM_MCLK1__AUX2 2 +#define CAM_MCLK1__XGPIOA_3 3 +#define CAM_MCLK1__CAM_HS0 4 +#define CAM_PD1__IIS1_MCLK 1 +#define CAM_PD1__XGPIOA_4 3 +#define CAM_PD1__CAM_VS0 4 +#define CAM_PD1__IIC4_SDA 6 +#define IIC3_SCL__IIC3_SCL 0 +#define IIC3_SCL__XGPIOA_5 3 +#define IIC3_SDA__IIC3_SDA 0 +#define IIC3_SDA__XGPIOA_6 3 +#define SD0_CLK__SDIO0_CLK 0 +#define SD0_CLK__IIC1_SDA 1 +#define SD0_CLK__SPI0_SCK 2 +#define SD0_CLK__XGPIOA_7 3 +#define SD0_CLK__PWM_15 5 +#define SD0_CLK__EPHY_LNK_LED 6 +#define SD0_CLK__DBG_0 7 +#define SD0_CMD__SDIO0_CMD 0 +#define SD0_CMD__IIC1_SCL 1 +#define SD0_CMD__SPI0_SDO 2 +#define SD0_CMD__XGPIOA_8 3 +#define SD0_CMD__PWM_14 5 +#define SD0_CMD__EPHY_SPD_LED 6 +#define SD0_CMD__DBG_1 7 +#define SD0_D0__SDIO0_D_0 0 +#define SD0_D0__CAM_MCLK1 1 +#define SD0_D0__SPI0_SDI 2 +#define SD0_D0__XGPIOA_9 3 +#define SD0_D0__UART3_TX 4 +#define SD0_D0__PWM_13 5 +#define SD0_D0__WG0_D0 6 +#define SD0_D0__DBG_2 7 +#define SD0_D1__SDIO0_D_1 0 +#define SD0_D1__IIC1_SDA 1 +#define SD0_D1__AUX0 2 +#define SD0_D1__XGPIOA_10 3 +#define SD0_D1__UART1_TX 4 +#define SD0_D1__PWM_12 5 +#define SD0_D1__WG0_D1 6 +#define SD0_D1__DBG_3 7 +#define SD0_D2__SDIO0_D_2 0 +#define SD0_D2__IIC1_SCL 1 +#define SD0_D2__AUX1 2 +#define SD0_D2__XGPIOA_11 3 +#define SD0_D2__UART1_RX 4 +#define SD0_D2__PWM_11 5 +#define SD0_D2__WG1_D0 6 +#define SD0_D2__DBG_4 7 +#define SD0_D3__SDIO0_D_3 0 +#define SD0_D3__CAM_MCLK0 1 +#define SD0_D3__SPI0_CS_X 2 +#define SD0_D3__XGPIOA_12 3 +#define SD0_D3__UART3_RX 4 +#define SD0_D3__PWM_10 5 +#define SD0_D3__WG1_D1 6 +#define SD0_D3__DBG_5 7 +#define SD0_CD__SDIO0_CD 0 +#define SD0_CD__XGPIOA_13 3 +#define SD0_PWR_EN__SDIO0_PWR_EN 0 +#define SD0_PWR_EN__XGPIOA_14 3 +#define SPK_EN__XGPIOA_15 3 +#define UART0_TX__UART0_TX 0 +#define UART0_TX__CAM_MCLK1 1 +#define UART0_TX__PWM_4 2 +#define UART0_TX__XGPIOA_16 3 +#define UART0_TX__UART1_TX 4 +#define UART0_TX__AUX1 5 +#define UART0_TX__DBG_6 7 +#define UART0_RX__UART0_RX 0 +#define UART0_RX__CAM_MCLK0 1 +#define UART0_RX__PWM_5 2 +#define UART0_RX__XGPIOA_17 3 +#define UART0_RX__UART1_RX 4 +#define UART0_RX__AUX0 5 +#define UART0_RX__DBG_7 7 +#define EMMC_RSTN__EMMC_RSTN 0 +#define EMMC_RSTN__XGPIOA_21 3 +#define EMMC_RSTN__AUX2 4 +#define EMMC_DAT2__EMMC_DAT_2 0 +#define EMMC_DAT2__SPINOR_HOLD_X 1 +#define EMMC_DAT2__SPINAND_HOLD 2 +#define EMMC_DAT2__XGPIOA_26 3 +#define EMMC_CLK__EMMC_CLK 0 +#define EMMC_CLK__SPINOR_SCK 1 +#define EMMC_CLK__SPINAND_CLK 2 +#define EMMC_CLK__XGPIOA_22 3 +#define EMMC_DAT0__EMMC_DAT_0 0 +#define EMMC_DAT0__SPINOR_MOSI 1 +#define EMMC_DAT0__SPINAND_MOSI 2 +#define EMMC_DAT0__XGPIOA_25 3 +#define EMMC_DAT3__EMMC_DAT_3 0 +#define EMMC_DAT3__SPINOR_WP_X 1 +#define EMMC_DAT3__SPINAND_WP 2 +#define EMMC_DAT3__XGPIOA_27 3 +#define EMMC_CMD__EMMC_CMD 0 +#define EMMC_CMD__SPINOR_MISO 1 +#define EMMC_CMD__SPINAND_MISO 2 +#define EMMC_CMD__XGPIOA_23 3 +#define EMMC_DAT1__EMMC_DAT_1 0 +#define EMMC_DAT1__SPINOR_CS_X 1 +#define EMMC_DAT1__SPINAND_CS 2 +#define EMMC_DAT1__XGPIOA_24 3 +#define JTAG_CPU_TMS__JTAG_CPU_TMS 0 +#define JTAG_CPU_TMS__CAM_MCLK0 1 +#define JTAG_CPU_TMS__PWM_7 2 +#define JTAG_CPU_TMS__XGPIOA_19 3 +#define JTAG_CPU_TMS__UART1_RTS 4 +#define JTAG_CPU_TMS__AUX0 5 +#define JTAG_CPU_TMS__UART1_TX 6 +#define JTAG_CPU_TMS__VO_D_28 7 +#define JTAG_CPU_TCK__JTAG_CPU_TCK 0 +#define JTAG_CPU_TCK__CAM_MCLK1 1 +#define JTAG_CPU_TCK__PWM_6 2 +#define JTAG_CPU_TCK__XGPIOA_18 3 +#define JTAG_CPU_TCK__UART1_CTS 4 +#define JTAG_CPU_TCK__AUX1 5 +#define JTAG_CPU_TCK__UART1_RX 6 +#define JTAG_CPU_TCK__VO_D_29 7 +#define JTAG_CPU_TRST__JTAG_CPU_TRST 0 +#define JTAG_CPU_TRST__XGPIOA_20 3 +#define JTAG_CPU_TRST__VO_D_30 6 +#define IIC0_SCL__IIC0_SCL 0 +#define IIC0_SCL__UART1_TX 1 +#define IIC0_SCL__UART2_TX 2 +#define IIC0_SCL__XGPIOA_28 3 +#define IIC0_SCL__WG0_D0 5 +#define IIC0_SCL__DBG_10 7 +#define IIC0_SDA__IIC0_SDA 0 +#define IIC0_SDA__UART1_RX 1 +#define IIC0_SDA__UART2_RX 2 +#define IIC0_SDA__XGPIOA_29 3 +#define IIC0_SDA__WG0_D1 5 +#define IIC0_SDA__WG1_D0 6 +#define IIC0_SDA__DBG_11 7 +#define AUX0__AUX0 0 +#define AUX0__XGPIOA_30 3 +#define AUX0__IIS1_MCLK 4 +#define AUX0__VO_D_31 5 +#define AUX0__WG1_D1 6 +#define AUX0__DBG_12 7 +#define PWR_VBAT_DET__PWR_VBAT_DET 0 +#define PWR_RSTN__PWR_RSTN 0 +#define PWR_SEQ1__PWR_SEQ1 0 +#define PWR_SEQ1__PWR_GPIO_3 3 +#define PWR_SEQ2__PWR_SEQ2 0 +#define PWR_SEQ2__PWR_GPIO_4 3 +#define PWR_SEQ3__PWR_SEQ3 0 +#define PWR_SEQ3__PWR_GPIO_5 3 +#define PTEST__PWR_PTEST 0 +#define PWR_WAKEUP0__PWR_WAKEUP0 0 +#define PWR_WAKEUP0__PWR_IR0 1 +#define PWR_WAKEUP0__PWR_UART0_TX 2 +#define PWR_WAKEUP0__PWR_GPIO_6 3 +#define PWR_WAKEUP0__UART1_TX 4 +#define PWR_WAKEUP0__IIC4_SCL 5 +#define PWR_WAKEUP0__EPHY_LNK_LED 6 +#define PWR_WAKEUP0__WG2_D0 7 +#define PWR_WAKEUP1__PWR_WAKEUP1 0 +#define PWR_WAKEUP1__PWR_IR1 1 +#define PWR_WAKEUP1__PWR_GPIO_7 3 +#define PWR_WAKEUP1__UART1_TX 4 +#define PWR_WAKEUP1__IIC4_SCL 5 +#define PWR_WAKEUP1__EPHY_LNK_LED 6 +#define PWR_WAKEUP1__WG0_D0 7 +#define PWR_BUTTON1__PWR_BUTTON1 0 +#define PWR_BUTTON1__PWR_GPIO_8 3 +#define PWR_BUTTON1__UART1_RX 4 +#define PWR_BUTTON1__IIC4_SDA 5 +#define PWR_BUTTON1__EPHY_SPD_LED 6 +#define PWR_BUTTON1__WG2_D1 7 +#define PWR_ON__PWR_ON 0 +#define PWR_ON__PWR_GPIO_9 3 +#define PWR_ON__UART1_RX 4 +#define PWR_ON__IIC4_SDA 5 +#define PWR_ON__EPHY_SPD_LED 6 +#define PWR_ON__WG0_D1 7 +#define XTAL_XIN__PWR_XTAL_CLKIN 0 +#define PWR_GPIO0__PWR_GPIO_0 0 +#define PWR_GPIO0__UART2_TX 1 +#define PWR_GPIO0__PWR_UART0_RX 2 +#define PWR_GPIO0__PWM_8 4 +#define PWR_GPIO1__PWR_GPIO_1 0 +#define PWR_GPIO1__UART2_RX 1 +#define PWR_GPIO1__EPHY_LNK_LED 3 +#define PWR_GPIO1__PWM_9 4 +#define PWR_GPIO1__PWR_IIC_SCL 5 +#define PWR_GPIO1__IIC2_SCL 6 +#define PWR_GPIO1__PWR_MCU_JTAG_TMS 7 +#define PWR_GPIO2__PWR_GPIO_2 0 +#define PWR_GPIO2__PWR_SECTICK 2 +#define PWR_GPIO2__EPHY_SPD_LED 3 +#define PWR_GPIO2__PWM_10 4 +#define PWR_GPIO2__PWR_IIC_SDA 5 +#define PWR_GPIO2__IIC2_SDA 6 +#define PWR_GPIO2__PWR_MCU_JTAG_TCK 7 +#define CLK32K__CLK32K 0 +#define CLK32K__AUX0 1 +#define CLK32K__PWR_MCU_JTAG_TDI 2 +#define CLK32K__PWR_GPIO_10 3 +#define CLK32K__PWM_2 4 +#define CLK32K__KEY_COL0 5 +#define CLK32K__CAM_MCLK0 6 +#define CLK32K__DBG_0 7 +#define CLK25M__CLK25M 0 +#define CLK25M__AUX1 1 +#define CLK25M__PWR_MCU_JTAG_TDO 2 +#define CLK25M__PWR_GPIO_11 3 +#define CLK25M__PWM_3 4 +#define CLK25M__KEY_COL1 5 +#define CLK25M__CAM_MCLK1 6 +#define CLK25M__DBG_1 7 +#define IIC2_SCL__IIC2_SCL 0 +#define IIC2_SCL__PWM_14 1 +#define IIC2_SCL__PWR_GPIO_12 3 +#define IIC2_SCL__UART2_RX 4 +#define IIC2_SCL__KEY_COL2 7 +#define IIC2_SDA__IIC2_SDA 0 +#define IIC2_SDA__PWM_15 1 +#define IIC2_SDA__PWR_GPIO_13 3 +#define IIC2_SDA__UART2_TX 4 +#define IIC2_SDA__IIS1_MCLK 5 +#define IIC2_SDA__IIS2_MCLK 6 +#define IIC2_SDA__KEY_COL3 7 +#define UART2_TX__UART2_TX 0 +#define UART2_TX__PWM_11 1 +#define UART2_TX__PWR_UART1_TX 2 +#define UART2_TX__PWR_GPIO_14 3 +#define UART2_TX__KEY_ROW3 4 +#define UART2_TX__UART4_TX 5 +#define UART2_TX__IIS2_BCLK 6 +#define UART2_TX__WG2_D0 7 +#define UART2_RTS__UART2_RTS 0 +#define UART2_RTS__PWM_8 1 +#define UART2_RTS__PWR_GPIO_15 3 +#define UART2_RTS__KEY_ROW0 4 +#define UART2_RTS__UART4_RTS 5 +#define UART2_RTS__IIS2_DO 6 +#define UART2_RTS__WG1_D0 7 +#define UART2_RX__UART2_RX 0 +#define UART2_RX__PWM_10 1 +#define UART2_RX__PWR_UART1_RX 2 +#define UART2_RX__PWR_GPIO_16 3 +#define UART2_RX__KEY_COL3 4 +#define UART2_RX__UART4_RX 5 +#define UART2_RX__IIS2_DI 6 +#define UART2_RX__WG2_D1 7 +#define UART2_CTS__UART2_CTS 0 +#define UART2_CTS__PWM_9 1 +#define UART2_CTS__PWR_GPIO_17 3 +#define UART2_CTS__KEY_ROW1 4 +#define UART2_CTS__UART4_CTS 5 +#define UART2_CTS__IIS2_LRCK 6 +#define UART2_CTS__WG1_D1 7 +#define SD1_D3__PWR_SD1_D3_VO32 0 +#define SD1_D3__SPI2_CS_X 1 +#define SD1_D3__IIC1_SCL 2 +#define SD1_D3__PWR_GPIO_18 3 +#define SD1_D3__CAM_MCLK0 4 +#define SD1_D3__UART3_CTS 5 +#define SD1_D3__PWR_SPINOR1_CS_X 6 +#define SD1_D3__PWM_4 7 +#define SD1_D2__PWR_SD1_D2_VO33 0 +#define SD1_D2__IIC1_SCL 1 +#define SD1_D2__UART2_TX 2 +#define SD1_D2__PWR_GPIO_19 3 +#define SD1_D2__CAM_MCLK0 4 +#define SD1_D2__UART3_TX 5 +#define SD1_D2__PWR_SPINOR1_HOLD_X 6 +#define SD1_D2__PWM_5 7 +#define SD1_D1__PWR_SD1_D1_VO34 0 +#define SD1_D1__IIC1_SDA 1 +#define SD1_D1__UART2_RX 2 +#define SD1_D1__PWR_GPIO_20 3 +#define SD1_D1__CAM_MCLK1 4 +#define SD1_D1__UART3_RX 5 +#define SD1_D1__PWR_SPINOR1_WP_X 6 +#define SD1_D1__PWM_6 7 +#define SD1_D0__PWR_SD1_D0_VO35 0 +#define SD1_D0__SPI2_SDI 1 +#define SD1_D0__IIC1_SDA 2 +#define SD1_D0__PWR_GPIO_21 3 +#define SD1_D0__CAM_MCLK1 4 +#define SD1_D0__UART3_RTS 5 +#define SD1_D0__PWR_SPINOR1_MISO 6 +#define SD1_D0__PWM_7 7 +#define SD1_CMD__PWR_SD1_CMD_VO36 0 +#define SD1_CMD__SPI2_SDO 1 +#define SD1_CMD__IIC3_SCL 2 +#define SD1_CMD__PWR_GPIO_22 3 +#define SD1_CMD__CAM_VS0 4 +#define SD1_CMD__EPHY_LNK_LED 5 +#define SD1_CMD__PWR_SPINOR1_MOSI 6 +#define SD1_CMD__PWM_8 7 +#define SD1_CLK__PWR_SD1_CLK_VO37 0 +#define SD1_CLK__SPI2_SCK 1 +#define SD1_CLK__IIC3_SDA 2 +#define SD1_CLK__PWR_GPIO_23 3 +#define SD1_CLK__CAM_HS0 4 +#define SD1_CLK__EPHY_SPD_LED 5 +#define SD1_CLK__PWR_SPINOR1_SCK 6 +#define SD1_CLK__PWM_9 7 +#define RSTN__RSTN 0 +#define PWM0_BUCK__PWM_0 0 +#define PWM0_BUCK__XGPIOB_0 3 +#define ADC3__CAM_MCLK0 1 +#define ADC3__IIC4_SCL 2 +#define ADC3__XGPIOB_1 3 +#define ADC3__PWM_12 4 +#define ADC3__EPHY_LNK_LED 5 +#define ADC3__WG2_D0 6 +#define ADC3__UART3_TX 7 +#define ADC2__CAM_MCLK1 1 +#define ADC2__IIC4_SDA 2 +#define ADC2__XGPIOB_2 3 +#define ADC2__PWM_13 4 +#define ADC2__EPHY_SPD_LED 5 +#define ADC2__WG2_D1 6 +#define ADC2__UART3_RX 7 +#define ADC1__XGPIOB_3 3 +#define ADC1__KEY_COL2 4 +#define USB_ID__USB_ID 0 +#define USB_ID__XGPIOB_4 3 +#define USB_VBUS_EN__USB_VBUS_EN 0 +#define USB_VBUS_EN__XGPIOB_5 3 +#define PKG_TYPE0__PKG_TYPE0 0 +#define USB_VBUS_DET__USB_VBUS_DET 0 +#define USB_VBUS_DET__XGPIOB_6 3 +#define USB_VBUS_DET__CAM_MCLK0 4 +#define USB_VBUS_DET__CAM_MCLK1 5 +#define PKG_TYPE1__PKG_TYPE1 0 +#define PKG_TYPE2__PKG_TYPE2 0 +#define MUX_SPI1_MISO__UART3_RTS 1 +#define MUX_SPI1_MISO__IIC1_SDA 2 +#define MUX_SPI1_MISO__XGPIOB_8 3 +#define MUX_SPI1_MISO__PWM_9 4 +#define MUX_SPI1_MISO__KEY_COL1 5 +#define MUX_SPI1_MISO__SPI1_SDI 6 +#define MUX_SPI1_MISO__DBG_14 7 +#define MUX_SPI1_MOSI__UART3_RX 1 +#define MUX_SPI1_MOSI__IIC1_SCL 2 +#define MUX_SPI1_MOSI__XGPIOB_7 3 +#define MUX_SPI1_MOSI__PWM_8 4 +#define MUX_SPI1_MOSI__KEY_COL0 5 +#define MUX_SPI1_MOSI__SPI1_SDO 6 +#define MUX_SPI1_MOSI__DBG_13 7 +#define MUX_SPI1_CS__UART3_CTS 1 +#define MUX_SPI1_CS__CAM_MCLK0 2 +#define MUX_SPI1_CS__XGPIOB_10 3 +#define MUX_SPI1_CS__PWM_11 4 +#define MUX_SPI1_CS__KEY_ROW3 5 +#define MUX_SPI1_CS__SPI1_CS_X 6 +#define MUX_SPI1_CS__DBG_16 7 +#define MUX_SPI1_SCK__UART3_TX 1 +#define MUX_SPI1_SCK__CAM_MCLK1 2 +#define MUX_SPI1_SCK__XGPIOB_9 3 +#define MUX_SPI1_SCK__PWM_10 4 +#define MUX_SPI1_SCK__KEY_ROW2 5 +#define MUX_SPI1_SCK__SPI1_SCK 6 +#define MUX_SPI1_SCK__DBG_15 7 +#define PAD_ETH_TXM__UART3_RTS 1 +#define PAD_ETH_TXM__IIC1_SDA 2 +#define PAD_ETH_TXM__XGPIOB_24 3 +#define PAD_ETH_TXM__PWM_12 4 +#define PAD_ETH_TXM__CAM_MCLK1 5 +#define PAD_ETH_TXM__SPI1_SDI 6 +#define PAD_ETH_TXM__IIS2_BCLK 7 +#define PAD_ETH_TXP__UART3_RX 1 +#define PAD_ETH_TXP__IIC1_SCL 2 +#define PAD_ETH_TXP__XGPIOB_25 3 +#define PAD_ETH_TXP__PWM_13 4 +#define PAD_ETH_TXP__CAM_MCLK0 5 +#define PAD_ETH_TXP__SPI1_SDO 6 +#define PAD_ETH_TXP__IIS2_LRCK 7 +#define PAD_ETH_RXM__UART3_CTS 1 +#define PAD_ETH_RXM__CAM_MCLK0 2 +#define PAD_ETH_RXM__XGPIOB_26 3 +#define PAD_ETH_RXM__PWM_14 4 +#define PAD_ETH_RXM__CAM_VS0 5 +#define PAD_ETH_RXM__SPI1_CS_X 6 +#define PAD_ETH_RXM__IIS2_DI 7 +#define PAD_ETH_RXP__UART3_TX 1 +#define PAD_ETH_RXP__CAM_MCLK1 2 +#define PAD_ETH_RXP__XGPIOB_27 3 +#define PAD_ETH_RXP__PWM_15 4 +#define PAD_ETH_RXP__CAM_HS0 5 +#define PAD_ETH_RXP__SPI1_SCK 6 +#define PAD_ETH_RXP__IIS2_DO 7 +#define VIVO_D10__PWM_1 0 +#define VIVO_D10__VI1_D_10 1 +#define VIVO_D10__VO_D_23 2 +#define VIVO_D10__XGPIOB_11 3 +#define VIVO_D10__RMII0_IRQ 4 +#define VIVO_D10__CAM_MCLK0 5 +#define VIVO_D10__IIC1_SDA 6 +#define VIVO_D10__UART2_TX 7 +#define VIVO_D9__PWM_2 0 +#define VIVO_D9__VI1_D_9 1 +#define VIVO_D9__VO_D_22 2 +#define VIVO_D9__XGPIOB_12 3 +#define VIVO_D9__CAM_MCLK1 5 +#define VIVO_D9__IIC1_SCL 6 +#define VIVO_D9__UART2_RX 7 +#define VIVO_D8__PWM_3 0 +#define VIVO_D8__VI1_D_8 1 +#define VIVO_D8__VO_D_21 2 +#define VIVO_D8__XGPIOB_13 3 +#define VIVO_D8__RMII0_MDIO 4 +#define VIVO_D8__SPI3_SDO 5 +#define VIVO_D8__IIC2_SCL 6 +#define VIVO_D8__CAM_VS0 7 +#define VIVO_D7__VI2_D_7 0 +#define VIVO_D7__VI1_D_7 1 +#define VIVO_D7__VO_D_20 2 +#define VIVO_D7__XGPIOB_14 3 +#define VIVO_D7__RMII0_RXD1 4 +#define VIVO_D7__SPI3_SDI 5 +#define VIVO_D7__IIC2_SDA 6 +#define VIVO_D7__CAM_HS0 7 +#define VIVO_D6__VI2_D_6 0 +#define VIVO_D6__VI1_D_6 1 +#define VIVO_D6__VO_D_19 2 +#define VIVO_D6__XGPIOB_15 3 +#define VIVO_D6__RMII0_REFCLKI 4 +#define VIVO_D6__SPI3_SCK 5 +#define VIVO_D6__UART2_TX 6 +#define VIVO_D6__CAM_VS0 7 +#define VIVO_D5__VI2_D_5 0 +#define VIVO_D5__VI1_D_5 1 +#define VIVO_D5__VO_D_18 2 +#define VIVO_D5__XGPIOB_16 3 +#define VIVO_D5__RMII0_RXD0 4 +#define VIVO_D5__SPI3_CS_X 5 +#define VIVO_D5__UART2_RX 6 +#define VIVO_D5__CAM_HS0 7 +#define VIVO_D4__VI2_D_4 0 +#define VIVO_D4__VI1_D_4 1 +#define VIVO_D4__VO_D_17 2 +#define VIVO_D4__XGPIOB_17 3 +#define VIVO_D4__RMII0_MDC 4 +#define VIVO_D4__IIC1_SDA 5 +#define VIVO_D4__UART2_CTS 6 +#define VIVO_D4__CAM_VS0 7 +#define VIVO_D3__VI2_D_3 0 +#define VIVO_D3__VI1_D_3 1 +#define VIVO_D3__VO_D_16 2 +#define VIVO_D3__XGPIOB_18 3 +#define VIVO_D3__RMII0_TXD0 4 +#define VIVO_D3__IIC1_SCL 5 +#define VIVO_D3__UART2_RTS 6 +#define VIVO_D3__CAM_HS0 7 +#define VIVO_D2__VI2_D_2 0 +#define VIVO_D2__VI1_D_2 1 +#define VIVO_D2__VO_D_15 2 +#define VIVO_D2__XGPIOB_19 3 +#define VIVO_D2__RMII0_TXD1 4 +#define VIVO_D2__CAM_MCLK1 5 +#define VIVO_D2__PWM_2 6 +#define VIVO_D2__UART2_TX 7 +#define VIVO_D1__VI2_D_1 0 +#define VIVO_D1__VI1_D_1 1 +#define VIVO_D1__VO_D_14 2 +#define VIVO_D1__XGPIOB_20 3 +#define VIVO_D1__RMII0_RXDV 4 +#define VIVO_D1__IIC3_SDA 5 +#define VIVO_D1__PWM_3 6 +#define VIVO_D1__IIC4_SCL 7 +#define VIVO_D0__VI2_D_0 0 +#define VIVO_D0__VI1_D_0 1 +#define VIVO_D0__VO_D_13 2 +#define VIVO_D0__XGPIOB_21 3 +#define VIVO_D0__RMII0_TXCLK 4 +#define VIVO_D0__IIC3_SCL 5 +#define VIVO_D0__WG1_D0 6 +#define VIVO_D0__IIC4_SDA 7 +#define VIVO_CLK__VI2_CLK 0 +#define VIVO_CLK__VI1_CLK 1 +#define VIVO_CLK__VO_CLK1 2 +#define VIVO_CLK__XGPIOB_22 3 +#define VIVO_CLK__RMII0_TXEN 4 +#define VIVO_CLK__CAM_MCLK0 5 +#define VIVO_CLK__WG1_D1 6 +#define VIVO_CLK__UART2_RX 7 +#define PAD_MIPIRX5N__VI1_D_11 1 +#define PAD_MIPIRX5N__VO_D_12 2 +#define PAD_MIPIRX5N__XGPIOC_0 3 +#define PAD_MIPIRX5N__CAM_MCLK0 5 +#define PAD_MIPIRX5N__WG0_D0 6 +#define PAD_MIPIRX5N__DBG_0 7 +#define PAD_MIPIRX5P__VI1_D_12 1 +#define PAD_MIPIRX5P__VO_D_11 2 +#define PAD_MIPIRX5P__XGPIOC_1 3 +#define PAD_MIPIRX5P__IIS1_MCLK 4 +#define PAD_MIPIRX5P__CAM_MCLK1 5 +#define PAD_MIPIRX5P__WG0_D1 6 +#define PAD_MIPIRX5P__DBG_1 7 +#define PAD_MIPIRX4N__VI0_CLK 1 +#define PAD_MIPIRX4N__VI1_D_13 2 +#define PAD_MIPIRX4N__XGPIOC_2 3 +#define PAD_MIPIRX4N__IIC1_SDA 4 +#define PAD_MIPIRX4N__CAM_MCLK0 5 +#define PAD_MIPIRX4N__KEY_ROW0 6 +#define PAD_MIPIRX4N__MUX_SPI1_SCK 7 +#define PAD_MIPIRX4P__VI0_D_0 1 +#define PAD_MIPIRX4P__VI1_D_14 2 +#define PAD_MIPIRX4P__XGPIOC_3 3 +#define PAD_MIPIRX4P__IIC1_SCL 4 +#define PAD_MIPIRX4P__CAM_MCLK1 5 +#define PAD_MIPIRX4P__KEY_ROW1 6 +#define PAD_MIPIRX4P__MUX_SPI1_CS 7 +#define PAD_MIPIRX3N__VI0_D_1 1 +#define PAD_MIPIRX3N__VI1_D_15 2 +#define PAD_MIPIRX3N__XGPIOC_4 3 +#define PAD_MIPIRX3N__CAM_MCLK0 4 +#define PAD_MIPIRX3N__MUX_SPI1_MISO 7 +#define PAD_MIPIRX3P__VI0_D_2 1 +#define PAD_MIPIRX3P__VI1_D_16 2 +#define PAD_MIPIRX3P__XGPIOC_5 3 +#define PAD_MIPIRX3P__MUX_SPI1_MOSI 7 +#define PAD_MIPIRX2N__VI0_D_3 1 +#define PAD_MIPIRX2N__VO_D_10 2 +#define PAD_MIPIRX2N__XGPIOC_6 3 +#define PAD_MIPIRX2N__VI1_D_17 4 +#define PAD_MIPIRX2N__IIC4_SCL 5 +#define PAD_MIPIRX2N__DBG_6 7 +#define PAD_MIPIRX2P__VI0_D_4 1 +#define PAD_MIPIRX2P__VO_D_9 2 +#define PAD_MIPIRX2P__XGPIOC_7 3 +#define PAD_MIPIRX2P__VI1_D_18 4 +#define PAD_MIPIRX2P__IIC4_SDA 5 +#define PAD_MIPIRX2P__DBG_7 7 +#define PAD_MIPIRX1N__VI0_D_5 1 +#define PAD_MIPIRX1N__VO_D_8 2 +#define PAD_MIPIRX1N__XGPIOC_8 3 +#define PAD_MIPIRX1N__KEY_ROW3 6 +#define PAD_MIPIRX1N__DBG_8 7 +#define PAD_MIPIRX1P__VI0_D_6 1 +#define PAD_MIPIRX1P__VO_D_7 2 +#define PAD_MIPIRX1P__XGPIOC_9 3 +#define PAD_MIPIRX1P__IIC1_SDA 4 +#define PAD_MIPIRX1P__KEY_ROW2 6 +#define PAD_MIPIRX1P__DBG_9 7 +#define PAD_MIPIRX0N__VI0_D_7 1 +#define PAD_MIPIRX0N__VO_D_6 2 +#define PAD_MIPIRX0N__XGPIOC_10 3 +#define PAD_MIPIRX0N__IIC1_SCL 4 +#define PAD_MIPIRX0N__CAM_MCLK1 5 +#define PAD_MIPIRX0N__DBG_10 7 +#define PAD_MIPIRX0P__VI0_D_8 1 +#define PAD_MIPIRX0P__VO_D_5 2 +#define PAD_MIPIRX0P__XGPIOC_11 3 +#define PAD_MIPIRX0P__CAM_MCLK0 4 +#define PAD_MIPIRX0P__DBG_11 7 +#define PAD_MIPI_TXM4__SD1_CLK 1 +#define PAD_MIPI_TXM4__VO_D_24 2 +#define PAD_MIPI_TXM4__XGPIOC_18 3 +#define PAD_MIPI_TXM4__CAM_MCLK1 4 +#define PAD_MIPI_TXM4__PWM_12 5 +#define PAD_MIPI_TXM4__IIC1_SDA 6 +#define PAD_MIPI_TXM4__DBG_18 7 +#define PAD_MIPI_TXP4__SD1_CMD 1 +#define PAD_MIPI_TXP4__VO_D_25 2 +#define PAD_MIPI_TXP4__XGPIOC_19 3 +#define PAD_MIPI_TXP4__CAM_MCLK0 4 +#define PAD_MIPI_TXP4__PWM_13 5 +#define PAD_MIPI_TXP4__IIC1_SCL 6 +#define PAD_MIPI_TXP4__DBG_19 7 +#define PAD_MIPI_TXM3__SD1_D0 1 +#define PAD_MIPI_TXM3__VO_D_26 2 +#define PAD_MIPI_TXM3__XGPIOC_20 3 +#define PAD_MIPI_TXM3__IIC2_SDA 4 +#define PAD_MIPI_TXM3__PWM_14 5 +#define PAD_MIPI_TXM3__IIC1_SDA 6 +#define PAD_MIPI_TXM3__CAM_VS0 7 +#define PAD_MIPI_TXP3__SD1_D1 1 +#define PAD_MIPI_TXP3__VO_D_27 2 +#define PAD_MIPI_TXP3__XGPIOC_21 3 +#define PAD_MIPI_TXP3__IIC2_SCL 4 +#define PAD_MIPI_TXP3__PWM_15 5 +#define PAD_MIPI_TXP3__IIC1_SCL 6 +#define PAD_MIPI_TXP3__CAM_HS0 7 +#define PAD_MIPI_TXM2__VI0_D_13 1 +#define PAD_MIPI_TXM2__VO_D_0 2 +#define PAD_MIPI_TXM2__XGPIOC_16 3 +#define PAD_MIPI_TXM2__IIC1_SDA 4 +#define PAD_MIPI_TXM2__PWM_8 5 +#define PAD_MIPI_TXM2__SPI0_SCK 6 +#define PAD_MIPI_TXM2__SD1_D2 7 +#define PAD_MIPI_TXP2__VI0_D_14 1 +#define PAD_MIPI_TXP2__VO_CLK0 2 +#define PAD_MIPI_TXP2__XGPIOC_17 3 +#define PAD_MIPI_TXP2__IIC1_SCL 4 +#define PAD_MIPI_TXP2__PWM_9 5 +#define PAD_MIPI_TXP2__SPI0_CS_X 6 +#define PAD_MIPI_TXP2__SD1_D3 7 +#define PAD_MIPI_TXM1__VI0_D_11 1 +#define PAD_MIPI_TXM1__VO_D_2 2 +#define PAD_MIPI_TXM1__XGPIOC_14 3 +#define PAD_MIPI_TXM1__IIC2_SDA 4 +#define PAD_MIPI_TXM1__PWM_10 5 +#define PAD_MIPI_TXM1__SPI0_SDO 6 +#define PAD_MIPI_TXM1__DBG_14 7 +#define PAD_MIPI_TXP1__VI0_D_12 1 +#define PAD_MIPI_TXP1__VO_D_1 2 +#define PAD_MIPI_TXP1__XGPIOC_15 3 +#define PAD_MIPI_TXP1__IIC2_SCL 4 +#define PAD_MIPI_TXP1__PWM_11 5 +#define PAD_MIPI_TXP1__SPI0_SDI 6 +#define PAD_MIPI_TXP1__DBG_15 7 +#define PAD_MIPI_TXM0__VI0_D_9 1 +#define PAD_MIPI_TXM0__VO_D_4 2 +#define PAD_MIPI_TXM0__XGPIOC_12 3 +#define PAD_MIPI_TXM0__CAM_MCLK1 4 +#define PAD_MIPI_TXM0__PWM_14 5 +#define PAD_MIPI_TXM0__CAM_VS0 6 +#define PAD_MIPI_TXM0__DBG_12 7 +#define PAD_MIPI_TXP0__VI0_D_10 1 +#define PAD_MIPI_TXP0__VO_D_3 2 +#define PAD_MIPI_TXP0__XGPIOC_13 3 +#define PAD_MIPI_TXP0__CAM_MCLK0 4 +#define PAD_MIPI_TXP0__PWM_15 5 +#define PAD_MIPI_TXP0__CAM_HS0 6 +#define PAD_MIPI_TXP0__DBG_13 7 +#define PAD_AUD_AINL_MIC__XGPIOC_23 3 +#define PAD_AUD_AINL_MIC__IIS1_BCLK 4 +#define PAD_AUD_AINL_MIC__IIS2_BCLK 5 +#define PAD_AUD_AINR_MIC__XGPIOC_22 3 +#define PAD_AUD_AINR_MIC__IIS1_DO 4 +#define PAD_AUD_AINR_MIC__IIS2_DI 5 +#define PAD_AUD_AINR_MIC__IIS1_DI 6 +#define PAD_AUD_AOUTL__XGPIOC_25 3 +#define PAD_AUD_AOUTL__IIS1_LRCK 4 +#define PAD_AUD_AOUTL__IIS2_LRCK 5 +#define PAD_AUD_AOUTR__XGPIOC_24 3 +#define PAD_AUD_AOUTR__IIS1_DI 4 +#define PAD_AUD_AOUTR__IIS2_DO 5 +#define PAD_AUD_AOUTR__IIS1_DO 6 +#define GPIO_RTX__XGPIOB_23 3 +#define GPIO_RTX__PWM_1 4 +#define GPIO_RTX__CAM_MCLK0 5 +#define GPIO_ZQ__PWR_GPIO_24 3 +#define GPIO_ZQ__PWM_2 4 diff --git a/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinmux.h b/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinmux.h new file mode 100755 index 0000000000..9b3e81ef42 --- /dev/null +++ b/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinmux.h @@ -0,0 +1,46 @@ +#ifndef _CV181X_PINMUX_H_ +#define _CV181X_PINMUX_H_ + +#define PINMUX_UART0 0 +#define PINMUX_UART1 1 +#define PINMUX_UART2 2 +#define PINMUX_UART3 3 +#define PINMUX_UART3_2 4 +#define PINMUX_I2C0 5 +#define PINMUX_I2C1 6 +#define PINMUX_I2C2 7 +#define PINMUX_I2C3 8 +#define PINMUX_I2C4 9 +#define PINMUX_I2C4_2 10 +#define PINMUX_SPI0 11 +#define PINMUX_SPI1 12 +#define PINMUX_SPI2 13 +#define PINMUX_SPI2_2 14 +#define PINMUX_SPI3 15 +#define PINMUX_SPI3_2 16 +#define PINMUX_I2S0 17 +#define PINMUX_I2S1 18 +#define PINMUX_I2S2 19 +#define PINMUX_I2S3 20 +#define PINMUX_USBID 21 +#define PINMUX_SDIO0 22 +#define PINMUX_SDIO1 23 +#define PINMUX_ND 24 +#define PINMUX_EMMC 25 +#define PINMUX_SPI_NOR 26 +#define PINMUX_SPI_NAND 27 +#define PINMUX_CAM0 28 +#define PINMUX_CAM1 29 +#define PINMUX_PCM0 30 +#define PINMUX_PCM1 31 +#define PINMUX_CSI0 32 +#define PINMUX_CSI1 33 +#define PINMUX_CSI2 34 +#define PINMUX_DSI 35 +#define PINMUX_VI0 36 +#define PINMUX_VO 37 +#define PINMUX_PWM1 38 +#define PINMUX_UART4 39 +#define PINMUX_SPI_NOR1 40 + +#endif // end of _CV181X_PINMUX_H_ diff --git a/bsp/cvitek/drivers/libraries/cv181x/cv181x_reg_fmux_gpio.h b/bsp/cvitek/drivers/libraries/cv181x/cv181x_reg_fmux_gpio.h new file mode 100755 index 0000000000..5dbf34be30 --- /dev/null +++ b/bsp/cvitek/drivers/libraries/cv181x/cv181x_reg_fmux_gpio.h @@ -0,0 +1,475 @@ +// $Module: fmux_gpio $ +// $RegisterBank Version: V 1.0.00 $ +// $Author: ghost $ +// $Date: Fri, 30 Jul 2021 08:58:54 PM $ +// + +//GEN REG ADDR/OFFSET/MASK +#define FMUX_GPIO_REG_IOCTRL_CAM_MCLK0 0x0 +#define FMUX_GPIO_REG_IOCTRL_CAM_PD0 0x4 +#define FMUX_GPIO_REG_IOCTRL_CAM_RST0 0x8 +#define FMUX_GPIO_REG_IOCTRL_CAM_MCLK1 0xc +#define FMUX_GPIO_REG_IOCTRL_CAM_PD1 0x10 +#define FMUX_GPIO_REG_IOCTRL_IIC3_SCL 0x14 +#define FMUX_GPIO_REG_IOCTRL_IIC3_SDA 0x18 +#define FMUX_GPIO_REG_IOCTRL_SD0_CLK 0x1c +#define FMUX_GPIO_REG_IOCTRL_SD0_CMD 0x20 +#define FMUX_GPIO_REG_IOCTRL_SD0_D0 0x24 +#define FMUX_GPIO_REG_IOCTRL_SD0_D1 0x28 +#define FMUX_GPIO_REG_IOCTRL_SD0_D2 0x2c +#define FMUX_GPIO_REG_IOCTRL_SD0_D3 0x30 +#define FMUX_GPIO_REG_IOCTRL_SD0_CD 0x34 +#define FMUX_GPIO_REG_IOCTRL_SD0_PWR_EN 0x38 +#define FMUX_GPIO_REG_IOCTRL_SPK_EN 0x3c +#define FMUX_GPIO_REG_IOCTRL_UART0_TX 0x40 +#define FMUX_GPIO_REG_IOCTRL_UART0_RX 0x44 +#define FMUX_GPIO_REG_IOCTRL_EMMC_RSTN 0x48 +#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT2 0x4c +#define FMUX_GPIO_REG_IOCTRL_EMMC_CLK 0x50 +#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT0 0x54 +#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT3 0x58 +#define FMUX_GPIO_REG_IOCTRL_EMMC_CMD 0x5c +#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT1 0x60 +#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TMS 0x64 +#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TCK 0x68 +#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TRST 0x6c +#define FMUX_GPIO_REG_IOCTRL_IIC0_SCL 0x70 +#define FMUX_GPIO_REG_IOCTRL_IIC0_SDA 0x74 +#define FMUX_GPIO_REG_IOCTRL_AUX0 0x78 +#define FMUX_GPIO_REG_IOCTRL_PWR_VBAT_DET 0x7c +#define FMUX_GPIO_REG_IOCTRL_PWR_RSTN 0x80 +#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ1 0x84 +#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ2 0x88 +#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ3 0x8c +#define FMUX_GPIO_REG_IOCTRL_PWR_WAKEUP0 0x90 +#define FMUX_GPIO_REG_IOCTRL_PWR_WAKEUP1 0x94 +#define FMUX_GPIO_REG_IOCTRL_PWR_BUTTON1 0x98 +#define FMUX_GPIO_REG_IOCTRL_PWR_ON 0x9c +#define FMUX_GPIO_REG_IOCTRL_XTAL_XIN 0xa0 +#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO0 0xa4 +#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO1 0xa8 +#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO2 0xac +#define FMUX_GPIO_REG_IOCTRL_CLK32K 0xb0 +#define FMUX_GPIO_REG_IOCTRL_CLK25M 0xb4 +#define FMUX_GPIO_REG_IOCTRL_IIC2_SCL 0xb8 +#define FMUX_GPIO_REG_IOCTRL_IIC2_SDA 0xbc +#define FMUX_GPIO_REG_IOCTRL_UART2_TX 0xc0 +#define FMUX_GPIO_REG_IOCTRL_UART2_RTS 0xc4 +#define FMUX_GPIO_REG_IOCTRL_UART2_RX 0xc8 +#define FMUX_GPIO_REG_IOCTRL_UART2_CTS 0xcc +#define FMUX_GPIO_REG_IOCTRL_SD1_D3 0xd0 +#define FMUX_GPIO_REG_IOCTRL_SD1_D2 0xd4 +#define FMUX_GPIO_REG_IOCTRL_SD1_D1 0xd8 +#define FMUX_GPIO_REG_IOCTRL_SD1_D0 0xdc +#define FMUX_GPIO_REG_IOCTRL_SD1_CMD 0xe0 +#define FMUX_GPIO_REG_IOCTRL_SD1_CLK 0xe4 +#define FMUX_GPIO_REG_IOCTRL_RSTN 0xe8 +#define FMUX_GPIO_REG_IOCTRL_PWM0_BUCK 0xec +#define FMUX_GPIO_REG_IOCTRL_ADC3 0xf0 +#define FMUX_GPIO_REG_IOCTRL_ADC2 0xf4 +#define FMUX_GPIO_REG_IOCTRL_ADC1 0xf8 +#define FMUX_GPIO_REG_IOCTRL_USB_ID 0xfc +#define FMUX_GPIO_REG_IOCTRL_USB_VBUS_EN 0x100 +#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE0 0x104 +#define FMUX_GPIO_REG_IOCTRL_USB_VBUS_DET 0x108 +#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE1 0x10c +#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE2 0x110 +#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MISO 0x114 +#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MOSI 0x118 +#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_CS 0x11c +#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_SCK 0x120 +#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXM 0x124 +#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXP 0x128 +#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXM 0x12c +#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXP 0x130 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D10 0x134 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D9 0x138 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D8 0x13c +#define FMUX_GPIO_REG_IOCTRL_VIVO_D7 0x140 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D6 0x144 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D5 0x148 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D4 0x14c +#define FMUX_GPIO_REG_IOCTRL_VIVO_D3 0x150 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D2 0x154 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D1 0x158 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D0 0x15c +#define FMUX_GPIO_REG_IOCTRL_VIVO_CLK 0x160 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX5N 0x164 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX5P 0x168 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4N 0x16c +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4P 0x170 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3N 0x174 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3P 0x178 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2N 0x17c +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2P 0x180 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1N 0x184 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1P 0x188 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0N 0x18c +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0P 0x190 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM4 0x194 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP4 0x198 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM3 0x19c +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP3 0x1a0 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM2 0x1a4 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP2 0x1a8 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM1 0x1ac +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP1 0x1b0 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM0 0x1b4 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP0 0x1b8 +#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINL_MIC 0x1bc +#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINR_MIC 0x1c0 +#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTL 0x1c4 +#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTR 0x1c8 +#define FMUX_GPIO_REG_IOCTRL_GPIO_RTX 0x1cc +#define FMUX_GPIO_REG_IOCTRL_GPIO_ZQ 0x1d0 +#define FMUX_GPIO_FUNCSEL_CAM_MCLK0 0x0 +#define FMUX_GPIO_FUNCSEL_CAM_MCLK0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_CAM_MCLK0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_CAM_PD0 0x4 +#define FMUX_GPIO_FUNCSEL_CAM_PD0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_CAM_PD0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_CAM_RST0 0x8 +#define FMUX_GPIO_FUNCSEL_CAM_RST0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_CAM_RST0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_CAM_MCLK1 0xc +#define FMUX_GPIO_FUNCSEL_CAM_MCLK1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_CAM_MCLK1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_CAM_PD1 0x10 +#define FMUX_GPIO_FUNCSEL_CAM_PD1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_CAM_PD1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_IIC3_SCL 0x14 +#define FMUX_GPIO_FUNCSEL_IIC3_SCL_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_IIC3_SCL_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_IIC3_SDA 0x18 +#define FMUX_GPIO_FUNCSEL_IIC3_SDA_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_IIC3_SDA_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_CLK 0x1c +#define FMUX_GPIO_FUNCSEL_SD0_CLK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_CLK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_CMD 0x20 +#define FMUX_GPIO_FUNCSEL_SD0_CMD_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_CMD_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_D0 0x24 +#define FMUX_GPIO_FUNCSEL_SD0_D0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_D0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_D1 0x28 +#define FMUX_GPIO_FUNCSEL_SD0_D1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_D1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_D2 0x2c +#define FMUX_GPIO_FUNCSEL_SD0_D2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_D2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_D3 0x30 +#define FMUX_GPIO_FUNCSEL_SD0_D3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_D3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_CD 0x34 +#define FMUX_GPIO_FUNCSEL_SD0_CD_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_CD_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN 0x38 +#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SPK_EN 0x3c +#define FMUX_GPIO_FUNCSEL_SPK_EN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SPK_EN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_UART0_TX 0x40 +#define FMUX_GPIO_FUNCSEL_UART0_TX_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_UART0_TX_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_UART0_RX 0x44 +#define FMUX_GPIO_FUNCSEL_UART0_RX_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_UART0_RX_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_EMMC_RSTN 0x48 +#define FMUX_GPIO_FUNCSEL_EMMC_RSTN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_EMMC_RSTN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT2 0x4c +#define FMUX_GPIO_FUNCSEL_EMMC_DAT2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_EMMC_CLK 0x50 +#define FMUX_GPIO_FUNCSEL_EMMC_CLK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_EMMC_CLK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT0 0x54 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT3 0x58 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_EMMC_CMD 0x5c +#define FMUX_GPIO_FUNCSEL_EMMC_CMD_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_EMMC_CMD_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT1 0x60 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS 0x64 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK 0x68 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST 0x6c +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_IIC0_SCL 0x70 +#define FMUX_GPIO_FUNCSEL_IIC0_SCL_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_IIC0_SCL_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_IIC0_SDA 0x74 +#define FMUX_GPIO_FUNCSEL_IIC0_SDA_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_IIC0_SDA_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_AUX0 0x78 +#define FMUX_GPIO_FUNCSEL_AUX0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_AUX0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET 0x7c +#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_RSTN 0x80 +#define FMUX_GPIO_FUNCSEL_PWR_RSTN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_RSTN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ1 0x84 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ2 0x88 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ3 0x8c +#define FMUX_GPIO_FUNCSEL_PWR_SEQ3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0 0x90 +#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP1 0x94 +#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1 0x98 +#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_ON 0x9c +#define FMUX_GPIO_FUNCSEL_PWR_ON_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_ON_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_XTAL_XIN 0xa0 +#define FMUX_GPIO_FUNCSEL_XTAL_XIN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_XTAL_XIN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO0 0xa4 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO1 0xa8 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO2 0xac +#define FMUX_GPIO_FUNCSEL_PWR_GPIO2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_CLK32K 0xb0 +#define FMUX_GPIO_FUNCSEL_CLK32K_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_CLK32K_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_CLK25M 0xb4 +#define FMUX_GPIO_FUNCSEL_CLK25M_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_CLK25M_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_IIC2_SCL 0xb8 +#define FMUX_GPIO_FUNCSEL_IIC2_SCL_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_IIC2_SCL_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_IIC2_SDA 0xbc +#define FMUX_GPIO_FUNCSEL_IIC2_SDA_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_IIC2_SDA_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_UART2_TX 0xc0 +#define FMUX_GPIO_FUNCSEL_UART2_TX_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_UART2_TX_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_UART2_RTS 0xc4 +#define FMUX_GPIO_FUNCSEL_UART2_RTS_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_UART2_RTS_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_UART2_RX 0xc8 +#define FMUX_GPIO_FUNCSEL_UART2_RX_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_UART2_RX_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_UART2_CTS 0xcc +#define FMUX_GPIO_FUNCSEL_UART2_CTS_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_UART2_CTS_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_D3 0xd0 +#define FMUX_GPIO_FUNCSEL_SD1_D3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_D3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_D2 0xd4 +#define FMUX_GPIO_FUNCSEL_SD1_D2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_D2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_D1 0xd8 +#define FMUX_GPIO_FUNCSEL_SD1_D1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_D1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_D0 0xdc +#define FMUX_GPIO_FUNCSEL_SD1_D0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_D0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_CMD 0xe0 +#define FMUX_GPIO_FUNCSEL_SD1_CMD_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_CMD_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_CLK 0xe4 +#define FMUX_GPIO_FUNCSEL_SD1_CLK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_CLK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_RSTN 0xe8 +#define FMUX_GPIO_FUNCSEL_RSTN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_RSTN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWM0_BUCK 0xec +#define FMUX_GPIO_FUNCSEL_PWM0_BUCK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWM0_BUCK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_ADC3 0xf0 +#define FMUX_GPIO_FUNCSEL_ADC3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_ADC3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_ADC2 0xf4 +#define FMUX_GPIO_FUNCSEL_ADC2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_ADC2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_ADC1 0xf8 +#define FMUX_GPIO_FUNCSEL_ADC1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_ADC1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_USB_ID 0xfc +#define FMUX_GPIO_FUNCSEL_USB_ID_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_USB_ID_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_USB_VBUS_EN 0x100 +#define FMUX_GPIO_FUNCSEL_USB_VBUS_EN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_USB_VBUS_EN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE0 0x104 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET 0x108 +#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE1 0x10c +#define FMUX_GPIO_FUNCSEL_PKG_TYPE1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE2 0x110 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO 0x114 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI 0x118 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS 0x11c +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK 0x120 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM 0x124 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP 0x128 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM 0x12c +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP 0x130 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D10 0x134 +#define FMUX_GPIO_FUNCSEL_VIVO_D10_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D10_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D9 0x138 +#define FMUX_GPIO_FUNCSEL_VIVO_D9_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D9_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D8 0x13c +#define FMUX_GPIO_FUNCSEL_VIVO_D8_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D8_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D7 0x140 +#define FMUX_GPIO_FUNCSEL_VIVO_D7_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D7_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D6 0x144 +#define FMUX_GPIO_FUNCSEL_VIVO_D6_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D6_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D5 0x148 +#define FMUX_GPIO_FUNCSEL_VIVO_D5_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D5_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D4 0x14c +#define FMUX_GPIO_FUNCSEL_VIVO_D4_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D4_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D3 0x150 +#define FMUX_GPIO_FUNCSEL_VIVO_D3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D2 0x154 +#define FMUX_GPIO_FUNCSEL_VIVO_D2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D1 0x158 +#define FMUX_GPIO_FUNCSEL_VIVO_D1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D0 0x15c +#define FMUX_GPIO_FUNCSEL_VIVO_D0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_CLK 0x160 +#define FMUX_GPIO_FUNCSEL_VIVO_CLK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_CLK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N 0x164 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P 0x168 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N 0x16c +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P 0x170 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N 0x174 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P 0x178 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N 0x17c +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P 0x180 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N 0x184 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P 0x188 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N 0x18c +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P 0x190 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4 0x194 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4 0x198 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3 0x19c +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3 0x1a0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2 0x1a4 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2 0x1a8 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1 0x1ac +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1 0x1b0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0 0x1b4 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0 0x1b8 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC 0x1bc +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC 0x1c0 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL 0x1c4 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR 0x1c8 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_GPIO_RTX 0x1cc +#define FMUX_GPIO_FUNCSEL_GPIO_RTX_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_GPIO_RTX_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_GPIO_ZQ 0x1d0 +#define FMUX_GPIO_FUNCSEL_GPIO_ZQ_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_GPIO_ZQ_MASK 0x7 diff --git a/bsp/cvitek/drivers/libraries/cv181x/pinctrl.h b/bsp/cvitek/drivers/libraries/cv181x/pinctrl.h new file mode 100755 index 0000000000..58bd0938d3 --- /dev/null +++ b/bsp/cvitek/drivers/libraries/cv181x/pinctrl.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved. + * + * File Name: pinctrl.h + * Description: + */ + +#ifndef __PINCTRL_CV181X_H__ +#define __PINCTRL_CV181X_H__ + +//#include "../core.h" +#include "cv181x_pinlist_swconfig.h" +#include "cv181x_reg_fmux_gpio.h" + +#define PAD_MIPI_TXM4__MIPI_TXM4 0 +#define PAD_MIPI_TXP4__MIPI_TXP4 0 +#define PAD_MIPI_TXM3__MIPI_TXM3 0 +#define PAD_MIPI_TXP3__MIPI_TXP3 0 +#define PAD_MIPI_TXM2__MIPI_TXM2 0 +#define PAD_MIPI_TXP2__MIPI_TXP2 0 +#define PAD_MIPI_TXM1__MIPI_TXM1 0 +#define PAD_MIPI_TXP1__MIPI_TXP1 0 +#define PAD_MIPI_TXM0__MIPI_TXM0 0 +#define PAD_MIPI_TXP0__MIPI_TXP0 0 + +#define PINMUX_BASE 0x03001000 +#define PINMUX_MASK(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_MASK +#define PINMUX_OFFSET(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET +#define PINMUX_VALUE(PIN_NAME, FUNC_NAME) PIN_NAME##__##FUNC_NAME +#define PINMUX_CONFIG(PIN_NAME, FUNC_NAME) \ + mmio_clrsetbits_32(PINMUX_BASE + FMUX_GPIO_FUNCSEL_##PIN_NAME, \ + PINMUX_MASK(PIN_NAME) << PINMUX_OFFSET(PIN_NAME), \ + PINMUX_VALUE(PIN_NAME, FUNC_NAME)) + +#endif /* __PINCTRL_CV181X_H__ */ diff --git a/bsp/cvitek/drivers/libraries/mmio.h b/bsp/cvitek/drivers/libraries/mmio.h new file mode 100755 index 0000000000..bc36d5a3ca --- /dev/null +++ b/bsp/cvitek/drivers/libraries/mmio.h @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __MMIO_H__ +#define __MMIO_H__ +#include +#include "types.h" + +#define __raw_readb(a) (*(volatile unsigned char *)(a)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_readl(a) (*(volatile unsigned int *)(a)) +#define __raw_readq(a) (*(volatile unsigned long long *)(a)) + +#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) +#define __raw_writeq(v,a) (*(volatile unsigned long long *)(a) = (v)) + +/* + * I/O memory access primitives. Reads are ordered relative to any + * following Normal memory access. Writes are ordered relative to any prior + * Normal memory access. The memory barriers here are necessary as RISC-V + * doesn't define any ordering between the memory space and the I/O space. + */ +#define __io_br() do {} while (0) +#define __io_ar(v) __asm__ __volatile__ ("fence i,r" : : : "memory") +#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory") +//#define __io_aw() mmiowb_set_pending() +#define __io_aw() do {} while (0) + +#define readb(c) ({ u8 __v; __io_br(); __v = __raw_readb(c); __io_ar(__v); __v; }) +#define readw(c) ({ u16 __v; __io_br(); __v = __raw_readw(c); __io_ar(__v); __v; }) +#define readl(c) ({ u32 __v; __io_br(); __v = __raw_readl(c); __io_ar(__v); __v; }) + +#define writeb(v, c) ({ __io_bw(); __raw_writeb((v), (c)); __io_aw(); }) +#define writew(v, c) ({ __io_bw(); __raw_writew((v), (c)); __io_aw(); }) +#define writel(v, c) ({ __io_bw(); __raw_writel((v), (c)); __io_aw(); }) + + +#ifdef CONFIG_64BIT +#define readq(c) ({ u64 __v; __io_br(); __v = __raw_readq(c); __io_ar(__v); __v; }) +#define writeq(v, c) ({ __io_bw(); __raw_writeq((v), (c)); __io_aw(); }) +#endif // CONFIG_64BIT + +/* +#define __raw_readb(a) (*(volatile unsigned char *)(a)) +#define __raw_readw(a) (*(volatile unsigned short *)(a)) +#define __raw_readl(a) (*(volatile unsigned int *)(a)) +#define __raw_readq(a) (*(volatile unsigned long long *)(a)) + +#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) +#define __raw_writeq(v,a) (*(volatile unsigned long long *)(a) = (v)) + +#define readb(a) __raw_readb(a) +#define readw(a) __raw_readw(a) +#define readl(a) __raw_readl(a) +#define readq(a) __raw_readq(a) + +#define writeb(v, a) __raw_writeb(v,a) +#define writew(v, a) __raw_writew(v,a) +#define writel(v, a) __raw_writel(v,a) +#define writeq(v, a) __raw_writeq(v,a) + +#define cpu_write8(a, v) writeb(a, v) +#define cpu_write16(a, v) writew(a, v) +#define cpu_write32(a, v) writel(a, v) +*/ + +#define mmio_wr32 mmio_write_32 +#define mmio_rd32 mmio_read_32 + +static inline void mmio_write_8(uintptr_t addr, uint8_t value) +{ + writeb(value, (void *) addr); +} + +static inline uint8_t mmio_read_8(uintptr_t addr) +{ + return readb((void *) addr); +} + +static inline void mmio_write_16(uintptr_t addr, uint16_t value) +{ + writew(value, (void *) addr); +} + +static inline uint16_t mmio_read_16(uintptr_t addr) +{ + return readw((void *) addr); +} + +static inline void mmio_write_32(uintptr_t addr, uint32_t value) +{ + writel(value, (void *) addr); +} + +static inline uint32_t mmio_read_32(uintptr_t addr) +{ + return readl((void *) addr); +} + +static inline void mmio_write_64(uintptr_t addr, uint64_t value) +{ + writeq(value, (void *) addr); +} + +static inline uint64_t mmio_read_64(uintptr_t addr) +{ + return readq((void *) addr); +} + +static inline void mmio_clrbits_32(uintptr_t addr, uint32_t clear) +{ + writel(readl((void *) addr) & ~clear , (void *) addr); +} + +static inline void mmio_setbits_32(uintptr_t addr, uint32_t set) +{ + writel(readl((void *) addr) | set , (void *) addr); +} + +static inline void mmio_clrsetbits_32(uintptr_t addr, uint32_t clear, + uint32_t set) +{ + writel((readl((void *) addr) & ~clear) | set , (void *) addr); +} + +/* from Linux usage */ +#define ioremap(a, l) (a) + +#define _reg_read(addr) mmio_read_32((addr)) +#define _reg_write(addr, data) mmio_write_32((addr), (data)) +#define _reg_write_mask(addr, mask, data) mmio_clrsetbits_32(addr, mask, data) + +#define ioread8 readb +#define ioread16 readw +#define ioread32 readl +#define ioread64 readq + +#define iowrite8 writeb +#define iowrite16 writew +#define iowrite32 writel +#define iowrite64 writeq + +#endif /* __MMIO_H__ */ diff --git a/bsp/cvitek/drivers/libraries/types.h b/bsp/cvitek/drivers/libraries/types.h new file mode 100755 index 0000000000..b6a8bc006c --- /dev/null +++ b/bsp/cvitek/drivers/libraries/types.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _LINUX_TYPES_H +#define _LINUX_TYPES_H + +#ifndef __ASSEMBLY__ +#ifdef CONFIG_64BIT +typedef unsigned long uintptr_t; +typedef unsigned long size_t; +/* bsd */ +typedef unsigned char u_char; +typedef unsigned short u_short; +typedef unsigned int u_int; +typedef unsigned long u_long; + +/* sysv */ +typedef unsigned char unchar; +typedef unsigned short ushort; +typedef unsigned int uint; +typedef unsigned long ulong; + +typedef signed char s8; +typedef signed short s16; +typedef signed int s32; +typedef signed long s64; + +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned int u32; +typedef unsigned long u64; + +typedef signed char __s8; +typedef signed short __s16; +typedef signed int __s32; +typedef signed long __s64; + +typedef unsigned char __u8; +typedef unsigned short __u16; +typedef unsigned int __u32; +typedef unsigned long __u64; + +#endif /* CONFIG_64BIT */ +#endif /* __ASSEMBLY__ */ +#endif /* _LINUX_TYPES_H */ diff --git a/bsp/cvitek/mkimage b/bsp/cvitek/mkimage new file mode 100755 index 0000000000..6a720c3fb0 Binary files /dev/null and b/bsp/cvitek/mkimage differ diff --git a/bsp/cvitek/mksdimg.sh b/bsp/cvitek/mksdimg.sh new file mode 100755 index 0000000000..788def063a --- /dev/null +++ b/bsp/cvitek/mksdimg.sh @@ -0,0 +1,37 @@ +#/bin/sh +set -e + +PROJECT_PATH=$1 +IMAGE_NAME=$2 + +if [ -z "$PROJECT_PATH" ] || [ -z "$IMAGE_NAME" ]; then + echo "Usage: $0 " + exit 1 +fi + +ROOT_PATH=$(pwd) +echo ${ROOT_PATH} + +function get_board_type() +{ + BOARD_CONFIG=("CONFIG_BOARD_TYPE_MILKV_DUO" "CONFIG_BOARD_TYPE_MILKV_DUO_SPINOR" "CONFIG_BOARD_TYPE_MILKV_DUO_SPINAND" "CONFIG_BOARD_TYPE_MILKV_DUO256M") + BOARD_VALUE=("milkv-duo" "milkv-duo-spinor" "milkv-duo-spinand" "milkv-duo256m") + + for ((i=0;i<${#BOARD_CONFIG[@]};i++)) + do + config_value=$(grep -w "${BOARD_CONFIG[i]}" ${PROJECT_PATH}/.config | cut -d= -f2) + if [ "$config_value" == "y" ]; then + BOARD_TYPE=${BOARD_VALUE[i]} + break + fi + done +} + +get_board_type + +echo "start compress kernel..." + +lzma -c -9 -f -k ${PROJECT_PATH}/${IMAGE_NAME} > ${PROJECT_PATH}/Image.lzma + +mkdir -p ${ROOT_PATH}/output/${BOARD_TYPE} +./mkimage -f ${PROJECT_PATH}/multi.its -r ${ROOT_PATH}/output/${BOARD_TYPE}/boot.sd \ No newline at end of file diff --git a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin deleted file mode 100755 index 84ea0561c0..0000000000 Binary files a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin and /dev/null differ diff --git a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.bin b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.bin deleted file mode 100755 index c9902e4a9e..0000000000 --- a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.bin +++ /dev/null @@ -1 +0,0 @@ -ﾭ \ No newline at end of file diff --git a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env deleted file mode 100755 index cff9e11100..0000000000 --- a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env +++ /dev/null @@ -1,2 +0,0 @@ -MONITOR_RUNADDR=0x0000000080000000 -BLCP_2ND_RUNADDR=0x0000000083f40000 diff --git a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin deleted file mode 100755 index d2dabd6868..0000000000 Binary files a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin and /dev/null differ diff --git a/bsp/cvitek/pre-build/fsbl/build/cvi_board_memmap.h b/bsp/cvitek/pre-build/fsbl/build/cvi_board_memmap.h deleted file mode 100755 index 906c5b0ba6..0000000000 --- a/bsp/cvitek/pre-build/fsbl/build/cvi_board_memmap.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef __BOARD_MMAP__83494f74__ -#define __BOARD_MMAP__83494f74__ - -#define CONFIG_SYS_TEXT_BASE 0x80200000 /* offset 2.0MiB */ -#define CVIMMAP_ATF_SIZE 0x80000 /* 512.0KiB */ -#define CVIMMAP_BOOTLOGO_ADDR 0x82473000 /* offset 36.44921875MiB */ -#define CVIMMAP_BOOTLOGO_SIZE 0x0 /* 0.0KiB */ -#define CVIMMAP_CONFIG_SYS_INIT_SP_ADDR 0x82300000 /* offset 35.0MiB */ -#define CVIMMAP_CVI_UPDATE_HEADER_ADDR 0x813ffc00 /* offset 19.9990234375MiB */ -#define CVIMMAP_CVI_UPDATE_HEADER_SIZE 0x400 /* 1.0KiB */ -#define CVIMMAP_DRAM_BASE 0x80000000 /* offset 0.0KiB */ -#define CVIMMAP_DRAM_SIZE 0x4000000 /* 64.0MiB */ -#define CVIMMAP_FREERTOS_ADDR 0x83f40000 /* offset 63.25MiB */ -#define CVIMMAP_FREERTOS_RESERVED_ION_SIZE 0x0 /* 0.0KiB */ -#define CVIMMAP_FREERTOS_SIZE 0xc0000 /* 768.0KiB */ -#define CVIMMAP_FSBL_C906L_START_ADDR 0x83f40000 /* offset 63.25MiB */ -#define CVIMMAP_FSBL_UNZIP_ADDR 0x81400000 /* offset 20.0MiB */ -#define CVIMMAP_FSBL_UNZIP_SIZE 0xf00000 /* 15.0MiB */ -#define CVIMMAP_H26X_BITSTREAM_ADDR 0x82473000 /* offset 36.44921875MiB */ -#define CVIMMAP_H26X_BITSTREAM_SIZE 0x0 /* 0.0KiB */ -#define CVIMMAP_H26X_ENC_BUFF_ADDR 0x82473000 /* offset 36.44921875MiB */ -#define CVIMMAP_H26X_ENC_BUFF_SIZE 0x0 /* 0.0KiB */ -#define CVIMMAP_ION_ADDR 0x82473000 /* offset 36.44921875MiB */ -#define CVIMMAP_ION_SIZE 0x1acd000 /* 26.80078125MiB */ -#define CVIMMAP_ISP_MEM_BASE_ADDR 0x82473000 /* offset 36.44921875MiB */ -#define CVIMMAP_ISP_MEM_BASE_SIZE 0x0 /* 0.0KiB */ -#define CVIMMAP_KERNEL_MEMORY_ADDR 0x80000000 /* offset 0.0KiB */ -#define CVIMMAP_KERNEL_MEMORY_SIZE 0x3f40000 /* 63.25MiB */ -#define CVIMMAP_MONITOR_ADDR 0x80000000 /* offset 0.0KiB */ -#define CVIMMAP_OPENSBI_FDT_ADDR 0x80080000 /* offset 512.0KiB */ -#define CVIMMAP_OPENSBI_SIZE 0x80000 /* 512.0KiB */ -#define CVIMMAP_UIMAG_ADDR 0x81400000 /* offset 20.0MiB */ -#define CVIMMAP_UIMAG_SIZE 0xf00000 /* 15.0MiB */ - -#endif /* __BOARD_MMAP__83494f74__ */ diff --git a/bsp/cvitek/pre-build/fsbl/plat/cv180x/chip_conf.py b/bsp/cvitek/pre-build/fsbl/plat/cv180x/chip_conf.py deleted file mode 100755 index 2c487eda69..0000000000 --- a/bsp/cvitek/pre-build/fsbl/plat/cv180x/chip_conf.py +++ /dev/null @@ -1,38 +0,0 @@ -#!/usr/bin/env python3 - -import logging -import struct -import argparse - -CHIP_CONF_CMD_DELAY_MS = 0xFFFFFFFD -CHIP_CONF_CMD_DELAY_US = 0xFFFFFFFE - -CHIP_CONF_SCAN_START_1 = 0xFFFFFFA0 - - -def gen_chip_conf(args): - logging.info("gen_chip_conf") - regs = [ - (0x0E00000C, 0xA0000001), # ATF_DBG_REG = 0x0E00000C - (0x0E00000C, 0xA0000002), - # (CHIP_CONF_CMD_DELAY_MS, 100), - # (CHIP_CONF_CMD_DELAY_US, 100), - (CHIP_CONF_SCAN_START_1, 0xFFFFFFFF), - ] - - chip_conf = b"".join(struct.pack("= %r is required" % (PYTHON_MIN_VERSION,)) - sys.exit(-1) - - -try: - import coloredlogs -except ImportError: - coloredlogs = None - -try: - import argcomplete -except ImportError: - argcomplete = None - - -LOADER_2ND_MAGIC_ORIG = b"BL33" -LOADER_2ND_MAGIC_LZMA = b"B3MA" -LOADER_2ND_MAGIC_LZ4 = b"B3Z4" - -LOADER_2ND_MAGIC_LIST = [ - LOADER_2ND_MAGIC_ORIG, - LOADER_2ND_MAGIC_LZMA, - LOADER_2ND_MAGIC_LZ4, -] - -IMAGE_ALIGN = 512 -PARAM1_SIZE = 0x1000 -PARAM1_SIZE_WO_SIG = 0x800 -PARAM2_SIZE = 0x1000 - - -def round_up(divident, divisor): - return ((divident + divisor - 1) // divisor) * divisor - - -def lzma_compress(body): - z = lzma.LZMACompressor(lzma.FORMAT_ALONE, preset=lzma.PRESET_EXTREME) - compressed = z.compress(body) - compressed += z.flush() - - return compressed - - -def lz4_compress(body): - try: - import lz4.frame - except ImportError: - logging.error("lz4 is not installed. Run 'pip install lz4'.") - raise - - compressed = lz4.frame.compress(body) - return compressed - - -class Entry: - __slots__ = "name", "type", "addr", "_content", "entry_size" - - def __init__(self): - self.addr = None - self._content = None - - @property - def end(self): - return self.addr + self.entry_size - - @property - def content(self): - return self._content - - @content.setter - def content(self, value): - if type(value) == int: - value = value.to_bytes(self.entry_size, "little") - - if self.entry_size is not None: - if len(value) > self.entry_size: - raise ValueError("%s (%d bytes) must <= %#r" % (self.name, len(value), self.entry_size)) - value = value + b"\0" * (self.entry_size - len(value)) - - self._content = value - - @classmethod - def make(cls, name, entry_size, _type, init=None): - entry = Entry() - entry.name = name - entry.type = _type - entry.entry_size = entry_size - - if type(init) in (bytes, bytearray): - entry.content = bytes(init) - elif entry_size is not None: - entry.content = b"\0" * entry.entry_size - else: - entry.content = b"" - - return (name, entry) - - def toint(self): - if self.type != int: - raise TypeError("%s is not int type" % self.name) - - return int.from_bytes(self.content, "little") - - def tostr(self): - v = self.content - if self.type == int: - v = "%#08x" % self.toint() - elif type(self.content) in [bytes, bytearray]: - v = v.hex() - if len(v) > 32: - v = v[:32] + "..." - - return v - - def __str__(self): - v = self.tostr() - return "<%s=%s (%dbytes)>" % (self.name, v, self.entry_size) - - def __repr__(self): - v = self.tostr() - return "<%s: a=%#x s=%#x c=%s %r>" % (self.name, self.addr, self.entry_size, v, self.type) - - -class FIP: - param1 = OrderedDict( - [ - Entry.make("MAGIC1", 8, int, b"CVBL01\n\0"), - Entry.make("MAGIC2", 4, int), - Entry.make("PARAM_CKSUM", 4, int), - Entry.make("NAND_INFO", 128, int), - Entry.make("NOR_INFO", 36, int), - Entry.make("FIP_FLAGS", 8, int), - Entry.make("CHIP_CONF_SIZE", 4, int), - Entry.make("BLCP_IMG_CKSUM", 4, int), - Entry.make("BLCP_IMG_SIZE", 4, int), - Entry.make("BLCP_IMG_RUNADDR", 4, int), - Entry.make("BLCP_PARAM_LOADADDR", 4, int), - Entry.make("BLCP_PARAM_SIZE", 4, int), - Entry.make("BL2_IMG_CKSUM", 4, int), - Entry.make("BL2_IMG_SIZE", 4, int), - Entry.make("BLD_IMG_SIZE", 4, int), - Entry.make("PARAM2_LOADADDR", 4, int), - Entry.make("RESERVED1", 4, int), - Entry.make("CHIP_CONF", 760, bytes), - Entry.make("BL_EK", 32, bytes), - Entry.make("ROOT_PK", 512, bytes), - Entry.make("BL_PK", 512, bytes), - Entry.make("BL_PK_SIG", 512, bytes), - Entry.make("CHIP_CONF_SIG", 512, bytes), - Entry.make("BL2_IMG_SIG", 512, bytes), - Entry.make("BLCP_IMG_SIG", 512, bytes), - ] - ) - - body1 = OrderedDict( - [ - Entry.make("BLCP", None, bytes), - Entry.make("BL2", None, bytes), - ] - ) - - param2 = OrderedDict( - [ - Entry.make("MAGIC1", 8, int, b"CVLD02\n\0"), - Entry.make("PARAM2_CKSUM", 4, int), - Entry.make("RESERVED1", 4, bytes), - # DDR param - Entry.make("DDR_PARAM_CKSUM", 4, int), - Entry.make("DDR_PARAM_LOADADDR", 4, int), - Entry.make("DDR_PARAM_SIZE", 4, int), - Entry.make("DDR_PARAM_RESERVED", 4, int), - # BLCP_2ND - Entry.make("BLCP_2ND_CKSUM", 4, int), - Entry.make("BLCP_2ND_LOADADDR", 4, int), - Entry.make("BLCP_2ND_SIZE", 4, int), - Entry.make("BLCP_2ND_RUNADDR", 4, int), - # ATF-BL31 or OpenSBI - Entry.make("MONITOR_CKSUM", 4, int), - Entry.make("MONITOR_LOADADDR", 4, int), - Entry.make("MONITOR_SIZE", 4, int), - Entry.make("MONITOR_RUNADDR", 4, int), - # u-boot - Entry.make("LOADER_2ND_RESERVED0", 4, int), - Entry.make("LOADER_2ND_LOADADDR", 4, int), - Entry.make("LOADER_2ND_RESERVED1", 4, int), - Entry.make("LOADER_2ND_RESERVED2", 4, int), - # Reserved - Entry.make("RESERVED_LAST", 4096 - 16 * 5, bytes), - ] - ) - - body2 = OrderedDict( - [ - Entry.make("DDR_PARAM", None, bytes), - Entry.make("BLCP_2ND", None, bytes), - Entry.make("MONITOR", None, bytes), - Entry.make("LOADER_2ND", None, bytes), - ] - ) - - ldr_2nd_hdr = OrderedDict( - [ - Entry.make("JUMP0", 4, int), - Entry.make("MAGIC", 4, int), - Entry.make("CKSUM", 4, int), - Entry.make("SIZE", 4, int), - Entry.make("RUNADDR", 8, int), - Entry.make("RESERVED1", 4, int), - Entry.make("RESERVED2", 4, int), - ] - ) - - FIP_FLAGS_SCS_MASK = 0x000c - FIP_FLAGS_ENCRYPTED_MASK = 0x0030 - - def _param_size(self, param): - return max((e.end for e in param.values())) - - def _gen_param(self): - addr = 0 - for entry in self.param1.values(): - entry.addr = addr - addr += entry.entry_size - - assert PARAM1_SIZE_WO_SIG == self.param1["BL_PK_SIG"].addr - - addr = 0 - for entry in self.param2.values(): - entry.addr = addr - addr += entry.entry_size - - assert PARAM2_SIZE == self.param2["RESERVED_LAST"].addr + self.param2["RESERVED_LAST"].entry_size - - addr = 0 - for entry in self.ldr_2nd_hdr.values(): - entry.addr = addr - addr += entry.entry_size - - def __init__(self): - self.compress_algo = None - self._gen_param() - - def image_crc(self, image): - crc = binascii.crc_hqx(image, 0) - crc = pack("