From 75c6c40a64bac559860d3f1976d19655a9ef345c Mon Sep 17 00:00:00 2001 From: JasonJiaJie Date: Tue, 7 Nov 2017 10:45:02 +0800 Subject: [DeviceDriver][serial]Fix data bits error issue when using tcsetattr to set uart parameters. data bits should get from CSIZE. --- components/drivers/serial/serial.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/components/drivers/serial/serial.c b/components/drivers/serial/serial.c index 52dd65e17b..7ebec7a7b3 100644 --- a/components/drivers/serial/serial.c +++ b/components/drivers/serial/serial.c @@ -32,6 +32,7 @@ * 2015-11-10 bernard fix the poll rx issue when there is no data. * 2016-05-10 armink add fifo mode to DMA rx when serial->config.bufsz != 0. * 2017-01-19 aubr.cool prevent change serial rx bufsz when serial is opened. + * 2017-11-07 JasonJia fix data bits error issue when using tcsetattr. */ #include @@ -932,13 +933,24 @@ static rt_err_t rt_serial_control(struct rt_device *dev, baudrate = _get_baudrate(cfgetospeed(tio)); config.baud_rate = baudrate; - if (tio->c_cflag & CS6) config.data_bits = DATA_BITS_6; - else if (tio->c_cflag & CS7) config.data_bits = DATA_BITS_7; - else if (tio->c_cflag & CS8) config.data_bits = DATA_BITS_8; - else config.data_bits = DATA_BITS_5; + switch (tio->c_cflag & CSIZE) + { + case CS5: + config.data_bits = DATA_BITS_5; + break; + case CS6: + config.data_bits = DATA_BITS_6; + break; + case CS7: + config.data_bits = DATA_BITS_7; + break; + default: + config.data_bits = DATA_BITS_8; + break; + } - if (tio->c_cflag & CSTOPB) config.data_bits = STOP_BITS_2; - else config.data_bits = STOP_BITS_1; + if (tio->c_cflag & CSTOPB) config.stop_bits = STOP_BITS_2; + else config.stop_bits = STOP_BITS_1; if (tio->c_cflag & PARENB) { -- cgit v1.3.1 From d6f80720b628580258c757485a6a55901b5fdb53 Mon Sep 17 00:00:00 2001 From: SummerGift Date: Tue, 7 Nov 2017 12:34:26 +0800 Subject: update bsp/stm32f429-apollo/rtconfig.h bsp/stm32f429-apollo/.config --- bsp/stm32f429-apollo/.config | 21 +++++++++++++++++++-- bsp/stm32f429-apollo/rtconfig.h | 20 ++++++++++++++++++-- 2 files changed, 37 insertions(+), 4 deletions(-) diff --git a/bsp/stm32f429-apollo/.config b/bsp/stm32f429-apollo/.config index 56a7603dbf..27d5bc355d 100644 --- a/bsp/stm32f429-apollo/.config +++ b/bsp/stm32f429-apollo/.config @@ -14,7 +14,7 @@ CONFIG_RT_TICK_PER_SECOND=1000 CONFIG_RT_DEBUG=y CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_DEBUG_INIT=1 -# CONFIG_RT_DEBUG_THREAD is not set +CONFIG_RT_DEBUG_THREAD=0 CONFIG_RT_USING_HOOK=y CONFIG_IDLE_THREAD_STACK_SIZE=1024 # CONFIG_RT_USING_TIMER_SOFT is not set @@ -42,6 +42,7 @@ CONFIG_RT_USING_SMALL_MEM=y # Kernel Device Object # CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_INTERRUPT_INFO is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart" @@ -100,6 +101,8 @@ CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 CONFIG_RT_DFS_ELM_REENTRANT=y CONFIG_RT_USING_DFS_DEVFS=y CONFIG_RT_USING_DFS_NET=y +CONFIG_HAVE_SYS_SELECT_H=y +# CONFIG_HAVE_SYS_SOCKET_H is not set # CONFIG_RT_USING_DFS_ROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set # CONFIG_RT_USING_DFS_UFFS is not set @@ -151,7 +154,14 @@ CONFIG_RT_LWIP_DNS=y CONFIG_RT_LWIP_DHCP=y CONFIG_IP_SOF_BROADCAST=1 CONFIG_IP_SOF_BROADCAST_RECV=1 -CONFIG_LWIP_USING_DHCPD=y +# CONFIG_LWIP_USING_DHCPD is not set + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.10.30" +CONFIG_RT_LWIP_GWADDR="192.168.10.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" CONFIG_RT_LWIP_UDP=y CONFIG_RT_LWIP_TCP=y # CONFIG_RT_LWIP_RAW is not set @@ -189,6 +199,11 @@ CONFIG_LWIP_SO_RCVBUF=1 # # CONFIG_RT_USING_GUIENGINE is not set +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + # # RT-Thread online packages # @@ -227,12 +242,14 @@ CONFIG_LWIP_SO_RCVBUF=1 # # multimedia packages # +# CONFIG_PKG_USING_FASTLZ is not set # # tools packages # # CONFIG_PKG_USING_CMBACKTRACE is not set # CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set # # miscellaneous packages diff --git a/bsp/stm32f429-apollo/rtconfig.h b/bsp/stm32f429-apollo/rtconfig.h index acf7687364..9a94a8d13e 100644 --- a/bsp/stm32f429-apollo/rtconfig.h +++ b/bsp/stm32f429-apollo/rtconfig.h @@ -15,7 +15,7 @@ #define RT_DEBUG #define RT_USING_OVERFLOW_CHECK #define RT_DEBUG_INIT 1 -/* RT_DEBUG_THREAD is not set */ +#define RT_DEBUG_THREAD 0 #define RT_USING_HOOK #define IDLE_THREAD_STACK_SIZE 1024 /* RT_USING_TIMER_SOFT is not set */ @@ -40,6 +40,7 @@ /* Kernel Device Object */ #define RT_USING_DEVICE +/* RT_USING_INTERRUPT_INFO is not set */ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart" @@ -93,6 +94,8 @@ #define RT_DFS_ELM_REENTRANT #define RT_USING_DFS_DEVFS #define RT_USING_DFS_NET +#define HAVE_SYS_SELECT_H +/* HAVE_SYS_SOCKET_H is not set */ /* RT_USING_DFS_ROMFS is not set */ /* RT_USING_DFS_RAMFS is not set */ /* RT_USING_DFS_UFFS is not set */ @@ -139,7 +142,13 @@ #define RT_LWIP_DHCP #define IP_SOF_BROADCAST 1 #define IP_SOF_BROADCAST_RECV 1 -#define LWIP_USING_DHCPD +/* LWIP_USING_DHCPD is not set */ + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.10.30" +#define RT_LWIP_GWADDR "192.168.10.1" +#define RT_LWIP_MSKADDR "255.255.255.0" #define RT_LWIP_UDP #define RT_LWIP_TCP /* RT_LWIP_RAW is not set */ @@ -175,6 +184,10 @@ /* RT_USING_GUIENGINE is not set */ +/* VBUS(Virtual Software BUS) */ + +/* RT_USING_VBUS is not set */ + /* RT-Thread online packages */ /* system packages */ @@ -205,10 +218,13 @@ /* multimedia packages */ +/* PKG_USING_FASTLZ is not set */ + /* tools packages */ /* PKG_USING_CMBACKTRACE is not set */ /* PKG_USING_EASYLOGGER is not set */ +/* PKG_USING_SYSTEMVIEW is not set */ /* miscellaneous packages */ -- cgit v1.3.1 From 1bbe09df9492378fe2f8d71271f33d721c6eee9d Mon Sep 17 00:00:00 2001 From: 勤为本 <1207280597@qq.com> Date: Tue, 7 Nov 2017 16:47:39 +0800 Subject: 把龙芯1c的SPI接口改为RTT统一的SPI接口 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/ls1cdev/drivers/drv_spi.c | 229 +++++++++++++++++++++++++++++++++++++++ bsp/ls1cdev/drivers/drv_spi.h | 55 ++++++++++ bsp/ls1cdev/drivers/led.c | 40 ------- bsp/ls1cdev/drivers/led.h | 27 ----- bsp/ls1cdev/libraries/ls1c_spi.c | 141 +++++------------------- bsp/ls1cdev/libraries/ls1c_spi.h | 96 +++++++++++----- bsp/ls1cdev/rtconfig.h | 5 + 7 files changed, 389 insertions(+), 204 deletions(-) create mode 100644 bsp/ls1cdev/drivers/drv_spi.c create mode 100644 bsp/ls1cdev/drivers/drv_spi.h delete mode 100644 bsp/ls1cdev/drivers/led.c delete mode 100644 bsp/ls1cdev/drivers/led.h diff --git a/bsp/ls1cdev/drivers/drv_spi.c b/bsp/ls1cdev/drivers/drv_spi.c new file mode 100644 index 0000000000..b26de557db --- /dev/null +++ b/bsp/ls1cdev/drivers/drv_spi.c @@ -0,0 +1,229 @@ +/* + * File : drv_spi.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2017-11-02 Ϊ first version + */ + +#include +#include +#include "drv_spi.h" + + +//#define DEBUG + +#ifdef DEBUG +#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__) +#else +#define DEBUG_PRINTF(...) +#endif + + +static rt_err_t configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration); +static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message *message); + + +static struct rt_spi_ops ls1c_spi_ops = +{ + .configure = configure, + .xfer = xfer +}; + + +static rt_err_t configure(struct rt_spi_device *device, + struct rt_spi_configuration *configuration) +{ + struct rt_spi_bus *spi_bus = NULL; + struct ls1c_spi *ls1c_spi = NULL; + unsigned char SPIx = 0; + void *spi_base = NULL; + unsigned char cpol = 0; + unsigned char cpha = 0; + unsigned char val = 0; + + RT_ASSERT(NULL != device); + RT_ASSERT(NULL != configuration); + + spi_bus = device->bus; + ls1c_spi = (struct ls1c_spi *)spi_bus->parent.user_data; + SPIx = ls1c_spi->SPIx; + spi_base = ls1c_spi_get_base(SPIx); + + { + // ʹSPImasterģʽرж + reg_write_8(0x53, spi_base + LS1C_SPI_SPCR_OFFSET); + + // ״̬Ĵ + reg_write_8(0xc0, spi_base + LS1C_SPI_SPSR_OFFSET); + + // 1ֽڲжϣ()뷢(д)ʱͬʱ + reg_write_8(0x03, spi_base + LS1C_SPI_SPER_OFFSET); + + // رSPI flash + val = reg_read_8(spi_base + LS1C_SPI_SFC_PARAM_OFFSET); + val &= 0xfe; + reg_write_8(val, spi_base + LS1C_SPI_SFC_PARAM_OFFSET); + + // spi flashʱƼĴ + reg_write_8(0x05, spi_base + LS1C_SPI_SFC_TIMING_OFFSET); + } + + // baudrate + ls1c_spi_set_clock(spi_base, configuration->max_hz); + + // ͨģʽ(ʱӼԺλ) + if (configuration->mode & RT_SPI_CPOL) // cpol + { + cpol = SPI_CPOL_1; + } + else + { + cpol = SPI_CPOL_0; + } + if (configuration->mode & RT_SPI_CPHA) // cpha + { + cpha = SPI_CPHA_1; + } + else + { + cpha = SPI_CPHA_0; + } + ls1c_spi_set_mode(spi_base, cpol, cpha); + + DEBUG_PRINTF("ls1c spi%d configuration\n", SPIx); + + return RT_EOK; +} + + +static rt_uint32_t xfer(struct rt_spi_device *device, + struct rt_spi_message *message) +{ + struct rt_spi_bus *spi_bus = NULL; + struct ls1c_spi *ls1c_spi = NULL; + void *spi_base = NULL; + unsigned char SPIx = 0; + struct ls1c_spi_cs *ls1c_spi_cs = NULL; + unsigned char cs = 0; + rt_uint32_t size = 0; + const rt_uint8_t *send_ptr = NULL; + rt_uint8_t *recv_ptr = NULL; + rt_uint8_t data = 0; + + RT_ASSERT(NULL != device); + RT_ASSERT(NULL != message); + + spi_bus = device->bus; + ls1c_spi = spi_bus->parent.user_data; + SPIx = ls1c_spi->SPIx; + spi_base = ls1c_spi_get_base(SPIx); + ls1c_spi_cs = device->parent.user_data; + cs = ls1c_spi_cs->cs; + size = message->length; + + DEBUG_PRINTF("[%s] SPIx=%d, cs=%d\n", __FUNCTION__, SPIx, cs); + + // take cs + if (message->cs_take) + { + ls1c_spi_set_cs(spi_base, cs, 0); + } + + // շ + send_ptr = message->send_buf; + recv_ptr = message->recv_buf; + while (size--) + { + data = 0xFF; + if (NULL != send_ptr) + { + data = *send_ptr++; + } + + if (NULL != recv_ptr) + { + *recv_ptr++ = ls1c_spi_txrx_byte(spi_base, data); + } + else + { + ls1c_spi_txrx_byte(spi_base, data); + } + } + + // release cs + if (message->cs_release) + { + ls1c_spi_set_cs(spi_base, cs, 1); + } + + return message->length; +} + + +#ifdef RT_USING_SPI0 +struct ls1c_spi ls1c_spi0 = +{ + .SPIx = LS1C_SPI_0, +}; + +static struct rt_spi_bus spi0_bus; +#endif + + +#ifdef RT_USING_SPI1 +struct ls1c_spi ls1c_spi1 = +{ + .SPIx = LS1C_SPI_1, +}; + +static struct rt_spi_bus spi1_bus; +#endif + + +/* + * ʼעо1cspi + * @SPI SPIߣLS1C_SPI_0 LS1C_SPI_1 + * @spi_bus_name + * @ret + */ +rt_err_t ls1c_spi_bus_register(rt_uint8_t SPI, const char *spi_bus_name) +{ + struct rt_spi_bus *spi_bus = NULL; + +#ifdef RT_USING_SPI0 + if (LS1C_SPI_0 == SPI) + { + spi_bus = &spi0_bus; + spi_bus->parent.user_data = &ls1c_spi0; + } +#endif + +#ifdef RT_USING_SPI1 + if (LS1C_SPI_1 == SPI) + { + spi_bus = &spi1_bus; + spi_bus->parent.user_data = &ls1c_spi1; + } +#endif + + return rt_spi_bus_register(spi_bus, spi_bus_name, &ls1c_spi_ops); +} + + diff --git a/bsp/ls1cdev/drivers/drv_spi.h b/bsp/ls1cdev/drivers/drv_spi.h new file mode 100644 index 0000000000..94fbb58097 --- /dev/null +++ b/bsp/ls1cdev/drivers/drv_spi.h @@ -0,0 +1,55 @@ +/* + * File : drv_spi.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2017-11-02 Ϊ first version + */ + +#ifndef LS1C_DRV_SPI_H +#define LS1C_DRV_SPI_H + + +#include "../libraries/ls1c_spi.h" + + +struct ls1c_spi +{ + unsigned char SPIx; // LS1C_SPI_0 or LS1C_SPI_1 +}; + + +struct ls1c_spi_cs +{ + unsigned char cs; // LS1C_SPI_CS_0, LS1C_SPI_CS_1, LS1C_SPI_CS_2 or LS1C_SPI_CS_3 +}; + + + +/* + * ʼעо1cspi + * @SPI SPIߣLS1C_SPI_0 LS1C_SPI_1 + * @spi_bus_name + * @ret + */ +rt_err_t ls1c_spi_bus_register(rt_uint8_t SPI, const char *spi_bus_name); + + +#endif + diff --git a/bsp/ls1cdev/drivers/led.c b/bsp/ls1cdev/drivers/led.c deleted file mode 100644 index 6f73ac9892..0000000000 --- a/bsp/ls1cdev/drivers/led.c +++ /dev/null @@ -1,40 +0,0 @@ -// ledӿ -// ʹõ͵ƽledߵƽϨled - - -#include "ls1c_gpio.h" - - -// ʼled -// @led_gpio ledgpio -void led_init(unsigned int led_gpio) -{ - gpio_init(led_gpio, gpio_mode_output); - gpio_set(led_gpio, gpio_level_high); // ָʾĬϨ - - return ; -} - - -// led -// @led_gpio ledgpio -void led_on(unsigned int led_gpio) -{ - gpio_set(led_gpio, gpio_level_low); - - return ; -} - - -// Ϩled -// @led_gpio -void led_off(unsigned int led_gpio) -{ - gpio_set(led_gpio, gpio_level_high); - - return ; -} - - - - diff --git a/bsp/ls1cdev/drivers/led.h b/bsp/ls1cdev/drivers/led.h deleted file mode 100644 index 76ea905371..0000000000 --- a/bsp/ls1cdev/drivers/led.h +++ /dev/null @@ -1,27 +0,0 @@ -// ledӿ -// ʹõ͵ƽledߵƽϨled - -#ifndef __OPENLOONGSON_LED_H -#define __OPENLOONGSON_LED_H - - -// ʼled -// @led_gpio ledgpio -void led_init(unsigned int led_gpio); - - -// led -// @led_gpio ledgpio -void led_on(unsigned int led_gpio); - - -// Ϩled -// @led_gpio -void led_off(unsigned int led_gpio); - - - - - -#endif - diff --git a/bsp/ls1cdev/libraries/ls1c_spi.c b/bsp/ls1cdev/libraries/ls1c_spi.c index 8547626c30..7da50e1c37 100644 --- a/bsp/ls1cdev/libraries/ls1c_spi.c +++ b/bsp/ls1cdev/libraries/ls1c_spi.c @@ -32,53 +32,13 @@ #include "ls1c_spi.h" -// Ĵƫ -#define LS1C_SPI_SPCR_OFFSET (0) // ƼĴ -#define LS1C_SPI_SPSR_OFFSET (1) // ״̬Ĵ -#define LS1C_SPI_TxFIFO_OFFSET (2) // ͵ݼĴݼĴƫͬ -#define LS1C_SPI_RxFIFO_OFFSET (2) // յݼĴ뷢ݼĴƫͬ -#define LS1C_SPI_SPER_OFFSET (3) // ⲿĴ -#define LS1C_SPI_SFC_PARAM_OFFSET (4) // ƼĴ -#define LS1C_SPI_SFC_SOFTCS_OFFSET (5) // ƬѡƼĴ -#define LS1C_SPI_SFC_TIMING_OFFSET (6) // ʱƼĴ - -// ĴSPCRеλ -#define LS1C_SPI_SPCR_SPIE_BIT (7) -#define LS1C_SPI_SPCR_SPIE_MASK (0x01 << LS1C_SPI_SPCR_SPIE_BIT) -#define LS1C_SPI_SPCR_SPE_BIT (6) -#define LS1C_SPI_SPCR_SPE_MASK (0x01 << LS1C_SPI_SPCR_SPE_BIT) -#define LS1C_SPI_SPCR_CPOL_BIT (3) -#define LS1C_SPI_SPCR_CPOL_MASK (0x01 << LS1C_SPI_SPCR_CPOL_BIT) -#define LS1C_SPI_SPCR_CPHA_BIT (2) -#define LS1C_SPI_SPCR_CPHA_MASK (0x01 << LS1C_SPI_SPCR_CPHA_BIT) -#define LS1C_SPI_SPCR_SPR_BIT (0) -#define LS1C_SPI_SPCR_SPR_MASK (0x03 << LS1C_SPI_SPCR_SPR_BIT) - -// ĴSPSRеλ -#define LS1C_SPI_SPSR_SPIF_BIT (7) -#define LS1C_SPI_SPSR_SPIF_MASK (0x01 << LS1C_SPI_SPSR_SPIF_BIT) -#define LS1C_SPI_SPSR_WCOL_BIT (6) -#define LS1C_SPI_SPSR_WCOL_MASK (0x01 << LS1C_SPI_SPSR_WCOL_BIT) - -// ĴSPERеλ -#define LS1C_SPI_SPER_SPRE_BIT (0) -#define LS1C_SPI_SPER_SPRE_MASK (0x3 << LS1C_SPI_SPER_SPRE_BIT) - -// ĴSFC_SOFTCSλ -#define LS1C_SPI_SFC_SOFTCS_CSN_BIT (4) -#define LS1C_SPI_SFC_SOFTCS_CSN_MASK (0x0f << LS1C_SPI_SFC_SOFTCS_CSN_BIT) -#define LS1C_SPI_SFC_SOFTCS_CSEN_BIT (0) -#define LS1C_SPI_SFC_SOFTCS_CSEN_MASK (0x0f << LS1C_SPI_SFC_SOFTCS_CSEN_BIT) - -// ͳʱֵ -#define LS1C_SPI_TX_TIMEOUT (20000) /* * ȡָSPIģĻַ * @SPIx SPIģı */ -inline void *spi_get_base(ls1c_spi_t SPIx) +inline void *ls1c_spi_get_base(unsigned char SPIx) { void *base = NULL; @@ -103,15 +63,12 @@ inline void *spi_get_base(ls1c_spi_t SPIx) /* * ӡָSPIģмĴֵ - * @spi_info_p SPIģϢ + * @spi_base ַ */ -void spi_print_all_regs_info(ls1c_spi_info_t *spi_info_p) +void ls1c_spi_print_all_regs_info(void *spi_base) { - void *spi_base = spi_get_base(spi_info_p->SPIx); - - rt_kprintf("[%s] SPI%d's info:\r\n\ - SPCR=0x%x, SPSR=0x%x, SPER=0x%x, SFC_PARAM=0x%x, SFC_SOFTCS=0x%x, SFC_TIMING=0x%x\r\n", - __FUNCTION__, spi_info_p->SPIx, + rt_kprintf("[%s] SPCR=0x%x, SPSR=0x%x, SPER=0x%x, SFC_PARAM=0x%x, SFC_SOFTCS=0x%x, SFC_TIMING=0x%x\r\n", + __FUNCTION__, reg_read_8(spi_base + LS1C_SPI_SPCR_OFFSET), reg_read_8(spi_base + LS1C_SPI_SPSR_OFFSET), reg_read_8(spi_base + LS1C_SPI_SPER_OFFSET), @@ -128,7 +85,7 @@ void spi_print_all_regs_info(ls1c_spi_info_t *spi_info_p) * @max_speed_hz SPIͨٶ * @ret Ƶϵ */ -unsigned int spi_get_div(unsigned int max_speed_hz) +unsigned int ls1c_spi_get_div(unsigned int max_speed_hz) { unsigned long clk = 0; unsigned int div = 0; @@ -189,16 +146,16 @@ unsigned int spi_get_div(unsigned int max_speed_hz) /* * ʱ - * @spi_info_p SPIģϢ + * @spi_base ַ + * @max_hz Ƶʣλhz */ -void spi_set_clock(ls1c_spi_info_t *spi_info_p) +void ls1c_spi_set_clock(void *spi_base, unsigned long max_hz) { - void *spi_base = spi_get_base(spi_info_p->SPIx); unsigned int div = 0; unsigned char val = 0; // ȡƵϵ - div = spi_get_div(spi_info_p->max_speed_hz); + div = ls1c_spi_get_div(max_hz); // spr val = reg_read_8(spi_base + LS1C_SPI_SPCR_OFFSET); @@ -218,22 +175,23 @@ void spi_set_clock(ls1c_spi_info_t *spi_info_p) /* * ͨģʽ(ʱӼԺλ) - * @spi_info_p SPIģϢ + * @spi_base ַ + * @cpol ʱӼ + * @cpha ʱλ */ -void spi_set_mode(ls1c_spi_info_t *spi_info_p) +void ls1c_spi_set_mode(void *spi_base, unsigned char cpol, unsigned char cpha) { - void *spi_base = spi_get_base(spi_info_p->SPIx); unsigned char val = 0; val = reg_read_8(spi_base + LS1C_SPI_SPCR_OFFSET); // ʱӼ--cpol - val &= (~LS1C_SPI_SPCR_CPOL_MASK); // cpol0 - val |= (spi_info_p->cpol << LS1C_SPI_SPCR_CPOL_BIT); // дµcpol + val &= (~LS1C_SPI_SPCR_CPOL_MASK); // cpol0 + val |= (cpol << LS1C_SPI_SPCR_CPOL_BIT); // дµcpol // ʱλ--cpha - val &= (~LS1C_SPI_SPCR_CPHA_MASK); // cpha0 - val |= (spi_info_p->cpha << LS1C_SPI_SPCR_CPHA_BIT); // дµcpha + val &= (~LS1C_SPI_SPCR_CPHA_MASK); // cpha0 + val |= (cpha << LS1C_SPI_SPCR_CPHA_BIT); // дµcpha reg_write_8(val, spi_base + LS1C_SPI_SPCR_OFFSET); @@ -243,13 +201,12 @@ void spi_set_mode(ls1c_spi_info_t *spi_info_p) /* * ָƬѡΪָ״̬ - * @spi_info_p SPIģϢ + * @spi_base ַ + * @cs Ƭѡ * @new_status Ƭѡŵ״̬ȡֵΪ01ߵƽ͵ƽ */ -void spi_set_cs(ls1c_spi_info_t *spi_info_p, int new_status) +void ls1c_spi_set_cs(void *spi_base, unsigned char cs, int new_status) { - void *spi_base = spi_get_base(spi_info_p->SPIx); - unsigned char cs = spi_info_p->cs; unsigned char val = 0; val = 0xf0 | (0x01 << cs); // ȫcsn=1ָcsen=1 @@ -267,51 +224,12 @@ void spi_set_cs(ls1c_spi_info_t *spi_info_p, int new_status) } -/* - * ʼָSPIģ - * @spi_info_p SPIģϢ - */ -void spi_init(ls1c_spi_info_t *spi_info_p) -{ - void *spi_base = spi_get_base(spi_info_p->SPIx); - unsigned char val = 0; - - // ʹSPImasterģʽرж - reg_write_8(0x53, spi_base + LS1C_SPI_SPCR_OFFSET); - - // ״̬Ĵ - reg_write_8(0xc0, spi_base + LS1C_SPI_SPSR_OFFSET); - - // 1ֽڲжϣ()뷢(д)ʱͬʱ - reg_write_8(0x03, spi_base + LS1C_SPI_SPER_OFFSET); - - // رSPI flash - val = reg_read_8(spi_base + LS1C_SPI_SFC_PARAM_OFFSET); - val &= 0xfe; - reg_write_8(val, spi_base + LS1C_SPI_SFC_PARAM_OFFSET); - - // spi flashʱƼĴ - reg_write_8(0x05, spi_base + LS1C_SPI_SFC_TIMING_OFFSET); - - // ʱ - spi_set_clock(spi_info_p); - - // ͨģʽ(ʱӼԺλ) - spi_set_mode(spi_info_p); - - // ӡĴϢ(ڵ) -// spi_print_all_regs_info(spi_info_p); - - return ; -} - - /* * ȴշ + * @spi_base ַ */ -inline void spi_wait_txrx_done(ls1c_spi_info_t *spi_info_p) +inline void ls1c_spi_wait_txrx_done(void *spi_base) { - void *spi_base = spi_get_base(spi_info_p->SPIx); int timeout = LS1C_SPI_TX_TIMEOUT; while (timeout--) @@ -326,10 +244,10 @@ inline void spi_wait_txrx_done(ls1c_spi_info_t *spi_info_p) /* * жϺͱ־λ + * @spi_base ַ */ -inline void spi_clear(ls1c_spi_info_t *spi_info_p) +inline void ls1c_spi_clear(void *spi_base) { - void *spi_base = spi_get_base(spi_info_p->SPIx); unsigned char val = 0; // ж @@ -356,20 +274,19 @@ inline void spi_clear(ls1c_spi_info_t *spi_info_p) * ע⣬ڶϵͳУ˺Ҫ⡣ * ֤ںij豸շijֽڵĹУܱлͬʱͬһSPIϵĴ豸ͨ * Ϊо1cÿ·SPIϿܽвͬĴ豸ͨƵʡģʽȿܲͬ - * @spi_info_p SPIӿ + * @spi_base ַ * @tx_ch ͵ * @ret յ */ -unsigned char spi_txrx_byte(ls1c_spi_info_t *spi_info_p, unsigned char tx_ch) +unsigned char ls1c_spi_txrx_byte(void *spi_base, unsigned char tx_ch) { - void *spi_base = spi_get_base(spi_info_p->SPIx); unsigned char rx_ch = 0; // շ reg_write_8(tx_ch, spi_base + LS1C_SPI_TxFIFO_OFFSET); // ʼ - spi_wait_txrx_done(spi_info_p); // ȴշ + ls1c_spi_wait_txrx_done(spi_base); // ȴշ rx_ch = reg_read_8(spi_base + LS1C_SPI_RxFIFO_OFFSET); // ȡյ - spi_clear(spi_info_p); // жϺͱ־λ + ls1c_spi_clear(spi_base); // жϺͱ־λ return rx_ch; } diff --git a/bsp/ls1cdev/libraries/ls1c_spi.h b/bsp/ls1cdev/libraries/ls1c_spi.h index 6b041b19c1..8046127de7 100644 --- a/bsp/ls1cdev/libraries/ls1c_spi.h +++ b/bsp/ls1cdev/libraries/ls1c_spi.h @@ -29,15 +29,10 @@ // SPIģ -typedef enum -{ - LS1C_SPI_0 = 0, - LS1C_SPI_1, -}ls1c_spi_t; - +#define LS1C_SPI_0 (0) +#define LS1C_SPI_1 (1) // Ƭѡ -#define LS1C_SPI_INVALID_CS (-1) #define LS1C_SPI_CS_0 (0) #define LS1C_SPI_CS_1 (1) #define LS1C_SPI_CS_2 (2) @@ -50,31 +45,80 @@ typedef enum #define SPI_CPHA_0 (0) -// ӲSPIϢ -typedef struct -{ - ls1c_spi_t SPIx; // SPIģ - unsigned long max_speed_hz; // ͨٶȣλhz - unsigned char cs; // Ƭѡ - unsigned char cpol; // ʱӼ - unsigned char cpha; // ʱλ -}ls1c_spi_info_t; +// Ĵƫ +#define LS1C_SPI_SPCR_OFFSET (0) // ƼĴ +#define LS1C_SPI_SPSR_OFFSET (1) // ״̬Ĵ +#define LS1C_SPI_TxFIFO_OFFSET (2) // ͵ݼĴݼĴƫͬ +#define LS1C_SPI_RxFIFO_OFFSET (2) // յݼĴ뷢ݼĴƫͬ +#define LS1C_SPI_SPER_OFFSET (3) // ⲿĴ +#define LS1C_SPI_SFC_PARAM_OFFSET (4) // ƼĴ +#define LS1C_SPI_SFC_SOFTCS_OFFSET (5) // ƬѡƼĴ +#define LS1C_SPI_SFC_TIMING_OFFSET (6) // ʱƼĴ + +// ĴSPCRеλ +#define LS1C_SPI_SPCR_SPIE_BIT (7) +#define LS1C_SPI_SPCR_SPIE_MASK (0x01 << LS1C_SPI_SPCR_SPIE_BIT) +#define LS1C_SPI_SPCR_SPE_BIT (6) +#define LS1C_SPI_SPCR_SPE_MASK (0x01 << LS1C_SPI_SPCR_SPE_BIT) +#define LS1C_SPI_SPCR_CPOL_BIT (3) +#define LS1C_SPI_SPCR_CPOL_MASK (0x01 << LS1C_SPI_SPCR_CPOL_BIT) +#define LS1C_SPI_SPCR_CPHA_BIT (2) +#define LS1C_SPI_SPCR_CPHA_MASK (0x01 << LS1C_SPI_SPCR_CPHA_BIT) +#define LS1C_SPI_SPCR_SPR_BIT (0) +#define LS1C_SPI_SPCR_SPR_MASK (0x03 << LS1C_SPI_SPCR_SPR_BIT) + +// ĴSPSRеλ +#define LS1C_SPI_SPSR_SPIF_BIT (7) +#define LS1C_SPI_SPSR_SPIF_MASK (0x01 << LS1C_SPI_SPSR_SPIF_BIT) +#define LS1C_SPI_SPSR_WCOL_BIT (6) +#define LS1C_SPI_SPSR_WCOL_MASK (0x01 << LS1C_SPI_SPSR_WCOL_BIT) + +// ĴSPERеλ +#define LS1C_SPI_SPER_SPRE_BIT (0) +#define LS1C_SPI_SPER_SPRE_MASK (0x3 << LS1C_SPI_SPER_SPRE_BIT) + +// ĴSFC_SOFTCSλ +#define LS1C_SPI_SFC_SOFTCS_CSN_BIT (4) +#define LS1C_SPI_SFC_SOFTCS_CSN_MASK (0x0f << LS1C_SPI_SFC_SOFTCS_CSN_BIT) +#define LS1C_SPI_SFC_SOFTCS_CSEN_BIT (0) +#define LS1C_SPI_SFC_SOFTCS_CSEN_MASK (0x0f << LS1C_SPI_SFC_SOFTCS_CSEN_BIT) + +// ͳʱֵ +#define LS1C_SPI_TX_TIMEOUT (20000) + + +/* + * ȡָSPIģĻַ + * @SPIx SPIģı + */ +inline void *ls1c_spi_get_base(unsigned char SPIx); /* - * ʼָSPIģ - * @spi_info_p SPIģϢ + * ʱ + * @spi_base ַ + * @max_hz Ƶʣλhz */ -void spi_init(ls1c_spi_info_t *spi_info_p); +void ls1c_spi_set_clock(void *spi_base, unsigned long max_hz); + + +/* + * ͨģʽ(ʱӼԺλ) + * @spi_base ַ + * @cpol ʱӼ + * @cpha ʱλ + */ +void ls1c_spi_set_mode(void *spi_base, unsigned char cpol, unsigned char cpha); /* * ָƬѡΪָ״̬ - * @spi_info_p SPIģϢ + * @spi_base ַ + * @cs Ƭѡ * @new_status Ƭѡŵ״̬ȡֵΪ01ߵƽ͵ƽ */ -void spi_set_cs(ls1c_spi_info_t *spi_info_p, int new_status); +void ls1c_spi_set_cs(void *spi_base, unsigned char cs, int new_status); /* @@ -82,18 +126,20 @@ void spi_set_cs(ls1c_spi_info_t *spi_info_p, int new_status); * ע⣬ڶϵͳУ˺Ҫ⡣ * ֤ںij豸շijֽڵĹУܱлͬʱͬһSPIϵĴ豸ͨ * Ϊо1cÿ·SPIϿܽвͬĴ豸ͨƵʡģʽȿܲͬ - * @spi_info_p SPIӿ + * @spi_base ַ * @tx_ch ͵ * @ret յ */ -unsigned char spi_txrx_byte(ls1c_spi_info_t *spi_info_p, unsigned char tx_ch); +unsigned char ls1c_spi_txrx_byte(void *spi_base, unsigned char tx_ch); /* * ӡָSPIģмĴֵ - * @spi_info_p SPIģϢ + * @spi_base ַ */ -void spi_print_all_regs_info(ls1c_spi_info_t *spi_info_p); +void ls1c_spi_print_all_regs_info(void *spi_base); + + #endif diff --git a/bsp/ls1cdev/rtconfig.h b/bsp/ls1cdev/rtconfig.h index 168d3a7fda..ae208a485e 100644 --- a/bsp/ls1cdev/rtconfig.h +++ b/bsp/ls1cdev/rtconfig.h @@ -227,6 +227,11 @@ #define RTGUI_IMAGE_BMP // +#define RT_USING_SPI +#define RT_USING_SPI0 +#define RT_USING_SPI1 + + // #endif -- cgit v1.3.1 From ba2f149a4c083d1a8f7a9991d8434347eb578c96 Mon Sep 17 00:00:00 2001 From: armink Date: Tue, 7 Nov 2017 20:29:32 +0800 Subject: [DeviceDriver] Change `pin_irq_enable` to `rt_pin_irq_enable`. --- components/drivers/include/drivers/pin.h | 2 +- components/drivers/misc/pin.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/components/drivers/include/drivers/pin.h b/components/drivers/include/drivers/pin.h index 9745aafdf7..a4ac39c75b 100644 --- a/components/drivers/include/drivers/pin.h +++ b/components/drivers/include/drivers/pin.h @@ -96,7 +96,7 @@ int rt_pin_read(rt_base_t pin); rt_err_t rt_pin_attach_irq(rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args); rt_err_t rt_pin_dettach_irq(rt_int32_t pin); -rt_err_t pin_irq_enable(rt_base_t pin, rt_uint32_t enabled); +rt_err_t rt_pin_irq_enable(rt_base_t pin, rt_uint32_t enabled); int rt_device_pin_irq_register(const char *name, const struct rt_pin_ops *ops, void *user_data); diff --git a/components/drivers/misc/pin.c b/components/drivers/misc/pin.c index 9cbe47089e..9ed827f0b5 100644 --- a/components/drivers/misc/pin.c +++ b/components/drivers/misc/pin.c @@ -117,7 +117,7 @@ rt_err_t rt_pin_dettach_irq(rt_int32_t pin) } return RT_ENOSYS; } -rt_err_t pin_irq_enable(rt_base_t pin, rt_uint32_t enabled) +rt_err_t rt_pin_irq_enable(rt_base_t pin, rt_uint32_t enabled) { RT_ASSERT(_hw_pin.ops != RT_NULL); if(_hw_pin.ops->pin_irq_enable) -- cgit v1.3.1 From 1e9f9824d3d001d7936a189f93cbd991c05eaaa7 Mon Sep 17 00:00:00 2001 From: armink Date: Tue, 7 Nov 2017 20:40:44 +0800 Subject: [BSP] Update stm32f40x BSP gpio driver. --- bsp/stm32f40x/drivers/gpio.c | 847 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 777 insertions(+), 70 deletions(-) diff --git a/bsp/stm32f40x/drivers/gpio.c b/bsp/stm32f40x/drivers/gpio.c index 88819f73b5..4462f2847e 100644 --- a/bsp/stm32f40x/drivers/gpio.c +++ b/bsp/stm32f40x/drivers/gpio.c @@ -1,15 +1,15 @@ /* * File : gpio.c * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * COPYRIGHT (C) 2017, RT-Thread Development Team * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * http://www.rt-thread.org/license/LICENSE * * Change Logs: - * Date Author Notes - * 2015-01-05 Bernard the first version + * Date Author Notes + * 2017-03-24 armink the first version */ #include @@ -18,6 +18,13 @@ #ifdef RT_USING_PIN +#define STM32_PIN_NUMBERS 100 //[48, 64, 100, 144 ] + +#define __STM32_PIN(index, rcc, gpio, gpio_index) { 0, RCC_##rcc##Periph_GPIO##gpio, GPIO##gpio, GPIO_Pin_##gpio_index} +#define __STM32_PIN_DEFAULT {-1, 0, 0, 0} + +#define ITEM_NUM(items) sizeof(items)/sizeof(items[0]) + /* STM32 GPIO driver */ struct pin_index { @@ -27,68 +34,413 @@ struct pin_index uint32_t pin; }; +/* STM32 GPIO irq information */ +struct pin_irq +{ + /* EXTI port source gpiox, such as EXTI_PortSourceGPIOA */ + rt_uint8_t port_source; + /* EXTI pin sources, such as EXTI_PinSource0 */ + rt_uint8_t pin_source; + /* NVIC IRQ EXTI channel, such as EXTI0_IRQn */ + enum IRQn irq_exti_channel; + /* EXTI line, such as EXTI_Line0 */ + rt_uint32_t exti_line; +}; + static const struct pin_index pins[] = { - { 0, RCC_AHB1Periph_GPIOC, GPIOC, GPIO_Pin_7}, - { 1, RCC_AHB1Periph_GPIOC, GPIOC, GPIO_Pin_6}, - { 2, RCC_AHB1Periph_GPIOC, GPIOC, GPIO_Pin_8}, - { 3, RCC_AHB1Periph_GPIOB, GPIOB, GPIO_Pin_11}, - { 4, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_14}, - { 5, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_13}, - { 6, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_11}, - { 7, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_9}, - - { 8, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_12}, - { 9, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_13}, - {10, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_14}, - {11, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_15}, - {12, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_6}, - {13, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_5}, - - {14, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_8}, - {15, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_9}, - {16, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_5}, - {17, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_6}, - {18, RCC_AHB1Periph_GPIOB, GPIOB, GPIO_Pin_6}, - {19, RCC_AHB1Periph_GPIOB, GPIOB, GPIO_Pin_7}, - {20, RCC_AHB1Periph_GPIOC, GPIOC, GPIO_Pin_9}, - {21, RCC_AHB1Periph_GPIOA, GPIOA, GPIO_Pin_8}, - - {22, RCC_AHB1Periph_GPIOC, GPIOC, GPIO_Pin_12}, - {23, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_2}, - {24, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_1}, - {25, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_0}, - {26, RCC_AHB1Periph_GPIOA, GPIOA, GPIO_Pin_9}, - {27, RCC_AHB1Periph_GPIOC, GPIOC, GPIO_Pin_13}, - {28, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_15}, - {29, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_12}, - {30, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_10}, - {31, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_8}, - {32, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_7}, - {33, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_4}, - {34, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_3}, - {35, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_2}, - {36, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_1}, - {37, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_0}, - {38, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_11}, - {39, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_10}, - {40, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_7}, - {41, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_3}, - {42, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_4}, - {43, RCC_AHB1Periph_GPIOB, GPIOB, GPIO_Pin_8}, - {44, RCC_AHB1Periph_GPIOC, GPIOC, GPIO_Pin_15}, - {45, RCC_AHB1Periph_GPIOC, GPIOC, GPIO_Pin_14}, - {46, RCC_AHB1Periph_GPIOC, GPIOC, GPIO_Pin_11}, - {47, RCC_AHB1Periph_GPIOB, GPIOB, GPIO_Pin_5}, - {48, RCC_AHB1Periph_GPIOC, GPIOC, GPIO_Pin_10}, - {49, RCC_AHB1Periph_GPIOA, GPIOA, GPIO_Pin_15}, - {50, RCC_AHB1Periph_GPIOB, GPIOB, GPIO_Pin_4}, - {51, RCC_AHB1Periph_GPIOA, GPIOA, GPIO_Pin_7}, - {52, RCC_AHB1Periph_GPIOB, GPIOB, GPIO_Pin_3}, - {53, RCC_AHB1Periph_GPIOA, GPIOA, GPIO_Pin_4}, +#if (STM32_PIN_NUMBERS == 48) + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(2, AHB1, C, 13), + __STM32_PIN(3, AHB1, C, 14), + __STM32_PIN(4, AHB1, C, 15), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(10, AHB1, A, 0), + __STM32_PIN(11, AHB1, A, 1), + __STM32_PIN(12, AHB1, A, 2), + __STM32_PIN(13, AHB1, A, 3), + __STM32_PIN(14, AHB1, A, 4), + __STM32_PIN(15, AHB1, A, 5), + __STM32_PIN(16, AHB1, A, 6), + __STM32_PIN(17, AHB1, A, 7), + __STM32_PIN(18, AHB1, B, 0), + __STM32_PIN(19, AHB1, B, 1), + __STM32_PIN(20, AHB1, B, 2), + __STM32_PIN(21, AHB1, B, 10), + __STM32_PIN(22, AHB1, B, 11), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(25, AHB1, B, 12), + __STM32_PIN(26, AHB1, B, 13), + __STM32_PIN(27, AHB1, B, 14), + __STM32_PIN(28, AHB1, B, 15), + __STM32_PIN(29, AHB1, A, 8), + __STM32_PIN(30, AHB1, A, 9), + __STM32_PIN(31, AHB1, A, 10), + __STM32_PIN(32, AHB1, A, 11), + __STM32_PIN(33, AHB1, A, 12), + __STM32_PIN(34, AHB1, A, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(37, AHB1, A, 14), + __STM32_PIN(38, AHB1, A, 15), + __STM32_PIN(39, AHB1, B, 3), + __STM32_PIN(40, AHB1, B, 4), + __STM32_PIN(41, AHB1, B, 5), + __STM32_PIN(42, AHB1, B, 6), + __STM32_PIN(43, AHB1, B, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN(45, AHB1, B, 8), + __STM32_PIN(46, AHB1, B, 9), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + +#endif +#if (STM32_PIN_NUMBERS == 64) + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(2, AHB1, C, 13), + __STM32_PIN(3, AHB1, C, 14), + __STM32_PIN(4, AHB1, C, 15), + __STM32_PIN(5, AHB1, D, 0), + __STM32_PIN(6, AHB1, D, 1), + __STM32_PIN_DEFAULT, + __STM32_PIN(8, AHB1, C, 0), + __STM32_PIN(9, AHB1, C, 1), + __STM32_PIN(10, AHB1, C, 2), + __STM32_PIN(11, AHB1, C, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(14, AHB1, A, 0), + __STM32_PIN(15, AHB1, A, 1), + __STM32_PIN(16, AHB1, A, 2), + __STM32_PIN(17, AHB1, A, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(20, AHB1, A, 4), + __STM32_PIN(21, AHB1, A, 5), + __STM32_PIN(22, AHB1, A, 6), + __STM32_PIN(23, AHB1, A, 7), + __STM32_PIN(24, AHB1, C, 4), + __STM32_PIN(25, AHB1, C, 5), + __STM32_PIN(26, AHB1, B, 0), + __STM32_PIN(27, AHB1, B, 1), + __STM32_PIN(28, AHB1, B, 2), + __STM32_PIN(29, AHB1, B, 10), + __STM32_PIN(30, AHB1, B, 11), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(33, AHB1, B, 12), + __STM32_PIN(34, AHB1, B, 13), + __STM32_PIN(35, AHB1, B, 14), + __STM32_PIN(36, AHB1, B, 15), + __STM32_PIN(37, AHB1, C, 6), + __STM32_PIN(38, AHB1, C, 7), + __STM32_PIN(39, AHB1, C, 8), + __STM32_PIN(40, AHB1, C, 9), + __STM32_PIN(41, AHB1, A, 8), + __STM32_PIN(42, AHB1, A, 9), + __STM32_PIN(43, AHB1, A, 10), + __STM32_PIN(44, AHB1, A, 11), + __STM32_PIN(45, AHB1, A, 12), + __STM32_PIN(46, AHB1, A, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(49, AHB1, A, 14), + __STM32_PIN(50, AHB1, A, 15), + __STM32_PIN(51, AHB1, C, 10), + __STM32_PIN(52, AHB1, C, 11), + __STM32_PIN(53, AHB1, C, 12), + __STM32_PIN(54, AHB1, D, 2), + __STM32_PIN(55, AHB1, B, 3), + __STM32_PIN(56, AHB1, B, 4), + __STM32_PIN(57, AHB1, B, 5), + __STM32_PIN(58, AHB1, B, 6), + __STM32_PIN(59, AHB1, B, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN(61, AHB1, B, 8), + __STM32_PIN(62, AHB1, B, 9), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, +#endif +#if (STM32_PIN_NUMBERS == 100) + __STM32_PIN_DEFAULT, + __STM32_PIN(1, AHB1, E, 2), + __STM32_PIN(2, AHB1, E, 3), + __STM32_PIN(3, AHB1, E, 4), + __STM32_PIN(4, AHB1, E, 5), + __STM32_PIN(5, AHB1, E, 6), + __STM32_PIN_DEFAULT, + __STM32_PIN(7, AHB1, C, 13), + __STM32_PIN(8, AHB1, C, 14), + __STM32_PIN(9, AHB1, C, 15), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(15, AHB1, C, 0), + __STM32_PIN(16, AHB1, C, 1), + __STM32_PIN(17, AHB1, C, 2), + __STM32_PIN(18, AHB1, C, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(23, AHB1, A, 0), + __STM32_PIN(24, AHB1, A, 1), + __STM32_PIN(25, AHB1, A, 2), + __STM32_PIN(26, AHB1, A, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(29, AHB1, A, 4), + __STM32_PIN(30, AHB1, A, 5), + __STM32_PIN(31, AHB1, A, 6), + __STM32_PIN(32, AHB1, A, 7), + __STM32_PIN(33, AHB1, C, 4), + __STM32_PIN(34, AHB1, C, 5), + __STM32_PIN(35, AHB1, B, 0), + __STM32_PIN(36, AHB1, B, 1), + __STM32_PIN(37, AHB1, B, 2), + __STM32_PIN(38, AHB1, E, 7), + __STM32_PIN(39, AHB1, E, 8), + __STM32_PIN(40, AHB1, E, 9), + __STM32_PIN(41, AHB1, E, 10), + __STM32_PIN(42, AHB1, E, 11), + __STM32_PIN(43, AHB1, E, 12), + __STM32_PIN(44, AHB1, E, 13), + __STM32_PIN(45, AHB1, E, 14), + __STM32_PIN(46, AHB1, E, 15), + __STM32_PIN(47, AHB1, B, 10), + __STM32_PIN(48, AHB1, B, 11), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(51, AHB1, B, 12), + __STM32_PIN(52, AHB1, B, 13), + __STM32_PIN(53, AHB1, B, 14), + __STM32_PIN(54, AHB1, B, 15), + __STM32_PIN(55, AHB1, D, 8), + __STM32_PIN(56, AHB1, D, 9), + __STM32_PIN(57, AHB1, D, 10), + __STM32_PIN(58, AHB1, D, 11), + __STM32_PIN(59, AHB1, D, 12), + __STM32_PIN(60, AHB1, D, 13), + __STM32_PIN(61, AHB1, D, 14), + __STM32_PIN(62, AHB1, D, 15), + __STM32_PIN(63, AHB1, C, 6), + __STM32_PIN(64, AHB1, C, 7), + __STM32_PIN(65, AHB1, C, 8), + __STM32_PIN(66, AHB1, C, 9), + __STM32_PIN(67, AHB1, A, 8), + __STM32_PIN(68, AHB1, A, 9), + __STM32_PIN(69, AHB1, A, 10), + __STM32_PIN(70, AHB1, A, 11), + __STM32_PIN(71, AHB1, A, 12), + __STM32_PIN(72, AHB1, A, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(76, AHB1, A, 14), + __STM32_PIN(77, AHB1, A, 15), + __STM32_PIN(78, AHB1, C, 10), + __STM32_PIN(79, AHB1, C, 11), + __STM32_PIN(80, AHB1, C, 12), + __STM32_PIN(81, AHB1, D, 0), + __STM32_PIN(82, AHB1, D, 1), + __STM32_PIN(83, AHB1, D, 2), + __STM32_PIN(84, AHB1, D, 3), + __STM32_PIN(85, AHB1, D, 4), + __STM32_PIN(86, AHB1, D, 5), + __STM32_PIN(87, AHB1, D, 6), + __STM32_PIN(88, AHB1, D, 7), + __STM32_PIN(89, AHB1, B, 3), + __STM32_PIN(90, AHB1, B, 4), + __STM32_PIN(91, AHB1, B, 5), + __STM32_PIN(92, AHB1, B, 6), + __STM32_PIN(93, AHB1, B, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN(95, AHB1, B, 8), + __STM32_PIN(96, AHB1, B, 9), + __STM32_PIN(97, AHB1, E, 0), + __STM32_PIN(98, AHB1, E, 1), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, +#endif +#if (STM32_PIN_NUMBERS == 144) + __STM32_PIN_DEFAULT, + __STM32_PIN(1, AHB1, E, 2), + __STM32_PIN(2, AHB1, E, 3), + __STM32_PIN(3, AHB1, E, 4), + __STM32_PIN(4, AHB1, E, 5), + __STM32_PIN(5, AHB1, E, 6), + __STM32_PIN_DEFAULT, + __STM32_PIN(7, AHB1, C, 13), + __STM32_PIN(8, AHB1, C, 14), + __STM32_PIN(9, AHB1, C, 15), + + __STM32_PIN(10, AHB1, F, 0), + __STM32_PIN(11, AHB1, F, 1), + __STM32_PIN(12, AHB1, F, 2), + __STM32_PIN(13, AHB1, F, 3), + __STM32_PIN(14, AHB1, F, 4), + __STM32_PIN(15, AHB1, F, 5), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(18, AHB1, F, 6), + __STM32_PIN(19, AHB1, F, 7), + __STM32_PIN(20, AHB1, F, 8), + __STM32_PIN(21, AHB1, F, 9), + __STM32_PIN(22, AHB1, F, 10), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(26, AHB1, C, 0), + __STM32_PIN(27, AHB1, C, 1), + __STM32_PIN(28, AHB1, C, 2), + __STM32_PIN(29, AHB1, C, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(34, AHB1, A, 0), + __STM32_PIN(35, AHB1, A, 1), + __STM32_PIN(36, AHB1, A, 2), + __STM32_PIN(37, AHB1, A, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(40, AHB1, A, 4), + __STM32_PIN(41, AHB1, A, 5), + __STM32_PIN(42, AHB1, A, 6), + __STM32_PIN(43, AHB1, A, 7), + __STM32_PIN(44, AHB1, C, 4), + __STM32_PIN(45, AHB1, C, 5), + __STM32_PIN(46, AHB1, B, 0), + __STM32_PIN(47, AHB1, B, 1), + __STM32_PIN(48, AHB1, B, 2), + __STM32_PIN(49, AHB1, F, 11), + __STM32_PIN(50, AHB1, F, 12), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(53, AHB1, F, 13), + __STM32_PIN(54, AHB1, F, 14), + __STM32_PIN(55, AHB1, F, 15), + __STM32_PIN(56, AHB1, G, 0), + __STM32_PIN(57, AHB1, G, 1), + __STM32_PIN(58, AHB1, E, 7), + __STM32_PIN(59, AHB1, E, 8), + __STM32_PIN(60, AHB1, E, 9), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(63, AHB1, E, 10), + __STM32_PIN(64, AHB1, E, 11), + __STM32_PIN(65, AHB1, E, 12), + __STM32_PIN(66, AHB1, E, 13), + __STM32_PIN(67, AHB1, E, 14), + __STM32_PIN(68, AHB1, E, 15), + __STM32_PIN(69, AHB1, B, 10), + __STM32_PIN(70, AHB1, B, 11), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(73, AHB1, B, 12), + __STM32_PIN(74, AHB1, B, 13), + __STM32_PIN(75, AHB1, B, 14), + __STM32_PIN(76, AHB1, B, 15), + __STM32_PIN(77, AHB1, D, 8), + __STM32_PIN(78, AHB1, D, 9), + __STM32_PIN(79, AHB1, D, 10), + __STM32_PIN(80, AHB1, D, 11), + __STM32_PIN(81, AHB1, D, 12), + __STM32_PIN(82, AHB1, D, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(85, AHB1, D, 14), + __STM32_PIN(86, AHB1, D, 15), + __STM32_PIN(87, AHB1, G, 2), + __STM32_PIN(88, AHB1, G, 3), + __STM32_PIN(89, AHB1, G, 4), + __STM32_PIN(90, AHB1, G, 5), + __STM32_PIN(91, AHB1, G, 6), + __STM32_PIN(92, AHB1, G, 7), + __STM32_PIN(93, AHB1, G, 8), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(96, AHB1, C, 6), + __STM32_PIN(97, AHB1, C, 7), + __STM32_PIN(98, AHB1, C, 8), + __STM32_PIN(99, AHB1, C, 9), + __STM32_PIN(100, AHB1, A, 8), + __STM32_PIN(101, AHB1, A, 9), + __STM32_PIN(102, AHB1, A, 10), + __STM32_PIN(103, AHB1, A, 11), + __STM32_PIN(104, AHB1, A, 12), + __STM32_PIN(105, AHB1, A, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(109, AHB1, A, 14), + __STM32_PIN(110, AHB1, A, 15), + __STM32_PIN(111, AHB1, C, 10), + __STM32_PIN(112, AHB1, C, 11), + __STM32_PIN(113, AHB1, C, 12), + __STM32_PIN(114, AHB1, D, 0), + __STM32_PIN(115, AHB1, D, 1), + __STM32_PIN(116, AHB1, D, 2), + __STM32_PIN(117, AHB1, D, 3), + __STM32_PIN(118, AHB1, D, 4), + __STM32_PIN(119, AHB1, D, 5), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(122, AHB1, D, 6), + __STM32_PIN(123, AHB1, D, 7), + __STM32_PIN(124, AHB1, G, 9), + __STM32_PIN(125, AHB1, G, 10), + __STM32_PIN(126, AHB1, G, 11), + __STM32_PIN(127, AHB1, G, 12), + __STM32_PIN(128, AHB1, G, 13), + __STM32_PIN(129, AHB1, G, 14), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(132, AHB1, G, 15), + __STM32_PIN(133, AHB1, B, 3), + __STM32_PIN(134, AHB1, B, 4), + __STM32_PIN(135, AHB1, B, 5), + __STM32_PIN(136, AHB1, B, 6), + __STM32_PIN(137, AHB1, B, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN(139, AHB1, B, 8), + __STM32_PIN(140, AHB1, B, 9), + __STM32_PIN(141, AHB1, E, 0), + __STM32_PIN(142, AHB1, E, 1), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, +#endif +}; + +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, }; -#define ITEM_NUM(items) sizeof(items)/sizeof(items[0]) const struct pin_index *get_pin(uint8_t pin) { const struct pin_index *index; @@ -96,6 +448,8 @@ const struct pin_index *get_pin(uint8_t pin) if (pin < ITEM_NUM(pins)) { index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; } else { @@ -165,15 +519,15 @@ void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) RCC_AHB1PeriphClockCmd(index->rcc, ENABLE); /* Configure GPIO_InitStructure */ - GPIO_InitStructure.GPIO_Pin = index->pin; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_Pin = index->pin; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; if (mode == PIN_MODE_OUTPUT) { /* output setting */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; } else if (mode == PIN_MODE_INPUT) { @@ -187,27 +541,380 @@ void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; } - else + else if (mode == PIN_MODE_INPUT_PULLDOWN) { - /* input setting:default. */ + /* input setting: pull down. */ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: open drain */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; + } + else + { + /* error mode */ + RT_ASSERT(0); + } GPIO_Init(index->gpio, &GPIO_InitStructure); } +rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) +{ + int i; + for (i = 0; i < 32; i++) + { + if ((1UL << i) == bit) + { + return i; + } + } + return -1; +} + +rt_inline rt_int32_t bitno2bit(rt_uint32_t bitno) +{ + if (bitno <= 32) + { + return 1UL << bitno; + } + else + { + return 0; + } +} + +static const struct pin_irq *get_pin_irq(uint16_t pin) +{ + static struct pin_irq irq; + const struct pin_index *index; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_NULL; + } + + irq.exti_line = index->pin; + irq.pin_source = bit2bitno(index->pin); + irq.port_source = ((uint32_t)index->gpio - GPIOA_BASE) / (GPIOB_BASE - GPIOA_BASE); + switch (irq.pin_source) + { + case 0 : irq.irq_exti_channel = EXTI0_IRQn;break; + case 1 : irq.irq_exti_channel = EXTI1_IRQn;break; + case 2 : irq.irq_exti_channel = EXTI2_IRQn;break; + case 3 : irq.irq_exti_channel = EXTI3_IRQn;break; + case 4 : irq.irq_exti_channel = EXTI4_IRQn;break; + case 5 : + case 6 : + case 7 : + case 8 : + case 9 : irq.irq_exti_channel = EXTI9_5_IRQn;break; + case 10 : + case 11 : + case 12 : + case 13 : + case 14 : + case 15 : irq.irq_exti_channel = EXTI15_10_IRQn;break; + default : return RT_NULL; + } + + return &irq; +}; + +rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + const struct pin_index *index; + rt_base_t level; + + rt_int32_t irqindex = -1; + index = get_pin(pin); + if (index == RT_NULL) + { + return -RT_ENOSYS; + } + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)) + { + return -RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args + ) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return -RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + //TODO PA1 will overwrite PB1's hdr, using rt_list ? + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +rt_err_t stm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return -RT_ENOSYS; + } + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)) + { + return -RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) +{ + const struct pin_index *index; + const struct pin_irq *irq; + rt_base_t level; + rt_int32_t irqindex = -1; + NVIC_InitTypeDef NVIC_InitStructure; + EXTI_InitTypeDef EXTI_InitStructure; + + index = get_pin(pin); + if (index == RT_NULL) + { + return -RT_ENOSYS; + } + if (enabled == PIN_IRQ_ENABLE) + { + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_hdr_tab)) + { + return -RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return -RT_ENOSYS; + } + + irq = get_pin_irq(pin); + if (irq == RT_NULL) + { + rt_hw_interrupt_enable(level); + return -RT_ENOSYS; + } + /* select the input source pin for the EXTI line */ + SYSCFG_EXTILineConfig(irq->port_source, irq->pin_source); + /* select the mode(interrupt, event) and configure the trigger selection */ + EXTI_InitStructure.EXTI_Line = irq->exti_line; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + break; + case PIN_IRQ_MODE_FALLING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; + break; + case PIN_IRQ_MODE_RISING_FALLING: + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling; + break; + } + EXTI_InitStructure.EXTI_LineCmd = ENABLE; + EXTI_Init(&EXTI_InitStructure); + /* configure NVIC IRQ channel mapped to the EXTI line */ + NVIC_InitStructure.NVIC_IRQChannel = irq->irq_exti_channel; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + irq = get_pin_irq(index->pin); + if (irq == RT_NULL) + { + return -RT_ENOSYS; + } + EXTI_InitStructure.EXTI_Line = irq->exti_line; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + EXTI_InitStructure.EXTI_LineCmd = DISABLE; + EXTI_Init(&EXTI_InitStructure); + } + else + { + return -RT_ENOSYS; + } + + return RT_EOK; +} const static struct rt_pin_ops _stm32_pin_ops = { stm32_pin_mode, stm32_pin_write, stm32_pin_read, + stm32_pin_attach_irq, + stm32_pin_dettach_irq, + stm32_pin_irq_enable, }; int stm32_hw_pin_init(void) { - rt_device_pin_register("pin", &_stm32_pin_ops, RT_NULL); - return 0; + int result; + + /* enable SYSCFG clock for EXTI */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + + result = rt_device_pin_register("pin", &_stm32_pin_ops, RT_NULL); + return result; } INIT_BOARD_EXPORT(stm32_hw_pin_init); +rt_inline void pin_irq_hdr(int irqno) +{ + EXTI_ClearITPendingBit(bitno2bit(irqno)); + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + +void EXTI0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(0); + /* leave interrupt */ + rt_interrupt_leave(); +} + +void EXTI1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(1); + /* leave interrupt */ + rt_interrupt_leave(); +} + +void EXTI2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(2); + /* leave interrupt */ + rt_interrupt_leave(); +} + +void EXTI3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(3); + /* leave interrupt */ + rt_interrupt_leave(); +} + +void EXTI4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(4); + /* leave interrupt */ + rt_interrupt_leave(); +} + +void EXTI9_5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + if (EXTI_GetITStatus(EXTI_Line5) != RESET) + { + pin_irq_hdr(5); + } + if (EXTI_GetITStatus(EXTI_Line6) != RESET) + { + pin_irq_hdr(6); + } + if (EXTI_GetITStatus(EXTI_Line7) != RESET) + { + pin_irq_hdr(7); + } + if (EXTI_GetITStatus(EXTI_Line8) != RESET) + { + pin_irq_hdr(8); + } + if (EXTI_GetITStatus(EXTI_Line9) != RESET) + { + pin_irq_hdr(9); + } + /* leave interrupt */ + rt_interrupt_leave(); +} + +void EXTI15_10_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + if (EXTI_GetITStatus(EXTI_Line10) != RESET) + { + pin_irq_hdr(10); + } + if (EXTI_GetITStatus(EXTI_Line11) != RESET) + { + pin_irq_hdr(11); + } + if (EXTI_GetITStatus(EXTI_Line12) != RESET) + { + pin_irq_hdr(12); + } + if (EXTI_GetITStatus(EXTI_Line13) != RESET) + { + pin_irq_hdr(13); + } + if (EXTI_GetITStatus(EXTI_Line14) != RESET) + { + pin_irq_hdr(14); + } + if (EXTI_GetITStatus(EXTI_Line15) != RESET) + { + pin_irq_hdr(15); + } + /* leave interrupt */ + rt_interrupt_leave(); +} + #endif -- cgit v1.3.1 From 045f6c368c70ef5111764a21f0984bd5c3e00a69 Mon Sep 17 00:00:00 2001 From: armink Date: Tue, 7 Nov 2017 20:53:33 +0800 Subject: [BSP] Fix stm32f10x BSP error code. --- bsp/stm32f10x/drivers/gpio.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/bsp/stm32f10x/drivers/gpio.c b/bsp/stm32f10x/drivers/gpio.c index fd64151b7b..abb62311a9 100755 --- a/bsp/stm32f10x/drivers/gpio.c +++ b/bsp/stm32f10x/drivers/gpio.c @@ -16,8 +16,6 @@ #include #include #include -#include -#include #ifdef RT_USING_PIN @@ -591,12 +589,12 @@ rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, index = get_pin(pin); if (index == RT_NULL) { - return RT_ENOSYS; + return -RT_ENOSYS; } irqindex = bit2bitno(index->pin); if(irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) { - return RT_ENOSYS; + return -RT_ENOSYS; } level = rt_hw_interrupt_disable(); @@ -612,7 +610,7 @@ rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, if(pin_irq_hdr_tab[irqindex].pin != -1) { rt_hw_interrupt_enable(level); - return RT_EBUSY; + return -RT_EBUSY; } pin_irq_hdr_tab[irqindex].pin = pin; pin_irq_hdr_tab[irqindex].hdr = hdr; @@ -631,12 +629,12 @@ rt_err_t stm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin) index = get_pin(pin); if (index == RT_NULL) { - return RT_ENOSYS; + return -RT_ENOSYS; } irqindex = bit2bitno(index->pin); if(irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) { - return RT_ENOSYS; + return -RT_ENOSYS; } level = rt_hw_interrupt_disable(); @@ -667,20 +665,20 @@ rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, index = get_pin(pin); if (index == RT_NULL) { - return RT_ENOSYS; + return -RT_ENOSYS; } if(enabled == PIN_IRQ_ENABLE) { irqindex = bit2bitno(index->pin); if(irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) { - return RT_ENOSYS; + return -RT_ENOSYS; } level = rt_hw_interrupt_disable(); if(pin_irq_hdr_tab[irqindex].pin == -1) { rt_hw_interrupt_enable(level); - return RT_ENOSYS; + return -RT_ENOSYS; } irqmap = &pin_irq_map[irqindex]; /* GPIO Periph clock enable */ @@ -720,7 +718,7 @@ rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, irqmap = get_pin_irq_map(index->pin); if(irqmap == RT_NULL) { - return RT_ENOSYS; + return -RT_ENOSYS; } EXTI_InitStructure.EXTI_Line = irqmap->irqbit; EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; @@ -730,7 +728,7 @@ rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, } else { - return RT_ENOSYS; + return -RT_ENOSYS; } return RT_EOK; -- cgit v1.3.1 From 4dfabdcb0a202317ca223cf6675224ecb008c83e Mon Sep 17 00:00:00 2001 From: SummerGift Date: Thu, 9 Nov 2017 11:12:26 +0800 Subject: add components/libc/compilers/armlibc/dirent.h --- components/libc/compilers/armlibc/dirent.h | 54 ++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 components/libc/compilers/armlibc/dirent.h diff --git a/components/libc/compilers/armlibc/dirent.h b/components/libc/compilers/armlibc/dirent.h new file mode 100644 index 0000000000..1adf952031 --- /dev/null +++ b/components/libc/compilers/armlibc/dirent.h @@ -0,0 +1,54 @@ +#ifndef __RTT_DIRENT_H__ +#define __RTT_DIRENT_H__ + +#include +#include + +/* +* dirent.h - format of directory entries + * Ref: http://www.opengroup.org/onlinepubs/009695399/basedefs/dirent.h.html + */ + +/* File types */ +#define FT_REGULAR 0 /* regular file */ +#define FT_SOCKET 1 /* socket file */ +#define FT_DIRECTORY 2 /* directory */ +#define FT_USER 3 /* user defined */ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef HAVE_DIR_STRUCTURE +typedef struct +{ + int fd; /* directory file */ + char buf[512]; + int num; + int cur; +} DIR; +#endif + +#ifndef HAVE_DIRENT_STRUCTURE +struct dirent +{ + rt_uint8_t d_type; /* The type of the file */ + rt_uint8_t d_namlen; /* The length of the not including the terminating null file name */ + rt_uint16_t d_reclen; /* length of this record */ + char d_name[256]; /* The null-terminated file name */ +}; +#endif + +int closedir(DIR *); +DIR *opendir(const char *); +struct dirent *readdir(DIR *); +int readdir_r(DIR *, struct dirent *, struct dirent **); +void rewinddir(DIR *); +void seekdir(DIR *, long int); +long telldir(DIR *); + +#ifdef __cplusplus +} +#endif + +#endif -- cgit v1.3.1 From 024e3ea8f692fd7ecd9c36dad544fd69ea70c4bd Mon Sep 17 00:00:00 2001 From: MurphyZhao Date: Thu, 9 Nov 2017 11:57:11 +0800 Subject: [Fix] Fix issue caused by global info and local info in wlan/wlan_cmd.c [Add] Change network_mode value according to the finsh shell command --- components/drivers/wlan/wlan_cmd.c | 69 ++++++++++++++++++-------------------- 1 file changed, 33 insertions(+), 36 deletions(-) diff --git a/components/drivers/wlan/wlan_cmd.c b/components/drivers/wlan/wlan_cmd.c index 2ff0db903d..273061fada 100644 --- a/components/drivers/wlan/wlan_cmd.c +++ b/components/drivers/wlan/wlan_cmd.c @@ -41,8 +41,11 @@ struct rt_wlan_info info; #define WIFI_SETTING_FN "/appfs/setting.json" #endif -#ifndef WIFI_DEVICE_NAME -#define WIFI_DEVICE_NAME "w0" +#ifndef WIFI_DEVICE_STA_NAME +#define WIFI_DEVICE_STA_NAME "w0" +#endif +#ifndef WIFI_DEVICE_AP_NAME +#define WIFI_DEVICE_AP_NAME "ap" #endif #ifdef RT_USING_DFS @@ -304,53 +307,43 @@ int wifi_default(void) /* read default setting for wifi */ wifi_read_cfg(WIFI_SETTING_FN); - /* get wlan device */ - wlan = (struct rt_wlan_device*)rt_device_find(WIFI_DEVICE_NAME); - if (!wlan) - { - rt_kprintf("no wlan:%s device\n", WIFI_DEVICE_NAME); - return -1; - } - if (network_mode == WIFI_STATION) { - struct rt_wlan_info *info; - - info = (struct rt_wlan_info *)rt_malloc (sizeof(struct rt_wlan_info)); - if (!info) + /* get wlan device */ + wlan = (struct rt_wlan_device*)rt_device_find(WIFI_DEVICE_STA_NAME); + if (!wlan) { - rt_kprintf("wifi: out of memory\n"); + rt_kprintf("no wlan:%s device\n", WIFI_DEVICE_STA_NAME); return -1; } /* wifi station */ - rt_wlan_info_init(info, WIFI_STATION, SECURITY_WPA2_MIXED_PSK, wifi_ssid); + rt_wlan_info_init(&info, WIFI_STATION, SECURITY_WPA2_MIXED_PSK, wifi_ssid); result =rt_wlan_init(wlan, WIFI_STATION); if (result == RT_EOK) { - result = rt_wlan_connect(wlan, info, wifi_key); + result = rt_wlan_connect(wlan, &info, wifi_key); } } else { /* wifi AP */ - struct rt_wlan_info *info; - - info = (struct rt_wlan_info *)rt_malloc (sizeof(struct rt_wlan_info)); - if (!info) + /* get wlan device */ + wlan = (struct rt_wlan_device*)rt_device_find(WIFI_DEVICE_AP_NAME); + if (!wlan) { - rt_kprintf("wifi: out of memory\n"); + rt_kprintf("no wlan:%s device\n", WIFI_DEVICE_AP_NAME); return -1; } - rt_wlan_info_init(info, WIFI_AP, SECURITY_WPA2_AES_PSK, wifi_ssid); - info->channel = 11; + rt_wlan_info_init(&info, WIFI_AP, SECURITY_WPA2_AES_PSK, wifi_ssid); + info.channel = 11; /* wifi soft-AP */ result =rt_wlan_init(wlan, WIFI_AP); if (result == RT_EOK) { - result = rt_wlan_softap(wlan, info, wifi_key); + result = rt_wlan_softap(wlan, &info, wifi_key); } } @@ -417,6 +410,7 @@ int wifi(int argc, char** argv) if (strcmp(argv[2], "join") == 0) { rt_wlan_init(wlan, WIFI_STATION); + network_mode = WIFI_STATION; /* TODO: use easy-join to replace */ rt_wlan_info_init(&info, WIFI_STATION, SECURITY_WPA2_MIXED_PSK, argv[3]); @@ -471,34 +465,37 @@ int wifi(int argc, char** argv) else if (strcmp(argv[2], "ap") == 0) { rt_err_t result = RT_EOK; - struct rt_wlan_info *info; - info = (struct rt_wlan_info*)rt_malloc(sizeof(struct rt_wlan_info)); if (argc == 4) { // open soft-AP - rt_wlan_info_init(info, WIFI_AP, SECURITY_OPEN, argv[3]); - info->channel = 11; + rt_wlan_info_init(&info, WIFI_AP, SECURITY_OPEN, argv[3]); + info.channel = 11; result =rt_wlan_init(wlan, WIFI_AP); /* start soft ap */ - result = rt_wlan_softap(wlan, info, NULL); + result = rt_wlan_softap(wlan, &info, NULL); + if (result == RT_EOK) + { + network_mode = WIFI_AP; + } } else if (argc == 5) { // WPA2 with password - rt_wlan_info_init(info, WIFI_AP, SECURITY_WPA2_AES_PSK, argv[3]); - info->channel = 11; + rt_wlan_info_init(&info, WIFI_AP, SECURITY_WPA2_AES_PSK, argv[3]); + info.channel = 11; result =rt_wlan_init(wlan, WIFI_AP); /* start soft ap */ - result = rt_wlan_softap(wlan, info, argv[4]); + result = rt_wlan_softap(wlan, &info, argv[4]); + if (result == RT_EOK) + { + network_mode = WIFI_AP; + } } else { - /* release information */ - rt_free(info); - wifi_usage(); } -- cgit v1.3.1