From 0f33da3f0e222461e505a933f4d66b328f10479a Mon Sep 17 00:00:00 2001 From: misonyo Date: Sat, 27 Apr 2019 17:35:46 +0800 Subject: [libcpu/cortex-m7]add cache driver --- bsp/imxrt/Libraries/imxrt1021/drivers/SConscript | 1 - bsp/imxrt/Libraries/imxrt1021/drivers/drv_cache.c | 71 ------------------ bsp/imxrt/Libraries/imxrt1050/drivers/SConscript | 1 - bsp/imxrt/Libraries/imxrt1050/drivers/drv_cache.c | 71 ------------------ libcpu/arm/cortex-m7/cpu_cache.c | 89 +++++++++++++++++++++++ 5 files changed, 89 insertions(+), 144 deletions(-) delete mode 100644 bsp/imxrt/Libraries/imxrt1021/drivers/drv_cache.c delete mode 100644 bsp/imxrt/Libraries/imxrt1050/drivers/drv_cache.c create mode 100644 libcpu/arm/cortex-m7/cpu_cache.c diff --git a/bsp/imxrt/Libraries/imxrt1021/drivers/SConscript b/bsp/imxrt/Libraries/imxrt1021/drivers/SConscript index db25271739..b8cd9401cd 100644 --- a/bsp/imxrt/Libraries/imxrt1021/drivers/SConscript +++ b/bsp/imxrt/Libraries/imxrt1021/drivers/SConscript @@ -5,7 +5,6 @@ cwd = GetCurrentDir() # add the general drivers. src = Split(""" drv_uart.c -drv_cache.c """) CPPPATH = [cwd] diff --git a/bsp/imxrt/Libraries/imxrt1021/drivers/drv_cache.c b/bsp/imxrt/Libraries/imxrt1021/drivers/drv_cache.c deleted file mode 100644 index 4f88e769c4..0000000000 --- a/bsp/imxrt/Libraries/imxrt1021/drivers/drv_cache.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-04-02 tanek first implementation - */ - -#include -#include -#include - -void rt_hw_cpu_icache_enable(void) -{ - SCB_EnableICache(); -} - -void rt_hw_cpu_icache_disable(void) -{ - SCB_DisableICache(); -} - -rt_base_t rt_hw_cpu_icache_status(void) -{ - return 0; -} - -void rt_hw_cpu_icache_ops(int ops, void* addr, int size) -{ - if (ops & RT_HW_CACHE_INVALIDATE) - { - ICACHE_InvalidateByRange((uint32_t)addr, size); - } -} - -void rt_hw_cpu_dcache_enable(void) -{ - SCB_EnableDCache(); -} - -void rt_hw_cpu_dcache_disable(void) -{ - SCB_DisableDCache(); -} - -rt_base_t rt_hw_cpu_dcache_status(void) -{ - return 0; -} - -void rt_hw_cpu_dcache_ops(int ops, void* addr, int size) -{ - if (ops & (RT_HW_CACHE_FLUSH | RT_HW_CACHE_INVALIDATE)) - { - DCACHE_CleanInvalidateByRange((uint32_t)addr, size); - } - else if (ops & RT_HW_CACHE_FLUSH) - { - DCACHE_CleanByRange((uint32_t)addr, size); - } - else if (ops & RT_HW_CACHE_INVALIDATE) - { - DCACHE_InvalidateByRange((uint32_t)addr, size); - } - else - { - RT_ASSERT(0); - } -} diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript b/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript index d22ab2b10a..8a322f88f3 100644 --- a/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript +++ b/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript @@ -5,7 +5,6 @@ cwd = GetCurrentDir() # add the general drivers. src = Split(""" drv_uart.c -drv_cache.c """) CPPPATH = [cwd] diff --git a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_cache.c b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_cache.c deleted file mode 100644 index 4f88e769c4..0000000000 --- a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_cache.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-04-02 tanek first implementation - */ - -#include -#include -#include - -void rt_hw_cpu_icache_enable(void) -{ - SCB_EnableICache(); -} - -void rt_hw_cpu_icache_disable(void) -{ - SCB_DisableICache(); -} - -rt_base_t rt_hw_cpu_icache_status(void) -{ - return 0; -} - -void rt_hw_cpu_icache_ops(int ops, void* addr, int size) -{ - if (ops & RT_HW_CACHE_INVALIDATE) - { - ICACHE_InvalidateByRange((uint32_t)addr, size); - } -} - -void rt_hw_cpu_dcache_enable(void) -{ - SCB_EnableDCache(); -} - -void rt_hw_cpu_dcache_disable(void) -{ - SCB_DisableDCache(); -} - -rt_base_t rt_hw_cpu_dcache_status(void) -{ - return 0; -} - -void rt_hw_cpu_dcache_ops(int ops, void* addr, int size) -{ - if (ops & (RT_HW_CACHE_FLUSH | RT_HW_CACHE_INVALIDATE)) - { - DCACHE_CleanInvalidateByRange((uint32_t)addr, size); - } - else if (ops & RT_HW_CACHE_FLUSH) - { - DCACHE_CleanByRange((uint32_t)addr, size); - } - else if (ops & RT_HW_CACHE_INVALIDATE) - { - DCACHE_InvalidateByRange((uint32_t)addr, size); - } - else - { - RT_ASSERT(0); - } -} diff --git a/libcpu/arm/cortex-m7/cpu_cache.c b/libcpu/arm/cortex-m7/cpu_cache.c new file mode 100644 index 0000000000..4a1a9c2201 --- /dev/null +++ b/libcpu/arm/cortex-m7/cpu_cache.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-04-02 tanek first implementation + * 2019-04-27 misonyo update to cortex-m7 series + */ + +#include +#include +#include + +/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */ +#define L1CACHE_LINESIZE_BYTE (32) + +void rt_hw_cpu_icache_enable(void) +{ + SCB_EnableICache(); +} + +void rt_hw_cpu_icache_disable(void) +{ + SCB_DisableICache(); +} + +rt_base_t rt_hw_cpu_icache_status(void) +{ + return 0; +} + +void rt_hw_cpu_icache_ops(int ops, void* addr, int size) +{ + rt_uint32_t address = (rt_uint32_t)addr & (rt_uint32_t) ~(L1CACHE_LINESIZE_BYTE - 1); + rt_int32_t size_byte = size + address - (rt_uint32_t)addr; + rt_uint32_t linesize = 32U; + if (ops & RT_HW_CACHE_INVALIDATE) + { + __DSB(); + while (size_byte > 0) + { + SCB->ICIMVAU = address; + address += linesize; + size_byte -= linesize; + } + __DSB(); + __ISB(); + } +} + +void rt_hw_cpu_dcache_enable(void) +{ + SCB_EnableDCache(); +} + +void rt_hw_cpu_dcache_disable(void) +{ + SCB_DisableDCache(); +} + +rt_base_t rt_hw_cpu_dcache_status(void) +{ + return 0; +} + +void rt_hw_cpu_dcache_ops(int ops, void* addr, int size) +{ + rt_uint32_t startAddr = (rt_uint32_t)addr & (rt_uint32_t)~(L1CACHE_LINESIZE_BYTE - 1); + rt_uint32_t size_byte = size + (rt_uint32_t)addr - startAddr; + + if (ops & (RT_HW_CACHE_FLUSH | RT_HW_CACHE_INVALIDATE)) + { + SCB_CleanInvalidateDCache_by_Addr((rt_uint32_t *)startAddr, size_byte); + } + else if (ops & RT_HW_CACHE_FLUSH) + { + SCB_CleanDCache_by_Addr((rt_uint32_t *)startAddr, size_byte); + } + else if (ops & RT_HW_CACHE_INVALIDATE) + { + SCB_InvalidateDCache_by_Addr((rt_uint32_t *)startAddr, size_byte); + } + else + { + RT_ASSERT(0); + } +} -- cgit v1.3.1