From 79771e42e7f638587bb34cdabbeb7eba850c0ee8 Mon Sep 17 00:00:00 2001 From: wanghaijing Date: Wed, 28 Apr 2021 14:26:43 +0800 Subject: [rename] stm32f767-fire-challenger-v1 --- .github/workflows/action.yml | 2 +- bsp/stm32/README.md | 2 +- bsp/stm32/stm32f767-atk-apollo/README.md | 2 +- bsp/stm32/stm32f767-atk-apollo/board/Kconfig | 15 - bsp/stm32/stm32f767-fire-challenger-v1/.config | 590 ++++ bsp/stm32/stm32f767-fire-challenger-v1/.gitignore | 42 + bsp/stm32/stm32f767-fire-challenger-v1/Kconfig | 21 + bsp/stm32/stm32f767-fire-challenger-v1/README.md | 131 + bsp/stm32/stm32f767-fire-challenger-v1/SConscript | 15 + bsp/stm32/stm32f767-fire-challenger-v1/SConstruct | 60 + .../applications/SConscript | 12 + .../applications/main.c | 30 + .../board/CubeMX_Config/.mxproject | 13 + .../board/CubeMX_Config/CubeMX_Config.ioc | 516 ++++ .../board/CubeMX_Config/Inc/main.h | 91 + .../board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h | 458 ++++ .../board/CubeMX_Config/Inc/stm32f7xx_it.h | 84 + .../CubeMX_Config/MDK-ARM/CubeMX_Config.uvoptx | 133 + .../CubeMX_Config/MDK-ARM/CubeMX_Config.uvprojx | 648 +++++ .../CubeMX_Config/MDK-ARM/startup_stm32f767xx.s | 517 ++++ .../board/CubeMX_Config/Src/main.c | 642 +++++ .../board/CubeMX_Config/Src/stm32f7xx_hal_msp.c | 981 +++++++ .../board/CubeMX_Config/Src/stm32f7xx_it.c | 218 ++ .../board/CubeMX_Config/Src/system_stm32f7xx.c | 278 ++ .../stm32f767-fire-challenger-v1/board/Kconfig | 237 ++ .../stm32f767-fire-challenger-v1/board/SConscript | 40 + .../stm32f767-fire-challenger-v1/board/board.c | 71 + .../stm32f767-fire-challenger-v1/board/board.h | 50 + .../board/linker_scripts/link.icf | 28 + .../board/linker_scripts/link.lds | 157 ++ .../board/linker_scripts/link.sct | 15 + .../board/ports/drv_qspi_flash.c | 77 + .../board/ports/fal_cfg.h | 48 + .../board/ports/lcd_port.h | 33 + .../board/ports/phy_reset.c | 16 + .../board/ports/sdcard_port.c | 73 + .../board/ports/sdram_port.h | 65 + .../stm32f767-fire-challenger-v1/figures/board.jpg | Bin 0 -> 181776 bytes bsp/stm32/stm32f767-fire-challenger-v1/project.ewd | 2834 ++++++++++++++++++++ bsp/stm32/stm32f767-fire-challenger-v1/project.ewp | 2267 ++++++++++++++++ bsp/stm32/stm32f767-fire-challenger-v1/project.eww | 10 + .../stm32f767-fire-challenger-v1/project.uvopt | 184 ++ .../stm32f767-fire-challenger-v1/project.uvoptx | 1040 +++++++ .../stm32f767-fire-challenger-v1/project.uvprojx | 847 ++++++ bsp/stm32/stm32f767-fire-challenger-v1/rtconfig.h | 189 ++ bsp/stm32/stm32f767-fire-challenger-v1/rtconfig.py | 150 ++ .../stm32f767-fire-challenger-v1/template.ewp | 2031 ++++++++++++++ .../stm32f767-fire-challenger-v1/template.eww | 10 + .../stm32f767-fire-challenger-v1/template.uvoptx | 192 ++ .../stm32f767-fire-challenger-v1/template.uvprojx | 395 +++ bsp/stm32/stm32f767-fire-challenger/.config | 399 --- bsp/stm32/stm32f767-fire-challenger/.gitignore | 42 - bsp/stm32/stm32f767-fire-challenger/Kconfig | 21 - bsp/stm32/stm32f767-fire-challenger/README.md | 131 - bsp/stm32/stm32f767-fire-challenger/SConscript | 15 - bsp/stm32/stm32f767-fire-challenger/SConstruct | 60 - .../applications/SConscript | 12 - .../stm32f767-fire-challenger/applications/main.c | 30 - .../board/CubeMX_Config/.mxproject | 13 - .../board/CubeMX_Config/CubeMX_Config.ioc | 516 ---- .../board/CubeMX_Config/Inc/main.h | 91 - .../board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h | 458 ---- .../board/CubeMX_Config/Inc/stm32f7xx_it.h | 84 - .../CubeMX_Config/MDK-ARM/CubeMX_Config.uvoptx | 133 - .../CubeMX_Config/MDK-ARM/CubeMX_Config.uvprojx | 648 ----- .../CubeMX_Config/MDK-ARM/startup_stm32f767xx.s | 517 ---- .../board/CubeMX_Config/Src/main.c | 642 ----- .../board/CubeMX_Config/Src/stm32f7xx_hal_msp.c | 981 ------- .../board/CubeMX_Config/Src/stm32f7xx_it.c | 218 -- .../board/CubeMX_Config/Src/system_stm32f7xx.c | 278 -- bsp/stm32/stm32f767-fire-challenger/board/Kconfig | 237 -- .../stm32f767-fire-challenger/board/SConscript | 40 - bsp/stm32/stm32f767-fire-challenger/board/board.c | 71 - bsp/stm32/stm32f767-fire-challenger/board/board.h | 50 - .../board/linker_scripts/link.icf | 28 - .../board/linker_scripts/link.lds | 157 -- .../board/linker_scripts/link.sct | 15 - .../board/ports/drv_qspi_flash.c | 77 - .../board/ports/fal_cfg.h | 48 - .../board/ports/lcd_port.h | 33 - .../board/ports/phy_reset.c | 16 - .../board/ports/sdcard_port.c | 73 - .../board/ports/sdram_port.h | 65 - .../stm32f767-fire-challenger/figures/board.jpg | Bin 181776 -> 0 bytes bsp/stm32/stm32f767-fire-challenger/project.ewd | 2834 -------------------- bsp/stm32/stm32f767-fire-challenger/project.ewp | 2267 ---------------- bsp/stm32/stm32f767-fire-challenger/project.eww | 10 - bsp/stm32/stm32f767-fire-challenger/project.uvopt | 184 -- .../stm32f767-fire-challenger/project.uvprojx | 828 ------ bsp/stm32/stm32f767-fire-challenger/rtconfig.h | 180 -- bsp/stm32/stm32f767-fire-challenger/rtconfig.py | 150 -- bsp/stm32/stm32f767-fire-challenger/template.ewp | 2031 -------------- bsp/stm32/stm32f767-fire-challenger/template.eww | 10 - .../stm32f767-fire-challenger/template.uvoptx | 192 -- .../stm32f767-fire-challenger/template.uvprojx | 395 --- 95 files changed, 16542 insertions(+), 15298 deletions(-) create mode 100644 bsp/stm32/stm32f767-fire-challenger-v1/.config create mode 100644 bsp/stm32/stm32f767-fire-challenger-v1/.gitignore create mode 100644 bsp/stm32/stm32f767-fire-challenger-v1/Kconfig create mode 100644 bsp/stm32/stm32f767-fire-challenger-v1/README.md create mode 100644 bsp/stm32/stm32f767-fire-challenger-v1/SConscript create mode 100644 bsp/stm32/stm32f767-fire-challenger-v1/SConstruct create mode 100644 bsp/stm32/stm32f767-fire-challenger-v1/applications/SConscript create mode 100644 bsp/stm32/stm32f767-fire-challenger-v1/applications/main.c create mode 100644 bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/.mxproject create mode 100644 bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/CubeMX_Config.ioc create mode 100644 bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Inc/main.h create mode 100644 bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h create mode 100644 bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Inc/stm32f7xx_it.h create mode 100644 bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/MDK-ARM/CubeMX_Config.uvoptx create mode 100644 bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/MDK-ARM/CubeMX_Config.uvprojx create mode 100644 bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/MDK-ARM/startup_stm32f767xx.s create mode 100644 bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Src/main.c create mode 100644 bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c create mode 100644 bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Src/stm32f7xx_it.c create mode 100644 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delete mode 100644 bsp/stm32/stm32f767-fire-challenger/project.ewd delete mode 100644 bsp/stm32/stm32f767-fire-challenger/project.ewp delete mode 100644 bsp/stm32/stm32f767-fire-challenger/project.eww delete mode 100644 bsp/stm32/stm32f767-fire-challenger/project.uvopt delete mode 100644 bsp/stm32/stm32f767-fire-challenger/project.uvprojx delete mode 100644 bsp/stm32/stm32f767-fire-challenger/rtconfig.h delete mode 100644 bsp/stm32/stm32f767-fire-challenger/rtconfig.py delete mode 100644 bsp/stm32/stm32f767-fire-challenger/template.ewp delete mode 100644 bsp/stm32/stm32f767-fire-challenger/template.eww delete mode 100644 bsp/stm32/stm32f767-fire-challenger/template.uvoptx delete mode 100644 bsp/stm32/stm32f767-fire-challenger/template.uvprojx diff --git a/.github/workflows/action.yml b/.github/workflows/action.yml index 6b902850a4..ecbc19cca9 100644 --- a/.github/workflows/action.yml +++ b/.github/workflows/action.yml @@ -97,7 +97,7 @@ jobs: - {RTT_BSP: "stm32/stm32f469-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f746-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f767-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32f767-fire-challenger", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32f767-fire-challenger-v1", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f767-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32g070-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32g071-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} diff --git a/bsp/stm32/README.md b/bsp/stm32/README.md index 1a36605aa1..1c355c2d1d 100644 --- a/bsp/stm32/README.md +++ b/bsp/stm32/README.md @@ -43,7 +43,7 @@ STM32 系列 BSP 目前支持情况如下表所示： | **F7 系列** | | | [stm32f746-st-disco](stm32f746-st-disco) | ST 官方 STM32F746-discovery 开发板 | | [stm32f767-atk-apollo](stm32f767-atk-apollo) | 正点原子 F767 阿波罗开发板 | -| [stm32f767-fire-challenger](stm32f767-fire-challenger/) | 野火 F767 挑战者开发板 | +| [stm32f767-fire-challenger-v1](stm32f767-fire-challenger-v1/) | 野火 F767-V1 挑战者开发板 | | [stm32f767-st-nucleo](stm32f767-st-nucleo) | ST 官方 STM32F767-nucleo 开发板 | | [stm32f769-st-disco](stm32f769-st-disco) | ST 官方 STM32f769-discovery 开发板 | | **G0 系列** | | diff --git a/bsp/stm32/stm32f767-atk-apollo/README.md b/bsp/stm32/stm32f767-atk-apollo/README.md index efec3e704b..3045c68705 100644 --- a/bsp/stm32/stm32f767-atk-apollo/README.md +++ b/bsp/stm32/stm32f767-atk-apollo/README.md @@ -52,7 +52,7 @@ | **片上外设** | **支持情况** | **备注** | | GPIO | 支持 | PA0，PA1... PK15 ---> PIN: 0，1...176 | | UART | 支持 | | -| SPI | 支持 | | +| SPI | 支持 | SPI2 | | I2C | 支持 | 软件 I2C | | ADC | 支持 | | | RTC | 支持 | 支持外部晶振和内部低速时钟 | diff --git a/bsp/stm32/stm32f767-atk-apollo/board/Kconfig b/bsp/stm32/stm32f767-atk-apollo/board/Kconfig index df86ffc383..cda9c0dfef 100644 --- a/bsp/stm32/stm32f767-atk-apollo/board/Kconfig +++ b/bsp/stm32/stm32f767-atk-apollo/board/Kconfig @@ -110,21 +110,6 @@ menu "On-chip Peripheral Drivers" default n select RT_USING_SPI if BSP_USING_SPI - config BSP_USING_SPI1 - bool "Enable SPI1 BUS" - default n - - config BSP_SPI1_TX_USING_DMA - bool "Enable SPI1 TX DMA" - depends on BSP_USING_SPI1 - default n - - config BSP_SPI1_RX_USING_DMA - bool "Enable SPI1 RX DMA" - depends on BSP_USING_SPI1 - select BSP_SPI1_TX_USING_DMA - default n - config BSP_USING_SPI2 bool "Enable SPI2 BUS" default n diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/.config b/bsp/stm32/stm32f767-fire-challenger-v1/.config new file mode 100644 index 0000000000..10dded4cd7 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/.config @@ -0,0 +1,590 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_SMALL_MEM is not set +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP_AS_HEAP=y +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40003 +CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M7=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +CONFIG_FINSH_USING_MSH_ONLY=y +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_LIBC_USING_TIME=y + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set +CONFIG_SOC_FAMILY_STM32=y +CONFIG_SOC_SERIES_STM32F7=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_STM32F767IG=y + +# +# Onboard Peripheral Drivers +# +CONFIG_BSP_USING_USB_TO_USART=y +# CONFIG_BSP_USING_RS232 is not set +# CONFIG_BSP_USING_SDRAM is not set +# CONFIG_BSP_USING_QSPI_FLASH is not set +# CONFIG_BSP_USING_LCD is not set +# CONFIG_BSP_USING_MPU6050 is not set +# CONFIG_BSP_USING_POT is not set +# CONFIG_BSP_USING_SDCARD is not set + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set +CONFIG_BSP_USING_SPI=y +CONFIG_BSP_USING_SPI1=y +CONFIG_BSP_SPI1_TX_USING_DMA=y +CONFIG_BSP_SPI1_RX_USING_DMA=y +# CONFIG_BSP_USING_SPI2 is not set +# CONFIG_BSP_USING_SPI5 is not set +# CONFIG_BSP_USING_QSPI is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_FMC is not set +# CONFIG_BSP_USING_LTDC is not set +# CONFIG_BSP_USING_CRC is not set +# CONFIG_BSP_USING_RNG is not set +# CONFIG_BSP_USING_UDID is not set + +# +# Board extended module Drivers +# diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/.gitignore b/bsp/stm32/stm32f767-fire-challenger-v1/.gitignore new file mode 100644 index 0000000000..7221bde019 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/Kconfig b/bsp/stm32/stm32f767-fire-challenger-v1/Kconfig new file mode 100644 index 0000000000..8cbc7b71a8 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/README.md b/bsp/stm32/stm32f767-fire-challenger-v1/README.md new file mode 100644 index 0000000000..12709f2ce9 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/README.md @@ -0,0 +1,131 @@ +# STM32F767-V1 挑战者开发板 BSP 说明 + +## 简介 + +本文档为 野火stm32f767-v1 开发板的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +挑战者 STM32F767-V1 是野火推出的一款基于 ARM Cortex-M7 内核的开发板，最高主频为 216Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32F767 的芯片性能。 + +开发板外观如下图所示： + +![board](figures/board.jpg) + +该开发板常用 **板载资源** 如下： + +- MCU：STM32f767，主频 216MHz，1MB FLASH ，512KB RAM ，16K CACHE +- 外部 RAM：型号，8MB +- 外部 FLASH：型号，16MB +- 常用外设 + - LED：RGB灯 + - 按键：2个，K1（兼具唤醒功能，PA0），K2（PC13） +- 常用接口：USB 转串口、SD 卡接口、以太网接口、LCD 接口 +- 调试接口，标准 JTAG/SWD + +开发板更多详细信息请参考野火 [STM32 挑战者开发板介绍](https://fire-stm32.taobao.com/index.htm)。 + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :---------------- | :----------: | :------------------------------------------------------ | +| USB 转串口 | 支持 | | +| RS232 | 支持 | 与以太网有引脚冲突 | +| QSPI Flash | 支持 | | +| 电位器 | 支持 | 使用 ADC1 | +| 以太网 | 暂不支持 | 移植中 | +| MPU6050六轴传感器 | 支持 | | +| SDRAM | 支持 | | +| LCD | 支持 | 支持 RGB 屏 | +| SD卡 | 支持 | | +| CAN | 即将支持 | | +| EMW1062 | 暂不支持 | | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...176 | +| UART | 支持 | UART1/x/x | +| SPI | 暂不支持 | | +| I2C | 支持 | 软件 I2C | +| ADC | 支持 | | +| RTC | 支持 | 支持外部晶振和内部低速时钟 | +| WDT | 支持 | | +| FLASH | 支持 | 已适配 [FAL](https://github.com/RT-Thread-packages/fal) | +| SDIO | 支持 | | +| PWM | 暂不支持 | 即将支持 | +| USB Device | 暂不支持 | 即将支持 | +| USB Host | 暂不支持 | 即将支持 | +| **扩展模块** | **支持情况** | **备注** | +| 暂无 | 暂不支持 | 暂不支持 | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 Jlink 仿真器下载程序，在通过 Jlink 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，LED 闪烁。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.0 build Dec 10 2018 + 2006 - 2018 Copyright by rt-thread team +msh > +``` +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口1 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 + +## 注意事项 + +暂无 + +## 联系人信息 + +维护人: + +- [greedyhao](https://github.com/greedyhao), 邮箱： \ No newline at end of file diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/SConscript b/bsp/stm32/stm32f767-fire-challenger-v1/SConscript new file mode 100644 index 0000000000..20f7689c53 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/SConstruct b/bsp/stm32/stm32f767-fire-challenger-v1/SConstruct new file mode 100644 index 0000000000..050835a35a --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +stm32_library = 'STM32F7xx_HAL' +rtconfig.BSP_LIBRARY_TYPE = stm32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/applications/SConscript b/bsp/stm32/stm32f767-fire-challenger-v1/applications/SConscript new file mode 100644 index 0000000000..6f66f7ab73 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/applications/SConscript @@ -0,0 +1,12 @@ +import rtconfig +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd, str(Dir('#'))] +src = Split(""" +main.c +""") + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/applications/main.c b/bsp/stm32/stm32f767-fire-challenger-v1/applications/main.c new file mode 100644 index 0000000000..3570c667c9 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/applications/main.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-06 SummerGift first version + */ + +#include +#include +#include + +/* defined the LED0 pin: PH10 */ +#define LED0_PIN GET_PIN(H, 10) + +int main(void) +{ + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); + rt_thread_mdelay(500); + } +} diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/.mxproject new file mode 100644 index 0000000000..6c898500f2 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/.mxproject @@ -0,0 +1,13 @@ +[PreviousGenFiles] +HeaderPath=/media/greedyhao/Data/Files/github/my-rt-thread/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Inc +HeaderFiles=stm32f7xx_it.h;stm32f7xx_hal_conf.h;main.h; +SourcePath=/media/greedyhao/Data/Files/github/my-rt-thread/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Src +SourceFiles=stm32f7xx_it.c;stm32f7xx_hal_msp.c;main.c; + +[PreviousLibFiles] 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tm32_hal_legacy.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h; + +[PreviousUsedKeilFiles] +SourceFiles=../Src/main.c;../Src/stm32f7xx_it.c;../Src/stm32f7xx_hal_msp.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;..//Src/system_stm32f7xx.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;..//Src/system_stm32f7xx.c;../Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;null; +HeaderPath=../Drivers/STM32F7xx_HAL_Driver/Inc;../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F7xx/Include;../Drivers/CMSIS/Include;../Inc; + diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/CubeMX_Config.ioc new file mode 100644 index 0000000000..c9b386e6ca --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/CubeMX_Config.ioc @@ -0,0 +1,516 @@ +#MicroXplorer Configuration settings - do not modify +ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_5 +ADC1.IPParameters=Rank-0\#ChannelRegularConversion,master,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag +ADC1.NbrOfConversionFlag=1 +ADC1.Rank-0\#ChannelRegularConversion=1 +ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES +ADC1.master=1 +ETH.IPParameters=MediaInterface +ETH.MediaInterface=ETH_MEDIA_INTERFACE_RMII +File.Version=6 +KeepUserPlacement=false +Mcu.Family=STM32F7 +Mcu.IP0=ADC1 +Mcu.IP1=CORTEX_M7 +Mcu.IP10=SYS +Mcu.IP11=USART1 +Mcu.IP2=DMA2D +Mcu.IP3=ETH +Mcu.IP4=FMC +Mcu.IP5=LTDC +Mcu.IP6=NVIC +Mcu.IP7=QUADSPI +Mcu.IP8=RCC +Mcu.IP9=SDMMC1 +Mcu.IPNb=12 +Mcu.Name=STM32F767I(G-I)Tx +Mcu.Package=LQFP176 +Mcu.Pin0=PE4 +Mcu.Pin1=PE5 +Mcu.Pin10=PF5 +Mcu.Pin11=PF6 +Mcu.Pin12=PF7 +Mcu.Pin13=PF8 +Mcu.Pin14=PF9 +Mcu.Pin15=PF10 +Mcu.Pin16=PH0/OSC_IN +Mcu.Pin17=PH1/OSC_OUT +Mcu.Pin18=PC0 +Mcu.Pin19=PC1 +Mcu.Pin2=PE6 +Mcu.Pin20=PA1 +Mcu.Pin21=PA2 +Mcu.Pin22=PH2 +Mcu.Pin23=PH3 +Mcu.Pin24=PA3 +Mcu.Pin25=PA5 +Mcu.Pin26=PA7 +Mcu.Pin27=PC4 +Mcu.Pin28=PC5 +Mcu.Pin29=PB0 +Mcu.Pin3=PI9 +Mcu.Pin30=PB1 +Mcu.Pin31=PB2 +Mcu.Pin32=PF11 +Mcu.Pin33=PF12 +Mcu.Pin34=PF13 +Mcu.Pin35=PF14 +Mcu.Pin36=PF15 +Mcu.Pin37=PG0 +Mcu.Pin38=PG1 +Mcu.Pin39=PE7 +Mcu.Pin4=PI10 +Mcu.Pin40=PE8 +Mcu.Pin41=PE9 +Mcu.Pin42=PE10 +Mcu.Pin43=PE11 +Mcu.Pin44=PE12 +Mcu.Pin45=PE13 +Mcu.Pin46=PE14 +Mcu.Pin47=PE15 +Mcu.Pin48=PB11 +Mcu.Pin49=PH6 +Mcu.Pin5=PF0 +Mcu.Pin50=PH7 +Mcu.Pin51=PH8 +Mcu.Pin52=PH10 +Mcu.Pin53=PB12 +Mcu.Pin54=PB13 +Mcu.Pin55=PD8 +Mcu.Pin56=PD9 +Mcu.Pin57=PD10 +Mcu.Pin58=PD14 +Mcu.Pin59=PD15 +Mcu.Pin6=PF1 +Mcu.Pin60=PG4 +Mcu.Pin61=PG5 +Mcu.Pin62=PG6 +Mcu.Pin63=PG7 +Mcu.Pin64=PG8 +Mcu.Pin65=PC7 +Mcu.Pin66=PC8 +Mcu.Pin67=PC9 +Mcu.Pin68=PA9 +Mcu.Pin69=PA10 +Mcu.Pin7=PF2 +Mcu.Pin70=PA11 +Mcu.Pin71=PA12 +Mcu.Pin72=PH13 +Mcu.Pin73=PH15 +Mcu.Pin74=PI0 +Mcu.Pin75=PI2 +Mcu.Pin76=PC10 +Mcu.Pin77=PC11 +Mcu.Pin78=PC12 +Mcu.Pin79=PD0 +Mcu.Pin8=PF3 +Mcu.Pin80=PD1 +Mcu.Pin81=PD2 +Mcu.Pin82=PD6 +Mcu.Pin83=PG10 +Mcu.Pin84=PG11 +Mcu.Pin85=PG12 +Mcu.Pin86=PG15 +Mcu.Pin87=PB6 +Mcu.Pin88=PB8 +Mcu.Pin89=PB9 +Mcu.Pin9=PF4 +Mcu.Pin90=PE0 +Mcu.Pin91=PE1 +Mcu.Pin92=PI4 +Mcu.Pin93=VP_DMA2D_VS_DMA2D +Mcu.Pin94=VP_SYS_VS_Systick +Mcu.PinsNb=95 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F767IGTx +MxCube.Version=5.1.0 +MxDb.Version=DB.5.0.10 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PA1.Mode=RMII +PA1.Signal=ETH_REF_CLK +PA10.Locked=true +PA10.Mode=Asynchronous +PA10.Signal=USART1_RX +PA11.GPIOParameters=GPIO_Speed +PA11.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PA11.Locked=true +PA11.Mode=RGB888 +PA11.Signal=LTDC_R4 +PA12.GPIOParameters=GPIO_Speed +PA12.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PA12.Locked=true +PA12.Mode=RGB888 +PA12.Signal=LTDC_R5 +PA2.Mode=RMII +PA2.Signal=ETH_MDIO +PA3.GPIOParameters=GPIO_Speed +PA3.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PA3.Mode=RGB888 +PA3.Signal=LTDC_B5 +PA5.Signal=ADCx_IN5 +PA7.Mode=RMII +PA7.Signal=ETH_CRS_DV +PA9.Locked=true +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PB0.GPIOParameters=GPIO_Speed +PB0.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PB0.Mode=RGB888 +PB0.Signal=LTDC_R3 +PB1.GPIOParameters=GPIO_Speed +PB1.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PB1.Mode=RGB888 +PB1.Signal=LTDC_R6 +PB11.Mode=RMII +PB11.Signal=ETH_TX_EN +PB12.Mode=RMII +PB12.Signal=ETH_TXD0 +PB13.Mode=RMII +PB13.Signal=ETH_TXD1 +PB2.Mode=Single Bank 1 +PB2.Signal=QUADSPI_CLK +PB6.Locked=true +PB6.Mode=Single Bank 1 +PB6.Signal=QUADSPI_BK1_NCS +PB8.GPIOParameters=GPIO_Speed +PB8.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PB8.Mode=RGB888 +PB8.Signal=LTDC_B6 +PB9.GPIOParameters=GPIO_Speed +PB9.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PB9.Mode=RGB888 +PB9.Signal=LTDC_B7 +PC0.Signal=FMC_SDNWE +PC1.Mode=RMII +PC1.Signal=ETH_MDC +PC10.Mode=SD_4_bits_Wide_bus +PC10.Signal=SDMMC1_D2 +PC11.Mode=SD_4_bits_Wide_bus +PC11.Signal=SDMMC1_D3 +PC12.Mode=SD_4_bits_Wide_bus +PC12.Signal=SDMMC1_CK +PC4.Mode=RMII +PC4.Signal=ETH_RXD0 +PC5.Mode=RMII +PC5.Signal=ETH_RXD1 +PC7.GPIOParameters=GPIO_Speed +PC7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PC7.Locked=true +PC7.Mode=RGB888 +PC7.Signal=LTDC_G6 +PC8.Mode=SD_4_bits_Wide_bus +PC8.Signal=SDMMC1_D0 +PC9.Mode=SD_4_bits_Wide_bus +PC9.Signal=SDMMC1_D1 +PCC.Checker=false +PCC.Line=STM32F7x7 +PCC.MCU=STM32F767I(G-I)Tx +PCC.PartNumber=STM32F767IGTx +PCC.Seq0=0 +PCC.Series=STM32F7 +PCC.Temperature=25 +PCC.Vdd=3.3 +PD0.Signal=FMC_D2_DA2 +PD1.Signal=FMC_D3_DA3 +PD10.Signal=FMC_D15_DA15 +PD14.Signal=FMC_D0_DA0 +PD15.Signal=FMC_D1_DA1 +PD2.Mode=SD_4_bits_Wide_bus +PD2.Signal=SDMMC1_CMD +PD6.GPIOParameters=GPIO_Speed +PD6.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PD6.Mode=RGB888 +PD6.Signal=LTDC_B2 +PD8.Signal=FMC_D13_DA13 +PD9.Signal=FMC_D14_DA14 +PE0.Signal=FMC_NBL0 +PE1.Signal=FMC_NBL1 +PE10.Signal=FMC_D7_DA7 +PE11.Signal=FMC_D8_DA8 +PE12.Signal=FMC_D9_DA9 +PE13.Signal=FMC_D10_DA10 +PE14.Signal=FMC_D11_DA11 +PE15.Signal=FMC_D12_DA12 +PE4.GPIOParameters=GPIO_Speed +PE4.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PE4.Mode=RGB888 +PE4.Signal=LTDC_B0 +PE5.GPIOParameters=GPIO_Speed +PE5.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PE5.Mode=RGB888 +PE5.Signal=LTDC_G0 +PE6.GPIOParameters=GPIO_Speed +PE6.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PE6.Mode=RGB888 +PE6.Signal=LTDC_G1 +PE7.Signal=FMC_D4_DA4 +PE8.Signal=FMC_D5_DA5 +PE9.Signal=FMC_D6_DA6 +PF0.Signal=FMC_A0 +PF1.Signal=FMC_A1 +PF10.GPIOParameters=GPIO_Speed +PF10.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PF10.Mode=RGB888 +PF10.Signal=LTDC_DE +PF11.Signal=FMC_SDNRAS +PF12.Signal=FMC_A6 +PF13.Signal=FMC_A7 +PF14.Signal=FMC_A8 +PF15.Signal=FMC_A9 +PF2.Signal=FMC_A2 +PF3.Signal=FMC_A3 +PF4.Signal=FMC_A4 +PF5.Signal=FMC_A5 +PF6.Mode=Single Bank 1 +PF6.Signal=QUADSPI_BK1_IO3 +PF7.Locked=true +PF7.Mode=Single Bank 1 +PF7.Signal=QUADSPI_BK1_IO2 +PF8.Mode=Single Bank 1 +PF8.Signal=QUADSPI_BK1_IO0 +PF9.Mode=Single Bank 1 +PF9.Signal=QUADSPI_BK1_IO1 +PG0.Signal=FMC_A10 +PG1.Signal=FMC_A11 +PG10.GPIOParameters=GPIO_Speed +PG10.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PG10.Locked=true +PG10.Mode=RGB888 +PG10.Signal=LTDC_G3 +PG11.GPIOParameters=GPIO_Speed +PG11.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PG11.Locked=true +PG11.Mode=RGB888 +PG11.Signal=LTDC_B3 +PG12.Mode=RGB888 +PG12.Signal=LTDC_B1 +PG15.Signal=FMC_SDNCAS +PG4.Signal=FMC_A14_BA0 +PG5.Signal=FMC_A15_BA1 +PG6.GPIOParameters=GPIO_Speed +PG6.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PG6.Mode=RGB888 +PG6.Signal=LTDC_R7 +PG7.GPIOParameters=GPIO_Speed +PG7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PG7.Mode=RGB888 +PG7.Signal=LTDC_CLK +PG8.Signal=FMC_SDCLK +PH0/OSC_IN.Mode=HSE-External-Oscillator +PH0/OSC_IN.Signal=RCC_OSC_IN +PH1/OSC_OUT.Mode=HSE-External-Oscillator +PH1/OSC_OUT.Signal=RCC_OSC_OUT +PH10.Locked=true +PH10.Signal=GPIO_Output +PH13.Locked=true +PH13.Mode=RGB888 +PH13.Signal=LTDC_G2 +PH15.Mode=RGB888 +PH15.Signal=LTDC_G4 +PH2.Mode=RGB888 +PH2.Signal=LTDC_R0 +PH3.Mode=RGB888 +PH3.Signal=LTDC_R1 +PH6.Mode=SdramChipSelect2_1 +PH6.Signal=FMC_SDNE1 +PH7.Mode=SdramChipSelect2_1 +PH7.Signal=FMC_SDCKE1 +PH8.Mode=RGB888 +PH8.Signal=LTDC_R2 +PI0.Locked=true +PI0.Mode=RGB888 +PI0.Signal=LTDC_G5 +PI10.Mode=RGB888 +PI10.Signal=LTDC_HSYNC +PI2.Mode=RGB888 +PI2.Signal=LTDC_G7 +PI4.Mode=RGB888 +PI4.Signal=LTDC_B4 +PI9.Mode=RGB888 +PI9.Signal=LTDC_VSYNC +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F767IGTx +ProjectManager.FirmwarePackage=STM32Cube FW_F7 V1.15.0 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=0 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=CubeMX_Config.ioc +ProjectManager.ProjectName=CubeMX_Config +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=MDK-ARM V5 +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_ETH_Init-ETH-false-HAL-true,6-MX_FMC_Init-FMC-false-HAL-true,7-MX_QUADSPI_Init-QUADSPI-false-HAL-true,8-MX_SDMMC1_SD_Init-SDMMC1-false-HAL-true,9-MX_DMA2D_Init-DMA2D-false-HAL-true,10-MX_LTDC_Init-LTDC-false-HAL-true,11-MX_ADC1_Init-ADC1-false-HAL-true +RCC.AHBFreq_Value=216000000 +RCC.APB1CLKDivider=RCC_HCLK_DIV4 +RCC.APB1Freq_Value=54000000 +RCC.APB1TimFreq_Value=108000000 +RCC.APB2CLKDivider=RCC_HCLK_DIV2 +RCC.APB2Freq_Value=108000000 +RCC.APB2TimFreq_Value=216000000 +RCC.CECFreq_Value=32786.88524590164 +RCC.CortexFreq_Value=216000000 +RCC.DFSDMAudioFreq_Value=96000000 +RCC.DFSDMFreq_Value=108000000 +RCC.EthernetFreq_Value=216000000 +RCC.FCLKCortexFreq_Value=216000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=216000000 +RCC.HSE_VALUE=25000000 +RCC.HSI_VALUE=16000000 +RCC.I2C1Freq_Value=54000000 +RCC.I2C2Freq_Value=54000000 +RCC.I2C3Freq_Value=54000000 +RCC.I2C4Freq_Value=54000000 +RCC.I2SFreq_Value=96000000 +RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,DFSDMAudioFreq_Value,DFSDMFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LCDTFTFreq_Value,LPTIM1Freq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SRoutputFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLQoutputFreq_Value,PLLRFreq_Value,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIR,PLLSAIRCLKFreq_Value,PLLSAIoutputFreq_Value,PLLSourceVirtual,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC2Freq_Value,SDMMCClockSelection,SDMMCFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value +RCC.LCDTFTFreq_Value=32000000 +RCC.LPTIM1Freq_Value=54000000 +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=32000 +RCC.MCO2PinFreq_Value=216000000 +RCC.PLLCLKFreq_Value=216000000 +RCC.PLLI2SPCLKFreq_Value=96000000 +RCC.PLLI2SQCLKFreq_Value=96000000 +RCC.PLLI2SRCLKFreq_Value=96000000 +RCC.PLLI2SRoutputFreq_Value=96000000 +RCC.PLLM=25 +RCC.PLLN=432 +RCC.PLLQ=9 +RCC.PLLQCLKFreq_Value=48000000 +RCC.PLLQoutputFreq_Value=48000000 +RCC.PLLRFreq_Value=216000000 +RCC.PLLSAIPCLKFreq_Value=96000000 +RCC.PLLSAIQCLKFreq_Value=96000000 +RCC.PLLSAIR=3 +RCC.PLLSAIRCLKFreq_Value=64000000 +RCC.PLLSAIoutputFreq_Value=96000000 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +RCC.RNGFreq_Value=48000000 +RCC.SAI1Freq_Value=96000000 +RCC.SAI2Freq_Value=96000000 +RCC.SDMMC2Freq_Value=216000000 +RCC.SDMMCClockSelection=RCC_SDMMC1CLKSOURCE_CLK48 +RCC.SDMMCFreq_Value=48000000 +RCC.SPDIFRXFreq_Value=96000000 +RCC.SYSCLKFreq_VALUE=216000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.UART4Freq_Value=54000000 +RCC.UART5Freq_Value=54000000 +RCC.UART7Freq_Value=54000000 +RCC.UART8Freq_Value=54000000 +RCC.USART1Freq_Value=108000000 +RCC.USART2Freq_Value=54000000 +RCC.USART3Freq_Value=54000000 +RCC.USART6Freq_Value=108000000 +RCC.USBFreq_Value=48000000 +RCC.VCOI2SOutputFreq_Value=192000000 +RCC.VCOInputFreq_Value=1000000 +RCC.VCOOutputFreq_Value=432000000 +RCC.VCOSAIOutputFreq_Value=192000000 +SH.ADCx_IN5.0=ADC1_IN5,IN5 +SH.ADCx_IN5.ConfNb=1 +SH.FMC_A0.0=FMC_A0,12b-sda1 +SH.FMC_A0.ConfNb=1 +SH.FMC_A1.0=FMC_A1,12b-sda1 +SH.FMC_A1.ConfNb=1 +SH.FMC_A10.0=FMC_A10,12b-sda1 +SH.FMC_A10.ConfNb=1 +SH.FMC_A11.0=FMC_A11,12b-sda1 +SH.FMC_A11.ConfNb=1 +SH.FMC_A14_BA0.0=FMC_BA0,FourSdramBanks1 +SH.FMC_A14_BA0.ConfNb=1 +SH.FMC_A15_BA1.0=FMC_BA1,FourSdramBanks1 +SH.FMC_A15_BA1.ConfNb=1 +SH.FMC_A2.0=FMC_A2,12b-sda1 +SH.FMC_A2.ConfNb=1 +SH.FMC_A3.0=FMC_A3,12b-sda1 +SH.FMC_A3.ConfNb=1 +SH.FMC_A4.0=FMC_A4,12b-sda1 +SH.FMC_A4.ConfNb=1 +SH.FMC_A5.0=FMC_A5,12b-sda1 +SH.FMC_A5.ConfNb=1 +SH.FMC_A6.0=FMC_A6,12b-sda1 +SH.FMC_A6.ConfNb=1 +SH.FMC_A7.0=FMC_A7,12b-sda1 +SH.FMC_A7.ConfNb=1 +SH.FMC_A8.0=FMC_A8,12b-sda1 +SH.FMC_A8.ConfNb=1 +SH.FMC_A9.0=FMC_A9,12b-sda1 +SH.FMC_A9.ConfNb=1 +SH.FMC_D0_DA0.0=FMC_D0,sd-16b-d1 +SH.FMC_D0_DA0.ConfNb=1 +SH.FMC_D10_DA10.0=FMC_D10,sd-16b-d1 +SH.FMC_D10_DA10.ConfNb=1 +SH.FMC_D11_DA11.0=FMC_D11,sd-16b-d1 +SH.FMC_D11_DA11.ConfNb=1 +SH.FMC_D12_DA12.0=FMC_D12,sd-16b-d1 +SH.FMC_D12_DA12.ConfNb=1 +SH.FMC_D13_DA13.0=FMC_D13,sd-16b-d1 +SH.FMC_D13_DA13.ConfNb=1 +SH.FMC_D14_DA14.0=FMC_D14,sd-16b-d1 +SH.FMC_D14_DA14.ConfNb=1 +SH.FMC_D15_DA15.0=FMC_D15,sd-16b-d1 +SH.FMC_D15_DA15.ConfNb=1 +SH.FMC_D1_DA1.0=FMC_D1,sd-16b-d1 +SH.FMC_D1_DA1.ConfNb=1 +SH.FMC_D2_DA2.0=FMC_D2,sd-16b-d1 +SH.FMC_D2_DA2.ConfNb=1 +SH.FMC_D3_DA3.0=FMC_D3,sd-16b-d1 +SH.FMC_D3_DA3.ConfNb=1 +SH.FMC_D4_DA4.0=FMC_D4,sd-16b-d1 +SH.FMC_D4_DA4.ConfNb=1 +SH.FMC_D5_DA5.0=FMC_D5,sd-16b-d1 +SH.FMC_D5_DA5.ConfNb=1 +SH.FMC_D6_DA6.0=FMC_D6,sd-16b-d1 +SH.FMC_D6_DA6.ConfNb=1 +SH.FMC_D7_DA7.0=FMC_D7,sd-16b-d1 +SH.FMC_D7_DA7.ConfNb=1 +SH.FMC_D8_DA8.0=FMC_D8,sd-16b-d1 +SH.FMC_D8_DA8.ConfNb=1 +SH.FMC_D9_DA9.0=FMC_D9,sd-16b-d1 +SH.FMC_D9_DA9.ConfNb=1 +SH.FMC_NBL0.0=FMC_NBL0,Sd2ByteEnable1 +SH.FMC_NBL0.ConfNb=1 +SH.FMC_NBL1.0=FMC_NBL1,Sd2ByteEnable1 +SH.FMC_NBL1.ConfNb=1 +SH.FMC_SDCLK.0=FMC_SDCLK,12b-sda1 +SH.FMC_SDCLK.ConfNb=1 +SH.FMC_SDNCAS.0=FMC_SDNCAS,12b-sda1 +SH.FMC_SDNCAS.ConfNb=1 +SH.FMC_SDNRAS.0=FMC_SDNRAS,12b-sda1 +SH.FMC_SDNRAS.ConfNb=1 +SH.FMC_SDNWE.0=FMC_SDNWE,12b-sda1 +SH.FMC_SDNWE.ConfNb=1 +USART1.IPParameters=VirtualMode-Asynchronous +USART1.VirtualMode-Asynchronous=VM_ASYNC +VP_DMA2D_VS_DMA2D.Mode=DMA2D_Activate +VP_DMA2D_VS_DMA2D.Signal=DMA2D_VS_DMA2D +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +board=custom diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Inc/main.h b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Inc/main.h new file mode 100644 index 0000000000..03c0f13fc7 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Inc/main.h @@ -0,0 +1,91 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + ** This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h new file mode 100644 index 0000000000..f00413fa52 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h @@ -0,0 +1,458 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_conf.h + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2019 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_CONF_H +#define __STM32F7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + +#define HAL_ADC_MODULE_ENABLED +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +#define HAL_DMA2D_MODULE_ENABLED +#define HAL_ETH_MODULE_ENABLED +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +#define HAL_SDRAM_MODULE_ENABLED +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +#define HAL_LTDC_MODULE_ENABLED +#define HAL_QSPI_MODULE_ENABLED +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +#define HAL_SD_MODULE_ENABLED +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_MDIOS_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_EXTI_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define ART_ACCLERATOR_ENABLE 0U /* To enable instruction cache and prefetch */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* LAN8742A_PHY_ADDRESS Address*/ +#define LAN8742A_PHY_ADDRESS 1 +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x1FU) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0004U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0010U) /*!< PHY Duplex mask */ + +#define PHY_ISFR ((uint16_t)0x001DU) /*!< PHY Interrupt Source Flag register Offset */ +#define PHY_ISFR_INT4 ((uint16_t)0x000BU) /*!< PHY Link down inturrupt */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f7xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f7xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f7xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f7xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f7xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32f7xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED + #include "stm32f7xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f7xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Inc/stm32f7xx_it.h b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Inc/stm32f7xx_it.h new file mode 100644 index 0000000000..a398e3c63b --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Inc/stm32f7xx_it.h @@ -0,0 +1,84 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_IT_H +#define __STM32F7xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/MDK-ARM/CubeMX_Config.uvoptx b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/MDK-ARM/CubeMX_Config.uvoptx new file mode 100644 index 0000000000..565b317696 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/MDK-ARM/CubeMX_Config.uvoptx @@ -0,0 +1,133 @@ + + + + CubeMX_Config + 0x4 + ARM-ADS + + 216000000 + + 1 + 1 + 0 + 1 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 13 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ST-LINKIII-KEIL_SWO + -U-O142 -O2254 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F7x_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F767IG$Flash\STM32F7x_1024.FLM) -FF1STM32F7x_TCM -FS1200000 -FL1100000 -FP1($$Device:STM32F767IG$Flash\STM32F7x_TCM.FLM) + + + 0 + + -U-O142 -O2254 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F7x_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F767IG$Flash\STM32F7x_1024.FLM) -FF1STM32F7x_TCM -FS1200000 -FL1100000 -FP1($$Device:STM32F767IG$Flash\STM32F7x_TCM.FLM) + + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/MDK-ARM/CubeMX_Config.uvprojx b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/MDK-ARM/CubeMX_Config.uvprojx new file mode 100644 index 0000000000..06c86a1736 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/MDK-ARM/CubeMX_Config.uvprojx @@ -0,0 +1,648 @@ + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + CubeMX_Config + 0x4 + ARM-ADS + + + STM32F767IGTx + STMicroelectronics + IRAM(0x20000000-0x2007FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(12000000) FPU3(DFPU) CPUTYPE("Cortex-M7") ELITTLE + + + + + + + + + + + + + + + + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + CubeMX_Config\ + CubeMX_Config + 1 + 0 + 1 + 1 + 1 + ./CubeMX_Config/ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 13 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4107 + + 1 + STLink\ST-LINKIII-KEIL_SWO.dll + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 3 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + + + + + 1 + + + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + + + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + + + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + + + USE_HAL_DRIVER,STM32F767xx + + ../Inc;../Drivers/STM32F7xx_HAL_Driver/Inc;../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F7xx/Include;../Drivers/CMSIS/Include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Application/MDK-ARM + + + startup_stm32f767xx.s + 2 + startup_stm32f767xx.s + + + + + + ::CMSIS + + + + Drivers/STM32F7xx_HAL_Driver + + + stm32f7xx_hal_adc.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c + + + stm32f7xx_hal_adc_ex.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c + + + stm32f7xx_hal_cortex.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c + + + stm32f7xx_hal_dma2d.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c + + + stm32f7xx_hal_eth.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c + + + stm32f7xx_ll_fmc.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c + + + stm32f7xx_hal_sdram.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c + + + stm32f7xx_hal_ltdc.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c + + + stm32f7xx_hal_ltdc_ex.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c + + + stm32f7xx_hal_dsi.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c + + + stm32f7xx_hal_qspi.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c + + + stm32f7xx_ll_sdmmc.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c + + + stm32f7xx_hal_sd.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c + + + stm32f7xx_hal_tim.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c + + + stm32f7xx_hal_tim_ex.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c + + + stm32f7xx_hal_uart.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c + + + stm32f7xx_hal_rcc.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c + + + stm32f7xx_hal_rcc_ex.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c + + + stm32f7xx_hal_flash.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c + + + stm32f7xx_hal_flash_ex.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c + + + stm32f7xx_hal_gpio.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c + + + stm32f7xx_hal_dma.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c + + + stm32f7xx_hal_dma_ex.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c + + + stm32f7xx_hal_pwr.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c + + + stm32f7xx_hal_pwr_ex.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c + + + stm32f7xx_hal.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c + + + stm32f7xx_hal_i2c.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c + + + stm32f7xx_hal_i2c_ex.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c + + + stm32f7xx_hal_exti.c + 1 + ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c + + + + + Drivers/CMSIS + + + system_stm32f7xx.c + 1 + ../Src/system_stm32f7xx.c + + + + + Application/User + + + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + + + + + + main.c + 1 + ../Src/main.c + + + stm32f7xx_it.c + 1 + ../Src/stm32f7xx_it.c + + + stm32f7xx_hal_msp.c + 1 + ../Src/stm32f7xx_hal_msp.c + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/MDK-ARM/startup_stm32f767xx.s b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/MDK-ARM/startup_stm32f767xx.s new file mode 100644 index 0000000000..332954ec76 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/MDK-ARM/startup_stm32f767xx.s @@ -0,0 +1,517 @@ +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f767xx.s +;* Author : MCD Application Team +;* Description : STM32F767xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD 0 ; Reserved + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt + DCD SDMMC2_IRQHandler ; SDMMC2 + DCD CAN3_TX_IRQHandler ; CAN3 TX + DCD CAN3_RX0_IRQHandler ; CAN3 RX0 + DCD CAN3_RX1_IRQHandler ; CAN3 RX1 + DCD CAN3_SCE_IRQHandler ; CAN3 SCE + DCD JPEG_IRQHandler ; JPEG + DCD MDIOS_IRQHandler ; MDIOS +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT CAN3_TX_IRQHandler [WEAK] + EXPORT CAN3_RX0_IRQHandler [WEAK] + EXPORT CAN3_RX1_IRQHandler [WEAK] + EXPORT CAN3_SCE_IRQHandler [WEAK] + EXPORT JPEG_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +SAI2_IRQHandler +QUADSPI_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +DFSDM1_FLT3_IRQHandler +SDMMC2_IRQHandler +CAN3_TX_IRQHandler +CAN3_RX0_IRQHandler +CAN3_RX1_IRQHandler +CAN3_SCE_IRQHandler +JPEG_IRQHandler +MDIOS_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Src/main.c new file mode 100644 index 0000000000..50bede137d --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Src/main.c @@ -0,0 +1,642 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + ** This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +ADC_HandleTypeDef hadc1; + +DMA2D_HandleTypeDef hdma2d; + +ETH_HandleTypeDef heth; + +LTDC_HandleTypeDef hltdc; + +QSPI_HandleTypeDef hqspi; + +SD_HandleTypeDef hsd1; + +UART_HandleTypeDef huart1; + +SDRAM_HandleTypeDef hsdram1; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_USART1_UART_Init(void); +static void MX_ETH_Init(void); +static void MX_FMC_Init(void); +static void MX_QUADSPI_Init(void); +static void MX_SDMMC1_SD_Init(void); +static void MX_DMA2D_Init(void); +static void MX_LTDC_Init(void); +static void MX_ADC1_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_USART1_UART_Init(); + MX_ETH_Init(); + MX_FMC_Init(); + MX_QUADSPI_Init(); + MX_SDMMC1_SD_Init(); + MX_DMA2D_Init(); + MX_LTDC_Init(); + MX_ADC1_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 25; + RCC_OscInitStruct.PLL.PLLN = 432; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 9; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Activate the Over-Drive mode + */ + if (HAL_PWREx_EnableOverDrive() != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC|RCC_PERIPHCLK_USART1 + |RCC_PERIPHCLK_SDMMC1|RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.PLLSAI.PLLSAIN = 192; + PeriphClkInitStruct.PLLSAI.PLLSAIR = 3; + PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2; + PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV2; + PeriphClkInitStruct.PLLSAIDivQ = 1; + PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2; + PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; + PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_CLK48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief ADC1 Initialization Function + * @param None + * @retval None + */ +static void MX_ADC1_Init(void) +{ + + /* USER CODE BEGIN ADC1_Init 0 */ + + /* USER CODE END ADC1_Init 0 */ + + ADC_ChannelConfTypeDef sConfig = {0}; + + /* USER CODE BEGIN ADC1_Init 1 */ + + /* USER CODE END ADC1_Init 1 */ + /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) + */ + hadc1.Instance = ADC1; + hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; + hadc1.Init.Resolution = ADC_RESOLUTION_12B; + hadc1.Init.ScanConvMode = DISABLE; + hadc1.Init.ContinuousConvMode = DISABLE; + hadc1.Init.DiscontinuousConvMode = DISABLE; + hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; + hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hadc1.Init.NbrOfConversion = 1; + hadc1.Init.DMAContinuousRequests = DISABLE; + hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + if (HAL_ADC_Init(&hadc1) != HAL_OK) + { + Error_Handler(); + } + /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. + */ + sConfig.Channel = ADC_CHANNEL_5; + sConfig.Rank = ADC_REGULAR_RANK_1; + sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN ADC1_Init 2 */ + + /* USER CODE END ADC1_Init 2 */ + +} + +/** + * @brief DMA2D Initialization Function + * @param None + * @retval None + */ +static void MX_DMA2D_Init(void) +{ + + /* USER CODE BEGIN DMA2D_Init 0 */ + + /* USER CODE END DMA2D_Init 0 */ + + /* USER CODE BEGIN DMA2D_Init 1 */ + + /* USER CODE END DMA2D_Init 1 */ + hdma2d.Instance = DMA2D; + hdma2d.Init.Mode = DMA2D_M2M; + hdma2d.Init.ColorMode = DMA2D_OUTPUT_ARGB8888; + hdma2d.Init.OutputOffset = 0; + hdma2d.LayerCfg[1].InputOffset = 0; + hdma2d.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888; + hdma2d.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA; + hdma2d.LayerCfg[1].InputAlpha = 0; + hdma2d.LayerCfg[1].AlphaInverted = DMA2D_REGULAR_ALPHA; + hdma2d.LayerCfg[1].RedBlueSwap = DMA2D_RB_REGULAR; + if (HAL_DMA2D_Init(&hdma2d) != HAL_OK) + { + Error_Handler(); + } + if (HAL_DMA2D_ConfigLayer(&hdma2d, 1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN DMA2D_Init 2 */ + + /* USER CODE END DMA2D_Init 2 */ + +} + +/** + * @brief ETH Initialization Function + * @param None + * @retval None + */ +static void MX_ETH_Init(void) +{ + + /* USER CODE BEGIN ETH_Init 0 */ + + /* USER CODE END ETH_Init 0 */ + + uint8_t MACAddr[6] ; + + /* USER CODE BEGIN ETH_Init 1 */ + + /* USER CODE END ETH_Init 1 */ + heth.Instance = ETH; + heth.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE; + heth.Init.PhyAddress = LAN8742A_PHY_ADDRESS; + MACAddr[0] = 0x00; + MACAddr[1] = 0x80; + MACAddr[2] = 0xE1; + MACAddr[3] = 0x00; + MACAddr[4] = 0x00; + MACAddr[5] = 0x00; + heth.Init.MACAddr = &MACAddr[0]; + heth.Init.RxMode = ETH_RXPOLLING_MODE; + heth.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE; + heth.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII; + + /* USER CODE BEGIN MACADDRESS */ + + /* USER CODE END MACADDRESS */ + + if (HAL_ETH_Init(&heth) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN ETH_Init 2 */ + + /* USER CODE END ETH_Init 2 */ + +} + +/** + * @brief LTDC Initialization Function + * @param None + * @retval None + */ +static void MX_LTDC_Init(void) +{ + + /* USER CODE BEGIN LTDC_Init 0 */ + + /* USER CODE END LTDC_Init 0 */ + + LTDC_LayerCfgTypeDef pLayerCfg = {0}; + LTDC_LayerCfgTypeDef pLayerCfg1 = {0}; + + /* USER CODE BEGIN LTDC_Init 1 */ + + /* USER CODE END LTDC_Init 1 */ + hltdc.Instance = LTDC; + hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL; + hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL; + hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL; + hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC; + hltdc.Init.HorizontalSync = 7; + hltdc.Init.VerticalSync = 3; + hltdc.Init.AccumulatedHBP = 14; + hltdc.Init.AccumulatedVBP = 5; + hltdc.Init.AccumulatedActiveW = 654; + hltdc.Init.AccumulatedActiveH = 485; + hltdc.Init.TotalWidth = 660; + hltdc.Init.TotalHeigh = 487; + hltdc.Init.Backcolor.Blue = 0; + hltdc.Init.Backcolor.Green = 0; + hltdc.Init.Backcolor.Red = 0; + if (HAL_LTDC_Init(&hltdc) != HAL_OK) + { + Error_Handler(); + } + pLayerCfg.WindowX0 = 0; + pLayerCfg.WindowX1 = 0; + pLayerCfg.WindowY0 = 0; + pLayerCfg.WindowY1 = 0; + pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888; + pLayerCfg.Alpha = 0; + pLayerCfg.Alpha0 = 0; + pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_CA; + pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_CA; + pLayerCfg.FBStartAdress = 0; + pLayerCfg.ImageWidth = 0; + pLayerCfg.ImageHeight = 0; + pLayerCfg.Backcolor.Blue = 0; + pLayerCfg.Backcolor.Green = 0; + pLayerCfg.Backcolor.Red = 0; + if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK) + { + Error_Handler(); + } + pLayerCfg1.WindowX0 = 0; + pLayerCfg1.WindowX1 = 0; + pLayerCfg1.WindowY0 = 0; + pLayerCfg1.WindowY1 = 0; + pLayerCfg1.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888; + pLayerCfg1.Alpha = 0; + pLayerCfg1.Alpha0 = 0; + pLayerCfg1.BlendingFactor1 = LTDC_BLENDING_FACTOR1_CA; + pLayerCfg1.BlendingFactor2 = LTDC_BLENDING_FACTOR2_CA; + pLayerCfg1.FBStartAdress = 0; + pLayerCfg1.ImageWidth = 0; + pLayerCfg1.ImageHeight = 0; + pLayerCfg1.Backcolor.Blue = 0; + pLayerCfg1.Backcolor.Green = 0; + pLayerCfg1.Backcolor.Red = 0; + if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg1, 1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN LTDC_Init 2 */ + + /* USER CODE END LTDC_Init 2 */ + +} + +/** + * @brief QUADSPI Initialization Function + * @param None + * @retval None + */ +static void MX_QUADSPI_Init(void) +{ + + /* USER CODE BEGIN QUADSPI_Init 0 */ + + /* USER CODE END QUADSPI_Init 0 */ + + /* USER CODE BEGIN QUADSPI_Init 1 */ + + /* USER CODE END QUADSPI_Init 1 */ + /* QUADSPI parameter configuration*/ + hqspi.Instance = QUADSPI; + hqspi.Init.ClockPrescaler = 255; + hqspi.Init.FifoThreshold = 1; + hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_NONE; + hqspi.Init.FlashSize = 1; + hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_1_CYCLE; + hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0; + hqspi.Init.FlashID = QSPI_FLASH_ID_1; + hqspi.Init.DualFlash = QSPI_DUALFLASH_DISABLE; + if (HAL_QSPI_Init(&hqspi) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN QUADSPI_Init 2 */ + + /* USER CODE END QUADSPI_Init 2 */ + +} + +/** + * @brief SDMMC1 Initialization Function + * @param None + * @retval None + */ +static void MX_SDMMC1_SD_Init(void) +{ + + /* USER CODE BEGIN SDMMC1_Init 0 */ + + /* USER CODE END SDMMC1_Init 0 */ + + /* USER CODE BEGIN SDMMC1_Init 1 */ + + /* USER CODE END SDMMC1_Init 1 */ + hsd1.Instance = SDMMC1; + hsd1.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + hsd1.Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; + hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + hsd1.Init.BusWide = SDMMC_BUS_WIDE_1B; + hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + hsd1.Init.ClockDiv = 0; + if (HAL_SD_Init(&hsd1) != HAL_OK) + { + Error_Handler(); + } + if (HAL_SD_ConfigWideBusOperation(&hsd1, SDMMC_BUS_WIDE_4B) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SDMMC1_Init 2 */ + + /* USER CODE END SDMMC1_Init 2 */ + +} + +/** + * @brief USART1 Initialization Function + * @param None + * @retval None + */ +static void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + +/* FMC initialization function */ +static void MX_FMC_Init(void) +{ + FMC_SDRAM_TimingTypeDef SdramTiming; + + /** Perform the SDRAM1 memory initialization sequence + */ + hsdram1.Instance = FMC_SDRAM_DEVICE; + /* hsdram1.Init */ + hsdram1.Init.SDBank = FMC_SDRAM_BANK2; + hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8; + hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; + hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16; + hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; + hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_1; + hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; + hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_DISABLE; + hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE; + hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0; + /* SdramTiming */ + SdramTiming.LoadToActiveDelay = 16; + SdramTiming.ExitSelfRefreshDelay = 16; + SdramTiming.SelfRefreshTime = 16; + SdramTiming.RowCycleDelay = 16; + SdramTiming.WriteRecoveryTime = 16; + SdramTiming.RPDelay = 16; + SdramTiming.RCDDelay = 16; + + if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK) + { + Error_Handler( ); + } + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOI_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOH, GPIO_PIN_10, GPIO_PIN_RESET); + + /*Configure GPIO pin : PH10 */ + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c new file mode 100644 index 0000000000..a395939496 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c @@ -0,0 +1,981 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : stm32f7xx_hal_msp.c + * Description : This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + ** This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief ADC MSP Initialization +* This function configures the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspInit 0 */ + + /* USER CODE END ADC1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ADC1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**ADC1 GPIO Configuration + PA5 ------> ADC1_IN5 + */ + GPIO_InitStruct.Pin = GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN ADC1_MspInit 1 */ + + /* USER CODE END ADC1_MspInit 1 */ + } + +} + +/** +* @brief ADC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +{ + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspDeInit 0 */ + + /* USER CODE END ADC1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ADC1_CLK_DISABLE(); + + /**ADC1 GPIO Configuration + PA5 ------> ADC1_IN5 + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5); + + /* USER CODE BEGIN ADC1_MspDeInit 1 */ + + /* USER CODE END ADC1_MspDeInit 1 */ + } + +} + +/** +* @brief DMA2D MSP Initialization +* This function configures the hardware resources used in this example +* @param hdma2d: DMA2D handle pointer +* @retval None +*/ +void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) +{ + if(hdma2d->Instance==DMA2D) + { + /* USER CODE BEGIN DMA2D_MspInit 0 */ + + /* USER CODE END DMA2D_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_DMA2D_CLK_ENABLE(); + /* USER CODE BEGIN DMA2D_MspInit 1 */ + + /* USER CODE END DMA2D_MspInit 1 */ + } + +} + +/** +* @brief DMA2D MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hdma2d: DMA2D handle pointer +* @retval None +*/ +void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) +{ + if(hdma2d->Instance==DMA2D) + { + /* USER CODE BEGIN DMA2D_MspDeInit 0 */ + + /* USER CODE END DMA2D_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_DMA2D_CLK_DISABLE(); + /* USER CODE BEGIN DMA2D_MspDeInit 1 */ + + /* USER CODE END DMA2D_MspDeInit 1 */ + } + +} + +/** +* @brief ETH MSP Initialization +* This function configures the hardware resources used in this example +* @param heth: ETH handle pointer +* @retval None +*/ +void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(heth->Instance==ETH) + { + /* USER CODE BEGIN ETH_MspInit 0 */ + + /* USER CODE END ETH_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ETH_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**ETH GPIO Configuration + PC1 ------> ETH_MDC + PA1 ------> ETH_REF_CLK + PA2 ------> ETH_MDIO + PA7 ------> ETH_CRS_DV + PC4 ------> ETH_RXD0 + PC5 ------> ETH_RXD1 + PB11 ------> ETH_TX_EN + PB12 ------> ETH_TXD0 + PB13 ------> ETH_TXD1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN ETH_MspInit 1 */ + + /* USER CODE END ETH_MspInit 1 */ + } + +} + +/** +* @brief ETH MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param heth: ETH handle pointer +* @retval None +*/ +void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) +{ + if(heth->Instance==ETH) + { + /* USER CODE BEGIN ETH_MspDeInit 0 */ + + /* USER CODE END ETH_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ETH_CLK_DISABLE(); + + /**ETH GPIO Configuration + PC1 ------> ETH_MDC + PA1 ------> ETH_REF_CLK + PA2 ------> ETH_MDIO + PA7 ------> ETH_CRS_DV + PC4 ------> ETH_RXD0 + PC5 ------> ETH_RXD1 + PB11 ------> ETH_TX_EN + PB12 ------> ETH_TXD0 + PB13 ------> ETH_TXD1 + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5); + + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13); + + /* USER CODE BEGIN ETH_MspDeInit 1 */ + + /* USER CODE END ETH_MspDeInit 1 */ + } + +} + +/** +* @brief LTDC MSP Initialization +* This function configures the hardware resources used in this example +* @param hltdc: LTDC handle pointer +* @retval None +*/ +void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hltdc->Instance==LTDC) + { + /* USER CODE BEGIN LTDC_MspInit 0 */ + + /* USER CODE END LTDC_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_LTDC_CLK_ENABLE(); + + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOI_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**LTDC GPIO Configuration + PE4 ------> LTDC_B0 + PE5 ------> LTDC_G0 + PE6 ------> LTDC_G1 + PI9 ------> LTDC_VSYNC + PI10 ------> LTDC_HSYNC + PF10 ------> LTDC_DE + PH2 ------> LTDC_R0 + PH3 ------> LTDC_R1 + PA3 ------> LTDC_B5 + PB0 ------> LTDC_R3 + PB1 ------> LTDC_R6 + PH8 ------> LTDC_R2 + PG6 ------> LTDC_R7 + PG7 ------> LTDC_CLK + PC7 ------> LTDC_G6 + PA11 ------> LTDC_R4 + PA12 ------> LTDC_R5 + PH13 ------> LTDC_G2 + PH15 ------> LTDC_G4 + PI0 ------> LTDC_G5 + PI2 ------> LTDC_G7 + PD6 ------> LTDC_B2 + PG10 ------> LTDC_G3 + PG11 ------> LTDC_B3 + PG12 ------> LTDC_B1 + PB8 ------> LTDC_B6 + PB9 ------> LTDC_B7 + PI4 ------> LTDC_B4 + */ + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_2 + |GPIO_PIN_4; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_8|GPIO_PIN_13 + |GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_11|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF9_LTDC; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF9_LTDC; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN LTDC_MspInit 1 */ + + /* USER CODE END LTDC_MspInit 1 */ + } + +} + +/** +* @brief LTDC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hltdc: LTDC handle pointer +* @retval None +*/ +void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) +{ + if(hltdc->Instance==LTDC) + { + /* USER CODE BEGIN LTDC_MspDeInit 0 */ + + /* USER CODE END LTDC_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_LTDC_CLK_DISABLE(); + + /**LTDC GPIO Configuration + PE4 ------> LTDC_B0 + PE5 ------> LTDC_G0 + PE6 ------> LTDC_G1 + PI9 ------> LTDC_VSYNC + PI10 ------> LTDC_HSYNC + PF10 ------> LTDC_DE + PH2 ------> LTDC_R0 + PH3 ------> LTDC_R1 + PA3 ------> LTDC_B5 + PB0 ------> LTDC_R3 + PB1 ------> LTDC_R6 + PH8 ------> LTDC_R2 + PG6 ------> LTDC_R7 + PG7 ------> LTDC_CLK + PC7 ------> LTDC_G6 + PA11 ------> LTDC_R4 + PA12 ------> LTDC_R5 + PH13 ------> LTDC_G2 + PH15 ------> LTDC_G4 + PI0 ------> LTDC_G5 + PI2 ------> LTDC_G7 + PD6 ------> LTDC_B2 + PG10 ------> LTDC_G3 + PG11 ------> LTDC_B3 + PG12 ------> LTDC_B1 + PB8 ------> LTDC_B6 + PB9 ------> LTDC_B7 + PI4 ------> LTDC_B4 + */ + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6); + + HAL_GPIO_DeInit(GPIOI, GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_2 + |GPIO_PIN_4); + + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_10); + + HAL_GPIO_DeInit(GPIOH, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_8|GPIO_PIN_13 + |GPIO_PIN_15); + + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_3|GPIO_PIN_11|GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_8|GPIO_PIN_9); + + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_7); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_6); + + /* USER CODE BEGIN LTDC_MspDeInit 1 */ + + /* USER CODE END LTDC_MspDeInit 1 */ + } + +} + +/** +* @brief QSPI MSP Initialization +* This function configures the hardware resources used in this example +* @param hqspi: QSPI handle pointer +* @retval None +*/ +void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hqspi->Instance==QUADSPI) + { + /* USER CODE BEGIN QUADSPI_MspInit 0 */ + + /* USER CODE END QUADSPI_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_QSPI_CLK_ENABLE(); + + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**QUADSPI GPIO Configuration + PF6 ------> QUADSPI_BK1_IO3 + PF7 ------> QUADSPI_BK1_IO2 + PF8 ------> QUADSPI_BK1_IO0 + PF9 ------> QUADSPI_BK1_IO1 + PB2 ------> QUADSPI_CLK + PB6 ------> QUADSPI_BK1_NCS + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN QUADSPI_MspInit 1 */ + + /* USER CODE END QUADSPI_MspInit 1 */ + } + +} + +/** +* @brief QSPI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hqspi: QSPI handle pointer +* @retval None +*/ +void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi) +{ + if(hqspi->Instance==QUADSPI) + { + /* USER CODE BEGIN QUADSPI_MspDeInit 0 */ + + /* USER CODE END QUADSPI_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_QSPI_CLK_DISABLE(); + + /**QUADSPI GPIO Configuration + PF6 ------> QUADSPI_BK1_IO3 + PF7 ------> QUADSPI_BK1_IO2 + PF8 ------> QUADSPI_BK1_IO0 + PF9 ------> QUADSPI_BK1_IO1 + PB2 ------> QUADSPI_CLK + PB6 ------> QUADSPI_BK1_NCS + */ + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_2|GPIO_PIN_6); + + /* USER CODE BEGIN QUADSPI_MspDeInit 1 */ + + /* USER CODE END QUADSPI_MspDeInit 1 */ + } + +} + +/** +* @brief SD MSP Initialization +* This function configures the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspInit(SD_HandleTypeDef* hsd) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hsd->Instance==SDMMC1) + { + /* USER CODE BEGIN SDMMC1_MspInit 0 */ + + /* USER CODE END SDMMC1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SDMMC1_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**SDMMC1 GPIO Configuration + PC8 ------> SDMMC1_D0 + PC9 ------> SDMMC1_D1 + PC10 ------> SDMMC1_D2 + PC11 ------> SDMMC1_D3 + PC12 ------> SDMMC1_CK + PD2 ------> SDMMC1_CMD + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN SDMMC1_MspInit 1 */ + + /* USER CODE END SDMMC1_MspInit 1 */ + } + +} + +/** +* @brief SD MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hsd: SD handle pointer +* @retval None +*/ +void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) +{ + if(hsd->Instance==SDMMC1) + { + /* USER CODE BEGIN SDMMC1_MspDeInit 0 */ + + /* USER CODE END SDMMC1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SDMMC1_CLK_DISABLE(); + + /**SDMMC1 GPIO Configuration + PC8 ------> SDMMC1_D0 + PC9 ------> SDMMC1_D1 + PC10 ------> SDMMC1_D2 + PC11 ------> SDMMC1_D3 + PC12 ------> SDMMC1_CK + PD2 ------> SDMMC1_CMD + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); + + /* USER CODE BEGIN SDMMC1_MspDeInit 1 */ + + /* USER CODE END SDMMC1_MspDeInit 1 */ + } + +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); + + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + +} + +static uint32_t FMC_Initialized = 0; + +static void HAL_FMC_MspInit(void){ + /* USER CODE BEGIN FMC_MspInit 0 */ + + /* USER CODE END FMC_MspInit 0 */ + GPIO_InitTypeDef GPIO_InitStruct; + if (FMC_Initialized) { + return; + } + FMC_Initialized = 1; + /* Peripheral clock enable */ + __HAL_RCC_FMC_CLK_ENABLE(); + + /** FMC GPIO Configuration + PF0 ------> FMC_A0 + PF1 ------> FMC_A1 + PF2 ------> FMC_A2 + PF3 ------> FMC_A3 + PF4 ------> FMC_A4 + PF5 ------> FMC_A5 + PC0 ------> FMC_SDNWE + PF11 ------> FMC_SDNRAS + PF12 ------> FMC_A6 + PF13 ------> FMC_A7 + PF14 ------> FMC_A8 + PF15 ------> FMC_A9 + PG0 ------> FMC_A10 + PG1 ------> FMC_A11 + PE7 ------> FMC_D4 + PE8 ------> FMC_D5 + PE9 ------> FMC_D6 + PE10 ------> FMC_D7 + PE11 ------> FMC_D8 + PE12 ------> FMC_D9 + PE13 ------> FMC_D10 + PE14 ------> FMC_D11 + PE15 ------> FMC_D12 + PH6 ------> FMC_SDNE1 + PH7 ------> FMC_SDCKE1 + PD8 ------> FMC_D13 + PD9 ------> FMC_D14 + PD10 ------> FMC_D15 + PD14 ------> FMC_D0 + PD15 ------> FMC_D1 + PG4 ------> FMC_BA0 + PG5 ------> FMC_BA1 + PG8 ------> FMC_SDCLK + PD0 ------> FMC_D2 + PD1 ------> FMC_D3 + PG15 ------> FMC_SDNCAS + PE0 ------> FMC_NBL0 + PE1 ------> FMC_NBL1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 + |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5 + |GPIO_PIN_8|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 + |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN FMC_MspInit 1 */ + + /* USER CODE END FMC_MspInit 1 */ +} + +void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){ + /* USER CODE BEGIN SDRAM_MspInit 0 */ + + /* USER CODE END SDRAM_MspInit 0 */ + HAL_FMC_MspInit(); + /* USER CODE BEGIN SDRAM_MspInit 1 */ + + /* USER CODE END SDRAM_MspInit 1 */ +} + +static uint32_t FMC_DeInitialized = 0; + +static void HAL_FMC_MspDeInit(void){ + /* USER CODE BEGIN FMC_MspDeInit 0 */ + + /* USER CODE END FMC_MspDeInit 0 */ + if (FMC_DeInitialized) { + return; + } + FMC_DeInitialized = 1; + /* Peripheral clock enable */ + __HAL_RCC_FMC_CLK_DISABLE(); + + /** FMC GPIO Configuration + PF0 ------> FMC_A0 + PF1 ------> FMC_A1 + PF2 ------> FMC_A2 + PF3 ------> FMC_A3 + PF4 ------> FMC_A4 + PF5 ------> FMC_A5 + PC0 ------> FMC_SDNWE + PF11 ------> FMC_SDNRAS + PF12 ------> FMC_A6 + PF13 ------> FMC_A7 + PF14 ------> FMC_A8 + PF15 ------> FMC_A9 + PG0 ------> FMC_A10 + PG1 ------> FMC_A11 + PE7 ------> FMC_D4 + PE8 ------> FMC_D5 + PE9 ------> FMC_D6 + PE10 ------> FMC_D7 + PE11 ------> FMC_D8 + PE12 ------> FMC_D9 + PE13 ------> FMC_D10 + PE14 ------> FMC_D11 + PE15 ------> FMC_D12 + PH6 ------> FMC_SDNE1 + PH7 ------> FMC_SDCKE1 + PD8 ------> FMC_D13 + PD9 ------> FMC_D14 + PD10 ------> FMC_D15 + PD14 ------> FMC_D0 + PD15 ------> FMC_D1 + PG4 ------> FMC_BA0 + PG5 ------> FMC_BA1 + PG8 ------> FMC_SDCLK + PD0 ------> FMC_D2 + PD1 ------> FMC_D3 + PG15 ------> FMC_SDNCAS + PE0 ------> FMC_NBL0 + PE1 ------> FMC_NBL1 + */ + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 + |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); + + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0); + + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5 + |GPIO_PIN_8|GPIO_PIN_15); + + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1); + + HAL_GPIO_DeInit(GPIOH, GPIO_PIN_6|GPIO_PIN_7); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 + |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1); + + /* USER CODE BEGIN FMC_MspDeInit 1 */ + + /* USER CODE END FMC_MspDeInit 1 */ +} + +void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef* hsdram){ + /* USER CODE BEGIN SDRAM_MspDeInit 0 */ + + /* USER CODE END SDRAM_MspDeInit 0 */ + HAL_FMC_MspDeInit(); + /* USER CODE BEGIN SDRAM_MspDeInit 1 */ + + /* USER CODE END SDRAM_MspDeInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Src/stm32f7xx_it.c b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Src/stm32f7xx_it.c new file mode 100644 index 0000000000..fc333c38eb --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Src/stm32f7xx_it.c @@ -0,0 +1,218 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f7xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M7 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F7xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f7xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Src/system_stm32f7xx.c b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Src/system_stm32f7xx.c new file mode 100644 index 0000000000..cb4e56623f --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/CubeMX_Config/Src/system_stm32f7xx.c @@ -0,0 +1,278 @@ +/** + ****************************************************************************** + * @file system_stm32f7xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f7xx_system + * @{ + */ + +/** @addtogroup STM32F7xx_System_Private_Includes + * @{ + */ + +#include "stm32f7xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Variables + * @{ + */ + + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000; + const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/Kconfig b/bsp/stm32/stm32f767-fire-challenger-v1/board/Kconfig new file mode 100644 index 0000000000..6239d9e6f6 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/Kconfig @@ -0,0 +1,237 @@ +menu "Hardware Drivers Config" + +config SOC_STM32F767IG + bool + select SOC_SERIES_STM32F7 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + + config BSP_USING_USB_TO_USART + bool "Enable USB TO USART (uart1)" + select BSP_USING_UART + select BSP_USING_UART1 + default y + + config BSP_USING_RS232 + bool "Enable RS232 (uart2 pin conflict with Ethernet)" + select BSP_USING_UART + select BSP_USING_UART2 + default n + + config BSP_USING_SDRAM + bool "Enable SDRAM" + select BSP_USING_FMC + default n + + config BSP_USING_QSPI_FLASH + bool "Enable QSPI FLASH (W25Q128 qspi1)" + select BSP_USING_QSPI + select RT_USING_SFUD + select RT_SFUD_USING_QSPI + default n + + config BSP_USING_LCD + bool "Enable LCD" + select BSP_USING_LTDC + select BSP_USING_SDRAM + default n + + config BSP_USING_MPU6050 + bool "Enable MPU6050 (i2c4)" + select BSP_USING_I2C4 + select PKG_USING_MPU6XXX + default n + + config BSP_USING_POT + bool "Enable potentiometer" + select BSP_USING_ADC + select BSP_USING_ADC1 + default n + + config BSP_USING_SDCARD + bool "Enable SDCARD (sdio)" + select BSP_USING_SDIO + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + select RT_USING_PIN + default n + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y + + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART3 + bool "Enable UART3" + default n + + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + endif + + config BSP_USING_ON_CHIP_FLASH + bool "Enable on-chip FLASH" + default n + +menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n + + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + depends on BSP_USING_SPI2 + default n + + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + depends on BSP_USING_SPI2 + select BSP_SPI2_TX_USING_DMA + default n + + config BSP_USING_SPI5 + bool "Enable SPI5 BUS" + default n + + config BSP_SPI5_TX_USING_DMA + bool "Enable SPI5 TX DMA" + depends on BSP_USING_SPI5 + default n + + config BSP_SPI5_RX_USING_DMA + bool "Enable SPI5 RX DMA" + depends on BSP_USING_SPI5 + select BSP_SPI5_TX_USING_DMA + default n + endif + + config BSP_USING_QSPI + bool "Enable QSPI BUS" + select RT_USING_QSPI + select RT_USING_SPI + default n + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + endif + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1 + comment "Notice: PB6 --> 22; PB7 --> 23" + config BSP_I2C1_SCL_PIN + int "I2C1 scl pin number" + range 1 176 + default 22 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 1 176 + default 23 + endif + + menuconfig BSP_USING_ONCHIP_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + if BSP_USING_ONCHIP_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_LSE + + config BSP_RTC_USING_LSE + bool "RTC USING LSE" + + config BSP_RTC_USING_LSI + bool "RTC USING LSI" + endchoice + endif + + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n + + config BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + select RT_USING_DFS + default n + + config BSP_USING_FMC + bool + default n + + config BSP_USING_LTDC + bool + default n + + source "../libraries/HAL_Drivers/Kconfig" + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/SConscript b/bsp/stm32/stm32f767-fire-challenger-v1/board/SConscript new file mode 100644 index 0000000000..6dd2b9f997 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/SConscript @@ -0,0 +1,40 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +CubeMX_Config/Src/stm32f7xx_hal_msp.c +''') + +if GetDepend(['BSP_USING_ETH']): + src += Glob('ports/phy_reset.c') + +if GetDepend(['BSP_USING_QSPI_FLASH']): + src += Glob('ports/drv_qspi_flash.c') + +if GetDepend(['BSP_USING_SDCARD']): + src += Glob('ports/sdcard_port.c') + +path = [cwd] +path += [cwd + '/CubeMX_Config/Inc'] +path += [cwd + '/ports'] + +startup_path_prefix = SDK_LIB + +if rtconfig.CROSS_TOOL == 'gcc': + src += [startup_path_prefix + '/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f767xx.s'] +elif rtconfig.CROSS_TOOL == 'keil': + src += [startup_path_prefix + '/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/arm/startup_stm32f767xx.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src += [startup_path_prefix + '/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/startup_stm32f767xx.s'] + +CPPDEFINES = ['STM32F767xx'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') \ No newline at end of file diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/board.c b/bsp/stm32/stm32f767-fire-challenger-v1/board/board.c new file mode 100644 index 0000000000..de621405e1 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/board.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-06 SummerGift first version + */ + +#include "board.h" + +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /**Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 25; + RCC_OscInitStruct.PLL.PLLN = 432; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 9; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /**Activate the Over-Drive mode + */ + if (HAL_PWREx_EnableOverDrive() != HAL_OK) + { + Error_Handler(); + } + /**Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC|RCC_PERIPHCLK_USART1 + |RCC_PERIPHCLK_SDMMC1|RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.PLLSAI.PLLSAIN = 192; + PeriphClkInitStruct.PLLSAI.PLLSAIR = 3; + PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2; + PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV2; + PeriphClkInitStruct.PLLSAIDivQ = 1; + PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2; + PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; + PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_CLK48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } +} diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/board.h b/bsp/stm32/stm32f767-fire-challenger-v1/board/board.h new file mode 100644 index 0000000000..e9a1277849 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/board.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-5 SummerGift first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include +#include "drv_common.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define STM32_SRAM_SIZE (512) +#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) + +#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000) +#define STM32_FLASH_SIZE (1024 * 1024) +#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) + +#if defined(__CC_ARM) || defined(__CLANG_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END STM32_SRAM_END + +void SystemClock_Config(void); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.icf b/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.icf new file mode 100644 index 0000000000..9dc3dbbcd4 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.icf @@ -0,0 +1,28 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0400; +define symbol __ICFEDIT_size_heap__ = 0x0000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.lds b/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.lds new file mode 100644 index 0000000000..99ad02213b --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.lds @@ -0,0 +1,157 @@ +/* + * linker script for STM32F4xx with GNU ld + * bernard.xiong 2009-10-14 + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 512k /* 128K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.sct b/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.sct new file mode 100644 index 0000000000..e0bd37ed5e --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00100000 { ; load region size_region + ER_IROM1 0x08000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20020000 0x00060000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32f767-fire-challenger-v1/board/ports/drv_qspi_flash.c new file mode 100644 index 0000000000..a3091fd2eb --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/ports/drv_qspi_flash.c @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-27 zylx first version + */ + +#include +#include +#include +#include +#include + +#ifdef BSP_USING_QSPI_FLASH + +#include "spi_flash.h" +#include "spi_flash_sfud.h" + +char w25qxx_read_status_register2(struct rt_qspi_device *device) +{ + /* 0x35 read status register2 */ + char instruction = 0x35, status; + + rt_qspi_send_then_recv(device, &instruction, 1, &status, 1); + + return status; +} + +void w25qxx_write_enable(struct rt_qspi_device *device) +{ + /* 0x06 write enable */ + char instruction = 0x06; + + rt_qspi_send(device, &instruction, 1); +} + +void w25qxx_enter_qspi_mode(struct rt_qspi_device *device) +{ + char status = 0; + /* 0x38 enter qspi mode */ + char instruction = 0x38; + char write_status2_buf[2] = {0}; + + /* 0x31 write status register2 */ + write_status2_buf[0] = 0x31; + + status = w25qxx_read_status_register2(device); + if (!(status & 0x02)) + { + status |= 1 << 1; + w25qxx_write_enable(device); + write_status2_buf[1] = status; + rt_qspi_send(device, &write_status2_buf, 2); + rt_qspi_send(device, &instruction, 1); + rt_kprintf("flash already enter qspi mode\n"); + rt_thread_mdelay(10); + } +} + +static int rt_hw_qspi_flash_with_sfud_init(void) +{ + stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL); + + /* init w25q128 */ + if (RT_NULL == rt_sfud_flash_probe("W25Q128", "qspi10")) + { + return -RT_ERROR; + } + + return RT_EOK; +} +INIT_COMPONENT_EXPORT(rt_hw_qspi_flash_with_sfud_init); + +#endif/* BSP_USING_QSPI_FLASH */ diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/ports/fal_cfg.h b/bsp/stm32/stm32f767-fire-challenger-v1/board/ports/fal_cfg.h new file mode 100644 index 0000000000..5ddddaa2cd --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/ports/fal_cfg.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-5 SummerGift first version + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +#define FLASH_SIZE_GRANULARITY_32K (4 * 32 * 1024) +#define FLASH_SIZE_GRANULARITY_128K (128 * 1024) +#define FLASH_SIZE_GRANULARITY_256K (3 * 256 * 1024) + +#define STM32_FLASH_START_ADRESS_32K STM32_FLASH_START_ADRESS +#define STM32_FLASH_START_ADRESS_128K (STM32_FLASH_START_ADRESS_32K + FLASH_SIZE_GRANULARITY_32K) +#define STM32_FLASH_START_ADRESS_256K (STM32_FLASH_START_ADRESS_128K + FLASH_SIZE_GRANULARITY_128K) + +extern const struct fal_flash_dev stm32_onchip_flash_32k; +extern const struct fal_flash_dev stm32_onchip_flash_128k; +extern const struct fal_flash_dev stm32_onchip_flash_256k; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &stm32_onchip_flash_32k, \ + &stm32_onchip_flash_128k, \ + &stm32_onchip_flash_256k, \ +} +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG + +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WROD, "bootloader", "onchip_flash_32k", 0 , FLASH_SIZE_GRANULARITY_32K , 0}, \ + {FAL_PART_MAGIC_WROD, "param", "onchip_flash_128k", 0 , FLASH_SIZE_GRANULARITY_128K, 0}, \ + {FAL_PART_MAGIC_WROD, "app", "onchip_flash_256k", 0 , FLASH_SIZE_GRANULARITY_256K, 0}, \ +} + +#endif /* FAL_PART_HAS_TABLE_CFG */ +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/ports/lcd_port.h b/bsp/stm32/stm32f767-fire-challenger-v1/board/ports/lcd_port.h new file mode 100644 index 0000000000..8d297ec915 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/ports/lcd_port.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-01-08 zylx first version + */ + +#ifndef __LCD_PORT_H__ +#define __LCD_PORT_H__ + +/* fire 5 inch screen, 800 * 480 */ +#define LCD_WIDTH 800 +#define LCD_HEIGHT 480 +#define LCD_BITS_PER_PIXEL 16 +#define LCD_BUF_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_BITS_PER_PIXEL / 8) +#define LCD_PIXEL_FORMAT RTGRAPHIC_PIXEL_FORMAT_RGB565 + +#define LCD_HSYNC_WIDTH 2 +#define LCD_VSYNC_HEIGHT 2 +#define LCD_HBP 46 +#define LCD_VBP 23 +#define LCD_HFP 22 +#define LCD_VFP 22 + +#define LCD_BACKLIGHT_USING_GPIO +#define LCD_BL_GPIO_NUM GET_PIN(D, 7) +#define LCD_DISP_GPIO_NUM GET_PIN(D, 4) +/* fire 5 inch screen, 800 * 480 */ + +#endif /* __LCD_PORT_H__ */ diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/ports/phy_reset.c b/bsp/stm32/stm32f767-fire-challenger-v1/board/ports/phy_reset.c new file mode 100644 index 0000000000..8eaf6dcd5a --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/ports/phy_reset.c @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-23 flybreak first version + */ + +#include + +void phy_reset(void) +{ + /* The phy reset pin of this BSP circuit is connected to the chip reset pin, so no additional reset is required. */ +} diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/ports/sdcard_port.c b/bsp/stm32/stm32f767-fire-challenger-v1/board/ports/sdcard_port.c new file mode 100644 index 0000000000..f1a7b8c27f --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/ports/sdcard_port.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-13 balanceTWK add sdcard port file + */ + +#include + +#ifdef BSP_USING_SDCARD + +#include +#include +#include +#include "drv_gpio.h" + +#define DBG_TAG "app.card" +#define DBG_LVL DBG_INFO +#include + +#define WIFI_RESET_PIN GET_PIN(G, 9) + +int ewm1062_disable(void) +{ + rt_pin_mode(WIFI_RESET_PIN, PIN_MODE_OUTPUT); + rt_pin_write(WIFI_RESET_PIN,PIN_LOW); + return RT_EOK; +} +INIT_BOARD_EXPORT(ewm1062_disable); + +void sd_mount(void *parameter) +{ + while (1) + { + rt_thread_mdelay(500); + if(rt_device_find("sd0") != RT_NULL) + { + if (dfs_mount("sd0", "/", "elm", 0, 0) == RT_EOK) + { + LOG_I("sd card mount to '/'"); + break; + } + else + { + LOG_W("sd card mount to '/' failed!"); + } + } + } +} + +int stm32_sdcard_mount(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("sd_mount", sd_mount, RT_NULL, + 1024, RT_THREAD_PRIORITY_MAX - 2, 20); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + LOG_E("create sd_mount thread err!"); + } + return RT_EOK; +} +INIT_ENV_EXPORT(stm32_sdcard_mount); + +#endif /* BSP_USING_SDCARD */ + diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/board/ports/sdram_port.h b/bsp/stm32/stm32f767-fire-challenger-v1/board/ports/sdram_port.h new file mode 100644 index 0000000000..7f9485aa4a --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/board/ports/sdram_port.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-04 zylx The first version for STM32F4xx + */ + +#ifndef __SDRAM_PORT_H__ +#define __SDRAM_PORT_H__ + +/* parameters for sdram peripheral */ +/* Bank1 or Bank2 */ +#define SDRAM_TARGET_BANK 2 +/* stm32f7 Bank1:0XC0000000 Bank2:0XD0000000 */ +#define SDRAM_BANK_ADDR ((uint32_t)0XD0000000) +/* data width: 8, 16, 32 */ +#define SDRAM_DATA_WIDTH 16 +/* column bit numbers: 8, 9, 10, 11 */ +#define SDRAM_COLUMN_BITS 8 +/* row bit numbers: 11, 12, 13 */ +#define SDRAM_ROW_BITS 12 +/* cas latency clock number: 1, 2, 3 */ +#define SDRAM_CAS_LATENCY 2 +/* read pipe delay: 0, 1, 2 */ +#define SDRAM_RPIPE_DELAY 0 +/* clock divid: 2, 3 */ +#define SDCLOCK_PERIOD 2 +/* refresh rate counter */ +#define SDRAM_REFRESH_COUNT ((uint32_t)0x056A) +#define SDRAM_SIZE ((uint32_t)0x800000) + +/* Timing configuration for IS42S16400J */ +/* 108 MHz of SD clock frequency (216MHz/2) */ +/* TMRD: 2 Clock cycles */ +#define LOADTOACTIVEDELAY 2 +/* TXSR: 8x9.25ns */ +#define EXITSELFREFRESHDELAY 8 +/* TRAS: 5x9.25ns */ +#define SELFREFRESHTIME 5 +/* TRC: 7x9.25ns */ +#define ROWCYCLEDELAY 7 +/* TWR: 2 Clock cycles */ +#define WRITERECOVERYTIME 2 +/* TRP: 2x9.25ns */ +#define RPDELAY 2 +/* TRCD: 2x9.25ns */ +#define RCDDELAY 3 + +/* memory mode register */ +#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) +#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) +#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) +#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) +#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) +#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) + +#endif diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/figures/board.jpg b/bsp/stm32/stm32f767-fire-challenger-v1/figures/board.jpg new file mode 100644 index 0000000000..8dbe504ba5 Binary files /dev/null and b/bsp/stm32/stm32f767-fire-challenger-v1/figures/board.jpg differ diff --git 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### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + STM32F767IGTx + STMicroelectronics + Keil.STM32F7xx_DFP.2.11.0 + http://www.keil.com/pack + IRAM(0x20020000,0x60000) IRAM2(0x20000000,0x20000) IROM(0x08000000,0x100000) IROM2(0x00200000,0x100000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20020000 -FC1000 -FN2 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FF1STM32F7x_1024dual -FS18000000 -FL1100000 -FP0($$Device:STM32F767IGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FP1($$Device:STM32F767IGTx$CMSIS\Flash\STM32F7x_1024dual.FLM)) + 0 + $$Device:STM32F767IGTx$Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h + + + + + + + + + + $$Device:STM32F767IGTx$CMSIS\SVD\STM32F7x7_v1r2.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + 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..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_gpio.c + + + stm32f7xx_hal_exti.c + 1 + ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_exti.c + + + stm32f7xx_hal_cryp_ex.c + 1 + ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_cryp_ex.c + + + stm32f7xx_hal_dma_ex.c + 1 + ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma_ex.c + + + stm32f7xx_hal_qspi.c + 1 + ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_qspi.c + + + stm32f7xx_hal_cortex.c + 1 + ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_cortex.c + + + stm32f7xx_hal_dma.c + 1 + ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma.c + + + stm32f7xx_hal_spi.c + 1 + ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_spi.c + + + system_stm32f7xx.c + 1 + ..\libraries\STM32F7xx_HAL\CMSIS\Device\ST\STM32F7xx\Source\Templates\system_stm32f7xx.c + + + stm32f7xx_hal_uart.c + 1 + ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart.c + + + stm32f7xx_hal_pwr_ex.c + 1 + ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr_ex.c + + + stm32f7xx_hal_rng.c + 1 + ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rng.c + + + stm32f7xx_hal_crc_ex.c + 1 + ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_crc_ex.c + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/rtconfig.h b/bsp/stm32/stm32f767-fire-challenger-v1/rtconfig.h new file mode 100644 index 0000000000..8efa97ef30 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/rtconfig.h @@ -0,0 +1,189 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 + +/* kservice optimization */ + +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_USING_MEMHEAP_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40003 +#define ARCH_ARM +#define RT_USING_CPU_FFS +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M7 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_USING_MSH_ONLY +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +#define RT_USING_SPI + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_LIBC_USING_TIME + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* AI packages */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + +#define SOC_FAMILY_STM32 +#define SOC_SERIES_STM32F7 + +/* Hardware Drivers Config */ + +#define SOC_STM32F767IG + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_USB_TO_USART + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 +#define BSP_USING_SPI +#define BSP_USING_SPI1 +#define BSP_SPI1_TX_USING_DMA +#define BSP_SPI1_RX_USING_DMA + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/rtconfig.py b/bsp/stm32/stm32f767-fire-challenger-v1/rtconfig.py new file mode 100644 index 0000000000..ef6f4ff7c2 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/rtconfig.py @@ -0,0 +1,150 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m7' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m7 -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M7.fp.sp' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M7' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv5_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M7' + AFLAGS += ' --fpu VFPv5_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/template.ewp b/bsp/stm32/stm32f767-fire-challenger-v1/template.ewp new file mode 100644 index 0000000000..21c66ca0d0 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/template.ewp @@ -0,0 +1,2031 @@ + + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/template.eww b/bsp/stm32/stm32f767-fire-challenger-v1/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/template.uvoptx b/bsp/stm32/stm32f767-fire-challenger-v1/template.uvoptx new file mode 100644 index 0000000000..a7bce0b7d6 --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/template.uvoptx @@ -0,0 +1,192 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U59400616 -O14 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight JTAG-DP") -D00(5BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06451041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20020000 -FC1000 -FN1 -FF0STM32F7x_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F767IGTx$CMSIS\Flash\STM32F7x_1024.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN2 -FC1000 -FD20020000 -FF0STM32F7x_1024 -FF1STM32F7x_1024dual -FL0100000 -FL1100000 -FS08000000 -FS18000000 -FP0($$Device:STM32F767IGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FP1($$Device:STM32F767IGTx$CMSIS\Flash\STM32F7x_1024dual.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/stm32/stm32f767-fire-challenger-v1/template.uvprojx b/bsp/stm32/stm32f767-fire-challenger-v1/template.uvprojx new file mode 100644 index 0000000000..559eb8a0bd --- /dev/null +++ b/bsp/stm32/stm32f767-fire-challenger-v1/template.uvprojx @@ -0,0 +1,395 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32F767IGTx + STMicroelectronics + Keil.STM32F7xx_DFP.2.11.0 + http://www.keil.com/pack + IRAM(0x20020000,0x60000) IRAM2(0x20000000,0x20000) IROM(0x08000000,0x100000) IROM2(0x00200000,0x100000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20020000 -FC1000 -FN2 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FF1STM32F7x_1024dual -FS18000000 -FL1100000 -FP0($$Device:STM32F767IGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FP1($$Device:STM32F767IGTx$CMSIS\Flash\STM32F7x_1024dual.FLM)) + 0 + $$Device:STM32F767IGTx$Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h + + + + + + + + + + $$Device:STM32F767IGTx$CMSIS\SVD\STM32F7x7_v1r2.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 3 + 0 + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20020000 + 0x60000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x200000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20020000 + 0x60000 + + + 0 + 0x20000000 + 0x20000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + + + + + + + diff --git a/bsp/stm32/stm32f767-fire-challenger/.config b/bsp/stm32/stm32f767-fire-challenger/.config deleted file mode 100644 index d9bdefcf56..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/.config +++ /dev/null @@ -1,399 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=8 -# CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=4 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_USING_HOOK=y -CONFIG_RT_USING_IDLE_HOOK=y -CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=1024 -# CONFIG_RT_USING_TIMER_SOFT is not set -CONFIG_RT_DEBUG=y -CONFIG_RT_DEBUG_COLOR=y -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_SIGNALS is not set - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_MEMHEAP=y -# CONFIG_RT_USING_NOHEAP is not set -# CONFIG_RT_USING_SMALL_MEM is not set -# CONFIG_RT_USING_SLAB is not set -CONFIG_RT_USING_MEMHEAP_AS_HEAP=y -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40002 -CONFIG_ARCH_ARM=y -CONFIG_RT_USING_CPU_FFS=y -CONFIG_ARCH_ARM_CORTEX_M=y -CONFIG_ARCH_ARM_CORTEX_M7=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 -CONFIG_RT_MAIN_THREAD_PRIORITY=10 - -# -# C++ features -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Command shell -# -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_CMD_SIZE=80 -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_USING_MSH_DEFAULT=y -CONFIG_FINSH_USING_MSH_ONLY=y -CONFIG_FINSH_ARG_MAX=10 - -# -# Device virtual file system -# -# CONFIG_RT_USING_DFS is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -CONFIG_RT_PIPE_BUFSZ=512 -# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set -CONFIG_RT_USING_SERIAL=y -# CONFIG_RT_SERIAL_USING_DMA is not set -CONFIG_RT_SERIAL_RB_BUFSZ=64 -# CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_HWTIMER is not set -# CONFIG_RT_USING_CPUTIME is not set -# CONFIG_RT_USING_I2C is not set -CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_ADC is not set -# CONFIG_RT_USING_PWM is not set -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_MTD is not set -# CONFIG_RT_USING_PM is not set -# CONFIG_RT_USING_RTC is not set -# CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set -# CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_AUDIO is not set -# CONFIG_RT_USING_SENSOR is not set - -# -# Using Hardware Crypto drivers -# -# CONFIG_RT_USING_HWCRYPTO is not set - -# -# Using WiFi -# -# CONFIG_RT_USING_WIFI is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# POSIX layer and C standard library -# -# CONFIG_RT_USING_LIBC is not set -# CONFIG_RT_USING_PTHREADS is not set - -# -# Network -# - -# -# Socket abstraction layer -# -# CONFIG_RT_USING_SAL is not set - -# -# Network interface device -# -# CONFIG_RT_USING_NETDEV is not set - -# -# light weight TCP/IP stack -# -# CONFIG_RT_USING_LWIP is not set - -# -# Modbus master and slave stack -# -# CONFIG_RT_USING_MODBUS is not set - -# -# AT commands -# -# CONFIG_RT_USING_AT is not set - -# -# VBUS(Virtual Software BUS) -# -# CONFIG_RT_USING_VBUS is not set - -# -# Utilities -# -# CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set -# CONFIG_RT_USING_UTEST is not set -# CONFIG_RT_USING_LWP is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_WEBNET is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_LIBMODBUS is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_RW007 is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_AT_DEVICE is not set -# CONFIG_PKG_USING_ATSRV_SOCKET is not set -# CONFIG_PKG_USING_WIZNET is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTKIT is not set -# CONFIG_PKG_USING_NIMBLE is not set -# CONFIG_PKG_USING_OTA_DOWNLOADER is not set -# CONFIG_PKG_USING_IPMSG is not set -# CONFIG_PKG_USING_LSSDP is not set -# CONFIG_PKG_USING_AIRKISS_OPEN is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_libsodium is not set -# CONFIG_PKG_USING_TINYCRYPT is not set - -# -# language packages -# -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set - -# -# multimedia packages -# -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_STEMWIN is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_ADBD is not set - -# -# system packages -# -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_PERSIMMON is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_FAL is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_CMSIS is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_THREAD_POOL is not set - -# -# peripheral libraries and drivers -# -# CONFIG_PKG_USING_SENSORS_DRIVERS is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_AP3216C is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_U8G2 is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_WM_LIBRARIES is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_ROSSERIAL is not set -# CONFIG_PKG_USING_AT24CXX is not set -# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_AD7746 is not set -# CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set - -# -# miscellaneous packages -# -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_DSTR is not set -# CONFIG_PKG_USING_TINYFRAME is not set -# CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set -# CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_NNOM is not set -CONFIG_SOC_FAMILY_STM32=y -CONFIG_SOC_SERIES_STM32F7=y - -# -# Hardware Drivers Config -# -CONFIG_SOC_STM32F767IG=y - -# -# Onboard Peripheral Drivers -# -CONFIG_BSP_USING_USB_TO_USART=y -# CONFIG_BSP_USING_RS232 is not set -# CONFIG_BSP_USING_SDRAM is not set -# CONFIG_BSP_USING_QSPI_FLASH is not set -# CONFIG_BSP_USING_LCD is not set -# CONFIG_BSP_USING_MPU6050 is not set -# CONFIG_BSP_USING_POT is not set -# CONFIG_BSP_USING_SDCARD is not set - -# -# On-chip Peripheral Drivers -# -CONFIG_BSP_USING_GPIO=y -CONFIG_BSP_USING_UART=y -CONFIG_BSP_USING_UART1=y -# CONFIG_BSP_USING_UART2 is not set -# CONFIG_BSP_USING_UART3 is not set -# CONFIG_BSP_USING_ON_CHIP_FLASH is not set -# CONFIG_BSP_USING_SPI is not set -# CONFIG_BSP_USING_QSPI is not set -# CONFIG_BSP_USING_ADC is not set -# CONFIG_BSP_USING_I2C1 is not set -# CONFIG_BSP_USING_ONCHIP_RTC is not set -# CONFIG_BSP_USING_WDT is not set -# CONFIG_BSP_USING_SDIO is not set -# CONFIG_BSP_USING_FMC is not set -# CONFIG_BSP_USING_LTDC is not set - -# -# Board extended module Drivers -# diff --git a/bsp/stm32/stm32f767-fire-challenger/.gitignore b/bsp/stm32/stm32f767-fire-challenger/.gitignore deleted file mode 100644 index 7221bde019..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/.gitignore +++ /dev/null @@ -1,42 +0,0 @@ -*.pyc -*.map -*.dblite -*.elf -*.bin -*.hex -*.axf -*.exe -*.pdb -*.idb -*.ilk -*.old -build -Debug -documentation/html -packages/ -*~ -*.o -*.obj -*.out -*.bak -*.dep -*.lib -*.i -*.d -.DS_Stor* -.config 3 -.config 4 -.config 5 -Midea-X1 -*.uimg -GPATH -GRTAGS -GTAGS -.vscode -JLinkLog.txt -JLinkSettings.ini -DebugConfig/ -RTE/ -settings/ -*.uvguix* -cconfig.h diff --git a/bsp/stm32/stm32f767-fire-challenger/Kconfig b/bsp/stm32/stm32f767-fire-challenger/Kconfig deleted file mode 100644 index 8cbc7b71a8..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/Kconfig +++ /dev/null @@ -1,21 +0,0 @@ -mainmenu "RT-Thread Configuration" - -config BSP_DIR - string - option env="BSP_ROOT" - default "." - -config RTT_DIR - string - option env="RTT_ROOT" - default "../../.." - -config PKGS_DIR - string - option env="PKGS_ROOT" - default "packages" - -source "$RTT_DIR/Kconfig" -source "$PKGS_DIR/Kconfig" -source "../libraries/Kconfig" -source "board/Kconfig" diff --git a/bsp/stm32/stm32f767-fire-challenger/README.md b/bsp/stm32/stm32f767-fire-challenger/README.md deleted file mode 100644 index 3945c9acea..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/README.md +++ /dev/null @@ -1,131 +0,0 @@ -# STM32F767 挑战者开发板 BSP 说明 - -## 简介 - -本文档为 野火stm32f767 开发板的 BSP (板级支持包) 说明。 - -主要内容如下： - -- 开发板资源介绍 -- BSP 快速上手 -- 进阶使用方法 - -通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 - -## 开发板介绍 - -挑战者 STM32F767 是野火推出的一款基于 ARM Cortex-M7 内核的开发板，最高主频为 216Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32F767 的芯片性能。 - -开发板外观如下图所示： - -![board](figures/board.jpg) - -该开发板常用 **板载资源** 如下： - -- MCU：STM32f767，主频 216MHz，1MB FLASH ，512KB RAM ，16K CACHE -- 外部 RAM：型号，8MB -- 外部 FLASH：型号，16MB -- 常用外设 - - LED：RGB灯 - - 按键：2个，K1（兼具唤醒功能，PA0），K2（PC13） -- 常用接口：USB 转串口、SD 卡接口、以太网接口、LCD 接口 -- 调试接口，标准 JTAG/SWD - -开发板更多详细信息请参考野火 [STM32 挑战者开发板介绍](https://fire-stm32.taobao.com/index.htm)。 - -## 外设支持 - -本 BSP 目前对外设的支持情况如下： - -| **板载外设** | **支持情况** | **备注** | -| :---------------- | :----------: | :------------------------------------------------------ | -| USB 转串口 | 支持 | | -| RS232 | 支持 | 与以太网有引脚冲突 | -| QSPI Flash | 支持 | | -| 电位器 | 支持 | 使用 ADC1 | -| 以太网 | 暂不支持 | 移植中 | -| MPU6050六轴传感器 | 支持 | | -| SDRAM | 支持 | | -| LCD | 支持 | 支持 RGB 屏 | -| SD卡 | 支持 | | -| CAN | 即将支持 | | -| EMW1062 | 暂不支持 | | -| **片上外设** | **支持情况** | **备注** | -| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...176 | -| UART | 支持 | UART1/x/x | -| SPI | 支持 | SPI1/x/x | -| I2C | 支持 | 软件 I2C | -| ADC | 支持 | | -| RTC | 支持 | 支持外部晶振和内部低速时钟 | -| WDT | 支持 | | -| FLASH | 支持 | 已适配 [FAL](https://github.com/RT-Thread-packages/fal) | -| SDIO | 支持 | | -| PWM | 暂不支持 | 即将支持 | -| USB Device | 暂不支持 | 即将支持 | -| USB Host | 暂不支持 | 即将支持 | -| **扩展模块** | **支持情况** | **备注** | -| 暂无 | 暂不支持 | 暂不支持 | - -## 使用说明 - -使用说明分为如下两个章节： - -- 快速上手 - - 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 - -- 进阶使用 - - 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 - - -### 快速上手 - -本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 - -#### 硬件连接 - -使用数据线连接开发板到 PC，打开电源开关。 - -#### 编译下载 - -双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 - -> 工程默认配置使用 Jlink 仿真器下载程序，在通过 Jlink 连接开发板的基础上，点击下载按钮即可下载程序到开发板 - -#### 运行结果 - -下载程序成功之后，系统会自动运行，LED 闪烁。 - -连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: - -```bash - \ | / -- RT - Thread Operating System - / | \ 4.0.0 build Dec 10 2018 - 2006 - 2018 Copyright by rt-thread team -msh > -``` -### 进阶使用 - -此 BSP 默认只开启了 GPIO 和 串口1 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下： - -1. 在 bsp 下打开 env 工具。 - -2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 - -3. 输入`pkgs --update`命令更新软件包。 - -4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 - -本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。 - -## 注意事项 - -暂无 - -## 联系人信息 - -维护人: - -- [greedyhao](https://github.com/greedyhao), 邮箱： \ No newline at end of file diff --git a/bsp/stm32/stm32f767-fire-challenger/SConscript b/bsp/stm32/stm32f767-fire-challenger/SConscript deleted file mode 100644 index 20f7689c53..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/SConscript +++ /dev/null @@ -1,15 +0,0 @@ -# for module compiling -import os -Import('RTT_ROOT') -from building import * - -cwd = GetCurrentDir() -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/stm32/stm32f767-fire-challenger/SConstruct b/bsp/stm32/stm32f767-fire-challenger/SConstruct deleted file mode 100644 index 050835a35a..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/SConstruct +++ /dev/null @@ -1,60 +0,0 @@ -import os -import sys -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -TARGET = 'rt-thread.' + rtconfig.TARGET_EXT - -DefaultEnvironment(tools=[]) -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -if rtconfig.PLATFORM == 'iar': - env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) - env.Replace(ARFLAGS = ['']) - env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') - -Export('RTT_ROOT') -Export('rtconfig') - -SDK_ROOT = os.path.abspath('./') - -if os.path.exists(SDK_ROOT + '/libraries'): - libraries_path_prefix = SDK_ROOT + '/libraries' -else: - libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' - -SDK_LIB = libraries_path_prefix -Export('SDK_LIB') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) - -stm32_library = 'STM32F7xx_HAL' -rtconfig.BSP_LIBRARY_TYPE = stm32_library - -# include libraries -objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript'))) - -# include drivers -objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'))) - -# make a building -DoBuilding(TARGET, objs) diff --git a/bsp/stm32/stm32f767-fire-challenger/applications/SConscript b/bsp/stm32/stm32f767-fire-challenger/applications/SConscript deleted file mode 100644 index 6f66f7ab73..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/applications/SConscript +++ /dev/null @@ -1,12 +0,0 @@ -import rtconfig -from building import * - -cwd = GetCurrentDir() -CPPPATH = [cwd, str(Dir('#'))] -src = Split(""" -main.c -""") - -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/stm32/stm32f767-fire-challenger/applications/main.c b/bsp/stm32/stm32f767-fire-challenger/applications/main.c deleted file mode 100644 index 3570c667c9..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/applications/main.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-11-06 SummerGift first version - */ - -#include -#include -#include - -/* defined the LED0 pin: PH10 */ -#define LED0_PIN GET_PIN(H, 10) - -int main(void) -{ - /* set LED0 pin mode to output */ - rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - - while (1) - { - rt_pin_write(LED0_PIN, PIN_HIGH); - rt_thread_mdelay(500); - rt_pin_write(LED0_PIN, PIN_LOW); - rt_thread_mdelay(500); - } -} diff --git a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/.mxproject deleted file mode 100644 index 6c898500f2..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/.mxproject +++ /dev/null @@ -1,13 +0,0 @@ -[PreviousGenFiles] -HeaderPath=/media/greedyhao/Data/Files/github/my-rt-thread/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Inc -HeaderFiles=stm32f7xx_it.h;stm32f7xx_hal_conf.h;main.h; -SourcePath=/media/greedyhao/Data/Files/github/my-rt-thread/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Src -SourceFiles=stm32f7xx_it.c;stm32f7xx_hal_msp.c;main.c; - -[PreviousLibFiles] -LibFiles=Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dsi.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h;Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dsi.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h;Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h; - -[PreviousUsedKeilFiles] -SourceFiles=../Src/main.c;../Src/stm32f7xx_it.c;../Src/stm32f7xx_hal_msp.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;..//Src/system_stm32f7xx.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;..//Src/system_stm32f7xx.c;../Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;null; -HeaderPath=../Drivers/STM32F7xx_HAL_Driver/Inc;../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F7xx/Include;../Drivers/CMSIS/Include;../Inc; - diff --git a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/CubeMX_Config.ioc deleted file mode 100644 index c9b386e6ca..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/CubeMX_Config.ioc +++ /dev/null @@ -1,516 +0,0 @@ -#MicroXplorer Configuration settings - do not modify -ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_5 -ADC1.IPParameters=Rank-0\#ChannelRegularConversion,master,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag -ADC1.NbrOfConversionFlag=1 -ADC1.Rank-0\#ChannelRegularConversion=1 -ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES -ADC1.master=1 -ETH.IPParameters=MediaInterface -ETH.MediaInterface=ETH_MEDIA_INTERFACE_RMII -File.Version=6 -KeepUserPlacement=false -Mcu.Family=STM32F7 -Mcu.IP0=ADC1 -Mcu.IP1=CORTEX_M7 -Mcu.IP10=SYS -Mcu.IP11=USART1 -Mcu.IP2=DMA2D -Mcu.IP3=ETH -Mcu.IP4=FMC -Mcu.IP5=LTDC -Mcu.IP6=NVIC -Mcu.IP7=QUADSPI -Mcu.IP8=RCC -Mcu.IP9=SDMMC1 -Mcu.IPNb=12 -Mcu.Name=STM32F767I(G-I)Tx -Mcu.Package=LQFP176 -Mcu.Pin0=PE4 -Mcu.Pin1=PE5 -Mcu.Pin10=PF5 -Mcu.Pin11=PF6 -Mcu.Pin12=PF7 -Mcu.Pin13=PF8 -Mcu.Pin14=PF9 -Mcu.Pin15=PF10 -Mcu.Pin16=PH0/OSC_IN -Mcu.Pin17=PH1/OSC_OUT -Mcu.Pin18=PC0 -Mcu.Pin19=PC1 -Mcu.Pin2=PE6 -Mcu.Pin20=PA1 -Mcu.Pin21=PA2 -Mcu.Pin22=PH2 -Mcu.Pin23=PH3 -Mcu.Pin24=PA3 -Mcu.Pin25=PA5 -Mcu.Pin26=PA7 -Mcu.Pin27=PC4 -Mcu.Pin28=PC5 -Mcu.Pin29=PB0 -Mcu.Pin3=PI9 -Mcu.Pin30=PB1 -Mcu.Pin31=PB2 -Mcu.Pin32=PF11 -Mcu.Pin33=PF12 -Mcu.Pin34=PF13 -Mcu.Pin35=PF14 -Mcu.Pin36=PF15 -Mcu.Pin37=PG0 -Mcu.Pin38=PG1 -Mcu.Pin39=PE7 -Mcu.Pin4=PI10 -Mcu.Pin40=PE8 -Mcu.Pin41=PE9 -Mcu.Pin42=PE10 -Mcu.Pin43=PE11 -Mcu.Pin44=PE12 -Mcu.Pin45=PE13 -Mcu.Pin46=PE14 -Mcu.Pin47=PE15 -Mcu.Pin48=PB11 -Mcu.Pin49=PH6 -Mcu.Pin5=PF0 -Mcu.Pin50=PH7 -Mcu.Pin51=PH8 -Mcu.Pin52=PH10 -Mcu.Pin53=PB12 -Mcu.Pin54=PB13 -Mcu.Pin55=PD8 -Mcu.Pin56=PD9 -Mcu.Pin57=PD10 -Mcu.Pin58=PD14 -Mcu.Pin59=PD15 -Mcu.Pin6=PF1 -Mcu.Pin60=PG4 -Mcu.Pin61=PG5 -Mcu.Pin62=PG6 -Mcu.Pin63=PG7 -Mcu.Pin64=PG8 -Mcu.Pin65=PC7 -Mcu.Pin66=PC8 -Mcu.Pin67=PC9 -Mcu.Pin68=PA9 -Mcu.Pin69=PA10 -Mcu.Pin7=PF2 -Mcu.Pin70=PA11 -Mcu.Pin71=PA12 -Mcu.Pin72=PH13 -Mcu.Pin73=PH15 -Mcu.Pin74=PI0 -Mcu.Pin75=PI2 -Mcu.Pin76=PC10 -Mcu.Pin77=PC11 -Mcu.Pin78=PC12 -Mcu.Pin79=PD0 -Mcu.Pin8=PF3 -Mcu.Pin80=PD1 -Mcu.Pin81=PD2 -Mcu.Pin82=PD6 -Mcu.Pin83=PG10 -Mcu.Pin84=PG11 -Mcu.Pin85=PG12 -Mcu.Pin86=PG15 -Mcu.Pin87=PB6 -Mcu.Pin88=PB8 -Mcu.Pin89=PB9 -Mcu.Pin9=PF4 -Mcu.Pin90=PE0 -Mcu.Pin91=PE1 -Mcu.Pin92=PI4 -Mcu.Pin93=VP_DMA2D_VS_DMA2D -Mcu.Pin94=VP_SYS_VS_Systick -Mcu.PinsNb=95 -Mcu.ThirdPartyNb=0 -Mcu.UserConstants= -Mcu.UserName=STM32F767IGTx -MxCube.Version=5.1.0 -MxDb.Version=DB.5.0.10 -NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 -NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true -NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false -PA1.Mode=RMII -PA1.Signal=ETH_REF_CLK -PA10.Locked=true -PA10.Mode=Asynchronous -PA10.Signal=USART1_RX -PA11.GPIOParameters=GPIO_Speed -PA11.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PA11.Locked=true -PA11.Mode=RGB888 -PA11.Signal=LTDC_R4 -PA12.GPIOParameters=GPIO_Speed -PA12.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PA12.Locked=true -PA12.Mode=RGB888 -PA12.Signal=LTDC_R5 -PA2.Mode=RMII -PA2.Signal=ETH_MDIO -PA3.GPIOParameters=GPIO_Speed -PA3.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PA3.Mode=RGB888 -PA3.Signal=LTDC_B5 -PA5.Signal=ADCx_IN5 -PA7.Mode=RMII -PA7.Signal=ETH_CRS_DV -PA9.Locked=true -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX -PB0.GPIOParameters=GPIO_Speed -PB0.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PB0.Mode=RGB888 -PB0.Signal=LTDC_R3 -PB1.GPIOParameters=GPIO_Speed -PB1.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PB1.Mode=RGB888 -PB1.Signal=LTDC_R6 -PB11.Mode=RMII -PB11.Signal=ETH_TX_EN -PB12.Mode=RMII -PB12.Signal=ETH_TXD0 -PB13.Mode=RMII -PB13.Signal=ETH_TXD1 -PB2.Mode=Single Bank 1 -PB2.Signal=QUADSPI_CLK -PB6.Locked=true -PB6.Mode=Single Bank 1 -PB6.Signal=QUADSPI_BK1_NCS -PB8.GPIOParameters=GPIO_Speed -PB8.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PB8.Mode=RGB888 -PB8.Signal=LTDC_B6 -PB9.GPIOParameters=GPIO_Speed -PB9.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PB9.Mode=RGB888 -PB9.Signal=LTDC_B7 -PC0.Signal=FMC_SDNWE -PC1.Mode=RMII -PC1.Signal=ETH_MDC -PC10.Mode=SD_4_bits_Wide_bus -PC10.Signal=SDMMC1_D2 -PC11.Mode=SD_4_bits_Wide_bus -PC11.Signal=SDMMC1_D3 -PC12.Mode=SD_4_bits_Wide_bus -PC12.Signal=SDMMC1_CK -PC4.Mode=RMII -PC4.Signal=ETH_RXD0 -PC5.Mode=RMII -PC5.Signal=ETH_RXD1 -PC7.GPIOParameters=GPIO_Speed -PC7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PC7.Locked=true -PC7.Mode=RGB888 -PC7.Signal=LTDC_G6 -PC8.Mode=SD_4_bits_Wide_bus -PC8.Signal=SDMMC1_D0 -PC9.Mode=SD_4_bits_Wide_bus -PC9.Signal=SDMMC1_D1 -PCC.Checker=false -PCC.Line=STM32F7x7 -PCC.MCU=STM32F767I(G-I)Tx -PCC.PartNumber=STM32F767IGTx -PCC.Seq0=0 -PCC.Series=STM32F7 -PCC.Temperature=25 -PCC.Vdd=3.3 -PD0.Signal=FMC_D2_DA2 -PD1.Signal=FMC_D3_DA3 -PD10.Signal=FMC_D15_DA15 -PD14.Signal=FMC_D0_DA0 -PD15.Signal=FMC_D1_DA1 -PD2.Mode=SD_4_bits_Wide_bus -PD2.Signal=SDMMC1_CMD -PD6.GPIOParameters=GPIO_Speed -PD6.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PD6.Mode=RGB888 -PD6.Signal=LTDC_B2 -PD8.Signal=FMC_D13_DA13 -PD9.Signal=FMC_D14_DA14 -PE0.Signal=FMC_NBL0 -PE1.Signal=FMC_NBL1 -PE10.Signal=FMC_D7_DA7 -PE11.Signal=FMC_D8_DA8 -PE12.Signal=FMC_D9_DA9 -PE13.Signal=FMC_D10_DA10 -PE14.Signal=FMC_D11_DA11 -PE15.Signal=FMC_D12_DA12 -PE4.GPIOParameters=GPIO_Speed -PE4.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PE4.Mode=RGB888 -PE4.Signal=LTDC_B0 -PE5.GPIOParameters=GPIO_Speed -PE5.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PE5.Mode=RGB888 -PE5.Signal=LTDC_G0 -PE6.GPIOParameters=GPIO_Speed -PE6.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PE6.Mode=RGB888 -PE6.Signal=LTDC_G1 -PE7.Signal=FMC_D4_DA4 -PE8.Signal=FMC_D5_DA5 -PE9.Signal=FMC_D6_DA6 -PF0.Signal=FMC_A0 -PF1.Signal=FMC_A1 -PF10.GPIOParameters=GPIO_Speed -PF10.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PF10.Mode=RGB888 -PF10.Signal=LTDC_DE -PF11.Signal=FMC_SDNRAS -PF12.Signal=FMC_A6 -PF13.Signal=FMC_A7 -PF14.Signal=FMC_A8 -PF15.Signal=FMC_A9 -PF2.Signal=FMC_A2 -PF3.Signal=FMC_A3 -PF4.Signal=FMC_A4 -PF5.Signal=FMC_A5 -PF6.Mode=Single Bank 1 -PF6.Signal=QUADSPI_BK1_IO3 -PF7.Locked=true -PF7.Mode=Single Bank 1 -PF7.Signal=QUADSPI_BK1_IO2 -PF8.Mode=Single Bank 1 -PF8.Signal=QUADSPI_BK1_IO0 -PF9.Mode=Single Bank 1 -PF9.Signal=QUADSPI_BK1_IO1 -PG0.Signal=FMC_A10 -PG1.Signal=FMC_A11 -PG10.GPIOParameters=GPIO_Speed -PG10.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PG10.Locked=true -PG10.Mode=RGB888 -PG10.Signal=LTDC_G3 -PG11.GPIOParameters=GPIO_Speed -PG11.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PG11.Locked=true -PG11.Mode=RGB888 -PG11.Signal=LTDC_B3 -PG12.Mode=RGB888 -PG12.Signal=LTDC_B1 -PG15.Signal=FMC_SDNCAS -PG4.Signal=FMC_A14_BA0 -PG5.Signal=FMC_A15_BA1 -PG6.GPIOParameters=GPIO_Speed -PG6.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PG6.Mode=RGB888 -PG6.Signal=LTDC_R7 -PG7.GPIOParameters=GPIO_Speed -PG7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PG7.Mode=RGB888 -PG7.Signal=LTDC_CLK -PG8.Signal=FMC_SDCLK -PH0/OSC_IN.Mode=HSE-External-Oscillator -PH0/OSC_IN.Signal=RCC_OSC_IN -PH1/OSC_OUT.Mode=HSE-External-Oscillator -PH1/OSC_OUT.Signal=RCC_OSC_OUT -PH10.Locked=true -PH10.Signal=GPIO_Output -PH13.Locked=true -PH13.Mode=RGB888 -PH13.Signal=LTDC_G2 -PH15.Mode=RGB888 -PH15.Signal=LTDC_G4 -PH2.Mode=RGB888 -PH2.Signal=LTDC_R0 -PH3.Mode=RGB888 -PH3.Signal=LTDC_R1 -PH6.Mode=SdramChipSelect2_1 -PH6.Signal=FMC_SDNE1 -PH7.Mode=SdramChipSelect2_1 -PH7.Signal=FMC_SDCKE1 -PH8.Mode=RGB888 -PH8.Signal=LTDC_R2 -PI0.Locked=true -PI0.Mode=RGB888 -PI0.Signal=LTDC_G5 -PI10.Mode=RGB888 -PI10.Signal=LTDC_HSYNC -PI2.Mode=RGB888 -PI2.Signal=LTDC_G7 -PI4.Mode=RGB888 -PI4.Signal=LTDC_B4 -PI9.Mode=RGB888 -PI9.Signal=LTDC_VSYNC -PinOutPanel.RotationAngle=0 -ProjectManager.AskForMigrate=true -ProjectManager.BackupPrevious=false -ProjectManager.CompilerOptimize=6 -ProjectManager.ComputerToolchain=false -ProjectManager.CoupleFile=false -ProjectManager.CustomerFirmwarePackage= -ProjectManager.DefaultFWLocation=true -ProjectManager.DeletePrevious=true -ProjectManager.DeviceId=STM32F767IGTx -ProjectManager.FirmwarePackage=STM32Cube FW_F7 V1.15.0 -ProjectManager.FreePins=false -ProjectManager.HalAssertFull=false -ProjectManager.HeapSize=0x200 -ProjectManager.KeepUserCode=true -ProjectManager.LastFirmware=true -ProjectManager.LibraryCopy=0 -ProjectManager.MainLocation=Src -ProjectManager.NoMain=false -ProjectManager.PreviousToolchain= -ProjectManager.ProjectBuild=false -ProjectManager.ProjectFileName=CubeMX_Config.ioc -ProjectManager.ProjectName=CubeMX_Config -ProjectManager.StackSize=0x400 -ProjectManager.TargetToolchain=MDK-ARM V5 -ProjectManager.ToolChainLocation= -ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_ETH_Init-ETH-false-HAL-true,6-MX_FMC_Init-FMC-false-HAL-true,7-MX_QUADSPI_Init-QUADSPI-false-HAL-true,8-MX_SDMMC1_SD_Init-SDMMC1-false-HAL-true,9-MX_DMA2D_Init-DMA2D-false-HAL-true,10-MX_LTDC_Init-LTDC-false-HAL-true,11-MX_ADC1_Init-ADC1-false-HAL-true -RCC.AHBFreq_Value=216000000 -RCC.APB1CLKDivider=RCC_HCLK_DIV4 -RCC.APB1Freq_Value=54000000 -RCC.APB1TimFreq_Value=108000000 -RCC.APB2CLKDivider=RCC_HCLK_DIV2 -RCC.APB2Freq_Value=108000000 -RCC.APB2TimFreq_Value=216000000 -RCC.CECFreq_Value=32786.88524590164 -RCC.CortexFreq_Value=216000000 -RCC.DFSDMAudioFreq_Value=96000000 -RCC.DFSDMFreq_Value=108000000 -RCC.EthernetFreq_Value=216000000 -RCC.FCLKCortexFreq_Value=216000000 -RCC.FamilyName=M -RCC.HCLKFreq_Value=216000000 -RCC.HSE_VALUE=25000000 -RCC.HSI_VALUE=16000000 -RCC.I2C1Freq_Value=54000000 -RCC.I2C2Freq_Value=54000000 -RCC.I2C3Freq_Value=54000000 -RCC.I2C4Freq_Value=54000000 -RCC.I2SFreq_Value=96000000 -RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,DFSDMAudioFreq_Value,DFSDMFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LCDTFTFreq_Value,LPTIM1Freq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SRoutputFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLQoutputFreq_Value,PLLRFreq_Value,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIR,PLLSAIRCLKFreq_Value,PLLSAIoutputFreq_Value,PLLSourceVirtual,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC2Freq_Value,SDMMCClockSelection,SDMMCFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value -RCC.LCDTFTFreq_Value=32000000 -RCC.LPTIM1Freq_Value=54000000 -RCC.LSE_VALUE=32768 -RCC.LSI_VALUE=32000 -RCC.MCO2PinFreq_Value=216000000 -RCC.PLLCLKFreq_Value=216000000 -RCC.PLLI2SPCLKFreq_Value=96000000 -RCC.PLLI2SQCLKFreq_Value=96000000 -RCC.PLLI2SRCLKFreq_Value=96000000 -RCC.PLLI2SRoutputFreq_Value=96000000 -RCC.PLLM=25 -RCC.PLLN=432 -RCC.PLLQ=9 -RCC.PLLQCLKFreq_Value=48000000 -RCC.PLLQoutputFreq_Value=48000000 -RCC.PLLRFreq_Value=216000000 -RCC.PLLSAIPCLKFreq_Value=96000000 -RCC.PLLSAIQCLKFreq_Value=96000000 -RCC.PLLSAIR=3 -RCC.PLLSAIRCLKFreq_Value=64000000 -RCC.PLLSAIoutputFreq_Value=96000000 -RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE -RCC.RNGFreq_Value=48000000 -RCC.SAI1Freq_Value=96000000 -RCC.SAI2Freq_Value=96000000 -RCC.SDMMC2Freq_Value=216000000 -RCC.SDMMCClockSelection=RCC_SDMMC1CLKSOURCE_CLK48 -RCC.SDMMCFreq_Value=48000000 -RCC.SPDIFRXFreq_Value=96000000 -RCC.SYSCLKFreq_VALUE=216000000 -RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK -RCC.UART4Freq_Value=54000000 -RCC.UART5Freq_Value=54000000 -RCC.UART7Freq_Value=54000000 -RCC.UART8Freq_Value=54000000 -RCC.USART1Freq_Value=108000000 -RCC.USART2Freq_Value=54000000 -RCC.USART3Freq_Value=54000000 -RCC.USART6Freq_Value=108000000 -RCC.USBFreq_Value=48000000 -RCC.VCOI2SOutputFreq_Value=192000000 -RCC.VCOInputFreq_Value=1000000 -RCC.VCOOutputFreq_Value=432000000 -RCC.VCOSAIOutputFreq_Value=192000000 -SH.ADCx_IN5.0=ADC1_IN5,IN5 -SH.ADCx_IN5.ConfNb=1 -SH.FMC_A0.0=FMC_A0,12b-sda1 -SH.FMC_A0.ConfNb=1 -SH.FMC_A1.0=FMC_A1,12b-sda1 -SH.FMC_A1.ConfNb=1 -SH.FMC_A10.0=FMC_A10,12b-sda1 -SH.FMC_A10.ConfNb=1 -SH.FMC_A11.0=FMC_A11,12b-sda1 -SH.FMC_A11.ConfNb=1 -SH.FMC_A14_BA0.0=FMC_BA0,FourSdramBanks1 -SH.FMC_A14_BA0.ConfNb=1 -SH.FMC_A15_BA1.0=FMC_BA1,FourSdramBanks1 -SH.FMC_A15_BA1.ConfNb=1 -SH.FMC_A2.0=FMC_A2,12b-sda1 -SH.FMC_A2.ConfNb=1 -SH.FMC_A3.0=FMC_A3,12b-sda1 -SH.FMC_A3.ConfNb=1 -SH.FMC_A4.0=FMC_A4,12b-sda1 -SH.FMC_A4.ConfNb=1 -SH.FMC_A5.0=FMC_A5,12b-sda1 -SH.FMC_A5.ConfNb=1 -SH.FMC_A6.0=FMC_A6,12b-sda1 -SH.FMC_A6.ConfNb=1 -SH.FMC_A7.0=FMC_A7,12b-sda1 -SH.FMC_A7.ConfNb=1 -SH.FMC_A8.0=FMC_A8,12b-sda1 -SH.FMC_A8.ConfNb=1 -SH.FMC_A9.0=FMC_A9,12b-sda1 -SH.FMC_A9.ConfNb=1 -SH.FMC_D0_DA0.0=FMC_D0,sd-16b-d1 -SH.FMC_D0_DA0.ConfNb=1 -SH.FMC_D10_DA10.0=FMC_D10,sd-16b-d1 -SH.FMC_D10_DA10.ConfNb=1 -SH.FMC_D11_DA11.0=FMC_D11,sd-16b-d1 -SH.FMC_D11_DA11.ConfNb=1 -SH.FMC_D12_DA12.0=FMC_D12,sd-16b-d1 -SH.FMC_D12_DA12.ConfNb=1 -SH.FMC_D13_DA13.0=FMC_D13,sd-16b-d1 -SH.FMC_D13_DA13.ConfNb=1 -SH.FMC_D14_DA14.0=FMC_D14,sd-16b-d1 -SH.FMC_D14_DA14.ConfNb=1 -SH.FMC_D15_DA15.0=FMC_D15,sd-16b-d1 -SH.FMC_D15_DA15.ConfNb=1 -SH.FMC_D1_DA1.0=FMC_D1,sd-16b-d1 -SH.FMC_D1_DA1.ConfNb=1 -SH.FMC_D2_DA2.0=FMC_D2,sd-16b-d1 -SH.FMC_D2_DA2.ConfNb=1 -SH.FMC_D3_DA3.0=FMC_D3,sd-16b-d1 -SH.FMC_D3_DA3.ConfNb=1 -SH.FMC_D4_DA4.0=FMC_D4,sd-16b-d1 -SH.FMC_D4_DA4.ConfNb=1 -SH.FMC_D5_DA5.0=FMC_D5,sd-16b-d1 -SH.FMC_D5_DA5.ConfNb=1 -SH.FMC_D6_DA6.0=FMC_D6,sd-16b-d1 -SH.FMC_D6_DA6.ConfNb=1 -SH.FMC_D7_DA7.0=FMC_D7,sd-16b-d1 -SH.FMC_D7_DA7.ConfNb=1 -SH.FMC_D8_DA8.0=FMC_D8,sd-16b-d1 -SH.FMC_D8_DA8.ConfNb=1 -SH.FMC_D9_DA9.0=FMC_D9,sd-16b-d1 -SH.FMC_D9_DA9.ConfNb=1 -SH.FMC_NBL0.0=FMC_NBL0,Sd2ByteEnable1 -SH.FMC_NBL0.ConfNb=1 -SH.FMC_NBL1.0=FMC_NBL1,Sd2ByteEnable1 -SH.FMC_NBL1.ConfNb=1 -SH.FMC_SDCLK.0=FMC_SDCLK,12b-sda1 -SH.FMC_SDCLK.ConfNb=1 -SH.FMC_SDNCAS.0=FMC_SDNCAS,12b-sda1 -SH.FMC_SDNCAS.ConfNb=1 -SH.FMC_SDNRAS.0=FMC_SDNRAS,12b-sda1 -SH.FMC_SDNRAS.ConfNb=1 -SH.FMC_SDNWE.0=FMC_SDNWE,12b-sda1 -SH.FMC_SDNWE.ConfNb=1 -USART1.IPParameters=VirtualMode-Asynchronous -USART1.VirtualMode-Asynchronous=VM_ASYNC -VP_DMA2D_VS_DMA2D.Mode=DMA2D_Activate -VP_DMA2D_VS_DMA2D.Signal=DMA2D_VS_DMA2D -VP_SYS_VS_Systick.Mode=SysTick -VP_SYS_VS_Systick.Signal=SYS_VS_Systick -board=custom diff --git a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Inc/main.h b/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Inc/main.h deleted file mode 100644 index 03c0f13fc7..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Inc/main.h +++ /dev/null @@ -1,91 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file : main.h - * @brief : Header for main.c file. - * This file contains the common defines of the application. - ****************************************************************************** - ** This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * COPYRIGHT(c) 2018 STMicroelectronics - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MAIN_H -#define __MAIN_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Exported types ------------------------------------------------------------*/ -/* USER CODE BEGIN ET */ - -/* USER CODE END ET */ - -/* Exported constants --------------------------------------------------------*/ -/* USER CODE BEGIN EC */ - -/* USER CODE END EC */ - -/* Exported macro ------------------------------------------------------------*/ -/* USER CODE BEGIN EM */ - -/* USER CODE END EM */ - -/* Exported functions prototypes ---------------------------------------------*/ -void Error_Handler(void); - -/* USER CODE BEGIN EFP */ - -/* USER CODE END EFP */ - -/* Private defines -----------------------------------------------------------*/ -/* USER CODE BEGIN Private defines */ - -/* USER CODE END Private defines */ - -#ifdef __cplusplus -} -#endif - -#endif /* __MAIN_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h b/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h deleted file mode 100644 index f00413fa52..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h +++ /dev/null @@ -1,458 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_conf.h - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2019 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_CONF_H -#define __STM32F7xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED - -#define HAL_ADC_MODULE_ENABLED -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA2D_MODULE_ENABLED -#define HAL_ETH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -#define HAL_SDRAM_MODULE_ENABLED -/* #define HAL_HASH_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -#define HAL_LTDC_MODULE_ENABLED -#define HAL_QSPI_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -#define HAL_SD_MODULE_ENABLED -/* #define HAL_MMC_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_SPI_MODULE_ENABLED */ -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -/* #define HAL_JPEG_MODULE_ENABLED */ -/* #define HAL_MDIOS_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_EXTI_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -#define HAL_EXTI_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_I2C_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 0U -#define ART_ACCLERATOR_ENABLE 0U /* To enable instruction cache and prefetch */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* LAN8742A_PHY_ADDRESS Address*/ -#define LAN8742A_PHY_ADDRESS 1 -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) - -#define PHY_READ_TO ((uint32_t)0x0000FFFFU) -#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ -#define PHY_SR ((uint16_t)0x1FU) /*!< PHY status register Offset */ - -#define PHY_SPEED_STATUS ((uint16_t)0x0004U) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0010U) /*!< PHY Duplex mask */ - -#define PHY_ISFR ((uint16_t)0x001DU) /*!< PHY Interrupt Source Flag register Offset */ -#define PHY_ISFR_INT4 ((uint16_t)0x000BU) /*!< PHY Link down inturrupt */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 0U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f7xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f7xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f7xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f7xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f7xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f7xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f7xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f7xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f7xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f7xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f7xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f7xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f7xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f7xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f7xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f7xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f7xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f7xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f7xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f7xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f7xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f7xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f7xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f7xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f7xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f7xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f7xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f7xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f7xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f7xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f7xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f7xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f7xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f7xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f7xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f7xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f7xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f7xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f7xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f7xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f7xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f7xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f7xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f7xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_JPEG_MODULE_ENABLED - #include "stm32f7xx_hal_jpeg.h" -#endif /* HAL_JPEG_MODULE_ENABLED */ - -#ifdef HAL_MDIOS_MODULE_ENABLED - #include "stm32f7xx_hal_mdios.h" -#endif /* HAL_MDIOS_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f7xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Inc/stm32f7xx_it.h b/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Inc/stm32f7xx_it.h deleted file mode 100644 index a398e3c63b..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Inc/stm32f7xx_it.h +++ /dev/null @@ -1,84 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file stm32f7xx_it.h - * @brief This file contains the headers of the interrupt handlers. - ****************************************************************************** - * - * COPYRIGHT(c) 2018 STMicroelectronics - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_IT_H -#define __STM32F7xx_IT_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Exported types ------------------------------------------------------------*/ -/* USER CODE BEGIN ET */ - -/* USER CODE END ET */ - -/* Exported constants --------------------------------------------------------*/ -/* USER CODE BEGIN EC */ - -/* USER CODE END EC */ - -/* Exported macro ------------------------------------------------------------*/ -/* USER CODE BEGIN EM */ - -/* USER CODE END EM */ - -/* Exported functions prototypes ---------------------------------------------*/ -void NMI_Handler(void); -void HardFault_Handler(void); -void MemManage_Handler(void); -void BusFault_Handler(void); -void UsageFault_Handler(void); -void SVC_Handler(void); -void DebugMon_Handler(void); -void PendSV_Handler(void); -void SysTick_Handler(void); -/* USER CODE BEGIN EFP */ - -/* USER CODE END EFP */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_IT_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/MDK-ARM/CubeMX_Config.uvoptx b/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/MDK-ARM/CubeMX_Config.uvoptx deleted file mode 100644 index 565b317696..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/MDK-ARM/CubeMX_Config.uvoptx +++ /dev/null @@ -1,133 +0,0 @@ - - - - CubeMX_Config - 0x4 - ARM-ADS - - 216000000 - - 1 - 1 - 0 - 1 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 0 - 0 - 1 - - 0 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - 13 - - - - - - - - - - - STLink\ST-LINKIII-KEIL_SWO.dll - - - - 0 - ST-LINKIII-KEIL_SWO - -U-O142 -O2254 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F7x_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F767IG$Flash\STM32F7x_1024.FLM) -FF1STM32F7x_TCM -FS1200000 -FL1100000 -FP1($$Device:STM32F767IG$Flash\STM32F7x_TCM.FLM) - - - 0 - - -U-O142 -O2254 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F7x_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F767IG$Flash\STM32F7x_1024.FLM) -FF1STM32F7x_TCM -FS1200000 -FL1100000 -FP1($$Device:STM32F767IG$Flash\STM32F7x_TCM.FLM) - - - - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - diff --git a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/MDK-ARM/CubeMX_Config.uvprojx b/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/MDK-ARM/CubeMX_Config.uvprojx deleted file mode 100644 index 06c86a1736..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/MDK-ARM/CubeMX_Config.uvprojx +++ /dev/null @@ -1,648 +0,0 @@ - - - 1.1 - -
### uVision Project, (C) Keil Software
- - - - CubeMX_Config - 0x4 - ARM-ADS - - - STM32F767IGTx - STMicroelectronics - IRAM(0x20000000-0x2007FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(12000000) FPU3(DFPU) CPUTYPE("Cortex-M7") ELITTLE - - - - - - - - - - - - - - - - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - CubeMX_Config\ - CubeMX_Config - 1 - 0 - 1 - 1 - 1 - ./CubeMX_Config/ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - - - - SARMCM3.DLL - -REMAP -MPU - DCM.DLL - -pCM7 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM7 - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - - 0 - 13 - - - - - - - - - - - - - - STLink\ST-LINKIII-KEIL_SWO.dll - - - - - 1 - 0 - 0 - 1 - 1 - 4107 - - 1 - STLink\ST-LINKIII-KEIL_SWO.dll - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M7" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 3 - 0 - 0 - 8 - 1 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - - - - - 1 - - - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - - - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - - - - - 0 - 0x0 - 0x0 - - - - - - 1 - 4 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 1 - 0 - - - USE_HAL_DRIVER,STM32F767xx - - ../Inc;../Drivers/STM32F7xx_HAL_Driver/Inc;../Drivers/STM32F7xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F7xx/Include;../Drivers/CMSIS/Include - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - - - - - - - - - - - - Application/MDK-ARM - - - startup_stm32f767xx.s - 2 - startup_stm32f767xx.s - - - - - - ::CMSIS - - - - Drivers/STM32F7xx_HAL_Driver - - - stm32f7xx_hal_adc.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c - - - stm32f7xx_hal_adc_ex.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c - - - stm32f7xx_hal_cortex.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c - - - stm32f7xx_hal_dma2d.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c - - - stm32f7xx_hal_eth.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c - - - stm32f7xx_ll_fmc.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c - - - stm32f7xx_hal_sdram.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c - - - stm32f7xx_hal_ltdc.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c - - - stm32f7xx_hal_ltdc_ex.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c - - - stm32f7xx_hal_dsi.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c - - - stm32f7xx_hal_qspi.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c - - - stm32f7xx_ll_sdmmc.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c - - - stm32f7xx_hal_sd.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c - - - stm32f7xx_hal_tim.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c - - - stm32f7xx_hal_tim_ex.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c - - - stm32f7xx_hal_uart.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c - - - stm32f7xx_hal_rcc.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c - - - stm32f7xx_hal_rcc_ex.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c - - - stm32f7xx_hal_flash.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c - - - stm32f7xx_hal_flash_ex.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c - - - stm32f7xx_hal_gpio.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c - - - stm32f7xx_hal_dma.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c - - - stm32f7xx_hal_dma_ex.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c - - - stm32f7xx_hal_pwr.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c - - - stm32f7xx_hal_pwr_ex.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c - - - stm32f7xx_hal.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c - - - stm32f7xx_hal_i2c.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c - - - stm32f7xx_hal_i2c_ex.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c - - - stm32f7xx_hal_exti.c - 1 - ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c - - - - - Drivers/CMSIS - - - system_stm32f7xx.c - 1 - ../Src/system_stm32f7xx.c - - - - - Application/User - - - - - 2 - 0 - 0 - 0 - 0 - 1 - 2 - 2 - 2 - 2 - 11 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - - - - - - main.c - 1 - ../Src/main.c - - - stm32f7xx_it.c - 1 - ../Src/stm32f7xx_it.c - - - stm32f7xx_hal_msp.c - 1 - ../Src/stm32f7xx_hal_msp.c - - - - - - - - - - - - - - - - - - - - diff --git a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/MDK-ARM/startup_stm32f767xx.s b/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/MDK-ARM/startup_stm32f767xx.s deleted file mode 100644 index 332954ec76..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/MDK-ARM/startup_stm32f767xx.s +++ /dev/null @@ -1,517 +0,0 @@ -;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** -;* File Name : startup_stm32f767xx.s -;* Author : MCD Application Team -;* Description : STM32F767xx devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM7 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD RNG_IRQHandler ; Rng - DCD FPU_IRQHandler ; FPU - DCD UART7_IRQHandler ; UART7 - DCD UART8_IRQHandler ; UART8 - DCD SPI4_IRQHandler ; SPI4 - DCD SPI5_IRQHandler ; SPI5 - DCD SPI6_IRQHandler ; SPI6 - DCD SAI1_IRQHandler ; SAI1 - DCD LTDC_IRQHandler ; LTDC - DCD LTDC_ER_IRQHandler ; LTDC error - DCD DMA2D_IRQHandler ; DMA2D - DCD SAI2_IRQHandler ; SAI2 - DCD QUADSPI_IRQHandler ; QUADSPI - DCD LPTIM1_IRQHandler ; LPTIM1 - DCD CEC_IRQHandler ; HDMI_CEC - DCD I2C4_EV_IRQHandler ; I2C4 Event - DCD I2C4_ER_IRQHandler ; I2C4 Error - DCD SPDIF_RX_IRQHandler ; SPDIF_RX - DCD 0 ; Reserved - DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt - DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt - DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt - DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt - DCD SDMMC2_IRQHandler ; SDMMC2 - DCD CAN3_TX_IRQHandler ; CAN3 TX - DCD CAN3_RX0_IRQHandler ; CAN3 RX0 - DCD CAN3_RX1_IRQHandler ; CAN3 RX1 - DCD CAN3_SCE_IRQHandler ; CAN3 SCE - DCD JPEG_IRQHandler ; JPEG - DCD MDIOS_IRQHandler ; MDIOS -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT SDMMC1_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT UART7_IRQHandler [WEAK] - EXPORT UART8_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SPI5_IRQHandler [WEAK] - EXPORT SPI6_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT LTDC_IRQHandler [WEAK] - EXPORT LTDC_ER_IRQHandler [WEAK] - EXPORT DMA2D_IRQHandler [WEAK] - EXPORT SAI2_IRQHandler [WEAK] - EXPORT QUADSPI_IRQHandler [WEAK] - EXPORT LPTIM1_IRQHandler [WEAK] - EXPORT CEC_IRQHandler [WEAK] - EXPORT I2C4_EV_IRQHandler [WEAK] - EXPORT I2C4_ER_IRQHandler [WEAK] - EXPORT SPDIF_RX_IRQHandler [WEAK] - EXPORT DFSDM1_FLT0_IRQHandler [WEAK] - EXPORT DFSDM1_FLT1_IRQHandler [WEAK] - EXPORT DFSDM1_FLT2_IRQHandler [WEAK] - EXPORT DFSDM1_FLT3_IRQHandler [WEAK] - EXPORT SDMMC2_IRQHandler [WEAK] - EXPORT CAN3_TX_IRQHandler [WEAK] - EXPORT CAN3_RX0_IRQHandler [WEAK] - EXPORT CAN3_RX1_IRQHandler [WEAK] - EXPORT CAN3_SCE_IRQHandler [WEAK] - EXPORT JPEG_IRQHandler [WEAK] - EXPORT MDIOS_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FMC_IRQHandler -SDMMC1_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -RNG_IRQHandler -FPU_IRQHandler -UART7_IRQHandler -UART8_IRQHandler -SPI4_IRQHandler -SPI5_IRQHandler -SPI6_IRQHandler -SAI1_IRQHandler -LTDC_IRQHandler -LTDC_ER_IRQHandler -DMA2D_IRQHandler -SAI2_IRQHandler -QUADSPI_IRQHandler -LPTIM1_IRQHandler -CEC_IRQHandler -I2C4_EV_IRQHandler -I2C4_ER_IRQHandler -SPDIF_RX_IRQHandler -DFSDM1_FLT0_IRQHandler -DFSDM1_FLT1_IRQHandler -DFSDM1_FLT2_IRQHandler -DFSDM1_FLT3_IRQHandler -SDMMC2_IRQHandler -CAN3_TX_IRQHandler -CAN3_RX0_IRQHandler -CAN3_RX1_IRQHandler -CAN3_SCE_IRQHandler -JPEG_IRQHandler -MDIOS_IRQHandler - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Src/main.c deleted file mode 100644 index 50bede137d..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Src/main.c +++ /dev/null @@ -1,642 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file : main.c - * @brief : Main program body - ****************************************************************************** - ** This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * COPYRIGHT(c) 2018 STMicroelectronics - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" - -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN PTD */ - -/* USER CODE END PTD */ - -/* Private define ------------------------------------------------------------*/ -/* USER CODE BEGIN PD */ - -/* USER CODE END PD */ - -/* Private macro -------------------------------------------------------------*/ -/* USER CODE BEGIN PM */ - -/* USER CODE END PM */ - -/* Private variables ---------------------------------------------------------*/ -ADC_HandleTypeDef hadc1; - -DMA2D_HandleTypeDef hdma2d; - -ETH_HandleTypeDef heth; - -LTDC_HandleTypeDef hltdc; - -QSPI_HandleTypeDef hqspi; - -SD_HandleTypeDef hsd1; - -UART_HandleTypeDef huart1; - -SDRAM_HandleTypeDef hsdram1; - -/* USER CODE BEGIN PV */ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -void SystemClock_Config(void); -static void MX_GPIO_Init(void); -static void MX_USART1_UART_Init(void); -static void MX_ETH_Init(void); -static void MX_FMC_Init(void); -static void MX_QUADSPI_Init(void); -static void MX_SDMMC1_SD_Init(void); -static void MX_DMA2D_Init(void); -static void MX_LTDC_Init(void); -static void MX_ADC1_Init(void); -/* USER CODE BEGIN PFP */ - -/* USER CODE END PFP */ - -/* Private user code ---------------------------------------------------------*/ -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/** - * @brief The application entry point. - * @retval int - */ -int main(void) -{ - /* USER CODE BEGIN 1 */ - - /* USER CODE END 1 */ - - /* MCU Configuration--------------------------------------------------------*/ - - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); - - /* USER CODE BEGIN Init */ - - /* USER CODE END Init */ - - /* Configure the system clock */ - SystemClock_Config(); - - /* USER CODE BEGIN SysInit */ - - /* USER CODE END SysInit */ - - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - MX_USART1_UART_Init(); - MX_ETH_Init(); - MX_FMC_Init(); - MX_QUADSPI_Init(); - MX_SDMMC1_SD_Init(); - MX_DMA2D_Init(); - MX_LTDC_Init(); - MX_ADC1_Init(); - /* USER CODE BEGIN 2 */ - - /* USER CODE END 2 */ - - /* Infinite loop */ - /* USER CODE BEGIN WHILE */ - while (1) - { - /* USER CODE END WHILE */ - - /* USER CODE BEGIN 3 */ - } - /* USER CODE END 3 */ -} - -/** - * @brief System Clock Configuration - * @retval None - */ -void SystemClock_Config(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - - /** Configure the main internal regulator output voltage - */ - __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /** Initializes the CPU, AHB and APB busses clocks - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 25; - RCC_OscInitStruct.PLL.PLLN = 432; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 9; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - Error_Handler(); - } - /** Activate the Over-Drive mode - */ - if (HAL_PWREx_EnableOverDrive() != HAL_OK) - { - Error_Handler(); - } - /** Initializes the CPU, AHB and APB busses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) - { - Error_Handler(); - } - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC|RCC_PERIPHCLK_USART1 - |RCC_PERIPHCLK_SDMMC1|RCC_PERIPHCLK_CLK48; - PeriphClkInitStruct.PLLSAI.PLLSAIN = 192; - PeriphClkInitStruct.PLLSAI.PLLSAIR = 3; - PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2; - PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV2; - PeriphClkInitStruct.PLLSAIDivQ = 1; - PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2; - PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; - PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; - PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_CLK48; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - { - Error_Handler(); - } -} - -/** - * @brief ADC1 Initialization Function - * @param None - * @retval None - */ -static void MX_ADC1_Init(void) -{ - - /* USER CODE BEGIN ADC1_Init 0 */ - - /* USER CODE END ADC1_Init 0 */ - - ADC_ChannelConfTypeDef sConfig = {0}; - - /* USER CODE BEGIN ADC1_Init 1 */ - - /* USER CODE END ADC1_Init 1 */ - /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) - */ - hadc1.Instance = ADC1; - hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; - hadc1.Init.Resolution = ADC_RESOLUTION_12B; - hadc1.Init.ScanConvMode = DISABLE; - hadc1.Init.ContinuousConvMode = DISABLE; - hadc1.Init.DiscontinuousConvMode = DISABLE; - hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; - hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; - hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; - hadc1.Init.NbrOfConversion = 1; - hadc1.Init.DMAContinuousRequests = DISABLE; - hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; - if (HAL_ADC_Init(&hadc1) != HAL_OK) - { - Error_Handler(); - } - /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. - */ - sConfig.Channel = ADC_CHANNEL_5; - sConfig.Rank = ADC_REGULAR_RANK_1; - sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; - if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN ADC1_Init 2 */ - - /* USER CODE END ADC1_Init 2 */ - -} - -/** - * @brief DMA2D Initialization Function - * @param None - * @retval None - */ -static void MX_DMA2D_Init(void) -{ - - /* USER CODE BEGIN DMA2D_Init 0 */ - - /* USER CODE END DMA2D_Init 0 */ - - /* USER CODE BEGIN DMA2D_Init 1 */ - - /* USER CODE END DMA2D_Init 1 */ - hdma2d.Instance = DMA2D; - hdma2d.Init.Mode = DMA2D_M2M; - hdma2d.Init.ColorMode = DMA2D_OUTPUT_ARGB8888; - hdma2d.Init.OutputOffset = 0; - hdma2d.LayerCfg[1].InputOffset = 0; - hdma2d.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888; - hdma2d.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA; - hdma2d.LayerCfg[1].InputAlpha = 0; - hdma2d.LayerCfg[1].AlphaInverted = DMA2D_REGULAR_ALPHA; - hdma2d.LayerCfg[1].RedBlueSwap = DMA2D_RB_REGULAR; - if (HAL_DMA2D_Init(&hdma2d) != HAL_OK) - { - Error_Handler(); - } - if (HAL_DMA2D_ConfigLayer(&hdma2d, 1) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN DMA2D_Init 2 */ - - /* USER CODE END DMA2D_Init 2 */ - -} - -/** - * @brief ETH Initialization Function - * @param None - * @retval None - */ -static void MX_ETH_Init(void) -{ - - /* USER CODE BEGIN ETH_Init 0 */ - - /* USER CODE END ETH_Init 0 */ - - uint8_t MACAddr[6] ; - - /* USER CODE BEGIN ETH_Init 1 */ - - /* USER CODE END ETH_Init 1 */ - heth.Instance = ETH; - heth.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE; - heth.Init.PhyAddress = LAN8742A_PHY_ADDRESS; - MACAddr[0] = 0x00; - MACAddr[1] = 0x80; - MACAddr[2] = 0xE1; - MACAddr[3] = 0x00; - MACAddr[4] = 0x00; - MACAddr[5] = 0x00; - heth.Init.MACAddr = &MACAddr[0]; - heth.Init.RxMode = ETH_RXPOLLING_MODE; - heth.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE; - heth.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII; - - /* USER CODE BEGIN MACADDRESS */ - - /* USER CODE END MACADDRESS */ - - if (HAL_ETH_Init(&heth) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN ETH_Init 2 */ - - /* USER CODE END ETH_Init 2 */ - -} - -/** - * @brief LTDC Initialization Function - * @param None - * @retval None - */ -static void MX_LTDC_Init(void) -{ - - /* USER CODE BEGIN LTDC_Init 0 */ - - /* USER CODE END LTDC_Init 0 */ - - LTDC_LayerCfgTypeDef pLayerCfg = {0}; - LTDC_LayerCfgTypeDef pLayerCfg1 = {0}; - - /* USER CODE BEGIN LTDC_Init 1 */ - - /* USER CODE END LTDC_Init 1 */ - hltdc.Instance = LTDC; - hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL; - hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL; - hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL; - hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC; - hltdc.Init.HorizontalSync = 7; - hltdc.Init.VerticalSync = 3; - hltdc.Init.AccumulatedHBP = 14; - hltdc.Init.AccumulatedVBP = 5; - hltdc.Init.AccumulatedActiveW = 654; - hltdc.Init.AccumulatedActiveH = 485; - hltdc.Init.TotalWidth = 660; - hltdc.Init.TotalHeigh = 487; - hltdc.Init.Backcolor.Blue = 0; - hltdc.Init.Backcolor.Green = 0; - hltdc.Init.Backcolor.Red = 0; - if (HAL_LTDC_Init(&hltdc) != HAL_OK) - { - Error_Handler(); - } - pLayerCfg.WindowX0 = 0; - pLayerCfg.WindowX1 = 0; - pLayerCfg.WindowY0 = 0; - pLayerCfg.WindowY1 = 0; - pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888; - pLayerCfg.Alpha = 0; - pLayerCfg.Alpha0 = 0; - pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_CA; - pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_CA; - pLayerCfg.FBStartAdress = 0; - pLayerCfg.ImageWidth = 0; - pLayerCfg.ImageHeight = 0; - pLayerCfg.Backcolor.Blue = 0; - pLayerCfg.Backcolor.Green = 0; - pLayerCfg.Backcolor.Red = 0; - if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK) - { - Error_Handler(); - } - pLayerCfg1.WindowX0 = 0; - pLayerCfg1.WindowX1 = 0; - pLayerCfg1.WindowY0 = 0; - pLayerCfg1.WindowY1 = 0; - pLayerCfg1.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888; - pLayerCfg1.Alpha = 0; - pLayerCfg1.Alpha0 = 0; - pLayerCfg1.BlendingFactor1 = LTDC_BLENDING_FACTOR1_CA; - pLayerCfg1.BlendingFactor2 = LTDC_BLENDING_FACTOR2_CA; - pLayerCfg1.FBStartAdress = 0; - pLayerCfg1.ImageWidth = 0; - pLayerCfg1.ImageHeight = 0; - pLayerCfg1.Backcolor.Blue = 0; - pLayerCfg1.Backcolor.Green = 0; - pLayerCfg1.Backcolor.Red = 0; - if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg1, 1) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN LTDC_Init 2 */ - - /* USER CODE END LTDC_Init 2 */ - -} - -/** - * @brief QUADSPI Initialization Function - * @param None - * @retval None - */ -static void MX_QUADSPI_Init(void) -{ - - /* USER CODE BEGIN QUADSPI_Init 0 */ - - /* USER CODE END QUADSPI_Init 0 */ - - /* USER CODE BEGIN QUADSPI_Init 1 */ - - /* USER CODE END QUADSPI_Init 1 */ - /* QUADSPI parameter configuration*/ - hqspi.Instance = QUADSPI; - hqspi.Init.ClockPrescaler = 255; - hqspi.Init.FifoThreshold = 1; - hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_NONE; - hqspi.Init.FlashSize = 1; - hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_1_CYCLE; - hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0; - hqspi.Init.FlashID = QSPI_FLASH_ID_1; - hqspi.Init.DualFlash = QSPI_DUALFLASH_DISABLE; - if (HAL_QSPI_Init(&hqspi) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN QUADSPI_Init 2 */ - - /* USER CODE END QUADSPI_Init 2 */ - -} - -/** - * @brief SDMMC1 Initialization Function - * @param None - * @retval None - */ -static void MX_SDMMC1_SD_Init(void) -{ - - /* USER CODE BEGIN SDMMC1_Init 0 */ - - /* USER CODE END SDMMC1_Init 0 */ - - /* USER CODE BEGIN SDMMC1_Init 1 */ - - /* USER CODE END SDMMC1_Init 1 */ - hsd1.Instance = SDMMC1; - hsd1.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; - hsd1.Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; - hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; - hsd1.Init.BusWide = SDMMC_BUS_WIDE_1B; - hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; - hsd1.Init.ClockDiv = 0; - if (HAL_SD_Init(&hsd1) != HAL_OK) - { - Error_Handler(); - } - if (HAL_SD_ConfigWideBusOperation(&hsd1, SDMMC_BUS_WIDE_4B) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN SDMMC1_Init 2 */ - - /* USER CODE END SDMMC1_Init 2 */ - -} - -/** - * @brief USART1 Initialization Function - * @param None - * @retval None - */ -static void MX_USART1_UART_Init(void) -{ - - /* USER CODE BEGIN USART1_Init 0 */ - - /* USER CODE END USART1_Init 0 */ - - /* USER CODE BEGIN USART1_Init 1 */ - - /* USER CODE END USART1_Init 1 */ - huart1.Instance = USART1; - huart1.Init.BaudRate = 115200; - huart1.Init.WordLength = UART_WORDLENGTH_8B; - huart1.Init.StopBits = UART_STOPBITS_1; - huart1.Init.Parity = UART_PARITY_NONE; - huart1.Init.Mode = UART_MODE_TX_RX; - huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; - huart1.Init.OverSampling = UART_OVERSAMPLING_16; - huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - if (HAL_UART_Init(&huart1) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN USART1_Init 2 */ - - /* USER CODE END USART1_Init 2 */ - -} - -/* FMC initialization function */ -static void MX_FMC_Init(void) -{ - FMC_SDRAM_TimingTypeDef SdramTiming; - - /** Perform the SDRAM1 memory initialization sequence - */ - hsdram1.Instance = FMC_SDRAM_DEVICE; - /* hsdram1.Init */ - hsdram1.Init.SDBank = FMC_SDRAM_BANK2; - hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8; - hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; - hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16; - hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; - hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_1; - hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; - hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_DISABLE; - hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE; - hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0; - /* SdramTiming */ - SdramTiming.LoadToActiveDelay = 16; - SdramTiming.ExitSelfRefreshDelay = 16; - SdramTiming.SelfRefreshTime = 16; - SdramTiming.RowCycleDelay = 16; - SdramTiming.WriteRecoveryTime = 16; - SdramTiming.RPDelay = 16; - SdramTiming.RCDDelay = 16; - - if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK) - { - Error_Handler( ); - } - -} - -/** - * @brief GPIO Initialization Function - * @param None - * @retval None - */ -static void MX_GPIO_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - - /* GPIO Ports Clock Enable */ - __HAL_RCC_GPIOE_CLK_ENABLE(); - __HAL_RCC_GPIOI_CLK_ENABLE(); - __HAL_RCC_GPIOF_CLK_ENABLE(); - __HAL_RCC_GPIOH_CLK_ENABLE(); - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - __HAL_RCC_GPIOG_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOH, GPIO_PIN_10, GPIO_PIN_RESET); - - /*Configure GPIO pin : PH10 */ - GPIO_InitStruct.Pin = GPIO_PIN_10; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); - -} - -/* USER CODE BEGIN 4 */ - -/* USER CODE END 4 */ - -/** - * @brief This function is executed in case of error occurrence. - * @retval None - */ -void Error_Handler(void) -{ - /* USER CODE BEGIN Error_Handler_Debug */ - /* User can add his own implementation to report the HAL error return state */ - - /* USER CODE END Error_Handler_Debug */ -} - -#ifdef USE_FULL_ASSERT -/** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ -void assert_failed(uint8_t *file, uint32_t line) -{ - /* USER CODE BEGIN 6 */ - /* User can add his own implementation to report the file name and line number, - tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - /* USER CODE END 6 */ -} -#endif /* USE_FULL_ASSERT */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c b/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c deleted file mode 100644 index a395939496..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c +++ /dev/null @@ -1,981 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * File Name : stm32f7xx_hal_msp.c - * Description : This file provides code for the MSP Initialization - * and de-Initialization codes. - ****************************************************************************** - ** This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * COPYRIGHT(c) 2018 STMicroelectronics - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN TD */ - -/* USER CODE END TD */ - -/* Private define ------------------------------------------------------------*/ -/* USER CODE BEGIN Define */ - -/* USER CODE END Define */ - -/* Private macro -------------------------------------------------------------*/ -/* USER CODE BEGIN Macro */ - -/* USER CODE END Macro */ - -/* Private variables ---------------------------------------------------------*/ -/* USER CODE BEGIN PV */ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -/* USER CODE BEGIN PFP */ - -/* USER CODE END PFP */ - -/* External functions --------------------------------------------------------*/ -/* USER CODE BEGIN ExternalFunctions */ - -/* USER CODE END ExternalFunctions */ - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ -/** - * Initializes the Global MSP. - */ -void HAL_MspInit(void) -{ - /* USER CODE BEGIN MspInit 0 */ - - /* USER CODE END MspInit 0 */ - - __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - /* System interrupt init*/ - - /* USER CODE BEGIN MspInit 1 */ - - /* USER CODE END MspInit 1 */ -} - -/** -* @brief ADC MSP Initialization -* This function configures the hardware resources used in this example -* @param hadc: ADC handle pointer -* @retval None -*/ -void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(hadc->Instance==ADC1) - { - /* USER CODE BEGIN ADC1_MspInit 0 */ - - /* USER CODE END ADC1_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_ADC1_CLK_ENABLE(); - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**ADC1 GPIO Configuration - PA5 ------> ADC1_IN5 - */ - GPIO_InitStruct.Pin = GPIO_PIN_5; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* USER CODE BEGIN ADC1_MspInit 1 */ - - /* USER CODE END ADC1_MspInit 1 */ - } - -} - -/** -* @brief ADC MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hadc: ADC handle pointer -* @retval None -*/ -void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) -{ - if(hadc->Instance==ADC1) - { - /* USER CODE BEGIN ADC1_MspDeInit 0 */ - - /* USER CODE END ADC1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_ADC1_CLK_DISABLE(); - - /**ADC1 GPIO Configuration - PA5 ------> ADC1_IN5 - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5); - - /* USER CODE BEGIN ADC1_MspDeInit 1 */ - - /* USER CODE END ADC1_MspDeInit 1 */ - } - -} - -/** -* @brief DMA2D MSP Initialization -* This function configures the hardware resources used in this example -* @param hdma2d: DMA2D handle pointer -* @retval None -*/ -void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) -{ - if(hdma2d->Instance==DMA2D) - { - /* USER CODE BEGIN DMA2D_MspInit 0 */ - - /* USER CODE END DMA2D_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_DMA2D_CLK_ENABLE(); - /* USER CODE BEGIN DMA2D_MspInit 1 */ - - /* USER CODE END DMA2D_MspInit 1 */ - } - -} - -/** -* @brief DMA2D MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hdma2d: DMA2D handle pointer -* @retval None -*/ -void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) -{ - if(hdma2d->Instance==DMA2D) - { - /* USER CODE BEGIN DMA2D_MspDeInit 0 */ - - /* USER CODE END DMA2D_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_DMA2D_CLK_DISABLE(); - /* USER CODE BEGIN DMA2D_MspDeInit 1 */ - - /* USER CODE END DMA2D_MspDeInit 1 */ - } - -} - -/** -* @brief ETH MSP Initialization -* This function configures the hardware resources used in this example -* @param heth: ETH handle pointer -* @retval None -*/ -void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(heth->Instance==ETH) - { - /* USER CODE BEGIN ETH_MspInit 0 */ - - /* USER CODE END ETH_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_ETH_CLK_ENABLE(); - - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**ETH GPIO Configuration - PC1 ------> ETH_MDC - PA1 ------> ETH_REF_CLK - PA2 ------> ETH_MDIO - PA7 ------> ETH_CRS_DV - PC4 ------> ETH_RXD0 - PC5 ------> ETH_RXD1 - PB11 ------> ETH_TX_EN - PB12 ------> ETH_TXD0 - PB13 ------> ETH_TXD1 - */ - GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF11_ETH; - HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF11_ETH; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF11_ETH; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /* USER CODE BEGIN ETH_MspInit 1 */ - - /* USER CODE END ETH_MspInit 1 */ - } - -} - -/** -* @brief ETH MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param heth: ETH handle pointer -* @retval None -*/ -void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) -{ - if(heth->Instance==ETH) - { - /* USER CODE BEGIN ETH_MspDeInit 0 */ - - /* USER CODE END ETH_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_ETH_CLK_DISABLE(); - - /**ETH GPIO Configuration - PC1 ------> ETH_MDC - PA1 ------> ETH_REF_CLK - PA2 ------> ETH_MDIO - PA7 ------> ETH_CRS_DV - PC4 ------> ETH_RXD0 - PC5 ------> ETH_RXD1 - PB11 ------> ETH_TX_EN - PB12 ------> ETH_TXD0 - PB13 ------> ETH_TXD1 - */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5); - - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7); - - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13); - - /* USER CODE BEGIN ETH_MspDeInit 1 */ - - /* USER CODE END ETH_MspDeInit 1 */ - } - -} - -/** -* @brief LTDC MSP Initialization -* This function configures the hardware resources used in this example -* @param hltdc: LTDC handle pointer -* @retval None -*/ -void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(hltdc->Instance==LTDC) - { - /* USER CODE BEGIN LTDC_MspInit 0 */ - - /* USER CODE END LTDC_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_LTDC_CLK_ENABLE(); - - __HAL_RCC_GPIOE_CLK_ENABLE(); - __HAL_RCC_GPIOI_CLK_ENABLE(); - __HAL_RCC_GPIOF_CLK_ENABLE(); - __HAL_RCC_GPIOH_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - __HAL_RCC_GPIOG_CLK_ENABLE(); - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); - /**LTDC GPIO Configuration - PE4 ------> LTDC_B0 - PE5 ------> LTDC_G0 - PE6 ------> LTDC_G1 - PI9 ------> LTDC_VSYNC - PI10 ------> LTDC_HSYNC - PF10 ------> LTDC_DE - PH2 ------> LTDC_R0 - PH3 ------> LTDC_R1 - PA3 ------> LTDC_B5 - PB0 ------> LTDC_R3 - PB1 ------> LTDC_R6 - PH8 ------> LTDC_R2 - PG6 ------> LTDC_R7 - PG7 ------> LTDC_CLK - PC7 ------> LTDC_G6 - PA11 ------> LTDC_R4 - PA12 ------> LTDC_R5 - PH13 ------> LTDC_G2 - PH15 ------> LTDC_G4 - PI0 ------> LTDC_G5 - PI2 ------> LTDC_G7 - PD6 ------> LTDC_B2 - PG10 ------> LTDC_G3 - PG11 ------> LTDC_B3 - PG12 ------> LTDC_B1 - PB8 ------> LTDC_B6 - PB9 ------> LTDC_B7 - PI4 ------> LTDC_B4 - */ - GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; - HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_2 - |GPIO_PIN_4; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; - HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_10; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; - HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_8|GPIO_PIN_13 - |GPIO_PIN_15; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; - HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_11|GPIO_PIN_12; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF9_LTDC; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_11; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; - HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_7; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; - HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_6; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; - HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_10; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF9_LTDC; - HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_12; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; - HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /* USER CODE BEGIN LTDC_MspInit 1 */ - - /* USER CODE END LTDC_MspInit 1 */ - } - -} - -/** -* @brief LTDC MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hltdc: LTDC handle pointer -* @retval None -*/ -void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) -{ - if(hltdc->Instance==LTDC) - { - /* USER CODE BEGIN LTDC_MspDeInit 0 */ - - /* USER CODE END LTDC_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_LTDC_CLK_DISABLE(); - - /**LTDC GPIO Configuration - PE4 ------> LTDC_B0 - PE5 ------> LTDC_G0 - PE6 ------> LTDC_G1 - PI9 ------> LTDC_VSYNC - PI10 ------> LTDC_HSYNC - PF10 ------> LTDC_DE - PH2 ------> LTDC_R0 - PH3 ------> LTDC_R1 - PA3 ------> LTDC_B5 - PB0 ------> LTDC_R3 - PB1 ------> LTDC_R6 - PH8 ------> LTDC_R2 - PG6 ------> LTDC_R7 - PG7 ------> LTDC_CLK - PC7 ------> LTDC_G6 - PA11 ------> LTDC_R4 - PA12 ------> LTDC_R5 - PH13 ------> LTDC_G2 - PH15 ------> LTDC_G4 - PI0 ------> LTDC_G5 - PI2 ------> LTDC_G7 - PD6 ------> LTDC_B2 - PG10 ------> LTDC_G3 - PG11 ------> LTDC_B3 - PG12 ------> LTDC_B1 - PB8 ------> LTDC_B6 - PB9 ------> LTDC_B7 - PI4 ------> LTDC_B4 - */ - HAL_GPIO_DeInit(GPIOE, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6); - - HAL_GPIO_DeInit(GPIOI, GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_2 - |GPIO_PIN_4); - - HAL_GPIO_DeInit(GPIOF, GPIO_PIN_10); - - HAL_GPIO_DeInit(GPIOH, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_8|GPIO_PIN_13 - |GPIO_PIN_15); - - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_3|GPIO_PIN_11|GPIO_PIN_12); - - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_8|GPIO_PIN_9); - - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_11 - |GPIO_PIN_12); - - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_7); - - HAL_GPIO_DeInit(GPIOD, GPIO_PIN_6); - - /* USER CODE BEGIN LTDC_MspDeInit 1 */ - - /* USER CODE END LTDC_MspDeInit 1 */ - } - -} - -/** -* @brief QSPI MSP Initialization -* This function configures the hardware resources used in this example -* @param hqspi: QSPI handle pointer -* @retval None -*/ -void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(hqspi->Instance==QUADSPI) - { - /* USER CODE BEGIN QUADSPI_MspInit 0 */ - - /* USER CODE END QUADSPI_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_QSPI_CLK_ENABLE(); - - __HAL_RCC_GPIOF_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**QUADSPI GPIO Configuration - PF6 ------> QUADSPI_BK1_IO3 - PF7 ------> QUADSPI_BK1_IO2 - PF8 ------> QUADSPI_BK1_IO0 - PF9 ------> QUADSPI_BK1_IO1 - PB2 ------> QUADSPI_CLK - PB6 ------> QUADSPI_BK1_NCS - */ - GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; - HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; - HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_2; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_6; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /* USER CODE BEGIN QUADSPI_MspInit 1 */ - - /* USER CODE END QUADSPI_MspInit 1 */ - } - -} - -/** -* @brief QSPI MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hqspi: QSPI handle pointer -* @retval None -*/ -void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* hqspi) -{ - if(hqspi->Instance==QUADSPI) - { - /* USER CODE BEGIN QUADSPI_MspDeInit 0 */ - - /* USER CODE END QUADSPI_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_QSPI_CLK_DISABLE(); - - /**QUADSPI GPIO Configuration - PF6 ------> QUADSPI_BK1_IO3 - PF7 ------> QUADSPI_BK1_IO2 - PF8 ------> QUADSPI_BK1_IO0 - PF9 ------> QUADSPI_BK1_IO1 - PB2 ------> QUADSPI_CLK - PB6 ------> QUADSPI_BK1_NCS - */ - HAL_GPIO_DeInit(GPIOF, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9); - - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_2|GPIO_PIN_6); - - /* USER CODE BEGIN QUADSPI_MspDeInit 1 */ - - /* USER CODE END QUADSPI_MspDeInit 1 */ - } - -} - -/** -* @brief SD MSP Initialization -* This function configures the hardware resources used in this example -* @param hsd: SD handle pointer -* @retval None -*/ -void HAL_SD_MspInit(SD_HandleTypeDef* hsd) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(hsd->Instance==SDMMC1) - { - /* USER CODE BEGIN SDMMC1_MspInit 0 */ - - /* USER CODE END SDMMC1_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_SDMMC1_CLK_ENABLE(); - - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); - /**SDMMC1 GPIO Configuration - PC8 ------> SDMMC1_D0 - PC9 ------> SDMMC1_D1 - PC10 ------> SDMMC1_D2 - PC11 ------> SDMMC1_D3 - PC12 ------> SDMMC1_CK - PD2 ------> SDMMC1_CMD - */ - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 - |GPIO_PIN_12; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1; - HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_2; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1; - HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - - /* USER CODE BEGIN SDMMC1_MspInit 1 */ - - /* USER CODE END SDMMC1_MspInit 1 */ - } - -} - -/** -* @brief SD MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hsd: SD handle pointer -* @retval None -*/ -void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd) -{ - if(hsd->Instance==SDMMC1) - { - /* USER CODE BEGIN SDMMC1_MspDeInit 0 */ - - /* USER CODE END SDMMC1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_SDMMC1_CLK_DISABLE(); - - /**SDMMC1 GPIO Configuration - PC8 ------> SDMMC1_D0 - PC9 ------> SDMMC1_D1 - PC10 ------> SDMMC1_D2 - PC11 ------> SDMMC1_D3 - PC12 ------> SDMMC1_CK - PD2 ------> SDMMC1_CMD - */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 - |GPIO_PIN_12); - - HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); - - /* USER CODE BEGIN SDMMC1_MspDeInit 1 */ - - /* USER CODE END SDMMC1_MspDeInit 1 */ - } - -} - -/** -* @brief UART MSP Initialization -* This function configures the hardware resources used in this example -* @param huart: UART handle pointer -* @retval None -*/ -void HAL_UART_MspInit(UART_HandleTypeDef* huart) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(huart->Instance==USART1) - { - /* USER CODE BEGIN USART1_MspInit 0 */ - - /* USER CODE END USART1_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_USART1_CLK_ENABLE(); - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration - PA9 ------> USART1_TX - PA10 ------> USART1_RX - */ - GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF7_USART1; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* USER CODE BEGIN USART1_MspInit 1 */ - - /* USER CODE END USART1_MspInit 1 */ - } - -} - -/** -* @brief UART MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param huart: UART handle pointer -* @retval None -*/ -void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) -{ - if(huart->Instance==USART1) - { - /* USER CODE BEGIN USART1_MspDeInit 0 */ - - /* USER CODE END USART1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration - PA9 ------> USART1_TX - PA10 ------> USART1_RX - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); - - /* USER CODE BEGIN USART1_MspDeInit 1 */ - - /* USER CODE END USART1_MspDeInit 1 */ - } - -} - -static uint32_t FMC_Initialized = 0; - -static void HAL_FMC_MspInit(void){ - /* USER CODE BEGIN FMC_MspInit 0 */ - - /* USER CODE END FMC_MspInit 0 */ - GPIO_InitTypeDef GPIO_InitStruct; - if (FMC_Initialized) { - return; - } - FMC_Initialized = 1; - /* Peripheral clock enable */ - __HAL_RCC_FMC_CLK_ENABLE(); - - /** FMC GPIO Configuration - PF0 ------> FMC_A0 - PF1 ------> FMC_A1 - PF2 ------> FMC_A2 - PF3 ------> FMC_A3 - PF4 ------> FMC_A4 - PF5 ------> FMC_A5 - PC0 ------> FMC_SDNWE - PF11 ------> FMC_SDNRAS - PF12 ------> FMC_A6 - PF13 ------> FMC_A7 - PF14 ------> FMC_A8 - PF15 ------> FMC_A9 - PG0 ------> FMC_A10 - PG1 ------> FMC_A11 - PE7 ------> FMC_D4 - PE8 ------> FMC_D5 - PE9 ------> FMC_D6 - PE10 ------> FMC_D7 - PE11 ------> FMC_D8 - PE12 ------> FMC_D9 - PE13 ------> FMC_D10 - PE14 ------> FMC_D11 - PE15 ------> FMC_D12 - PH6 ------> FMC_SDNE1 - PH7 ------> FMC_SDCKE1 - PD8 ------> FMC_D13 - PD9 ------> FMC_D14 - PD10 ------> FMC_D15 - PD14 ------> FMC_D0 - PD15 ------> FMC_D1 - PG4 ------> FMC_BA0 - PG5 ------> FMC_BA1 - PG8 ------> FMC_SDCLK - PD0 ------> FMC_D2 - PD1 ------> FMC_D3 - PG15 ------> FMC_SDNCAS - PE0 ------> FMC_NBL0 - PE1 ------> FMC_NBL1 - */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 - |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF12_FMC; - HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_0; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF12_FMC; - HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5 - |GPIO_PIN_8|GPIO_PIN_15; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF12_FMC; - HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 - |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 - |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF12_FMC; - HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF12_FMC; - HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 - |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF12_FMC; - HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - - /* USER CODE BEGIN FMC_MspInit 1 */ - - /* USER CODE END FMC_MspInit 1 */ -} - -void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){ - /* USER CODE BEGIN SDRAM_MspInit 0 */ - - /* USER CODE END SDRAM_MspInit 0 */ - HAL_FMC_MspInit(); - /* USER CODE BEGIN SDRAM_MspInit 1 */ - - /* USER CODE END SDRAM_MspInit 1 */ -} - -static uint32_t FMC_DeInitialized = 0; - -static void HAL_FMC_MspDeInit(void){ - /* USER CODE BEGIN FMC_MspDeInit 0 */ - - /* USER CODE END FMC_MspDeInit 0 */ - if (FMC_DeInitialized) { - return; - } - FMC_DeInitialized = 1; - /* Peripheral clock enable */ - __HAL_RCC_FMC_CLK_DISABLE(); - - /** FMC GPIO Configuration - PF0 ------> FMC_A0 - PF1 ------> FMC_A1 - PF2 ------> FMC_A2 - PF3 ------> FMC_A3 - PF4 ------> FMC_A4 - PF5 ------> FMC_A5 - PC0 ------> FMC_SDNWE - PF11 ------> FMC_SDNRAS - PF12 ------> FMC_A6 - PF13 ------> FMC_A7 - PF14 ------> FMC_A8 - PF15 ------> FMC_A9 - PG0 ------> FMC_A10 - PG1 ------> FMC_A11 - PE7 ------> FMC_D4 - PE8 ------> FMC_D5 - PE9 ------> FMC_D6 - PE10 ------> FMC_D7 - PE11 ------> FMC_D8 - PE12 ------> FMC_D9 - PE13 ------> FMC_D10 - PE14 ------> FMC_D11 - PE15 ------> FMC_D12 - PH6 ------> FMC_SDNE1 - PH7 ------> FMC_SDCKE1 - PD8 ------> FMC_D13 - PD9 ------> FMC_D14 - PD10 ------> FMC_D15 - PD14 ------> FMC_D0 - PD15 ------> FMC_D1 - PG4 ------> FMC_BA0 - PG5 ------> FMC_BA1 - PG8 ------> FMC_SDCLK - PD0 ------> FMC_D2 - PD1 ------> FMC_D3 - PG15 ------> FMC_SDNCAS - PE0 ------> FMC_NBL0 - PE1 ------> FMC_NBL1 - */ - HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 - |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 - |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); - - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0); - - HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5 - |GPIO_PIN_8|GPIO_PIN_15); - - HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 - |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 - |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1); - - HAL_GPIO_DeInit(GPIOH, GPIO_PIN_6|GPIO_PIN_7); - - HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 - |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1); - - /* USER CODE BEGIN FMC_MspDeInit 1 */ - - /* USER CODE END FMC_MspDeInit 1 */ -} - -void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef* hsdram){ - /* USER CODE BEGIN SDRAM_MspDeInit 0 */ - - /* USER CODE END SDRAM_MspDeInit 0 */ - HAL_FMC_MspDeInit(); - /* USER CODE BEGIN SDRAM_MspDeInit 1 */ - - /* USER CODE END SDRAM_MspDeInit 1 */ -} - -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Src/stm32f7xx_it.c b/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Src/stm32f7xx_it.c deleted file mode 100644 index fc333c38eb..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Src/stm32f7xx_it.c +++ /dev/null @@ -1,218 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file stm32f7xx_it.c - * @brief Interrupt Service Routines. - ****************************************************************************** - * - * COPYRIGHT(c) 2018 STMicroelectronics - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" -#include "stm32f7xx_it.h" -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN TD */ - -/* USER CODE END TD */ - -/* Private define ------------------------------------------------------------*/ -/* USER CODE BEGIN PD */ - -/* USER CODE END PD */ - -/* Private macro -------------------------------------------------------------*/ -/* USER CODE BEGIN PM */ - -/* USER CODE END PM */ - -/* Private variables ---------------------------------------------------------*/ -/* USER CODE BEGIN PV */ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -/* USER CODE BEGIN PFP */ - -/* USER CODE END PFP */ - -/* Private user code ---------------------------------------------------------*/ -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/* External variables --------------------------------------------------------*/ - -/* USER CODE BEGIN EV */ - -/* USER CODE END EV */ - -/******************************************************************************/ -/* Cortex-M7 Processor Interruption and Exception Handlers */ -/******************************************************************************/ -/** - * @brief This function handles Non maskable interrupt. - */ -void NMI_Handler(void) -{ - /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ - - /* USER CODE END NonMaskableInt_IRQn 0 */ - /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ - - /* USER CODE END NonMaskableInt_IRQn 1 */ -} - -/** - * @brief This function handles Hard fault interrupt. - */ -void HardFault_Handler(void) -{ - /* USER CODE BEGIN HardFault_IRQn 0 */ - - /* USER CODE END HardFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_HardFault_IRQn 0 */ - /* USER CODE END W1_HardFault_IRQn 0 */ - } -} - -/** - * @brief This function handles Memory management fault. - */ -void MemManage_Handler(void) -{ - /* USER CODE BEGIN MemoryManagement_IRQn 0 */ - - /* USER CODE END MemoryManagement_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ - /* USER CODE END W1_MemoryManagement_IRQn 0 */ - } -} - -/** - * @brief This function handles Pre-fetch fault, memory access fault. - */ -void BusFault_Handler(void) -{ - /* USER CODE BEGIN BusFault_IRQn 0 */ - - /* USER CODE END BusFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_BusFault_IRQn 0 */ - /* USER CODE END W1_BusFault_IRQn 0 */ - } -} - -/** - * @brief This function handles Undefined instruction or illegal state. - */ -void UsageFault_Handler(void) -{ - /* USER CODE BEGIN UsageFault_IRQn 0 */ - - /* USER CODE END UsageFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ - /* USER CODE END W1_UsageFault_IRQn 0 */ - } -} - -/** - * @brief This function handles System service call via SWI instruction. - */ -void SVC_Handler(void) -{ - /* USER CODE BEGIN SVCall_IRQn 0 */ - - /* USER CODE END SVCall_IRQn 0 */ - /* USER CODE BEGIN SVCall_IRQn 1 */ - - /* USER CODE END SVCall_IRQn 1 */ -} - -/** - * @brief This function handles Debug monitor. - */ -void DebugMon_Handler(void) -{ - /* USER CODE BEGIN DebugMonitor_IRQn 0 */ - - /* USER CODE END DebugMonitor_IRQn 0 */ - /* USER CODE BEGIN DebugMonitor_IRQn 1 */ - - /* USER CODE END DebugMonitor_IRQn 1 */ -} - -/** - * @brief This function handles Pendable request for system service. - */ -void PendSV_Handler(void) -{ - /* USER CODE BEGIN PendSV_IRQn 0 */ - - /* USER CODE END PendSV_IRQn 0 */ - /* USER CODE BEGIN PendSV_IRQn 1 */ - - /* USER CODE END PendSV_IRQn 1 */ -} - -/** - * @brief This function handles System tick timer. - */ -void SysTick_Handler(void) -{ - /* USER CODE BEGIN SysTick_IRQn 0 */ - - /* USER CODE END SysTick_IRQn 0 */ - HAL_IncTick(); - /* USER CODE BEGIN SysTick_IRQn 1 */ - - /* USER CODE END SysTick_IRQn 1 */ -} - -/******************************************************************************/ -/* STM32F7xx Peripheral Interrupt Handlers */ -/* Add here the Interrupt Handlers for the used peripherals. */ -/* For the available peripheral interrupt handler names, */ -/* please refer to the startup file (startup_stm32f7xx.s). */ -/******************************************************************************/ - -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Src/system_stm32f7xx.c b/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Src/system_stm32f7xx.c deleted file mode 100644 index cb4e56623f..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/CubeMX_Config/Src/system_stm32f7xx.c +++ /dev/null @@ -1,278 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f7xx.c - * @author MCD Application Team - * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. - * - * This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f7xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f7xx_system - * @{ - */ - -/** @addtogroup STM32F7xx_System_Private_Includes - * @{ - */ - -#include "stm32f7xx.h" - -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @} - */ - -/** @addtogroup STM32F7xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F7xx_System_Private_Defines - * @{ - */ - -/************************* Miscellaneous Configuration ************************/ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -/******************************************************************************/ - -/** - * @} - */ - -/** @addtogroup STM32F7xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F7xx_System_Private_Variables - * @{ - */ - - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ - uint32_t SystemCoreClock = 16000000; - const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - -/** - * @} - */ - -/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F7xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemFrequency variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - #endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N - SYSCLK = PLL_VCO / PLL_P - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32/stm32f767-fire-challenger/board/Kconfig b/bsp/stm32/stm32f767-fire-challenger/board/Kconfig deleted file mode 100644 index 6239d9e6f6..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/Kconfig +++ /dev/null @@ -1,237 +0,0 @@ -menu "Hardware Drivers Config" - -config SOC_STM32F767IG - bool - select SOC_SERIES_STM32F7 - select RT_USING_COMPONENTS_INIT - select RT_USING_USER_MAIN - default y - -menu "Onboard Peripheral Drivers" - - config BSP_USING_USB_TO_USART - bool "Enable USB TO USART (uart1)" - select BSP_USING_UART - select BSP_USING_UART1 - default y - - config BSP_USING_RS232 - bool "Enable RS232 (uart2 pin conflict with Ethernet)" - select BSP_USING_UART - select BSP_USING_UART2 - default n - - config BSP_USING_SDRAM - bool "Enable SDRAM" - select BSP_USING_FMC - default n - - config BSP_USING_QSPI_FLASH - bool "Enable QSPI FLASH (W25Q128 qspi1)" - select BSP_USING_QSPI - select RT_USING_SFUD - select RT_SFUD_USING_QSPI - default n - - config BSP_USING_LCD - bool "Enable LCD" - select BSP_USING_LTDC - select BSP_USING_SDRAM - default n - - config BSP_USING_MPU6050 - bool "Enable MPU6050 (i2c4)" - select BSP_USING_I2C4 - select PKG_USING_MPU6XXX - default n - - config BSP_USING_POT - bool "Enable potentiometer" - select BSP_USING_ADC - select BSP_USING_ADC1 - default n - - config BSP_USING_SDCARD - bool "Enable SDCARD (sdio)" - select BSP_USING_SDIO - select RT_USING_DFS - select RT_USING_DFS_ELMFAT - select RT_USING_PIN - default n - -endmenu - -menu "On-chip Peripheral Drivers" - - config BSP_USING_GPIO - bool "Enable GPIO" - select RT_USING_PIN - default y - - menuconfig BSP_USING_UART - bool "Enable UART" - default y - select RT_USING_SERIAL - if BSP_USING_UART - config BSP_USING_UART1 - bool "Enable UART1" - default y - - config BSP_UART1_RX_USING_DMA - bool "Enable UART1 RX DMA" - depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA - default n - - config BSP_USING_UART2 - bool "Enable UART2" - default n - - config BSP_UART2_RX_USING_DMA - bool "Enable UART2 RX DMA" - depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA - default n - - config BSP_USING_UART3 - bool "Enable UART3" - default n - - config BSP_UART3_RX_USING_DMA - bool "Enable UART3 RX DMA" - depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA - default n - endif - - config BSP_USING_ON_CHIP_FLASH - bool "Enable on-chip FLASH" - default n - -menuconfig BSP_USING_SPI - bool "Enable SPI BUS" - default n - select RT_USING_SPI - if BSP_USING_SPI - config BSP_USING_SPI1 - bool "Enable SPI1 BUS" - default n - - config BSP_SPI1_TX_USING_DMA - bool "Enable SPI1 TX DMA" - depends on BSP_USING_SPI1 - default n - - config BSP_SPI1_RX_USING_DMA - bool "Enable SPI1 RX DMA" - depends on BSP_USING_SPI1 - select BSP_SPI1_TX_USING_DMA - default n - - config BSP_USING_SPI2 - bool "Enable SPI2 BUS" - default n - - config BSP_SPI2_TX_USING_DMA - bool "Enable SPI2 TX DMA" - depends on BSP_USING_SPI2 - default n - - config BSP_SPI2_RX_USING_DMA - bool "Enable SPI2 RX DMA" - depends on BSP_USING_SPI2 - select BSP_SPI2_TX_USING_DMA - default n - - config BSP_USING_SPI5 - bool "Enable SPI5 BUS" - default n - - config BSP_SPI5_TX_USING_DMA - bool "Enable SPI5 TX DMA" - depends on BSP_USING_SPI5 - default n - - config BSP_SPI5_RX_USING_DMA - bool "Enable SPI5 RX DMA" - depends on BSP_USING_SPI5 - select BSP_SPI5_TX_USING_DMA - default n - endif - - config BSP_USING_QSPI - bool "Enable QSPI BUS" - select RT_USING_QSPI - select RT_USING_SPI - default n - - menuconfig BSP_USING_ADC - bool "Enable ADC" - default n - select RT_USING_ADC - if BSP_USING_ADC - config BSP_USING_ADC1 - bool "Enable ADC1" - default n - endif - - menuconfig BSP_USING_I2C1 - bool "Enable I2C1 BUS (software simulation)" - default n - select RT_USING_I2C - select RT_USING_I2C_BITOPS - select RT_USING_PIN - if BSP_USING_I2C1 - comment "Notice: PB6 --> 22; PB7 --> 23" - config BSP_I2C1_SCL_PIN - int "I2C1 scl pin number" - range 1 176 - default 22 - config BSP_I2C1_SDA_PIN - int "I2C1 sda pin number" - range 1 176 - default 23 - endif - - menuconfig BSP_USING_ONCHIP_RTC - bool "Enable RTC" - select RT_USING_RTC - default n - if BSP_USING_ONCHIP_RTC - choice - prompt "Select clock source" - default BSP_RTC_USING_LSE - - config BSP_RTC_USING_LSE - bool "RTC USING LSE" - - config BSP_RTC_USING_LSI - bool "RTC USING LSI" - endchoice - endif - - config BSP_USING_WDT - bool "Enable Watchdog Timer" - select RT_USING_WDT - default n - - config BSP_USING_SDIO - bool "Enable SDIO" - select RT_USING_SDIO - select RT_USING_DFS - default n - - config BSP_USING_FMC - bool - default n - - config BSP_USING_LTDC - bool - default n - - source "../libraries/HAL_Drivers/Kconfig" - -endmenu - -menu "Board extended module Drivers" - -endmenu - -endmenu diff --git a/bsp/stm32/stm32f767-fire-challenger/board/SConscript b/bsp/stm32/stm32f767-fire-challenger/board/SConscript deleted file mode 100644 index 6dd2b9f997..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/SConscript +++ /dev/null @@ -1,40 +0,0 @@ -import os -import rtconfig -from building import * - -Import('SDK_LIB') - -cwd = GetCurrentDir() - -# add general drivers -src = Split(''' -board.c -CubeMX_Config/Src/stm32f7xx_hal_msp.c -''') - -if GetDepend(['BSP_USING_ETH']): - src += Glob('ports/phy_reset.c') - -if GetDepend(['BSP_USING_QSPI_FLASH']): - src += Glob('ports/drv_qspi_flash.c') - -if GetDepend(['BSP_USING_SDCARD']): - src += Glob('ports/sdcard_port.c') - -path = [cwd] -path += [cwd + '/CubeMX_Config/Inc'] -path += [cwd + '/ports'] - -startup_path_prefix = SDK_LIB - -if rtconfig.CROSS_TOOL == 'gcc': - src += [startup_path_prefix + '/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f767xx.s'] -elif rtconfig.CROSS_TOOL == 'keil': - src += [startup_path_prefix + '/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/arm/startup_stm32f767xx.s'] -elif rtconfig.CROSS_TOOL == 'iar': - src += [startup_path_prefix + '/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/startup_stm32f767xx.s'] - -CPPDEFINES = ['STM32F767xx'] -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) - -Return('group') \ No newline at end of file diff --git a/bsp/stm32/stm32f767-fire-challenger/board/board.c b/bsp/stm32/stm32f767-fire-challenger/board/board.c deleted file mode 100644 index de621405e1..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/board.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-11-06 SummerGift first version - */ - -#include "board.h" - -void SystemClock_Config(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - - /**Configure the main internal regulator output voltage - */ - __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /**Initializes the CPU, AHB and APB busses clocks - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 25; - RCC_OscInitStruct.PLL.PLLN = 432; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 9; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - Error_Handler(); - } - /**Activate the Over-Drive mode - */ - if (HAL_PWREx_EnableOverDrive() != HAL_OK) - { - Error_Handler(); - } - /**Initializes the CPU, AHB and APB busses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) - { - Error_Handler(); - } - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC|RCC_PERIPHCLK_USART1 - |RCC_PERIPHCLK_SDMMC1|RCC_PERIPHCLK_CLK48; - PeriphClkInitStruct.PLLSAI.PLLSAIN = 192; - PeriphClkInitStruct.PLLSAI.PLLSAIR = 3; - PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2; - PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV2; - PeriphClkInitStruct.PLLSAIDivQ = 1; - PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2; - PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; - PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; - PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_CLK48; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - { - Error_Handler(); - } -} diff --git a/bsp/stm32/stm32f767-fire-challenger/board/board.h b/bsp/stm32/stm32f767-fire-challenger/board/board.h deleted file mode 100644 index e9a1277849..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/board.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-11-5 SummerGift first version - */ - -#ifndef __BOARD_H__ -#define __BOARD_H__ - -#include -#include -#include "drv_common.h" -#include "drv_gpio.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define STM32_SRAM_SIZE (512) -#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) - -#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000) -#define STM32_FLASH_SIZE (1024 * 1024) -#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE)) - -#if defined(__CC_ARM) || defined(__CLANG_ARM) -extern int Image$$RW_IRAM1$$ZI$$Limit; -#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) -#elif __ICCARM__ -#pragma section="CSTACK" -#define HEAP_BEGIN (__segment_end("CSTACK")) -#else -extern int __bss_end; -#define HEAP_BEGIN (&__bss_end) -#endif - -#define HEAP_END STM32_SRAM_END - -void SystemClock_Config(void); - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/bsp/stm32/stm32f767-fire-challenger/board/linker_scripts/link.icf b/bsp/stm32/stm32f767-fire-challenger/board/linker_scripts/link.icf deleted file mode 100644 index 9dc3dbbcd4..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/linker_scripts/link.icf +++ /dev/null @@ -1,28 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2007FFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x0400; -define symbol __ICFEDIT_size_heap__ = 0x0000; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, last block CSTACK}; \ No newline at end of file diff --git a/bsp/stm32/stm32f767-fire-challenger/board/linker_scripts/link.lds b/bsp/stm32/stm32f767-fire-challenger/board/linker_scripts/link.lds deleted file mode 100644 index 99ad02213b..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/linker_scripts/link.lds +++ /dev/null @@ -1,157 +0,0 @@ -/* - * linker script for STM32F4xx with GNU ld - * bernard.xiong 2009-10-14 - */ - -/* Program Entry, set to mark it as "used" and avoid gc */ -MEMORY -{ - ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */ - RAM (rw) : ORIGIN = 0x20000000, LENGTH = 512k /* 128K sram */ -} -ENTRY(Reset_Handler) -_system_stack_size = 0x200; - -SECTIONS -{ - .text : - { - . = ALIGN(4); - _stext = .; - KEEP(*(.isr_vector)) /* Startup code */ - - . = ALIGN(4); - *(.text) /* remaining code */ - *(.text.*) /* remaining code */ - *(.rodata) /* read-only data (constants) */ - *(.rodata*) - *(.glue_7) - *(.glue_7t) - *(.gnu.linkonce.t*) - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - - /* section information for initial. */ - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - - . = ALIGN(4); - - PROVIDE(__ctors_start__ = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - PROVIDE(__ctors_end__ = .); - - . = ALIGN(4); - - _etext = .; - } > ROM = 0 - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - - /* This is used by the startup in order to initialize the .data secion */ - _sidata = .; - } > ROM - __exidx_end = .; - - /* .data section which is used for initialized data */ - - .data : AT (_sidata) - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _sdata = . ; - - *(.data) - *(.data.*) - *(.gnu.linkonce.d*) - - PROVIDE(__dtors_start__ = .); - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - PROVIDE(__dtors_end__ = .); - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _edata = . ; - } >RAM - - .stack : - { - . = ALIGN(4); - _sstack = .; - . = . + _system_stack_size; - . = ALIGN(4); - _estack = .; - } >RAM - - __bss_start = .; - .bss : - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; - - *(.bss) - *(.bss.*) - *(COMMON) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _ebss = . ; - - *(.bss.init) - } > RAM - __bss_end = .; - - _end = .; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/bsp/stm32/stm32f767-fire-challenger/board/linker_scripts/link.sct b/bsp/stm32/stm32f767-fire-challenger/board/linker_scripts/link.sct deleted file mode 100644 index e0bd37ed5e..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/linker_scripts/link.sct +++ /dev/null @@ -1,15 +0,0 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x08000000 0x00100000 { ; load region size_region - ER_IROM1 0x08000000 0x00100000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20020000 0x00060000 { ; RW data - .ANY (+RW +ZI) - } -} - diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32f767-fire-challenger/board/ports/drv_qspi_flash.c deleted file mode 100644 index a3091fd2eb..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/ports/drv_qspi_flash.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-11-27 zylx first version - */ - -#include -#include -#include -#include -#include - -#ifdef BSP_USING_QSPI_FLASH - -#include "spi_flash.h" -#include "spi_flash_sfud.h" - -char w25qxx_read_status_register2(struct rt_qspi_device *device) -{ - /* 0x35 read status register2 */ - char instruction = 0x35, status; - - rt_qspi_send_then_recv(device, &instruction, 1, &status, 1); - - return status; -} - -void w25qxx_write_enable(struct rt_qspi_device *device) -{ - /* 0x06 write enable */ - char instruction = 0x06; - - rt_qspi_send(device, &instruction, 1); -} - -void w25qxx_enter_qspi_mode(struct rt_qspi_device *device) -{ - char status = 0; - /* 0x38 enter qspi mode */ - char instruction = 0x38; - char write_status2_buf[2] = {0}; - - /* 0x31 write status register2 */ - write_status2_buf[0] = 0x31; - - status = w25qxx_read_status_register2(device); - if (!(status & 0x02)) - { - status |= 1 << 1; - w25qxx_write_enable(device); - write_status2_buf[1] = status; - rt_qspi_send(device, &write_status2_buf, 2); - rt_qspi_send(device, &instruction, 1); - rt_kprintf("flash already enter qspi mode\n"); - rt_thread_mdelay(10); - } -} - -static int rt_hw_qspi_flash_with_sfud_init(void) -{ - stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL); - - /* init w25q128 */ - if (RT_NULL == rt_sfud_flash_probe("W25Q128", "qspi10")) - { - return -RT_ERROR; - } - - return RT_EOK; -} -INIT_COMPONENT_EXPORT(rt_hw_qspi_flash_with_sfud_init); - -#endif/* BSP_USING_QSPI_FLASH */ diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/fal_cfg.h b/bsp/stm32/stm32f767-fire-challenger/board/ports/fal_cfg.h deleted file mode 100644 index 5ddddaa2cd..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/ports/fal_cfg.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-12-5 SummerGift first version - */ - -#ifndef _FAL_CFG_H_ -#define _FAL_CFG_H_ - -#include -#include - -#define FLASH_SIZE_GRANULARITY_32K (4 * 32 * 1024) -#define FLASH_SIZE_GRANULARITY_128K (128 * 1024) -#define FLASH_SIZE_GRANULARITY_256K (3 * 256 * 1024) - -#define STM32_FLASH_START_ADRESS_32K STM32_FLASH_START_ADRESS -#define STM32_FLASH_START_ADRESS_128K (STM32_FLASH_START_ADRESS_32K + FLASH_SIZE_GRANULARITY_32K) -#define STM32_FLASH_START_ADRESS_256K (STM32_FLASH_START_ADRESS_128K + FLASH_SIZE_GRANULARITY_128K) - -extern const struct fal_flash_dev stm32_onchip_flash_32k; -extern const struct fal_flash_dev stm32_onchip_flash_128k; -extern const struct fal_flash_dev stm32_onchip_flash_256k; - -/* flash device table */ -#define FAL_FLASH_DEV_TABLE \ -{ \ - &stm32_onchip_flash_32k, \ - &stm32_onchip_flash_128k, \ - &stm32_onchip_flash_256k, \ -} -/* ====================== Partition Configuration ========================== */ -#ifdef FAL_PART_HAS_TABLE_CFG - -/* partition table */ -#define FAL_PART_TABLE \ -{ \ - {FAL_PART_MAGIC_WROD, "bootloader", "onchip_flash_32k", 0 , FLASH_SIZE_GRANULARITY_32K , 0}, \ - {FAL_PART_MAGIC_WROD, "param", "onchip_flash_128k", 0 , FLASH_SIZE_GRANULARITY_128K, 0}, \ - {FAL_PART_MAGIC_WROD, "app", "onchip_flash_256k", 0 , FLASH_SIZE_GRANULARITY_256K, 0}, \ -} - -#endif /* FAL_PART_HAS_TABLE_CFG */ -#endif /* _FAL_CFG_H_ */ diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/lcd_port.h b/bsp/stm32/stm32f767-fire-challenger/board/ports/lcd_port.h deleted file mode 100644 index 8d297ec915..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/ports/lcd_port.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-01-08 zylx first version - */ - -#ifndef __LCD_PORT_H__ -#define __LCD_PORT_H__ - -/* fire 5 inch screen, 800 * 480 */ -#define LCD_WIDTH 800 -#define LCD_HEIGHT 480 -#define LCD_BITS_PER_PIXEL 16 -#define LCD_BUF_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_BITS_PER_PIXEL / 8) -#define LCD_PIXEL_FORMAT RTGRAPHIC_PIXEL_FORMAT_RGB565 - -#define LCD_HSYNC_WIDTH 2 -#define LCD_VSYNC_HEIGHT 2 -#define LCD_HBP 46 -#define LCD_VBP 23 -#define LCD_HFP 22 -#define LCD_VFP 22 - -#define LCD_BACKLIGHT_USING_GPIO -#define LCD_BL_GPIO_NUM GET_PIN(D, 7) -#define LCD_DISP_GPIO_NUM GET_PIN(D, 4) -/* fire 5 inch screen, 800 * 480 */ - -#endif /* __LCD_PORT_H__ */ diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/phy_reset.c b/bsp/stm32/stm32f767-fire-challenger/board/ports/phy_reset.c deleted file mode 100644 index 8eaf6dcd5a..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/ports/phy_reset.c +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-11-23 flybreak first version - */ - -#include - -void phy_reset(void) -{ - /* The phy reset pin of this BSP circuit is connected to the chip reset pin, so no additional reset is required. */ -} diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/sdcard_port.c b/bsp/stm32/stm32f767-fire-challenger/board/ports/sdcard_port.c deleted file mode 100644 index f1a7b8c27f..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/ports/sdcard_port.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-12-13 balanceTWK add sdcard port file - */ - -#include - -#ifdef BSP_USING_SDCARD - -#include -#include -#include -#include "drv_gpio.h" - -#define DBG_TAG "app.card" -#define DBG_LVL DBG_INFO -#include - -#define WIFI_RESET_PIN GET_PIN(G, 9) - -int ewm1062_disable(void) -{ - rt_pin_mode(WIFI_RESET_PIN, PIN_MODE_OUTPUT); - rt_pin_write(WIFI_RESET_PIN,PIN_LOW); - return RT_EOK; -} -INIT_BOARD_EXPORT(ewm1062_disable); - -void sd_mount(void *parameter) -{ - while (1) - { - rt_thread_mdelay(500); - if(rt_device_find("sd0") != RT_NULL) - { - if (dfs_mount("sd0", "/", "elm", 0, 0) == RT_EOK) - { - LOG_I("sd card mount to '/'"); - break; - } - else - { - LOG_W("sd card mount to '/' failed!"); - } - } - } -} - -int stm32_sdcard_mount(void) -{ - rt_thread_t tid; - - tid = rt_thread_create("sd_mount", sd_mount, RT_NULL, - 1024, RT_THREAD_PRIORITY_MAX - 2, 20); - if (tid != RT_NULL) - { - rt_thread_startup(tid); - } - else - { - LOG_E("create sd_mount thread err!"); - } - return RT_EOK; -} -INIT_ENV_EXPORT(stm32_sdcard_mount); - -#endif /* BSP_USING_SDCARD */ - diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/sdram_port.h b/bsp/stm32/stm32f767-fire-challenger/board/ports/sdram_port.h deleted file mode 100644 index 7f9485aa4a..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/board/ports/sdram_port.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-12-04 zylx The first version for STM32F4xx - */ - -#ifndef __SDRAM_PORT_H__ -#define __SDRAM_PORT_H__ - -/* parameters for sdram peripheral */ -/* Bank1 or Bank2 */ -#define SDRAM_TARGET_BANK 2 -/* stm32f7 Bank1:0XC0000000 Bank2:0XD0000000 */ -#define SDRAM_BANK_ADDR ((uint32_t)0XD0000000) -/* data width: 8, 16, 32 */ -#define SDRAM_DATA_WIDTH 16 -/* column bit numbers: 8, 9, 10, 11 */ -#define SDRAM_COLUMN_BITS 8 -/* row bit numbers: 11, 12, 13 */ -#define SDRAM_ROW_BITS 12 -/* cas latency clock number: 1, 2, 3 */ -#define SDRAM_CAS_LATENCY 2 -/* read pipe delay: 0, 1, 2 */ -#define SDRAM_RPIPE_DELAY 0 -/* clock divid: 2, 3 */ -#define SDCLOCK_PERIOD 2 -/* refresh rate counter */ -#define SDRAM_REFRESH_COUNT ((uint32_t)0x056A) -#define SDRAM_SIZE ((uint32_t)0x800000) - -/* Timing configuration for IS42S16400J */ -/* 108 MHz of SD clock frequency (216MHz/2) */ -/* TMRD: 2 Clock cycles */ -#define LOADTOACTIVEDELAY 2 -/* TXSR: 8x9.25ns */ -#define EXITSELFREFRESHDELAY 8 -/* TRAS: 5x9.25ns */ -#define SELFREFRESHTIME 5 -/* TRC: 7x9.25ns */ -#define ROWCYCLEDELAY 7 -/* TWR: 2 Clock cycles */ -#define WRITERECOVERYTIME 2 -/* TRP: 2x9.25ns */ -#define RPDELAY 2 -/* TRCD: 2x9.25ns */ -#define RCDDELAY 3 - -/* memory mode register */ -#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) -#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) -#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) -#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) -#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) -#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) -#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) - -#endif diff --git a/bsp/stm32/stm32f767-fire-challenger/figures/board.jpg b/bsp/stm32/stm32f767-fire-challenger/figures/board.jpg deleted file mode 100644 index 8dbe504ba5..0000000000 Binary files a/bsp/stm32/stm32f767-fire-challenger/figures/board.jpg and /dev/null differ diff --git a/bsp/stm32/stm32f767-fire-challenger/project.ewd b/bsp/stm32/stm32f767-fire-challenger/project.ewd deleted file mode 100644 index e94c83ed06..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/project.ewd +++ /dev/null @@ -1,2834 +0,0 @@ - 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- - diff --git a/bsp/stm32/stm32f767-fire-challenger/project.eww b/bsp/stm32/stm32f767-fire-challenger/project.eww deleted file mode 100644 index c2cb02eb1e..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/project.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\project.ewp - - - - - diff --git a/bsp/stm32/stm32f767-fire-challenger/project.uvopt b/bsp/stm32/stm32f767-fire-challenger/project.uvopt deleted file mode 100644 index 0e93bee143..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/project.uvopt +++ /dev/null @@ -1,184 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - - - - 0 - 0 - - - - rt-thread - 0x4 - ARM-ADS - - 25000000 - - 1 - 1 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\keil\List\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 0 - 0 - 1 - - 255 - - - 0 - Datasheet - DATASHTS\ST\STM32F4xx\DM00053488.pdf - - - 1 - Reference Manual - DATASHTS\ST\STM32F4xx\DM00031020.pdf - - - 2 - Technical Reference Manual - datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF - - - 3 - Generic User Guide - datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 0 - 1 - 1 - 0 - 0 - 0 - 6 - - - - - - - - - - - Segger\JL2CM3.dll - - - - 0 - JL2CM3 - -U20090928 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 - - - 0 - UL2CM3 - UL2CM3(-O207 -S0 -C0 -FO7 -FN1 -FC800 -FD20000000 -FF0STM32F4xx_1024 -FL0100000 -FS08000000 - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - diff --git a/bsp/stm32/stm32f767-fire-challenger/project.uvprojx b/bsp/stm32/stm32f767-fire-challenger/project.uvprojx deleted file mode 100644 index c77cfd7c72..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/project.uvprojx +++ /dev/null @@ -1,828 +0,0 @@ - - - 2.1 -
### uVision Project, (C) Keil Software
- - - rt-thread - 0x4 - ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC - 0 - - - STM32F767IGTx - STMicroelectronics - Keil.STM32F7xx_DFP.2.11.0 - http://www.keil.com/pack - IRAM(0x20020000,0x60000) IRAM2(0x20000000,0x20000) IROM(0x08000000,0x100000) IROM2(0x00200000,0x100000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20020000 -FC1000 -FN2 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FF1STM32F7x_1024dual -FS18000000 -FL1100000 -FP0($$Device:STM32F767IGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FP1($$Device:STM32F767IGTx$CMSIS\Flash\STM32F7x_1024dual.FLM)) - 0 - $$Device:STM32F767IGTx$Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h - - - - - - - - - - $$Device:STM32F767IGTx$CMSIS\SVD\STM32F7x7_v1r2.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\build\keil\Obj\ - rt-thread - 1 - 0 - 0 - 1 - 0 - .\build\keil\List\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 0 - fromelf --bin !L --output rtthread.bin - - 0 - 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..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_cryp_ex.c - - - - - stm32f7xx_hal_exti.c - 1 - ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_exti.c - - - - - stm32f7xx_hal_dma.c - 1 - ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma.c - - - - - stm32f7xx_hal_dma_ex.c - 1 - ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma_ex.c - - - - - stm32f7xx_hal_pwr.c - 1 - ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr.c - - - - - stm32f7xx_hal_pwr_ex.c - 1 - ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr_ex.c - - - - - stm32f7xx_hal_rcc.c - 1 - ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc.c - - - - - stm32f7xx_hal_rcc_ex.c - 1 - ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc_ex.c - - - - - stm32f7xx_hal_rng.c - 1 - ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rng.c - - - - - stm32f7xx_hal_sram.c - 1 - ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_sram.c - - - - - stm32f7xx_hal_gpio.c - 1 - ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_gpio.c - - - - - stm32f7xx_hal_uart.c - 1 - ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart.c - - - - - stm32f7xx_hal_uart_ex.c - 1 - ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart_ex.c - - - - - stm32f7xx_hal_usart.c - 1 - ..\libraries\STM32F7xx_HAL\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_usart.c - - - - - - - - - - - - diff --git a/bsp/stm32/stm32f767-fire-challenger/rtconfig.h b/bsp/stm32/stm32f767-fire-challenger/rtconfig.h deleted file mode 100644 index 5cdccf1960..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/rtconfig.h +++ /dev/null @@ -1,180 +0,0 @@ -#ifndef RT_CONFIG_H__ -#define RT_CONFIG_H__ - -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - -/* RT-Thread Kernel */ - -#define RT_NAME_MAX 8 -#define RT_ALIGN_SIZE 4 -#define RT_THREAD_PRIORITY_32 -#define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK -#define RT_USING_HOOK -#define RT_USING_IDLE_HOOK -#define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 1024 -#define RT_DEBUG -#define RT_DEBUG_COLOR - -/* Inter-Thread communication */ - -#define RT_USING_SEMAPHORE -#define RT_USING_MUTEX -#define RT_USING_EVENT -#define RT_USING_MAILBOX -#define RT_USING_MESSAGEQUEUE - -/* Memory Management */ - -#define RT_USING_MEMPOOL -#define RT_USING_MEMHEAP -#define RT_USING_MEMHEAP_AS_HEAP -#define RT_USING_HEAP - -/* Kernel Device Object */ - -#define RT_USING_DEVICE -#define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40002 -#define ARCH_ARM -#define RT_USING_CPU_FFS -#define ARCH_ARM_CORTEX_M -#define ARCH_ARM_CORTEX_M7 - -/* RT-Thread Components */ - -#define RT_USING_COMPONENTS_INIT -#define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 2048 -#define RT_MAIN_THREAD_PRIORITY 10 - -/* C++ features */ - - -/* Command shell */ - -#define RT_USING_FINSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_USING_HISTORY -#define FINSH_HISTORY_LINES 5 -#define FINSH_USING_SYMTAB -#define FINSH_USING_DESCRIPTION -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 -#define FINSH_CMD_SIZE 80 -#define FINSH_USING_MSH -#define FINSH_USING_MSH_DEFAULT -#define FINSH_USING_MSH_ONLY -#define FINSH_ARG_MAX 10 - -/* Device virtual file system */ - - -/* Device Drivers */ - -#define RT_USING_DEVICE_IPC -#define RT_PIPE_BUFSZ 512 -#define RT_USING_SERIAL -#define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_PIN - -/* Using Hardware Crypto drivers */ - - -/* Using WiFi */ - - -/* Using USB */ - - -/* POSIX layer and C standard library */ - - -/* Network */ - -/* Socket abstraction layer */ - - -/* Network interface device */ - - -/* light weight TCP/IP stack */ - - -/* Modbus master and slave stack */ - - -/* AT commands */ - - -/* VBUS(Virtual Software BUS) */ - - -/* Utilities */ - - -/* RT-Thread online packages */ - -/* IoT - internet of things */ - - -/* Wi-Fi */ - -/* Marvell WiFi */ - - -/* Wiced WiFi */ - - -/* IoT Cloud */ - - -/* security packages */ - - -/* language packages */ - - -/* multimedia packages */ - - -/* tools packages */ - - -/* system packages */ - - -/* peripheral libraries and drivers */ - - -/* miscellaneous packages */ - - -/* samples: kernel and components samples */ - -#define SOC_FAMILY_STM32 -#define SOC_SERIES_STM32F7 - -/* Hardware Drivers Config */ - -#define SOC_STM32F767IG - -/* Onboard Peripheral Drivers */ - -#define BSP_USING_USB_TO_USART - -/* On-chip Peripheral Drivers */ - -#define BSP_USING_GPIO -#define BSP_USING_UART -#define BSP_USING_UART1 - -/* Board extended module Drivers */ - - -#endif diff --git a/bsp/stm32/stm32f767-fire-challenger/rtconfig.py b/bsp/stm32/stm32f767-fire-challenger/rtconfig.py deleted file mode 100644 index ef6f4ff7c2..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/rtconfig.py +++ /dev/null @@ -1,150 +0,0 @@ -import os - -# toolchains options -ARCH='arm' -CPU='cortex-m7' -CROSS_TOOL='gcc' - -# bsp lib config -BSP_LIBRARY_TYPE = None - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'C:\Users\XXYYZZ' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = r'C:/Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iar' - EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # toolchains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - CXX = PREFIX + 'g++' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m7 -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -Dgcc' - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2 -g' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - CXX = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M7.fp.sp' - CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' - LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' - - CFLAGS += ' -D__MICROLIB ' - AFLAGS += ' --pd "__MICROLIB SETA 1" ' - LFLAGS += ' --library_type=microlib ' - EXEC_PATH += '/ARM/ARMCC/bin/' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - CFLAGS += ' -std=c99' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iar': - # toolchains - CC = 'iccarm' - CXX = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = '-Dewarm' - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M7' - CFLAGS += ' -e' - CFLAGS += ' --fpu=VFPv5_sp' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' --silent' - - AFLAGS = DEVICE - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M7' - AFLAGS += ' --fpu VFPv5_sp' - AFLAGS += ' -S' - - if BUILD == 'debug': - CFLAGS += ' --debug' - CFLAGS += ' -On' - else: - CFLAGS += ' -Oh' - - LFLAGS = ' --config "board/linker_scripts/link.icf"' - LFLAGS += ' --entry __iar_program_start' - - CXXFLAGS = CFLAGS - - EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' - -def dist_handle(BSP_ROOT, dist_dir): - import sys - cwd_path = os.getcwd() - sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) - from sdk_dist import dist_do_building - dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/stm32/stm32f767-fire-challenger/template.ewp b/bsp/stm32/stm32f767-fire-challenger/template.ewp deleted file mode 100644 index 21c66ca0d0..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/template.ewp +++ /dev/null @@ -1,2031 +0,0 @@ - - - 3 - - rt-thread - - ARM - - 1 - - General - 3 - - 29 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 34 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 10 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 20 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 29 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 34 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 10 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 20 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - diff --git a/bsp/stm32/stm32f767-fire-challenger/template.eww b/bsp/stm32/stm32f767-fire-challenger/template.eww deleted file mode 100644 index bd036bb4c9..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/template.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\template.ewp - - - - - diff --git a/bsp/stm32/stm32f767-fire-challenger/template.uvoptx b/bsp/stm32/stm32f767-fire-challenger/template.uvoptx deleted file mode 100644 index a7bce0b7d6..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/template.uvoptx +++ /dev/null @@ -1,192 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rt-thread - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\keil\List\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 18 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 3 - - - - - - - - - - - Segger\JL2CM3.dll - - - - 0 - JL2CM3 - -U59400616 -O14 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight JTAG-DP") -D00(5BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06451041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20020000 -FC1000 -FN1 -FF0STM32F7x_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F767IGTx$CMSIS\Flash\STM32F7x_1024.FLM) - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN2 -FC1000 -FD20020000 -FF0STM32F7x_1024 -FF1STM32F7x_1024dual -FL0100000 -FL1100000 -FS08000000 -FS18000000 -FP0($$Device:STM32F767IGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FP1($$Device:STM32F767IGTx$CMSIS\Flash\STM32F7x_1024dual.FLM) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - 1 - 0 - 0 - 2 - 10000000 - - - - - - Source Group 1 - 0 - 0 - 0 - 0 - - - diff --git a/bsp/stm32/stm32f767-fire-challenger/template.uvprojx b/bsp/stm32/stm32f767-fire-challenger/template.uvprojx deleted file mode 100644 index 559eb8a0bd..0000000000 --- a/bsp/stm32/stm32f767-fire-challenger/template.uvprojx +++ /dev/null @@ -1,395 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - rt-thread - 0x4 - ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC - 0 - - - STM32F767IGTx - STMicroelectronics - Keil.STM32F7xx_DFP.2.11.0 - http://www.keil.com/pack - IRAM(0x20020000,0x60000) IRAM2(0x20000000,0x20000) IROM(0x08000000,0x100000) IROM2(0x00200000,0x100000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20020000 -FC1000 -FN2 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FF1STM32F7x_1024dual -FS18000000 -FL1100000 -FP0($$Device:STM32F767IGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FP1($$Device:STM32F767IGTx$CMSIS\Flash\STM32F7x_1024dual.FLM)) - 0 - $$Device:STM32F767IGTx$Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h - - - - - - - - - - $$Device:STM32F767IGTx$CMSIS\SVD\STM32F7x7_v1r2.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\build\keil\Obj\ - rt-thread - 1 - 0 - 0 - 1 - 0 - .\build\keil\List\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 0 - fromelf --bin !L --output rtthread.bin - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -REMAP -MPU - DCM.DLL - -pCM7 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM7 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M7" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 3 - 0 - 1 - 1 - 8 - 0 - 0 - 0 - 0 - 4 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 1 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20020000 - 0x60000 - - - 1 - 0x8000000 - 0x100000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x8000000 - 0x100000 - - - 1 - 0x200000 - 0x100000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20020000 - 0x60000 - - - 0 - 0x20000000 - 0x20000 - - - - - - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 0 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - .\board\linker_scripts\link.sct - - - - - - - - - - - Source Group 1 - - - - - - - - - - - - -- cgit v1.3.1