From 892ef3dc5bcb6e504629513b57ec4e1023a0d9d1 Mon Sep 17 00:00:00 2001 From: Yaochenger <75192526+Yaochenger@users.noreply.github.com> Date: Thu, 2 Mar 2023 10:34:35 +0800 Subject: [libcpu/risc-v]将cv32e40p文件夹中文件移至BSP (#7002) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/core-v-mcu/Libraries/core_v_hal_libraries/SConscript | 1 + .../bmsis/core-v-mcu/source/trap_gcc.S | 16 ++++++++++++++++ libcpu/risc-v/cv32e40p/SConscript | 14 -------------- libcpu/risc-v/cv32e40p/trap_gcc.S | 16 ---------------- 4 files changed, 17 insertions(+), 30 deletions(-) create mode 100644 bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/source/trap_gcc.S delete mode 100644 libcpu/risc-v/cv32e40p/SConscript delete mode 100644 libcpu/risc-v/cv32e40p/trap_gcc.S diff --git a/bsp/core-v-mcu/Libraries/core_v_hal_libraries/SConscript b/bsp/core-v-mcu/Libraries/core_v_hal_libraries/SConscript index ee0ab6bb49..98d5fe70f6 100644 --- a/bsp/core-v-mcu/Libraries/core_v_hal_libraries/SConscript +++ b/bsp/core-v-mcu/Libraries/core_v_hal_libraries/SConscript @@ -20,6 +20,7 @@ core_v_hal/source/hal_timer_irq.c bmsis/core-v-mcu/source/core-v-mcu.c bmsis/core-v-mcu/source/crt0.S bmsis/core-v-mcu/source/vectors.S +bmsis/core-v-mcu/source/trap_gcc.S core_v_udma_driver/source/udma_uart_driver.c core_v_udma_driver/source/udma_cam_driver.c core_v_udma_driver/source/udma_i2cm_driver.c diff --git a/bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/source/trap_gcc.S b/bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/source/trap_gcc.S new file mode 100644 index 0000000000..be10e64d3b --- /dev/null +++ b/bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/source/trap_gcc.S @@ -0,0 +1,16 @@ +#include "cpuport.h" + + .globl rt_hw_do_after_save_above + .type rt_hw_do_after_save_above,@function +rt_hw_do_after_save_above: + addi sp, sp, -4 + STORE ra, 0 * REGBYTES(sp) + + csrr a0, mcause + csrr a1, mepc + mv a2, sp + call rt_rv32_system_irq_handler + + LOAD ra, 0 * REGBYTES(sp) + addi sp, sp, 4 + ret diff --git a/libcpu/risc-v/cv32e40p/SConscript b/libcpu/risc-v/cv32e40p/SConscript deleted file mode 100644 index 20f325b692..0000000000 --- a/libcpu/risc-v/cv32e40p/SConscript +++ /dev/null @@ -1,14 +0,0 @@ -# RT-Thread building script for component - -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') -CPPPATH = [cwd] -ASFLAGS = '' - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS) - -Return('group') diff --git a/libcpu/risc-v/cv32e40p/trap_gcc.S b/libcpu/risc-v/cv32e40p/trap_gcc.S deleted file mode 100644 index be10e64d3b..0000000000 --- a/libcpu/risc-v/cv32e40p/trap_gcc.S +++ /dev/null @@ -1,16 +0,0 @@ -#include "cpuport.h" - - .globl rt_hw_do_after_save_above - .type rt_hw_do_after_save_above,@function -rt_hw_do_after_save_above: - addi sp, sp, -4 - STORE ra, 0 * REGBYTES(sp) - - csrr a0, mcause - csrr a1, mepc - mv a2, sp - call rt_rv32_system_irq_handler - - LOAD ra, 0 * REGBYTES(sp) - addi sp, sp, 4 - ret -- cgit v1.3.1